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Add the MSAA samples array or make sure its contents are initialized.
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(cherry picked from commit f7d80aa00611917bc8ce637136d982b151b8f44f)
This also involved adding the new MSAA fields to driCreateConfigs().
Also, re-add prog_instructions->Sampler field for i965 driver. Will
have to revisit that.
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Merge commit 'origin/gallium-0.2' into gallium-master-merge
Conflicts:
Makefile
docs/relnotes-7.4.html
docs/relnotes.html
src/mesa/drivers/dri/i965/brw_wm.h
src/mesa/main/imports.c
src/mesa/main/mtypes.h
src/mesa/main/texcompress.c
src/mesa/main/texenvprogram.c
src/mesa/main/version.h
src/mesa/vbo/vbo_exec_api.c
src/mesa/vbo/vbo_save_draw.c
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this path isn't enabled by default in any case.
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The MI opcodes have different variable length masks, so use an operand
specific mask to decode the length.
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A couple of minor typos that proclaimed an error in the wrong command, and
failed to offset the mask.
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By selecting a 4444 texture format due to a bad test, we hit the
intel_update_wrapper error path, and despite the appearance of error handling
in it and its callers, the desired behavior (software fallback) doesn't occur.
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Too much commit -a while debugging.
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This lets swrast produce an fbconfig suitable for the root visual now that
the server's not allowing mismatched fbconfigs.
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Some apps won't run w/ indirect rendering contexts.
Also, consolidate some context-init code in new init_glx_context() function.
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No real-world impact on performance seen. Even glxgears seems to be, if
anything, happier.
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This still leaves us with a broken depth 32 visual, but now it's the server's
visual setup that's at fault.
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In a normal build system this is generated by configure.
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Rendering and textures are limited to 8kx8k, but mesa limits things to
4kx4k, and magic guard band stuff may break on 8kx8k drawing. This is safe
though, and makes compiz work on bigger screens.
Signed-off-by: Keith Packard <keithp@keithp.com>
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This is a 10% win on the ever-important glxgears not-a-benchmark.
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This saves an inadvertent round-trip to the X Server on DrawBuffers, which was
hurting some metaops.
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We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x (z0,z24,z24s8)
on either class of chipsets. The only restriction is no mixing bpp when also
mixing tiling. This shouldn't be occurring currently.
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Anytime we're not rendering to the default/window FBO, need to invert
rendering, not just when rendering to a texture. Otherwise, if a FBO
consists of a mix of textures and renderbuffers the up/down orientation
was inconsistant.
Fixes shadowtex.c bad rendering.
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Previously, "in-place" swizzles such as:
MOV t, t.xxyx;
were handled incorrectly. Fixed by splitting the one loop into two loops so we
get all the refs before assigning them (to avoid potential clobbering).
(cherry picked from master/commit faa48915d27634a12f123eaa6e954ec79565e365)
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(cherry picked from master/commit f78c388b6c156cb155f089b00612f00919090a8e)
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(cherry picked from master/commit 72ee0e247d799c85612c72bbd2257648e11fa583)
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intel_meta_set_passthrough_transform(), intel_meta_restore_transform()
(cherry picked from master, commit 723648f2ee2a8e529063c9da84e9dff9c8c6be99)
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Move the remaining extension string enables to intel_extensions.c.
Make sure that GL_NV_texture_env_combine4 is not enabled on i830.
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Just to reinforce the understanding that an extended swizzle with 0 and 1
terms is possible there.
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If the texture swizzle is not XYZW (no-op) add an extra MOV instruction
after the TEX instruction to rearrange the components.
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Previously, "in-place" swizzles such as:
MOV t, t.xxyx;
were handled incorrectly. Fixed by splitting the one loop into two loops so we
get all the refs before assigning them (to avoid potential clobbering).
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