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path: root/src/mesa/drivers
AgeCommit message (Collapse)Author
2009-04-28r300: remove unused debugging in set tex buffer pathsDave Airlie
2009-04-28radeon: remove kernel mm, dri2 path takes care of itDave Airlie
2009-04-27r300: fix fragment program limitsMaciej Cencora
2009-04-27r300: fallback only if stencil test is enabledMaciej Cencora
2009-04-27r300: do front/back color selection in HW for software TCL pathMaciej Cencora
2009-04-27r300: fix valgrind warningsMaciej Cencora
2009-04-27r300: fix point size clamping when point is not attenuatedMaciej Cencora
2009-04-27i965: #include prog_print.h to silence warningBrian Paul
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052 (cherry picked from master, commit dc9705d12d162ba6d087eb762e315de9f97bc456)
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
2009-04-27r300: fix performance regressionMaciej Cencora
This performance regression on non TCL hw was introduced by ed4c6cbe017b4e8bacb7e012d4baaf77a20a2c33. This patch depends on "r300: always route 4 texcoord components to RS" and "r300: add point attenuation stage for TCL fallbacks".
2009-04-27r300: add point attenuation stage for TCL fallbacksMaciej Cencora
2009-04-27r300: always route 4 texcoord components to RSMaciej Cencora
Routing <4 components may lead to lock up. Thanks to Alex Deucher for suggestion.
2009-04-27r300: flush stdout to get consistent debugging infoMaciej Cencora
2009-04-27r300: add atom print function for kernel mm pathMaciej Cencora
2009-04-27r300: handle texcoords properlyMaciej Cencora
add 1D texture case and setup default Q value to 1.0
2009-04-27r300: remove unnecessary function callsMaciej Cencora
ae_create_context is called by vbo_CreateContext ae_invalidate_state is called by vbo_InvalidateState
2009-04-27r300: rename stateMaciej Cencora
According to r300_reg.h from radeon drm module 0x4f30 is ZB_ZMASK_OFFSET. Also cleanup as trailing whitespaces.
2009-04-27r300: remove unnecessary function callsMaciej Cencora
r300SetEarlyZState is called during r300UpdateShaderStates which is called for every rendering operation.
2009-04-24i965: rework GLSL/WM register allocationBrian Paul
Use a bitvector of used/free flags. If we run out of temps, examine the live intervals of the temp regs in the program and free those which are no longer alive. Also, enable the new WM const buffer code.
2009-04-27r300: always emit output insts after all KIL instsMaciej Cencora
2009-04-24intel: Fix more issues with the combined depth-stencil attachmentIan Romanick
2009-04-24intel: Initialize region ptr to prevent assertion in intel_region_referenceIan Romanick
2009-04-24intel / DRI2: When available, use DRI2GetBuffersWithFormatIan Romanick
This interface gives the driver two important features. First, it can allocate the (fake) front-buffer only when needed. Second, it can tell the buffer allocator the format of buffers being allocated. This enables support for back-buffer and depth-buffer with different bits per pixel. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kristian Høgsberg <krh@redhat.com>
2009-04-24r300: fix cliprect valuesJerome Glisse
2009-04-24i965: use drm_intel_gem_bo_map/unmap_gtt() when possible, otherwise ↵Brian Paul
dri_bo_subdata() This wraps up the unfinished business from commit a9a363f8298e9d534e60e3d2869f8677138a1e7e
2009-04-24r300: emit cliprect when in dri2 modeJerome Glisse
2009-04-24i965: fix point size issueRoland Scheidegger
need to clamp point size to user set min/max values, even for constant point size. Fixes glean pointAtten test.
2009-04-23i965: revert part of commit 4f4907d69f9020ce17aef21b6431d2dd65e01982Brian Paul
The drm_intel_gem_bo_map_gtt() call that replaced dri_bo_map() is producing errors like: intel_bufmgr_gem.c:689: Error preparing buffer map 39 (vp_const_buffer): Invalid argument . and returning NULL, causing a segfault in the memcpy(). Just reverting until we can get to the root issue...
2009-04-23i915: fix fix for anisotropic filteringRoland Scheidegger
forgot to commit the changes to actually support 4x aniso filtering...
2009-04-23i965: Support drawing to FBO cube faces other than positive X.Eric Anholt
Also fixes drawing to 3D texture depth levels.
2009-04-23intel: Take advantage of GL_READ_ONLY_ARB to map to GEM bo_map write flag.Eric Anholt
This is a CPU win in general, but in particular reduces the pain of Mesa's calculation of min/max indices in DrawElements (wtf?).
2009-04-22i965: disable debug printfBrian Paul
2009-04-22i965: enable VS constant buffersBrian Paul
In the VS constants can now be handled in two different ways: 1. If there's room in the GRF, put constants there. They're preloaded from the CURBE prior to VS execution. This is the historical approach. The problem is the GRF may not have room for all the shader's constants and temps and misc registers. Hence... 2. Use a separate constant buffer which is read from using a READ message. This allows a very large number of constants and frees up GRF regs for shader temporaries. This is the new approach. May be a little slower than 1. 1 vs. 2 is chosen according to how many constants and temps the shader needs.
2009-04-22i965: define BRW_MAX_GRFBrian Paul
2009-04-22i965: remove old code to init surface-related cache IDsBrian Paul
These types are only found in the new surface state cache now.
2009-04-22i965: comments, reformattingBrian Paul
2009-04-22i965: actually use the new, second surface state cacheBrian Paul
2009-04-22i965: checkpoint commit: use two state caches instead of oneBrian Paul
The new, second cache will only be used for surface-related items. Since we can create many surfaces the original, single cache could get filled quickly. When we cleared it, we had to regenerate shaders, etc. With two caches, we can avoid doing that.
2009-04-22i965: remove unused state atom entriesBrian Paul
2009-04-22intel: fix max anisotropy supportedRoland Scheidegger
i915 actually supports up to 4 (according to header file - not tested), i965 up to 16 (code already handled this but slightly broken), so don't use 2 for all chips, even though angular dependency is very high.
2009-04-22i965: the brw_constant_buffer state atom is no longer dynamicBrian Paul
No more dynamic atoms so we can simplify the state validation code a little.
2009-04-22i965: add _NEW_PROGRAM_CONSTANTS to mesa_bits[] listBrian Paul
2009-04-22i915: check the new _NEW_PROGRAM_CONSTANT flagBrian Paul
2009-04-22i965: use _NEW_PROGRAM_CONSTANTS and always create new const buffersBrian Paul
When program constants change we create a new VS constant buffer instead of re-using the old one. This allows us to have several const buffers in flight with vertex rendering.
2009-04-22i965: updates to some debug codeBrian Paul
2009-04-22i965: use new _NEW_PROGRAM_CONSTANTS flag instead of dynamic flagsBrian Paul
2009-04-22r200/r300/r500: add _NEW_PROGRAM_CONSTANTS flagBrian Paul
Make sure we detect constant buffer changes indicated by the new flag. Should be able to remove _NEW_PROGRAM (and _NEW_MODELVIEW, _NEW_LIGHT, etc) from several places (someday.
2009-04-22Merge remote branch 'origin/master' into radeon-rewriteDave Airlie
2009-04-21i965: const correctnessBrian Paul