| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-02-26 | i965: fix for RHW workaround | Xiang, Haihao | |
| It is possible that an object whose vertices all are outside of a view plane is passed to clip thread due to the RHW workaround. This object should be rejected by clip thread. Fix bug #19879 | |||
| 2009-02-26 | radeon: fixup old packets emission for CS case | Dave Airlie | |
| 2009-02-26 | intel: Disable creating DRI2 FBconfigs with depth size != color size. | Eric Anholt | |
| While it's a nice idea to be able to allow clients to choose a smaller (or bigger for 16bpp screens!) depth size, right now DRI2 hands back a buffer with a size that matches the drawable, rather than being based off of the visual. This led to problems in readback as parts of the driver disagreed on what format the depth buffer was really in. Fixes the remainder of bug #19447. | |||
| 2009-02-26 | intel: Add span code for z24 without stencil. | Eric Anholt | |
| It seems that in this case the Mesa code is handing us x8z24 values instead of z24s8 values, so we need to not do the rotation. Fixes half of OGLconform depthrange.c. Bug #19447. | |||
| 2009-02-25 | intel: make template wrappers for the spans templates. | Eric Anholt | |
| This is insanity, but so is copying the same blocks containing the actual interesting code in the file three times each for the different tile formats. | |||
| 2009-02-25 | intel: Fix up x8r8g8b8 renderbuffer format so that alpha=1 spans code happens. | Eric Anholt | |
| I was lured into a false sense of security by the fact that the spans code was already there, and a bunch of tests didn't catch the problem. oglconform's mask.c did, though. Bug #19970. | |||
| 2009-02-26 | r100: fixup kms state emissions | Dave Airlie | |
| 2009-02-26 | radeon: avoid page flip code in DRI2 | Dave Airlie | |
| 2009-02-26 | radeon: enable DRI2 for r100 | Dave Airlie | |
| 2009-02-26 | radeon: move CB/ZB state init into emit code | Dave Airlie | |
| This removes the use of the sarea for this stuff so makes DRI2 easier and emits the CB/ZB info in the correct place | |||
| 2009-02-26 | r300: fixup texture state emission for kms path | Dave Airlie | |
| 2009-02-26 | r300: don't call page flip on DRI2 | Dave Airlie | |
| 2009-02-26 | r300: don't flush VAP too often. | Dave Airlie | |
| Flush the VAP the first time for each state atom we upload new VAP data | |||
| 2009-02-25 | i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs. | Eric Anholt | |
| 2009-02-25 | R300: Add support for RS600 chips | Alex Deucher | |
| 2009-02-25 | r300: drop r300Flush for the generic one | Dave Airlie | |
| 2009-02-24 | r300: fix bo ref/unref, plugs DRI handle leaks | Dave Airlie | |
| 2009-02-23 | r300: fixup old setTexOffset DRI1 extension | Dave Airlie | |
| 2009-02-23 | radeon: add more debug info to the flush debug | Dave Airlie | |
| 2009-02-23 | r300: revert back autostate change on cacheflush emit | Dave Airlie | |
| 2009-02-23 | r300: use OUT_BATCH_REGVAL in a few more places | Dave Airlie | |
| 2009-02-23 | r300: set u to 0 so debug logs are easier to read | Dave Airlie | |
| 2009-02-23 | radeon: stabilise r300 driver like the F10 mesa bufmgr | Dave Airlie | |
| For some reason flushs caused by this CS needs flush hook, caused the chip to lockup on r300 under compiz, whereas the F10 driver was rock solid. | |||
| 2009-02-23 | radeon: add some debugging for flush ioctls | Dave Airlie | |
| 2009-02-23 | radeon: make state atom print like old r300 code | Dave Airlie | |
| 2009-02-23 | radeon: fixup legacy bo/cs out of VRAM waiting. | Dave Airlie | |
| This is similiar to the code from the F10 r300 bufmgr | |||
| 2009-02-23 | i965: fix line stipple fallback for GL_LINE_STRIP primitives | Robert Ellison | |
| When doing line stipple, the stipple count resets on each line segment, unless the primitive is a GL_LINE_LOOP or a GL_LINE_STRIP. The existing code correctly identifies the need for a software fallback to handle conformant line stipple on GL_LINE_LOOP primitives, but neglects to make the same assessment on GL_LINE_STRIP primitives. This fixes it so they match. | |||
| 2009-02-23 | mesa: fix _glxapi_get_proc_address() for mangled names | Tom Fogal | |
| 2009-02-22 | mesa: move a bunch of compiler-related stuff into new compiler.h header | Brian Paul | |
| This trims down and cleans up imports.h and glheader.h quite a bit. | |||
| 2009-02-22 | texmem: fix typo from brianp's changes. | Dave Airlie | |
| Reported by cjb via tinderbox on irc | |||
| 2009-02-21 | mesa: use an array for current texture objects | Brian Paul | |
| Use loops to consolidate lots of texture object code. | |||
| 2009-02-21 | mesa: re-org texgen state | Brian Paul | |
| New gl_texgen struct allows quite a bit of code reduction. | |||
| 2009-02-21 | intel: Fix intelSetTexBuffer miptree leak. | Kristian Høgsberg | |
| The intelImage also holds a reference to the miptree, so unref that as well. | |||
| 2009-02-21 | intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions. | Eric Anholt | |
| This lets us avoid allocing new buffers for renderbuffers, finalized miptrees, and PBO-uploaded textures when there's an unreferenced but still active one cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded textures. The size of BOs allocated for a desktop running current GL cairogears on i915 is cut in half with this. Note that this means we require libdrm 2.4.5. | |||
| 2009-02-21 | i965: Fix render target read domains. | Eric Anholt | |
| We were asking for something illegal (write_domain != 0 && read_domains != write_domain) because at the time of writing the region surfaces were used for texturing occasionally as well, and we weren't really clear on the model GEM was going to use. This reliably triggered a kernel bug with domain handling, resulting in oglconform mustpass.c failure. Of course, it only became visible after 01bc4d441fd6821ad9fc20d5e9544e4e587e4ff0 cleaned up some gratuitous flushing. | |||
| 2009-02-20 | i965: use the new prog_instruction::TexShadow field | Brian Paul | |
| GLSL shadow() sampler calls are properly propogated down to the driver now. The glean glsl1 shadow() tests work (except for the alpha channel). | |||
| 2009-02-20 | i965: check depth_mode in translate_tex_format() for MESA_FORMAT_S8_Z24 | Brian Paul | |
| Note that I24X8 vs. A24X8 vs. L24X8 doesn't seem to make any difference for texture/shadow compare, however. | |||
| 2009-02-20 | i965: separate emit_op() and emit_tex_op() functions | Brian Paul | |
| 2009-02-20 | i965: update comment, use const qualifier | Brian Paul | |
| 2009-02-20 | i965: var renaming, clean-up | Brian Paul | |
| 2009-02-20 | i965: added comment | Brian Paul | |
| 2009-02-20 | intel: fix datatype typo, s/GLboolean/GLuint/ | Brian Paul | |
| Fixes mysterious failures in glean glsl1 test. | |||
| 2009-02-20 | i965: additional debug output | Brian Paul | |
| 2009-02-18 | r300: make DRI2 not crash on compiz start | Dave Airlie | |
| 2009-02-18 | radeon: move device param id check ifndef | Dave Airlie | |
| 2009-02-17 | radeon: initialise swapped objects pointer | Dave Airlie | |
| 2009-02-17 | radeon: legacy texMem interface fixups. | Dave Airlie | |
| The texmem.c interface is wildly messed up it really wants to own the objects so let it, pain in the ass but this code should work a lot better now | |||
| 2009-02-17 | Revert "dri/radeon: export a function to cleanup a texture object." | Dave Airlie | |
| This reverts commit 5325f8624093bb1ec30d581b4ff64218ceab99f9. | |||
| 2009-02-17 | radeon/r200: drop legacy texture heap code | Dave Airlie | |
| 2009-02-17 | radeon/r200: fixup texturing aging calls | Dave Airlie | |
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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