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This adds (so far) unused PBO functions, and holding the lock while writing
to regions (which may be shared static screen regions).
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The idling it was trying to ensure was covered by the
intel_miptree_image_map()->intel_region_map() that immediately followed it.
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Each buffer object now has a relocation buffer pointer, which contains the
relocations for the buffer if there are any. At the point where we have to
create a new type of relocation entry, we can change the code over to allowing
multiple relocation lists, but trying to anticipate what that'll look like
now just increases complexity.
This is a 30% performance improvement on 965.
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The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
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Now that the dri_bufmgr is stored in the context rather than the screen, all
access to one is single-threaded anyway.
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bufmgr_fake doesn't care about it, but with ttm we would end up with the
buffer remaining referenced until application exit.
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I broke this with cherry-pick resolving on
93c98a466947570e0589b662df49095b2f4bc43c.
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Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
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This takes advantage of the DRM_BO_HINT_PRESUMED_OFFSET change and allows
the kernel to avoid mapping and re-writing buffers when relocations occur.
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This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
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state."
I had forgotten part of brw_state_cache.c that made this fix not relevant for
master (last_addr comparison and flagging based on cache id).
This reverts commit a4642f3d18bdaebaba31e5dee72fe5de9d890ffb.
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Otherwise, choosing a new program wouldn't necessarily update the state, and
and an old program could be executed, leading to various sorts of pretty
pictures or hangs.
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by another window.
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Reduces diff to branch which has a relocation in this state emit.
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The uint64_t flags (as defined by drm.h) were being used as unsigned ints in
many places.
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it should be handled in fb_write.
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Pixel Mask Copy is modified as the pixel shader thread
turns off pixels based on kill instructions.
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t_vb_program.c
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See https://bugs.freedesktop.org/show_bug.cgi?id=13324 .
Also use tx_table_be for VALID_FORMAT, in case r200SetTexImages ever gets
called for MESA_FORMAT_RGB888.
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It makes quake4-demo works well on 965.
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to IP pre-increment, and should point to
the first instruction after the do instruction
of the do-while block of code
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This could lead to incorrect rendering or even lockups.
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The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
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This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
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