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Previously, a register defined at main scope and used in a loop in a
loop could end up getting marked as needed only from the definition
outside of the loops to the end of the inner loop, and we would
cleverly slot in something else in its register in the end of the
outer loop.
Fixes glsl-vs-loop-nested and glsl-fs-loop-nested on glsl2. This
doesn't happen much on master because the original compiler does its
own register allocation, so we find little we can do with linear scan
register (re)allocation.
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Reported by Karl Schultz.
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Conflicts:
src/mesa/drivers/dri/i965/brw_wm_emit.c
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Check whether the index is within bounds before accessing the array.
Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
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Bug #24984.
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This shaves more instructions off of the VS of my GL demo, but no
performance difference this time at n=6. This also fixes a regression
that was in this path, which is now piglit's glsl-vs-mov-after-deref.
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Fixes bug 24967.
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Depending on the writemask or the opcode, we can often trim the source
channels considered used for dead code elimination. This saves actual
instructions on 965 in the non-GLSL path for glean glsl1, and cleans up
the writemasks of programs even further.
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This fixes the dead code elimination to work on the particular code
mentioned in the previous commit.
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GLSL code such as:
vec4 result = {0, 1, 0, 0};
gl_FragColor = result;
emits code like:
0: MOV TEMP[0], CONST[0];
1: MOV OUTPUT[1], TEMP[0];
and this replaces it with:
0: MOV TEMP[0], CONST[0];
1: MOV OUTPUT[1], CONST[0];
Even when the dead code eliminator fails to clean up a now-useless MOV
instruction (since it doesn't do live/dead ranges), this should at reduce
dependencies.
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This cleans up a bunch of instructions in GLSL programs to have limited
writemasks, which would translate to wins in shaders that hit the i965
brw_wm_glsl.c path by depending less on in-driver optimizations. It will
also help hit other optimization passes I'm looking at.
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Seems to b working well enough to enable all the time.
Optimizations can be disabled with "export MESA_GLSL=nopt" if needed.
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This is a check-point commit; not turned on yet.
Use the linear scan register allocation algorithm to re-allocate temporary
registers. This is done by computing the live intervals for registers and
reallocating temps with that information.
For some shaders this dramatically reduces the number of temp registers
needed.
For the time being we give up on a few cases such as relative-indexed temps
and subroutine calls (but we inline most GLSL functions anyway).
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This is pretty simplistic for now, but helps with certain shaders.
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