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Actually, window width - 1, height - 1
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This is a check-point commit; not turned on yet.
Use the linear scan register allocation algorithm to re-allocate temporary
registers. This is done by computing the live intervals for registers and
reallocating temps with that information.
For some shaders this dramatically reduces the number of temp registers
needed.
For the time being we give up on a few cases such as relative-indexed temps
and subroutine calls (but we inline most GLSL functions anyway).
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Initialize the shader's pragma settings before calling the compiler.
Added pragma "Ignore" fields to allow overriding the #pragma directives found
in shader source code.
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BTW, the debug pragma syntax is "#pragma debug(on)"
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wasn't good enough for deeply nested if's.
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This reverts commit 752296b8f311c5e3844f3ce89d17ba57224ce5ba.
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trying to unroll, bail, and fallback to doing the real loop.
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add new entrypoints, new texture format, etc
translate in texenvprogram.c for drivers using the mesa-generated tex env
fragment program
also handled in swrast, but not tested (cannot work due to negative texel
results not handled correctly)
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This was used to handle both variable declarations and references to variables.
Instead, just do storage allocation and assignment for declarations and
references, respectively.
This is a step toward better var/uniform allocation (only allocate storage
for vars/uniforms that are actually referenced by the code).
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This regression came from commit c0b59420eec5ffdf22a5919d38851c3620b97c09.
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This was never fully fleshed out and hasn't been used.
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This still needs more testing bug glean and Mesa GLSL tests seem OK.
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This is pretty simplistic for now, but helps with certain shaders.
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And check opcode number to avoid crashing on driver-private opcodes.
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See bug 20319.
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s/FRAG_RESULT_DEPR/FRAG_RESULT_DEPTH/
s/FRAG_RESULT_COLR/FRAG_RESULT/COLOR/
Remove FRAG_RESULT_COLH (NV half-precision) output since we never used it.
Next, we might merge the COLOR and DATA outputs (COLOR0, COLOR1, etc).
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Plus add some comments.
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The i965 driver needs an extra instruction field for color output information.
It was using the Sampler field for this. Use the Aux field instead. This
will probaby be revisited at some point...
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This fixes swizzled conditional expressions such "(b ? p : q).x"
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This fixes the case of "infinitely" nested swizzles such as EXPR.wzyx.yxwz.xxyz
This doesn't appear in typical shaders but with function inlining and the
compiler's internal use of swizzles it can happen.
New glean glsl1 test case added for this.
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New gl_texgen struct allows quite a bit of code reduction.
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Such TEX instructions will have the TexShadow flag set.
The gl_program::ShadowSamplers field is now set in the linker. We missed
that before.
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If the instruction is TEX/TXP/TXL/etc the TexShadow field will be true if
the instruction is a texture fetch with shadow compare.
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Move the is_boolean/integer_type() calls out of the loops.
Move the is_sampler_type() function near the bool/int functions.
Add a bunch of comments.
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We were off by one when checking for too many uniform values.
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If the vertex shader writes to a varying array with a variable index,
mark all the elements of that array as being written.
For example, if the vertex shader does:
for (i = 0; i < 4; i++)
gl_TexCoord[i] = expr;
Mark all texcoord outputs as being written, not just the first.
Linking will fail if a fragment shader tries to read an input that's not
written by the vertex shader. Before this fix, this linker test could fail.
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Old limit was 256. Note that no arrays are declared to this size.
The only place we have to be careful about raising this limit is the
prog_src/dst_register Index bitfields. These have been bumped up too.
Added assertions to check we don't exceed the bitfield in the future too.
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This new issue was exposed by commit 6eabfc27f19a10dfc2663e99f9560966ba1ff697
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This fixes a bug found with swizzled array indexes such as in "array[index.z]"
where "index" is an ivec4.
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Not all cases were handled before.
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Note: the default value for EmitCondCodes is FALSE. This means the GLSL
compiler will emit code like this:
SEQ TEMP[0].x, A, B;
IF TEMP[0].x;
...
ENDIF
But if EmitCondCodes is TRUE, condition codes will be used instead:
SEQ.C TEMP[0].x, A, B;
IF (NE.xxxx);
...
ENDIF
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