Age | Commit message (Collapse) | Author |
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Conflicts:
src/gallium/auxiliary/util/u_cpu_detect.c
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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lim x->0 log(x) = -inf so -FLT_MAX is a better approximation than 0
for LG2(0).
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Since sqrt() is basically implemented in terms of RSQ/RCP we'll do a
divide by zero if x=0 and wind up with unpredictable results.
Now use CMP instruction to test for x<=0 and return zero in that case.
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These options can be used to force vertex/fragment shaders to be no-op
shaders (actually, simple pass-through shaders). For debug/test purposes.
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For debug/test purposes.
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Conflicts:
src/mesa/shader/program_parse.tab.c
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Conflicts:
src/mesa/drivers/dri/intel/intel_clear.c
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Conflicts:
src/mesa/vbo/vbo_exec_array.c
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This is similar to what r300 does inside the driver, but I've added it as
a generic option since it seems most hardware will want it.
Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
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This helps let drivers treat NV_vp like ARB_vp.
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Conflicts:
src/mesa/drivers/dri/r600/r700_assembler.c
src/mesa/drivers/dri/r600/r700_chip.c
src/mesa/drivers/dri/r600/r700_render.c
src/mesa/drivers/dri/r600/r700_vertprog.c
src/mesa/drivers/dri/r600/r700_vertprog.h
src/mesa/drivers/dri/radeon/radeon_span.c
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The handling is a bit inefficient, unfortunately, but I don't want to make
any intrusive changes for Mesa 7.6.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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When we concatenate shaders to do our form of poor-man linking, if there's
multiple #version directives, preprocessing fails. This change disables
the extra #version directives by changing the first two chars to //.
This should help with some Wine issues such as bug 23946.
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Never set in mesa. Remove from tgsi translation as well.
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Conflicts:
src/mesa/shader/lex.yy.c
src/mesa/shader/program_parse.tab.c
src/mesa/shader/program_parse.tab.h
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Conditional write masks and the condition-code based KIL instruction
are all supported. The specific behavior of KIL in the following
shader may or may not match the behavior of other implementations:
!!ARBfp1.0
TEMP GT;
MOVC GT, fragment.texcoord[0];
KIL GT.x;
END
Should be it interpreted as 'KIL srcReg' or as 'KIL ccTest'? The
current parser will interpret it as 'KIL srcReg'.
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The lexer will return IDENTIFIER only when the name does not have an
associated symbol. Otherwise USED_IDENTIFIER is returned.
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Adds support for declaring TEMP and OUTPUT variables as 'LONG' or
'SHORT' precision. The precision specifiers are parsed, but they are
currently ignored. Some support for this may be added in the future,
but neither Intel hardware nor, as far as I'm aware, Radeon hardware
support multiple precisions.
Also adds support for instruction precision ('X', 'H', and 'R')
suffixes and instruction condition code output ('C') suffix. This
results in a fairly major change to the lexer. Instructions are
matched with all the possible suffix strings. The suffix string are
then carved off by a context (i.e., which program mode and options are
set) aware parser that converts the suffixes to bits in
prog_instruction.
This could have been handled in the same way _SAT was originally
handled in the lexer, but it would have resulted in a very large lexer
with lots of opportunity for cut-and-paste errors.
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The new constructor copies fields from the prog_instruction that the
parser expects the lexer to set.
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Fixes compilation warnings with MSVC.
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Fixes symbol collisions with typedefs in Microsoft headers.
Perhaps we should prefix/suffix all the lexer tokens to avoid this.
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