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2009-09-14st/mesa: convert to new tgsi_ureg mechanism for shader emitKeith Whitwell
Should be easier to read and work with than the older ways of emitting TGSI tokens. Also, emit simpler TGSI than previously: - translate away source and dest extended modifiers - translate away the SWZ opcode
2009-09-12mesa: remove unused SATURATE_PLUS_MINUS_ONE flagKeith Whitwell
Never set in mesa. Remove from tgsi translation as well.
2009-09-11i965: Move OPCODE_DDX/DDY to brw_wm_emit.c and make it actually work.Eric Anholt
Previously, it was trying to mess around with the varying's WM setup data to produce a result. Along with not actually working when passed a varying, this wouldn't work if you did dFd[xy]() on a temporary. Instead, just calculate the derivative using the neighbors in the subspan.
2009-09-11r600: fix texcoords from constantsAndre Maasikas
with some minor updates from Richard.
2009-09-11Revert "r600: support tex coords from constants"Alex Deucher
This reverts commit 4099bb76148007f9ccb6c86838b2bf37ea42de56. Tex coord src has to be a GPR.
2009-09-11r600: support tex coords from constantsAlex Deucher
Fixes neverball among other things.
2009-09-11r600: enable caching of vertex programsAndre Maasikas
2009-09-10i965: Enable loops in the VS.Eric Anholt
Passes piglit glsl-vs-loop testcase. Bug #20171
2009-09-10mesa: nicer vertex setupBrian Paul
2009-09-10st/mesa: use st_context() helperBrian Paul
2009-09-10Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-10intel: disable intel_stencil_drawpixels() for nowBrian Paul
It doesn't work reliably even when all the prerequisite checks are made.
2009-09-10Fix merge failIan Romanick
One of the conflicst from this merge was missed: commit 0c309bb494b6ee1c403442d1207743f749f95b6e Merge: c6c44bf d27d659 Author: Brian Paul <brianp@vmware.com> Date: Wed Sep 9 08:33:39 2009 -0600
2009-09-10mesa: need to set all stencil bits to 0 before setting the 1 bitsBrian Paul
Plus, check for pixel transfer stencil index/offset.
2009-09-10Merge branch 'mesa_7_5_branch' into mesa_7_6_branchIan Romanick
Conflicts: src/mesa/drivers/dri/intel/intel_context.c
2009-09-10i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254 (cherry picked from commit 5604b27b9326ac542069a49ed9650c4b0d3e939a)
2009-09-10intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Hopefully this will be one of the last cherry-picks. (cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
2009-09-10intel: Don't forget to map the depth read buffer in spans.Eric Anholt
This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
2009-09-10r300: enable rb3d_discard_src_pixel_lte_threshold for more chips on dri2Alex Deucher
2009-09-10r300: add full support for two sided stencil on r5xx for dri2Alex Deucher
2009-09-10mesa: fix cut&paste typosMathias Frohlich
2009-09-10mesa: in texenvprogram code, only do saturation when really needed.Brian Paul
For some env modes (like modulate or replace) we don't have to clamp because we know the results will be in [0,1].
2009-09-10radeon: Change debugging code to use macros instead of inline functions.Pauli Nieminen
Variadic functions can't be inlined which makes debugging to have quite large function overead. Only aleternative method is to use variadic macros which are inlined so compiler can optimize debugging to minimize overhead.
2009-09-09i965: Fix relocation delta for WM surfaces.Eric Anholt
This was a regression in 0f328c90dbc893e15005f2ab441d309c1c176245. Bug #23688 Bug #23254
2009-09-09radeon: Add more verbose error message for failed command buffer.Pauli Nieminen
2009-09-09i965: fix an overlooked merge conflictBrian Paul
2009-09-09r600: check if textures are actually enabled before submissionAlex Deucher
noticed by taiu on IRC.
2009-09-09Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-09mesa: regenerate get.c form get_gen.pyBrian Paul
2009-09-09mesa: move call to init_c_cliptest() from enable.c to tnl module.Brian Paul
Fixed gallium build breakage.
2009-09-09Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
2009-09-09mesa: disable GL_LUMINANCE case in _mesa_meta_draw_pixels()Brian Paul
Works around a bug found on i965. See bug 23670.
2009-09-09r600: fix ftp for dri1Alex Deucher
We use t->bo for dri1 since r600 uses CS for dri1.
2009-09-09intel: add B43 chipset supportZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2009-09-09r600: don't setup hardware state if TFPDave Airlie
if we have a BO here it means TFP and we should have set it up already. tested by b0le on #radeon
2009-09-08mesa: bump version to 7.7Brian Paul
2009-09-08mesa: fix viewport_z_clip breakageBrian Paul
2009-09-08intel: Add support for ARB_draw_elements_base_vertex.Eric Anholt
On the 965, we just drop the value into the primitive packet. On non-945, we rely on the sw tnl code handling it.
2009-09-08mesa: Add support for ARB_draw_elements_base_vertex.Eric Anholt
2009-09-08glapi: Add ARB_draw_elements_base_vertexEric Anholt
2009-09-08mesa: Expose NV_depth_clamp if ARB_depth_clamp is supported.Eric Anholt
The wording of these two is exactly the same, except for the issue "Can fragments with wc<=0 be generated when this extension is supported?", which idr thinks is a non-issue for us.
2009-09-08i965: Add support for ARB_depth_clamp.Eric Anholt
2009-09-08Regenerate files for GL_ARB_depth_clamp.Eric Anholt
2009-09-08mesa: Add support for ARB_depth_clamp.Eric Anholt
This currently doesn't include fixing up the cliptests in the assembly paths to support ARB_depth_clamp, so enabling depth_clamp forces the C path.
2009-09-08i965: Respect spec requirement for pixel shader computed depth with no zbuffer.Eric Anholt
2009-09-08i965: Set NULL WM surfaces as tiled according to requirement by specs.Eric Anholt
2009-09-08i965: Use the renderbuffer surface size instead of region size for WM surfaces.Eric Anholt
For drawing to lower mipmap levels, the region size makes the renderbuffer be the size of the lowest level, instead of the current level. On DRI1, Brian previously found that the RB size was incorrect, so leave this broken there.
2009-09-08Revert "intel: helper to debug bufmgr (disabled)"Eric Anholt
This reverts commit e0ec405a9fa6fbc1cf2ac531ed5efd1a64e01f18. This is already available in INTEL_DEBUG=bufmgr in the environment.
2009-09-08mesa: bump version to 7.5.2Brian Paul
I'm not 100% sure there'll be a 7.5.2 release, but just in case.
2009-09-08i965: #include clean-upsBrian Paul
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