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Plus, update the print/debug code.
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Only one flag defined so far: PROG_PARAM_CENTROID_BIT
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function
Bug #18659.
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There were hacks in EmitCopyBlit before to adjust offsets so that y=0 after
the offsets had been adjusted for a negative pitch. It appears that those
hacks were due to an unclear and surprising aspect of the hardware: inverting
the pitch results in the blit into the specified rectangle being inverted,
without the user needing to adjust y and base offset.
Tested with piglit copytexsubimage test on 915GM and GM965. Should fix
serious performance issues with ETQW and other applications.
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The blit bitmap code already handles scissoring. This is a 15-100% speedup on
blender benchmark.blend thanks to avoiding fallbacks. Bug #17951.
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Instead, have i965 and i915 both call the generic function from their Viewport.
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Some code cleanup is still in order.
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texture comparison logic is bypassed if the currently bound texture is not
a depth/depth_stencil texture.
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According to Keith the docs have these offsets the other way around
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RETURN0 macro reports file/line before returning zero.
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We now express arrays in terms of indirect addressing. For example:
dst = a[i];
becomes:
MOV dst, TEMP[1 + TEMP[2].y];
At instruction-emit time indirect addressing is converted into ARL/
ADDR-relative form:
ARL ADDR.x, TEMP[2].y;
MOV dst, TEMP[1 + ADDR.x];
This fixes a number of array-related issues. Arrays of arrays and complex
array/struct nesting works now.
There may be some regressions, but more work is coming.
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This fixes glReadPixels(GL_LUMINANCE, GL_FLOAT)/glGetTexImage(GL_LUMINANCE, GL_FLOAT) issue
on fixed-point color buffers.
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Conflicts:
src/mesa/shader/prog_print.c
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The Swizzle and Size fields carry all the info we need now.
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This is a step toward better array handling code. In particular, when more
than one operand of an instruction uses indirect addressing, we'll need some
temporary instructions and registers. By converting IR storage to instruction
operands all in one place (emit_instruction()) we can be smarter about this.
Also, somewhat better handling of dst register swizzle/writemask handling.
This results in tighter writemasks on some instructions which is good for
SOA execution.
And, cleaner instruction commenting with inst_comment().
Next: remove some more dead code and additional clean-ups...
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Was broken by commit 9aca9a4b72b2a7b378e50bd88f9c3324d07375ec.
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git+ssh://marcheu@git.freedesktop.org/git/nouveau/mesa into gallium-0.2
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support.
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This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke
blender, among other apps.
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* commit 'origin/gallium-0.1':
Mesa: fix number of buffers in st_draw_vbo().
Nouveau: fix nv20_vertex_layout()
Nouveau: update nv20 miptree according to nv40.
Nouveau: build, link and use nv20.
Nouveau: name replace for nv20.
Nouveau: Rename nv20/ files as nv20.
Nouveau: copy nv30_vertprog.c to nv20.
Nouveau: start nv20 by copying the nv10 tree.
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As far as I can read in the docs, VS threads can be 1:1 with the pairs of
VUE handles allocated for them. Also, G4X can run twice as many threads as
before (though we won't unless the we bump the preferred URB entries for VS).
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We were dividing the number of URB entries by two to get number of threads,
which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the
maximum number of threads is 24, not 12.
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The clip thread could potentially deadlock when processing tristrips since
being moved back to dual-thread mode, as the two threads could each have 4 VUEs
referenced and not be able to allocate another one since SF processing
wasn't able to continue (needing 5 entries before it freed 2).
In constrained URB mode, similar deadlock could even have occurred with
polygons (so we cut back max_threads if we can't handle it any primitive type).
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It shouldn't offer anything new over what's in the docs (except for G4X notes),
but here it's all in one place.
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Conflicts:
src/mesa/shader/prog_execute.c
src/mesa/shader/slang/library/slang_vertex_builtin_gc.h
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