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It's time to start splitting some of this up.
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While I don't know of any performance changes from this (once extra
reg available out of 128), it makes the generated asm a lot cleaner
looking.
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Having the single opcode write then read the reg meant that single
instruction opcodes had to consider their source regs to interfere
with their dest regs.
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Fixes these GCC warnings.
brw_wm_fp.c: In function 'search_or_add_const4f':
brw_wm_fp.c:92: warning: 'reg.Index2' is used uninitialized in this function
brw_wm_fp.c:84: note: 'reg.Index2' was declared here
brw_wm_fp.c:92: warning: 'reg.RelAddr2' is used uninitialized in this function
brw_wm_fp.c:84: note: 'reg.RelAddr2' was declared here
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Fixes this GCC warning.
brw_vs.c: In function 'do_vs_prog':
brw_vs.c:46: warning: unused variable 'ctx'
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Fixes this GCC warning.
brw_eu_emit.c: In function 'brw_math2':
brw_eu_emit.c:1189: warning: unused variable 'intel'
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Fixes this GCC warning.
i915_vtbl.c: In function 'i915_assert_not_dirty':
i915_vtbl.c:670: warning: unused variable 'dirty'
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Fixes this GCC warning.
i830_vtbl.c: In function 'i830_assert_not_dirty':
i830_vtbl.c:704: warning: unused variable 'i830'
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Improves performance of my GLSL demo 14.3% (+/- 4%, n=4) by
eliminating the moves used in ir_assignment and ir_swizzle handling.
Still 16.5% to go to catch up to the Mesa IR backend, presumably
because instructions are almost perfectly mis-scheduled now.
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We were trying to remap a fully-filled array down to only handing the
WM the components it uses. This is called attribute swizzling, and if
you don't enable it you just get 1:1 mappings of inputs to outputs.
This almost fixes glsl-routing, except for the highest gl_TexCoord[]
indices.
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We'd overwrite the same element twice.
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We would compute a new buffer, but never point the hardware at the new
buffer. This partially fixes glsl-routing, as now it get the updated
uniform for which attribute to draw.
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If someone happened to land a set in a different swizzle order, we
would have assertion failed.
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_mesa_add_unnamed_constant() already does that.
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_mesa_add_state_reference does that check for us anyway.
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Fixes glsl-fs-texturecube-2-*
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Fixes point-line-no-cull.
Bug #30532
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We sensibly only provide it if the FS asks for it. We could actually
skip WPOS unless the FS needed WPOS.zw, but that's something for
later.
Fixes: glsl-texture2d and probably many others.
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Fixes glsl1-gl_FrontFacing var (2) with new FS.
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This should fix texturing in the new FS backend.
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Not needed now that we're doing barycentric.
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I only set it on the color_regions == 0 case, missing the important
case, causing GPU hangs on pre-gen6.
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The jump delta is now in the part of the instruction where the
destination fields used to be, and the src args are ignored (or not,
for the new non-predicated IF that we don't use yet).
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It's not that hard to detect when we need the header.
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We could do the first operand as well by flipping the comparison, but
this covered several CMPs in code I was looking at.
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A debug disable had slipped in.
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https://bugs.freedesktop.org/show_bug.cgi?id=30632
NOTE: this is a candidate for the 7.9 branch.
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NOTE: this is a candidate for the 7.9 branch.
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This uses message headers for now, since we'll need it for MRT. We
can cut out the header later.
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It instead sensibly appears in the src0 slot.
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We could try to detect this in expression handling and do it
proactively there, but it seems like less logic to do it in one
optional pass at the end.
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The glsl core should be handling most dead code issues for us, but we
generate some things in codegen that may not get used, like the 1/w
value or pixel deltas. It seems a lot easier this way than trying to
work out up front whether we're going to use those values or not.
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This also means that our intervals now highlight dead code.
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Easy enough patch, who needs a full test run. Oh, that's right. Me.
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The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't
apply to shadow compares, which always return an intensity value. The
texture swizzles can do the job for us.
Fixes:
glsl1-shadow2D(): 1
glsl1-shadow2D(): 3
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passes all piglit RG tests with softpipe.
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FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
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Luckily, one of them would result in failing out register allocation
when the other bugs were encountered. Applies to
glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still
fails register allocation, but now legitimately.
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