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seems to work here ...
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128 gprs, 256 reg-based consts
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- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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- MUL_LIT is ALU.Trans instruction
- some Trans instructions can take 3 arguments
- don't clobber dst.x, use dst.z as temp, it'll get written correct
value in last insn
- respect source swizzles
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registers takes radius
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1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
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Noticed by rnoland on IRC.
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with some minor updates from Richard.
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noticed by taiu on IRC.
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We use t->bo for dri1 since r600 uses CS for dri1.
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if we have a BO here it means TFP and we should have set it
up already.
tested by b0le on #radeon
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Fixes #22741
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Mostly fixes progs/demos/lodbias when MESA_TEX_PROG=1. But the LOD still
seems off by -1 or so.
May be an issue with the params passed to _swrast_compute_lambda()
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In get_array_bounds we were previously defining a user buffer sized as
(nr_vertices * stride). The trouble is that if the vertex data
occupies less than stride bytes, the extra tailing (stride - size)
bytes may extend outside the memory actually allocated by the app and
caused a segfault.
To fix this, define a the buffer bounds to be:
ptr .. ptr + (nr-1)*stride + element_size
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This should help to work around bugs 24083 and 23670.
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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If the 'end' index is out of bounds issue a warning as before. But instead
of just no-op'ing the draw call, examine the actual array indices to see
if they're OK. If the max array index is out of bounds, issue another
warning and no-op the draw call. Otherwise, draw normally. This is a
debug build-only feature since it could impact performance.
This "fixes" the missing torus in the OGL Distilled / Picking demo.
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92033a9516942d7272ce4bf36ecd422009bbaf60 and 822c7964819ca1fcc270880d4ca8b3de8a4276d0
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This happens to rendering with textures with a border, which had resulted
in a segfault on dereferencing the irb.
(cherry-picked from commit 8bba183b9eeb162661a287bf2e118c6dd419dd24)
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If arx and ary are equal, we still want to choose from one of them,
and not arz.
This is the same as Michal's softpipe fix.
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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The handling is a bit inefficient, unfortunately, but I don't want to make
any intrusive changes for Mesa 7.6.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Since commit 2921a2555d0a76fa649b23c31e3264bbc78b2ff5 ('intel: Deassociated
drawables from private context struct in intelUnbindContext'),
intel->driDrawable may be NULL in intel_flush().
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This should help detecting possible memory leaks with dma buffers and prevent
possible visual corruption if data would be overwriten too early.
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Do-while makes macro safe to be used with if and for constructions.
Also remove __LINE__ macro from variable name because scope is local to macro anyway.
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Copy'n'paste apparently prevented the RADEON_VERTS flag from being enabled.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Normally, the mesa/st would create a fake front buffer out of a
client-allocated surface.
In the DRI setting, however, st/dri provides a front buffer surface which is
created and maintained by the X server. Prefer to use this surface instead,
so that front buffer rendering and reading works correctly.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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