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Conflicts:
src/mesa/drivers/dri/intel/intel_clear.c
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As shown in mfeatures.h, this allows users of convolve.h to work without
knowing if the feature is available.
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As shown in mfeatures.h, this allows users of colortab.h to work
without knowing if the feature is available.
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As shown in mfeatures.h, this allows users of pixel.h to work without
knowing if the feature is available.
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The comments document the conventions that a feature may follow.
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Handles GL_TEXTURE_1D, GL_TEXTURE_2D, GL_TEXTURE_CUBE_MAP.
But GL_TEXTURE_3D and texture borders not supported yet.
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This fixes the clears in openarena with the new metaops clear code, and
the new piglit vbo-subdata-sync test.
Bug #23857.
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Its flagging of extra state that's already flagged by the vtbl new_batch
when appropriate was confusing my tracking down of the OA clear bug.
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Conflicts:
src/mesa/vbo/vbo_exec_array.c
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This is similar to what r300 does inside the driver, but I've added it as
a generic option since it seems most hardware will want it.
Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
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This helps let drivers treat NV_vp like ARB_vp.
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At the time of the enable there may not be a Z buffer, but one
may be attached to the FBO later.
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If the currently bound FBO isn't yet validated it's possible for
rgbMode to be zero so we'll lose the texture enable.
This could fix some FBO rendering glitches, but I don't know of
any specific instances.
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If there happened to be a bound VBO when intel_generate_mipmap() was
called we blew up because of a bad vertex array pointer.
Fixes regnumonline, bug 23859.
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Otherwise some apps will emit tons of warnings.
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Radeon generic scissors code had problem that some of code was using exclusive
and some inclusive bottom right corner. Only r600 driver is using exclusive
coordinate so changed generic code to pass inclusive coordinate and r600 driver
changes BR coordinate to be exclusive.
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Conflicts:
src/mesa/drivers/dri/r600/r700_assembler.c
src/mesa/drivers/dri/r600/r700_chip.c
src/mesa/drivers/dri/r600/r700_render.c
src/mesa/drivers/dri/r600/r700_vertprog.c
src/mesa/drivers/dri/r600/r700_vertprog.h
src/mesa/drivers/dri/radeon/radeon_span.c
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seems to work here ...
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128 gprs, 256 reg-based consts
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- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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- MUL_LIT is ALU.Trans instruction
- some Trans instructions can take 3 arguments
- don't clobber dst.x, use dst.z as temp, it'll get written correct
value in last insn
- respect source swizzles
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registers takes radius
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1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
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Noticed by rnoland on IRC.
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with some minor updates from Richard.
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noticed by taiu on IRC.
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We use t->bo for dri1 since r600 uses CS for dri1.
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if we have a BO here it means TFP and we should have set it
up already.
tested by b0le on #radeon
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Caused by some weird logic regarding the __WIN32__ define which made
the finite definition dependent on the header include order.
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