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2007-11-30fix broken two-sided stencilBrian
2007-11-30Updates of some OpenVMS makefiles.joukj
2007-11-30Merge branch 'master' of git+ssh://joukj@git.freedesktop.org/git/mesa/mesajoukj
2007-11-30i965: if source depth to render target is set,Xiang, Haihao
it should be handled in fb_write.
2007-11-30i965: use uncompressed instruction to ensure onlyXiang, Haihao
Pixel Mask Copy is modified as the pixel shader thread turns off pixels based on kill instructions.
2007-11-29[i915] Make INTEL_DEBUG=bufmgr actually do things for bufmgr_fake.Eric Anholt
2007-11-29New ctx->Driver.Map/UnmapTexture() functions for accessing textures from ↵Brian
t_vb_program.c
2007-11-29cleanups, commentsBrian
2007-11-29Move _mesa_load_tracked_matrices() from TNL module to prog_statevars.cBrian
2007-11-28r200: Fix texture format regression on big endian systems.Michel Dänzer
See https://bugs.freedesktop.org/show_bug.cgi?id=13324 . Also use tx_table_be for VALID_FORMAT, in case r200SetTexImages ever gets called for MESA_FORMAT_RGB888.
2007-11-28i965: update RefCount when using Vertex/Fragment program.Xiang, Haihao
It makes quake4-demo works well on 965.
2007-11-27use DEFAULT_SOFTWARE_DEPTH_BITSDelle
2007-11-27set fp->UsesKill when emitting OPCODE_KILBrian
2007-11-27improve 24-bit Z to 32-bit Z conversionBrian
2007-11-27i965: The jump instruction count is addedXiang, Haihao
to IP pre-increment, and should point to the first instruction after the do instruction of the do-while block of code
2007-11-26i915: Catch cases where not all state is emitted for a new batchbuffer.Keith Whitwell
This could lead to incorrect rendering or even lockups.
2007-11-26i915: Some additional blit fixes and assertions.Michel Dänzer
2007-11-25intel: Fix relative symlinks.Michel Dänzer
2007-11-23Consolidate texture fetch code and use partial derivatives when possible.Brian
2007-11-23Fix parsing of gl_FrontLightModelProduct.sceneColor, don't segfault on ↵Brian
variable array indexes.
2007-11-23need to check border width in sample_linear_2d() - fixes failed assertion in ↵Brian
texwrap.c test
2007-11-22Consolidate point size computation, clamping in get_size().Brian
Also, apply user-defined clamp limits to point size even when not using attentuation or program-computed size.
2007-11-22fix z buffer read/write issue with rv100-like chips and old ddxRoland Scheidegger
2007-11-20[965] Replace 965 texture format code with common code.Eric Anholt
The only functional difference should be that 965 now gets the optimization where textures default to 16bpp when the screen is 16bpp.
2007-11-20[965] Remove dead exec vfmt code which was replaced by generic vbo code.Eric Anholt
2007-11-20clamp lambda to Min/MaxLodBrian
2007-11-19[965] Add INTEL_DEBUG=fall debugging output.Eric Anholt
2007-11-19[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.Eric Anholt
2007-11-19fix some texture format assertions, etcBrian
2007-11-19fix out-of-bounds array index (ix=-1)Brian
2007-11-16[intel] Add 965 support to shared intel_blit.cEric Anholt
This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16[i915] Pass static region names in so debugging says more than "static region".Eric Anholt
2007-11-16[intel] Move additional code to be shared from intel_context.h to intel/.Eric Anholt
2007-11-16[intel] Move intel_tex.h into place, forgotten in the previous commit.Eric Anholt
2007-11-16[965] Add batchbuffer decode for several more packets.Eric Anholt
2007-11-16[intel] Fix typos in intel_chipset.h macros.Eric Anholt
2007-11-16[i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them.Eric Anholt
2007-11-16[i915] Reenable batchbuffer debug under INTEL_DEBUG=bat.Eric Anholt
2007-11-16[intel] Add some doxygen notes on what the bufmgr_fake block members mean.Eric Anholt
2007-11-16[intel] Add a simple relocation cache to the fake buffer manager.Eric Anholt
This is required for 965 performance, as it avoids a lot of repeated data uploads of the state caches due to surface offsets in them.
2007-11-16[intel] Assert against 0-sized buffers in dri_bufmgr_fake.c.Eric Anholt
They shouldn't be created, and this often helps catch stupid issues.
2007-11-16[intel] Add support for multiple levels of relocation in bufmgr_fake.Eric Anholt
This is required for 965 support, which has relocations in other places than just the batchbuffer.
2007-11-16[i915] Push locking in intelClearWithTris down inside meta_draw_poly.Eric Anholt
The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad.
2007-11-15fix bogus assumption if ddx has set up surface reg for z bufferRoland Scheidegger
this is wrong since even if ddx has not set up a surface reg to cover the z buffer we should pretend it has on those rv100 chips since they presumably do not do z buffer tiling if not using hyperz, so we can use linear addressing just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug almost certainly broke newer non-tcl chips.
2007-11-15fix position invariant vertex programs for sw-tnlRoland Scheidegger
do the same math as for fixed function pipe, including user clip planes. (mostly resurrected from the dead t_vb_arbprogram.c code)
2007-11-12i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730Xiang, Haihao
2007-11-09[i915] Remove old frontbuffer rotation hack.Eric Anholt
This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately.
2007-11-09[intel] By default, output batchbuffer decode to stderr like other debug info.Eric Anholt
2007-11-09[intel] Initialize a depth buffer if the visual has depth 24 but no stencil.Eric Anholt
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt
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