Age | Commit message (Collapse) | Author | |
---|---|---|---|
2008-11-05 | mesa: remove extra \n from printf string | Brian Paul | |
2008-11-05 | mesa: add Initialized field to gl_uniform struct, for debugging purposes only | Brian Paul | |
2008-11-05 | mesa: add Initialized field to gl_uniform struct, for debugging purposes only | Brian Paul | |
2008-11-05 | Merge commit 'origin/master' into gallium-0.2 | Alan Hourihane | |
2008-11-04 | mesa: fix float-valued GLSL vertex attribute variables | Brian Paul | |
The swizzle mask for such variables wasn't set up properly. | |||
2008-11-04 | mesa: fix float-valued GLSL vertex attribute variables | Brian Paul | |
The swizzle mask for such variables wasn't set up properly. | |||
2008-11-03 | gallium: no renderbuffer, so just exit. | Alan Hourihane | |
2008-11-03 | i965: Clean up stale NDC comment. | Eric Anholt | |
2008-11-03 | i965: Avoid vs header computation for negative rhw on G4X. | Eric Anholt | |
This cuts one MOV out when setting a zero header. | |||
2008-11-03 | i965: Merge GM45 into the G4X chipset define. | Eric Anholt | |
The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up. | |||
2008-11-03 | i965: Fix copy'n'paste issue that made brw->urb.constrained useless. | Eric Anholt | |
Also, add a comment explaining what brw->urb.constrained tries to do. | |||
2008-11-03 | softpipe: Don't call pipe_buffer_destroy directly. | José Fonseca | |
Use pipe_buffer_reference instead. | |||
2008-11-02 | i965: Clean up stale NDC comment. | Eric Anholt | |
2008-11-02 | i965: Avoid vs header computation for negative rhw on G4X. | Eric Anholt | |
This cuts one MOV out when setting a zero header. | |||
2008-11-02 | i965: Merge GM45 into the G4X chipset define. | Eric Anholt | |
The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up. | |||
2008-11-02 | i965: Fix copy'n'paste issue that made brw->urb.constrained useless. | Eric Anholt | |
Also, add a comment explaining what brw->urb.constrained tries to do. | |||
2008-11-01 | Merge commit 'origin/master' into gallium-0.2 | Alan Hourihane | |
Conflicts: src/mesa/shader/slang/library/slang_vertex_builtin_gc.h | |||
2008-11-01 | mesa: silence warnings | Brian Paul | |
2008-11-01 | mesa: do scope replacement for while/for loops too | Brian Paul | |
This fixes a function inlining bug involving vars declared inside loop bodies. | |||
2008-11-01 | mesa: glsl tree print improvements | Brian Paul | |
2008-11-01 | mesa: fix assignment / parameter passing of sampler types | Brian Paul | |
2008-11-01 | mesa: additional debug flags for glsl debug/disassembly | Brian Paul | |
2008-11-01 | mesa: silence warnings | Brian Paul | |
2008-11-01 | mesa: do scope replacement for while/for loops too | Brian Paul | |
This fixes a function inlining bug involving vars declared inside loop bodies. | |||
2008-11-01 | mesa: glsl tree print improvements | Brian Paul | |
2008-11-01 | mesa: fix assignment / parameter passing of sampler types | Brian Paul | |
2008-11-01 | mesa: additional debug flags for glsl debug/disassembly | Brian Paul | |
2008-11-01 | Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1 | Keith Packard | |
Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <keithp@keithp.com> | |||
2008-10-31 | mesa: fix some bugs with precision qualifier parsing | Brian Paul | |
2008-10-31 | mesa: do scope replacement for variable initializers too | Brian Paul | |
2008-10-31 | mesa: fix copy/paste error in GLSL error msg | Brian Paul | |
2008-10-31 | mesa: fix some bugs with precision qualifier parsing | Brian Paul | |
2008-10-31 | mesa: do scope replacement for variable initializers too | Brian Paul | |
2008-10-31 | mesa: fix copy/paste error in GLSL error msg | Brian Paul | |
2008-10-31 | intel: pixelzoom doesn't apply to glBitmap, so disable the fallback. | Eric Anholt | |
2008-10-31 | intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX) | Eric Anholt | |
GL_COLOR_INDEX mode is just like other normal formats (that is, not depth/stencil) and is uploaded fine by TexImage. | |||
2008-10-31 | intel: Add more fallback debugging for glDrawPixels. | Eric Anholt | |
2008-10-31 | i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions. | Gary Wong | |
(Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.) | |||
2008-10-31 | i965: support destination horiz strides in align1 access mode. | Gary Wong | |
This is required for scatter writes in destination regions to work. | |||
2008-10-31 | mesa: fix a typo in the previous commit | Xiang, Haihao | |
2008-10-30 | mesa: fix an issue in _mesa_PointParameterfv(). | Xiang, Haihao | |
2008-10-28 | intel: Fix glDrawPixels with 4d RasterPos. | Eric Anholt | |
2008-10-28 | i965: Fix check_aperture calls to cover everything needed for the prim at once. | Eric Anholt | |
Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive. | |||
2008-10-28 | mesa: fix stand-alone glslcompiler build | Brian Paul | |
2008-10-28 | intel: Don't keep intel->pClipRects, and instead just calculate it when needed. | Eric Anholt | |
This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change. | |||
2008-10-28 | i965: Allocate temporaries contiguously with other regs in fragment shaders. | Gary Wong | |
This is required for threads to be spawned with correctly sized GRF register blocks. | |||
2008-10-27 | i965: Fix compiler warning from unused var. | Eric Anholt | |
2008-10-27 | i965: Remove dead brw->wrap flag. | Eric Anholt | |
2008-10-27 | intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names. | Eric Anholt | |
Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL, which needs a handle, and failing. None of our buffers were tiled yet, but they will be at some point with DRI2 and UXA. | |||
2008-10-27 | Merge commit 'origin/master' into gallium-0.2 | Alan Hourihane | |