Age | Commit message (Expand) | Author |
2009-09-16 | Merge branch 'mesa_7_5_branch' into mesa_7_6_branch | Ian Romanick |
2009-09-16 | intel: Deassociated drawables from private context struct in intelUnbindContext | Ian Romanick |
2009-09-16 | i965: do a flush in clear, fix openarena render issue, | Zou Nan hai |
2009-09-15 | mesa: compile glUniformMatrix() functions into display lists | Brian Paul |
2009-09-15 | mesa: implement more glUniform display list functions | Brian Paul |
2009-09-15 | mesa: compile glUniform4f() into display lists | Brian Paul |
2009-09-15 | mesa: compile glUseProgram/glUseProgramObjectARB into display lists | Brian Paul |
2009-09-15 | Merge commit 'origin/mesa_7_5_branch' into mesa_7_6_branch | Ian Romanick |
2009-09-15 | GLX: Complain when buggy applications call GLX 1.3 functions. | Ian Romanick |
2009-09-15 | Merge branch 'mesa_7_5_branch' into mesa_7_6_branch | Brian Paul |
2009-09-14 | glsl: added some link debug code (disabled) | Brian Paul |
2009-09-14 | glsl: remove extra #version directives from concatenated shader sources | Brian Paul |
2009-09-14 | gallium: Add Mac OS to pipe/p_thread.h. | Vinson Lee |
2009-09-11 | llvmpipe: asst fixes for 'make linux-llvmpipe' | Brian Paul |
2009-09-11 | mesa: raise GL_INVALID_ENUM not GL_INVALID_VALUE for glTexParamter errors | Vinson Lee |
2009-09-11 | radeon: Remove structure allocation from iterator variable. | Pauli Nieminen |
2009-09-10 | Merge branch 'mesa_7_5_branch' into mesa_7_6_branch | Brian Paul |
2009-09-10 | intel: disable intel_stencil_drawpixels() for now | Brian Paul |
2009-09-10 | softpipe: minor indentation fix | Brian Paul |
2009-09-10 | softpipe: set dirty_render_cache in softpipe_clear() | Brian Paul |
2009-09-10 | Fix merge fail | Ian Romanick |
2009-09-10 | tgsi: use new tgsi_call_record to handle execution mask stacks | Brian Paul |
2009-09-10 | mesa: need to set all stencil bits to 0 before setting the 1 bits | Brian Paul |
2009-09-10 | Merge branch 'mesa_7_5_branch' into mesa_7_6_branch | Ian Romanick |
2009-09-10 | i965: Fix relocation delta for WM surfaces. | Eric Anholt |
2009-09-10 | intel: add B43 chipset support | Zhenyu Wang |
2009-09-10 | mesa: in texenvprogram code, only do saturation when really needed. | Brian Paul |
2009-09-10 | gallium: Add PIPE_OS_APPLE back to auxiliary/util/u_time.h. | Vinson Lee |
2009-09-10 | radeon: Change debugging code to use macros instead of inline functions. | Pauli Nieminen |
2009-09-09 | radeon: Add more verbose error message for failed command buffer. | Pauli Nieminen |
2009-09-09 | Merge branch 'mesa_7_5_branch' into mesa_7_6_branch | Brian Paul |
2009-09-09 | gallium: Added HaikuOS platform | aljen |
2009-09-09 | mesa: disable GL_LUMINANCE case in _mesa_meta_draw_pixels() | Brian Paul |
2009-09-08 | mesa: bump version to 7.5.2 | Brian Paul |
2009-09-08 | i965: fix incorrect test for vertex position attribute | Brian Paul |
2009-09-04 | i965: Fix warnings in intel_pixel_read.c. | Eric Anholt |
2009-09-04 | intel: Also get the DRI2 front buffer when doing front buffer reading. | Eric Anholt |
2009-09-04 | intel: Update Mesa state before span setup in glReadPixels. | Eric Anholt |
2009-09-04 | intel: Move intel_pixel_read.c to shared for use with i965. | Eric Anholt |
2009-09-04 | i965: Add missing state dependency of sf_unit on _NEW_BUFFERS. | Eric Anholt |
2009-09-04 | intel: Align cubemap texture height to its padding requirements. | Eric Anholt |
2009-09-04 | intel: Align untiled region height to 2 according to 965 docs. | Eric Anholt |
2009-09-04 | i965: Fix source depth reg setting for FSes reading and writing to depth. | Eric Anholt |
2009-09-04 | i965: Respect CondSwizzle in OPCODE_IF. | Eric Anholt |
2009-09-04 | i965: asst clean-ups, etc in brw_vs_emit() | Brian Paul |
2009-09-04 | i965: Emit conditional code updates as required for GLSL VS if statements. | Eric Anholt |
2009-09-04 | i965: Spell "conditional" correctly. | Eric Anholt |
2009-09-04 | i965: Fix RECT shadow sampling by not losing the other texcoords. | Eric Anholt |
2009-09-04 | i965: Assert that the offset in the VBO is below the VBO size. | Eric Anholt |
2009-09-04 | i965: Even if no VS inputs are set, still load some amount of URB as required. | Eric Anholt |