Age | Commit message (Collapse) | Author |
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This is good for about 5% on ipers on 965, and should help any cpu-bound app.
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Mapping and unmapping buffers is expensive, and having the map around isn't
harmful (other than consuming address space). So, once mapped, just leave
buffers mapped in case they get re-used.
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Add both MI_FLUSH and intel_batchbuffer_flush to intelEmitCopyBlit.
This ensures that the data are flushed *and* the gem kernel driver sees the
various memory domain transitions.
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Use the new DRM_IOCTL_I915_GEM_BUSY ioctl to detect
idle buffers for re-use.
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We don't need an MI_FLUSH there, because everything that's been flushed in the
batch will eventually hit the hardware.
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Otherwise, since the MI_FLUSH at the end of every batch had been removed,
non-automatic-flushing chips (965) wouldn't get flushed and apps with static
rendering would get partial screen contents until the server's blockhandler
flush kicked in.
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The right solution would probably be keeping a list of regions which have been
rendered to.
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The write_domain needs to be set after any batch buffer uses an object,
track when that happens in the new 'cpu_domain_set' field.
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Only a few relocations are typically used, so don't clear the
whole thing.
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This avoids kernel relocations for most batchbuffer relocs.
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Track DRM GEM name changes.
Add driver hooks for bo_subdata and bo_get_subdata so that GEM can use pread
and pwrite.
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Fix the kernel API to place the read/write domain information in the
relocation instead of the buffer.
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Make sure 'used' tracks the right value through the whole function.
Also, use GLint for intel_batchbuffer_space in case we do bad things
in the future.
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This existed to get the icache flushed. However, GEM handles this for us
now for sure, and we had disabled it prematurely anyway.
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The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
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Doesn't deal with local modifications yet (need new kernel set_domain ioctl
for that to work). Also, guesses what domains are affected based on the
read/write bits set in the flags. Works for 915, probably not so much for
965.
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Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
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small integers are much prettier, and let me correlate to DRM debug output.
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This is just cosmetic, to produce less scary values when the ioctl fails and
doesn't return values there.
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Instead of attempting to fix these for GEM, just disable until GEM is
working.
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(And fix a nearby whitespace nit)
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Fencing was used in two places: ensuring that we didn't get too many frames
ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on
buffers like we would do for CPU access on them. The "don't get too far ahead"
is now the responsibility of the execution manager (kernel).
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Use floor() to convert to int (per Mark Kildard and the SI).
Also, change translate_id() to return a signed integer since we may be
offsetting from GL_LIST_BASE.
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GL_REPLACE_EXT comes from the ancient GL_EXT_texture extension. Found an old demo that
actually uses it.
The values of the GL_REPLACE and GL_REPLACE_EXT tokens is different, unfortunately.
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Fixes problem with bitmaps jumping around by one pixel depending on window
size. The rasterpos is often X.9999 instead of X+1.
Run progs/redbook/drawf and resize window to check.
Cherry picked from gallium-0.1 branch
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The previous default these days served mostly to cause artifical problems with
GLX compositing managers like compiz (see e.g.
http://bugs.freedesktop.org/show_bug.cgi?id=10501).
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The 32-bit immediate value in the i965 instruction word must contain two
copies of any 16-bit constants. brw_imm_uw and brw_imm_w just needed to
copy the value into both halves of the immediate value instruction field.
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also clean header inclusion after code movement
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