Age | Commit message (Collapse) | Author |
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I removed the HiZ memory management, because the HiZ RAM is too small
and I also did it in hope that HiZ will be enabled more often.
This also sets aligned strides to HIZ_PITCH and ZMASK_PITCH.
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Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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should fix scons build.
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Plugs a memory leak when compiling shaders with user defined structures.
NOTE: This is a candidate for the 7.9 and 7.10 branches.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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It doesn't work.
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this just adds a format check + format conversion.
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This adds support for the RGTC unsigned and signed
texture storage and fetch methods.
the code is a port of the DXT5 alpha compression code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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We need this to do signed stuff for RGTC.
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So far I haven't implemented the u_format code for these.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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still can't get signed to work
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This reverts commit b6d40213935da702570eca2c0861bd4b1d7f5254.
This actually breaks gears here on my rv670.
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TRUNC is neither a scalar instruction nor exclusive to the Trans unit.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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Signed-off-by: Dave Airlie <airlied@redhat.com>
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With an extremely dumb strategy. But it's the same i915c employs.
Also improve the hw_atom code slightly by statically specifying the
required batch space. For extremely variably stuff (shaders, constants)
it would probably be better to add a new parameter to the hw_atom->validate
function.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Also contains the first few bits for hw state atoms.
v2: Implement suggestion by Jakob Bornecrantz.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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v2: Add the batch bo to the libdrm validation lost, for otherwise
libdrm won't take previously used buffers into account.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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These files can be decoded with intel_dump_decode from the intel-gpu-tools
available at:
http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Now also for the DRAW_RECT command
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Move it to i915_state_static.c This way i915_emit_state.c only emits
state and doesn't (re)calculate it.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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A copy and paste error.
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If another thread bound a context to the drawable then unbound it, the
driContextPriv would end up NULL.
With the previous two fixes, this fixes glx-multithread-makecurrent-2,
despite the issue not being about the multithreaded makecurrent.
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The driver only has one reasonable place to look for its context to
flush anything, which is the current context. Don't bother it with
having to check.
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The GLX Spec says you only implicitly glFlush if the drawable being
swapped is the current context's drawable.
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This extension allows a client to bind one context in multiple threads
simultaneously. It is then up to the client to manage synchronization of
access to the GL, just as normal multithreaded GL from multiple contexts
requires synchronization management to shared objects.
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Premature semicolon.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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valgrind gives me a warning with llvmpipe with profile builds but
not debug builds, this seems to fix the issue at least.
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Fixes bug #34346.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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The old code even falls apart for nr == 0 (which is caught earlier, but)!
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Fixes regression from a08e612fd8e7ca2ac2fef8961e56e5b094033717
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This adds the opcode and the code to convert ir_txd to OPCODE_TXD;
it doesn't actually add support yet.
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Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
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Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was
never handled.
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The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're
doing a non-bias texture lookup. It has the same value as the new constant
BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no
functional changes.
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From volume 4, page 161 of the public i965 documentation.
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There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa
due to ureg_src size, reshuffling the structure member to better better
alignment work around the issue.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893
7.9 + 7.10 candidate
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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7.9 & 7.10 candidate
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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