Age | Commit message (Collapse) | Author | |
---|---|---|---|
2009-06-22 | functions declaration with 'extern' | Cooper Yuan | |
2009-06-22 | Pass viewport id to r700SendViewportState function, otherwise the radom ↵ | Cooper Yuan | |
value may beyond R700_MAX_VIEWPORTS | |||
2009-06-22 | add LINK_STATES for SPI_PS and SEMANTIC | Cooper Yuan | |
2009-06-12 | Merge master and fix conflicts | Alex Deucher | |
2009-06-12 | Merge branch 'mesa_7_5_branch' | Jakob Bornecrantz | |
2009-06-12 | mesa: Enable uploads of only depth to z24s8 textures | Jakob Bornecrantz | |
2009-06-12 | Disable SGI_swap_control extension for DRI2 | Owen W. Taylor | |
We currently don't have support for SGI_swap_control for direct contexts with DRI2, so disable reporting the extension. Reporting the extension, and then having glXSwapIntervalSGI() "succeed" but do nothing can confuse applications. https://bugs.freedesktop.org/show_bug.cgi?id=22123 | |||
2009-06-12 | radeon: fix size of mipmap texture array | Dave Airlie | |
2009-06-12 | radeon/r200/r300: fix max texture levels assert | Dave Airlie | |
use the actual value set in the context | |||
2009-06-12 | Merge remote branch 'main/radeon-rewrite' | Dave Airlie | |
2009-06-11 | Add RV740 support | Alex Deucher | |
2009-06-11 | r300: fix VAP setup | Maciej Cencora | |
If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang. | |||
2009-06-11 | r300: fix for SW TCL path | Maciej Cencora | |
We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order. We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8. | |||
2009-06-11 | r300: don't send unused attributes for SW TCL path | Maciej Cencora | |
2009-06-11 | r300: send only RS_IP_* regs that we are going to use | Maciej Cencora | |
2009-06-11 | r300: fix RS setup when no colors and textures are sent to FP | Maciej Cencora | |
RS_COL_FMT field is part of RS_IP_* reg not RS_INST_* | |||
2009-06-11 | r300: r500 fragment program fixes | Maciej Cencora | |
- when rewriting per component negate swizzle, first instruction should get not negated source - KIL instruction ignores swizzles TODO: - tex instructions does not support saturation - tex instructions cannot read from consant memory | |||
2009-06-11 | radeon: increase max bo count | Maciej Cencora | |
2009-06-11 | r300: fix a GPU lock up | Maciej Cencora | |
Sending from VAP more texture coordinates than RS expects results in GPU hang. Fixes BumpSelfShadow from DirectX8 SDK. | |||
2009-06-11 | r300: fix vertex program bug | Maciej Cencora | |
If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements. Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests. | |||
2009-06-11 | r300: move some code for easier debugging | Maciej Cencora | |
2009-06-11 | r300: print vertex program when debugging is enabled | Maciej Cencora | |
2009-06-11 | r300: fix output register allocation for vertex shaders | Maciej Cencora | |
If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases. | |||
2009-06-11 | r300: hw doesn't support saturation for tex instructions | Maciej Cencora | |
2009-06-11 | mesa: rework vertex shader output / fragment shader input attribute matching | Brian Paul | |
Before, if a vertex shader's outputs didn't exactly match a fragment shader's inputs we could wind up with invalid TGSI shader declarations. For example: Before patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[0] <- note duplicate [0] DCL OUT[4], GENERIC[2] After patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2] | |||
2009-06-11 | mesa: add default function for ctx->Driver.CheckQuery() hook | Brian Paul | |
2009-06-11 | python/retrace: Show the contents of the depth/stencil and surfaces ↵ | José Fonseca | |
before/after transfers. | |||
2009-06-11 | python/retrace: Interpret is_texture_referenced/is_buffer_referenced. | José Fonseca | |
2009-06-11 | wgl: Fix prototype. | José Fonseca | |
2009-06-11 | Merge branch 'mesa_7_5_branch' | José Fonseca | |
2009-06-11 | mesa: Use new pf_is_depth_and_stencil inline. | José Fonseca | |
2009-06-11 | gallium: New pf_is_depth_and_stencil / pf_is_depth_or_stencil inlines. | José Fonseca | |
2009-06-11 | mesa: Use PIPE_TEXTURE_USAGE_DEPTH_STENCIL for any depth or stencil format. | José Fonseca | |
2009-06-11 | mesa: Remove dead code. | José Fonseca | |
2009-06-11 | st/mesa: fix typo s/BFC0/BFC1/ | Brian Paul | |
2009-06-11 | vbo: fix assertion, #define IMM_BUFFER_NAME | Brian Paul | |
This was sometimes seen when Glean exited upon test failure when using Gallium. | |||
2009-06-11 | Merge branch 'mesa_7_5_branch' | José Fonseca | |
Conflicts: src/mesa/state_tracker/st_cb_fbo.c src/mesa/state_tracker/st_framebuffer.c | |||
2009-06-11 | python/tests: Test sampling from a depth texture. | José Fonseca | |
2009-06-11 | mesa: Only do read write when we don't have a depth value to write | Jakob Bornecrantz | |
2009-06-11 | mesa: Take the format from the right structure. | José Fonseca | |
2009-06-11 | meas: Use a read/write transfer when writing stencil component, but not ↵ | José Fonseca | |
touching the depth component. | |||
2009-06-11 | r300: fix indexed primitive rendering when using memory manager | Jerome Glisse | |
2009-06-11 | Properly set aos_count | Alex Deucher | |
This is used by radeonReleaseArrays to free AOS. | |||
2009-06-11 | dri st: Don't require the PIPE_TEXTURE_USAGE_RENDER_TARGET property for ↵ | Thomas Hellstrom | |
depth- and stencil renderbuffers. Signed-off-by: Thomas Hellstrom <thellstrom-at-vmware-dot-com> | |||
2009-06-11 | intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL. | Michel Dänzer | |
Fixes glean depthStencil test. | |||
2009-06-10 | move radeon_set_screen_flags() up so CHIP_FAMILY is set before using it | Alex Deucher | |
fixes last commit. | |||
2009-06-10 | Use correct scratch reg offset for r6xx/r7xx | Alex Deucher | |
2009-06-10 | mesa: Reverse s8z24 into z24s8 as required by EXT_packed_depth_stencil. | José Fonseca | |
Actually, after spotting this problem, I realized this is unreachable code. However don't bother to enable this fast path now, given the normal path is working just fine. | |||
2009-06-10 | mesa: Fix typo in bitmask. | José Fonseca | |
2009-06-10 | mesa: Fix draw_stencil_pixels for PIPE_FORMAT_Z24S8_UNORM. | José Fonseca | |
Reversed component order. This fixes glean depthStencil test failures for PIPE_FORMAT_Z24S8_UNORM visuals. |