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this sets the stencil up for evergreen properly.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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https://bugs.freedesktop.org/show_bug.cgi?id=30632
NOTE: this is a candidate for the 7.9 branch.
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Since flush rework there could be only one relocation per
register in a block.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Got a speed up by tracking the dirty blocks in a seperate list instead of looping through all blocks. This version should work with block that get their dirty state disabled again and I added a dirty check during the flush as some blocks were already dirty.
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Flush read cache before writting register. Track flushing inside
of a same cs and avoid reflushing same bo if not necessary. Allmost
properly force flush if bo rendered too and then use as a texture
in same cs (missing pipeline flush dunno if it's needed or not).
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Allow fast lookup of relocation information & id which
was a CPU time consumming operation.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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we weren't decreasing when removing from the list.
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if we know the bo has gone not busy, no need to add another bo wait
thanks to Andre (taiu) on irc for pointing this out.
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since we plan on using dx10 constant buffers everywhere.
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we don't use this since constant buffers are now being used on all gpus.
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When we go to do a lot of bos in one draw like constant bufs we need
to avoid bouncing off the busy ioctl, this mitigates by backing off
on busy bos for a short amount of times.
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If we assume busy buffers are added to the list in order its unlikely
we'd fine one after the first busy one that isn't busy.
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this just keeps a list of bos submitted together, and uses them to decide
bo busy state for the whole group.
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NOTE: this is a candidate for the 7.9 branch.
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These texture formats (like R16G16B16A16_UNORM) were untested until now
because st/mesa doesn't use them. I am testing this with a hacked st/mesa
here.
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This uses message headers for now, since we'll need it for MRT. We
can cut out the header later.
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It instead sensibly appears in the src0 slot.
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We could try to detect this in expression handling and do it
proactively there, but it seems like less logic to do it in one
optional pass at the end.
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The glsl core should be handling most dead code issues for us, but we
generate some things in codegen that may not get used, like the 1/w
value or pixel deltas. It seems a lot easier this way than trying to
work out up front whether we're going to use those values or not.
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This also means that our intervals now highlight dead code.
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Add bo offset everywhere needed if r600_bo is ever a sub bo
of a bigger bo.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
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From AROS.
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no wonder it was slow, the code is deliberately forcing stuff into GTT,
we used to have domain management but it seems to have disappeared.
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this code was memcmp'ing two structs, but refcounting one of them afterwards,
so any subsequent memcmp was never going to work.
again this stops unnecessary uploads of vertex program,
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this function was taking quite a lot of pointless CPU.
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Easy enough patch, who needs a full test run. Oh, that's right. Me.
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The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't
apply to shadow compares, which always return an intensity value. The
texture swizzles can do the job for us.
Fixes:
glsl1-shadow2D(): 1
glsl1-shadow2D(): 3
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Blending with DST_ALPHA is undefined. SRC_ALPHA works, though.
I bet some other formats have similar limitations too.
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The hw swizzles have been obtained by a brute force approach,
and only C0 and C2 are stored in UV88, the other channels are
ignored.
R16G16 is going to be a lot trickier.
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passes all piglit RG tests with softpipe.
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FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
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Luckily, one of them would result in failing out register allocation
when the other bugs were encountered. Applies to
glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still
fails register allocation, but now legitimately.
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This quickly cuts 8% of the instructions in my glsl demo.
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By doing so using the register allocator now, we avoid wasting a
register to make the alignment happen.
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Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=30551
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Fixes this GCC warning.
r600_shader.c: In function 'tgsi_split_literal_constant':
r600_shader.c:818: warning: unused variable 'index'
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