| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-11-05 | draw: Implement TGSI_OPCODE_TRUNC. | michal | |
| 2008-11-05 | tgsi: Implement OPCODE_TRUNC. | michal | |
| 2008-11-05 | Merge commit 'origin/master' into gallium-0.2 | Alan Hourihane | |
| 2008-11-04 | mesa: fix float-valued GLSL vertex attribute variables | Brian Paul | |
| The swizzle mask for such variables wasn't set up properly. | |||
| 2008-11-03 | gallium: no renderbuffer, so just exit. | Alan Hourihane | |
| 2008-11-03 | gallium: Silence compiler warnings on Windows. | Michal Krol | |
| 2008-11-03 | gallium: Read from PIPE_FORMAT_Z32_FLOAT. | José Fonseca | |
| Mainly for debugging purposes for now. | |||
| 2008-11-03 | i965: Clean up stale NDC comment. | Eric Anholt | |
| 2008-11-03 | i965: Avoid vs header computation for negative rhw on G4X. | Eric Anholt | |
| This cuts one MOV out when setting a zero header. | |||
| 2008-11-03 | i965: Merge GM45 into the G4X chipset define. | Eric Anholt | |
| The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up. | |||
| 2008-11-03 | i965: Fix copy'n'paste issue that made brw->urb.constrained useless. | Eric Anholt | |
| Also, add a comment explaining what brw->urb.constrained tries to do. | |||
| 2008-11-03 | gallium: WinCE portability fixes. | José Fonseca | |
| 2008-11-03 | gallium: Fix typo. | José Fonseca | |
| 2008-11-03 | softpipe: Don't call pipe_buffer_destroy directly. | José Fonseca | |
| Use pipe_buffer_reference instead. | |||
| 2008-11-03 | pipebuffer: Ensure refcounts of live buffer objects are never zero. | José Fonseca | |
| 2008-11-03 | gallium: Ensure refcounts of live objects are never zero. | José Fonseca | |
| 2008-11-03 | gallium: Fix msvc warning. | José Fonseca | |
| 2008-11-02 | i965: Clean up stale NDC comment. | Eric Anholt | |
| 2008-11-02 | i965: Avoid vs header computation for negative rhw on G4X. | Eric Anholt | |
| This cuts one MOV out when setting a zero header. | |||
| 2008-11-02 | i965: Merge GM45 into the G4X chipset define. | Eric Anholt | |
| The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up. | |||
| 2008-11-02 | i965: Fix copy'n'paste issue that made brw->urb.constrained useless. | Eric Anholt | |
| Also, add a comment explaining what brw->urb.constrained tries to do. | |||
| 2008-11-01 | Merge commit 'origin/master' into gallium-0.2 | Alan Hourihane | |
| Conflicts: src/mesa/shader/slang/library/slang_vertex_builtin_gc.h | |||
| 2008-11-01 | mesa: silence warnings | Brian Paul | |
| 2008-11-01 | mesa: do scope replacement for while/for loops too | Brian Paul | |
| This fixes a function inlining bug involving vars declared inside loop bodies. | |||
| 2008-11-01 | mesa: glsl tree print improvements | Brian Paul | |
| 2008-11-01 | mesa: fix assignment / parameter passing of sampler types | Brian Paul | |
| 2008-11-01 | mesa: additional debug flags for glsl debug/disassembly | Brian Paul | |
| 2008-11-01 | Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1 | Keith Packard | |
| Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <keithp@keithp.com> | |||
| 2008-10-31 | mesa: fix some bugs with precision qualifier parsing | Brian Paul | |
| 2008-10-31 | mesa: do scope replacement for variable initializers too | Brian Paul | |
| 2008-10-31 | mesa: fix copy/paste error in GLSL error msg | Brian Paul | |
| 2008-10-31 | intel: pixelzoom doesn't apply to glBitmap, so disable the fallback. | Eric Anholt | |
| 2008-10-31 | intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX) | Eric Anholt | |
| GL_COLOR_INDEX mode is just like other normal formats (that is, not depth/stencil) and is uploaded fine by TexImage. | |||
| 2008-10-31 | intel: Add more fallback debugging for glDrawPixels. | Eric Anholt | |
| 2008-10-31 | i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions. | Gary Wong | |
| (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.) | |||
| 2008-10-31 | i965: support destination horiz strides in align1 access mode. | Gary Wong | |
| This is required for scatter writes in destination regions to work. | |||
| 2008-10-30 | CELL: fix use of stencil value mask | Robert Ellison | |
| The Cell stencil tests were completely ignoring the stencil value mask. Now the original code paths are still used if the stencil value mask is all 1s; but code to use the mask for the stencil value and reference value comparisons is now emitted if the mask is not all 1s. | |||
| 2008-10-31 | mesa: fix a typo in the previous commit | Xiang, Haihao | |
| 2008-10-30 | gallivm: replace the temp parameters of the JIT function with alloca'ed ↵ | Stephane Marchesin | |
| temps. This avoids useless writes of temporary results. | |||
| 2008-10-30 | cell: Protected use of non-initialized untile buffers | Jonathan White | |
| 2008-10-30 | CELL: stencil bug fixes | Robert Ellison | |
| Two definitive bugs in stenciling were fixed. The first, reversed registers in the generated Select Bytes (selb) instruction, caused the stenciling INCR and DECR operations to fail dramatically, putting new values in where old values were supposed to be and vice versa. The second caused stencil tiles to not be read and written from main memory by the SPUs. A per-spu flag, spu.read_depth, was used to indicate whether the SPU should be reading depth tiles, and was set only when depth was enabled. A second flag, spu.read_stencil, was set when stenciling was enabled, but never referenced. As stenciling and depth are in the same tiles on the Cell, and there is no corresponding TAG_WRITE_TILE_STENCIL to complement TAG_WRITE_TILE_COLOR and TAG_WRITE_TILE_Z, I fixed this by eliminating the unused "spu.read_stencil", renaming "spu.read_depth" to "spu.read_depth_stencil", and setting it if either stenciling or depth is enabled. I also added an optimization to the fragment ops generation code, that avoids calculating stencil values and/or stencil writemask when the stencil operations are all KEEP. | |||
| 2008-10-30 | cell: Added check for PIPE_FLUSH_RENDER_CACHE to cell_flush to fix black ↵ | Jonathan White | |
| blocks during st_readpixels due to a flush wait not happening in order to allow any previous rendering to complete. | |||
| 2008-10-30 | mesa: fix an issue in _mesa_PointParameterfv(). | Xiang, Haihao | |
| 2008-10-29 | gallium: grow SPE instruction buffer as needed | Brian Paul | |
| 2008-10-29 | gallium: no longer pass max_inst to ppc_init_func() | Brian Paul | |
| 2008-10-29 | gallium: use execmem for PPC code, grow instruction buffer as needed | Brian Paul | |
| 2008-10-29 | gallium: fix alignment parameter passed to u_mmAllocMem() | Brian Paul | |
| Was 32, now 5. The param is expressed as a power of two exponent. The net effect is that the alignment was a no-op on X86 but on PPC we always got the same memory address everytime rtasm_exec_malloc() was called. | |||
| 2008-10-29 | gallium: prefix memory manager functions with u_ to differentiate from ↵ | Brian Paul | |
| functions in mesa/main/mm.c | |||
| 2008-10-29 | gallium: test for PIPE_OS_LINUX instead of __linux__ | Brian Paul | |
| 2008-10-29 | cell: add scalar param to emit_function_call() to indicate scalar function calls | Brian Paul | |
| Scalar calls only use the X component of the src regs and smear the result across the dest register's X/Y/Z/W. | |||
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
| summaryrefslogtreecommitdiff |