From a48ee529a256611676884262ced218ad6c05f961 Mon Sep 17 00:00:00 2001
From: Marc Dietrich <marvin24@gmx.de>
Date: Mon, 31 Aug 2009 08:56:33 -0700
Subject: mesa: fix 32bit cross compilation on a 64bit machine

When cross compiling on a 64bit machine, gen_matypes.c is build
for the host machine (64bit) but must generates code for the target
machine (32bit). This causes wrong offsets all over the place and
crashes googleearth on my machine. Solution is to add -m32 when
cross compiling.

Attached patch is compatible with linux-x86-32 and autoconf based
builds.
---
 configure.ac          | 1 +
 src/mesa/x86/Makefile | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 8607ff17a3..63cc27eec9 100644
--- a/configure.ac
+++ b/configure.ac
@@ -121,6 +121,7 @@ AC_ARG_ENABLE([32-bit],
 if test "x$enable_32bit" = xyes; then
     if test "x$GCC" = xyes; then
         CFLAGS="$CFLAGS -m32"
+        ARCH_FLAGS="$ARCH_FLAGS -m32"
     fi
     if test "x$GXX" = xyes; then
         CXXFLAGS="$CXXFLAGS -m32"
diff --git a/src/mesa/x86/Makefile b/src/mesa/x86/Makefile
index aa49a9134a..69122c114b 100644
--- a/src/mesa/x86/Makefile
+++ b/src/mesa/x86/Makefile
@@ -21,7 +21,7 @@ clean:
 
 
 gen_matypes: gen_matypes.c
-	$(HOST_CC) $(INCLUDE_DIRS) $(HOST_CFLAGS) gen_matypes.c -o gen_matypes
+	$(HOST_CC) $(ARCH_FLAGS) $(INCLUDE_DIRS) $(HOST_CFLAGS) gen_matypes.c -o gen_matypes
 
 # need some special rules here, unfortunately
 matypes.h: ../main/mtypes.h ../tnl/t_context.h gen_matypes
-- 
cgit v1.2.3


From f7654faf16431d9749fa9f3a8720b4b7fc5c8445 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 31 Aug 2009 10:31:45 -0600
Subject: docs/: document cross-compile fix

---
 docs/relnotes-7.5.1.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes-7.5.1.html b/docs/relnotes-7.5.1.html
index df06302624..8ac2e632b2 100644
--- a/docs/relnotes-7.5.1.html
+++ b/docs/relnotes-7.5.1.html
@@ -54,6 +54,7 @@ tbd
 <li>Fixed Gallium glBitmap() Z position bug
 <li>Setting arrays of sampler uniforms did not work
 <li>Selection/Feedback mode didn't handle polygon culling correctly (bug 16866)
+<li>Fixed 32/64-bit cross compilation issue in gen_matypes.c
 </ul>
 
 
-- 
cgit v1.2.3


From 6bf86681f5903a06f98cc32ddf5715706de97c4a Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 31 Aug 2009 10:32:56 -0600
Subject: docs: fixed glXCreateGLXPixmap() for direct rendering

---
 docs/relnotes-7.5.1.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes-7.5.1.html b/docs/relnotes-7.5.1.html
index 8ac2e632b2..320e531e6d 100644
--- a/docs/relnotes-7.5.1.html
+++ b/docs/relnotes-7.5.1.html
@@ -55,6 +55,7 @@ tbd
 <li>Setting arrays of sampler uniforms did not work
 <li>Selection/Feedback mode didn't handle polygon culling correctly (bug 16866)
 <li>Fixed 32/64-bit cross compilation issue in gen_matypes.c
+<li>Fixed glXCreateGLXPixmap() for direct rendering.
 </ul>
 
 
-- 
cgit v1.2.3


From 2241665dc6d77a992edfc49a9d9d9ed8d1b52e60 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 31 Aug 2009 11:14:16 -0600
Subject: mesa: fix saturation logic in emit_texenv()

We need to clamp/saturate after each texenv stage, not just the last one.
Fixes glean texEnv failure for softpipe (and probably other fragment program-
based drivers).
---
 src/mesa/main/texenvprogram.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/texenvprogram.c b/src/mesa/main/texenvprogram.c
index 3ff30058ec..050a3a99fe 100644
--- a/src/mesa/main/texenvprogram.c
+++ b/src/mesa/main/texenvprogram.c
@@ -1097,7 +1097,7 @@ static struct ureg
 emit_texenv(struct texenv_fragment_program *p, GLuint unit)
 {
    struct state_key *key = p->state;
-   GLboolean saturate = (unit < p->last_tex_stage);
+   GLboolean saturate;
    GLuint rgb_shift, alpha_shift;
    struct ureg out, shift;
    struct ureg dest;
@@ -1125,6 +1125,11 @@ emit_texenv(struct texenv_fragment_program *p, GLuint unit)
       break;
    }
    
+   /* If we'll do rgb/alpha shifting don't saturate in emit_combine().
+    * We don't want to clamp twice.
+    */
+   saturate = !(rgb_shift || alpha_shift);
+
    /* If this is the very last calculation, emit direct to output reg:
     */
    if (key->separate_specular ||
@@ -1173,6 +1178,7 @@ emit_texenv(struct texenv_fragment_program *p, GLuint unit)
    /* Deal with the final shift:
     */
    if (alpha_shift || rgb_shift) {
+      saturate = GL_TRUE;  /* always saturate at this point */
       if (rgb_shift == alpha_shift) {
 	 shift = register_scalar_const(p, (GLfloat)(1<<rgb_shift));
       }
-- 
cgit v1.2.3


From 9f36473a8ecc9c3358ae99651f511725344f22cc Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 31 Aug 2009 11:17:59 -0600
Subject: mesa: added const qualifiers, move local var

---
 src/mesa/main/texenvprogram.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/mesa/main/texenvprogram.c b/src/mesa/main/texenvprogram.c
index 050a3a99fe..454d97506e 100644
--- a/src/mesa/main/texenvprogram.c
+++ b/src/mesa/main/texenvprogram.c
@@ -936,7 +936,7 @@ static struct ureg emit_combine_source( struct texenv_fragment_program *p,
    }
 }
 
-static GLboolean args_match( struct state_key *key, GLuint unit )
+static GLboolean args_match( const struct state_key *key, GLuint unit )
 {
    GLuint i, nr = key->unit[unit].NumArgsRGB;
 
@@ -1096,11 +1096,10 @@ static struct ureg emit_combine( struct texenv_fragment_program *p,
 static struct ureg
 emit_texenv(struct texenv_fragment_program *p, GLuint unit)
 {
-   struct state_key *key = p->state;
+   const struct state_key *key = p->state;
    GLboolean saturate;
    GLuint rgb_shift, alpha_shift;
-   struct ureg out, shift;
-   struct ureg dest;
+   struct ureg out, dest;
 
    if (!key->unit[unit].enabled) {
       return get_source(p, SRC_PREVIOUS, 0);
@@ -1152,7 +1151,6 @@ emit_texenv(struct texenv_fragment_program *p, GLuint unit)
    }
    else if (key->unit[unit].ModeRGB == MODE_DOT3_RGBA_EXT ||
 	    key->unit[unit].ModeRGB == MODE_DOT3_RGBA) {
-
       out = emit_combine( p, dest, WRITEMASK_XYZW, saturate,
 			  unit,
 			  key->unit[unit].NumArgsRGB,
@@ -1178,7 +1176,10 @@ emit_texenv(struct texenv_fragment_program *p, GLuint unit)
    /* Deal with the final shift:
     */
    if (alpha_shift || rgb_shift) {
+      struct ureg shift;
+
       saturate = GL_TRUE;  /* always saturate at this point */
+
       if (rgb_shift == alpha_shift) {
 	 shift = register_scalar_const(p, (GLfloat)(1<<rgb_shift));
       }
@@ -1278,7 +1279,7 @@ static GLboolean load_texenv_source( struct texenv_fragment_program *p,
 static GLboolean
 load_texunit_sources( struct texenv_fragment_program *p, int unit )
 {
-   struct state_key *key = p->state;
+   const struct state_key *key = p->state;
    GLuint i;
 
    for (i = 0; i < key->unit[unit].NumArgsRGB; i++) {
@@ -1298,7 +1299,7 @@ load_texunit_sources( struct texenv_fragment_program *p, int unit )
 static GLboolean
 load_texunit_bumpmap( struct texenv_fragment_program *p, int unit )
 {
-   struct state_key *key = p->state;
+   const struct state_key *key = p->state;
    GLuint bumpedUnitNr = key->unit[unit].OptRGB[1].Source - SRC_TEXTURE0;
    struct ureg texcDst, bumpMapRes;
    struct ureg constdudvcolor = register_const4f(p, 0.0, 0.0, 0.0, 1.0);
-- 
cgit v1.2.3


From fcf0804c05faefd196ed5525c068ee4cd30c5312 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 31 Aug 2009 13:28:31 -0600
Subject: swrast: can't use deferred texture/shading if using KIL instruction

If the fragment program uses KIL, we have to execute it before z/stencil
testing.  Otherwise, deferred texture/shading lets us skip shading for
pixels that fail z/stencil testing.
---
 src/mesa/swrast/s_context.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/swrast/s_context.c b/src/mesa/swrast/s_context.c
index e7c2ace32c..abf0008565 100644
--- a/src/mesa/swrast/s_context.c
+++ b/src/mesa/swrast/s_context.c
@@ -220,6 +220,9 @@ _swrast_update_deferred_texture(GLcontext *ctx)
          /* Z comes from fragment program/shader */
          swrast->_DeferredTexture = GL_FALSE;
       }
+      else if (fprog && fprog->UsesKill) {
+         swrast->_DeferredTexture = GL_FALSE;
+      }
       else if (ctx->Query.CurrentOcclusionObject) {
          /* occlusion query depends on shader discard/kill results */
          swrast->_DeferredTexture = GL_FALSE;
-- 
cgit v1.2.3


From 3f785080db33d437893564dded325452770699be Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Mon, 31 Aug 2009 17:54:46 -0600
Subject: swrast: fix selection/feedback regression

This fixes a conform selection/feedback regression introduced by commit
8f4d66c5f893b49eb3973aa3b31a856314c045c7
---
 src/mesa/swrast/s_triangle.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/swrast/s_triangle.c b/src/mesa/swrast/s_triangle.c
index 1d2fed7169..1ab0e19f92 100644
--- a/src/mesa/swrast/s_triangle.c
+++ b/src/mesa/swrast/s_triangle.c
@@ -61,7 +61,7 @@ _swrast_culltriangle( GLcontext *ctx,
    GLfloat fy = v2->attrib[FRAG_ATTRIB_WPOS][1] - v0->attrib[FRAG_ATTRIB_WPOS][1];
    GLfloat c = ex*fy-ey*fx;
 
-   if (c * swrast->_BackfaceSign * swrast->_BackfaceCullSign < 0.0F)
+   if (c * swrast->_BackfaceSign * swrast->_BackfaceCullSign <= 0.0F)
       return GL_FALSE;
 
    return GL_TRUE;
-- 
cgit v1.2.3


From d9b7d7875b0c114d2fa4956b2bffbe809e5b5a44 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 1 Sep 2009 08:53:31 -0600
Subject: progs/tests: re-enable exit() call

See bug 21267.
---
 progs/tests/fbotest1.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/progs/tests/fbotest1.c b/progs/tests/fbotest1.c
index 8dac21494e..0cd7f95c35 100644
--- a/progs/tests/fbotest1.c
+++ b/progs/tests/fbotest1.c
@@ -127,7 +127,7 @@ Init( void )
 
    if (!glutExtensionSupported("GL_EXT_framebuffer_object")) {
       printf("GL_EXT_framebuffer_object not found!\n");
-      /*exit(0);*/
+      exit(0);
    }
    printf("GL_RENDERER = %s\n", (char *) glGetString(GL_RENDERER));
 
-- 
cgit v1.2.3


From 1d7a989b104f02042fadfeec5bd20654bbb6fea6 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Tue, 1 Sep 2009 11:11:28 +0100
Subject: draw: remove unused variable

---
 src/gallium/auxiliary/draw/draw_pipe.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/auxiliary/draw/draw_pipe.c b/src/gallium/auxiliary/draw/draw_pipe.c
index be2f0f27f2..3cfae2de83 100644
--- a/src/gallium/auxiliary/draw/draw_pipe.c
+++ b/src/gallium/auxiliary/draw/draw_pipe.c
@@ -232,7 +232,6 @@ void draw_pipeline_run( struct draw_context *draw,
                         unsigned count )
 {
    char *verts = (char *)vertices;
-   unsigned i;
 
    draw->pipeline.verts = verts;
    draw->pipeline.vertex_stride = stride;
-- 
cgit v1.2.3


From de343680a3e6b2a588f8b3c844828b8d9e6cb6a5 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Wed, 2 Sep 2009 17:58:52 +0100
Subject: util: add version of u_blit_pixels which takes a writemask

Values outside the writemask are set in the destination to {0,0,0,1}
---
 src/gallium/auxiliary/util/u_blit.c           | 55 ++++++++++++++++++++-------
 src/gallium/auxiliary/util/u_blit.h           | 11 ++++++
 src/gallium/auxiliary/util/u_simple_shaders.c | 45 +++++++++++++++++++++-
 src/gallium/auxiliary/util/u_simple_shaders.h |  4 ++
 4 files changed, 100 insertions(+), 15 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_blit.c b/src/gallium/auxiliary/util/u_blit.c
index cda6dbd46d..c516317d70 100644
--- a/src/gallium/auxiliary/util/u_blit.c
+++ b/src/gallium/auxiliary/util/u_blit.c
@@ -62,7 +62,7 @@ struct blit_state
    struct pipe_viewport_state viewport;
 
    void *vs;
-   void *fs;
+   void *fs[TGSI_WRITEMASK_XYZW + 1];
 
    struct pipe_buffer *vbuf;  /**< quad vertices */
    unsigned vbuf_slot;
@@ -125,7 +125,7 @@ util_create_blit(struct pipe_context *pipe, struct cso_context *cso)
    }
 
    /* fragment shader */
-   ctx->fs = util_make_fragment_tex_shader(pipe);
+   ctx->fs[TGSI_WRITEMASK_XYZW] = util_make_fragment_tex_shader(pipe);
    ctx->vbuf = NULL;
 
    /* init vertex data that doesn't change */
@@ -146,9 +146,13 @@ void
 util_destroy_blit(struct blit_state *ctx)
 {
    struct pipe_context *pipe = ctx->pipe;
+   unsigned i;
 
    pipe->delete_vs_state(pipe, ctx->vs);
-   pipe->delete_fs_state(pipe, ctx->fs);
+
+   for (i = 0; i < Elements(ctx->fs); i++)
+      if (ctx->fs[i])
+         pipe->delete_fs_state(pipe, ctx->fs[i]);
 
    pipe_buffer_reference(&ctx->vbuf, NULL);
 
@@ -299,14 +303,15 @@ regions_overlap(int srcX0, int srcY0,
  * XXX need some control over blitting Z and/or stencil.
  */
 void
-util_blit_pixels(struct blit_state *ctx,
-                 struct pipe_surface *src,
-                 int srcX0, int srcY0,
-                 int srcX1, int srcY1,
-                 struct pipe_surface *dst,
-                 int dstX0, int dstY0,
-                 int dstX1, int dstY1,
-                 float z, uint filter)
+util_blit_pixels_writemask(struct blit_state *ctx,
+                           struct pipe_surface *src,
+                           int srcX0, int srcY0,
+                           int srcX1, int srcY1,
+                           struct pipe_surface *dst,
+                           int dstX0, int dstY0,
+                           int dstX1, int dstY1,
+                           float z, uint filter,
+                           uint writemask)
 {
    struct pipe_context *pipe = ctx->pipe;
    struct pipe_screen *screen = pipe->screen;
@@ -426,8 +431,11 @@ util_blit_pixels(struct blit_state *ctx,
    /* texture */
    cso_set_sampler_textures(ctx->cso, 1, &tex);
 
+   if (ctx->fs[writemask] == NULL)
+      ctx->fs[writemask] = util_make_fragment_tex_shader_writemask(pipe, writemask);
+
    /* shaders */
-   cso_set_fragment_shader_handle(ctx->cso, ctx->fs);
+   cso_set_fragment_shader_handle(ctx->cso, ctx->fs[writemask]);
    cso_set_vertex_shader_handle(ctx->cso, ctx->vs);
 
    /* drawing dest */
@@ -462,6 +470,27 @@ util_blit_pixels(struct blit_state *ctx,
 }
 
 
+void
+util_blit_pixels(struct blit_state *ctx,
+                 struct pipe_surface *src,
+                 int srcX0, int srcY0,
+                 int srcX1, int srcY1,
+                 struct pipe_surface *dst,
+                 int dstX0, int dstY0,
+                 int dstX1, int dstY1,
+                 float z, uint filter )
+{
+   util_blit_pixels_writemask( ctx, src, 
+                               srcX0, srcY0,
+                               srcX1, srcY1,
+                               dst,
+                               dstX0, dstY0,
+                               dstX1, dstY1,
+                               z, filter,
+                               TGSI_WRITEMASK_XYZW );
+}
+
+
 /* Release vertex buffer at end of frame to avoid synchronous
  * rendering.
  */
@@ -535,7 +564,7 @@ util_blit_pixels_tex(struct blit_state *ctx,
    cso_set_sampler_textures(ctx->cso, 1, &tex);
 
    /* shaders */
-   cso_set_fragment_shader_handle(ctx->cso, ctx->fs);
+   cso_set_fragment_shader_handle(ctx->cso, ctx->fs[TGSI_WRITEMASK_XYZW]);
    cso_set_vertex_shader_handle(ctx->cso, ctx->vs);
 
    /* drawing dest */
diff --git a/src/gallium/auxiliary/util/u_blit.h b/src/gallium/auxiliary/util/u_blit.h
index c35beceda8..a102021529 100644
--- a/src/gallium/auxiliary/util/u_blit.h
+++ b/src/gallium/auxiliary/util/u_blit.h
@@ -60,6 +60,17 @@ util_blit_pixels(struct blit_state *ctx,
                  int dstX1, int dstY1,
                  float z, uint filter);
 
+void
+util_blit_pixels_writemask(struct blit_state *ctx,
+                           struct pipe_surface *src,
+                           int srcX0, int srcY0,
+                           int srcX1, int srcY1,
+                           struct pipe_surface *dst,
+                           int dstX0, int dstY0,
+                           int dstX1, int dstY1,
+                           float z, uint filter,
+                           uint writemask);
+
 extern void
 util_blit_pixels_tex(struct blit_state *ctx,
                      struct pipe_texture *tex,
diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c b/src/gallium/auxiliary/util/u_simple_shaders.c
index e519c354d2..acc5b83c62 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@ -152,11 +152,14 @@ util_make_vertex_passthrough_shader(struct pipe_context *pipe,
 
 /**
  * Make simple fragment texture shader:
- *  TEX OUT[0], IN[0], SAMP[0], 2D;
+ *  IMM {0,0,0,1}                         // (if writemask != 0xf)
+ *  MOV OUT[0], IMM[0]                    // (if writemask != 0xf)
+ *  TEX OUT[0].writemask, IN[0], SAMP[0], 2D;
  *  END;
  */
 void *
-util_make_fragment_tex_shader(struct pipe_context *pipe)
+util_make_fragment_tex_shader_writemask(struct pipe_context *pipe,
+                                        unsigned writemask )
 {
    struct pipe_shader_state shader;
    struct tgsi_token tokens[100];
@@ -217,12 +220,43 @@ util_make_fragment_tex_shader(struct pipe_context *pipe)
                                      header,
                                      Elements(tokens) - ti);
 
+
+   if (writemask != TGSI_WRITEMASK_XYZW) {
+      struct tgsi_full_immediate imm;
+      static const float value[4] = { 0, 0, 0, 1 };
+
+      imm = tgsi_default_full_immediate();
+      imm.Immediate.NrTokens += 4;
+      imm.Immediate.DataType = TGSI_IMM_FLOAT32;
+      imm.u.Pointer = value;
+
+      ti += tgsi_build_full_immediate(&imm,
+                                      &tokens[ti],
+                                      header,
+                                      Elements(tokens) - ti );
+
+      /* MOV instruction */
+      inst = tgsi_default_full_instruction();
+      inst.Instruction.Opcode = TGSI_OPCODE_MOV;
+      inst.Instruction.NumDstRegs = 1;
+      inst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
+      inst.FullDstRegisters[0].DstRegister.Index = 0;
+      inst.Instruction.NumSrcRegs = 1;
+      inst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_IMMEDIATE;
+      inst.FullSrcRegisters[0].SrcRegister.Index = 0;
+      ti += tgsi_build_full_instruction(&inst,
+                                        &tokens[ti],
+                                        header,
+                                        Elements(tokens) - ti );
+   }
+
    /* TEX instruction */
    inst = tgsi_default_full_instruction();
    inst.Instruction.Opcode = TGSI_OPCODE_TEX;
    inst.Instruction.NumDstRegs = 1;
    inst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
    inst.FullDstRegisters[0].DstRegister.Index = 0;
+   inst.FullDstRegisters[0].DstRegister.WriteMask = writemask;
    inst.Instruction.NumSrcRegs = 2;
    inst.InstructionExtTexture.Texture = TGSI_TEXTURE_2D;
    inst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
@@ -253,6 +287,13 @@ util_make_fragment_tex_shader(struct pipe_context *pipe)
    return pipe->create_fs_state(pipe, &shader);
 }
 
+void *
+util_make_fragment_tex_shader(struct pipe_context *pipe )
+{
+   return util_make_fragment_tex_shader_writemask( pipe,
+                                                   TGSI_WRITEMASK_XYZW );
+}
+
 
 
 
diff --git a/src/gallium/auxiliary/util/u_simple_shaders.h b/src/gallium/auxiliary/util/u_simple_shaders.h
index 6f8d96af9b..d2e80d6eb4 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.h
+++ b/src/gallium/auxiliary/util/u_simple_shaders.h
@@ -49,6 +49,10 @@ util_make_vertex_passthrough_shader(struct pipe_context *pipe,
                                     const uint *semantic_indexes);
 
 
+extern void *
+util_make_fragment_tex_shader_writemask(struct pipe_context *pipe, 
+                                        unsigned writemask );
+
 extern void *
 util_make_fragment_tex_shader(struct pipe_context *pipe);
 
-- 
cgit v1.2.3


From e79054cc4090a2be346236236c9e18ae85cad43d Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Wed, 2 Sep 2009 18:30:11 +0100
Subject: st/mesa: Do GL_RGBA->GL_RGB texsubimage on hardware

State tracker currently backs GL_RGB textures with RGBA almost always.
This means we need to maintain A==1 in these textures to give correct GL_RGB
sampling results.

This change offloads the RGBA->RGB copy to hardware using the new writemask
version of u_blit_pixels.

More src/dstLogical/dstActual triples could be shifted to hardware by
this technique in future patches.
---
 src/mesa/state_tracker/st_cb_texture.c | 65 ++++++++++++++++++++++++++--------
 1 file changed, 51 insertions(+), 14 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c
index ee71c012c6..2d37d24ea8 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -56,6 +56,7 @@
 #include "pipe/p_context.h"
 #include "pipe/p_defines.h"
 #include "pipe/p_inlines.h"
+#include "pipe/p_shader_tokens.h"
 #include "util/u_tile.h"
 #include "util/u_blit.h"
 #include "util/u_surface.h"
@@ -1396,6 +1397,36 @@ fallback_copy_texsubimage(GLcontext *ctx, GLenum target, GLint level,
 }
 
 
+static unsigned
+compatible_src_dst_formats(const struct gl_renderbuffer *src,
+                           const struct gl_texture_image *dst)
+{
+   const GLenum srcFormat = src->_BaseFormat;
+   const GLenum dstLogicalFormat = dst->_BaseFormat;
+
+   if (srcFormat == dstLogicalFormat) {
+      /* This is the same as matching_base_formats, which should
+       * always pass, as it did previously.
+       */
+      return TGSI_WRITEMASK_XYZW;
+   }
+   else if (srcFormat == GL_RGBA &&
+            dstLogicalFormat == GL_RGB) {
+      /* Add a single special case to cope with RGBA->RGB transfers,
+       * setting A to 1.0 to cope with situations where the RGB
+       * destination is actually stored as RGBA.
+       */
+      return TGSI_WRITEMASK_XYZ; /* A ==> 1.0 */
+   }
+   else {
+      /* Otherwise fail.
+       */
+      return 0;
+   }
+}
+
+
+
 /**
  * Do a CopyTex[Sub]Image1/2/3D() using a hardware (blit) path if possible.
  * Note that the region to copy has already been clipped so we know we
@@ -1425,6 +1456,9 @@ st_copy_texsubimage(GLcontext *ctx,
    enum pipe_format dest_format, src_format;
    GLboolean use_fallback = GL_TRUE;
    GLboolean matching_base_formats;
+   GLuint format_writemask;
+   struct pipe_surface *dest_surface = NULL;
+   GLboolean do_flip = (st_fb_orientation(ctx->ReadBuffer) == Y_0_TOP);
 
    /* any rendering in progress must flushed before we grab the fb image */
    st_flush(ctx->st, PIPE_FLUSH_RENDER_CACHE, NULL);
@@ -1495,13 +1529,14 @@ st_copy_texsubimage(GLcontext *ctx,
     * textured-quad paths.
     */
    matching_base_formats = (strb->Base._BaseFormat == texImage->_BaseFormat);
+   format_writemask = compatible_src_dst_formats(&strb->Base, texImage);
 
-   if (matching_base_formats && ctx->_ImageTransferState == 0x0) {
-      /* try potential hardware path */
-      struct pipe_surface *dest_surface = NULL;
-      boolean do_flip = (st_fb_orientation(ctx->ReadBuffer) == Y_0_TOP);
+   if (ctx->_ImageTransferState == 0x0) {
 
-      if (src_format == dest_format && !do_flip) {
+      if (matching_base_formats && 
+          src_format == dest_format &&
+          !do_flip) 
+      {
          /* use surface_copy() / blit */
 
          dest_surface = screen->get_tex_surface(screen, stImage->pt,
@@ -1521,7 +1556,8 @@ st_copy_texsubimage(GLcontext *ctx,
                             width, height);
          use_fallback = GL_FALSE;
       }
-      else if (screen->is_format_supported(screen, src_format,
+      else if (format_writemask &&
+               screen->is_format_supported(screen, src_format,
                                            PIPE_TEXTURE_2D, 
                                            PIPE_TEXTURE_USAGE_SAMPLER,
                                            0) &&
@@ -1545,14 +1581,15 @@ st_copy_texsubimage(GLcontext *ctx,
             srcY0 = srcY;
             srcY1 = srcY0 + height;
          }
-         util_blit_pixels(ctx->st->blit,
-                          strb->surface,
-                          srcX, srcY0,
-                          srcX + width, srcY1,
-                          dest_surface,
-                          destX, destY,
-                          destX + width, destY + height,
-                          0.0, PIPE_TEX_MIPFILTER_NEAREST);
+         util_blit_pixels_writemask(ctx->st->blit,
+                                    strb->surface,
+                                    srcX, srcY0,
+                                    srcX + width, srcY1,
+                                    dest_surface,
+                                    destX, destY,
+                                    destX + width, destY + height,
+                                    0.0, PIPE_TEX_MIPFILTER_NEAREST,
+                                    format_writemask);
          use_fallback = GL_FALSE;
       }
 
-- 
cgit v1.2.3


From c3a0624ef01c3b347ed8a9fd3bab578b52bd9130 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 14:39:53 -0600
Subject: st/mesa: fix glCopyPixels(GL_STENCIL_INDEX) inverted position

If the renderbuffer orientation is Y=0=TOP we need to invert the dstY
position.
---
 src/mesa/state_tracker/st_cb_drawpixels.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c b/src/mesa/state_tracker/st_cb_drawpixels.c
index 8b5094a04f..adb349c1f1 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -842,6 +842,10 @@ copy_stencil_pixels(GLcontext *ctx, GLint srcx, GLint srcy,
    else
       usage = PIPE_TRANSFER_WRITE;
    
+   if (st_fb_orientation(ctx->DrawBuffer) == Y_0_TOP) {
+      dsty = rbDraw->Base.Height - dsty - height;
+   }
+
    ptDraw = st_cond_flush_get_tex_transfer(st_context(ctx),
 					   rbDraw->texture, 0, 0, 0,
 					   usage, dstx, dsty,
-- 
cgit v1.2.3


From 47df7900fd37f71bca0f3c4ae19d98866023a6c3 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 14:56:50 -0600
Subject: docs: move SGI GLU link

---
 docs/contents.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/contents.html b/docs/contents.html
index 1dca3a228d..d15e6c1e33 100644
--- a/docs/contents.html
+++ b/docs/contents.html
@@ -39,7 +39,6 @@ a:visited {
 <ul>
 <li><a href="download.html" target="MainFrame">Downloading / Unpacking</a>
 <li><a href="install.html" target="MainFrame">Compiling / Installing</a>
-<li><a href="glu.html" target="MainFrame">SGI's GLU</a>
 <li><a href="precompiled.html" target="MainFrame">Precompiled Libraries</a>
 </ul>
 
@@ -68,6 +67,7 @@ a:visited {
 <li><a href="repository.html" target="MainFrame">Source Code Repository</a>
 <li><a href="memory.html" target="MainFrame">DRI Memory Management</a>
 <li><a href="shading.html" target="MainFrame">Shading Language</a>
+<li><a href="glu.html" target="MainFrame">SGI's GLU</a>
 <li><a href="utilities.html" target="MainFrame">Utilities</a>
 <li><a href="helpwanted.html" target="MainFrame">Help Wanted</a>
 <li><a href="devinfo.html" target="MainFrame">Development Notes</a>
-- 
cgit v1.2.3


From ccb081414ba46a6e2d29bcc3c675e875717a8165 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 14:57:04 -0600
Subject: docs: update precompiled libs info

---
 docs/precompiled.html | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/docs/precompiled.html b/docs/precompiled.html
index 166d33d828..50cb2af60d 100644
--- a/docs/precompiled.html
+++ b/docs/precompiled.html
@@ -9,17 +9,11 @@
 <H1>Precompiled Libraries</H1>
 
 <p>
-In general, precompiled libraries are not available.
-However, people occasionally prepare packages of precompiled libraries
-for some systems.
+In general, precompiled Mesa libraries are not available.
 </p>
-
-<H2>Mesa-6.0 for Solaris</H2>
-
 <p>
-Steve Christensen has submitted precompiled Mesa-6.0 libraries for
-Solaris at <a href="http://sunfreeware.com/" target="_parent">
-sunfreeware.com</a>.
+However, some Linux distros (such as Ubuntu) seem to closely track
+Mesa and often have the latest Mesa release available as an update.
 </p>
 
 </BODY>
-- 
cgit v1.2.3


From 08575509e4d3ac152ebf18a6dc944f233d9a62b0 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 14:57:16 -0600
Subject: docs: added news entry for 7.5.1

---
 docs/news.html | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/docs/news.html b/docs/news.html
index 712ecedc10..07ad42ed49 100644
--- a/docs/news.html
+++ b/docs/news.html
@@ -11,6 +11,13 @@
 <H1>News</H1>
 
 
+<h2>September 3, 2009</h2>
+<p>
+<a href="relnotes-7.5.1.html">Mesa 7.5.1</a> is released.
+This is a bug-fix release which fixes bugs found in version 7.5.
+</p>
+
+
 <h2>July 17, 2009</h2>
 <p>
 <a href="relnotes-7.5.html">Mesa 7.5</a> is released.
-- 
cgit v1.2.3


From 0b4e835b13fb240f9c8f9fdc994cb80b99265845 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 14:57:30 -0600
Subject: docs: prep for 7.5.1 release

---
 docs/relnotes-7.5.1.html | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/docs/relnotes-7.5.1.html b/docs/relnotes-7.5.1.html
index 320e531e6d..c65fb85e27 100644
--- a/docs/relnotes-7.5.1.html
+++ b/docs/relnotes-7.5.1.html
@@ -8,7 +8,7 @@
 
 <body bgcolor="#eeeeee">
 
-<H1>Mesa 7.5.1 Release Notes / (date TBD)</H1>
+<H1>Mesa 7.5.1 Release Notes, 3 September 2009</H1>
 
 <p>
 Mesa 7.5.1 is a bug-fix release fixing issues found since the 7.5 release.
@@ -56,12 +56,9 @@ tbd
 <li>Selection/Feedback mode didn't handle polygon culling correctly (bug 16866)
 <li>Fixed 32/64-bit cross compilation issue in gen_matypes.c
 <li>Fixed glXCreateGLXPixmap() for direct rendering.
+<li>Fixed Gallium glCopyPixels(GL_STENCIL_INDEX) mispositioned image bug.
 </ul>
 
 
-<h2>Changes</h2>
-<ul>
-</ul>
-
 </body>
 </html>
-- 
cgit v1.2.3


From 67c286d20e6f1256950d81aab3f6b54cd4926602 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 15:04:49 -0600
Subject: st/mesa: silence uninitialized var warnings

---
 src/mesa/state_tracker/st_cb_texture.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c
index 2d37d24ea8..2db28ef0a4 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -526,9 +526,9 @@ st_TexImage(GLcontext * ctx,
    struct st_texture_image *stImage = st_texture_image(texImage);
    GLint postConvWidth, postConvHeight;
    GLint texelBytes, sizeInBytes;
-   GLuint dstRowStride;
+   GLuint dstRowStride = 0;
    struct gl_pixelstore_attrib unpackNB;
-   enum pipe_transfer_usage transfer_usage;
+   enum pipe_transfer_usage transfer_usage = 0;
 
    DBG("%s target %s level %d %dx%dx%d border %d\n", __FUNCTION__,
        _mesa_lookup_enum_by_nr(target), level, width, height, depth, border);
-- 
cgit v1.2.3


From 1c32caf075ce4015ba50d0aa9f0a2ff924c21970 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 15:23:15 -0600
Subject: gallium/xlib: silence uninitialized var warning

---
 src/gallium/winsys/xlib/xlib_brw_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/winsys/xlib/xlib_brw_screen.c b/src/gallium/winsys/xlib/xlib_brw_screen.c
index fe8dfff767..a78efb10fa 100644
--- a/src/gallium/winsys/xlib/xlib_brw_screen.c
+++ b/src/gallium/winsys/xlib/xlib_brw_screen.c
@@ -364,7 +364,7 @@ void xlib_brw_buffer_subdata_typed( struct pipe_winsys *pws,
                                     unsigned data_type )
 {
    unsigned aub_type = DW_GENERAL_STATE;
-   unsigned aub_sub_type;
+   unsigned aub_sub_type = 0;
 
    switch (data_type) {
    case BRW_CC_VP:
-- 
cgit v1.2.3


From 32156f3a1165624cd4e2d0d337809fb046bd9285 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 15:44:22 -0600
Subject: gallium/xlib: silence unitialized var warning

---
 src/gallium/state_trackers/glx/xlib/xm_api.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/glx/xlib/xm_api.c b/src/gallium/state_trackers/glx/xlib/xm_api.c
index a3d1651653..45ad694e23 100644
--- a/src/gallium/state_trackers/glx/xlib/xm_api.c
+++ b/src/gallium/state_trackers/glx/xlib/xm_api.c
@@ -743,7 +743,7 @@ XMesaContext XMesaCreateContext( XMesaVisual v, XMesaContext share_list )
 {
    static GLboolean firstTime = GL_TRUE;
    struct pipe_screen *screen;
-   struct pipe_context *pipe;
+   struct pipe_context *pipe = NULL;
    XMesaContext c;
    GLcontext *mesaCtx;
    uint pf;
-- 
cgit v1.2.3


From 7d3af894d692e1b4c39eb6b24210bd53993723d7 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 15:44:49 -0600
Subject: docs: point to fd.o for downloads instead of SourceForge

---
 docs/download.html | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/docs/download.html b/docs/download.html
index cf1cc21d37..3cb9423dd9 100644
--- a/docs/download.html
+++ b/docs/download.html
@@ -9,14 +9,14 @@
 <H1>Downloading</H1>
 
 <p>
-Primary download site:
-<a href="http://sourceforge.net/project/showfiles.php?group_id=3"
-target="_parent">SourceForge</a>
+Primary Mesa download site:
+<a href="ftp://ftp.freedesktop.org/pub/mesa/"
+target="_parent">freedesktop.org</a> (FTP)
 </p>
 
 <p>
-When a new release is coming, release candidates (betas) can be found
-<a href="http://www.mesa3d.org/beta/">here</a>.
+When a new release is coming, release candidates (betas) may be found
+<a href="ftp://ftp.freedesktop.org/pub/mesa/beta/" target="_parent">here</a>.
 </p>
 
 
-- 
cgit v1.2.3


From 1960da2e099e3899af3f668e5914162f9293cd6c Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 3 Sep 2009 15:49:10 -0600
Subject: docs: 7.5.1 md5 sums

---
 docs/relnotes-7.5.1.html | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes-7.5.1.html b/docs/relnotes-7.5.1.html
index c65fb85e27..1a4f608b7c 100644
--- a/docs/relnotes-7.5.1.html
+++ b/docs/relnotes-7.5.1.html
@@ -31,7 +31,15 @@ for DRI hardware acceleration.
 
 <h2>MD5 checksums</h2>
 <pre>
-tbd
+d7269e93bc7484430637d54ced250876  MesaLib-7.5.1.tar.gz
+877d6a4b24efc2b1d02aa553f262cba8  MesaLib-7.5.1.tar.bz2
+23f4fb757a05c8396425681234ae20e5  MesaLib-7.5.1.zip
+5af4bd113652108f5cec5113dad813f2  MesaDemos-7.5.1.tar.gz
+785402e3b9f0e335538fcc6bf19f6987  MesaDemos-7.5.1.tar.bz2
+950058cc6d6106e9c7d5876a03789fe9  MesaDemos-7.5.1.zip
+cb52ce2c93389c2711cbe8d857ec5303  MesaGLUT-7.5.1.tar.gz
+e3a9892e056d625c5353617a7c5b7e9c  MesaGLUT-7.5.1.tar.bz2
+da1de364df148c94b4994006191a1e69  MesaGLUT-7.5.1.zip
 </pre>
 
 
-- 
cgit v1.2.3


From cab307ce6b32d2ffdb0eb3bb5bae93c6fb9305fb Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Fri, 15 May 2009 09:14:24 -0600
Subject: i965: rename var: s/tmp/vs_inputs/ (cherry picked from commit
 840c09fc71542fdfc71edd2a2802925d467567bb)

---
 src/mesa/drivers/dri/i965/brw_draw_upload.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index b91b20bec6..1b8bcc14ec 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -343,7 +343,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
 {
    GLcontext *ctx = &brw->intel.ctx;
    struct intel_context *intel = intel_context(ctx);
-   GLuint tmp = brw->vs.prog_data->inputs_read; 
+   GLbitfield vs_inputs = brw->vs.prog_data->inputs_read; 
    GLuint i;
    const unsigned char *ptr = NULL;
    GLuint interleave = 0;
@@ -362,11 +362,11 @@ static void brw_prepare_vertices(struct brw_context *brw)
       _mesa_printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
 
    /* Accumulate the list of enabled arrays. */
-   while (tmp) {
-      GLuint i = _mesa_ffsll(tmp)-1;
+   while (vs_inputs) {
+      GLuint i = _mesa_ffsll(vs_inputs) - 1;
       struct brw_vertex_element *input = &brw->vb.inputs[i];
 
-      tmp &= ~(1<<i);
+      vs_inputs &= ~(1 << i);
       enabled[nr_enabled++] = input;
    }
 
@@ -477,17 +477,17 @@ static void brw_emit_vertices(struct brw_context *brw)
 {
    GLcontext *ctx = &brw->intel.ctx;
    struct intel_context *intel = intel_context(ctx);
-   GLuint tmp = brw->vs.prog_data->inputs_read;
+   GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
    struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
    GLuint i;
    GLuint nr_enabled = 0;
 
   /* Accumulate the list of enabled arrays. */
-   while (tmp) {
-      i = _mesa_ffsll(tmp)-1;
+   while (vs_inputs) {
+      i = _mesa_ffsll(vs_inputs) - 1;
       struct brw_vertex_element *input = &brw->vb.inputs[i];
 
-      tmp &= ~(1<<i);
+      vs_inputs &= ~(1 << i);
       enabled[nr_enabled++] = input;
    }
 
-- 
cgit v1.2.3


From 213ac4bb5de1cef601e0677ef2e5ca1779851e28 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 23 Jun 2009 19:30:25 -0700
Subject: i965: Set the max index buffer address correctly according to the
 docs.

It's the last addressable byte, not the byte after the end of the buffer.
(cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
---
 src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 1b8bcc14ec..3ef56a0068 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -635,7 +635,7 @@ static void brw_emit_indices(struct brw_context *brw)
    if (index_buffer == NULL)
       return;
 
-   ib_size = get_size(index_buffer->type) * index_buffer->count;
+   ib_size = get_size(index_buffer->type) * index_buffer->count - 1;
 
    /* Emit the indexbuffer packet:
     */
-- 
cgit v1.2.3


From 7e26bdb849b75f4aeb69cf8b1fdffbc461265490 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 3 Aug 2009 14:46:18 -0700
Subject: i965: Calculate enabled[] and nr_enabled once and re-use the values.

The code duplication bothered me.
(cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
---
 src/mesa/drivers/dri/i965/brw_context.h     |  3 ++
 src/mesa/drivers/dri/i965/brw_draw_upload.c | 44 ++++++++++-------------------
 2 files changed, 18 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 577497bf6b..e52fc3f374 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -477,6 +477,9 @@ struct brw_context
    struct {
       struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
 
+      struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
+      GLuint nr_enabled;
+
 #define BRW_NR_UPLOAD_BUFS 17
 #define BRW_UPLOAD_INIT_SIZE (128*1024)
 
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 3ef56a0068..c1fe85908b 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -350,9 +350,6 @@ static void brw_prepare_vertices(struct brw_context *brw)
    unsigned int min_index = brw->vb.min_index;
    unsigned int max_index = brw->vb.max_index;
 
-   struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
-   GLuint nr_enabled = 0;
-
    struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
    GLuint nr_uploads = 0;
 
@@ -362,12 +359,13 @@ static void brw_prepare_vertices(struct brw_context *brw)
       _mesa_printf("%s %d..%d\n", __FUNCTION__, min_index, max_index);
 
    /* Accumulate the list of enabled arrays. */
+   brw->vb.nr_enabled = 0;
    while (vs_inputs) {
       GLuint i = _mesa_ffsll(vs_inputs) - 1;
       struct brw_vertex_element *input = &brw->vb.inputs[i];
 
       vs_inputs &= ~(1 << i);
-      enabled[nr_enabled++] = input;
+      brw->vb.enabled[brw->vb.nr_enabled++] = input;
    }
 
    /* XXX: In the rare cases where this happens we fallback all
@@ -376,13 +374,13 @@ static void brw_prepare_vertices(struct brw_context *brw)
     * cases with > 17 vertex attributes enabled, so it probably
     * isn't an issue at this point.
     */
-   if (nr_enabled >= BRW_VEP_MAX) {
+   if (brw->vb.nr_enabled >= BRW_VEP_MAX) {
       intel->Fallback = 1;
       return;
    }
 
-   for (i = 0; i < nr_enabled; i++) {
-      struct brw_vertex_element *input = enabled[i];
+   for (i = 0; i < brw->vb.nr_enabled; i++) {
+      struct brw_vertex_element *input = brw->vb.enabled[i];
 
       input->element_size = get_size(input->glarray->Type) * input->glarray->Size;
       input->count = input->glarray->StrideB ? max_index + 1 - min_index : 1;
@@ -466,8 +464,8 @@ static void brw_prepare_vertices(struct brw_context *brw)
 
    brw_prepare_query_begin(brw);
 
-   for (i = 0; i < nr_enabled; i++) {
-      struct brw_vertex_element *input = enabled[i];
+   for (i = 0; i < brw->vb.nr_enabled; i++) {
+      struct brw_vertex_element *input = brw->vb.enabled[i];
 
       brw_add_validated_bo(brw, input->bo);
    }
@@ -477,19 +475,7 @@ static void brw_emit_vertices(struct brw_context *brw)
 {
    GLcontext *ctx = &brw->intel.ctx;
    struct intel_context *intel = intel_context(ctx);
-   GLbitfield vs_inputs = brw->vs.prog_data->inputs_read;
-   struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
    GLuint i;
-   GLuint nr_enabled = 0;
-
-  /* Accumulate the list of enabled arrays. */
-   while (vs_inputs) {
-      i = _mesa_ffsll(vs_inputs) - 1;
-      struct brw_vertex_element *input = &brw->vb.inputs[i];
-
-      vs_inputs &= ~(1 << i);
-      enabled[nr_enabled++] = input;
-   }
 
    brw_emit_query_begin(brw);
 
@@ -499,12 +485,12 @@ static void brw_emit_vertices(struct brw_context *brw)
     * are interleaved or from the same VBO.  TBD if this makes a
     * performance difference.
     */
-   BEGIN_BATCH(1 + nr_enabled * 4, IGNORE_CLIPRECTS);
+   BEGIN_BATCH(1 + brw->vb.nr_enabled * 4, IGNORE_CLIPRECTS);
    OUT_BATCH((CMD_VERTEX_BUFFER << 16) |
-	     ((1 + nr_enabled * 4) - 2));
+	     ((1 + brw->vb.nr_enabled * 4) - 2));
 
-   for (i = 0; i < nr_enabled; i++) {
-      struct brw_vertex_element *input = enabled[i];
+   for (i = 0; i < brw->vb.nr_enabled; i++) {
+      struct brw_vertex_element *input = brw->vb.enabled[i];
 
       OUT_BATCH((i << BRW_VB0_INDEX_SHIFT) |
 		BRW_VB0_ACCESS_VERTEXDATA |
@@ -517,10 +503,10 @@ static void brw_emit_vertices(struct brw_context *brw)
    }
    ADVANCE_BATCH();
 
-   BEGIN_BATCH(1 + nr_enabled * 2, IGNORE_CLIPRECTS);
-   OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + nr_enabled * 2) - 2));
-   for (i = 0; i < nr_enabled; i++) {
-      struct brw_vertex_element *input = enabled[i];
+   BEGIN_BATCH(1 + brw->vb.nr_enabled * 2, IGNORE_CLIPRECTS);
+   OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + brw->vb.nr_enabled * 2) - 2));
+   for (i = 0; i < brw->vb.nr_enabled; i++) {
+      struct brw_vertex_element *input = brw->vb.enabled[i];
       uint32_t format = get_surface_type(input->glarray->Type,
 					 input->glarray->Size,
 					 input->glarray->Format,
-- 
cgit v1.2.3


From 9eca0e5350377148976e0d1200f98bd20ac28197 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 30 Jul 2009 13:40:29 -0700
Subject: i965: Don't emit bad packets when no VBs are referenced.

It appears that sometimes Mesa (and I suppose a VS could as well) emits
a program which references no vertex data, and thus we end up with
nr_enabled == 0 even though some VBs are enabled.  We'd end up emitting
VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs.

Bug #22945 (wine with an uncompiled VS)
(cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
---
 src/mesa/drivers/dri/i965/brw_draw_upload.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index c1fe85908b..e7a87b6e09 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -479,6 +479,28 @@ static void brw_emit_vertices(struct brw_context *brw)
 
    brw_emit_query_begin(brw);
 
+   /* If the VS doesn't read any inputs (calculating vertex position from
+    * a state variable for some reason, for example), emit a single pad
+    * VERTEX_ELEMENT struct and bail.
+    *
+    * The stale VB state stays in place, but they don't do anything unless
+    * a VE loads from them.
+    */
+   if (brw->vb.nr_enabled == 0) {
+      BEGIN_BATCH(3, IGNORE_CLIPRECTS);
+      OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1);
+      OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) |
+		BRW_VE0_VALID |
+		(BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
+		(0 << BRW_VE0_SRC_OFFSET_SHIFT));
+      OUT_BATCH((BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT) |
+		(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT) |
+		(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
+		(BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT));
+      ADVANCE_BATCH();
+      return;
+   }
+
    /* Now emit VB and VEP state packets.
     *
     * This still defines a hardware VB for each input, even if they
-- 
cgit v1.2.3


From 456a16491bc757af6ba9a98e5706a78f748e9a79 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 3 Aug 2009 15:24:02 -0700
Subject: i965: Make sure the VS URB size is big enough to fit a VF VUE.

This fix is just from code and docs inspection, but it may fix hangs on
some applications.

(cherry picked from commit e93848e595176ae0bad3bfe64e0ca63fd089bb72)
---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index b69616d6e5..6792c3a34e 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -68,6 +68,7 @@ static void release_tmps( struct brw_vs_compile *c )
 static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 {
    GLuint i, reg = 0, mrf;
+   int attributes_in_vue;
 
 #if 0
    if (c->vp->program.Base.Parameters->NumParameters >= 6)
@@ -201,7 +202,13 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
     */
    c->prog_data.urb_read_length = (c->nr_inputs + 1) / 2;
 
-   c->prog_data.urb_entry_size = (c->nr_outputs + 2 + 3) / 4;
+   /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
+    * them to fit the biggest thing they need to.
+    */
+   attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs);
+
+   c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4;
+
    c->prog_data.total_grf = reg;
 
    if (INTEL_DEBUG & DEBUG_VS) {
-- 
cgit v1.2.3


From 217af32c2d6afab5e1907cc16fb4b6feb982abe7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 3 Aug 2009 17:12:43 -0700
Subject: i965: Even if no VS inputs are set, still load some amount of URB as
 required.

See comment on Vertex URB Entry Read Length for VS_STATE.

This, combined with the previous three commits, fixes #22945.
(cherry picked from commit e340d4f9866db4bae391288e83a630a310b0dd2b)
---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 6792c3a34e..b95079a5d1 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -124,6 +124,11 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
 	 reg++;
       }
    }
+   /* If there are no inputs, we'll still be reading one attribute's worth
+    * because it's required -- see urb_read_length setting.
+    */
+   if (c->nr_inputs == 0)
+      reg++;
 
    /* Allocate outputs: TODO: could organize the non-position outputs
     * to go straight into message regs.
@@ -201,6 +206,12 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c )
     * vertex urb, so is half the amount:
     */
    c->prog_data.urb_read_length = (c->nr_inputs + 1) / 2;
+   /* Setting this field to 0 leads to undefined behavior according to the
+    * the VS_STATE docs.  Our VUEs will always have at least one attribute
+    * sitting in them, even if it's padding.
+    */
+   if (c->prog_data.urb_read_length == 0)
+      c->prog_data.urb_read_length = 1;
 
    /* The VS VUEs are shared by VF (outputting our inputs) and VS, so size
     * them to fit the biggest thing they need to.
-- 
cgit v1.2.3


From 63b3fa2bcecc75a116ce651da435d205ccd43584 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 3 Aug 2009 17:55:14 -0700
Subject: i965: Assert that the offset in the VBO is below the VBO size.

This avoids sending a bad buffer address to the GPU due to programmer error,
and is permitted by the ARB_vbo spec.  Note that we still have the opportunity
to dereference past the end of the GPU, because we aren't clipping to a
correct _MaxElement, but that appears to be harder than it should be.  This
gets us the 90% solution.

Bug #19911.
(cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
---
 src/mesa/drivers/dri/i965/brw_draw_upload.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e7a87b6e09..05079c043a 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -396,6 +396,20 @@ static void brw_prepare_vertices(struct brw_context *brw)
 	 dri_bo_reference(input->bo);
 	 input->offset = (unsigned long)input->glarray->Ptr;
 	 input->stride = input->glarray->StrideB;
+
+	 /* This is a common place to reach if the user mistakenly supplies
+	  * a pointer in place of a VBO offset.  If we just let it go through,
+	  * we may end up dereferencing a pointer beyond the bounds of the
+	  * GTT.  We would hope that the VBO's max_index would save us, but
+	  * Mesa appears to hand us min/max values not clipped to the
+	  * array object's _MaxElement, and _MaxElement frequently appears
+	  * to be wrong anyway.
+	  *
+	  * The VBO spec allows application termination in this case, and it's
+	  * probably a service to the poor programmer to do so rather than
+	  * trying to just not render.
+	  */
+	 assert(input->offset < input->bo->size);
       } else {
 	 if (input->bo != NULL) {
 	    /* Already-uploaded vertex data is present from a previous
-- 
cgit v1.2.3


From f396263651b867be39800bfd274b1be3d78ef60f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 4 Aug 2009 12:39:22 -0700
Subject: i965: Fix RECT shadow sampling by not losing the other texcoords.

Bug #20821
(cherry picked from commit 191e028de20b2f954621b652aa77b06d0e93652a)
---
 src/mesa/drivers/dri/i965/brw_wm_fp.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c
index 49aad281d7..8cf3a1fd13 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_fp.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c
@@ -705,7 +705,11 @@ static void precalc_tex( struct brw_wm_compile *c,
 	      tmpcoord,
 	      0,
 	      inst->SrcReg[0],
-	      scale,
+	      src_swizzle(scale,
+			  SWIZZLE_X,
+			  SWIZZLE_Y,
+			  SWIZZLE_ONE,
+			  SWIZZLE_ONE),
 	      src_undef());
 
       coord = src_reg_from_dst(tmpcoord);
-- 
cgit v1.2.3


From 83e6c67363d77d89ab4b6e2e202c8634d582c907 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 4 Aug 2009 13:42:30 -0700
Subject: i965: Spell "conditional" correctly.

---
 src/mesa/drivers/dri/i965/brw_eu.c      |  2 +-
 src/mesa/drivers/dri/i965/brw_eu_emit.c | 26 +++++++++++++-------------
 src/mesa/drivers/dri/i965/brw_structs.h |  2 +-
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index c53efba599..1df561386e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -62,7 +62,7 @@ void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
 
 void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
 {
-   p->current->header.destreg__conditonalmod = conditional;
+   p->current->header.destreg__conditionalmod = conditional;
 }
 
 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2a147fb8c3..48243e1574 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -377,8 +377,8 @@ static struct brw_instruction *next_insn( struct brw_compile *p,
    /* Reset this one-shot flag: 
     */
 
-   if (p->current->header.destreg__conditonalmod) {
-      p->current->header.destreg__conditonalmod = 0;   
+   if (p->current->header.destreg__conditionalmod) {
+      p->current->header.destreg__conditionalmod = 0;
       p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
    }
 
@@ -746,7 +746,7 @@ void brw_CMP(struct brw_compile *p,
 {
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP);
 
-   insn->header.destreg__conditonalmod = conditional;
+   insn->header.destreg__conditionalmod = conditional;
    brw_set_dest(insn, dest);
    brw_set_src0(insn, src0);
    brw_set_src1(insn, src1);
@@ -790,7 +790,7 @@ void brw_math( struct brw_compile *p,
     * instructions.
     */
    insn->header.predicate_control = 0; 
-   insn->header.destreg__conditonalmod = msg_reg_nr;
+   insn->header.destreg__conditionalmod = msg_reg_nr;
 
    brw_set_dest(insn, dest);
    brw_set_src0(insn, src);
@@ -826,7 +826,7 @@ void brw_math_16( struct brw_compile *p,
    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
 
    insn = next_insn(p, BRW_OPCODE_SEND);
-   insn->header.destreg__conditonalmod = msg_reg_nr;
+   insn->header.destreg__conditionalmod = msg_reg_nr;
 
    brw_set_dest(insn, dest);
    brw_set_src0(insn, src);
@@ -842,7 +842,7 @@ void brw_math_16( struct brw_compile *p,
     */
    insn = next_insn(p, BRW_OPCODE_SEND);
    insn->header.compression_control = BRW_COMPRESSION_2NDHALF;
-   insn->header.destreg__conditonalmod = msg_reg_nr+1;
+   insn->header.destreg__conditionalmod = msg_reg_nr+1;
 
    brw_set_dest(insn, offset(dest,1));
    brw_set_src0(insn, src);
@@ -888,7 +888,7 @@ void brw_dp_WRITE_16( struct brw_compile *p,
    
       insn->header.predicate_control = 0; /* XXX */
       insn->header.compression_control = BRW_COMPRESSION_NONE; 
-      insn->header.destreg__conditonalmod = msg_reg_nr;
+      insn->header.destreg__conditionalmod = msg_reg_nr;
   
       brw_set_dest(insn, dest);
       brw_set_src0(insn, src);
@@ -933,7 +933,7 @@ void brw_dp_READ_16( struct brw_compile *p,
    
       insn->header.predicate_control = 0; /* XXX */
       insn->header.compression_control = BRW_COMPRESSION_NONE; 
-      insn->header.destreg__conditonalmod = msg_reg_nr;
+      insn->header.destreg__conditionalmod = msg_reg_nr;
   
       brw_set_dest(insn, dest);	/* UW? */
       brw_set_src0(insn, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW));
@@ -986,7 +986,7 @@ void brw_dp_READ_4( struct brw_compile *p,
    
       insn->header.predicate_control = BRW_PREDICATE_NONE;
       insn->header.compression_control = BRW_COMPRESSION_NONE; 
-      insn->header.destreg__conditonalmod = msg_reg_nr;
+      insn->header.destreg__conditionalmod = msg_reg_nr;
       insn->header.mask_control = BRW_MASK_DISABLE;
   
       /* cast dest to a uword[8] vector */
@@ -1059,7 +1059,7 @@ void brw_dp_READ_4_vs(struct brw_compile *p,
    
       insn->header.predicate_control = BRW_PREDICATE_NONE;
       insn->header.compression_control = BRW_COMPRESSION_NONE; 
-      insn->header.destreg__conditonalmod = msg_reg_nr;
+      insn->header.destreg__conditionalmod = msg_reg_nr;
       insn->header.mask_control = BRW_MASK_DISABLE;
       /*insn->header.access_mode = BRW_ALIGN_16;*/
   
@@ -1092,7 +1092,7 @@ void brw_fb_WRITE(struct brw_compile *p,
    
    insn->header.predicate_control = 0; /* XXX */
    insn->header.compression_control = BRW_COMPRESSION_NONE; 
-   insn->header.destreg__conditonalmod = msg_reg_nr;
+   insn->header.destreg__conditionalmod = msg_reg_nr;
   
    brw_set_dest(insn, dest);
    brw_set_src0(insn, src0);
@@ -1187,7 +1187,7 @@ void brw_SAMPLE(struct brw_compile *p,
    
       insn->header.predicate_control = 0; /* XXX */
       insn->header.compression_control = BRW_COMPRESSION_NONE;
-      insn->header.destreg__conditonalmod = msg_reg_nr;
+      insn->header.destreg__conditionalmod = msg_reg_nr;
 
       brw_set_dest(insn, dest);
       brw_set_src0(insn, src0);
@@ -1238,7 +1238,7 @@ void brw_urb_WRITE(struct brw_compile *p,
    brw_set_src0(insn, src0);
    brw_set_src1(insn, brw_imm_d(0));
 
-   insn->header.destreg__conditonalmod = msg_reg_nr;
+   insn->header.destreg__conditionalmod = msg_reg_nr;
 
    brw_set_urb_message(insn,
 		       allocate,
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 89e2981203..6011a4aa0a 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1168,7 +1168,7 @@ struct brw_instruction
       GLuint predicate_control:4;
       GLuint predicate_inverse:1;
       GLuint execution_size:3;
-      GLuint destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */
+      GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
       GLuint pad0:2;
       GLuint debug_control:1;
       GLuint saturate:1;
-- 
cgit v1.2.3


From 3d6c73513c5918a3f833ebf402803946b78828b8 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 4 Aug 2009 14:13:27 -0700
Subject: i965: Emit conditional code updates as required for GLSL VS if
 statements.

Previously, we'd be branching based on whatever condition code happened to be
laying around.
(cherry picked from commit 7007f8b352763af89805f287153cb7972bff0523)
---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index b95079a5d1..4887cdea5b 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1448,6 +1448,19 @@ void brw_vs_emit(struct brw_vs_compile *c )
 				    "unknown");
       }
 
+      /* Set the predication update on the last instruction of the native
+       * instruction sequence.
+       *
+       * This would be problematic if it was set on a math instruction,
+       * but that shouldn't be the case with the current GLSL compiler.
+       */
+      if (inst->CondUpdate) {
+	 struct brw_instruction *hw_insn = &p->store[p->nr_insn - 1];
+
+	 assert(hw_insn->header.destreg__conditionalmod == 0);
+	 hw_insn->header.destreg__conditionalmod = BRW_CONDITIONAL_NZ;
+      }
+
       if ((inst->DstReg.File == PROGRAM_OUTPUT)
           && (inst->DstReg.Index != VERT_RESULT_HPOS)
           && c->output_regs[inst->DstReg.Index].used_in_src) {
-- 
cgit v1.2.3


From a0b7850f1da6e367ed3380fbf0a59fa5af992546 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 18 Jun 2009 09:23:58 -0600
Subject: i965: asst clean-ups, etc in brw_vs_emit() (cherry picked from commit
 fd7d764514c540987549c3ea88a2d669b0f0ea58)

---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 4887cdea5b..7c09222281 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1195,15 +1195,14 @@ post_vs_emit( struct brw_vs_compile *c,
  */
 void brw_vs_emit(struct brw_vs_compile *c )
 {
-#define MAX_IFSN 32
+#define MAX_IF_DEPTH 32
    struct brw_compile *p = &c->func;
-   GLuint nr_insns = c->vp->program.Base.NumInstructions;
-   GLuint insn, if_insn = 0;
+   const GLuint nr_insns = c->vp->program.Base.NumInstructions;
+   GLuint insn, if_depth = 0;
    GLuint end_offset = 0;
    struct brw_instruction *end_inst, *last_inst;
-   struct brw_instruction *if_inst[MAX_IFSN];
-   struct brw_indirect stack_index = brw_indirect(0, 0);   
-
+   struct brw_instruction *if_inst[MAX_IF_DEPTH];
+   const struct brw_indirect stack_index = brw_indirect(0, 0);   
    GLuint index;
    GLuint file;
 
@@ -1394,15 +1393,15 @@ void brw_vs_emit(struct brw_vs_compile *c )
 	 emit_xpd(p, dst, args[0], args[1]);
 	 break;
       case OPCODE_IF:
-	 assert(if_insn < MAX_IFSN);
-         if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
+	 assert(if_depth < MAX_IF_DEPTH);
+         if_inst[if_depth++] = brw_IF(p, BRW_EXECUTE_8);
 	 break;
       case OPCODE_ELSE:
-	 if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]);
+	 if_inst[if_depth-1] = brw_ELSE(p, if_inst[if_depth-1]);
 	 break;
       case OPCODE_ENDIF:
-         assert(if_insn > 0);
-	 brw_ENDIF(p, if_inst[--if_insn]);
+         assert(if_depth > 0);
+	 brw_ENDIF(p, if_inst[--if_depth]);
 	 break;			
       case OPCODE_BRA:
          brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
-- 
cgit v1.2.3


From 8c764d5c34548d56e912cdc5990adffb0e8fd9f7 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 4 Aug 2009 18:02:31 -0700
Subject: i965: Respect CondSwizzle in OPCODE_IF.

Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be
useful for the looping code.

Bug #18992
(cherry picked from commit 78c022acd0b37bf8b32f04313d76255255e769c1)
(cherry picked from commit 63d7a2f53fb38e170f4e55f2b599e918edf2c512)
---
 src/mesa/drivers/dri/i965/brw_vs_emit.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c
index 7c09222281..72cd36a603 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c
@@ -1190,6 +1190,23 @@ post_vs_emit( struct brw_vs_compile *c,
    brw_set_src1(end_inst, brw_imm_d(offset * 16));
 }
 
+static uint32_t
+get_predicate(uint32_t swizzle)
+{
+   switch (swizzle) {
+   case SWIZZLE_XXXX:
+      return BRW_PREDICATE_ALIGN16_REPLICATE_X;
+   case SWIZZLE_YYYY:
+      return BRW_PREDICATE_ALIGN16_REPLICATE_Y;
+   case SWIZZLE_ZZZZ:
+      return BRW_PREDICATE_ALIGN16_REPLICATE_Z;
+   case SWIZZLE_WWWW:
+      return BRW_PREDICATE_ALIGN16_REPLICATE_W;
+   default:
+      _mesa_problem(NULL, "Unexpected predicate: 0x%08x\n", swizzle);
+      return BRW_PREDICATE_NORMAL;
+   }
+}
 
 /* Emit the vertex program instructions here.
  */
@@ -1394,7 +1411,10 @@ void brw_vs_emit(struct brw_vs_compile *c )
 	 break;
       case OPCODE_IF:
 	 assert(if_depth < MAX_IF_DEPTH);
-         if_inst[if_depth++] = brw_IF(p, BRW_EXECUTE_8);
+	 if_inst[if_depth] = brw_IF(p, BRW_EXECUTE_8);
+	 if_inst[if_depth]->header.predicate_control =
+	    get_predicate(inst->DstReg.CondSwizzle);
+	 if_depth++;
 	 break;
       case OPCODE_ELSE:
 	 if_inst[if_depth-1] = brw_ELSE(p, if_inst[if_depth-1]);
-- 
cgit v1.2.3


From 94d3b832cc5c73544c478804531e16644483d8be Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 5 Aug 2009 20:12:15 -0700
Subject: i965: Fix source depth reg setting for FSes reading and writing to
 depth.

For some IZ setups, we'd forget to account for the source depth register
being present, so we'd both read the wrong reg, and write output depth to
the wrong reg.

Bug #22603.
(cherry picked from commit f44916414ecd2b888c8a680d56b7467ccdff6886)
---
 src/mesa/drivers/dri/i965/brw_wm.c    | 2 ++
 src/mesa/drivers/dri/i965/brw_wm.h    | 1 +
 src/mesa/drivers/dri/i965/brw_wm_iz.c | 3 ++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 8a3b7df9c7..d4e22d5939 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -202,6 +202,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
    /* BRW_NEW_FRAGMENT_PROGRAM */
    const struct brw_fragment_program *fp = 
       (struct brw_fragment_program *)brw->fragment_program;
+   GLboolean uses_depth = (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
    GLuint lookup = 0;
    GLuint line_aa;
    GLuint i;
@@ -263,6 +264,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
 	 
    brw_wm_lookup_iz(line_aa,
 		    lookup,
+		    uses_depth,
 		    key);
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h
index 295fed851b..307b5e59dd 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -286,6 +286,7 @@ void brw_wm_print_program( struct brw_wm_compile *c,
 
 void brw_wm_lookup_iz( GLuint line_aa,
 		       GLuint lookup,
+		       GLboolean ps_uses_depth,
 		       struct brw_wm_prog_key *key );
 
 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.c b/src/mesa/drivers/dri/i965/brw_wm_iz.c
index bd60ac9b31..7e2b1c79de 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_iz.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_iz.c
@@ -118,6 +118,7 @@ const struct {
 
 void brw_wm_lookup_iz( GLuint line_aa,
 		       GLuint lookup,
+		       GLboolean ps_uses_depth,
 		       struct brw_wm_prog_key *key )
 {
    GLuint reg = 2;
@@ -127,7 +128,7 @@ void brw_wm_lookup_iz( GLuint line_aa,
    if (lookup & IZ_PS_COMPUTES_DEPTH_BIT)
       key->computes_depth = 1;
 
-   if (wm_iz_table[lookup].sd_present) {
+   if (wm_iz_table[lookup].sd_present || ps_uses_depth) {
       key->source_depth_reg = reg;
       reg += 2;
    }
-- 
cgit v1.2.3


From 945d34e88ab7413299227fea56acc746010bb2e9 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 7 Aug 2009 18:09:31 -0700
Subject: intel: Align untiled region height to 2 according to 965 docs.

This may or may not be required pre-965, but it doesn't seem unlikely, and
I'd rather be safe.
(cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
---
 src/mesa/drivers/dri/intel/intel_regions.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c
index 0aa5b8c02c..b8d2dec4cb 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -114,6 +114,13 @@ intel_region_alloc(struct intel_context *intel,
 {
    dri_bo *buffer;
 
+   /* If we're untiled, we have to align to 2 rows high because the
+    * data port accesses 2x2 blocks even if the bottom row isn't to be
+    * rendered, so failure to align means we could walk off the end of the
+    * GTT and fault.
+    */
+   height = ALIGN(height, 2);
+
    if (expect_accelerated_upload) {
       buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
 					     pitch * cpp * height, 64);
-- 
cgit v1.2.3


From a9504edee344936ef496341174d4c2d76ee0c44d Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Tue, 18 Aug 2009 18:48:54 -0700
Subject: intel: Align cubemap texture height to its padding requirements.
 (cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry
 picked from commit 29e51c3872531366570d032147abad50f8a3c1af)

---
 src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 51a617fcb4..3ab27c26ef 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -119,6 +119,16 @@ GLboolean brw_miptree_layout( struct intel_context *intel, struct intel_mipmap_t
     }
 
       }
+      /* The 965's sampler lays cachelines out according to how accesses
+       * in the texture surfaces run, so they may be "vertical" through
+       * memory.  As a result, the docs say in Surface Padding Requirements:
+       * Sampling Engine Surfaces that two extra rows of padding are required.
+       * We don't know of similar requirements for pre-965, but given that
+       * those docs are silent on padding requirements in general, let's play
+       * it safe.
+       */
+      if (mt->target == GL_TEXTURE_CUBE_MAP)
+	 mt->total_height += 2;
       break;
    }
 
-- 
cgit v1.2.3


From 1d1dfc96c48681c455e1174a60bd325b33a2784f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Thu, 16 Jul 2009 15:57:22 -0700
Subject: i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.
 (cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)

---
 src/mesa/drivers/dri/i965/brw_sf_state.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c
index c99918724b..38733c8c73 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_state.c
@@ -233,7 +233,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
    else if (sf.sf6.line_width <= 0x2)
        sf.sf6.line_width = 0;
 
-   /* _NEW_POINT */
+   /* _NEW_BUFFERS */
    key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
    if (!key->render_to_fbo) {
       /* Rendering to an OpenGL window */
@@ -263,6 +263,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
    }
    /* XXX clamp max depends on AA vs. non-AA */
 
+   /* _NEW_POINT */
    sf.sf7.sprite_point = key->point_sprite;
    sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
    sf.sf7.use_point_size_state = !key->point_attenuated;
@@ -328,7 +329,8 @@ const struct brw_tracked_state brw_sf_unit = {
       .mesa  = (_NEW_POLYGON | 
 		_NEW_LINE | 
 		_NEW_POINT | 
-		_NEW_SCISSOR),
+		_NEW_SCISSOR |
+		_NEW_BUFFERS),
       .brw   = BRW_NEW_URB_FENCE,
       .cache = (CACHE_NEW_SF_VP |
 		CACHE_NEW_SF_PROG)
-- 
cgit v1.2.3


From 04081a164ca6160404d87dccbfc641bfd46428e0 Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 19 Jun 2009 21:43:22 -0700
Subject: intel: Move intel_pixel_read.c to shared for use with i965. (cherry
 picked from commit dcfe0d66bfff9a55741aee298b7ffb051a48f0d3)

---
 src/mesa/drivers/dri/i915/intel_pixel_read.c  | 307 +-------------------------
 src/mesa/drivers/dri/intel/intel_pixel_read.c | 306 +++++++++++++++++++++++++
 2 files changed, 307 insertions(+), 306 deletions(-)
 mode change 100644 => 120000 src/mesa/drivers/dri/i915/intel_pixel_read.c
 create mode 100644 src/mesa/drivers/dri/intel/intel_pixel_read.c

diff --git a/src/mesa/drivers/dri/i915/intel_pixel_read.c b/src/mesa/drivers/dri/i915/intel_pixel_read.c
deleted file mode 100644
index 56087aacd4..0000000000
--- a/src/mesa/drivers/dri/i915/intel_pixel_read.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/**************************************************************************
- * 
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- * 
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- * 
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- * 
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * 
- **************************************************************************/
-
-#include "main/glheader.h"
-#include "main/enums.h"
-#include "main/mtypes.h"
-#include "main/macros.h"
-#include "main/image.h"
-#include "main/bufferobj.h"
-#include "swrast/swrast.h"
-
-#include "intel_screen.h"
-#include "intel_context.h"
-#include "intel_batchbuffer.h"
-#include "intel_blit.h"
-#include "intel_buffers.h"
-#include "intel_regions.h"
-#include "intel_pixel.h"
-#include "intel_buffer_objects.h"
-
-/* For many applications, the new ability to pull the source buffers
- * back out of the GTT and then do the packing/conversion operations
- * in software will be as much of an improvement as trying to get the
- * blitter and/or texture engine to do the work. 
- *
- * This step is gated on private backbuffers.
- * 
- * Obviously the frontbuffer can't be pulled back, so that is either
- * an argument for blit/texture readpixels, or for blitting to a
- * temporary and then pulling that back.
- *
- * When the destination is a pbo, however, it's not clear if it is
- * ever going to be pulled to main memory (though the access param
- * will be a good hint).  So it sounds like we do want to be able to
- * choose between blit/texture implementation on the gpu and pullback
- * and cpu-based copying.
- *
- * Unless you can magically turn client memory into a PBO for the
- * duration of this call, there will be a cpu-based copying step in
- * any case.
- */
-
-
-static GLboolean
-do_texture_readpixels(GLcontext * ctx,
-                      GLint x, GLint y, GLsizei width, GLsizei height,
-                      GLenum format, GLenum type,
-                      const struct gl_pixelstore_attrib *pack,
-                      struct intel_region *dest_region)
-{
-#if 0
-   struct intel_context *intel = intel_context(ctx);
-   intelScreenPrivate *screen = intel->intelScreen;
-   GLint pitch = pack->RowLength ? pack->RowLength : width;
-   __DRIdrawablePrivate *dPriv = intel->driDrawable;
-   int textureFormat;
-   GLenum glTextureFormat;
-   int destFormat, depthFormat, destPitch;
-   drm_clip_rect_t tmp;
-
-   if (INTEL_DEBUG & DEBUG_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-
-   if (ctx->_ImageTransferState ||
-       pack->SwapBytes || pack->LsbFirst || !pack->Invert) {
-      if (INTEL_DEBUG & DEBUG_PIXEL)
-         fprintf(stderr, "%s: check_color failed\n", __FUNCTION__);
-      return GL_FALSE;
-   }
-
-   intel->vtbl.meta_texrect_source(intel, intel_readbuf_region(intel));
-
-   if (!intel->vtbl.meta_render_dest(intel, dest_region, type, format)) {
-      if (INTEL_DEBUG & DEBUG_PIXEL)
-         fprintf(stderr, "%s: couldn't set dest %s/%s\n",
-                 __FUNCTION__,
-                 _mesa_lookup_enum_by_nr(type),
-                 _mesa_lookup_enum_by_nr(format));
-      return GL_FALSE;
-   }
-
-   LOCK_HARDWARE(intel);
-
-   if (intel->driDrawable->numClipRects) {
-      intel->vtbl.install_meta_state(intel);
-      intel->vtbl.meta_no_depth_write(intel);
-      intel->vtbl.meta_no_stencil_write(intel);
-
-      if (!driClipRectToFramebuffer(ctx->ReadBuffer, &x, &y, &width, &height)) {
-         UNLOCK_HARDWARE(intel);
-         SET_STATE(i830, state);
-         if (INTEL_DEBUG & DEBUG_PIXEL)
-            fprintf(stderr, "%s: cliprect failed\n", __FUNCTION__);
-         return GL_TRUE;
-      }
-
-      y = dPriv->h - y - height;
-      x += dPriv->x;
-      y += dPriv->y;
-
-
-      /* Set the frontbuffer up as a large rectangular texture.
-       */
-      intel->vtbl.meta_tex_rect_source(intel, src_region, textureFormat);
-
-
-      intel->vtbl.meta_texture_blend_replace(i830, glTextureFormat);
-
-
-      /* Set the 3d engine to draw into the destination region:
-       */
-
-      intel->vtbl.meta_draw_region(intel, dest_region);
-      intel->vtbl.meta_draw_format(intel, destFormat, depthFormat);     /* ?? */
-
-
-      /* Draw a single quad, no cliprects:
-       */
-      intel->vtbl.meta_disable_cliprects(intel);
-
-      intel->vtbl.draw_quad(intel,
-                            0, width, 0, height,
-                            0x00ff00ff, x, x + width, y, y + height);
-
-      intel->vtbl.leave_meta_state(intel);
-   }
-   UNLOCK_HARDWARE(intel);
-
-   intel_region_wait_fence(ctx, dest_region);   /* required by GL */
-   return GL_TRUE;
-#endif
-
-   return GL_FALSE;
-}
-
-
-
-
-static GLboolean
-do_blit_readpixels(GLcontext * ctx,
-                   GLint x, GLint y, GLsizei width, GLsizei height,
-                   GLenum format, GLenum type,
-                   const struct gl_pixelstore_attrib *pack, GLvoid * pixels)
-{
-   struct intel_context *intel = intel_context(ctx);
-   struct intel_region *src = intel_readbuf_region(intel);
-   struct intel_buffer_object *dst = intel_buffer_object(pack->BufferObj);
-   GLuint dst_offset;
-   GLuint rowLength;
-
-   if (INTEL_DEBUG & DEBUG_PIXEL)
-      _mesa_printf("%s\n", __FUNCTION__);
-
-   if (!src)
-      return GL_FALSE;
-
-   if (dst) {
-      /* XXX This validation should be done by core mesa:
-       */
-      if (!_mesa_validate_pbo_access(2, pack, width, height, 1,
-                                     format, type, pixels)) {
-         _mesa_error(ctx, GL_INVALID_OPERATION, "glDrawPixels");
-         return GL_TRUE;
-      }
-   }
-   else {
-      /* PBO only for now:
-       */
-      if (INTEL_DEBUG & DEBUG_PIXEL)
-         _mesa_printf("%s - not PBO\n", __FUNCTION__);
-      return GL_FALSE;
-   }
-
-
-   if (ctx->_ImageTransferState ||
-       !intel_check_blit_format(src, format, type)) {
-      if (INTEL_DEBUG & DEBUG_PIXEL)
-         _mesa_printf("%s - bad format for blit\n", __FUNCTION__);
-      return GL_FALSE;
-   }
-
-   if (pack->Alignment != 1 || pack->SwapBytes || pack->LsbFirst) {
-      if (INTEL_DEBUG & DEBUG_PIXEL)
-         _mesa_printf("%s: bad packing params\n", __FUNCTION__);
-      return GL_FALSE;
-   }
-
-   if (pack->RowLength > 0)
-      rowLength = pack->RowLength;
-   else
-      rowLength = width;
-
-   if (pack->Invert) {
-      if (INTEL_DEBUG & DEBUG_PIXEL)
-         _mesa_printf("%s: MESA_PACK_INVERT not done yet\n", __FUNCTION__);
-      return GL_FALSE;
-   }
-   else {
-      rowLength = -rowLength;
-   }
-
-   /* XXX 64-bit cast? */
-   dst_offset = (GLuint) _mesa_image_address(2, pack, pixels, width, height,
-                                             format, type, 0, 0, 0);
-
-
-   /* Although the blits go on the command buffer, need to do this and
-    * fire with lock held to guarentee cliprects are correct.
-    */
-   intelFlush(&intel->ctx);
-   LOCK_HARDWARE(intel);
-
-   if (intel->driDrawable->numClipRects) {
-      GLboolean all = (width * height * src->cpp == dst->Base.Size &&
-                       x == 0 && dst_offset == 0);
-
-      dri_bo *dst_buffer = intel_bufferobj_buffer(intel, dst,
-						  all ? INTEL_WRITE_FULL :
-						  INTEL_WRITE_PART);
-      __DRIdrawablePrivate *dPriv = intel->driDrawable;
-      int nbox = dPriv->numClipRects;
-      drm_clip_rect_t *box = dPriv->pClipRects;
-      drm_clip_rect_t rect;
-      drm_clip_rect_t src_rect;
-      int i;
-
-      src_rect.x1 = dPriv->x + x;
-      src_rect.y1 = dPriv->y + dPriv->h - (y + height);
-      src_rect.x2 = src_rect.x1 + width;
-      src_rect.y2 = src_rect.y1 + height;
-
-
-
-      for (i = 0; i < nbox; i++) {
-         if (!intel_intersect_cliprects(&rect, &src_rect, &box[i]))
-            continue;
-
-         intelEmitCopyBlit(intel,
-                           src->cpp,
-                           src->pitch, src->buffer, 0, src->tiling,
-                           rowLength, dst_buffer, dst_offset, GL_FALSE,
-                           rect.x1,
-                           rect.y1,
-                           rect.x1 - src_rect.x1,
-                           rect.y2 - src_rect.y2,
-                           rect.x2 - rect.x1, rect.y2 - rect.y1,
-			   GL_COPY);
-      }
-   }
-   UNLOCK_HARDWARE(intel);
-
-   if (INTEL_DEBUG & DEBUG_PIXEL)
-      _mesa_printf("%s - DONE\n", __FUNCTION__);
-
-   return GL_TRUE;
-}
-
-void
-intelReadPixels(GLcontext * ctx,
-                GLint x, GLint y, GLsizei width, GLsizei height,
-                GLenum format, GLenum type,
-                const struct gl_pixelstore_attrib *pack, GLvoid * pixels)
-{
-   if (INTEL_DEBUG & DEBUG_PIXEL)
-      fprintf(stderr, "%s\n", __FUNCTION__);
-
-   intelFlush(ctx);
-
-   if (do_blit_readpixels
-       (ctx, x, y, width, height, format, type, pack, pixels))
-      return;
-
-   if (do_texture_readpixels
-       (ctx, x, y, width, height, format, type, pack, pixels))
-      return;
-
-   if (INTEL_DEBUG & DEBUG_PIXEL)
-      _mesa_printf("%s: fallback to swrast\n", __FUNCTION__);
-
-   _swrast_ReadPixels(ctx, x, y, width, height, format, type, pack, pixels);
-}
diff --git a/src/mesa/drivers/dri/i915/intel_pixel_read.c b/src/mesa/drivers/dri/i915/intel_pixel_read.c
new file mode 120000
index 0000000000..cc4589f4d4
--- /dev/null
+++ b/src/mesa/drivers/dri/i915/intel_pixel_read.c
@@ -0,0 +1 @@
+../intel/intel_pixel_read.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
new file mode 100644
index 0000000000..2c57b470f5
--- /dev/null
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -0,0 +1,306 @@
+/**************************************************************************
+ *
+ * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+#include "main/glheader.h"
+#include "main/enums.h"
+#include "main/mtypes.h"
+#include "main/macros.h"
+#include "main/image.h"
+#include "main/bufferobj.h"
+#include "swrast/swrast.h"
+
+#include "intel_screen.h"
+#include "intel_context.h"
+#include "intel_batchbuffer.h"
+#include "intel_blit.h"
+#include "intel_buffers.h"
+#include "intel_regions.h"
+#include "intel_pixel.h"
+#include "intel_buffer_objects.h"
+
+/* For many applications, the new ability to pull the source buffers
+ * back out of the GTT and then do the packing/conversion operations
+ * in software will be as much of an improvement as trying to get the
+ * blitter and/or texture engine to do the work.
+ *
+ * This step is gated on private backbuffers.
+ *
+ * Obviously the frontbuffer can't be pulled back, so that is either
+ * an argument for blit/texture readpixels, or for blitting to a
+ * temporary and then pulling that back.
+ *
+ * When the destination is a pbo, however, it's not clear if it is
+ * ever going to be pulled to main memory (though the access param
+ * will be a good hint).  So it sounds like we do want to be able to
+ * choose between blit/texture implementation on the gpu and pullback
+ * and cpu-based copying.
+ *
+ * Unless you can magically turn client memory into a PBO for the
+ * duration of this call, there will be a cpu-based copying step in
+ * any case.
+ */
+
+
+static GLboolean
+do_texture_readpixels(GLcontext * ctx,
+                      GLint x, GLint y, GLsizei width, GLsizei height,
+                      GLenum format, GLenum type,
+                      const struct gl_pixelstore_attrib *pack,
+                      struct intel_region *dest_region)
+{
+#if 0
+   struct intel_context *intel = intel_context(ctx);
+   intelScreenPrivate *screen = intel->intelScreen;
+   GLint pitch = pack->RowLength ? pack->RowLength : width;
+   __DRIdrawablePrivate *dPriv = intel->driDrawable;
+   int textureFormat;
+   GLenum glTextureFormat;
+   int destFormat, depthFormat, destPitch;
+   drm_clip_rect_t tmp;
+
+   if (INTEL_DEBUG & DEBUG_PIXEL)
+      fprintf(stderr, "%s\n", __FUNCTION__);
+
+
+   if (ctx->_ImageTransferState ||
+       pack->SwapBytes || pack->LsbFirst || !pack->Invert) {
+      if (INTEL_DEBUG & DEBUG_PIXEL)
+         fprintf(stderr, "%s: check_color failed\n", __FUNCTION__);
+      return GL_FALSE;
+   }
+
+   intel->vtbl.meta_texrect_source(intel, intel_readbuf_region(intel));
+
+   if (!intel->vtbl.meta_render_dest(intel, dest_region, type, format)) {
+      if (INTEL_DEBUG & DEBUG_PIXEL)
+         fprintf(stderr, "%s: couldn't set dest %s/%s\n",
+                 __FUNCTION__,
+                 _mesa_lookup_enum_by_nr(type),
+                 _mesa_lookup_enum_by_nr(format));
+      return GL_FALSE;
+   }
+
+   LOCK_HARDWARE(intel);
+
+   if (intel->driDrawable->numClipRects) {
+      intel->vtbl.install_meta_state(intel);
+      intel->vtbl.meta_no_depth_write(intel);
+      intel->vtbl.meta_no_stencil_write(intel);
+
+      if (!driClipRectToFramebuffer(ctx->ReadBuffer, &x, &y, &width, &height)) {
+         UNLOCK_HARDWARE(intel);
+         SET_STATE(i830, state);
+         if (INTEL_DEBUG & DEBUG_PIXEL)
+            fprintf(stderr, "%s: cliprect failed\n", __FUNCTION__);
+         return GL_TRUE;
+      }
+
+      y = dPriv->h - y - height;
+      x += dPriv->x;
+      y += dPriv->y;
+
+
+      /* Set the frontbuffer up as a large rectangular texture.
+       */
+      intel->vtbl.meta_tex_rect_source(intel, src_region, textureFormat);
+
+
+      intel->vtbl.meta_texture_blend_replace(i830, glTextureFormat);
+
+
+      /* Set the 3d engine to draw into the destination region:
+       */
+
+      intel->vtbl.meta_draw_region(intel, dest_region);
+      intel->vtbl.meta_draw_format(intel, destFormat, depthFormat);     /* ?? */
+
+
+      /* Draw a single quad, no cliprects:
+       */
+      intel->vtbl.meta_disable_cliprects(intel);
+
+      intel->vtbl.draw_quad(intel,
+                            0, width, 0, height,
+                            0x00ff00ff, x, x + width, y, y + height);
+
+      intel->vtbl.leave_meta_state(intel);
+   }
+   UNLOCK_HARDWARE(intel);
+
+   intel_region_wait_fence(ctx, dest_region);   /* required by GL */
+   return GL_TRUE;
+#endif
+
+   return GL_FALSE;
+}
+
+
+
+
+static GLboolean
+do_blit_readpixels(GLcontext * ctx,
+                   GLint x, GLint y, GLsizei width, GLsizei height,
+                   GLenum format, GLenum type,
+                   const struct gl_pixelstore_attrib *pack, GLvoid * pixels)
+{
+   struct intel_context *intel = intel_context(ctx);
+   struct intel_region *src = intel_readbuf_region(intel);
+   struct intel_buffer_object *dst = intel_buffer_object(pack->BufferObj);
+   GLuint dst_offset;
+   GLuint rowLength;
+
+   if (INTEL_DEBUG & DEBUG_PIXEL)
+      _mesa_printf("%s\n", __FUNCTION__);
+
+   if (!src)
+      return GL_FALSE;
+
+   if (dst) {
+      /* XXX This validation should be done by core mesa:
+       */
+      if (!_mesa_validate_pbo_access(2, pack, width, height, 1,
+                                     format, type, pixels)) {
+         _mesa_error(ctx, GL_INVALID_OPERATION, "glDrawPixels");
+         return GL_TRUE;
+      }
+   }
+   else {
+      /* PBO only for now:
+       */
+      if (INTEL_DEBUG & DEBUG_PIXEL)
+         _mesa_printf("%s - not PBO\n", __FUNCTION__);
+      return GL_FALSE;
+   }
+
+
+   if (ctx->_ImageTransferState ||
+       !intel_check_blit_format(src, format, type)) {
+      if (INTEL_DEBUG & DEBUG_PIXEL)
+         _mesa_printf("%s - bad format for blit\n", __FUNCTION__);
+      return GL_FALSE;
+   }
+
+   if (pack->Alignment != 1 || pack->SwapBytes || pack->LsbFirst) {
+      if (INTEL_DEBUG & DEBUG_PIXEL)
+         _mesa_printf("%s: bad packing params\n", __FUNCTION__);
+      return GL_FALSE;
+   }
+
+   if (pack->RowLength > 0)
+      rowLength = pack->RowLength;
+   else
+      rowLength = width;
+
+   if (pack->Invert) {
+      if (INTEL_DEBUG & DEBUG_PIXEL)
+         _mesa_printf("%s: MESA_PACK_INVERT not done yet\n", __FUNCTION__);
+      return GL_FALSE;
+   }
+   else {
+      rowLength = -rowLength;
+   }
+
+   /* XXX 64-bit cast? */
+   dst_offset = (GLuint) _mesa_image_address(2, pack, pixels, width, height,
+                                             format, type, 0, 0, 0);
+
+
+   /* Although the blits go on the command buffer, need to do this and
+    * fire with lock held to guarentee cliprects are correct.
+    */
+   intelFlush(&intel->ctx);
+   LOCK_HARDWARE(intel);
+
+   if (intel->driDrawable->numClipRects) {
+      GLboolean all = (width * height * src->cpp == dst->Base.Size &&
+                       x == 0 && dst_offset == 0);
+
+      dri_bo *dst_buffer = intel_bufferobj_buffer(intel, dst,
+						  all ? INTEL_WRITE_FULL :
+						  INTEL_WRITE_PART);
+      __DRIdrawablePrivate *dPriv = intel->driDrawable;
+      int nbox = dPriv->numClipRects;
+      drm_clip_rect_t *box = dPriv->pClipRects;
+      drm_clip_rect_t rect;
+      drm_clip_rect_t src_rect;
+      int i;
+
+      src_rect.x1 = dPriv->x + x;
+      src_rect.y1 = dPriv->y + dPriv->h - (y + height);
+      src_rect.x2 = src_rect.x1 + width;
+      src_rect.y2 = src_rect.y1 + height;
+
+
+
+      for (i = 0; i < nbox; i++) {
+         if (!intel_intersect_cliprects(&rect, &src_rect, &box[i]))
+            continue;
+
+         intelEmitCopyBlit(intel,
+                           src->cpp,
+                           src->pitch, src->buffer, 0, src->tiling,
+                           rowLength, dst_buffer, dst_offset, GL_FALSE,
+                           rect.x1,
+                           rect.y1,
+                           rect.x1 - src_rect.x1,
+                           rect.y2 - src_rect.y2,
+                           rect.x2 - rect.x1, rect.y2 - rect.y1,
+			   GL_COPY);
+      }
+   }
+   UNLOCK_HARDWARE(intel);
+
+   if (INTEL_DEBUG & DEBUG_PIXEL)
+      _mesa_printf("%s - DONE\n", __FUNCTION__);
+
+   return GL_TRUE;
+}
+
+void
+intelReadPixels(GLcontext * ctx,
+                GLint x, GLint y, GLsizei width, GLsizei height,
+                GLenum format, GLenum type,
+                const struct gl_pixelstore_attrib *pack, GLvoid * pixels)
+{
+   if (INTEL_DEBUG & DEBUG_PIXEL)
+      fprintf(stderr, "%s\n", __FUNCTION__);
+
+   intelFlush(ctx);
+
+   if (do_blit_readpixels
+       (ctx, x, y, width, height, format, type, pack, pixels))
+      return;
+
+   if (do_texture_readpixels
+       (ctx, x, y, width, height, format, type, pack, pixels))
+      return;
+
+   if (INTEL_DEBUG & DEBUG_PIXEL)
+      _mesa_printf("%s: fallback to swrast\n", __FUNCTION__);
+
+   _swrast_ReadPixels(ctx, x, y, width, height, format, type, pack, pixels);
+}
-- 
cgit v1.2.3


From 2855ee82c6d74066e8d9e44b17b2ce3b5782110e Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 19 Jun 2009 22:03:37 -0700
Subject: intel: Update Mesa state before span setup in glReadPixels.

We could have mapped the wrong set of draw buffers.  Noticed while looking
into a DRI2 glean ReadPixels issue.
(cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
---
 src/mesa/drivers/dri/i965/intel_pixel_read.c  |  1 +
 src/mesa/drivers/dri/intel/intel_pixel.c      |  4 +---
 src/mesa/drivers/dri/intel/intel_pixel_read.c | 11 +++++++++++
 3 files changed, 13 insertions(+), 3 deletions(-)
 create mode 120000 src/mesa/drivers/dri/i965/intel_pixel_read.c

diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c
new file mode 120000
index 0000000000..cc4589f4d4
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -0,0 +1 @@
+../intel/intel_pixel_read.c
\ No newline at end of file
diff --git a/src/mesa/drivers/dri/intel/intel_pixel.c b/src/mesa/drivers/dri/intel/intel_pixel.c
index fc0ac0b79c..defb80f85d 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel.c
@@ -342,10 +342,8 @@ intelInitPixelFuncs(struct dd_function_table *functions)
       functions->Bitmap = intelBitmap;
       functions->CopyPixels = intelCopyPixels;
       functions->DrawPixels = intelDrawPixels;
-#ifdef I915
-      functions->ReadPixels = intelReadPixels;
-#endif
    }
+   functions->ReadPixels = intelReadPixels;
 }
 
 void
diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
index 2c57b470f5..538da28c50 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -291,6 +291,7 @@ intelReadPixels(GLcontext * ctx,
 
    intelFlush(ctx);
 
+#ifdef I915
    if (do_blit_readpixels
        (ctx, x, y, width, height, format, type, pack, pixels))
       return;
@@ -298,9 +299,19 @@ intelReadPixels(GLcontext * ctx,
    if (do_texture_readpixels
        (ctx, x, y, width, height, format, type, pack, pixels))
       return;
+#endif
 
    if (INTEL_DEBUG & DEBUG_PIXEL)
       _mesa_printf("%s: fallback to swrast\n", __FUNCTION__);
 
+   /* Update Mesa state before calling down into _swrast_ReadPixels, as
+    * the spans code requires the computed buffer states to be up to date,
+    * but _swrast_ReadPixels only updates Mesa state after setting up
+    * the spans code.
+    */
+
+   if (ctx->NewState)
+      _mesa_update_state(ctx);
+
    _swrast_ReadPixels(ctx, x, y, width, height, format, type, pack, pixels);
 }
-- 
cgit v1.2.3


From cf820a045f0626718ec147ebb26e31f82ec0b4fb Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 19 Jun 2009 22:12:52 -0700
Subject: intel: Also get the DRI2 front buffer when doing front buffer
 reading. (cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)

---
 src/mesa/drivers/dri/i965/Makefile         |  1 +
 src/mesa/drivers/dri/intel/intel_buffers.c | 17 +++++++++++++++++
 src/mesa/drivers/dri/intel/intel_context.c |  4 +++-
 src/mesa/drivers/dri/intel/intel_context.h |  8 ++++++++
 4 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile
index 2934414d99..81c2fdb0dc 100644
--- a/src/mesa/drivers/dri/i965/Makefile
+++ b/src/mesa/drivers/dri/i965/Makefile
@@ -22,6 +22,7 @@ DRIVER_SOURCES = \
 	intel_pixel_bitmap.c \
 	intel_pixel_copy.c \
 	intel_pixel_draw.c \
+	intel_pixel_read.c \
 	intel_state.c \
 	intel_swapbuffers.c \
 	intel_tex.c \
diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c
index d2fad9e4ea..44e34330a6 100644
--- a/src/mesa/drivers/dri/intel/intel_buffers.c
+++ b/src/mesa/drivers/dri/intel/intel_buffers.c
@@ -345,6 +345,23 @@ intelDrawBuffer(GLcontext * ctx, GLenum mode)
 static void
 intelReadBuffer(GLcontext * ctx, GLenum mode)
 {
+   if ((ctx->DrawBuffer != NULL) && (ctx->DrawBuffer->Name == 0)) {
+      struct intel_context *const intel = intel_context(ctx);
+      const GLboolean was_front_buffer_reading =
+	intel->is_front_buffer_reading;
+
+      intel->is_front_buffer_reading = (mode == GL_FRONT_LEFT)
+	|| (mode == GL_FRONT);
+
+      /* If we weren't front-buffer reading before but we are now, make sure
+       * that the front-buffer has actually been allocated.
+       */
+      if (!was_front_buffer_reading && intel->is_front_buffer_reading) {
+	 intel_update_renderbuffers(intel->driContext,
+				    intel->driContext->driDrawablePriv);
+      }
+   }
+
    if (ctx->ReadBuffer == ctx->DrawBuffer) {
       /* This will update FBO completeness status.
        * A framebuffer will be incomplete if the GL_READ_BUFFER setting
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 50ae677d20..977fad9313 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -220,7 +220,9 @@ intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
       struct intel_renderbuffer *stencil_rb;
 
       i = 0;
-      if ((intel->is_front_buffer_rendering || !intel_fb->color_rb[1])
+      if ((intel->is_front_buffer_rendering ||
+	   intel->is_front_buffer_reading ||
+	   !intel_fb->color_rb[1])
 	   && intel_fb->color_rb[0]) {
 	 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
 	 attachments[i++] = intel_bits_per_pixel(intel_fb->color_rb[0]);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index b3db561fd5..e2b3943fb5 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -295,6 +295,14 @@ struct intel_context
     * easily.
     */
    GLboolean is_front_buffer_rendering;
+   /**
+    * Track whether front-buffer is the current read target.
+    *
+    * This is closely associated with is_front_buffer_rendering, but may
+    * be set separately.  The DRI2 fake front buffer must be referenced
+    * either way.
+    */
+   GLboolean is_front_buffer_reading;
 
    drm_clip_rect_t fboRect;     /**< cliprect for FBO rendering */
 
-- 
cgit v1.2.3


From b2cba25f9eecf2063c3b98d66ade59cd9e50990e Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Mon, 22 Jun 2009 08:52:52 -0700
Subject: i965: Fix warnings in intel_pixel_read.c. (cherry picked from commit
 c80ce5ac90b1e0ac7a72cd41c314aa2000bfecf5)

---
 src/mesa/drivers/dri/intel/intel_pixel_read.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c
index 538da28c50..0370255614 100644
--- a/src/mesa/drivers/dri/intel/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c
@@ -31,6 +31,7 @@
 #include "main/macros.h"
 #include "main/image.h"
 #include "main/bufferobj.h"
+#include "main/state.h"
 #include "swrast/swrast.h"
 
 #include "intel_screen.h"
@@ -299,6 +300,9 @@ intelReadPixels(GLcontext * ctx,
    if (do_texture_readpixels
        (ctx, x, y, width, height, format, type, pack, pixels))
       return;
+#else
+   (void)do_blit_readpixels;
+   (void)do_texture_readpixels;
 #endif
 
    if (INTEL_DEBUG & DEBUG_PIXEL)
-- 
cgit v1.2.3


From bf19638a003f0915d3d5419b737c2006a8f24a31 Mon Sep 17 00:00:00 2001
From: Peter Hutterer <peter.hutterer@who-t.net>
Date: Mon, 7 Sep 2009 10:49:31 +1000
Subject: prog/glsl: fix Makefile for samplers_array.

The rule added in 488b3c4d1bc3d830477180759a42dbaf8f5801b0 does not use the
right INCDIR, breaking the build when GL isn't installed in the default include
paths.

7.5 branch only fix, already fixed in master by rewriting the Makefile
(ceb9459ed5e63207defa5d715958c2757933272f)

Signed-off-by: Peter Hutterer <peter.hutterer@who-t.net>
---
 progs/glsl/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/progs/glsl/Makefile b/progs/glsl/Makefile
index 6af7a665cf..37ccf8a9ea 100644
--- a/progs/glsl/Makefile
+++ b/progs/glsl/Makefile
@@ -190,7 +190,7 @@ samplers: samplers.o $(UTIL_OBJS)
 
 
 samplers_array.o: samplers.c $(UTIL_HEADERS)
-	$(APP_CC) $(CFLAGS) -DSAMPLERS_ARRAY $< -c -o $@
+	$(APP_CC) -I$(INCDIR) $(CFLAGS) -DSAMPLERS_ARRAY $< -c -o $@
 
 samplers_array: samplers_array.o $(UTIL_OBJS)
 
-- 
cgit v1.2.3


From 18bdb6e712d43632dcd2e73cea68e0b2953fe62e Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 8 Sep 2009 09:20:39 -0600
Subject: egl: also use X types for building on Apple/MacOS X

See bug 20413.
---
 include/EGL/eglplatform.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/EGL/eglplatform.h b/include/EGL/eglplatform.h
index 83e89cd704..9e83b60003 100644
--- a/include/EGL/eglplatform.h
+++ b/include/EGL/eglplatform.h
@@ -69,7 +69,8 @@ typedef HWND	NativeWindowType;
 typedef HBITMAP NativePixmapType;
 /** END Added for Windows **/
 
-#elif defined(__gnu_linux__) || defined(__FreeBSD__) || defined(__sun)
+#elif defined(__gnu_linux__) || defined(__FreeBSD__) || defined(__sun) || defined(__APPLE__)
+
 
 /** BEGIN Added for X (Mesa) **/
 #ifndef EGLAPI
-- 
cgit v1.2.3


From 8de625c7cf639c583e8bf43acb1214010989bb64 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 8 Sep 2009 12:21:42 -0600
Subject: i965: fix incorrect test for vertex position attribute

---
 src/mesa/drivers/dri/i965/brw_context.h     | 2 ++
 src/mesa/drivers/dri/i965/brw_draw.c        | 1 +
 src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index e52fc3f374..5cf12fb353 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -386,6 +386,8 @@ struct brw_cached_batch_item {
 struct brw_vertex_element {
    const struct gl_client_array *glarray;
 
+   /** The corresponding Mesa vertex attribute */
+   gl_vert_attrib attrib;
    /** Size of a complete element */
    GLuint element_size;
    /** Number of uploaded elements for this input. */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 5342622a73..54b0661db8 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -185,6 +185,7 @@ static void brw_merge_inputs( struct brw_context *brw,
 
    for (i = 0; i < VERT_ATTRIB_MAX; i++) {
       brw->vb.inputs[i].glarray = arrays[i];
+      brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
 
       if (arrays[i]->StrideB != 0)
 	 brw->vb.info.varying |= 1 << i;
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 05079c043a..fd9c3915c4 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -422,7 +422,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
 	 /* Queue the buffer object up to be uploaded in the next pass,
 	  * when we've decided if we're doing interleaved or not.
 	  */
-	 if (i == 0) {
+	 if (input->attrib == VERT_ATTRIB_POS) {
 	    /* Position array not properly enabled:
 	     */
             if (input->glarray->StrideB == 0) {
-- 
cgit v1.2.3


From 42943a4cf90d66ade212feea29a29a3702eec6c1 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Tue, 8 Sep 2009 14:45:24 -0600
Subject: mesa: bump version to 7.5.2

I'm not 100% sure there'll be a 7.5.2 release, but just in case.
---
 Makefile                | 2 +-
 configs/default         | 2 +-
 src/mesa/main/version.h | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index 6ad07e6137..636be5c28c 100644
--- a/Makefile
+++ b/Makefile
@@ -182,7 +182,7 @@ ultrix-gcc:
 
 # Rules for making release tarballs
 
-VERSION=7.5.1
+VERSION=7.5.2
 DIRECTORY = Mesa-$(VERSION)
 LIB_NAME = MesaLib-$(VERSION)
 DEMO_NAME = MesaDemos-$(VERSION)
diff --git a/configs/default b/configs/default
index 2981bb9a8f..773a6204d3 100644
--- a/configs/default
+++ b/configs/default
@@ -10,7 +10,7 @@ CONFIG_NAME = default
 # Version info
 MESA_MAJOR=7
 MESA_MINOR=5
-MESA_TINY=1
+MESA_TINY=2
 MESA_VERSION = $(MESA_MAJOR).$(MESA_MINOR).$(MESA_TINY)
 
 # external projects.  This should be useless now that we use libdrm.
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 50c1143ccc..995e46d318 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -1,6 +1,6 @@
 /*
  * Mesa 3-D graphics library
- * Version:  7.5.1
+ * Version:  7.5.2
  *
  * Copyright (C) 1999-2009  Brian Paul   All Rights Reserved.
  *
@@ -30,8 +30,8 @@
 /* Mesa version */
 #define MESA_MAJOR 7
 #define MESA_MINOR 5
-#define MESA_PATCH 1
-#define MESA_VERSION_STRING "7.5.1"
+#define MESA_PATCH 2
+#define MESA_VERSION_STRING "7.5.2-devel"
 
 /* To make version comparison easy */
 #define MESA_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
-- 
cgit v1.2.3


From d27d659043bd7f2bd9a2636209f299cda0664230 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Wed, 9 Sep 2009 08:21:05 -0600
Subject: scons: Set default_dri to no for Mac OS.

Mac OS does not have libdrm.
---
 common.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/common.py b/common.py
index a687efc86f..ccb962981d 100644
--- a/common.py
+++ b/common.py
@@ -33,9 +33,9 @@ else:
 	default_machine = _platform.machine()
 default_machine = _machine_map.get(default_machine, 'generic')
 
-if default_platform in ('linux', 'freebsd', 'darwin'):
+if default_platform in ('linux', 'freebsd'):
 	default_dri = 'yes'
-elif default_platform in ('winddk', 'windows', 'wince'):
+elif default_platform in ('winddk', 'windows', 'wince', 'darwin'):
 	default_dri = 'no'
 else:
 	default_dri = 'no'
-- 
cgit v1.2.3