From 8c27d99eb84709013f420a7500ddfdef71ac7391 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 4 Jun 2009 20:22:14 -0400 Subject: re-arrange state structure - split out renderbuffers - split out shaders - split our viewports Only send the state needed. --- src/mesa/drivers/dri/r600/r700_chip.c | 646 ++++++++++++++---------------- src/mesa/drivers/dri/r600/r700_chip.h | 426 +++++++++----------- src/mesa/drivers/dri/r600/r700_fragprog.c | 10 +- src/mesa/drivers/dri/r600/r700_render.c | 21 +- src/mesa/drivers/dri/r600/r700_state.c | 117 +++--- src/mesa/drivers/dri/r600/r700_state.h | 2 +- src/mesa/drivers/dri/r600/r700_vertprog.c | 6 +- 7 files changed, 557 insertions(+), 671 deletions(-) diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c index 5737847439..7fd557ca8e 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.c +++ b/src/mesa/drivers/dri/r600/r700_chip.c @@ -57,122 +57,105 @@ GLboolean r700InitChipObject(context_t *context) r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int)); pStateListWork = r700->pStateList; - LINK_STATES(DB_DEPTH_SIZE); - LINK_STATES(DB_DEPTH_VIEW); - - LINK_STATES(DB_DEPTH_BASE); - LINK_STATES(DB_DEPTH_INFO); + // DB + LINK_STATES(DB_DEPTH_SIZE); + LINK_STATES(DB_DEPTH_VIEW); + LINK_STATES(DB_DEPTH_BASE); + LINK_STATES(DB_DEPTH_INFO); LINK_STATES(DB_HTILE_DATA_BASE); - LINK_STATES(DB_STENCIL_CLEAR); - LINK_STATES(DB_DEPTH_CLEAR); - - LINK_STATES(PA_SC_SCREEN_SCISSOR_TL); - LINK_STATES(PA_SC_SCREEN_SCISSOR_BR); - - LINK_STATES(CB_COLOR0_BASE); - - LINK_STATES(CB_COLOR0_SIZE); - - LINK_STATES(CB_COLOR0_VIEW); - - LINK_STATES(CB_COLOR0_INFO); - LINK_STATES(CB_COLOR1_INFO); - LINK_STATES(CB_COLOR2_INFO); - LINK_STATES(CB_COLOR3_INFO); - LINK_STATES(CB_COLOR4_INFO); - LINK_STATES(CB_COLOR5_INFO); - LINK_STATES(CB_COLOR6_INFO); - LINK_STATES(CB_COLOR7_INFO); - - LINK_STATES(CB_COLOR0_TILE); - - LINK_STATES(CB_COLOR0_FRAG); - - LINK_STATES(CB_COLOR0_MASK); + LINK_STATES(DB_DEPTH_CLEAR); + LINK_STATES(DB_DEPTH_CONTROL); + LINK_STATES(DB_SHADER_CONTROL); + LINK_STATES(DB_RENDER_CONTROL); + LINK_STATES(DB_RENDER_OVERRIDE); + LINK_STATES(DB_HTILE_SURFACE); + LINK_STATES(DB_ALPHA_TO_MASK); + // SC + LINK_STATES(PA_SC_SCREEN_SCISSOR_TL); + LINK_STATES(PA_SC_SCREEN_SCISSOR_BR); LINK_STATES(PA_SC_WINDOW_OFFSET); - LINK_STATES(PA_SC_WINDOW_SCISSOR_TL); - LINK_STATES(PA_SC_WINDOW_SCISSOR_BR); - LINK_STATES(PA_SC_CLIPRECT_RULE); - LINK_STATES(PA_SC_CLIPRECT_0_TL); - LINK_STATES(PA_SC_CLIPRECT_0_BR); - LINK_STATES(PA_SC_CLIPRECT_1_TL); - LINK_STATES(PA_SC_CLIPRECT_1_BR); - LINK_STATES(PA_SC_CLIPRECT_2_TL); - LINK_STATES(PA_SC_CLIPRECT_2_BR); - LINK_STATES(PA_SC_CLIPRECT_3_TL); - LINK_STATES(PA_SC_CLIPRECT_3_BR); - - LINK_STATES(PA_SC_EDGERULE); - - LINK_STATES(CB_TARGET_MASK); - LINK_STATES(CB_SHADER_MASK); - LINK_STATES(PA_SC_GENERIC_SCISSOR_TL); - LINK_STATES(PA_SC_GENERIC_SCISSOR_BR); - - LINK_STATES(PA_SC_VPORT_SCISSOR_0_TL); - LINK_STATES(PA_SC_VPORT_SCISSOR_0_BR); - LINK_STATES(PA_SC_VPORT_SCISSOR_1_TL); - LINK_STATES(PA_SC_VPORT_SCISSOR_1_BR); - - LINK_STATES(PA_SC_VPORT_ZMIN_0); - LINK_STATES(PA_SC_VPORT_ZMAX_0); - - LINK_STATES(SX_MISC); - - LINK_STATES(SQ_VTX_SEMANTIC_0); - LINK_STATES(SQ_VTX_SEMANTIC_1); - LINK_STATES(SQ_VTX_SEMANTIC_2); - LINK_STATES(SQ_VTX_SEMANTIC_3); - LINK_STATES(SQ_VTX_SEMANTIC_4); - LINK_STATES(SQ_VTX_SEMANTIC_5); - LINK_STATES(SQ_VTX_SEMANTIC_6); - LINK_STATES(SQ_VTX_SEMANTIC_7); - LINK_STATES(SQ_VTX_SEMANTIC_8); - LINK_STATES(SQ_VTX_SEMANTIC_9); - LINK_STATES(SQ_VTX_SEMANTIC_10); - LINK_STATES(SQ_VTX_SEMANTIC_11); - LINK_STATES(SQ_VTX_SEMANTIC_12); - LINK_STATES(SQ_VTX_SEMANTIC_13); - LINK_STATES(SQ_VTX_SEMANTIC_14); - LINK_STATES(SQ_VTX_SEMANTIC_15); - LINK_STATES(SQ_VTX_SEMANTIC_16); - LINK_STATES(SQ_VTX_SEMANTIC_17); - LINK_STATES(SQ_VTX_SEMANTIC_18); - LINK_STATES(SQ_VTX_SEMANTIC_19); - LINK_STATES(SQ_VTX_SEMANTIC_20); - LINK_STATES(SQ_VTX_SEMANTIC_21); - LINK_STATES(SQ_VTX_SEMANTIC_22); - LINK_STATES(SQ_VTX_SEMANTIC_23); - LINK_STATES(SQ_VTX_SEMANTIC_24); - LINK_STATES(SQ_VTX_SEMANTIC_25); - LINK_STATES(SQ_VTX_SEMANTIC_26); - LINK_STATES(SQ_VTX_SEMANTIC_27); - LINK_STATES(SQ_VTX_SEMANTIC_28); - LINK_STATES(SQ_VTX_SEMANTIC_29); - LINK_STATES(SQ_VTX_SEMANTIC_30); - LINK_STATES(SQ_VTX_SEMANTIC_31); - - LINK_STATES(VGT_MAX_VTX_INDX); - LINK_STATES(VGT_MIN_VTX_INDX); - LINK_STATES(VGT_INDX_OFFSET); - LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX); - LINK_STATES(SX_ALPHA_TEST_CONTROL); - - LINK_STATES(CB_BLEND_RED); + LINK_STATES(PA_SC_WINDOW_SCISSOR_TL); + LINK_STATES(PA_SC_WINDOW_SCISSOR_BR); + LINK_STATES(PA_SC_CLIPRECT_RULE); + LINK_STATES(PA_SC_CLIPRECT_0_TL); + LINK_STATES(PA_SC_CLIPRECT_0_BR); + LINK_STATES(PA_SC_CLIPRECT_1_TL); + LINK_STATES(PA_SC_CLIPRECT_1_BR); + LINK_STATES(PA_SC_CLIPRECT_2_TL); + LINK_STATES(PA_SC_CLIPRECT_2_BR); + LINK_STATES(PA_SC_CLIPRECT_3_TL); + LINK_STATES(PA_SC_CLIPRECT_3_BR); + LINK_STATES(PA_SC_EDGERULE); + LINK_STATES(PA_SC_GENERIC_SCISSOR_TL); + LINK_STATES(PA_SC_GENERIC_SCISSOR_BR); + LINK_STATES(PA_SC_LINE_STIPPLE); + LINK_STATES(PA_SC_MPASS_PS_CNTL); + LINK_STATES(PA_SC_MODE_CNTL); + LINK_STATES(PA_SC_LINE_CNTL); + LINK_STATES(PA_SC_AA_CONFIG); + LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX); + LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX); + LINK_STATES(PA_SC_AA_MASK); + + // SU + LINK_STATES(PA_SU_POINT_SIZE); + LINK_STATES(PA_SU_POINT_MINMAX); + LINK_STATES(PA_SU_LINE_CNTL); + LINK_STATES(PA_SU_SC_MODE_CNTL); + LINK_STATES(PA_SU_VTX_CNTL); + LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL); + LINK_STATES(PA_SU_POLY_OFFSET_CLAMP); + LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE); + LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET); + LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE); + + // CL + LINK_STATES(PA_CL_CLIP_CNTL); + LINK_STATES(PA_CL_VTE_CNTL); + LINK_STATES(PA_CL_VS_OUT_CNTL); + LINK_STATES(PA_CL_NANINF_CNTL); + LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ); + LINK_STATES(PA_CL_GB_VERT_DISC_ADJ); + LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ); + LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ); + + // CB + LINK_STATES(CB_TARGET_MASK); + LINK_STATES(CB_SHADER_MASK); + LINK_STATES(CB_BLEND_RED); LINK_STATES(CB_BLEND_GREEN); - LINK_STATES(CB_BLEND_BLUE); + LINK_STATES(CB_BLEND_BLUE); LINK_STATES(CB_BLEND_ALPHA); + LINK_STATES(CB_SHADER_CONTROL); + LINK_STATES(CB_COLOR_CONTROL); + LINK_STATES(CB_CLRCMP_CONTROL); + LINK_STATES(CB_CLRCMP_SRC); + LINK_STATES(CB_CLRCMP_DST); + LINK_STATES(CB_CLRCMP_MSK); + + // SX + LINK_STATES(SX_MISC); + LINK_STATES(SX_ALPHA_TEST_CONTROL); + + // VGT + LINK_STATES(VGT_MAX_VTX_INDX); + LINK_STATES(VGT_MIN_VTX_INDX); + LINK_STATES(VGT_INDX_OFFSET); + LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX); + LINK_STATES(VGT_OUTPUT_PATH_CNTL); + LINK_STATES(VGT_GS_MODE); + LINK_STATES(VGT_PRIMITIVEID_EN); + LINK_STATES(VGT_DMA_NUM_INSTANCES); + LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); + LINK_STATES(VGT_INSTANCE_STEP_RATE_0); + LINK_STATES(VGT_INSTANCE_STEP_RATE_1); + LINK_STATES(VGT_STRMOUT_EN); + LINK_STATES(VGT_REUSE_OFF); - LINK_STATES(PA_CL_VPORT_XSCALE); - LINK_STATES(PA_CL_VPORT_XOFFSET); - LINK_STATES(PA_CL_VPORT_YSCALE); - LINK_STATES(PA_CL_VPORT_YOFFSET); - LINK_STATES(PA_CL_VPORT_ZSCALE); - LINK_STATES(PA_CL_VPORT_ZOFFSET); - - LINK_STATES(SPI_VS_OUT_ID_0); + // SPI + LINK_STATES(SPI_VS_OUT_ID_0); LINK_STATES(SPI_VS_OUT_ID_1); LINK_STATES(SPI_VS_OUT_ID_2); LINK_STATES(SPI_VS_OUT_ID_3); @@ -182,152 +165,33 @@ GLboolean r700InitChipObject(context_t *context) LINK_STATES(SPI_VS_OUT_ID_7); LINK_STATES(SPI_VS_OUT_ID_8); LINK_STATES(SPI_VS_OUT_ID_9); - - LINK_STATES(SPI_PS_INPUT_CNTL_0); - LINK_STATES(SPI_PS_INPUT_CNTL_1); - LINK_STATES(SPI_PS_INPUT_CNTL_2); - LINK_STATES(SPI_PS_INPUT_CNTL_3); - LINK_STATES(SPI_PS_INPUT_CNTL_4); - LINK_STATES(SPI_PS_INPUT_CNTL_5); - LINK_STATES(SPI_PS_INPUT_CNTL_6); - LINK_STATES(SPI_PS_INPUT_CNTL_7); - LINK_STATES(SPI_PS_INPUT_CNTL_8); - LINK_STATES(SPI_PS_INPUT_CNTL_9); - LINK_STATES(SPI_PS_INPUT_CNTL_10); - LINK_STATES(SPI_PS_INPUT_CNTL_11); - LINK_STATES(SPI_PS_INPUT_CNTL_12); - LINK_STATES(SPI_PS_INPUT_CNTL_13); - LINK_STATES(SPI_PS_INPUT_CNTL_14); - LINK_STATES(SPI_PS_INPUT_CNTL_15); - LINK_STATES(SPI_PS_INPUT_CNTL_16); - LINK_STATES(SPI_PS_INPUT_CNTL_17); - LINK_STATES(SPI_PS_INPUT_CNTL_18); - LINK_STATES(SPI_PS_INPUT_CNTL_19); - LINK_STATES(SPI_PS_INPUT_CNTL_20); - LINK_STATES(SPI_PS_INPUT_CNTL_21); - LINK_STATES(SPI_PS_INPUT_CNTL_22); - LINK_STATES(SPI_PS_INPUT_CNTL_23); - LINK_STATES(SPI_PS_INPUT_CNTL_24); - LINK_STATES(SPI_PS_INPUT_CNTL_25); - LINK_STATES(SPI_PS_INPUT_CNTL_26); - LINK_STATES(SPI_PS_INPUT_CNTL_27); - LINK_STATES(SPI_PS_INPUT_CNTL_28); - LINK_STATES(SPI_PS_INPUT_CNTL_29); - LINK_STATES(SPI_PS_INPUT_CNTL_30); - LINK_STATES(SPI_PS_INPUT_CNTL_31); - LINK_STATES(SPI_VS_OUT_CONFIG); + LINK_STATES(SPI_VS_OUT_CONFIG); LINK_STATES(SPI_THREAD_GROUPING); - LINK_STATES(SPI_PS_IN_CONTROL_0); + LINK_STATES(SPI_PS_IN_CONTROL_0); LINK_STATES(SPI_PS_IN_CONTROL_1); LINK_STATES(SPI_INTERP_CONTROL_0); - - LINK_STATES(SPI_INPUT_Z); + LINK_STATES(SPI_INPUT_Z); LINK_STATES(SPI_FOG_CNTL); - LINK_STATES(CB_BLEND0_CONTROL); - - LINK_STATES(CB_SHADER_CONTROL); - - /*LINK_STATES(VGT_DRAW_INITIATOR); */ - - LINK_STATES(DB_DEPTH_CONTROL); - - LINK_STATES(CB_COLOR_CONTROL); - LINK_STATES(DB_SHADER_CONTROL); - LINK_STATES(PA_CL_CLIP_CNTL); - LINK_STATES(PA_SU_SC_MODE_CNTL); - LINK_STATES(PA_CL_VTE_CNTL); - LINK_STATES(PA_CL_VS_OUT_CNTL); - LINK_STATES(PA_CL_NANINF_CNTL); - - LINK_STATES(SQ_PGM_START_PS); - LINK_STATES(SQ_PGM_RESOURCES_PS); - LINK_STATES(SQ_PGM_EXPORTS_PS); - LINK_STATES(SQ_PGM_START_VS); - LINK_STATES(SQ_PGM_RESOURCES_VS); - LINK_STATES(SQ_PGM_START_GS); - LINK_STATES(SQ_PGM_RESOURCES_GS); - LINK_STATES(SQ_PGM_START_ES); - LINK_STATES(SQ_PGM_RESOURCES_ES); - LINK_STATES(SQ_PGM_START_FS); - LINK_STATES(SQ_PGM_RESOURCES_FS); - LINK_STATES(SQ_ESGS_RING_ITEMSIZE); - LINK_STATES(SQ_GSVS_RING_ITEMSIZE); + // SQ + LINK_STATES(SQ_ESGS_RING_ITEMSIZE); + LINK_STATES(SQ_GSVS_RING_ITEMSIZE); LINK_STATES(SQ_ESTMP_RING_ITEMSIZE); LINK_STATES(SQ_GSTMP_RING_ITEMSIZE); LINK_STATES(SQ_VSTMP_RING_ITEMSIZE); LINK_STATES(SQ_PSTMP_RING_ITEMSIZE); - LINK_STATES(SQ_FBUF_RING_ITEMSIZE); + LINK_STATES(SQ_FBUF_RING_ITEMSIZE); LINK_STATES(SQ_REDUC_RING_ITEMSIZE); - LINK_STATES(SQ_GS_VERT_ITEMSIZE); - LINK_STATES(SQ_PGM_CF_OFFSET_PS); - LINK_STATES(SQ_PGM_CF_OFFSET_VS); - LINK_STATES(SQ_PGM_CF_OFFSET_GS); - LINK_STATES(SQ_PGM_CF_OFFSET_ES); - LINK_STATES(SQ_PGM_CF_OFFSET_FS); - - LINK_STATES(PA_SU_POINT_SIZE); - LINK_STATES(PA_SU_POINT_MINMAX); - LINK_STATES(PA_SU_LINE_CNTL); - LINK_STATES(PA_SC_LINE_STIPPLE); - LINK_STATES(VGT_OUTPUT_PATH_CNTL); - - LINK_STATES(VGT_GS_MODE); - - LINK_STATES(PA_SC_MPASS_PS_CNTL); - LINK_STATES(PA_SC_MODE_CNTL); - - LINK_STATES(VGT_PRIMITIVEID_EN); - LINK_STATES(VGT_DMA_NUM_INSTANCES); - - LINK_STATES(VGT_MULTI_PRIM_IB_RESET_EN); - - LINK_STATES(VGT_INSTANCE_STEP_RATE_0); - LINK_STATES(VGT_INSTANCE_STEP_RATE_1); - - LINK_STATES(VGT_STRMOUT_EN); - LINK_STATES(VGT_REUSE_OFF); - - LINK_STATES(PA_SC_LINE_CNTL); - LINK_STATES(PA_SC_AA_CONFIG); - LINK_STATES(PA_SU_VTX_CNTL); - LINK_STATES(PA_CL_GB_VERT_CLIP_ADJ); - LINK_STATES(PA_CL_GB_VERT_DISC_ADJ); - LINK_STATES(PA_CL_GB_HORZ_CLIP_ADJ); - LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ); - LINK_STATES(PA_SC_AA_SAMPLE_LOCS_MCTX); - LINK_STATES(PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX); - - LINK_STATES(CB_CLRCMP_CONTROL); - LINK_STATES(CB_CLRCMP_SRC); - LINK_STATES(CB_CLRCMP_DST); - LINK_STATES(CB_CLRCMP_MSK); - - LINK_STATES(PA_SC_AA_MASK); - - LINK_STATES(DB_RENDER_CONTROL); - LINK_STATES(DB_RENDER_OVERRIDE); - - LINK_STATES(DB_HTILE_SURFACE); - - LINK_STATES(DB_ALPHA_TO_MASK); - - LINK_STATES(PA_SU_POLY_OFFSET_DB_FMT_CNTL); - LINK_STATES(PA_SU_POLY_OFFSET_CLAMP); - LINK_STATES(PA_SU_POLY_OFFSET_FRONT_SCALE); - LINK_STATES(PA_SU_POLY_OFFSET_FRONT_OFFSET); - LINK_STATES(PA_SU_POLY_OFFSET_BACK_SCALE); + //LINK_STATES(SQ_GS_VERT_ITEMSIZE); - pStateListWork->puiValue = (unsigned int*)&(r700->PA_SU_POLY_OFFSET_BACK_OFFSET); - pStateListWork->unOffset = mmPA_SU_POLY_OFFSET_BACK_OFFSET - ASIC_CONTEXT_BASE_INDEX; + pStateListWork->puiValue = (unsigned int*)&(r700->SQ_GS_VERT_ITEMSIZE); + pStateListWork->unOffset = mmSQ_GS_VERT_ITEMSIZE - ASIC_CONTEXT_BASE_INDEX; pStateListWork->pNext = NULL; /* END OF STATE LIST */ - /* TODO : may need order sorting in case someone break the order of states in R700_CHIP_CONTEXT. */ - return GL_TRUE; } -void r700SetupVTXConstants(GLcontext * ctx, +void r700SetupVTXConstants(GLcontext * ctx, unsigned int nStreamID, void * pAos, unsigned int size, /* number of elements in vector */ @@ -348,37 +212,37 @@ void r700SetupVTXConstants(GLcontext * ctx, unsigned int uSQ_VTX_CONSTANT_WORD6_0 = 0; uSQ_VTX_CONSTANT_WORD0_0 = paos->offset; - uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; - - uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ - |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift - |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ - |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift - |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; - - uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; - - uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; + uSQ_VTX_CONSTANT_WORD1_0 = count * stride - 1; + + uSQ_VTX_CONSTANT_WORD2_0 |= 0 << BASE_ADDRESS_HI_shift /* TODO */ + |stride << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift + |GetSurfaceFormat(GL_FLOAT, size, NULL) << SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift /* TODO : trace back api for initial data type, not only GL_FLOAT */ + |SQ_NUM_FORMAT_SCALED << SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL_shift + |SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL_bit; + + uSQ_VTX_CONSTANT_WORD3_0 |= 1 << MEM_REQUEST_SIZE_shift; + + uSQ_VTX_CONSTANT_WORD6_0 |= SQ_TEX_VTX_VALID_BUFFER << SQ_TEX_RESOURCE_WORD6_0__TYPE_shift; BEGIN_BATCH_NO_AUTOSTATE(9); - R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7)); R600_OUT_BATCH((nStreamID + SQ_FETCH_RESOURCE_VS_OFFSET) * FETCH_RESOURCE_STRIDE); - R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, - paos->bo, - uSQ_VTX_CONSTANT_WORD0_0, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); - R600_OUT_BATCH(0); - R600_OUT_BATCH(0); - R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); + R600_OUT_BATCH_RELOC(uSQ_VTX_CONSTANT_WORD0_0, + paos->bo, + uSQ_VTX_CONSTANT_WORD0_0, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD1_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD2_0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD3_0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(0); + R600_OUT_BATCH(uSQ_VTX_CONSTANT_WORD6_0); END_BATCH(); COMMIT_BATCH(); - + } int r700SetupStreams(GLcontext * ctx) @@ -411,17 +275,17 @@ int r700SetupStreams(GLcontext * ctx) for(i=0; imesa_program.Base.InputsRead & unBit) - { - rcommon_emit_vector(ctx, + if(vpc->mesa_program.Base.InputsRead & unBit) + { + rcommon_emit_vector(ctx, &context->radeon.tcl.aos[i], vb->AttribPtr[i]->data, vb->AttribPtr[i]->size, - vb->AttribPtr[i]->stride, + vb->AttribPtr[i]->stride, vb->Count); /* currently aos are packed */ - r700SetupVTXConstants(ctx, + r700SetupVTXConstants(ctx, i, (void*)(&context->radeon.tcl.aos[i]), (unsigned int)vb->AttribPtr[i]->size, @@ -429,13 +293,13 @@ int r700SetupStreams(GLcontext * ctx) (unsigned int)vb->Count); } } - + return R600_FALLBACK_NONE; } inline GLboolean needRelocReg(context_t *context, unsigned int reg) { - switch (reg + ASIC_CONTEXT_BASE_INDEX) + switch (reg + ASIC_CONTEXT_BASE_INDEX) { case mmCB_COLOR0_BASE: case mmCB_COLOR1_BASE: @@ -444,13 +308,13 @@ inline GLboolean needRelocReg(context_t *context, unsigned int reg) case mmCB_COLOR4_BASE: case mmCB_COLOR5_BASE: case mmCB_COLOR6_BASE: - case mmCB_COLOR7_BASE: + case mmCB_COLOR7_BASE: case mmDB_DEPTH_BASE: - case mmSQ_PGM_START_VS: - case mmSQ_PGM_START_FS: - case mmSQ_PGM_START_ES: - case mmSQ_PGM_START_GS: - case mmSQ_PGM_START_PS: + case mmSQ_PGM_START_VS: + case mmSQ_PGM_START_FS: + case mmSQ_PGM_START_ES: + case mmSQ_PGM_START_GS: + case mmSQ_PGM_START_PS: return GL_TRUE; break; } @@ -467,39 +331,8 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg) uint32_t voffset; offset_modifiers offset_mod; - switch (reg + ASIC_CONTEXT_BASE_INDEX) + switch (reg + ASIC_CONTEXT_BASE_INDEX) { - case mmCB_COLOR0_BASE: - case mmCB_COLOR1_BASE: - case mmCB_COLOR2_BASE: - case mmCB_COLOR3_BASE: - case mmCB_COLOR4_BASE: - case mmCB_COLOR5_BASE: - case mmCB_COLOR6_BASE: - case mmCB_COLOR7_BASE: - { - GLcontext *ctx = GL_CONTEXT(context); - struct radeon_renderbuffer *rrb; - - rrb = radeon_get_colorbuffer(&context->radeon); - if (!rrb || !rrb->bo) - { - fprintf(stderr, "no rrb\n"); - return GL_FALSE; - } - - /* refer to radeonCreateScreen : screen->fbLocation = (temp & 0xffff) << 16; */ - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - - R600_OUT_BATCH_RELOC(r700->CB_COLOR0_BASE.u32All, - rrb->bo, - r700->CB_COLOR0_BASE.u32All, - 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); - return GL_TRUE; - } - break; case mmDB_DEPTH_BASE: { GLcontext *ctx = GL_CONTEXT(context); @@ -510,48 +343,14 @@ inline GLboolean setRelocReg(context_t *context, unsigned int reg) offset_mod.shiftbits = 0; offset_mod.mask = 0xFFFFFFFF; - R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, - rrb->bo, - r700->DB_DEPTH_BASE.u32All, + R600_OUT_BATCH_RELOC(r700->DB_DEPTH_BASE.u32All, + rrb->bo, + r700->DB_DEPTH_BASE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); return GL_TRUE; } break; - case mmSQ_PGM_START_VS: - { - pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); - - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - - R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_VS.u32All, - pbo, - r700->SQ_PGM_START_VS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - return GL_TRUE; - } - break; - case mmSQ_PGM_START_FS: - case mmSQ_PGM_START_ES: - case mmSQ_PGM_START_GS: - case mmSQ_PGM_START_PS: - { - pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); - - offset_mod.shift = NO_SHIFT; - offset_mod.shiftbits = 0; - offset_mod.mask = 0xFFFFFFFF; - - voffset = 0; - R600_OUT_BATCH_RELOC(r700->SQ_PGM_START_PS.u32All, - pbo, - r700->SQ_PGM_START_PS.u32All, - RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); - return GL_TRUE; - } - break; } return GL_FALSE; @@ -566,7 +365,7 @@ GLboolean r700SendContextStates(context_t *context) ContextState * pState = r700->pStateList; ContextState * pInit; unsigned int toSend; - unsigned int ui; + unsigned int ui; while(NULL != pState) { @@ -612,5 +411,162 @@ GLboolean r700SendContextStates(context_t *context) } +GLboolean r700SendRenderTargetState(context_t *context, int id) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + rrb = radeon_get_colorbuffer(&context->radeon); + if (!rrb || !rrb->bo) { + fprintf(stderr, "no rrb\n"); + return GL_FALSE; + } + + if (id > R700_MAX_RENDER_TARGETS) + return GL_FALSE; + + if (!r700->render_target[id].enabled) + return GL_FALSE; + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGSEQ(CB_COLOR0_BASE + (4 * id), 1); + R600_OUT_BATCH_RELOC(r700->render_target[id].CB_COLOR0_BASE.u32All, + rrb->bo, + r700->render_target[id].CB_COLOR0_BASE.u32All, + 0, RADEON_GEM_DOMAIN_VRAM, 0, &offset_mod); + END_BATCH(); + + if ((context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) && + (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)) { + BEGIN_BATCH_NO_AUTOSTATE(2); + R600_OUT_BATCH(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); + R600_OUT_BATCH((2 << id)); + END_BATCH(); + } + + BEGIN_BATCH_NO_AUTOSTATE(18); + R600_OUT_BATCH_REGVAL(CB_COLOR0_SIZE + (4 * id), r700->render_target[id].CB_COLOR0_SIZE.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_VIEW + (4 * id), r700->render_target[id].CB_COLOR0_VIEW.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_INFO + (4 * id), r700->render_target[id].CB_COLOR0_INFO.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_TILE + (4 * id), r700->render_target[id].CB_COLOR0_TILE.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_FRAG + (4 * id), r700->render_target[id].CB_COLOR0_FRAG.u32All); + R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All); + END_BATCH(); + + if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) { + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All); + END_BATCH(); + } + + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendPSState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + pbo = (struct radeon_bo *)r700GetActiveFpShaderBo(GL_CONTEXT(context)); + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGSEQ(SQ_PGM_START_PS, 1); + R600_OUT_BATCH_RELOC(r700->ps.SQ_PGM_START_PS.u32All, + pbo, + r700->ps.SQ_PGM_START_PS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(9); + R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_PS, r700->ps.SQ_PGM_RESOURCES_PS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_EXPORTS_PS, r700->ps.SQ_PGM_EXPORTS_PS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_PS, r700->ps.SQ_PGM_CF_OFFSET_PS.u32All); + END_BATCH(); + + COMMIT_BATCH(); + + return GL_TRUE; +} + +GLboolean r700SendVSState(context_t *context) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + pbo = (struct radeon_bo *)r700GetActiveVpShaderBo(GL_CONTEXT(context)); + + offset_mod.shift = NO_SHIFT; + offset_mod.shiftbits = 0; + offset_mod.mask = 0xFFFFFFFF; + + BEGIN_BATCH_NO_AUTOSTATE(3); + R600_OUT_BATCH_REGSEQ(SQ_PGM_START_VS, 1); + R600_OUT_BATCH_RELOC(r700->vs.SQ_PGM_START_VS.u32All, + pbo, + r700->vs.SQ_PGM_START_VS.u32All, + RADEON_GEM_DOMAIN_GTT, 0, 0, &offset_mod); + END_BATCH(); + + BEGIN_BATCH_NO_AUTOSTATE(6); + R600_OUT_BATCH_REGVAL(SQ_PGM_RESOURCES_VS, r700->vs.SQ_PGM_RESOURCES_VS.u32All); + R600_OUT_BATCH_REGVAL(SQ_PGM_CF_OFFSET_VS, r700->vs.SQ_PGM_CF_OFFSET_VS.u32All); + END_BATCH(); + + COMMIT_BATCH(); + + return GL_TRUE; +} +GLboolean r700SendViewportState(context_t *context, int id) +{ + R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context); + struct radeon_renderbuffer *rrb; + struct radeon_bo * pbo; + offset_modifiers offset_mod; + BATCH_LOCALS(&context->radeon); + + if (id > R700_MAX_VIEWPORTS) + return GL_FALSE; + + if (!r700->viewport[id].enabled) + return GL_FALSE; + + BEGIN_BATCH_NO_AUTOSTATE(16); + R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_SCISSOR_0_TL + (8 * id), 2); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All); + R600_OUT_BATCH_REGSEQ(PA_SC_VPORT_ZMIN_0 + (8 * id), 2); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All); + R600_OUT_BATCH_REGSEQ(PA_CL_VPORT_XSCALE_0 + (24 * id), 6); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XSCALE.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_XOFFSET.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YSCALE.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_YOFFSET.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZSCALE.u32All); + R600_OUT_BATCH(r700->viewport[id].PA_CL_VPORT_ZOFFSET.u32All); + END_BATCH(); + COMMIT_BATCH(); + + return GL_TRUE; +} diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h index 4ceada7378..2129c0bdf4 100644 --- a/src/mesa/drivers/dri/r600/r700_chip.h +++ b/src/mesa/drivers/dri/r600/r700_chip.h @@ -42,6 +42,10 @@ #define CLEARbit(x, bit) ( (x) &= ~(bit) ) #define R700_TEXTURE_NUMBERUNITS 16 +#define R700_MAX_RENDER_TARGETS 8 +#define R700_MAX_VIEWPORTS 16 +#define R700_MAX_SHADER_EXPORTS 32 +#define R700_MAX_UCP 6 /* Enum not show in r600_*.h */ @@ -170,6 +174,79 @@ typedef struct _R700_TEXTURE_STATES SAMPLER_STATE_STRUCT *samplers[R700_TEXTURE_NUMBERUNITS]; } R700_TEXTURE_STATES; +typedef struct _RENDER_TARGET_STATE_STRUCT +{ + union UINT_FLOAT CB_COLOR0_BASE; /* 0xA010 */ + union UINT_FLOAT CB_COLOR0_SIZE; /* 0xA018 */ + union UINT_FLOAT CB_COLOR0_VIEW; /* 0xA020 */ + union UINT_FLOAT CB_COLOR0_INFO; /* 0xA028 */ + union UINT_FLOAT CB_COLOR0_TILE; /* 0xA030 */ + union UINT_FLOAT CB_COLOR0_FRAG; /* 0xA038 */ + union UINT_FLOAT CB_COLOR0_MASK; /* 0xA040 */ + union UINT_FLOAT CB_BLEND0_CONTROL; /* 0xA1E0 */ + GLboolean enabled; +} RENDER_TARGET_STATE_STRUCT; + +typedef struct _VIEWPORT_STATE_STRUCT +{ + union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; /* 0xA094 */ + union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; /* 0xA095 */ + union UINT_FLOAT PA_SC_VPORT_ZMIN_0; /* 0xA0B4 */ + union UINT_FLOAT PA_SC_VPORT_ZMAX_0; /* 0xA0B5 */ + union UINT_FLOAT PA_CL_VPORT_XSCALE; /* 0xA10F */ + union UINT_FLOAT PA_CL_VPORT_XOFFSET; /* 0xA110 */ + union UINT_FLOAT PA_CL_VPORT_YSCALE; /* 0xA111 */ + union UINT_FLOAT PA_CL_VPORT_YOFFSET; /* 0xA112 */ + union UINT_FLOAT PA_CL_VPORT_ZSCALE; /* 0xA113 */ + union UINT_FLOAT PA_CL_VPORT_ZOFFSET; /* 0xA114 */ + GLboolean enabled; +} VIEWPORT_STATE_STRUCT; + +typedef struct _UCP_STATE_STRUCT +{ + union UINT_FLOAT PA_CL_UCP_0_X; + union UINT_FLOAT PA_CL_UCP_0_Y; + union UINT_FLOAT PA_CL_UCP_0_Z; + union UINT_FLOAT PA_CL_UCP_0_W; + GLboolean enabled; +} UCP_STATE_STRUCT; + +typedef struct _PS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */ + union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */ + union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ +} PS_STATE_STRUCT; + +typedef struct _VS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */ + union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ +} VS_STATE_STRUCT; + +typedef struct _GS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */ + union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */ +} GS_STATE_STRUCT; + +typedef struct _ES_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */ + union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */ +} ES_STATE_STRUCT; + +typedef struct _FS_STATE_STRUCT +{ + union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */ + union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */ + union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */ +} FS_STATE_STRUCT; + typedef struct ContextState { unsigned int * puiValue; @@ -179,43 +256,27 @@ typedef struct ContextState typedef struct _R700_CHIP_CONTEXT { + // DB union UINT_FLOAT DB_DEPTH_SIZE ; /* 0xA000 */ union UINT_FLOAT DB_DEPTH_VIEW ; /* 0xA001 */ - union UINT_FLOAT DB_DEPTH_BASE ; /* 0xA003 */ union UINT_FLOAT DB_DEPTH_INFO ; /* 0xA004 */ - union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */ - - union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */ + union UINT_FLOAT DB_HTILE_DATA_BASE ; /* 0xA005 */ + union UINT_FLOAT DB_STENCIL_CLEAR ; /* 0xA00A */ union UINT_FLOAT DB_DEPTH_CLEAR ; /* 0xA00B */ - - union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */ - union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */ - - union UINT_FLOAT CB_COLOR0_BASE ; /* 0xA010 */ - - union UINT_FLOAT CB_COLOR0_SIZE ; /* 0xA018 */ - - union UINT_FLOAT CB_COLOR0_VIEW ; /* 0xA020 */ - - union UINT_FLOAT CB_COLOR0_INFO ; /* 0xA028 */ - union UINT_FLOAT CB_COLOR1_INFO ; /* 0xA029 */ - union UINT_FLOAT CB_COLOR2_INFO ; /* 0xA02A */ - union UINT_FLOAT CB_COLOR3_INFO ; /* 0xA02B */ - union UINT_FLOAT CB_COLOR4_INFO ; /* 0xA02C */ - union UINT_FLOAT CB_COLOR5_INFO ; /* 0xA02D */ - union UINT_FLOAT CB_COLOR6_INFO ; /* 0xA02E */ - union UINT_FLOAT CB_COLOR7_INFO ; /* 0xA02F */ - - union UINT_FLOAT CB_COLOR0_TILE ; /* 0xA030 */ - - union UINT_FLOAT CB_COLOR0_FRAG ; /* 0xA038 */ - - union UINT_FLOAT CB_COLOR0_MASK ; /* 0xA040 */ - - union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */ - union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */ - union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */ + union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */ + union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */ + union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */ + union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */ + union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */ + union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */ + + // SC + union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL ; /* 0xA00C */ + union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR ; /* 0xA00D */ + union UINT_FLOAT PA_SC_WINDOW_OFFSET ; /* 0xA080 */ + union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL ; /* 0xA081 */ + union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR ; /* 0xA082 */ union UINT_FLOAT PA_SC_CLIPRECT_RULE ; /* 0xA083 */ union UINT_FLOAT PA_SC_CLIPRECT_0_TL ; /* 0xA084 */ union UINT_FLOAT PA_SC_CLIPRECT_0_BR ; /* 0xA085 */ @@ -225,78 +286,82 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT PA_SC_CLIPRECT_2_BR ; /* 0xA089 */ union UINT_FLOAT PA_SC_CLIPRECT_3_TL ; /* 0xA08A */ union UINT_FLOAT PA_SC_CLIPRECT_3_BR ; /* 0xA08B */ - union UINT_FLOAT PA_SC_EDGERULE ; /* 0xA08C */ + union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */ + union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */ + union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */ + union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */ + union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */ + union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */ + union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */ + union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */ + union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */ + union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */ + // CL + union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */ + union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */ + union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */ + union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */ + union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */ + union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */ + union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */ + union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */ + + // SU + union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */ + union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */ + union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */ + union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */ + union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */ + union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */ + union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */ + union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */ + + VIEWPORT_STATE_STRUCT viewport[R700_MAX_VIEWPORTS]; + UCP_STATE_STRUCT ucp[R700_MAX_UCP]; + + // CB union UINT_FLOAT CB_TARGET_MASK ; /* 0xA08E */ union UINT_FLOAT CB_SHADER_MASK ; /* 0xA08F */ - union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL ; /* 0xA090 */ - union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR ; /* 0xA091 */ - - union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL ; /* 0xA094 */ - union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR ; /* 0xA095 */ - union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_TL ; /* 0xA096 */ - union UINT_FLOAT PA_SC_VPORT_SCISSOR_1_BR ; /* 0xA097 */ - - union UINT_FLOAT PA_SC_VPORT_ZMIN_0 ; /* 0xA0B4 */ - union UINT_FLOAT PA_SC_VPORT_ZMAX_0 ; /* 0xA0B5 */ - - union UINT_FLOAT SX_MISC ; /* 0xA0D4 */ - - union UINT_FLOAT SQ_VTX_SEMANTIC_0 ; /* 0xA0E0 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_1 ; /* 0xA0E1 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_2 ; /* 0xA0E2 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_3 ; /* 0xA0E3 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_4 ; /* 0xA0E4 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_5 ; /* 0xA0E5 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_6 ; /* 0xA0E6 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_7 ; /* 0xA0E7 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_8 ; /* 0xA0E8 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_9 ; /* 0xA0E9 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_10 ; /* 0xA0EA */ - union UINT_FLOAT SQ_VTX_SEMANTIC_11 ; /* 0xA0EB */ - union UINT_FLOAT SQ_VTX_SEMANTIC_12 ; /* 0xA0EC */ - union UINT_FLOAT SQ_VTX_SEMANTIC_13 ; /* 0xA0ED */ - union UINT_FLOAT SQ_VTX_SEMANTIC_14 ; /* 0xA0EE */ - union UINT_FLOAT SQ_VTX_SEMANTIC_15 ; /* 0xA0EF */ - union UINT_FLOAT SQ_VTX_SEMANTIC_16 ; /* 0xA0F0 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_17 ; /* 0xA0F1 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_18 ; /* 0xA0F2 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_19 ; /* 0xA0F3 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_20 ; /* 0xA0F4 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_21 ; /* 0xA0F5 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_22 ; /* 0xA0F6 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_23 ; /* 0xA0F7 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_24 ; /* 0xA0F8 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_25 ; /* 0xA0F9 */ - union UINT_FLOAT SQ_VTX_SEMANTIC_26 ; /* 0xA0FA */ - union UINT_FLOAT SQ_VTX_SEMANTIC_27 ; /* 0xA0FB */ - union UINT_FLOAT SQ_VTX_SEMANTIC_28 ; /* 0xA0FC */ - union UINT_FLOAT SQ_VTX_SEMANTIC_29 ; /* 0xA0FD */ - union UINT_FLOAT SQ_VTX_SEMANTIC_30 ; /* 0xA0FE */ - union UINT_FLOAT SQ_VTX_SEMANTIC_31 ; /* 0xA0FF */ + union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */ + union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */ + union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */ + union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */ + union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */ + union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */ + union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */ + union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */ + union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */ + union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */ + RENDER_TARGET_STATE_STRUCT render_target[R700_MAX_RENDER_TARGETS]; + + // SX + union UINT_FLOAT SX_MISC ; /* 0xA0D4 */ + union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */ + // VGT union UINT_FLOAT VGT_MAX_VTX_INDX ; /* 0xA100 */ union UINT_FLOAT VGT_MIN_VTX_INDX ; /* 0xA101 */ union UINT_FLOAT VGT_INDX_OFFSET ; /* 0xA102 */ - union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */ - union UINT_FLOAT SX_ALPHA_TEST_CONTROL ; /* 0xA104 */ + union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; /* 0xA103 */ + union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */ + union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */ + union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */ + union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */ + union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */ + union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */ + union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */ + union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */ + union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */ - union UINT_FLOAT CB_BLEND_RED ; /* 0xA105 */ - union UINT_FLOAT CB_BLEND_GREEN ; /* 0xA106 */ - union UINT_FLOAT CB_BLEND_BLUE ; /* 0xA107 */ - union UINT_FLOAT CB_BLEND_ALPHA ; /* 0xA108 */ - - union UINT_FLOAT PA_CL_VPORT_XSCALE ; /* 0xA10F */ - union UINT_FLOAT PA_CL_VPORT_XOFFSET ; /* 0xA110 */ - union UINT_FLOAT PA_CL_VPORT_YSCALE ; /* 0xA111 */ - union UINT_FLOAT PA_CL_VPORT_YOFFSET ; /* 0xA112 */ - union UINT_FLOAT PA_CL_VPORT_ZSCALE ; /* 0xA113 */ - union UINT_FLOAT PA_CL_VPORT_ZOFFSET ; /* 0xA114 */ - + // SPI union UINT_FLOAT SPI_VS_OUT_ID_0 ; /* 0xA185 */ union UINT_FLOAT SPI_VS_OUT_ID_1 ; /* 0xA186 */ - union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */ + union UINT_FLOAT SPI_VS_OUT_ID_2 ; /* 0xA187 */ union UINT_FLOAT SPI_VS_OUT_ID_3 ; /* 0xA188 */ union UINT_FLOAT SPI_VS_OUT_ID_4 ; /* 0xA189 */ union UINT_FLOAT SPI_VS_OUT_ID_5 ; /* 0xA18A */ @@ -304,149 +369,40 @@ typedef struct _R700_CHIP_CONTEXT union UINT_FLOAT SPI_VS_OUT_ID_7 ; /* 0xA18C */ union UINT_FLOAT SPI_VS_OUT_ID_8 ; /* 0xA18D */ union UINT_FLOAT SPI_VS_OUT_ID_9 ; /* 0xA18E */ - - union UINT_FLOAT SPI_PS_INPUT_CNTL_0 ; /* 0xA191 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_1 ; /* 0xA192 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_2 ; /* 0xA193 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_3 ; /* 0xA194 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_4 ; /* 0xA195 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_5 ; /* 0xA196 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_6 ; /* 0xA197 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_7 ; /* 0xA198 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_8 ; /* 0xA199 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_9 ; /* 0xA19A */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_10 ; /* 0xA19B */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_11 ; /* 0xA19C */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_12 ; /* 0xA19D */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_13 ; /* 0xA19E */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_14 ; /* 0xA19F */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_15 ; /* 0xA1A0 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_16 ; /* 0xA1A1 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_17 ; /* 0xA1A2 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_18 ; /* 0xA1A3 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_19 ; /* 0xA1A4 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_20 ; /* 0xA1A5 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_21 ; /* 0xA1A6 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_22 ; /* 0xA1A7 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_23 ; /* 0xA1A8 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_24 ; /* 0xA1A9 */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_25 ; /* 0xA1AA */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_26 ; /* 0xA1AB */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_27 ; /* 0xA1AC */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_28 ; /* 0xA1AD */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_29 ; /* 0xA1AE */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_30 ; /* 0xA1AF */ - union UINT_FLOAT SPI_PS_INPUT_CNTL_31 ; /* 0xA1B0 */ - union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */ - union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */ - union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */ - union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */ - union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */ - - union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */ - union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */ - - union UINT_FLOAT CB_BLEND0_CONTROL ; /* 0xA1E0 */ - - union UINT_FLOAT CB_SHADER_CONTROL ; /* 0xA1E8 */ - - /*union UINT_FLOAT VGT_DRAW_INITIATOR*/ ; /* 0xA1FC */ - - union UINT_FLOAT DB_DEPTH_CONTROL ; /* 0xA200 */ - - union UINT_FLOAT CB_COLOR_CONTROL ; /* 0xA202 */ - union UINT_FLOAT DB_SHADER_CONTROL ; /* 0xA203 */ - union UINT_FLOAT PA_CL_CLIP_CNTL ; /* 0xA204 */ - union UINT_FLOAT PA_SU_SC_MODE_CNTL ; /* 0xA205 */ - union UINT_FLOAT PA_CL_VTE_CNTL ; /* 0xA206 */ - union UINT_FLOAT PA_CL_VS_OUT_CNTL ; /* 0xA207 */ - union UINT_FLOAT PA_CL_NANINF_CNTL ; /* 0xA208 */ - - union UINT_FLOAT SQ_PGM_START_PS ; /* 0xA210 */ - union UINT_FLOAT SQ_PGM_RESOURCES_PS ; /* 0xA214 */ - union UINT_FLOAT SQ_PGM_EXPORTS_PS ; /* 0xA215 */ - union UINT_FLOAT SQ_PGM_START_VS ; /* 0xA216 */ - union UINT_FLOAT SQ_PGM_RESOURCES_VS ; /* 0xA21A */ - union UINT_FLOAT SQ_PGM_START_GS ; /* 0xA21B */ - union UINT_FLOAT SQ_PGM_RESOURCES_GS ; /* 0xA21F */ - union UINT_FLOAT SQ_PGM_START_ES ; /* 0xA220 */ - union UINT_FLOAT SQ_PGM_RESOURCES_ES ; /* 0xA224 */ - union UINT_FLOAT SQ_PGM_START_FS ; /* 0xA225 */ - union UINT_FLOAT SQ_PGM_RESOURCES_FS ; /* 0xA229 */ - union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */ - union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */ - union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */ - union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */ - union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */ - union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */ - union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */ - union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */ - union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_PS ; /* 0xA233 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_VS ; /* 0xA234 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_GS ; /* 0xA235 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_ES ; /* 0xA236 */ - union UINT_FLOAT SQ_PGM_CF_OFFSET_FS ; /* 0xA237 */ - - union UINT_FLOAT PA_SU_POINT_SIZE ; /* 0xA280 */ - union UINT_FLOAT PA_SU_POINT_MINMAX ; /* 0xA281 */ - union UINT_FLOAT PA_SU_LINE_CNTL ; /* 0xA282 */ - union UINT_FLOAT PA_SC_LINE_STIPPLE ; /* 0xA283 */ - union UINT_FLOAT VGT_OUTPUT_PATH_CNTL ; /* 0xA284 */ - - union UINT_FLOAT VGT_GS_MODE ; /* 0xA290 */ - - union UINT_FLOAT PA_SC_MPASS_PS_CNTL ; /* 0xA292 */ - union UINT_FLOAT PA_SC_MODE_CNTL ; /* 0xA293 */ - - union UINT_FLOAT VGT_PRIMITIVEID_EN ; /* 0xA2A1 */ - union UINT_FLOAT VGT_DMA_NUM_INSTANCES ; /* 0xA2A2 */ - - union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; /* 0xA2A5 */ - - union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0 ; /* 0xA2A8 */ - union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1 ; /* 0xA2A9 */ - - union UINT_FLOAT VGT_STRMOUT_EN ; /* 0xA2AC */ - union UINT_FLOAT VGT_REUSE_OFF ; /* 0xA2AD */ - - union UINT_FLOAT PA_SC_LINE_CNTL ; /* 0xA300 */ - union UINT_FLOAT PA_SC_AA_CONFIG ; /* 0xA301 */ - union UINT_FLOAT PA_SU_VTX_CNTL ; /* 0xA302 */ - union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ ; /* 0xA303 */ - union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ ; /* 0xA304 */ - union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ ; /* 0xA305 */ - union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ ; /* 0xA306 */ - union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_MCTX ; /* 0xA307 */ - union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX; /* 0xA308 */ - - union UINT_FLOAT CB_CLRCMP_CONTROL ; /* 0xA30C */ - union UINT_FLOAT CB_CLRCMP_SRC ; /* 0xA30D */ - union UINT_FLOAT CB_CLRCMP_DST ; /* 0xA30E */ - union UINT_FLOAT CB_CLRCMP_MSK ; /* 0xA30F */ - - union UINT_FLOAT PA_SC_AA_MASK ; /* 0xA312 */ - - union UINT_FLOAT DB_RENDER_CONTROL ; /* 0xA343 */ - union UINT_FLOAT DB_RENDER_OVERRIDE ; /* 0xA344 */ - - union UINT_FLOAT DB_HTILE_SURFACE ; /* 0xA349 */ - - union UINT_FLOAT DB_ALPHA_TO_MASK ; /* 0xA351 */ - - union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; /* 0xA37E */ - union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP ; /* 0xA37F */ - union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE; /* 0xA380 */ - union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; /* 0xA381 */ - union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; /* 0xA382 */ - union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; /* 0xA383 */ - - ContextState * pStateList; - - R700_TEXTURE_STATES texture_states; + union UINT_FLOAT SPI_VS_OUT_CONFIG ; /* 0xA1B1 */ + union UINT_FLOAT SPI_THREAD_GROUPING ; /* 0xA1B2 */ + union UINT_FLOAT SPI_PS_IN_CONTROL_0 ; /* 0xA1B3 */ + union UINT_FLOAT SPI_PS_IN_CONTROL_1 ; /* 0xA1B4 */ + union UINT_FLOAT SPI_INTERP_CONTROL_0 ; /* 0xA1B5 */ + union UINT_FLOAT SPI_INPUT_Z ; /* 0xA1B6 */ + union UINT_FLOAT SPI_FOG_CNTL ; /* 0xA1B7 */ + union UINT_FLOAT SQ_VTX_SEMANTIC[R700_MAX_SHADER_EXPORTS]; + union UINT_FLOAT SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS]; + + // shaders + PS_STATE_STRUCT ps; + VS_STATE_STRUCT vs; + GS_STATE_STRUCT gs; + ES_STATE_STRUCT es; + PS_STATE_STRUCT fs; + + // SQ + union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE ; /* 0xA22A */ + union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE ; /* 0xA22B */ + union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE ; /* 0xA22C */ + union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE ; /* 0xA22D */ + union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE ; /* 0xA22E */ + union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE ; /* 0xA22F */ + union UINT_FLOAT SQ_FBUF_RING_ITEMSIZE ; /* 0xA230 */ + union UINT_FLOAT SQ_REDUC_RING_ITEMSIZE ; /* 0xA231 */ + union UINT_FLOAT SQ_GS_VERT_ITEMSIZE ; /* 0xA232 */ + + ContextState* pStateList; + + R700_TEXTURE_STATES texture_states; + + GLboolean bEnablePerspective; - GLboolean bEnablePerspective; - } R700_CHIP_CONTEXT; #endif /* _R700_CHIP_H_ */ diff --git a/src/mesa/drivers/dri/r600/r700_fragprog.c b/src/mesa/drivers/dri/r600/r700_fragprog.c index cebb82d853..0eea2567d5 100644 --- a/src/mesa/drivers/dri/r600/r700_fragprog.c +++ b/src/mesa/drivers/dri/r600/r700_fragprog.c @@ -293,7 +293,7 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, fp->shadercode.buf->id); */ - r700->SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ + r700->ps.SQ_PGM_START_PS.u32All = 0; /* set from buffer obj */ unNumOfReg = fp->r700Shader.nRegs + 1; @@ -301,17 +301,17 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx) ui = ui ? unNumOfReg : ui; - SETfield(r700->SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); + SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask); - CLEARbit(r700->SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit); + CLEARbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit); if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ { - SETfield(r700->SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize, + SETfield(r700->ps.SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize, STACK_SIZE_shift, STACK_SIZE_mask); } - SETfield(r700->SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, + SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode, EXPORT_MODE_shift, EXPORT_MODE_mask); if(fp->r700Shader.killIsUsed) diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c index 3a4328fdfe..2c67006217 100644 --- a/src/mesa/drivers/dri/r600/r700_render.c +++ b/src/mesa/drivers/dri/r600/r700_render.c @@ -112,17 +112,17 @@ static GLboolean r700SetupShaders(GLcontext * ctx) GLuint exportCount; - r700->SQ_PGM_RESOURCES_PS.u32All = 0; - r700->SQ_PGM_RESOURCES_VS.u32All = 0; + r700->ps.SQ_PGM_RESOURCES_PS.u32All = 0; + r700->vs.SQ_PGM_RESOURCES_VS.u32All = 0; - SETbit(r700->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); - SETbit(r700->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + SETbit(r700->ps.SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); + SETbit(r700->vs.SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit); r700SetupVertexProgram(ctx); r700SetupFragmentProgram(ctx); - exportCount = (r700->SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); + exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift); r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1; return GL_TRUE; @@ -259,7 +259,7 @@ static GLboolean r700RunRender(GLcontext * ctx, r700UpdateShaders(ctx); r700SetScissor(context); - r700SetRenderTarget(context); + r700SetRenderTarget(context, 0); r700SetDepthTarget(context); if(r700SetupStreams(ctx)) @@ -287,15 +287,16 @@ static GLboolean r700RunRender(GLcontext * ctx, r700SetupShaders(ctx); - /* set a valid base address to make the command checker happy */ - r700->SQ_PGM_START_FS.u32All = r700->SQ_PGM_START_PS.u32All; - r700->SQ_PGM_START_ES.u32All = r700->SQ_PGM_START_PS.u32All; - r700->SQ_PGM_START_GS.u32All = r700->SQ_PGM_START_PS.u32All; + r700SendPSState(context); + r700SendVSState(context); /* flush vtx */ //r700SyncSurf(context); /* */ r700SendContextStates(context); + r700SendViewportState(context); + r700SendRenderTargetState(context, 0); + /* richard test code */ for (i = 0; i < vb->PrimitiveCount; i++) diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 3556d6811c..17e99bf5e1 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -522,7 +522,7 @@ static void r700StencilOpSeparate(GLcontext * ctx, GLenum face, { } -static void r700UpdateWindow(GLcontext * ctx) //-------------------- +static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- { context_t *context = R700_CONTEXT(ctx); @@ -552,14 +552,16 @@ static void r700UpdateWindow(GLcontext * ctx) //-------------------- /* TODO : Need DMA flush as well. */ - r700->PA_CL_VPORT_XSCALE.f32All = sx; - r700->PA_CL_VPORT_XOFFSET.f32All = tx; + r700->viewport[id].PA_CL_VPORT_XSCALE.f32All = sx; + r700->viewport[id].PA_CL_VPORT_XOFFSET.f32All = tx; - r700->PA_CL_VPORT_YSCALE.f32All = sy; - r700->PA_CL_VPORT_YOFFSET.f32All = ty; + r700->viewport[id].PA_CL_VPORT_YSCALE.f32All = sy; + r700->viewport[id].PA_CL_VPORT_YOFFSET.f32All = ty; - r700->PA_CL_VPORT_ZSCALE.f32All = sz; - r700->PA_CL_VPORT_ZOFFSET.f32All = tz; + r700->viewport[id].PA_CL_VPORT_ZSCALE.f32All = sz; + r700->viewport[id].PA_CL_VPORT_ZOFFSET.f32All = tz; + + r700->viewport[id].enabled = GL_TRUE; } @@ -569,14 +571,14 @@ static void r700Viewport(GLcontext * ctx, GLsizei width, GLsizei height) //-------------------- { - r700UpdateWindow(ctx); + r700UpdateWindow(ctx, 0); radeon_viewport(ctx, x, y, width, height); } static void r700DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) //------------- { - r700UpdateWindow(ctx); + r700UpdateWindow(ctx, 0); } static void r700PointSize(GLcontext * ctx, GLfloat size) //------------------- @@ -608,6 +610,7 @@ void r700SetScissor(context_t *context) //--------------- { R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); unsigned x1, y1, x2, y2; + int id = 0; struct radeon_renderbuffer *rrb; rrb = radeon_get_colorbuffer(&context->radeon); @@ -670,28 +673,22 @@ void r700SetScissor(context_t *context) //--------------- SETfield(r700->PA_SC_GENERIC_SCISSOR_BR.u32All, y2, PA_SC_GENERIC_SCISSOR_BR__BR_Y_shift, PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask); - SETbit(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, x1, + SETbit(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, WINDOW_OFFSET_DISABLE_bit); + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, x1, PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_TL.u32All, y1, + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_TL.u32All, y1, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, x2, + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, x2, PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_0_BR.u32All, y2, + SETfield(r700->viewport[id].PA_SC_VPORT_SCISSOR_0_BR.u32All, y2, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); - SETbit(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, WINDOW_OFFSET_DISABLE_bit); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, x1, - PA_SC_VPORT_SCISSOR_0_TL__TL_X_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_TL.u32All, y1, - PA_SC_VPORT_SCISSOR_0_TL__TL_Y_shift, PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, x2, - PA_SC_VPORT_SCISSOR_0_BR__BR_X_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask); - SETfield(r700->PA_SC_VPORT_SCISSOR_1_BR.u32All, y2, - PA_SC_VPORT_SCISSOR_0_BR__BR_Y_shift, PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask); + r700->viewport[id].PA_SC_VPORT_ZMIN_0.u32All = 0; + r700->viewport[id].PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; + r700->viewport[id].enabled = GL_TRUE; } -void r700SetRenderTarget(context_t *context) +void r700SetRenderTarget(context_t *context, int id) { R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); @@ -699,7 +696,7 @@ void r700SetRenderTarget(context_t *context) unsigned int nPitchInPixel; /* screen/window/view */ - SETfield(r700->CB_TARGET_MASK.u32All, 0xF, TARGET0_ENABLE_shift, TARGET0_ENABLE_mask); + SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask); rrb = radeon_get_colorbuffer(&context->radeon); if (!rrb || !rrb->bo) { @@ -708,34 +705,38 @@ void r700SetRenderTarget(context_t *context) } /* color buffer */ - r700->CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; + r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset; nPitchInPixel = rrb->pitch/rrb->cpp; - SETfield(r700->CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1, PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask); - SETfield(r700->CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, + SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1, SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); - r700->CB_COLOR0_BASE.u32All = 0; - SETfield(r700->CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, + r700->render_target[id].CB_COLOR0_BASE.u32All = 0; + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask); + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL, CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask); if(4 == rrb->cpp) { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8, CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask); } else { - SETfield(r700->CB_COLOR0_INFO.u32All, COLOR_5_6_5, + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5, CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask); - SETfield(r700->CB_COLOR0_INFO.u32All, SWAP_ALT_REV, + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV, COMP_SWAP_shift, COMP_SWAP_mask); } - SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); - SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); - SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); + SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); + SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); + SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); + + CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */ + CLEARfield(r700->render_target[id].CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */ + r700->render_target[id].enabled = GL_TRUE; } void r700SetDepthTarget(context_t *context) @@ -746,7 +747,7 @@ void r700SetDepthTarget(context_t *context) unsigned int nPitchInPixel; /* depth buf */ - r700->DB_DEPTH_SIZE.u32All = 0; + r700->DB_DEPTH_SIZE.u32All = 0; r700->DB_DEPTH_BASE.u32All = 0; r700->DB_DEPTH_INFO.u32All = 0; @@ -819,21 +820,19 @@ void r700InitState(GLcontext * ctx) //------------------- r700->VGT_DMA_NUM_INSTANCES.u32All = 1; /* not alpha blend */ - CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask); + CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask); CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit); /* defualt shader connections. */ r700->SPI_VS_OUT_ID_0.u32All = 0x03020100; r700->SPI_VS_OUT_ID_1.u32All = 0x07060504; - r700->SPI_PS_INPUT_CNTL_0.u32All = 0x00000800; - r700->SPI_PS_INPUT_CNTL_1.u32All = 0x00000801; - r700->SPI_PS_INPUT_CNTL_2.u32All = 0x00000802; + r700->SPI_PS_INPUT_CNTL[0].u32All = 0x00000800; + r700->SPI_PS_INPUT_CNTL[1].u32All = 0x00000801; + r700->SPI_PS_INPUT_CNTL[2].u32All = 0x00000802; SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask); CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit); - CLEARfield(r700->CB_BLEND0_CONTROL.u32All, COLOR_SRCBLEND_mask); /* no dst blend */ - CLEARfield(r700->CB_BLEND0_CONTROL.u32All, ALPHA_SRCBLEND_mask); /* no dst blend */ r700->DB_SHADER_CONTROL.u32All = 0; SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit); @@ -897,7 +896,7 @@ void r700InitState(GLcontext * ctx) //------------------- r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All = 0x3F800000; r700->PA_CL_GB_HORZ_DISC_ADJ.u32All = 0x3F800000; - /* Disble color compares */ + /* Disable color compares */ SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS, CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask); SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS, @@ -924,32 +923,6 @@ void r700InitState(GLcontext * ctx) //------------------- r700->SX_MISC.u32All = 0; - /* depth buf */ - r700->DB_DEPTH_SIZE.u32All = 0; - r700->DB_DEPTH_BASE.u32All = 0; - r700->DB_DEPTH_INFO.u32All = 0; - r700->DB_DEPTH_CONTROL.u32All = 0; - r700->DB_DEPTH_CLEAR.u32All = 0x3F800000; - r700->DB_DEPTH_VIEW.u32All = 0; - r700->DB_RENDER_CONTROL.u32All = 0; - r700->DB_RENDER_OVERRIDE.u32All = 0; - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); - SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); - - /* color buffer */ - r700->CB_COLOR0_SIZE.u32All = 0; - r700->CB_COLOR0_BASE.u32All = 0; - r700->CB_COLOR0_INFO.u32All = 0; - SETbit(r700->CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit); - SETbit(r700->CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit); - SETfield(r700->CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask); - r700->CB_COLOR0_VIEW.u32All = 0; - r700->CB_COLOR0_TILE.u32All = 0; - r700->CB_COLOR0_FRAG.u32All = 0; - r700->CB_COLOR0_MASK.u32All = 0; - - r700->PA_SC_VPORT_ZMAX_0.u32All = 0x3F800000; } void r700InitStateFuncs(struct dd_function_table *functions) //----------------- diff --git a/src/mesa/drivers/dri/r600/r700_state.h b/src/mesa/drivers/dri/r600/r700_state.h index a75c7f0188..87f0903b67 100644 --- a/src/mesa/drivers/dri/r600/r700_state.h +++ b/src/mesa/drivers/dri/r600/r700_state.h @@ -42,7 +42,7 @@ extern void r700UpdateDrawBuffer (GLcontext * ctx); extern void r700InitState (GLcontext * ctx); extern void r700InitStateFuncs (struct dd_function_table *functions); -extern void r700SetRenderTarget(context_t *context); +extern void r700SetRenderTarget(context_t *context, int id); extern void r700SetDefaultStates(context_t * context); #endif /* _R600_SCREEN_H */ diff --git a/src/mesa/drivers/dri/r600/r700_vertprog.c b/src/mesa/drivers/dri/r600/r700_vertprog.c index ecb72549fe..b83e6f16bc 100644 --- a/src/mesa/drivers/dri/r600/r700_vertprog.c +++ b/src/mesa/drivers/dri/r600/r700_vertprog.c @@ -372,14 +372,14 @@ GLboolean r700SetupVertexProgram(GLcontext * ctx) (context->chipobj.MemUse)(context, vp->shadercode.buf->id); */ - r700->SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ + r700->vs.SQ_PGM_START_VS.u32All = 0; /* set from buffer object. */ - SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, + SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1, NUM_GPRS_shift, NUM_GPRS_mask); if(vp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */ { - SETfield(r700->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize, + SETfield(r700->vs.SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize, STACK_SIZE_shift, STACK_SIZE_mask); } -- cgit v1.2.3