From 7d6c8f980d1e23ad6f557d650e89c715861a3b0c Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Tue, 24 Nov 2009 15:02:23 +0000
Subject: tgsi: rename fields of tgsi_full_instruction to avoid excessive
 verbosity

InstructionPredicate -> Predicate
InstructionLabel -> Label
InstructionTexture -> Texture
FullSrcRegisters -> Src
FullDstRegisters -> Dst
---
 src/gallium/auxiliary/tgsi/tgsi_exec.c | 46 +++++++++++++++++-----------------
 1 file changed, 23 insertions(+), 23 deletions(-)

(limited to 'src/gallium/auxiliary/tgsi/tgsi_exec.c')

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index c113f4a3bc..a9bfb0d6df 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -107,10 +107,10 @@
 #define TEMP_P0            TGSI_EXEC_TEMP_P0
 
 #define IS_CHANNEL_ENABLED(INST, CHAN)\
-   ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
+   ((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
 
 #define IS_CHANNEL_ENABLED2(INST, CHAN)\
-   ((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
+   ((INST).Dst[1].DstRegister.WriteMask & (1 << (CHAN)))
 
 #define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
    for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
@@ -188,7 +188,7 @@ tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
 {
    uint i, chan;
 
-   uint writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
+   uint writemask = inst->Dst[0].DstRegister.WriteMask;
    if (writemask == TGSI_WRITEMASK_X ||
        writemask == TGSI_WRITEMASK_Y ||
        writemask == TGSI_WRITEMASK_Z ||
@@ -200,15 +200,15 @@ tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
 
    /* loop over src regs */
    for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
-      if ((inst->FullSrcRegisters[i].SrcRegister.File ==
-           inst->FullDstRegisters[0].DstRegister.File) &&
-          (inst->FullSrcRegisters[i].SrcRegister.Index ==
-           inst->FullDstRegisters[0].DstRegister.Index)) {
+      if ((inst->Src[i].SrcRegister.File ==
+           inst->Dst[0].DstRegister.File) &&
+          (inst->Src[i].SrcRegister.Index ==
+           inst->Dst[0].DstRegister.Index)) {
          /* loop over dest channels */
          uint channelsWritten = 0x0;
          FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
             /* check if we're reading a channel that's been written */
-            uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->FullSrcRegisters[i], chan);
+            uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
             if (channelsWritten & (1 << swizzle)) {
                return TRUE;
             }
@@ -1500,27 +1500,27 @@ store_dest(
 
       switch (chan_index) {
       case CHAN_X:
-         swizzle = inst->InstructionPredicate.SwizzleX;
+         swizzle = inst->Predicate.SwizzleX;
          break;
       case CHAN_Y:
-         swizzle = inst->InstructionPredicate.SwizzleY;
+         swizzle = inst->Predicate.SwizzleY;
          break;
       case CHAN_Z:
-         swizzle = inst->InstructionPredicate.SwizzleZ;
+         swizzle = inst->Predicate.SwizzleZ;
          break;
       case CHAN_W:
-         swizzle = inst->InstructionPredicate.SwizzleW;
+         swizzle = inst->Predicate.SwizzleW;
          break;
       default:
          assert(0);
          return;
       }
 
-      assert(inst->InstructionPredicate.Index == 0);
+      assert(inst->Predicate.Index == 0);
 
-      pred = &mach->Predicates[inst->InstructionPredicate.Index].xyzw[swizzle];
+      pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
 
-      if (inst->InstructionPredicate.Negate) {
+      if (inst->Predicate.Negate) {
          for (i = 0; i < QUAD_SIZE; i++) {
             if (pred->u[i]) {
                execmask &= ~(1 << i);
@@ -1572,10 +1572,10 @@ store_dest(
 }
 
 #define FETCH(VAL,INDEX,CHAN)\
-    fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
+    fetch_source (mach, VAL, &inst->Src[INDEX], CHAN)
 
 #define STORE(VAL,INDEX,CHAN)\
-    store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
+    store_dest (mach, VAL, &inst->Dst[INDEX], inst, CHAN )
 
 
 /**
@@ -1601,7 +1601,7 @@ exec_kil(struct tgsi_exec_machine *mach,
 
       /* unswizzle channel */
       swizzle = tgsi_util_get_full_src_register_swizzle (
-                        &inst->FullSrcRegisters[0],
+                        &inst->Src[0],
                         chan_index);
 
       /* check if the component has not been already tested */
@@ -1668,14 +1668,14 @@ exec_tex(struct tgsi_exec_machine *mach,
          boolean biasLod,
          boolean projected)
 {
-   const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
+   const uint unit = inst->Src[1].SrcRegister.Index;
    union tgsi_exec_channel r[4];
    uint chan_index;
    float lodBias;
 
    /*   debug_printf("Sampler %u unit %u\n", sampler, unit); */
 
-   switch (inst->InstructionTexture.Texture) {
+   switch (inst->Texture.Texture) {
    case TGSI_TEXTURE_1D:
    case TGSI_TEXTURE_SHADOW1D:
 
@@ -1765,7 +1765,7 @@ static void
 exec_txd(struct tgsi_exec_machine *mach,
          const struct tgsi_full_instruction *inst)
 {
-   const uint unit = inst->FullSrcRegisters[3].SrcRegister.Index;
+   const uint unit = inst->Src[3].SrcRegister.Index;
    union tgsi_exec_channel r[4];
    uint chan_index;
 
@@ -1773,7 +1773,7 @@ exec_txd(struct tgsi_exec_machine *mach,
     * XXX: This is fake TXD -- the derivatives are not taken into account, yet.
     */
 
-   switch (inst->InstructionTexture.Texture) {
+   switch (inst->Texture.Texture) {
    case TGSI_TEXTURE_1D:
    case TGSI_TEXTURE_SHADOW1D:
 
@@ -2740,7 +2740,7 @@ exec_instruction(
          mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
 
          /* Finally, jump to the subroutine */
-         *pc = inst->InstructionLabel.Label;
+         *pc = inst->Label.Label;
       }
       break;
 
-- 
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