From aa2b2e5d7d53ddd08425536edddec509a8834bfc Mon Sep 17 00:00:00 2001 From: Michal Krol Date: Mon, 2 Nov 2009 09:41:40 +0000 Subject: tgsi: Update for gallium interface changes. --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 199 ++++----------------------------- 1 file changed, 20 insertions(+), 179 deletions(-) (limited to 'src/gallium/auxiliary/tgsi/tgsi_exec.c') diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c index 14f0fc4e38..1989045985 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.c +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c @@ -107,6 +107,7 @@ #define TEMP_HALF_I TGSI_EXEC_TEMP_HALF_I #define TEMP_HALF_C TGSI_EXEC_TEMP_HALF_C #define TEMP_R0 TGSI_EXEC_TEMP_R0 +#define TEMP_P0 TGSI_EXEC_TEMP_P0 #define IS_CHANNEL_ENABLED(INST, CHAN)\ ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN))) @@ -1187,6 +1188,17 @@ fetch_src_file_channel( chan->u[3] = mach->Addrs[index->i[3]].xyzw[swizzle].u[3]; break; + case TGSI_FILE_PREDICATE: + assert(index->i[0] < TGSI_EXEC_NUM_PREDS); + assert(index->i[1] < TGSI_EXEC_NUM_PREDS); + assert(index->i[2] < TGSI_EXEC_NUM_PREDS); + assert(index->i[3] < TGSI_EXEC_NUM_PREDS); + chan->u[0] = mach->Addrs[0].xyzw[swizzle].u[0]; + chan->u[1] = mach->Addrs[0].xyzw[swizzle].u[1]; + chan->u[2] = mach->Addrs[0].xyzw[swizzle].u[2]; + chan->u[3] = mach->Addrs[0].xyzw[swizzle].u[3]; + break; + case TGSI_FILE_OUTPUT: /* vertex/fragment output vars can be read too */ chan->u[0] = mach->Outputs[index->i[0]].xyzw[swizzle].u[0]; @@ -1466,119 +1478,17 @@ store_dest( dst = &mach->Addrs[index].xyzw[chan_index]; break; + case TGSI_FILE_PREDICATE: + index = reg->DstRegister.Index; + assert(index < TGSI_EXEC_NUM_PREDS); + dst = &mach->Addrs[index].xyzw[chan_index]; + break; + default: assert( 0 ); return; } - if (inst->InstructionExtNv.CondFlowEnable) { - union tgsi_exec_channel *cc = &mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C]; - uint swizzle; - uint shift; - uint mask; - uint test; - - /* Only CC0 supported. - */ - assert( inst->InstructionExtNv.CondFlowIndex < 1 ); - - switch (chan_index) { - case CHAN_X: - swizzle = inst->InstructionExtNv.CondSwizzleX; - break; - case CHAN_Y: - swizzle = inst->InstructionExtNv.CondSwizzleY; - break; - case CHAN_Z: - swizzle = inst->InstructionExtNv.CondSwizzleZ; - break; - case CHAN_W: - swizzle = inst->InstructionExtNv.CondSwizzleW; - break; - default: - assert( 0 ); - return; - } - - switch (swizzle) { - case TGSI_SWIZZLE_X: - shift = TGSI_EXEC_CC_X_SHIFT; - mask = TGSI_EXEC_CC_X_MASK; - break; - case TGSI_SWIZZLE_Y: - shift = TGSI_EXEC_CC_Y_SHIFT; - mask = TGSI_EXEC_CC_Y_MASK; - break; - case TGSI_SWIZZLE_Z: - shift = TGSI_EXEC_CC_Z_SHIFT; - mask = TGSI_EXEC_CC_Z_MASK; - break; - case TGSI_SWIZZLE_W: - shift = TGSI_EXEC_CC_W_SHIFT; - mask = TGSI_EXEC_CC_W_MASK; - break; - default: - assert( 0 ); - return; - } - - switch (inst->InstructionExtNv.CondMask) { - case TGSI_CC_GT: - test = ~(TGSI_EXEC_CC_GT << shift) & mask; - for (i = 0; i < QUAD_SIZE; i++) - if (cc->u[i] & test) - execmask &= ~(1 << i); - break; - - case TGSI_CC_EQ: - test = ~(TGSI_EXEC_CC_EQ << shift) & mask; - for (i = 0; i < QUAD_SIZE; i++) - if (cc->u[i] & test) - execmask &= ~(1 << i); - break; - - case TGSI_CC_LT: - test = ~(TGSI_EXEC_CC_LT << shift) & mask; - for (i = 0; i < QUAD_SIZE; i++) - if (cc->u[i] & test) - execmask &= ~(1 << i); - break; - - case TGSI_CC_GE: - test = ~((TGSI_EXEC_CC_GT | TGSI_EXEC_CC_EQ) << shift) & mask; - for (i = 0; i < QUAD_SIZE; i++) - if (cc->u[i] & test) - execmask &= ~(1 << i); - break; - - case TGSI_CC_LE: - test = ~((TGSI_EXEC_CC_LT | TGSI_EXEC_CC_EQ) << shift) & mask; - for (i = 0; i < QUAD_SIZE; i++) - if (cc->u[i] & test) - execmask &= ~(1 << i); - break; - - case TGSI_CC_NE: - test = ~((TGSI_EXEC_CC_GT | TGSI_EXEC_CC_LT | TGSI_EXEC_CC_UN) << shift) & mask; - for (i = 0; i < QUAD_SIZE; i++) - if (cc->u[i] & test) - execmask &= ~(1 << i); - break; - - case TGSI_CC_TR: - break; - - case TGSI_CC_FL: - for (i = 0; i < QUAD_SIZE; i++) - execmask &= ~(1 << i); - break; - - default: - assert( 0 ); - return; - } - } - switch (inst->Instruction.Saturate) { case TGSI_SAT_NONE: for (i = 0; i < QUAD_SIZE; i++) @@ -1613,51 +1523,6 @@ store_dest( default: assert( 0 ); } - - if (inst->InstructionExtNv.CondDstUpdate) { - union tgsi_exec_channel *cc = &mach->Temps[TEMP_CC_I].xyzw[TEMP_CC_C]; - uint shift; - uint mask; - - /* Only CC0 supported. - */ - assert( inst->InstructionExtNv.CondDstIndex < 1 ); - - switch (chan_index) { - case CHAN_X: - shift = TGSI_EXEC_CC_X_SHIFT; - mask = ~TGSI_EXEC_CC_X_MASK; - break; - case CHAN_Y: - shift = TGSI_EXEC_CC_Y_SHIFT; - mask = ~TGSI_EXEC_CC_Y_MASK; - break; - case CHAN_Z: - shift = TGSI_EXEC_CC_Z_SHIFT; - mask = ~TGSI_EXEC_CC_Z_MASK; - break; - case CHAN_W: - shift = TGSI_EXEC_CC_W_SHIFT; - mask = ~TGSI_EXEC_CC_W_MASK; - break; - default: - assert( 0 ); - return; - } - - for (i = 0; i < QUAD_SIZE; i++) - if (execmask & (1 << i)) { - cc->u[i] &= mask; - if (dst->f[i] < 0.0f) - cc->u[i] |= TGSI_EXEC_CC_LT << shift; - else if (dst->f[i] > 0.0f) - cc->u[i] |= TGSI_EXEC_CC_GT << shift; - else if (dst->f[i] == 0.0f) - cc->u[i] |= TGSI_EXEC_CC_EQ << shift; - else - cc->u[i] |= TGSI_EXEC_CC_UN << shift; - } - } } #define FETCH(VAL,INDEX,CHAN)\ @@ -1717,32 +1582,8 @@ exec_kilp(struct tgsi_exec_machine *mach, { uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */ - if (inst->InstructionExtNv.CondFlowEnable) { - uint swizzle[4]; - uint chan_index; - - kilmask = 0x0; - - swizzle[0] = inst->InstructionExtNv.CondSwizzleX; - swizzle[1] = inst->InstructionExtNv.CondSwizzleY; - swizzle[2] = inst->InstructionExtNv.CondSwizzleZ; - swizzle[3] = inst->InstructionExtNv.CondSwizzleW; - - for (chan_index = 0; chan_index < 4; chan_index++) - { - uint i; - - for (i = 0; i < 4; i++) { - /* TODO: evaluate the condition code */ - if (0) - kilmask |= 1 << i; - } - } - } - else { - /* "unconditional" kil */ - kilmask = mach->ExecMask; - } + /* "unconditional" kil */ + kilmask = mach->ExecMask; mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask; } -- cgit v1.2.3