From f77a2690b463aa36297aec2a5035a9de68268dd9 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 19 Nov 2010 23:38:18 +0100 Subject: i915g: rip out ->sw_tiled It looks like this was meant to facilitate unfenced access to textures/ color/renderbuffers. It's totally incomplete and fundamentally broken on a few levels: - broken: The kernel needs to about every tiled bo to fix up bit17 swizzling on swap-in. - unflexible: fenced/unfenced relocs from execbuffer2 do the same, much simpler. - unneeded: with relaxed fencing tiled gem bos are as memory-efficient as this trick. Hence kill it. Reviewed-by: Jakob Bornecrantz Signed-off-by: Daniel Vetter Signed-off-by: Jakob Bornecrantz --- src/gallium/drivers/i915/i915_resource_texture.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/gallium/drivers/i915/i915_resource_texture.c') diff --git a/src/gallium/drivers/i915/i915_resource_texture.c b/src/gallium/drivers/i915/i915_resource_texture.c index c5c6179b16..eb040fea66 100644 --- a/src/gallium/drivers/i915/i915_resource_texture.c +++ b/src/gallium/drivers/i915/i915_resource_texture.c @@ -791,7 +791,6 @@ i915_texture_create(struct pipe_screen *screen, /* setup any hw fences */ if (tex->hw_tiled) { - assert(tex->sw_tiled == I915_TILE_NONE); iws->buffer_set_fence_reg(iws, tex->buffer, tex->stride, tex->hw_tiled); } -- cgit v1.2.3