From 83bb81856066101dff85fdebea32df55ed8de4c5 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sat, 8 Nov 2008 17:20:19 +0200 Subject: Nouveau: Rename nv20/ files as nv20. Signed-off-by: Pekka Paalanen --- src/gallium/drivers/nv20/nv20_state.c | 588 ++++++++++++++++++++++++++++++++++ 1 file changed, 588 insertions(+) create mode 100644 src/gallium/drivers/nv20/nv20_state.c (limited to 'src/gallium/drivers/nv20/nv20_state.c') diff --git a/src/gallium/drivers/nv20/nv20_state.c b/src/gallium/drivers/nv20/nv20_state.c new file mode 100644 index 0000000000..d2375aa2f6 --- /dev/null +++ b/src/gallium/drivers/nv20/nv20_state.c @@ -0,0 +1,588 @@ +#include "draw/draw_context.h" +#include "pipe/p_state.h" +#include "pipe/p_defines.h" +#include "pipe/p_shader_tokens.h" + +#include "tgsi/tgsi_parse.h" + +#include "nv10_context.h" +#include "nv10_state.h" + +static void * +nv10_blend_state_create(struct pipe_context *pipe, + const struct pipe_blend_state *cso) +{ + struct nv10_blend_state *cb; + + cb = MALLOC(sizeof(struct nv10_blend_state)); + + cb->b_enable = cso->blend_enable ? 1 : 0; + cb->b_srcfunc = ((nvgl_blend_func(cso->alpha_src_factor)<<16) | + (nvgl_blend_func(cso->rgb_src_factor))); + cb->b_dstfunc = ((nvgl_blend_func(cso->alpha_dst_factor)<<16) | + (nvgl_blend_func(cso->rgb_dst_factor))); + + cb->c_mask = (((cso->colormask & PIPE_MASK_A) ? (0x01<<24) : 0) | + ((cso->colormask & PIPE_MASK_R) ? (0x01<<16) : 0) | + ((cso->colormask & PIPE_MASK_G) ? (0x01<< 8) : 0) | + ((cso->colormask & PIPE_MASK_B) ? (0x01<< 0) : 0)); + + cb->d_enable = cso->dither ? 1 : 0; + + return (void *)cb; +} + +static void +nv10_blend_state_bind(struct pipe_context *pipe, void *blend) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + nv10->blend = (struct nv10_blend_state*)blend; + + nv10->dirty |= NV10_NEW_BLEND; +} + +static void +nv10_blend_state_delete(struct pipe_context *pipe, void *hwcso) +{ + FREE(hwcso); +} + + +static INLINE unsigned +wrap_mode(unsigned wrap) { + unsigned ret; + + switch (wrap) { + case PIPE_TEX_WRAP_REPEAT: + ret = NV10TCL_TX_FORMAT_WRAP_S_REPEAT; + break; + case PIPE_TEX_WRAP_MIRROR_REPEAT: + ret = NV10TCL_TX_FORMAT_WRAP_S_MIRRORED_REPEAT; + break; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: + ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE; + break; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: + ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER; + break; + case PIPE_TEX_WRAP_CLAMP: + ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP; + break; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: + case PIPE_TEX_WRAP_MIRROR_CLAMP: + default: + NOUVEAU_ERR("unknown wrap mode: %d\n", wrap); + ret = NV10TCL_TX_FORMAT_WRAP_S_REPEAT; + break; + } + + return ret >> NV10TCL_TX_FORMAT_WRAP_S_SHIFT; +} + +static void * +nv10_sampler_state_create(struct pipe_context *pipe, + const struct pipe_sampler_state *cso) +{ + struct nv10_sampler_state *ps; + uint32_t filter = 0; + + ps = MALLOC(sizeof(struct nv10_sampler_state)); + + ps->wrap = ((wrap_mode(cso->wrap_s) << NV10TCL_TX_FORMAT_WRAP_S_SHIFT) | + (wrap_mode(cso->wrap_t) << NV10TCL_TX_FORMAT_WRAP_T_SHIFT)); + + ps->en = 0; + if (cso->max_anisotropy > 1.0) { + /* no idea, binary driver sets it, works without it.. meh.. */ + ps->wrap |= (1 << 5); + +/* if (cso->max_anisotropy >= 16.0) { + ps->en |= NV10TCL_TX_ENABLE_ANISO_16X; + } else + if (cso->max_anisotropy >= 12.0) { + ps->en |= NV10TCL_TX_ENABLE_ANISO_12X; + } else + if (cso->max_anisotropy >= 10.0) { + ps->en |= NV10TCL_TX_ENABLE_ANISO_10X; + } else + if (cso->max_anisotropy >= 8.0) { + ps->en |= NV10TCL_TX_ENABLE_ANISO_8X; + } else + if (cso->max_anisotropy >= 6.0) { + ps->en |= NV10TCL_TX_ENABLE_ANISO_6X; + } else + if (cso->max_anisotropy >= 4.0) { + ps->en |= NV10TCL_TX_ENABLE_ANISO_4X; + } else { + ps->en |= NV10TCL_TX_ENABLE_ANISO_2X; + }*/ + } + + switch (cso->mag_img_filter) { + case PIPE_TEX_FILTER_LINEAR: + filter |= NV10TCL_TX_FILTER_MAGNIFY_LINEAR; + break; + case PIPE_TEX_FILTER_NEAREST: + default: + filter |= NV10TCL_TX_FILTER_MAGNIFY_NEAREST; + break; + } + + switch (cso->min_img_filter) { + case PIPE_TEX_FILTER_LINEAR: + switch (cso->min_mip_filter) { + case PIPE_TEX_MIPFILTER_NEAREST: + filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST; + break; + case PIPE_TEX_MIPFILTER_LINEAR: + filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR; + break; + case PIPE_TEX_MIPFILTER_NONE: + default: + filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR; + break; + } + break; + case PIPE_TEX_FILTER_NEAREST: + default: + switch (cso->min_mip_filter) { + case PIPE_TEX_MIPFILTER_NEAREST: + filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST; + break; + case PIPE_TEX_MIPFILTER_LINEAR: + filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR; + break; + case PIPE_TEX_MIPFILTER_NONE: + default: + filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST; + break; + } + break; + } + + ps->filt = filter; + +/* if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) { + switch (cso->compare_func) { + case PIPE_FUNC_NEVER: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_NEVER; + break; + case PIPE_FUNC_GREATER: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_GREATER; + break; + case PIPE_FUNC_EQUAL: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_EQUAL; + break; + case PIPE_FUNC_GEQUAL: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_GEQUAL; + break; + case PIPE_FUNC_LESS: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_LESS; + break; + case PIPE_FUNC_NOTEQUAL: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_NOTEQUAL; + break; + case PIPE_FUNC_LEQUAL: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_LEQUAL; + break; + case PIPE_FUNC_ALWAYS: + ps->wrap |= NV10TCL_TX_WRAP_RCOMP_ALWAYS; + break; + default: + break; + } + }*/ + + ps->bcol = ((float_to_ubyte(cso->border_color[3]) << 24) | + (float_to_ubyte(cso->border_color[0]) << 16) | + (float_to_ubyte(cso->border_color[1]) << 8) | + (float_to_ubyte(cso->border_color[2]) << 0)); + + return (void *)ps; +} + +static void +nv10_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler) +{ + struct nv10_context *nv10 = nv10_context(pipe); + unsigned unit; + + for (unit = 0; unit < nr; unit++) { + nv10->tex_sampler[unit] = sampler[unit]; + nv10->dirty_samplers |= (1 << unit); + } +} + +static void +nv10_sampler_state_delete(struct pipe_context *pipe, void *hwcso) +{ + FREE(hwcso); +} + +static void +nv10_set_sampler_texture(struct pipe_context *pipe, unsigned nr, + struct pipe_texture **miptree) +{ + struct nv10_context *nv10 = nv10_context(pipe); + unsigned unit; + + for (unit = 0; unit < nr; unit++) { + nv10->tex_miptree[unit] = (struct nv10_miptree *)miptree[unit]; + nv10->dirty_samplers |= (1 << unit); + } +} + +static void * +nv10_rasterizer_state_create(struct pipe_context *pipe, + const struct pipe_rasterizer_state *cso) +{ + struct nv10_rasterizer_state *rs; + int i; + + /*XXX: ignored: + * light_twoside + * offset_cw/ccw -nohw + * scissor + * point_smooth -nohw + * multisample + * offset_units / offset_scale + */ + rs = MALLOC(sizeof(struct nv10_rasterizer_state)); + + rs->templ = cso; + + rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01; + + rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff; + rs->line_smooth_en = cso->line_smooth ? 1 : 0; + + rs->point_size = *(uint32_t*)&cso->point_size; + + rs->poly_smooth_en = cso->poly_smooth ? 1 : 0; + + if (cso->front_winding == PIPE_WINDING_CCW) { + rs->front_face = NV10TCL_FRONT_FACE_CCW; + rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw); + rs->poly_mode_back = nvgl_polygon_mode(cso->fill_cw); + } else { + rs->front_face = NV10TCL_FRONT_FACE_CW; + rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw); + rs->poly_mode_back = nvgl_polygon_mode(cso->fill_ccw); + } + + switch (cso->cull_mode) { + case PIPE_WINDING_CCW: + rs->cull_face_en = 1; + if (cso->front_winding == PIPE_WINDING_CCW) + rs->cull_face = NV10TCL_CULL_FACE_FRONT; + else + rs->cull_face = NV10TCL_CULL_FACE_BACK; + break; + case PIPE_WINDING_CW: + rs->cull_face_en = 1; + if (cso->front_winding == PIPE_WINDING_CW) + rs->cull_face = NV10TCL_CULL_FACE_FRONT; + else + rs->cull_face = NV10TCL_CULL_FACE_BACK; + break; + case PIPE_WINDING_BOTH: + rs->cull_face_en = 1; + rs->cull_face = NV10TCL_CULL_FACE_FRONT_AND_BACK; + break; + case PIPE_WINDING_NONE: + default: + rs->cull_face_en = 0; + rs->cull_face = 0; + break; + } + + if (cso->point_sprite) { + rs->point_sprite = (1 << 0); + for (i = 0; i < 8; i++) { + if (cso->sprite_coord_mode[i] != PIPE_SPRITE_COORD_NONE) + rs->point_sprite |= (1 << (8 + i)); + } + } else { + rs->point_sprite = 0; + } + + return (void *)rs; +} + +static void +nv10_rasterizer_state_bind(struct pipe_context *pipe, void *rast) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + nv10->rast = (struct nv10_rasterizer_state*)rast; + + draw_set_rasterizer_state(nv10->draw, (nv10->rast ? nv10->rast->templ : NULL)); + + nv10->dirty |= NV10_NEW_RAST; +} + +static void +nv10_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso) +{ + FREE(hwcso); +} + +static void * +nv10_depth_stencil_alpha_state_create(struct pipe_context *pipe, + const struct pipe_depth_stencil_alpha_state *cso) +{ + struct nv10_depth_stencil_alpha_state *hw; + + hw = MALLOC(sizeof(struct nv10_depth_stencil_alpha_state)); + + hw->depth.func = nvgl_comparison_op(cso->depth.func); + hw->depth.write_enable = cso->depth.writemask ? 1 : 0; + hw->depth.test_enable = cso->depth.enabled ? 1 : 0; + + hw->stencil.enable = cso->stencil[0].enabled ? 1 : 0; + hw->stencil.wmask = cso->stencil[0].write_mask; + hw->stencil.func = nvgl_comparison_op(cso->stencil[0].func); + hw->stencil.ref = cso->stencil[0].ref_value; + hw->stencil.vmask = cso->stencil[0].value_mask; + hw->stencil.fail = nvgl_stencil_op(cso->stencil[0].fail_op); + hw->stencil.zfail = nvgl_stencil_op(cso->stencil[0].zfail_op); + hw->stencil.zpass = nvgl_stencil_op(cso->stencil[0].zpass_op); + + hw->alpha.enabled = cso->alpha.enabled ? 1 : 0; + hw->alpha.func = nvgl_comparison_op(cso->alpha.func); + hw->alpha.ref = float_to_ubyte(cso->alpha.ref); + + return (void *)hw; +} + +static void +nv10_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *dsa) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + nv10->dsa = (struct nv10_depth_stencil_alpha_state*)dsa; + + nv10->dirty |= NV10_NEW_DSA; +} + +static void +nv10_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso) +{ + FREE(hwcso); +} + +static void * +nv10_vp_state_create(struct pipe_context *pipe, + const struct pipe_shader_state *templ) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + return draw_create_vertex_shader(nv10->draw, templ); +} + +static void +nv10_vp_state_bind(struct pipe_context *pipe, void *shader) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + draw_bind_vertex_shader(nv10->draw, (struct draw_vertex_shader *) shader); + + nv10->dirty |= NV10_NEW_VERTPROG; +} + +static void +nv10_vp_state_delete(struct pipe_context *pipe, void *shader) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + draw_delete_vertex_shader(nv10->draw, (struct draw_vertex_shader *) shader); +} + +static void * +nv10_fp_state_create(struct pipe_context *pipe, + const struct pipe_shader_state *cso) +{ + struct nv10_fragment_program *fp; + + fp = CALLOC(1, sizeof(struct nv10_fragment_program)); + fp->pipe.tokens = tgsi_dup_tokens(cso->tokens); + + tgsi_scan_shader(cso->tokens, &fp->info); + + return (void *)fp; +} + +static void +nv10_fp_state_bind(struct pipe_context *pipe, void *hwcso) +{ + struct nv10_context *nv10 = nv10_context(pipe); + struct nv10_fragment_program *fp = hwcso; + + nv10->fragprog.current = fp; + nv10->dirty |= NV10_NEW_FRAGPROG; +} + +static void +nv10_fp_state_delete(struct pipe_context *pipe, void *hwcso) +{ + struct nv10_context *nv10 = nv10_context(pipe); + struct nv10_fragment_program *fp = hwcso; + + nv10_fragprog_destroy(nv10, fp); + FREE((void*)fp->pipe.tokens); + FREE(fp); +} + +static void +nv10_set_blend_color(struct pipe_context *pipe, + const struct pipe_blend_color *bcol) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + nv10->blend_color = (struct pipe_blend_color*)bcol; + + nv10->dirty |= NV10_NEW_BLENDCOL; +} + +static void +nv10_set_clip_state(struct pipe_context *pipe, + const struct pipe_clip_state *clip) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + draw_set_clip_state(nv10->draw, clip); +} + +static void +nv10_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, + const struct pipe_constant_buffer *buf ) +{ + struct nv10_context *nv10 = nv10_context(pipe); + struct pipe_winsys *ws = pipe->winsys; + + assert(shader < PIPE_SHADER_TYPES); + assert(index == 0); + + if (buf) { + void *mapped; + if (buf->size && (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ))) + { + memcpy(nv10->constbuf[shader], mapped, buf->size); + nv10->constbuf_nr[shader] = + buf->size / (4 * sizeof(float)); + ws->buffer_unmap(ws, buf->buffer); + } + } +} + +static void +nv10_set_framebuffer_state(struct pipe_context *pipe, + const struct pipe_framebuffer_state *fb) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + nv10->framebuffer = (struct pipe_framebuffer_state*)fb; + + nv10->dirty |= NV10_NEW_FRAMEBUFFER; +} + +static void +nv10_set_polygon_stipple(struct pipe_context *pipe, + const struct pipe_poly_stipple *stipple) +{ + NOUVEAU_ERR("line stipple hahaha\n"); +} + +static void +nv10_set_scissor_state(struct pipe_context *pipe, + const struct pipe_scissor_state *s) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + nv10->scissor = (struct pipe_scissor_state*)s; + + nv10->dirty |= NV10_NEW_SCISSOR; +} + +static void +nv10_set_viewport_state(struct pipe_context *pipe, + const struct pipe_viewport_state *vpt) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + nv10->viewport = (struct pipe_viewport_state*)vpt; + + draw_set_viewport_state(nv10->draw, nv10->viewport); + + nv10->dirty |= NV10_NEW_VIEWPORT; +} + +static void +nv10_set_vertex_buffers(struct pipe_context *pipe, unsigned count, + const struct pipe_vertex_buffer *vb) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + memcpy(nv10->vtxbuf, vb, sizeof(*vb) * count); + nv10->dirty |= NV10_NEW_VTXARRAYS; + + draw_set_vertex_buffers(nv10->draw, count, vb); +} + +static void +nv10_set_vertex_elements(struct pipe_context *pipe, unsigned count, + const struct pipe_vertex_element *ve) +{ + struct nv10_context *nv10 = nv10_context(pipe); + + memcpy(nv10->vtxelt, ve, sizeof(*ve) * count); + nv10->dirty |= NV10_NEW_VTXARRAYS; + + draw_set_vertex_elements(nv10->draw, count, ve); +} + +void +nv10_init_state_functions(struct nv10_context *nv10) +{ + nv10->pipe.create_blend_state = nv10_blend_state_create; + nv10->pipe.bind_blend_state = nv10_blend_state_bind; + nv10->pipe.delete_blend_state = nv10_blend_state_delete; + + nv10->pipe.create_sampler_state = nv10_sampler_state_create; + nv10->pipe.bind_sampler_states = nv10_sampler_state_bind; + nv10->pipe.delete_sampler_state = nv10_sampler_state_delete; + nv10->pipe.set_sampler_textures = nv10_set_sampler_texture; + + nv10->pipe.create_rasterizer_state = nv10_rasterizer_state_create; + nv10->pipe.bind_rasterizer_state = nv10_rasterizer_state_bind; + nv10->pipe.delete_rasterizer_state = nv10_rasterizer_state_delete; + + nv10->pipe.create_depth_stencil_alpha_state = + nv10_depth_stencil_alpha_state_create; + nv10->pipe.bind_depth_stencil_alpha_state = + nv10_depth_stencil_alpha_state_bind; + nv10->pipe.delete_depth_stencil_alpha_state = + nv10_depth_stencil_alpha_state_delete; + + nv10->pipe.create_vs_state = nv10_vp_state_create; + nv10->pipe.bind_vs_state = nv10_vp_state_bind; + nv10->pipe.delete_vs_state = nv10_vp_state_delete; + + nv10->pipe.create_fs_state = nv10_fp_state_create; + nv10->pipe.bind_fs_state = nv10_fp_state_bind; + nv10->pipe.delete_fs_state = nv10_fp_state_delete; + + nv10->pipe.set_blend_color = nv10_set_blend_color; + nv10->pipe.set_clip_state = nv10_set_clip_state; + nv10->pipe.set_constant_buffer = nv10_set_constant_buffer; + nv10->pipe.set_framebuffer_state = nv10_set_framebuffer_state; + nv10->pipe.set_polygon_stipple = nv10_set_polygon_stipple; + nv10->pipe.set_scissor_state = nv10_set_scissor_state; + nv10->pipe.set_viewport_state = nv10_set_viewport_state; + + nv10->pipe.set_vertex_buffers = nv10_set_vertex_buffers; + nv10->pipe.set_vertex_elements = nv10_set_vertex_elements; +} + -- cgit v1.2.3 From b5a3c4272be1561646c8a104e4faae870f16ddee Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sat, 8 Nov 2008 18:04:33 +0200 Subject: Nouveau: name replace for nv20. No functional changes, only changed function, struct, macro etc. names. nv10 -> nv20 nv30 -> nv20 celsius -> kelvin Did not touch fifo command macros. Don't try to build nv20_vertprog.c for now. Signed-off-by: Pekka Paalanen --- src/gallium/drivers/nv20/Makefile | 4 +- src/gallium/drivers/nv20/nv20_clear.c | 4 +- src/gallium/drivers/nv20/nv20_context.c | 194 ++++++++++----------- src/gallium/drivers/nv20/nv20_context.h | 104 +++++------ src/gallium/drivers/nv20/nv20_fragprog.c | 8 +- src/gallium/drivers/nv20/nv20_fragtex.c | 46 ++--- src/gallium/drivers/nv20/nv20_miptree.c | 68 ++++---- src/gallium/drivers/nv20/nv20_prim_vbuf.c | 132 +++++++------- src/gallium/drivers/nv20/nv20_screen.c | 54 +++--- src/gallium/drivers/nv20/nv20_screen.h | 14 +- src/gallium/drivers/nv20/nv20_state.c | 270 ++++++++++++++--------------- src/gallium/drivers/nv20/nv20_state.h | 30 ++-- src/gallium/drivers/nv20/nv20_state_emit.c | 200 ++++++++++----------- src/gallium/drivers/nv20/nv20_surface.c | 20 +-- src/gallium/drivers/nv20/nv20_vbo.c | 30 ++-- src/gallium/drivers/nv20/nv20_vertprog.c | 146 ++++++++-------- 16 files changed, 662 insertions(+), 662 deletions(-) (limited to 'src/gallium/drivers/nv20/nv20_state.c') diff --git a/src/gallium/drivers/nv20/Makefile b/src/gallium/drivers/nv20/Makefile index 76aafbe8f0..d777fd3d8b 100644 --- a/src/gallium/drivers/nv20/Makefile +++ b/src/gallium/drivers/nv20/Makefile @@ -14,8 +14,8 @@ DRIVER_SOURCES = \ nv20_state.c \ nv20_state_emit.c \ nv20_surface.c \ - nv20_vbo.c \ - nv20_vertprog.c + nv20_vbo.c +# nv20_vertprog.c C_SOURCES = \ $(COMMON_SOURCES) \ diff --git a/src/gallium/drivers/nv20/nv20_clear.c b/src/gallium/drivers/nv20/nv20_clear.c index be7e09cf4b..81b6f3e78a 100644 --- a/src/gallium/drivers/nv20/nv20_clear.c +++ b/src/gallium/drivers/nv20/nv20_clear.c @@ -2,10 +2,10 @@ #include "pipe/p_defines.h" #include "pipe/p_state.h" -#include "nv10_context.h" +#include "nv20_context.h" void -nv10_clear(struct pipe_context *pipe, struct pipe_surface *ps, +nv20_clear(struct pipe_context *pipe, struct pipe_surface *ps, unsigned clearValue) { pipe->surface_fill(pipe, ps, 0, 0, ps->width, ps->height, clearValue); diff --git a/src/gallium/drivers/nv20/nv20_context.c b/src/gallium/drivers/nv20/nv20_context.c index e9b61daae7..2af5b0203e 100644 --- a/src/gallium/drivers/nv20/nv20_context.c +++ b/src/gallium/drivers/nv20/nv20_context.c @@ -2,101 +2,101 @@ #include "pipe/p_defines.h" #include "pipe/p_winsys.h" -#include "nv10_context.h" -#include "nv10_screen.h" +#include "nv20_context.h" +#include "nv20_screen.h" static void -nv10_flush(struct pipe_context *pipe, unsigned flags, +nv20_flush(struct pipe_context *pipe, unsigned flags, struct pipe_fence_handle **fence) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - draw_flush(nv10->draw); + draw_flush(nv20->draw); FIRE_RING(fence); } static void -nv10_destroy(struct pipe_context *pipe) +nv20_destroy(struct pipe_context *pipe) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - if (nv10->draw) - draw_destroy(nv10->draw); + if (nv20->draw) + draw_destroy(nv20->draw); - FREE(nv10); + FREE(nv20); } -static void nv10_init_hwctx(struct nv10_context *nv10) +static void nv20_init_hwctx(struct nv20_context *nv20) { - struct nv10_screen *screen = nv10->screen; + struct nv20_screen *screen = nv20->screen; struct nouveau_winsys *nvws = screen->nvws; int i; float projectionmatrix[16]; - BEGIN_RING(celsius, NV10TCL_DMA_NOTIFY, 1); + BEGIN_RING(kelvin, NV10TCL_DMA_NOTIFY, 1); OUT_RING (screen->sync->handle); - BEGIN_RING(celsius, NV10TCL_DMA_IN_MEMORY0, 2); + BEGIN_RING(kelvin, NV10TCL_DMA_IN_MEMORY0, 2); OUT_RING (nvws->channel->vram->handle); OUT_RING (nvws->channel->gart->handle); - BEGIN_RING(celsius, NV10TCL_DMA_IN_MEMORY2, 2); + BEGIN_RING(kelvin, NV10TCL_DMA_IN_MEMORY2, 2); OUT_RING (nvws->channel->vram->handle); OUT_RING (nvws->channel->vram->handle); - BEGIN_RING(celsius, NV10TCL_NOP, 1); + BEGIN_RING(kelvin, NV10TCL_NOP, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_RT_HORIZ, 2); + BEGIN_RING(kelvin, NV10TCL_RT_HORIZ, 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 1); + BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 1); OUT_RING ((0x7ff<<16)|0x800); - BEGIN_RING(celsius, NV10TCL_VIEWPORT_CLIP_VERT(0), 1); + BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_VERT(0), 1); OUT_RING ((0x7ff<<16)|0x800); for (i=1;i<8;i++) { - BEGIN_RING(celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(i), 1); + BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_HORIZ(i), 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_VIEWPORT_CLIP_VERT(i), 1); + BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_VERT(i), 1); OUT_RING (0); } - BEGIN_RING(celsius, 0x290, 1); + BEGIN_RING(kelvin, 0x290, 1); OUT_RING ((0x10<<16)|1); - BEGIN_RING(celsius, 0x3f4, 1); + BEGIN_RING(kelvin, 0x3f4, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_NOP, 1); + BEGIN_RING(kelvin, NV10TCL_NOP, 1); OUT_RING (0); - if (nv10->screen->celsius->grclass != NV10TCL) { + if (nv20->screen->kelvin->grclass != NV10TCL) { /* For nv11, nv17 */ - BEGIN_RING(celsius, 0x120, 3); + BEGIN_RING(kelvin, 0x120, 3); OUT_RING (0); OUT_RING (1); OUT_RING (2); - BEGIN_RING(celsius, NV10TCL_NOP, 1); + BEGIN_RING(kelvin, NV10TCL_NOP, 1); OUT_RING (0); } - BEGIN_RING(celsius, NV10TCL_NOP, 1); + BEGIN_RING(kelvin, NV10TCL_NOP, 1); OUT_RING (0); /* Set state */ - BEGIN_RING(celsius, NV10TCL_FOG_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_FOG_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_FUNC, 2); + BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_FUNC, 2); OUT_RING (0x207); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_TX_ENABLE(0), 2); + BEGIN_RING(kelvin, NV10TCL_TX_ENABLE(0), 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_RC_IN_ALPHA(0), 12); + BEGIN_RING(kelvin, NV10TCL_RC_IN_ALPHA(0), 12); OUT_RING (0x30141010); OUT_RING (0); OUT_RING (0x20040000); @@ -110,22 +110,22 @@ static void nv10_init_hwctx(struct nv10_context *nv10) OUT_RING (0x300e0300); OUT_RING (0x0c091c80); - BEGIN_RING(celsius, NV10TCL_BLEND_FUNC_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_BLEND_FUNC_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_DITHER_ENABLE, 2); + BEGIN_RING(kelvin, NV10TCL_DITHER_ENABLE, 2); OUT_RING (1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_LINE_SMOOTH_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_LINE_SMOOTH_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_VERTEX_WEIGHT_ENABLE, 2); + BEGIN_RING(kelvin, NV10TCL_VERTEX_WEIGHT_ENABLE, 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_BLEND_FUNC_SRC, 4); + BEGIN_RING(kelvin, NV10TCL_BLEND_FUNC_SRC, 4); OUT_RING (1); OUT_RING (0); OUT_RING (0); OUT_RING (0x8006); - BEGIN_RING(celsius, NV10TCL_STENCIL_MASK, 8); + BEGIN_RING(kelvin, NV10TCL_STENCIL_MASK, 8); OUT_RING (0xff); OUT_RING (0x207); OUT_RING (0); @@ -134,103 +134,103 @@ static void nv10_init_hwctx(struct nv10_context *nv10) OUT_RING (0x1e00); OUT_RING (0x1e00); OUT_RING (0x1d01); - BEGIN_RING(celsius, NV10TCL_NORMALIZE_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_NORMALIZE_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_FOG_ENABLE, 2); + BEGIN_RING(kelvin, NV10TCL_FOG_ENABLE, 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_LIGHT_MODEL, 1); + BEGIN_RING(kelvin, NV10TCL_LIGHT_MODEL, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_COLOR_CONTROL, 1); + BEGIN_RING(kelvin, NV10TCL_COLOR_CONTROL, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_ENABLED_LIGHTS, 1); + BEGIN_RING(kelvin, NV10TCL_ENABLED_LIGHTS, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_POLYGON_OFFSET_POINT_ENABLE, 3); + BEGIN_RING(kelvin, NV10TCL_POLYGON_OFFSET_POINT_ENABLE, 3); OUT_RING (0); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_DEPTH_FUNC, 1); + BEGIN_RING(kelvin, NV10TCL_DEPTH_FUNC, 1); OUT_RING (0x201); - BEGIN_RING(celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_DEPTH_WRITE_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_DEPTH_TEST_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_DEPTH_TEST_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_POLYGON_OFFSET_FACTOR, 2); + BEGIN_RING(kelvin, NV10TCL_POLYGON_OFFSET_FACTOR, 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_POINT_SIZE, 1); + BEGIN_RING(kelvin, NV10TCL_POINT_SIZE, 1); OUT_RING (8); - BEGIN_RING(celsius, NV10TCL_POINT_PARAMETERS_ENABLE, 2); + BEGIN_RING(kelvin, NV10TCL_POINT_PARAMETERS_ENABLE, 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_LINE_WIDTH, 1); + BEGIN_RING(kelvin, NV10TCL_LINE_WIDTH, 1); OUT_RING (8); - BEGIN_RING(celsius, NV10TCL_LINE_SMOOTH_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_LINE_SMOOTH_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_POLYGON_MODE_FRONT, 2); + BEGIN_RING(kelvin, NV10TCL_POLYGON_MODE_FRONT, 2); OUT_RING (0x1b02); OUT_RING (0x1b02); - BEGIN_RING(celsius, NV10TCL_CULL_FACE, 2); + BEGIN_RING(kelvin, NV10TCL_CULL_FACE, 2); OUT_RING (0x405); OUT_RING (0x901); - BEGIN_RING(celsius, NV10TCL_POLYGON_SMOOTH_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_POLYGON_SMOOTH_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_CULL_FACE_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_CULL_FACE_ENABLE, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_CLIP_PLANE_ENABLE(0), 8); + BEGIN_RING(kelvin, NV10TCL_CLIP_PLANE_ENABLE(0), 8); for (i=0;i<8;i++) { OUT_RING (0); } - BEGIN_RING(celsius, NV10TCL_FOG_EQUATION_CONSTANT, 3); + BEGIN_RING(kelvin, NV10TCL_FOG_EQUATION_CONSTANT, 3); OUT_RING (0x3fc00000); /* -1.50 */ OUT_RING (0xbdb8aa0a); /* -0.09 */ OUT_RING (0); /* 0.00 */ - BEGIN_RING(celsius, NV10TCL_NOP, 1); + BEGIN_RING(kelvin, NV10TCL_NOP, 1); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_FOG_MODE, 2); + BEGIN_RING(kelvin, NV10TCL_FOG_MODE, 2); OUT_RING (0x802); OUT_RING (2); /* for some reason VIEW_MATRIX_ENABLE need to be 6 instead of 4 when * using texturing, except when using the texture matrix */ - BEGIN_RING(celsius, NV10TCL_VIEW_MATRIX_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_VIEW_MATRIX_ENABLE, 1); OUT_RING (6); - BEGIN_RING(celsius, NV10TCL_COLOR_MASK, 1); + BEGIN_RING(kelvin, NV10TCL_COLOR_MASK, 1); OUT_RING (0x01010101); /* Set vertex component */ - BEGIN_RING(celsius, NV10TCL_VERTEX_COL_4F_R, 4); + BEGIN_RING(kelvin, NV10TCL_VERTEX_COL_4F_R, 4); OUT_RINGf (1.0); OUT_RINGf (1.0); OUT_RINGf (1.0); OUT_RINGf (1.0); - BEGIN_RING(celsius, NV10TCL_VERTEX_COL2_3F_R, 3); + BEGIN_RING(kelvin, NV10TCL_VERTEX_COL2_3F_R, 3); OUT_RING (0); OUT_RING (0); OUT_RING (0); - BEGIN_RING(celsius, NV10TCL_VERTEX_NOR_3F_X, 3); + BEGIN_RING(kelvin, NV10TCL_VERTEX_NOR_3F_X, 3); OUT_RING (0); OUT_RING (0); OUT_RINGf (1.0); - BEGIN_RING(celsius, NV10TCL_VERTEX_TX0_4F_S, 4); + BEGIN_RING(kelvin, NV10TCL_VERTEX_TX0_4F_S, 4); OUT_RINGf (0.0); OUT_RINGf (0.0); OUT_RINGf (0.0); OUT_RINGf (1.0); - BEGIN_RING(celsius, NV10TCL_VERTEX_TX1_4F_S, 4); + BEGIN_RING(kelvin, NV10TCL_VERTEX_TX1_4F_S, 4); OUT_RINGf (0.0); OUT_RINGf (0.0); OUT_RINGf (0.0); OUT_RINGf (1.0); - BEGIN_RING(celsius, NV10TCL_VERTEX_FOG_1F, 1); + BEGIN_RING(kelvin, NV10TCL_VERTEX_FOG_1F, 1); OUT_RINGf (0.0); - BEGIN_RING(celsius, NV10TCL_EDGEFLAG_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_EDGEFLAG_ENABLE, 1); OUT_RING (1); memset(projectionmatrix, 0, sizeof(projectionmatrix)); - BEGIN_RING(celsius, NV10TCL_PROJECTION_MATRIX(0), 16); + BEGIN_RING(kelvin, NV10TCL_PROJECTION_MATRIX(0), 16); projectionmatrix[0*4+0] = 1.0; projectionmatrix[1*4+1] = 1.0; projectionmatrix[2*4+2] = 1.0; @@ -239,11 +239,11 @@ static void nv10_init_hwctx(struct nv10_context *nv10) OUT_RINGf (projectionmatrix[i]); } - BEGIN_RING(celsius, NV10TCL_DEPTH_RANGE_NEAR, 2); + BEGIN_RING(kelvin, NV10TCL_DEPTH_RANGE_NEAR, 2); OUT_RING (0.0); OUT_RINGf (16777216.0); - BEGIN_RING(celsius, NV10TCL_VIEWPORT_SCALE_X, 4); + BEGIN_RING(kelvin, NV10TCL_VIEWPORT_SCALE_X, 4); OUT_RINGf (-2048.0); OUT_RINGf (-2048.0); OUT_RINGf (16777215.0 * 0.5); @@ -253,44 +253,44 @@ static void nv10_init_hwctx(struct nv10_context *nv10) } static void -nv10_set_edgeflags(struct pipe_context *pipe, const unsigned *bitfield) +nv20_set_edgeflags(struct pipe_context *pipe, const unsigned *bitfield) { } struct pipe_context * -nv10_create(struct pipe_screen *pscreen, unsigned pctx_id) +nv20_create(struct pipe_screen *pscreen, unsigned pctx_id) { - struct nv10_screen *screen = nv10_screen(pscreen); + struct nv20_screen *screen = nv20_screen(pscreen); struct pipe_winsys *ws = pscreen->winsys; - struct nv10_context *nv10; + struct nv20_context *nv20; struct nouveau_winsys *nvws = screen->nvws; - nv10 = CALLOC(1, sizeof(struct nv10_context)); - if (!nv10) + nv20 = CALLOC(1, sizeof(struct nv20_context)); + if (!nv20) return NULL; - nv10->screen = screen; - nv10->pctx_id = pctx_id; + nv20->screen = screen; + nv20->pctx_id = pctx_id; - nv10->nvws = nvws; + nv20->nvws = nvws; - nv10->pipe.winsys = ws; - nv10->pipe.screen = pscreen; - nv10->pipe.destroy = nv10_destroy; - nv10->pipe.set_edgeflags = nv10_set_edgeflags; - nv10->pipe.draw_arrays = nv10_draw_arrays; - nv10->pipe.draw_elements = nv10_draw_elements; - nv10->pipe.clear = nv10_clear; - nv10->pipe.flush = nv10_flush; + nv20->pipe.winsys = ws; + nv20->pipe.screen = pscreen; + nv20->pipe.destroy = nv20_destroy; + nv20->pipe.set_edgeflags = nv20_set_edgeflags; + nv20->pipe.draw_arrays = nv20_draw_arrays; + nv20->pipe.draw_elements = nv20_draw_elements; + nv20->pipe.clear = nv20_clear; + nv20->pipe.flush = nv20_flush; - nv10_init_surface_functions(nv10); - nv10_init_state_functions(nv10); + nv20_init_surface_functions(nv20); + nv20_init_state_functions(nv20); - nv10->draw = draw_create(); - assert(nv10->draw); - draw_set_rasterize_stage(nv10->draw, nv10_draw_vbuf_stage(nv10)); + nv20->draw = draw_create(); + assert(nv20->draw); + draw_set_rasterize_stage(nv20->draw, nv20_draw_vbuf_stage(nv20)); - nv10_init_hwctx(nv10); + nv20_init_hwctx(nv20); - return &nv10->pipe; + return &nv20->pipe; } diff --git a/src/gallium/drivers/nv20/nv20_context.h b/src/gallium/drivers/nv20/nv20_context.h index f3b56de25a..8ad926db20 100644 --- a/src/gallium/drivers/nv20/nv20_context.h +++ b/src/gallium/drivers/nv20/nv20_context.h @@ -1,5 +1,5 @@ -#ifndef __NV10_CONTEXT_H__ -#define __NV10_CONTEXT_H__ +#ifndef __NV20_CONTEXT_H__ +#define __NV20_CONTEXT_H__ #include "pipe/p_context.h" #include "pipe/p_defines.h" @@ -15,42 +15,42 @@ #include "nouveau/nouveau_gldefs.h" #define NOUVEAU_PUSH_CONTEXT(ctx) \ - struct nv10_screen *ctx = nv10->screen + struct nv20_screen *ctx = nv20->screen #include "nouveau/nouveau_push.h" -#include "nv10_state.h" +#include "nv20_state.h" #define NOUVEAU_ERR(fmt, args...) \ fprintf(stderr, "%s:%d - "fmt, __func__, __LINE__, ##args); #define NOUVEAU_MSG(fmt, args...) \ fprintf(stderr, "nouveau: "fmt, ##args); -#define NV10_NEW_VERTPROG (1 << 0) -#define NV10_NEW_FRAGPROG (1 << 1) -#define NV10_NEW_VTXARRAYS (1 << 2) -#define NV10_NEW_BLEND (1 << 3) -#define NV10_NEW_BLENDCOL (1 << 4) -#define NV10_NEW_RAST (1 << 5) -#define NV10_NEW_DSA (1 << 6) -#define NV10_NEW_VIEWPORT (1 << 7) -#define NV10_NEW_SCISSOR (1 << 8) -#define NV10_NEW_FRAMEBUFFER (1 << 9) +#define NV20_NEW_VERTPROG (1 << 0) +#define NV20_NEW_FRAGPROG (1 << 1) +#define NV20_NEW_VTXARRAYS (1 << 2) +#define NV20_NEW_BLEND (1 << 3) +#define NV20_NEW_BLENDCOL (1 << 4) +#define NV20_NEW_RAST (1 << 5) +#define NV20_NEW_DSA (1 << 6) +#define NV20_NEW_VIEWPORT (1 << 7) +#define NV20_NEW_SCISSOR (1 << 8) +#define NV20_NEW_FRAMEBUFFER (1 << 9) -#include "nv10_screen.h" +#include "nv20_screen.h" -struct nv10_context { +struct nv20_context { struct pipe_context pipe; struct nouveau_winsys *nvws; - struct nv10_screen *screen; + struct nv20_screen *screen; unsigned pctx_id; struct draw_context *draw; uint32_t dirty; - struct nv10_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS]; - struct nv10_miptree *tex_miptree[PIPE_MAX_SAMPLERS]; + struct nv20_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS]; + struct nv20_miptree *tex_miptree[PIPE_MAX_SAMPLERS]; unsigned dirty_samplers; unsigned fp_samplers; unsigned vp_samplers; @@ -60,10 +60,10 @@ struct nv10_context { struct pipe_buffer *zeta; uint32_t lma_offset; - struct nv10_blend_state *blend; + struct nv20_blend_state *blend; struct pipe_blend_color *blend_color; - struct nv10_rasterizer_state *rast; - struct nv10_depth_stencil_alpha_state *dsa; + struct nv20_rasterizer_state *rast; + struct nv20_depth_stencil_alpha_state *dsa; struct pipe_viewport_state *viewport; struct pipe_scissor_state *scissor; struct pipe_framebuffer_state *framebuffer; @@ -90,15 +90,15 @@ struct nv10_context { struct nouveau_resource *exec_heap; struct nouveau_resource *data_heap; - struct nv10_vertex_program *active; + struct nv20_vertex_program *active; - struct nv10_vertex_program *current; + struct nv20_vertex_program *current; } vertprog; */ struct { - struct nv10_fragment_program *active; + struct nv20_fragment_program *active; - struct nv10_fragment_program *current; + struct nv20_fragment_program *current; struct pipe_buffer *constant_buf; } fragprog; @@ -106,45 +106,45 @@ struct nv10_context { struct pipe_vertex_element vtxelt[PIPE_MAX_ATTRIBS]; }; -static INLINE struct nv10_context * -nv10_context(struct pipe_context *pipe) +static INLINE struct nv20_context * +nv20_context(struct pipe_context *pipe) { - return (struct nv10_context *)pipe; + return (struct nv20_context *)pipe; } -extern void nv10_init_state_functions(struct nv10_context *nv10); -extern void nv10_init_surface_functions(struct nv10_context *nv10); +extern void nv20_init_state_functions(struct nv20_context *nv20); +extern void nv20_init_surface_functions(struct nv20_context *nv20); -extern void nv10_screen_init_miptree_functions(struct pipe_screen *pscreen); +extern void nv20_screen_init_miptree_functions(struct pipe_screen *pscreen); -/* nv10_clear.c */ -extern void nv10_clear(struct pipe_context *pipe, struct pipe_surface *ps, +/* nv20_clear.c */ +extern void nv20_clear(struct pipe_context *pipe, struct pipe_surface *ps, unsigned clearValue); -/* nv10_draw.c */ -extern struct draw_stage *nv10_draw_render_stage(struct nv10_context *nv10); +/* nv20_draw.c */ +extern struct draw_stage *nv20_draw_render_stage(struct nv20_context *nv20); -/* nv10_fragprog.c */ -extern void nv10_fragprog_bind(struct nv10_context *, - struct nv10_fragment_program *); -extern void nv10_fragprog_destroy(struct nv10_context *, - struct nv10_fragment_program *); +/* nv20_fragprog.c */ +extern void nv20_fragprog_bind(struct nv20_context *, + struct nv20_fragment_program *); +extern void nv20_fragprog_destroy(struct nv20_context *, + struct nv20_fragment_program *); -/* nv10_fragtex.c */ -extern void nv10_fragtex_bind(struct nv10_context *); +/* nv20_fragtex.c */ +extern void nv20_fragtex_bind(struct nv20_context *); -/* nv10_prim_vbuf.c */ -struct draw_stage *nv10_draw_vbuf_stage( struct nv10_context *nv10 ); -extern void nv10_vtxbuf_bind(struct nv10_context* nv10); +/* nv20_prim_vbuf.c */ +struct draw_stage *nv20_draw_vbuf_stage( struct nv20_context *nv20 ); +extern void nv20_vtxbuf_bind(struct nv20_context* nv20); -/* nv10_state.c and friends */ -extern void nv10_emit_hw_state(struct nv10_context *nv10); -extern void nv10_state_tex_update(struct nv10_context *nv10); +/* nv20_state.c and friends */ +extern void nv20_emit_hw_state(struct nv20_context *nv20); +extern void nv20_state_tex_update(struct nv20_context *nv20); -/* nv10_vbo.c */ -extern boolean nv10_draw_arrays(struct pipe_context *, unsigned mode, +/* nv20_vbo.c */ +extern boolean nv20_draw_arrays(struct pipe_context *, unsigned mode, unsigned start, unsigned count); -extern boolean nv10_draw_elements( struct pipe_context *pipe, +extern boolean nv20_draw_elements( struct pipe_context *pipe, struct pipe_buffer *indexBuffer, unsigned indexSize, unsigned prim, unsigned start, unsigned count); diff --git a/src/gallium/drivers/nv20/nv20_fragprog.c b/src/gallium/drivers/nv20/nv20_fragprog.c index 698db5a16a..4f496369dd 100644 --- a/src/gallium/drivers/nv20/nv20_fragprog.c +++ b/src/gallium/drivers/nv20/nv20_fragprog.c @@ -6,16 +6,16 @@ #include "tgsi/tgsi_parse.h" #include "tgsi/tgsi_util.h" -#include "nv10_context.h" +#include "nv20_context.h" void -nv10_fragprog_bind(struct nv10_context *nv10, struct nv10_fragment_program *fp) +nv20_fragprog_bind(struct nv20_context *nv20, struct nv20_fragment_program *fp) { } void -nv10_fragprog_destroy(struct nv10_context *nv10, - struct nv10_fragment_program *fp) +nv20_fragprog_destroy(struct nv20_context *nv20, + struct nv20_fragment_program *fp) { } diff --git a/src/gallium/drivers/nv20/nv20_fragtex.c b/src/gallium/drivers/nv20/nv20_fragtex.c index 238634d0bb..77c34897e2 100644 --- a/src/gallium/drivers/nv20/nv20_fragtex.c +++ b/src/gallium/drivers/nv20/nv20_fragtex.c @@ -1,4 +1,4 @@ -#include "nv10_context.h" +#include "nv20_context.h" static INLINE int log2i(int i) { @@ -33,14 +33,14 @@ static INLINE int log2i(int i) NV10TCL_TX_FORMAT_FORMAT_##tf, \ } -struct nv10_texture_format { +struct nv20_texture_format { boolean defined; uint pipe; int format; }; -static struct nv10_texture_format -nv10_texture_formats[] = { +static struct nv20_texture_format +nv20_texture_formats[] = { _(A8R8G8B8_UNORM, A8R8G8B8), _(A1R5G5B5_UNORM, A1R5G5B5), _(A4R4G4B4_UNORM, A4R4G4B4), @@ -54,10 +54,10 @@ nv10_texture_formats[] = { {}, }; -static struct nv10_texture_format * -nv10_fragtex_format(uint pipe_format) +static struct nv20_texture_format * +nv20_fragtex_format(uint pipe_format) { - struct nv10_texture_format *tf = nv10_texture_formats; + struct nv20_texture_format *tf = nv20_texture_formats; while (tf->defined) { if (tf->pipe == pipe_format) @@ -70,16 +70,16 @@ nv10_fragtex_format(uint pipe_format) static void -nv10_fragtex_build(struct nv10_context *nv10, int unit) +nv20_fragtex_build(struct nv20_context *nv20, int unit) { #if 0 - struct nv10_sampler_state *ps = nv10->tex_sampler[unit]; - struct nv10_miptree *nv10mt = nv10->tex_miptree[unit]; - struct pipe_texture *pt = &nv10mt->base; - struct nv10_texture_format *tf; + struct nv20_sampler_state *ps = nv20->tex_sampler[unit]; + struct nv20_miptree *nv20mt = nv20->tex_miptree[unit]; + struct pipe_texture *pt = &nv20mt->base; + struct nv20_texture_format *tf; uint32_t txf, txs, txp; - tf = nv10_fragtex_format(pt->format); + tf = nv20_fragtex_format(pt->format); if (!tf || !tf->defined) { NOUVEAU_ERR("Unsupported texture format: 0x%x\n", pt->format); return; @@ -107,9 +107,9 @@ nv10_fragtex_build(struct nv10_context *nv10, int unit) return; } - BEGIN_RING(celsius, NV10TCL_TX_OFFSET(unit), 8); - OUT_RELOCl(nv10mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); - OUT_RELOCd(nv10mt->buffer,txf,NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/); + BEGIN_RING(kelvin, NV10TCL_TX_OFFSET(unit), 8); + OUT_RELOCl(nv20mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); + OUT_RELOCd(nv20mt->buffer,txf,NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_OR | NOUVEAU_BO_RD, 1/*VRAM*/,2/*TT*/); OUT_RING (ps->wrap); OUT_RING (0x40000000); /* enable */ OUT_RING (txs); @@ -120,30 +120,30 @@ nv10_fragtex_build(struct nv10_context *nv10, int unit) } void -nv10_fragtex_bind(struct nv10_context *nv10) +nv20_fragtex_bind(struct nv20_context *nv20) { #if 0 - struct nv10_fragment_program *fp = nv10->fragprog.active; + struct nv20_fragment_program *fp = nv20->fragprog.active; unsigned samplers, unit; - samplers = nv10->fp_samplers & ~fp->samplers; + samplers = nv20->fp_samplers & ~fp->samplers; while (samplers) { unit = ffs(samplers) - 1; samplers &= ~(1 << unit); - BEGIN_RING(celsius, NV10TCL_TX_ENABLE(unit), 1); + BEGIN_RING(kelvin, NV10TCL_TX_ENABLE(unit), 1); OUT_RING (0); } - samplers = nv10->dirty_samplers & fp->samplers; + samplers = nv20->dirty_samplers & fp->samplers; while (samplers) { unit = ffs(samplers) - 1; samplers &= ~(1 << unit); - nv10_fragtex_build(nv10, unit); + nv20_fragtex_build(nv20, unit); } - nv10->fp_samplers = fp->samplers; + nv20->fp_samplers = fp->samplers; #endif } diff --git a/src/gallium/drivers/nv20/nv20_miptree.c b/src/gallium/drivers/nv20/nv20_miptree.c index ad084e72b8..dbfd779de9 100644 --- a/src/gallium/drivers/nv20/nv20_miptree.c +++ b/src/gallium/drivers/nv20/nv20_miptree.c @@ -2,13 +2,13 @@ #include "pipe/p_defines.h" #include "pipe/p_inlines.h" -#include "nv10_context.h" -#include "nv10_screen.h" +#include "nv20_context.h" +#include "nv20_screen.h" static void -nv10_miptree_layout(struct nv10_miptree *nv10mt) +nv20_miptree_layout(struct nv20_miptree *nv20mt) { - struct pipe_texture *pt = &nv10mt->base; + struct pipe_texture *pt = &nv20mt->base; boolean swizzled = FALSE; uint width = pt->width[0], height = pt->height[0]; uint offset = 0; @@ -27,12 +27,12 @@ nv10_miptree_layout(struct nv10_miptree *nv10mt) pt->nblocksy[l] = pf_get_nblocksy(&pt->block, height); if (swizzled) - nv10mt->level[l].pitch = pt->nblocksx[l] * pt->block.size; + nv20mt->level[l].pitch = pt->nblocksx[l] * pt->block.size; else - nv10mt->level[l].pitch = pt->nblocksx[0] * pt->block.size; - nv10mt->level[l].pitch = (nv10mt->level[l].pitch + 63) & ~63; + nv20mt->level[l].pitch = pt->nblocksx[0] * pt->block.size; + nv20mt->level[l].pitch = (nv20mt->level[l].pitch + 63) & ~63; - nv10mt->level[l].image_offset = + nv20mt->level[l].image_offset = CALLOC(nr_faces, sizeof(unsigned)); width = MAX2(1, width >> 1); @@ -42,28 +42,28 @@ nv10_miptree_layout(struct nv10_miptree *nv10mt) for (f = 0; f < nr_faces; f++) { for (l = 0; l <= pt->last_level; l++) { - nv10mt->level[l].image_offset[f] = offset; - offset += nv10mt->level[l].pitch * pt->height[l]; + nv20mt->level[l].image_offset[f] = offset; + offset += nv20mt->level[l].pitch * pt->height[l]; } } - nv10mt->total_size = offset; + nv20mt->total_size = offset; } static struct pipe_texture * -nv10_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt) +nv20_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt) { struct pipe_winsys *ws = screen->winsys; - struct nv10_miptree *mt; + struct nv20_miptree *mt; - mt = MALLOC(sizeof(struct nv10_miptree)); + mt = MALLOC(sizeof(struct nv20_miptree)); if (!mt) return NULL; mt->base = *pt; mt->base.refcount = 1; mt->base.screen = screen; - nv10_miptree_layout(mt); + nv20_miptree_layout(mt); mt->buffer = ws->buffer_create(ws, 256, PIPE_BUFFER_USAGE_PIXEL, mt->total_size); @@ -76,72 +76,72 @@ nv10_miptree_create(struct pipe_screen *screen, const struct pipe_texture *pt) } static void -nv10_miptree_release(struct pipe_screen *screen, struct pipe_texture **pt) +nv20_miptree_release(struct pipe_screen *screen, struct pipe_texture **pt) { struct pipe_texture *mt = *pt; *pt = NULL; if (--mt->refcount <= 0) { - struct nv10_miptree *nv10mt = (struct nv10_miptree *)mt; + struct nv20_miptree *nv20mt = (struct nv20_miptree *)mt; int l; - pipe_buffer_reference(screen, &nv10mt->buffer, NULL); + pipe_buffer_reference(screen, &nv20mt->buffer, NULL); for (l = 0; l <= mt->last_level; l++) { - if (nv10mt->level[l].image_offset) - FREE(nv10mt->level[l].image_offset); + if (nv20mt->level[l].image_offset) + FREE(nv20mt->level[l].image_offset); } - FREE(nv10mt); + FREE(nv20mt); } } static void -nv10_miptree_update(struct pipe_context *pipe, struct pipe_texture *mt, +nv20_miptree_update(struct pipe_context *pipe, struct pipe_texture *mt, uint face, uint levels) { } static struct pipe_surface * -nv10_miptree_surface_get(struct pipe_screen *screen, struct pipe_texture *pt, +nv20_miptree_surface_get(struct pipe_screen *screen, struct pipe_texture *pt, unsigned face, unsigned level, unsigned zslice, unsigned flags) { struct pipe_winsys *ws = screen->winsys; - struct nv10_miptree *nv10mt = (struct nv10_miptree *)pt; + struct nv20_miptree *nv20mt = (struct nv20_miptree *)pt; struct pipe_surface *ps; ps = ws->surface_alloc(ws); if (!ps) return NULL; - pipe_buffer_reference(screen, &ps->buffer, nv10mt->buffer); + pipe_buffer_reference(screen, &ps->buffer, nv20mt->buffer); ps->format = pt->format; ps->width = pt->width[level]; ps->height = pt->height[level]; ps->block = pt->block; ps->nblocksx = pt->nblocksx[level]; ps->nblocksy = pt->nblocksy[level]; - ps->stride = nv10mt->level[level].pitch; + ps->stride = nv20mt->level[level].pitch; if (pt->target == PIPE_TEXTURE_CUBE) { - ps->offset = nv10mt->level[level].image_offset[face]; + ps->offset = nv20mt->level[level].image_offset[face]; } else { - ps->offset = nv10mt->level[level].image_offset[0]; + ps->offset = nv20mt->level[level].image_offset[0]; } return ps; } static void -nv10_miptree_surface_release(struct pipe_screen *screen, +nv20_miptree_surface_release(struct pipe_screen *screen, struct pipe_surface **surface) { } -void nv10_screen_init_miptree_functions(struct pipe_screen *pscreen) +void nv20_screen_init_miptree_functions(struct pipe_screen *pscreen) { - pscreen->texture_create = nv10_miptree_create; - pscreen->texture_release = nv10_miptree_release; - pscreen->get_tex_surface = nv10_miptree_surface_get; - pscreen->tex_surface_release = nv10_miptree_surface_release; + pscreen->texture_create = nv20_miptree_create; + pscreen->texture_release = nv20_miptree_release; + pscreen->get_tex_surface = nv20_miptree_surface_get; + pscreen->tex_surface_release = nv20_miptree_surface_release; } diff --git a/src/gallium/drivers/nv20/nv20_prim_vbuf.c b/src/gallium/drivers/nv20/nv20_prim_vbuf.c index 62a8f6d89d..a51d657d27 100644 --- a/src/gallium/drivers/nv20/nv20_prim_vbuf.c +++ b/src/gallium/drivers/nv20/nv20_prim_vbuf.c @@ -42,18 +42,18 @@ #include "pipe/p_inlines.h" #include "pipe/p_winsys.h" -#include "nv10_context.h" -#include "nv10_state.h" +#include "nv20_context.h" +#include "nv20_state.h" #include "draw/draw_vbuf.h" /** - * Primitive renderer for nv10. + * Primitive renderer for nv20. */ -struct nv10_vbuf_render { +struct nv20_vbuf_render { struct vbuf_render base; - struct nv10_context *nv10; + struct nv20_context *nv20; /** Vertex buffer */ struct pipe_buffer* buffer; @@ -66,13 +66,13 @@ struct nv10_vbuf_render { }; -void nv10_vtxbuf_bind( struct nv10_context* nv10 ) +void nv20_vtxbuf_bind( struct nv20_context* nv20 ) { int i; for(i = 0; i < 8; i++) { - BEGIN_RING(celsius, NV10TCL_VERTEX_ARRAY_ATTRIB_OFFSET(i), 1); - OUT_RING(0/*nv10->vtxbuf*/); - BEGIN_RING(celsius, NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT(i) ,1); + BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_ATTRIB_OFFSET(i), 1); + OUT_RING(0/*nv20->vtxbuf*/); + BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT(i) ,1); OUT_RING(0/*XXX*/); } } @@ -80,75 +80,75 @@ void nv10_vtxbuf_bind( struct nv10_context* nv10 ) /** * Basically a cast wrapper. */ -static INLINE struct nv10_vbuf_render * -nv10_vbuf_render( struct vbuf_render *render ) +static INLINE struct nv20_vbuf_render * +nv20_vbuf_render( struct vbuf_render *render ) { assert(render); - return (struct nv10_vbuf_render *)render; + return (struct nv20_vbuf_render *)render; } static const struct vertex_info * -nv10_vbuf_render_get_vertex_info( struct vbuf_render *render ) +nv20_vbuf_render_get_vertex_info( struct vbuf_render *render ) { - struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render); - struct nv10_context *nv10 = nv10_render->nv10; + struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render); + struct nv20_context *nv20 = nv20_render->nv20; - nv10_emit_hw_state(nv10); + nv20_emit_hw_state(nv20); - return &nv10->vertex_info; + return &nv20->vertex_info; } static void * -nv10_vbuf_render_allocate_vertices( struct vbuf_render *render, +nv20_vbuf_render_allocate_vertices( struct vbuf_render *render, ushort vertex_size, ushort nr_vertices ) { - struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render); - struct nv10_context *nv10 = nv10_render->nv10; - struct pipe_winsys *winsys = nv10->pipe.winsys; + struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render); + struct nv20_context *nv20 = nv20_render->nv20; + struct pipe_winsys *winsys = nv20->pipe.winsys; size_t size = (size_t)vertex_size * (size_t)nr_vertices; - assert(!nv10_render->buffer); - nv10_render->buffer = winsys->buffer_create(winsys, 64, PIPE_BUFFER_USAGE_VERTEX, size); + assert(!nv20_render->buffer); + nv20_render->buffer = winsys->buffer_create(winsys, 64, PIPE_BUFFER_USAGE_VERTEX, size); - nv10->dirty |= NV10_NEW_VTXARRAYS; + nv20->dirty |= NV20_NEW_VTXARRAYS; return winsys->buffer_map(winsys, - nv10_render->buffer, + nv20_render->buffer, PIPE_BUFFER_USAGE_CPU_WRITE); } static void -nv10_vbuf_render_set_primitive( struct vbuf_render *render, +nv20_vbuf_render_set_primitive( struct vbuf_render *render, unsigned prim ) { - struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render); - nv10_render->hwprim = prim + 1; + struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render); + nv20_render->hwprim = prim + 1; } static void -nv10_vbuf_render_draw( struct vbuf_render *render, +nv20_vbuf_render_draw( struct vbuf_render *render, const ushort *indices, uint nr_indices) { - struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render); - struct nv10_context *nv10 = nv10_render->nv10; + struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render); + struct nv20_context *nv20 = nv20_render->nv20; int push, i; - nv10_emit_hw_state(nv10); + nv20_emit_hw_state(nv20); - BEGIN_RING(celsius, NV10TCL_VERTEX_ARRAY_OFFSET_POS, 1); - OUT_RELOCl(nv10_render->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); + BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_OFFSET_POS, 1); + OUT_RELOCl(nv20_render->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); - BEGIN_RING(celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1); - OUT_RING(nv10_render->hwprim); + BEGIN_RING(kelvin, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1); + OUT_RING(nv20_render->hwprim); if (nr_indices & 1) { - BEGIN_RING(celsius, NV10TCL_VB_ELEMENT_U32, 1); + BEGIN_RING(kelvin, NV10TCL_VB_ELEMENT_U32, 1); OUT_RING (indices[0]); indices++; nr_indices--; } @@ -157,7 +157,7 @@ nv10_vbuf_render_draw( struct vbuf_render *render, // XXX too big/small ? check the size push = MIN2(nr_indices, 1200 * 2); - BEGIN_RING_NI(celsius, NV10TCL_VB_ELEMENT_U16, push >> 1); + BEGIN_RING_NI(kelvin, NV10TCL_VB_ELEMENT_U16, push >> 1); for (i = 0; i < push; i+=2) OUT_RING((indices[i+1] << 16) | indices[i]); @@ -165,33 +165,33 @@ nv10_vbuf_render_draw( struct vbuf_render *render, indices += push; } - BEGIN_RING(celsius, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1); + BEGIN_RING(kelvin, NV10TCL_VERTEX_BUFFER_BEGIN_END, 1); OUT_RING (0); } static void -nv10_vbuf_render_release_vertices( struct vbuf_render *render, +nv20_vbuf_render_release_vertices( struct vbuf_render *render, void *vertices, unsigned vertex_size, unsigned vertices_used ) { - struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render); - struct nv10_context *nv10 = nv10_render->nv10; - struct pipe_winsys *winsys = nv10->pipe.winsys; - struct pipe_screen *pscreen = &nv10->screen->pipe; - - assert(nv10_render->buffer); - winsys->buffer_unmap(winsys, nv10_render->buffer); - pipe_buffer_reference(pscreen, &nv10_render->buffer, NULL); + struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render); + struct nv20_context *nv20 = nv20_render->nv20; + struct pipe_winsys *winsys = nv20->pipe.winsys; + struct pipe_screen *pscreen = &nv20->screen->pipe; + + assert(nv20_render->buffer); + winsys->buffer_unmap(winsys, nv20_render->buffer); + pipe_buffer_reference(pscreen, &nv20_render->buffer, NULL); } static void -nv10_vbuf_render_destroy( struct vbuf_render *render ) +nv20_vbuf_render_destroy( struct vbuf_render *render ) { - struct nv10_vbuf_render *nv10_render = nv10_vbuf_render(render); - FREE(nv10_render); + struct nv20_vbuf_render *nv20_render = nv20_vbuf_render(render); + FREE(nv20_render); } @@ -199,38 +199,38 @@ nv10_vbuf_render_destroy( struct vbuf_render *render ) * Create a new primitive render. */ static struct vbuf_render * -nv10_vbuf_render_create( struct nv10_context *nv10 ) +nv20_vbuf_render_create( struct nv20_context *nv20 ) { - struct nv10_vbuf_render *nv10_render = CALLOC_STRUCT(nv10_vbuf_render); + struct nv20_vbuf_render *nv20_render = CALLOC_STRUCT(nv20_vbuf_render); - nv10_render->nv10 = nv10; + nv20_render->nv20 = nv20; - nv10_render->base.max_vertex_buffer_bytes = 16*1024; - nv10_render->base.max_indices = 1024; - nv10_render->base.get_vertex_info = nv10_vbuf_render_get_vertex_info; - nv10_render->base.allocate_vertices = nv10_vbuf_render_allocate_vertices; - nv10_render->base.set_primitive = nv10_vbuf_render_set_primitive; - nv10_render->base.draw = nv10_vbuf_render_draw; - nv10_render->base.release_vertices = nv10_vbuf_render_release_vertices; - nv10_render->base.destroy = nv10_vbuf_render_destroy; + nv20_render->base.max_vertex_buffer_bytes = 16*1024; + nv20_render->base.max_indices = 1024; + nv20_render->base.get_vertex_info = nv20_vbuf_render_get_vertex_info; + nv20_render->base.allocate_vertices = nv20_vbuf_render_allocate_vertices; + nv20_render->base.set_primitive = nv20_vbuf_render_set_primitive; + nv20_render->base.draw = nv20_vbuf_render_draw; + nv20_render->base.release_vertices = nv20_vbuf_render_release_vertices; + nv20_render->base.destroy = nv20_vbuf_render_destroy; - return &nv10_render->base; + return &nv20_render->base; } /** * Create a new primitive vbuf/render stage. */ -struct draw_stage *nv10_draw_vbuf_stage( struct nv10_context *nv10 ) +struct draw_stage *nv20_draw_vbuf_stage( struct nv20_context *nv20 ) { struct vbuf_render *render; struct draw_stage *stage; - render = nv10_vbuf_render_create(nv10); + render = nv20_vbuf_render_create(nv20); if(!render) return NULL; - stage = draw_vbuf_stage( nv10->draw, render ); + stage = draw_vbuf_stage( nv20->draw, render ); if(!stage) { render->destroy(render); return NULL; diff --git a/src/gallium/drivers/nv20/nv20_screen.c b/src/gallium/drivers/nv20/nv20_screen.c index 27a9edf9bb..b7f5ea8512 100644 --- a/src/gallium/drivers/nv20/nv20_screen.c +++ b/src/gallium/drivers/nv20/nv20_screen.c @@ -1,13 +1,13 @@ #include "pipe/p_screen.h" -#include "nv10_context.h" -#include "nv10_screen.h" +#include "nv20_context.h" +#include "nv20_screen.h" static const char * -nv10_screen_get_name(struct pipe_screen *screen) +nv20_screen_get_name(struct pipe_screen *screen) { - struct nv10_screen *nv10screen = nv10_screen(screen); - struct nouveau_device *dev = nv10screen->nvws->channel->device; + struct nv20_screen *nv20screen = nv20_screen(screen); + struct nouveau_device *dev = nv20screen->nvws->channel->device; static char buffer[128]; snprintf(buffer, sizeof(buffer), "NV%02X", dev->chipset); @@ -15,13 +15,13 @@ nv10_screen_get_name(struct pipe_screen *screen) } static const char * -nv10_screen_get_vendor(struct pipe_screen *screen) +nv20_screen_get_vendor(struct pipe_screen *screen) { return "nouveau"; } static int -nv10_screen_get_param(struct pipe_screen *screen, int param) +nv20_screen_get_param(struct pipe_screen *screen, int param) { switch (param) { case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: @@ -60,7 +60,7 @@ nv10_screen_get_param(struct pipe_screen *screen, int param) } static float -nv10_screen_get_paramf(struct pipe_screen *screen, int param) +nv20_screen_get_paramf(struct pipe_screen *screen, int param) { switch (param) { case PIPE_CAP_MAX_LINE_WIDTH: @@ -80,7 +80,7 @@ nv10_screen_get_paramf(struct pipe_screen *screen, int param) } static boolean -nv10_screen_is_format_supported(struct pipe_screen *screen, +nv20_screen_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned tex_usage, unsigned geom_flags) @@ -114,7 +114,7 @@ nv10_screen_is_format_supported(struct pipe_screen *screen, } static void * -nv10_surface_map(struct pipe_screen *screen, struct pipe_surface *surface, +nv20_surface_map(struct pipe_screen *screen, struct pipe_surface *surface, unsigned flags ) { struct pipe_winsys *ws = screen->winsys; @@ -128,7 +128,7 @@ nv10_surface_map(struct pipe_screen *screen, struct pipe_surface *surface, } static void -nv10_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface) +nv20_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface) { struct pipe_winsys *ws = screen->winsys; @@ -136,21 +136,21 @@ nv10_surface_unmap(struct pipe_screen *screen, struct pipe_surface *surface) } static void -nv10_screen_destroy(struct pipe_screen *pscreen) +nv20_screen_destroy(struct pipe_screen *pscreen) { - struct nv10_screen *screen = nv10_screen(pscreen); + struct nv20_screen *screen = nv20_screen(pscreen); struct nouveau_winsys *nvws = screen->nvws; nvws->notifier_free(&screen->sync); - nvws->grobj_free(&screen->celsius); + nvws->grobj_free(&screen->kelvin); FREE(pscreen); } struct pipe_screen * -nv10_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws) +nv20_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws) { - struct nv10_screen *screen = CALLOC_STRUCT(nv10_screen); + struct nv20_screen *screen = CALLOC_STRUCT(nv20_screen); unsigned celsius_class; unsigned chipset = nvws->channel->device->chipset; int ret; @@ -174,7 +174,7 @@ nv10_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws) return NULL; } - ret = nvws->grobj_alloc(nvws, celsius_class, &screen->celsius); + ret = nvws->grobj_alloc(nvws, celsius_class, &screen->kelvin); if (ret) { NOUVEAU_ERR("Error creating 3D object: %d\n", ret); return FALSE; @@ -184,24 +184,24 @@ nv10_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws) ret = nvws->notifier_alloc(nvws, 1, &screen->sync); if (ret) { NOUVEAU_ERR("Error creating notifier object: %d\n", ret); - nv10_screen_destroy(&screen->pipe); + nv20_screen_destroy(&screen->pipe); return NULL; } screen->pipe.winsys = ws; - screen->pipe.destroy = nv10_screen_destroy; + screen->pipe.destroy = nv20_screen_destroy; - screen->pipe.get_name = nv10_screen_get_name; - screen->pipe.get_vendor = nv10_screen_get_vendor; - screen->pipe.get_param = nv10_screen_get_param; - screen->pipe.get_paramf = nv10_screen_get_paramf; + screen->pipe.get_name = nv20_screen_get_name; + screen->pipe.get_vendor = nv20_screen_get_vendor; + screen->pipe.get_param = nv20_screen_get_param; + screen->pipe.get_paramf = nv20_screen_get_paramf; - screen->pipe.is_format_supported = nv10_screen_is_format_supported; + screen->pipe.is_format_supported = nv20_screen_is_format_supported; - screen->pipe.surface_map = nv10_surface_map; - screen->pipe.surface_unmap = nv10_surface_unmap; + screen->pipe.surface_map = nv20_surface_map; + screen->pipe.surface_unmap = nv20_surface_unmap; - nv10_screen_init_miptree_functions(&screen->pipe); + nv20_screen_init_miptree_functions(&screen->pipe); return &screen->pipe; } diff --git a/src/gallium/drivers/nv20/nv20_screen.h b/src/gallium/drivers/nv20/nv20_screen.h index 3f8750a13f..8f2f2e341d 100644 --- a/src/gallium/drivers/nv20/nv20_screen.h +++ b/src/gallium/drivers/nv20/nv20_screen.h @@ -1,22 +1,22 @@ -#ifndef __NV10_SCREEN_H__ -#define __NV10_SCREEN_H__ +#ifndef __NV20_SCREEN_H__ +#define __NV20_SCREEN_H__ #include "pipe/p_screen.h" -struct nv10_screen { +struct nv20_screen { struct pipe_screen pipe; struct nouveau_winsys *nvws; /* HW graphics objects */ - struct nouveau_grobj *celsius; + struct nouveau_grobj *kelvin; struct nouveau_notifier *sync; }; -static INLINE struct nv10_screen * -nv10_screen(struct pipe_screen *screen) +static INLINE struct nv20_screen * +nv20_screen(struct pipe_screen *screen) { - return (struct nv10_screen *)screen; + return (struct nv20_screen *)screen; } #endif diff --git a/src/gallium/drivers/nv20/nv20_state.c b/src/gallium/drivers/nv20/nv20_state.c index d2375aa2f6..c3b87230b7 100644 --- a/src/gallium/drivers/nv20/nv20_state.c +++ b/src/gallium/drivers/nv20/nv20_state.c @@ -5,16 +5,16 @@ #include "tgsi/tgsi_parse.h" -#include "nv10_context.h" -#include "nv10_state.h" +#include "nv20_context.h" +#include "nv20_state.h" static void * -nv10_blend_state_create(struct pipe_context *pipe, +nv20_blend_state_create(struct pipe_context *pipe, const struct pipe_blend_state *cso) { - struct nv10_blend_state *cb; + struct nv20_blend_state *cb; - cb = MALLOC(sizeof(struct nv10_blend_state)); + cb = MALLOC(sizeof(struct nv20_blend_state)); cb->b_enable = cso->blend_enable ? 1 : 0; cb->b_srcfunc = ((nvgl_blend_func(cso->alpha_src_factor)<<16) | @@ -33,17 +33,17 @@ nv10_blend_state_create(struct pipe_context *pipe, } static void -nv10_blend_state_bind(struct pipe_context *pipe, void *blend) +nv20_blend_state_bind(struct pipe_context *pipe, void *blend) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - nv10->blend = (struct nv10_blend_state*)blend; + nv20->blend = (struct nv20_blend_state*)blend; - nv10->dirty |= NV10_NEW_BLEND; + nv20->dirty |= NV20_NEW_BLEND; } static void -nv10_blend_state_delete(struct pipe_context *pipe, void *hwcso) +nv20_blend_state_delete(struct pipe_context *pipe, void *hwcso) { FREE(hwcso); } @@ -82,13 +82,13 @@ wrap_mode(unsigned wrap) { } static void * -nv10_sampler_state_create(struct pipe_context *pipe, +nv20_sampler_state_create(struct pipe_context *pipe, const struct pipe_sampler_state *cso) { - struct nv10_sampler_state *ps; + struct nv20_sampler_state *ps; uint32_t filter = 0; - ps = MALLOC(sizeof(struct nv10_sampler_state)); + ps = MALLOC(sizeof(struct nv20_sampler_state)); ps->wrap = ((wrap_mode(cso->wrap_s) << NV10TCL_TX_FORMAT_WRAP_S_SHIFT) | (wrap_mode(cso->wrap_t) << NV10TCL_TX_FORMAT_WRAP_T_SHIFT)); @@ -204,41 +204,41 @@ nv10_sampler_state_create(struct pipe_context *pipe, } static void -nv10_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler) +nv20_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); unsigned unit; for (unit = 0; unit < nr; unit++) { - nv10->tex_sampler[unit] = sampler[unit]; - nv10->dirty_samplers |= (1 << unit); + nv20->tex_sampler[unit] = sampler[unit]; + nv20->dirty_samplers |= (1 << unit); } } static void -nv10_sampler_state_delete(struct pipe_context *pipe, void *hwcso) +nv20_sampler_state_delete(struct pipe_context *pipe, void *hwcso) { FREE(hwcso); } static void -nv10_set_sampler_texture(struct pipe_context *pipe, unsigned nr, +nv20_set_sampler_texture(struct pipe_context *pipe, unsigned nr, struct pipe_texture **miptree) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); unsigned unit; for (unit = 0; unit < nr; unit++) { - nv10->tex_miptree[unit] = (struct nv10_miptree *)miptree[unit]; - nv10->dirty_samplers |= (1 << unit); + nv20->tex_miptree[unit] = (struct nv20_miptree *)miptree[unit]; + nv20->dirty_samplers |= (1 << unit); } } static void * -nv10_rasterizer_state_create(struct pipe_context *pipe, +nv20_rasterizer_state_create(struct pipe_context *pipe, const struct pipe_rasterizer_state *cso) { - struct nv10_rasterizer_state *rs; + struct nv20_rasterizer_state *rs; int i; /*XXX: ignored: @@ -249,7 +249,7 @@ nv10_rasterizer_state_create(struct pipe_context *pipe, * multisample * offset_units / offset_scale */ - rs = MALLOC(sizeof(struct nv10_rasterizer_state)); + rs = MALLOC(sizeof(struct nv20_rasterizer_state)); rs->templ = cso; @@ -312,30 +312,30 @@ nv10_rasterizer_state_create(struct pipe_context *pipe, } static void -nv10_rasterizer_state_bind(struct pipe_context *pipe, void *rast) +nv20_rasterizer_state_bind(struct pipe_context *pipe, void *rast) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - nv10->rast = (struct nv10_rasterizer_state*)rast; + nv20->rast = (struct nv20_rasterizer_state*)rast; - draw_set_rasterizer_state(nv10->draw, (nv10->rast ? nv10->rast->templ : NULL)); + draw_set_rasterizer_state(nv20->draw, (nv20->rast ? nv20->rast->templ : NULL)); - nv10->dirty |= NV10_NEW_RAST; + nv20->dirty |= NV20_NEW_RAST; } static void -nv10_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso) +nv20_rasterizer_state_delete(struct pipe_context *pipe, void *hwcso) { FREE(hwcso); } static void * -nv10_depth_stencil_alpha_state_create(struct pipe_context *pipe, +nv20_depth_stencil_alpha_state_create(struct pipe_context *pipe, const struct pipe_depth_stencil_alpha_state *cso) { - struct nv10_depth_stencil_alpha_state *hw; + struct nv20_depth_stencil_alpha_state *hw; - hw = MALLOC(sizeof(struct nv10_depth_stencil_alpha_state)); + hw = MALLOC(sizeof(struct nv20_depth_stencil_alpha_state)); hw->depth.func = nvgl_comparison_op(cso->depth.func); hw->depth.write_enable = cso->depth.writemask ? 1 : 0; @@ -358,55 +358,55 @@ nv10_depth_stencil_alpha_state_create(struct pipe_context *pipe, } static void -nv10_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *dsa) +nv20_depth_stencil_alpha_state_bind(struct pipe_context *pipe, void *dsa) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - nv10->dsa = (struct nv10_depth_stencil_alpha_state*)dsa; + nv20->dsa = (struct nv20_depth_stencil_alpha_state*)dsa; - nv10->dirty |= NV10_NEW_DSA; + nv20->dirty |= NV20_NEW_DSA; } static void -nv10_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso) +nv20_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso) { FREE(hwcso); } static void * -nv10_vp_state_create(struct pipe_context *pipe, +nv20_vp_state_create(struct pipe_context *pipe, const struct pipe_shader_state *templ) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - return draw_create_vertex_shader(nv10->draw, templ); + return draw_create_vertex_shader(nv20->draw, templ); } static void -nv10_vp_state_bind(struct pipe_context *pipe, void *shader) +nv20_vp_state_bind(struct pipe_context *pipe, void *shader) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - draw_bind_vertex_shader(nv10->draw, (struct draw_vertex_shader *) shader); + draw_bind_vertex_shader(nv20->draw, (struct draw_vertex_shader *) shader); - nv10->dirty |= NV10_NEW_VERTPROG; + nv20->dirty |= NV20_NEW_VERTPROG; } static void -nv10_vp_state_delete(struct pipe_context *pipe, void *shader) +nv20_vp_state_delete(struct pipe_context *pipe, void *shader) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - draw_delete_vertex_shader(nv10->draw, (struct draw_vertex_shader *) shader); + draw_delete_vertex_shader(nv20->draw, (struct draw_vertex_shader *) shader); } static void * -nv10_fp_state_create(struct pipe_context *pipe, +nv20_fp_state_create(struct pipe_context *pipe, const struct pipe_shader_state *cso) { - struct nv10_fragment_program *fp; + struct nv20_fragment_program *fp; - fp = CALLOC(1, sizeof(struct nv10_fragment_program)); + fp = CALLOC(1, sizeof(struct nv20_fragment_program)); fp->pipe.tokens = tgsi_dup_tokens(cso->tokens); tgsi_scan_shader(cso->tokens, &fp->info); @@ -415,51 +415,51 @@ nv10_fp_state_create(struct pipe_context *pipe, } static void -nv10_fp_state_bind(struct pipe_context *pipe, void *hwcso) +nv20_fp_state_bind(struct pipe_context *pipe, void *hwcso) { - struct nv10_context *nv10 = nv10_context(pipe); - struct nv10_fragment_program *fp = hwcso; + struct nv20_context *nv20 = nv20_context(pipe); + struct nv20_fragment_program *fp = hwcso; - nv10->fragprog.current = fp; - nv10->dirty |= NV10_NEW_FRAGPROG; + nv20->fragprog.current = fp; + nv20->dirty |= NV20_NEW_FRAGPROG; } static void -nv10_fp_state_delete(struct pipe_context *pipe, void *hwcso) +nv20_fp_state_delete(struct pipe_context *pipe, void *hwcso) { - struct nv10_context *nv10 = nv10_context(pipe); - struct nv10_fragment_program *fp = hwcso; + struct nv20_context *nv20 = nv20_context(pipe); + struct nv20_fragment_program *fp = hwcso; - nv10_fragprog_destroy(nv10, fp); + nv20_fragprog_destroy(nv20, fp); FREE((void*)fp->pipe.tokens); FREE(fp); } static void -nv10_set_blend_color(struct pipe_context *pipe, +nv20_set_blend_color(struct pipe_context *pipe, const struct pipe_blend_color *bcol) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - nv10->blend_color = (struct pipe_blend_color*)bcol; + nv20->blend_color = (struct pipe_blend_color*)bcol; - nv10->dirty |= NV10_NEW_BLENDCOL; + nv20->dirty |= NV20_NEW_BLENDCOL; } static void -nv10_set_clip_state(struct pipe_context *pipe, +nv20_set_clip_state(struct pipe_context *pipe, const struct pipe_clip_state *clip) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - draw_set_clip_state(nv10->draw, clip); + draw_set_clip_state(nv20->draw, clip); } static void -nv10_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, +nv20_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, const struct pipe_constant_buffer *buf ) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); struct pipe_winsys *ws = pipe->winsys; assert(shader < PIPE_SHADER_TYPES); @@ -469,8 +469,8 @@ nv10_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, void *mapped; if (buf->size && (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ))) { - memcpy(nv10->constbuf[shader], mapped, buf->size); - nv10->constbuf_nr[shader] = + memcpy(nv20->constbuf[shader], mapped, buf->size); + nv20->constbuf_nr[shader] = buf->size / (4 * sizeof(float)); ws->buffer_unmap(ws, buf->buffer); } @@ -478,111 +478,111 @@ nv10_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, } static void -nv10_set_framebuffer_state(struct pipe_context *pipe, +nv20_set_framebuffer_state(struct pipe_context *pipe, const struct pipe_framebuffer_state *fb) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - nv10->framebuffer = (struct pipe_framebuffer_state*)fb; + nv20->framebuffer = (struct pipe_framebuffer_state*)fb; - nv10->dirty |= NV10_NEW_FRAMEBUFFER; + nv20->dirty |= NV20_NEW_FRAMEBUFFER; } static void -nv10_set_polygon_stipple(struct pipe_context *pipe, +nv20_set_polygon_stipple(struct pipe_context *pipe, const struct pipe_poly_stipple *stipple) { NOUVEAU_ERR("line stipple hahaha\n"); } static void -nv10_set_scissor_state(struct pipe_context *pipe, +nv20_set_scissor_state(struct pipe_context *pipe, const struct pipe_scissor_state *s) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - nv10->scissor = (struct pipe_scissor_state*)s; + nv20->scissor = (struct pipe_scissor_state*)s; - nv10->dirty |= NV10_NEW_SCISSOR; + nv20->dirty |= NV20_NEW_SCISSOR; } static void -nv10_set_viewport_state(struct pipe_context *pipe, +nv20_set_viewport_state(struct pipe_context *pipe, const struct pipe_viewport_state *vpt) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - nv10->viewport = (struct pipe_viewport_state*)vpt; + nv20->viewport = (struct pipe_viewport_state*)vpt; - draw_set_viewport_state(nv10->draw, nv10->viewport); + draw_set_viewport_state(nv20->draw, nv20->viewport); - nv10->dirty |= NV10_NEW_VIEWPORT; + nv20->dirty |= NV20_NEW_VIEWPORT; } static void -nv10_set_vertex_buffers(struct pipe_context *pipe, unsigned count, +nv20_set_vertex_buffers(struct pipe_context *pipe, unsigned count, const struct pipe_vertex_buffer *vb) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - memcpy(nv10->vtxbuf, vb, sizeof(*vb) * count); - nv10->dirty |= NV10_NEW_VTXARRAYS; + memcpy(nv20->vtxbuf, vb, sizeof(*vb) * count); + nv20->dirty |= NV20_NEW_VTXARRAYS; - draw_set_vertex_buffers(nv10->draw, count, vb); + draw_set_vertex_buffers(nv20->draw, count, vb); } static void -nv10_set_vertex_elements(struct pipe_context *pipe, unsigned count, +nv20_set_vertex_elements(struct pipe_context *pipe, unsigned count, const struct pipe_vertex_element *ve) { - struct nv10_context *nv10 = nv10_context(pipe); + struct nv20_context *nv20 = nv20_context(pipe); - memcpy(nv10->vtxelt, ve, sizeof(*ve) * count); - nv10->dirty |= NV10_NEW_VTXARRAYS; + memcpy(nv20->vtxelt, ve, sizeof(*ve) * count); + nv20->dirty |= NV20_NEW_VTXARRAYS; - draw_set_vertex_elements(nv10->draw, count, ve); + draw_set_vertex_elements(nv20->draw, count, ve); } void -nv10_init_state_functions(struct nv10_context *nv10) +nv20_init_state_functions(struct nv20_context *nv20) { - nv10->pipe.create_blend_state = nv10_blend_state_create; - nv10->pipe.bind_blend_state = nv10_blend_state_bind; - nv10->pipe.delete_blend_state = nv10_blend_state_delete; - - nv10->pipe.create_sampler_state = nv10_sampler_state_create; - nv10->pipe.bind_sampler_states = nv10_sampler_state_bind; - nv10->pipe.delete_sampler_state = nv10_sampler_state_delete; - nv10->pipe.set_sampler_textures = nv10_set_sampler_texture; - - nv10->pipe.create_rasterizer_state = nv10_rasterizer_state_create; - nv10->pipe.bind_rasterizer_state = nv10_rasterizer_state_bind; - nv10->pipe.delete_rasterizer_state = nv10_rasterizer_state_delete; - - nv10->pipe.create_depth_stencil_alpha_state = - nv10_depth_stencil_alpha_state_create; - nv10->pipe.bind_depth_stencil_alpha_state = - nv10_depth_stencil_alpha_state_bind; - nv10->pipe.delete_depth_stencil_alpha_state = - nv10_depth_stencil_alpha_state_delete; - - nv10->pipe.create_vs_state = nv10_vp_state_create; - nv10->pipe.bind_vs_state = nv10_vp_state_bind; - nv10->pipe.delete_vs_state = nv10_vp_state_delete; - - nv10->pipe.create_fs_state = nv10_fp_state_create; - nv10->pipe.bind_fs_state = nv10_fp_state_bind; - nv10->pipe.delete_fs_state = nv10_fp_state_delete; - - nv10->pipe.set_blend_color = nv10_set_blend_color; - nv10->pipe.set_clip_state = nv10_set_clip_state; - nv10->pipe.set_constant_buffer = nv10_set_constant_buffer; - nv10->pipe.set_framebuffer_state = nv10_set_framebuffer_state; - nv10->pipe.set_polygon_stipple = nv10_set_polygon_stipple; - nv10->pipe.set_scissor_state = nv10_set_scissor_state; - nv10->pipe.set_viewport_state = nv10_set_viewport_state; - - nv10->pipe.set_vertex_buffers = nv10_set_vertex_buffers; - nv10->pipe.set_vertex_elements = nv10_set_vertex_elements; + nv20->pipe.create_blend_state = nv20_blend_state_create; + nv20->pipe.bind_blend_state = nv20_blend_state_bind; + nv20->pipe.delete_blend_state = nv20_blend_state_delete; + + nv20->pipe.create_sampler_state = nv20_sampler_state_create; + nv20->pipe.bind_sampler_states = nv20_sampler_state_bind; + nv20->pipe.delete_sampler_state = nv20_sampler_state_delete; + nv20->pipe.set_sampler_textures = nv20_set_sampler_texture; + + nv20->pipe.create_rasterizer_state = nv20_rasterizer_state_create; + nv20->pipe.bind_rasterizer_state = nv20_rasterizer_state_bind; + nv20->pipe.delete_rasterizer_state = nv20_rasterizer_state_delete; + + nv20->pipe.create_depth_stencil_alpha_state = + nv20_depth_stencil_alpha_state_create; + nv20->pipe.bind_depth_stencil_alpha_state = + nv20_depth_stencil_alpha_state_bind; + nv20->pipe.delete_depth_stencil_alpha_state = + nv20_depth_stencil_alpha_state_delete; + + nv20->pipe.create_vs_state = nv20_vp_state_create; + nv20->pipe.bind_vs_state = nv20_vp_state_bind; + nv20->pipe.delete_vs_state = nv20_vp_state_delete; + + nv20->pipe.create_fs_state = nv20_fp_state_create; + nv20->pipe.bind_fs_state = nv20_fp_state_bind; + nv20->pipe.delete_fs_state = nv20_fp_state_delete; + + nv20->pipe.set_blend_color = nv20_set_blend_color; + nv20->pipe.set_clip_state = nv20_set_clip_state; + nv20->pipe.set_constant_buffer = nv20_set_constant_buffer; + nv20->pipe.set_framebuffer_state = nv20_set_framebuffer_state; + nv20->pipe.set_polygon_stipple = nv20_set_polygon_stipple; + nv20->pipe.set_scissor_state = nv20_set_scissor_state; + nv20->pipe.set_viewport_state = nv20_set_viewport_state; + + nv20->pipe.set_vertex_buffers = nv20_set_vertex_buffers; + nv20->pipe.set_vertex_elements = nv20_set_vertex_elements; } diff --git a/src/gallium/drivers/nv20/nv20_state.h b/src/gallium/drivers/nv20/nv20_state.h index 3a3fd0d4f4..34f402fdcb 100644 --- a/src/gallium/drivers/nv20/nv20_state.h +++ b/src/gallium/drivers/nv20/nv20_state.h @@ -1,10 +1,10 @@ -#ifndef __NV10_STATE_H__ -#define __NV10_STATE_H__ +#ifndef __NV20_STATE_H__ +#define __NV20_STATE_H__ #include "pipe/p_state.h" #include "tgsi/tgsi_scan.h" -struct nv10_blend_state { +struct nv20_blend_state { uint32_t b_enable; uint32_t b_srcfunc; uint32_t b_dstfunc; @@ -14,14 +14,14 @@ struct nv10_blend_state { uint32_t d_enable; }; -struct nv10_sampler_state { +struct nv20_sampler_state { uint32_t wrap; uint32_t en; uint32_t filt; uint32_t bcol; }; -struct nv10_rasterizer_state { +struct nv20_rasterizer_state { uint32_t shade_model; uint32_t line_width; @@ -43,24 +43,24 @@ struct nv10_rasterizer_state { const struct pipe_rasterizer_state *templ; }; -struct nv10_vertex_program_exec { +struct nv20_vertex_program_exec { uint32_t data[4]; boolean has_branch_offset; int const_index; }; -struct nv10_vertex_program_data { +struct nv20_vertex_program_data { int index; /* immediates == -1 */ float value[4]; }; -struct nv10_vertex_program { +struct nv20_vertex_program { const struct pipe_shader_state *pipe; boolean translated; - struct nv10_vertex_program_exec *insns; + struct nv20_vertex_program_exec *insns; unsigned nr_insns; - struct nv10_vertex_program_data *consts; + struct nv20_vertex_program_data *consts; unsigned nr_consts; struct nouveau_resource *exec; @@ -73,12 +73,12 @@ struct nv10_vertex_program { uint32_t or; }; -struct nv10_fragment_program_data { +struct nv20_fragment_program_data { unsigned offset; unsigned index; }; -struct nv10_fragment_program { +struct nv20_fragment_program { struct pipe_shader_state pipe; struct tgsi_shader_info info; @@ -89,7 +89,7 @@ struct nv10_fragment_program { uint32_t *insn; int insn_len; - struct nv10_fragment_program_data *consts; + struct nv20_fragment_program_data *consts; unsigned nr_consts; struct pipe_buffer *buffer; @@ -99,7 +99,7 @@ struct nv10_fragment_program { }; -struct nv10_depth_stencil_alpha_state { +struct nv20_depth_stencil_alpha_state { struct { uint32_t func; uint32_t write_enable; @@ -124,7 +124,7 @@ struct nv10_depth_stencil_alpha_state { } alpha; }; -struct nv10_miptree { +struct nv20_miptree { struct pipe_texture base; struct pipe_buffer *buffer; diff --git a/src/gallium/drivers/nv20/nv20_state_emit.c b/src/gallium/drivers/nv20/nv20_state_emit.c index 46c7e1d753..23029433f3 100644 --- a/src/gallium/drivers/nv20/nv20_state_emit.c +++ b/src/gallium/drivers/nv20/nv20_state_emit.c @@ -1,108 +1,108 @@ -#include "nv10_context.h" -#include "nv10_state.h" +#include "nv20_context.h" +#include "nv20_state.h" -static void nv10_state_emit_blend(struct nv10_context* nv10) +static void nv20_state_emit_blend(struct nv20_context* nv20) { - struct nv10_blend_state *b = nv10->blend; + struct nv20_blend_state *b = nv20->blend; - BEGIN_RING(celsius, NV10TCL_DITHER_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_DITHER_ENABLE, 1); OUT_RING (b->d_enable); - BEGIN_RING(celsius, NV10TCL_BLEND_FUNC_ENABLE, 3); + BEGIN_RING(kelvin, NV10TCL_BLEND_FUNC_ENABLE, 3); OUT_RING (b->b_enable); OUT_RING (b->b_srcfunc); OUT_RING (b->b_dstfunc); - BEGIN_RING(celsius, NV10TCL_COLOR_MASK, 1); + BEGIN_RING(kelvin, NV10TCL_COLOR_MASK, 1); OUT_RING (b->c_mask); } -static void nv10_state_emit_blend_color(struct nv10_context* nv10) +static void nv20_state_emit_blend_color(struct nv20_context* nv20) { - struct pipe_blend_color *c = nv10->blend_color; + struct pipe_blend_color *c = nv20->blend_color; - BEGIN_RING(celsius, NV10TCL_BLEND_COLOR, 1); + BEGIN_RING(kelvin, NV10TCL_BLEND_COLOR, 1); OUT_RING ((float_to_ubyte(c->color[3]) << 24)| (float_to_ubyte(c->color[0]) << 16)| (float_to_ubyte(c->color[1]) << 8) | (float_to_ubyte(c->color[2]) << 0)); } -static void nv10_state_emit_rast(struct nv10_context* nv10) +static void nv20_state_emit_rast(struct nv20_context* nv20) { - struct nv10_rasterizer_state *r = nv10->rast; + struct nv20_rasterizer_state *r = nv20->rast; - BEGIN_RING(celsius, NV10TCL_SHADE_MODEL, 2); + BEGIN_RING(kelvin, NV10TCL_SHADE_MODEL, 2); OUT_RING (r->shade_model); OUT_RING (r->line_width); - BEGIN_RING(celsius, NV10TCL_POINT_SIZE, 1); + BEGIN_RING(kelvin, NV10TCL_POINT_SIZE, 1); OUT_RING (r->point_size); - BEGIN_RING(celsius, NV10TCL_POLYGON_MODE_FRONT, 2); + BEGIN_RING(kelvin, NV10TCL_POLYGON_MODE_FRONT, 2); OUT_RING (r->poly_mode_front); OUT_RING (r->poly_mode_back); - BEGIN_RING(celsius, NV10TCL_CULL_FACE, 2); + BEGIN_RING(kelvin, NV10TCL_CULL_FACE, 2); OUT_RING (r->cull_face); OUT_RING (r->front_face); - BEGIN_RING(celsius, NV10TCL_LINE_SMOOTH_ENABLE, 2); + BEGIN_RING(kelvin, NV10TCL_LINE_SMOOTH_ENABLE, 2); OUT_RING (r->line_smooth_en); OUT_RING (r->poly_smooth_en); - BEGIN_RING(celsius, NV10TCL_CULL_FACE_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_CULL_FACE_ENABLE, 1); OUT_RING (r->cull_face_en); } -static void nv10_state_emit_dsa(struct nv10_context* nv10) +static void nv20_state_emit_dsa(struct nv20_context* nv20) { - struct nv10_depth_stencil_alpha_state *d = nv10->dsa; + struct nv20_depth_stencil_alpha_state *d = nv20->dsa; - BEGIN_RING(celsius, NV10TCL_DEPTH_FUNC, 1); + BEGIN_RING(kelvin, NV10TCL_DEPTH_FUNC, 1); OUT_RING (d->depth.func); - BEGIN_RING(celsius, NV10TCL_DEPTH_WRITE_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_DEPTH_WRITE_ENABLE, 1); OUT_RING (d->depth.write_enable); - BEGIN_RING(celsius, NV10TCL_DEPTH_TEST_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_DEPTH_TEST_ENABLE, 1); OUT_RING (d->depth.test_enable); #if 0 - BEGIN_RING(celsius, NV10TCL_STENCIL_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_STENCIL_ENABLE, 1); OUT_RING (d->stencil.enable); - BEGIN_RING(celsius, NV10TCL_STENCIL_MASK, 7); + BEGIN_RING(kelvin, NV10TCL_STENCIL_MASK, 7); OUT_RINGp ((uint32_t *)&(d->stencil.wmask), 7); #endif - BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_ENABLE, 1); + BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_ENABLE, 1); OUT_RING (d->alpha.enabled); - BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_FUNC, 1); + BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_FUNC, 1); OUT_RING (d->alpha.func); - BEGIN_RING(celsius, NV10TCL_ALPHA_FUNC_REF, 1); + BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_REF, 1); OUT_RING (d->alpha.ref); } -static void nv10_state_emit_viewport(struct nv10_context* nv10) +static void nv20_state_emit_viewport(struct nv20_context* nv20) { } -static void nv10_state_emit_scissor(struct nv10_context* nv10) +static void nv20_state_emit_scissor(struct nv20_context* nv20) { // XXX this is so not working -/* struct pipe_scissor_state *s = nv10->scissor; - BEGIN_RING(celsius, NV10TCL_SCISSOR_HORIZ, 2); +/* struct pipe_scissor_state *s = nv20->scissor; + BEGIN_RING(kelvin, NV10TCL_SCISSOR_HORIZ, 2); OUT_RING (((s->maxx - s->minx) << 16) | s->minx); OUT_RING (((s->maxy - s->miny) << 16) | s->miny);*/ } -static void nv10_state_emit_framebuffer(struct nv10_context* nv10) +static void nv20_state_emit_framebuffer(struct nv20_context* nv20) { - struct pipe_framebuffer_state* fb = nv10->framebuffer; + struct pipe_framebuffer_state* fb = nv20->framebuffer; struct pipe_surface *rt, *zeta = NULL; uint32_t rt_format, w, h; int colour_format = 0, zeta_format = 0; @@ -140,32 +140,32 @@ static void nv10_state_emit_framebuffer(struct nv10_context* nv10) } if (zeta) { - BEGIN_RING(celsius, NV10TCL_RT_PITCH, 1); + BEGIN_RING(kelvin, NV10TCL_RT_PITCH, 1); OUT_RING (rt->stride | (zeta->stride << 16)); } else { - BEGIN_RING(celsius, NV10TCL_RT_PITCH, 1); + BEGIN_RING(kelvin, NV10TCL_RT_PITCH, 1); OUT_RING (rt->stride | (rt->stride << 16)); } - nv10->rt[0] = rt->buffer; + nv20->rt[0] = rt->buffer; if (zeta_format) { - nv10->zeta = zeta->buffer; + nv20->zeta = zeta->buffer; } - BEGIN_RING(celsius, NV10TCL_RT_HORIZ, 3); + BEGIN_RING(kelvin, NV10TCL_RT_HORIZ, 3); OUT_RING ((w << 16) | 0); OUT_RING ((h << 16) | 0); OUT_RING (rt_format); - BEGIN_RING(celsius, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2); + BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2); OUT_RING (((w - 1) << 16) | 0 | 0x08000800); OUT_RING (((h - 1) << 16) | 0 | 0x08000800); } -static void nv10_vertex_layout(struct nv10_context *nv10) +static void nv20_vertex_layout(struct nv20_context *nv20) { - struct nv10_fragment_program *fp = nv10->fragprog.current; + struct nv20_fragment_program *fp = nv20->fragprog.current; uint32_t src = 0; int i; struct vertex_info vinfo; @@ -193,108 +193,108 @@ static void nv10_vertex_layout(struct nv10_context *nv10) } void -nv10_emit_hw_state(struct nv10_context *nv10) +nv20_emit_hw_state(struct nv20_context *nv20) { int i; - if (nv10->dirty & NV10_NEW_VERTPROG) { - //nv10_vertprog_bind(nv10, nv10->vertprog.current); - nv10->dirty &= ~NV10_NEW_VERTPROG; + if (nv20->dirty & NV20_NEW_VERTPROG) { + //nv20_vertprog_bind(nv20, nv20->vertprog.current); + nv20->dirty &= ~NV20_NEW_VERTPROG; } - if (nv10->dirty & NV10_NEW_FRAGPROG) { - nv10_fragprog_bind(nv10, nv10->fragprog.current); - /*XXX: clear NV10_NEW_FRAGPROG if no new program uploaded */ - nv10->dirty_samplers |= (1<<10); - nv10->dirty_samplers = 0; + if (nv20->dirty & NV20_NEW_FRAGPROG) { + nv20_fragprog_bind(nv20, nv20->fragprog.current); + /*XXX: clear NV20_NEW_FRAGPROG if no new program uploaded */ + nv20->dirty_samplers |= (1<<10); + nv20->dirty_samplers = 0; } - if (nv10->dirty_samplers || (nv10->dirty & NV10_NEW_FRAGPROG)) { - nv10_fragtex_bind(nv10); - nv10->dirty &= ~NV10_NEW_FRAGPROG; + if (nv20->dirty_samplers || (nv20->dirty & NV20_NEW_FRAGPROG)) { + nv20_fragtex_bind(nv20); + nv20->dirty &= ~NV20_NEW_FRAGPROG; } - if (nv10->dirty & NV10_NEW_VTXARRAYS) { - nv10->dirty &= ~NV10_NEW_VTXARRAYS; - nv10_vertex_layout(nv10); - nv10_vtxbuf_bind(nv10); + if (nv20->dirty & NV20_NEW_VTXARRAYS) { + nv20->dirty &= ~NV20_NEW_VTXARRAYS; + nv20_vertex_layout(nv20); + nv20_vtxbuf_bind(nv20); } - if (nv10->dirty & NV10_NEW_BLEND) { - nv10->dirty &= ~NV10_NEW_BLEND; - nv10_state_emit_blend(nv10); + if (nv20->dirty & NV20_NEW_BLEND) { + nv20->dirty &= ~NV20_NEW_BLEND; + nv20_state_emit_blend(nv20); } - if (nv10->dirty & NV10_NEW_BLENDCOL) { - nv10->dirty &= ~NV10_NEW_BLENDCOL; - nv10_state_emit_blend_color(nv10); + if (nv20->dirty & NV20_NEW_BLENDCOL) { + nv20->dirty &= ~NV20_NEW_BLENDCOL; + nv20_state_emit_blend_color(nv20); } - if (nv10->dirty & NV10_NEW_RAST) { - nv10->dirty &= ~NV10_NEW_RAST; - nv10_state_emit_rast(nv10); + if (nv20->dirty & NV20_NEW_RAST) { + nv20->dirty &= ~NV20_NEW_RAST; + nv20_state_emit_rast(nv20); } - if (nv10->dirty & NV10_NEW_DSA) { - nv10->dirty &= ~NV10_NEW_DSA; - nv10_state_emit_dsa(nv10); + if (nv20->dirty & NV20_NEW_DSA) { + nv20->dirty &= ~NV20_NEW_DSA; + nv20_state_emit_dsa(nv20); } - if (nv10->dirty & NV10_NEW_VIEWPORT) { - nv10->dirty &= ~NV10_NEW_VIEWPORT; - nv10_state_emit_viewport(nv10); + if (nv20->dirty & NV20_NEW_VIEWPORT) { + nv20->dirty &= ~NV20_NEW_VIEWPORT; + nv20_state_emit_viewport(nv20); } - if (nv10->dirty & NV10_NEW_SCISSOR) { - nv10->dirty &= ~NV10_NEW_SCISSOR; - nv10_state_emit_scissor(nv10); + if (nv20->dirty & NV20_NEW_SCISSOR) { + nv20->dirty &= ~NV20_NEW_SCISSOR; + nv20_state_emit_scissor(nv20); } - if (nv10->dirty & NV10_NEW_FRAMEBUFFER) { - nv10->dirty &= ~NV10_NEW_FRAMEBUFFER; - nv10_state_emit_framebuffer(nv10); + if (nv20->dirty & NV20_NEW_FRAMEBUFFER) { + nv20->dirty &= ~NV20_NEW_FRAMEBUFFER; + nv20_state_emit_framebuffer(nv20); } /* Emit relocs for every referenced buffer. * This is to ensure the bufmgr has an accurate idea of how * the buffer is used. This isn't very efficient, but we don't * seem to take a significant performance hit. Will be improved - * at some point. Vertex arrays are emitted by nv10_vbo.c + * at some point. Vertex arrays are emitted by nv20_vbo.c */ /* Render target */ // XXX figre out who's who for NV10TCL_DMA_* and fill accordingly -// BEGIN_RING(celsius, NV10TCL_DMA_COLOR0, 1); -// OUT_RELOCo(nv10->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(celsius, NV10TCL_COLOR_OFFSET, 1); - OUT_RELOCl(nv10->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); +// BEGIN_RING(kelvin, NV10TCL_DMA_COLOR0, 1); +// OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + BEGIN_RING(kelvin, NV10TCL_COLOR_OFFSET, 1); + OUT_RELOCl(nv20->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - if (nv10->zeta) { + if (nv20->zeta) { // XXX -// BEGIN_RING(celsius, NV10TCL_DMA_ZETA, 1); -// OUT_RELOCo(nv10->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(celsius, NV10TCL_ZETA_OFFSET, 1); - OUT_RELOCl(nv10->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); +// BEGIN_RING(kelvin, NV10TCL_DMA_ZETA, 1); +// OUT_RELOCo(nv20->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + BEGIN_RING(kelvin, NV10TCL_ZETA_OFFSET, 1); + OUT_RELOCl(nv20->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); /* XXX for when we allocate LMA on nv17 */ -/* BEGIN_RING(celsius, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1); - OUT_RELOCl(nv10->zeta + lma_offset);*/ +/* BEGIN_RING(kelvin, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1); + OUT_RELOCl(nv20->zeta + lma_offset);*/ } /* Vertex buffer */ - BEGIN_RING(celsius, NV10TCL_DMA_VTXBUF0, 1); - OUT_RELOCo(nv10->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(celsius, NV10TCL_COLOR_OFFSET, 1); - OUT_RELOCl(nv10->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + BEGIN_RING(kelvin, NV10TCL_DMA_VTXBUF0, 1); + OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + BEGIN_RING(kelvin, NV10TCL_COLOR_OFFSET, 1); + OUT_RELOCl(nv20->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); /* Texture images */ for (i = 0; i < 2; i++) { - if (!(nv10->fp_samplers & (1 << i))) + if (!(nv20->fp_samplers & (1 << i))) continue; - BEGIN_RING(celsius, NV10TCL_TX_OFFSET(i), 1); - OUT_RELOCl(nv10->tex[i].buffer, 0, NOUVEAU_BO_VRAM | + BEGIN_RING(kelvin, NV10TCL_TX_OFFSET(i), 1); + OUT_RELOCl(nv20->tex[i].buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); - BEGIN_RING(celsius, NV10TCL_TX_FORMAT(i), 1); - OUT_RELOCd(nv10->tex[i].buffer, nv10->tex[i].format, + BEGIN_RING(kelvin, NV10TCL_TX_FORMAT(i), 1); + OUT_RELOCd(nv20->tex[i].buffer, nv20->tex[i].format, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_OR, NV10TCL_TX_FORMAT_DMA0, NV10TCL_TX_FORMAT_DMA1); diff --git a/src/gallium/drivers/nv20/nv20_surface.c b/src/gallium/drivers/nv20/nv20_surface.c index 875e4c5858..41b6d6ad35 100644 --- a/src/gallium/drivers/nv20/nv20_surface.c +++ b/src/gallium/drivers/nv20/nv20_surface.c @@ -26,39 +26,39 @@ * **************************************************************************/ -#include "nv10_context.h" +#include "nv20_context.h" #include "pipe/p_defines.h" #include "pipe/p_winsys.h" #include "pipe/p_inlines.h" #include "util/u_tile.h" static void -nv10_surface_copy(struct pipe_context *pipe, unsigned do_flip, +nv20_surface_copy(struct pipe_context *pipe, unsigned do_flip, struct pipe_surface *dest, unsigned destx, unsigned desty, struct pipe_surface *src, unsigned srcx, unsigned srcy, unsigned width, unsigned height) { - struct nv10_context *nv10 = nv10_context(pipe); - struct nouveau_winsys *nvws = nv10->nvws; + struct nv20_context *nv20 = nv20_context(pipe); + struct nouveau_winsys *nvws = nv20->nvws; nvws->surface_copy(nvws, dest, destx, desty, src, srcx, srcy, width, height); } static void -nv10_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest, +nv20_surface_fill(struct pipe_context *pipe, struct pipe_surface *dest, unsigned destx, unsigned desty, unsigned width, unsigned height, unsigned value) { - struct nv10_context *nv10 = nv10_context(pipe); - struct nouveau_winsys *nvws = nv10->nvws; + struct nv20_context *nv20 = nv20_context(pipe); + struct nouveau_winsys *nvws = nv20->nvws; nvws->surface_fill(nvws, dest, destx, desty, width, height, value); } void -nv10_init_surface_functions(struct nv10_context *nv10) +nv20_init_surface_functions(struct nv20_context *nv20) { - nv10->pipe.surface_copy = nv10_surface_copy; - nv10->pipe.surface_fill = nv10_surface_fill; + nv20->pipe.surface_copy = nv20_surface_copy; + nv20->pipe.surface_fill = nv20_surface_fill; } diff --git a/src/gallium/drivers/nv20/nv20_vbo.c b/src/gallium/drivers/nv20/nv20_vbo.c index d0e788ac03..4edc4efebd 100644 --- a/src/gallium/drivers/nv20/nv20_vbo.c +++ b/src/gallium/drivers/nv20/nv20_vbo.c @@ -2,31 +2,31 @@ #include "pipe/p_context.h" #include "pipe/p_state.h" -#include "nv10_context.h" -#include "nv10_state.h" +#include "nv20_context.h" +#include "nv20_state.h" #include "nouveau/nouveau_channel.h" #include "nouveau/nouveau_pushbuf.h" -boolean nv10_draw_elements( struct pipe_context *pipe, +boolean nv20_draw_elements( struct pipe_context *pipe, struct pipe_buffer *indexBuffer, unsigned indexSize, unsigned prim, unsigned start, unsigned count) { - struct nv10_context *nv10 = nv10_context( pipe ); - struct draw_context *draw = nv10->draw; + struct nv20_context *nv20 = nv20_context( pipe ); + struct draw_context *draw = nv20->draw; unsigned i; - nv10_emit_hw_state(nv10); + nv20_emit_hw_state(nv20); /* * Map vertex buffers */ for (i = 0; i < PIPE_MAX_ATTRIBS; i++) { - if (nv10->vtxbuf[i].buffer) { + if (nv20->vtxbuf[i].buffer) { void *buf = pipe->winsys->buffer_map(pipe->winsys, - nv10->vtxbuf[i].buffer, + nv20->vtxbuf[i].buffer, PIPE_BUFFER_USAGE_CPU_READ); draw_set_mapped_vertex_buffer(draw, i, buf); } @@ -44,18 +44,18 @@ boolean nv10_draw_elements( struct pipe_context *pipe, } draw_set_mapped_constant_buffer(draw, - nv10->constbuf[PIPE_SHADER_VERTEX], - nv10->constbuf_nr[PIPE_SHADER_VERTEX]); + nv20->constbuf[PIPE_SHADER_VERTEX], + nv20->constbuf_nr[PIPE_SHADER_VERTEX]); /* draw! */ - draw_arrays(nv10->draw, prim, start, count); + draw_arrays(nv20->draw, prim, start, count); /* * unmap vertex/index buffers */ for (i = 0; i < PIPE_MAX_ATTRIBS; i++) { - if (nv10->vtxbuf[i].buffer) { - pipe->winsys->buffer_unmap(pipe->winsys, nv10->vtxbuf[i].buffer); + if (nv20->vtxbuf[i].buffer) { + pipe->winsys->buffer_unmap(pipe->winsys, nv20->vtxbuf[i].buffer); draw_set_mapped_vertex_buffer(draw, i, NULL); } } @@ -67,10 +67,10 @@ boolean nv10_draw_elements( struct pipe_context *pipe, return TRUE; } -boolean nv10_draw_arrays( struct pipe_context *pipe, +boolean nv20_draw_arrays( struct pipe_context *pipe, unsigned prim, unsigned start, unsigned count) { - return nv10_draw_elements(pipe, NULL, 0, prim, start, count); + return nv20_draw_elements(pipe, NULL, 0, prim, start, count); } diff --git a/src/gallium/drivers/nv20/nv20_vertprog.c b/src/gallium/drivers/nv20/nv20_vertprog.c index 72824559e8..a885fcd7a5 100644 --- a/src/gallium/drivers/nv20/nv20_vertprog.c +++ b/src/gallium/drivers/nv20/nv20_vertprog.c @@ -6,8 +6,8 @@ #include "tgsi/tgsi_parse.h" #include "tgsi/tgsi_dump.h" -#include "nv30_context.h" -#include "nv30_state.h" +#include "nv20_context.h" +#include "nv20_state.h" /* TODO (at least...): * 1. Indexed consts + ARL @@ -32,47 +32,47 @@ #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W) #define DEF_SCALE 0 #define DEF_CTEST 0 -#include "nv30_shader.h" +#include "nv20_shader.h" -#define swz(s,x,y,z,w) nv30_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w) -#define neg(s) nv30_sr_neg((s)) -#define abs(s) nv30_sr_abs((s)) +#define swz(s,x,y,z,w) nv20_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w) +#define neg(s) nv20_sr_neg((s)) +#define abs(s) nv20_sr_abs((s)) -struct nv30_vpc { - struct nv30_vertex_program *vp; +struct nv20_vpc { + struct nv20_vertex_program *vp; - struct nv30_vertex_program_exec *vpi; + struct nv20_vertex_program_exec *vpi; unsigned output_map[PIPE_MAX_SHADER_OUTPUTS]; int high_temp; int temp_temp_count; - struct nv30_sreg *imm; + struct nv20_sreg *imm; unsigned nr_imm; }; -static struct nv30_sreg -temp(struct nv30_vpc *vpc) +static struct nv20_sreg +temp(struct nv20_vpc *vpc) { int idx; idx = vpc->temp_temp_count++; idx += vpc->high_temp + 1; - return nv30_sr(NV30SR_TEMP, idx); + return nv20_sr(NV30SR_TEMP, idx); } -static struct nv30_sreg -constant(struct nv30_vpc *vpc, int pipe, float x, float y, float z, float w) +static struct nv20_sreg +constant(struct nv20_vpc *vpc, int pipe, float x, float y, float z, float w) { - struct nv30_vertex_program *vp = vpc->vp; - struct nv30_vertex_program_data *vpd; + struct nv20_vertex_program *vp = vpc->vp; + struct nv20_vertex_program_data *vpd; int idx; if (pipe >= 0) { for (idx = 0; idx < vp->nr_consts; idx++) { if (vp->consts[idx].index == pipe) - return nv30_sr(NV30SR_CONST, idx); + return nv20_sr(NV30SR_CONST, idx); } } @@ -85,16 +85,16 @@ constant(struct nv30_vpc *vpc, int pipe, float x, float y, float z, float w) vpd->value[1] = y; vpd->value[2] = z; vpd->value[3] = w; - return nv30_sr(NV30SR_CONST, idx); + return nv20_sr(NV30SR_CONST, idx); } #define arith(cc,s,o,d,m,s0,s1,s2) \ - nv30_vp_arith((cc), (s), NV30_VP_INST_##o, (d), (m), (s0), (s1), (s2)) + nv20_vp_arith((cc), (s), NV30_VP_INST_##o, (d), (m), (s0), (s1), (s2)) static void -emit_src(struct nv30_vpc *vpc, uint32_t *hw, int pos, struct nv30_sreg src) +emit_src(struct nv20_vpc *vpc, uint32_t *hw, int pos, struct nv20_sreg src) { - struct nv30_vertex_program *vp = vpc->vp; + struct nv20_vertex_program *vp = vpc->vp; uint32_t sr = 0; switch (src.type) { @@ -163,9 +163,9 @@ emit_src(struct nv30_vpc *vpc, uint32_t *hw, int pos, struct nv30_sreg src) } static void -emit_dst(struct nv30_vpc *vpc, uint32_t *hw, int slot, struct nv30_sreg dst) +emit_dst(struct nv20_vpc *vpc, uint32_t *hw, int slot, struct nv20_sreg dst) { - struct nv30_vertex_program *vp = vpc->vp; + struct nv20_vertex_program *vp = vpc->vp; switch (dst.type) { case NV30SR_TEMP: @@ -205,12 +205,12 @@ emit_dst(struct nv30_vpc *vpc, uint32_t *hw, int slot, struct nv30_sreg dst) } static void -nv30_vp_arith(struct nv30_vpc *vpc, int slot, int op, - struct nv30_sreg dst, int mask, - struct nv30_sreg s0, struct nv30_sreg s1, - struct nv30_sreg s2) +nv20_vp_arith(struct nv20_vpc *vpc, int slot, int op, + struct nv20_sreg dst, int mask, + struct nv20_sreg s0, struct nv20_sreg s1, + struct nv20_sreg s2) { - struct nv30_vertex_program *vp = vpc->vp; + struct nv20_vertex_program *vp = vpc->vp; uint32_t *hw; vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi)); @@ -248,13 +248,13 @@ nv30_vp_arith(struct nv30_vpc *vpc, int slot, int op, emit_src(vpc, hw, 2, s2); } -static INLINE struct nv30_sreg -tgsi_src(struct nv30_vpc *vpc, const struct tgsi_full_src_register *fsrc) { - struct nv30_sreg src; +static INLINE struct nv20_sreg +tgsi_src(struct nv20_vpc *vpc, const struct tgsi_full_src_register *fsrc) { + struct nv20_sreg src; switch (fsrc->SrcRegister.File) { case TGSI_FILE_INPUT: - src = nv30_sr(NV30SR_INPUT, fsrc->SrcRegister.Index); + src = nv20_sr(NV30SR_INPUT, fsrc->SrcRegister.Index); break; case TGSI_FILE_CONSTANT: src = constant(vpc, fsrc->SrcRegister.Index, 0, 0, 0, 0); @@ -265,7 +265,7 @@ tgsi_src(struct nv30_vpc *vpc, const struct tgsi_full_src_register *fsrc) { case TGSI_FILE_TEMPORARY: if (vpc->high_temp < fsrc->SrcRegister.Index) vpc->high_temp = fsrc->SrcRegister.Index; - src = nv30_sr(NV30SR_TEMP, fsrc->SrcRegister.Index); + src = nv20_sr(NV30SR_TEMP, fsrc->SrcRegister.Index); break; default: NOUVEAU_ERR("bad src file\n"); @@ -281,18 +281,18 @@ tgsi_src(struct nv30_vpc *vpc, const struct tgsi_full_src_register *fsrc) { return src; } -static INLINE struct nv30_sreg -tgsi_dst(struct nv30_vpc *vpc, const struct tgsi_full_dst_register *fdst) { - struct nv30_sreg dst; +static INLINE struct nv20_sreg +tgsi_dst(struct nv20_vpc *vpc, const struct tgsi_full_dst_register *fdst) { + struct nv20_sreg dst; switch (fdst->DstRegister.File) { case TGSI_FILE_OUTPUT: - dst = nv30_sr(NV30SR_OUTPUT, + dst = nv20_sr(NV30SR_OUTPUT, vpc->output_map[fdst->DstRegister.Index]); break; case TGSI_FILE_TEMPORARY: - dst = nv30_sr(NV30SR_TEMP, fdst->DstRegister.Index); + dst = nv20_sr(NV30SR_TEMP, fdst->DstRegister.Index); if (vpc->high_temp < dst.index) vpc->high_temp = dst.index; break; @@ -317,11 +317,11 @@ tgsi_mask(uint tgsi) } static boolean -nv30_vertprog_parse_instruction(struct nv30_vpc *vpc, +nv20_vertprog_parse_instruction(struct nv20_vpc *vpc, const struct tgsi_full_instruction *finst) { - struct nv30_sreg src[3], dst, tmp; - struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0); + struct nv20_sreg src[3], dst, tmp; + struct nv20_sreg none = nv20_sr(NV30SR_NONE, 0); int mask; int ai = -1, ci = -1; int i; @@ -484,7 +484,7 @@ nv30_vertprog_parse_instruction(struct nv30_vpc *vpc, } static boolean -nv30_vertprog_parse_decl_output(struct nv30_vpc *vpc, +nv20_vertprog_parse_decl_output(struct nv20_vpc *vpc, const struct tgsi_full_declaration *fdec) { int hw; @@ -539,7 +539,7 @@ nv30_vertprog_parse_decl_output(struct nv30_vpc *vpc, } static boolean -nv30_vertprog_prepare(struct nv30_vpc *vpc) +nv20_vertprog_prepare(struct nv20_vpc *vpc) { struct tgsi_parse_context p; int nr_imm = 0; @@ -560,7 +560,7 @@ nv30_vertprog_prepare(struct nv30_vpc *vpc) tgsi_parse_free(&p); if (nr_imm) { - vpc->imm = CALLOC(nr_imm, sizeof(struct nv30_sreg)); + vpc->imm = CALLOC(nr_imm, sizeof(struct nv20_sreg)); assert(vpc->imm); } @@ -568,21 +568,21 @@ nv30_vertprog_prepare(struct nv30_vpc *vpc) } static void -nv30_vertprog_translate(struct nv30_context *nv30, - struct nv30_vertex_program *vp) +nv20_vertprog_translate(struct nv20_context *nv20, + struct nv20_vertex_program *vp) { struct tgsi_parse_context parse; - struct nv30_vpc *vpc = NULL; + struct nv20_vpc *vpc = NULL; tgsi_dump(vp->pipe.tokens,0); - vpc = CALLOC(1, sizeof(struct nv30_vpc)); + vpc = CALLOC(1, sizeof(struct nv20_vpc)); if (!vpc) return; vpc->vp = vp; vpc->high_temp = -1; - if (!nv30_vertprog_prepare(vpc)) { + if (!nv20_vertprog_prepare(vpc)) { FREE(vpc); return; } @@ -599,7 +599,7 @@ nv30_vertprog_translate(struct nv30_context *nv30, fdec = &parse.FullToken.FullDeclaration; switch (fdec->Declaration.File) { case TGSI_FILE_OUTPUT: - if (!nv30_vertprog_parse_decl_output(vpc, fdec)) + if (!nv20_vertprog_parse_decl_output(vpc, fdec)) goto out_err; break; default: @@ -626,7 +626,7 @@ nv30_vertprog_translate(struct nv30_context *nv30, { const struct tgsi_full_instruction *finst; finst = &parse.FullToken.FullInstruction; - if (!nv30_vertprog_parse_instruction(vpc, finst)) + if (!nv20_vertprog_parse_instruction(vpc, finst)) goto out_err; } break; @@ -643,35 +643,35 @@ out_err: } static boolean -nv30_vertprog_validate(struct nv30_context *nv30) +nv20_vertprog_validate(struct nv20_context *nv20) { - struct nouveau_winsys *nvws = nv30->nvws; - struct pipe_winsys *ws = nv30->pipe.winsys; - struct nouveau_grobj *rankine = nv30->screen->rankine; - struct nv30_vertex_program *vp; + struct nouveau_winsys *nvws = nv20->nvws; + struct pipe_winsys *ws = nv20->pipe.winsys; + struct nouveau_grobj *rankine = nv20->screen->rankine; + struct nv20_vertex_program *vp; struct pipe_buffer *constbuf; boolean upload_code = FALSE, upload_data = FALSE; int i; - vp = nv30->vertprog; - constbuf = nv30->constbuf[PIPE_SHADER_VERTEX]; + vp = nv20->vertprog; + constbuf = nv20->constbuf[PIPE_SHADER_VERTEX]; /* Translate TGSI shader into hw bytecode */ if (!vp->translated) { - nv30_vertprog_translate(nv30, vp); + nv20_vertprog_translate(nv20, vp); if (!vp->translated) return FALSE; } /* Allocate hw vtxprog exec slots */ if (!vp->exec) { - struct nouveau_resource *heap = nv30->screen->vp_exec_heap; + struct nouveau_resource *heap = nv20->screen->vp_exec_heap; struct nouveau_stateobj *so; uint vplen = vp->nr_insns; if (nvws->res_alloc(heap, vplen, vp, &vp->exec)) { while (heap->next && heap->size < vplen) { - struct nv30_vertex_program *evict; + struct nv20_vertex_program *evict; evict = heap->next->priv; nvws->res_free(&evict->exec); @@ -691,11 +691,11 @@ nv30_vertprog_validate(struct nv30_context *nv30) /* Allocate hw vtxprog const slots */ if (vp->nr_consts && !vp->data) { - struct nouveau_resource *heap = nv30->screen->vp_data_heap; + struct nouveau_resource *heap = nv20->screen->vp_data_heap; if (nvws->res_alloc(heap, vp->nr_consts, vp, &vp->data)) { while (heap->next && heap->size < vp->nr_consts) { - struct nv30_vertex_program *evict; + struct nv20_vertex_program *evict; evict = heap->next->priv; nvws->res_free(&evict->data); @@ -718,7 +718,7 @@ nv30_vertprog_validate(struct nv30_context *nv30) */ if (vp->exec_start != vp->exec->start) { for (i = 0; i < vp->nr_insns; i++) { - struct nv30_vertex_program_exec *vpi = &vp->insns[i]; + struct nv20_vertex_program_exec *vpi = &vp->insns[i]; if (vpi->has_branch_offset) { assert(0); @@ -730,7 +730,7 @@ nv30_vertprog_validate(struct nv30_context *nv30) if (vp->nr_consts && vp->data_start != vp->data->start) { for (i = 0; i < vp->nr_insns; i++) { - struct nv30_vertex_program_exec *vpi = &vp->insns[i]; + struct nv20_vertex_program_exec *vpi = &vp->insns[i]; if (vpi->const_index >= 0) { vpi->data[1] &= ~NV30_VP_INST_CONST_SRC_MASK; @@ -754,7 +754,7 @@ nv30_vertprog_validate(struct nv30_context *nv30) } for (i = 0; i < vp->nr_consts; i++) { - struct nv30_vertex_program_data *vpd = &vp->consts[i]; + struct nv20_vertex_program_data *vpd = &vp->consts[i]; if (vpd->index >= 0) { if (!upload_data && @@ -792,8 +792,8 @@ nv30_vertprog_validate(struct nv30_context *nv30) } } - if (vp->so != nv30->state.hw[NV30_STATE_VERTPROG]) { - so_ref(vp->so, &nv30->state.hw[NV30_STATE_VERTPROG]); + if (vp->so != nv20->state.hw[NV30_STATE_VERTPROG]) { + so_ref(vp->so, &nv20->state.hw[NV30_STATE_VERTPROG]); return TRUE; } @@ -801,9 +801,9 @@ nv30_vertprog_validate(struct nv30_context *nv30) } void -nv30_vertprog_destroy(struct nv30_context *nv30, struct nv30_vertex_program *vp) +nv20_vertprog_destroy(struct nv20_context *nv20, struct nv20_vertex_program *vp) { - struct nouveau_winsys *nvws = nv30->screen->nvws; + struct nouveau_winsys *nvws = nv20->screen->nvws; vp->translated = FALSE; @@ -829,8 +829,8 @@ nv30_vertprog_destroy(struct nv30_context *nv30, struct nv30_vertex_program *vp) so_ref(NULL, &vp->so); } -struct nv30_state_entry nv30_state_vertprog = { - .validate = nv30_vertprog_validate, +struct nv20_state_entry nv20_state_vertprog = { + .validate = nv20_vertprog_validate, .dirty = { .pipe = NV30_NEW_VERTPROG /*| NV30_NEW_UCP*/, .hw = NV30_STATE_VERTPROG, -- cgit v1.2.3 From bcd5dda4358a5e47551278477bd00d2c63415c44 Mon Sep 17 00:00:00 2001 From: Pekka Paalanen Date: Sun, 7 Dec 2008 01:05:54 +0200 Subject: nouveau: make nv20 use NV{20,25}TCL objects Up till now, nv20 driver has been using NV10TCL, and being really an nv10 driver. That has changed. Signed-off-by: Pekka Paalanen --- src/gallium/drivers/nv20/nv20_context.c | 393 +++++++++++++++++++---------- src/gallium/drivers/nv20/nv20_fragtex.c | 10 +- src/gallium/drivers/nv20/nv20_prim_vbuf.c | 31 +-- src/gallium/drivers/nv20/nv20_screen.c | 22 +- src/gallium/drivers/nv20/nv20_state.c | 75 +++--- src/gallium/drivers/nv20/nv20_state_emit.c | 88 +++---- 6 files changed, 367 insertions(+), 252 deletions(-) (limited to 'src/gallium/drivers/nv20/nv20_state.c') diff --git a/src/gallium/drivers/nv20/nv20_context.c b/src/gallium/drivers/nv20/nv20_context.c index ba2f0bf1e8..9a17f4af57 100644 --- a/src/gallium/drivers/nv20/nv20_context.c +++ b/src/gallium/drivers/nv20/nv20_context.c @@ -33,217 +33,340 @@ static void nv20_init_hwctx(struct nv20_context *nv20) struct nouveau_winsys *nvws = screen->nvws; int i; float projectionmatrix[16]; + const boolean is_nv25tcl = (nv20->screen->kelvin->grclass == NV25TCL); - BEGIN_RING(kelvin, NV10TCL_DMA_NOTIFY, 1); + BEGIN_RING(kelvin, NV20TCL_DMA_NOTIFY, 1); OUT_RING (screen->sync->handle); - BEGIN_RING(kelvin, NV10TCL_DMA_IN_MEMORY0, 2); - OUT_RING (nvws->channel->vram->handle); - OUT_RING (nvws->channel->gart->handle); - BEGIN_RING(kelvin, NV10TCL_DMA_IN_MEMORY2, 2); + BEGIN_RING(kelvin, NV20TCL_DMA_TEXTURE0, 2); OUT_RING (nvws->channel->vram->handle); + OUT_RING (nvws->channel->gart->handle); /* TEXTURE1 */ + BEGIN_RING(kelvin, NV20TCL_DMA_COLOR, 2); OUT_RING (nvws->channel->vram->handle); + OUT_RING (nvws->channel->vram->handle); /* ZETA */ - BEGIN_RING(kelvin, NV10TCL_NOP, 1); - OUT_RING (0); + BEGIN_RING(kelvin, NV20TCL_DMA_QUERY, 1); + OUT_RING (0); /* renouveau: beef0351, unique */ - BEGIN_RING(kelvin, NV10TCL_RT_HORIZ, 2); + BEGIN_RING(kelvin, NV20TCL_RT_HORIZ, 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 1); - OUT_RING ((0x7ff<<16)|0x800); - BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_VERT(0), 1); - OUT_RING ((0x7ff<<16)|0x800); + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 1); + OUT_RING ((0xfff << 16) | 0x0); + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_VERT(0), 1); + OUT_RING ((0xfff << 16) | 0x0); - for (i=1;i<8;i++) { - BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_HORIZ(i), 1); + for (i = 1; i < NV20TCL_VIEWPORT_CLIP_HORIZ__SIZE; i++) { + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(i), 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_VERT(i), 1); + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_VERT(i), 1); OUT_RING (0); } + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_MODE, 1); + OUT_RING (0); + + BEGIN_RING(kelvin, 0x17e0, 3); + OUT_RINGf (0.0); + OUT_RINGf (0.0); + OUT_RINGf (1.0); + + if (is_nv25tcl) { + BEGIN_RING(kelvin, NV20TCL_TX_RCOMP, 1); + OUT_RING (NV20TCL_TX_RCOMP_LEQUAL | 0xdb0); + } else { + BEGIN_RING(kelvin, 0x1e68, 1); + OUT_RING (0x4b800000); /* 16777216.000000 */ + BEGIN_RING(kelvin, NV20TCL_TX_RCOMP, 1); + OUT_RING (NV20TCL_TX_RCOMP_LEQUAL); + } + BEGIN_RING(kelvin, 0x290, 1); - OUT_RING ((0x10<<16)|1); - BEGIN_RING(kelvin, 0x3f4, 1); + OUT_RING ((0x10 << 16) | 1); + BEGIN_RING(kelvin, 0x9fc, 1); OUT_RING (0); + BEGIN_RING(kelvin, 0x1d80, 1); + OUT_RING (1); + BEGIN_RING(kelvin, 0x9f8, 1); + OUT_RING (4); + BEGIN_RING(kelvin, 0x17ec, 3); + OUT_RINGf (0.0); + OUT_RINGf (1.0); + OUT_RINGf (0.0); + + if (is_nv25tcl) { + BEGIN_RING(kelvin, 0x1d88, 1); + OUT_RING (3); - BEGIN_RING(kelvin, NV10TCL_NOP, 1); + BEGIN_RING(kelvin, NV25TCL_DMA_IN_MEMORY9, 1); + OUT_RING (nvws->channel->vram->handle); + BEGIN_RING(kelvin, NV25TCL_DMA_IN_MEMORY8, 1); + OUT_RING (nvws->channel->vram->handle); + } + BEGIN_RING(kelvin, NV20TCL_DMA_FENCE, 1); + OUT_RING (0); /* renouveau: beef1e10 */ + + BEGIN_RING(kelvin, 0x1e98, 1); OUT_RING (0); +#if 0 + if (is_nv25tcl) { + BEGIN_RING(NvSub3D, NV25TCL_DMA_IN_MEMORY4, 2); + OUT_RING (NvDmaTT); /* renouveau: beef0202 */ + OUT_RING (NvDmaFB); /* renouveau: beef0201 */ - if (nv20->screen->kelvin->grclass != NV10TCL) { - /* For nv11, nv17 */ - BEGIN_RING(kelvin, 0x120, 3); - OUT_RING (0); - OUT_RING (1); - OUT_RING (2); + BEGIN_RING(NvSub3D, NV20TCL_DMA_TEXTURE1, 1); + OUT_RING (NvDmaTT); /* renouveau: beef0202 */ + } +#endif + BEGIN_RING(kelvin, NV20TCL_NOTIFY, 1); + OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_NOP, 1); + BEGIN_RING(kelvin, 0x120, 3); + OUT_RING (0); + OUT_RING (1); + OUT_RING (2); + +/* error: ILLEGAL_MTHD, PROTECTION_FAULT + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_TRANSLATE_X, 4); + OUT_RINGf (0.0); + OUT_RINGf (512.0); + OUT_RINGf (0.0); + OUT_RINGf (0.0); +*/ + + if (is_nv25tcl) { + BEGIN_RING(kelvin, 0x022c, 2); + OUT_RING (0x280); + OUT_RING (0x07d28000); + } + +/* * illegal method, protection fault + BEGIN_RING(NvSub3D, 0x1c2c, 1); + OUT_RING (0); */ + + if (is_nv25tcl) { + BEGIN_RING(kelvin, 0x1da4, 1); OUT_RING (0); } - BEGIN_RING(kelvin, NV10TCL_NOP, 1); - OUT_RING (0); +/* * crashes with illegal method, protection fault + BEGIN_RING(NvSub3D, 0x1c18, 1); + OUT_RING (0x200); */ - /* Set state */ - BEGIN_RING(kelvin, NV10TCL_FOG_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_RT_HORIZ, 2); + OUT_RING ((0 << 16) | 0); + OUT_RING ((0 << 16) | 0); + + /* *** Set state *** */ + + BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_FUNC, 2); + OUT_RING (NV20TCL_ALPHA_FUNC_FUNC_ALWAYS); + OUT_RING (0); /* NV20TCL_ALPHA_FUNC_REF */ + + for (i = 0; i < NV20TCL_TX_ENABLE__SIZE; ++i) { + BEGIN_RING(kelvin, NV20TCL_TX_ENABLE(i), 1); + OUT_RING (0); + } + BEGIN_RING(kelvin, NV20TCL_TX_SHADER_OP, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_FUNC, 2); - OUT_RING (0x207); + BEGIN_RING(kelvin, NV20TCL_TX_SHADER_CULL_MODE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_TX_ENABLE(0), 2); + BEGIN_RING(kelvin, NV20TCL_RC_IN_ALPHA(0), 4); + OUT_RING (0x30d410d0); OUT_RING (0); OUT_RING (0); - - BEGIN_RING(kelvin, NV10TCL_RC_IN_ALPHA(0), 12); - OUT_RING (0x30141010); OUT_RING (0); - OUT_RING (0x20040000); + BEGIN_RING(kelvin, NV20TCL_RC_OUT_RGB(0), 4); + OUT_RING (0x00000c00); OUT_RING (0); OUT_RING (0); OUT_RING (0); + BEGIN_RING(kelvin, NV20TCL_RC_ENABLE, 1); + OUT_RING (0x00011101); + BEGIN_RING(kelvin, NV20TCL_RC_FINAL0, 2); + OUT_RING (0x130e0300); + OUT_RING (0x0c091c80); + BEGIN_RING(kelvin, NV20TCL_RC_OUT_ALPHA(0), 4); OUT_RING (0x00000c00); OUT_RING (0); - OUT_RING (0x00000c00); - OUT_RING (0x18000000); - OUT_RING (0x300e0300); - OUT_RING (0x0c091c80); - - BEGIN_RING(kelvin, NV10TCL_BLEND_FUNC_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_DITHER_ENABLE, 2); - OUT_RING (1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_LINE_SMOOTH_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_RC_IN_RGB(0), 4); + OUT_RING (0x20c400c0); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_VERTEX_WEIGHT_ENABLE, 2); OUT_RING (0); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_BLEND_FUNC_SRC, 4); - OUT_RING (1); + BEGIN_RING(kelvin, NV20TCL_RC_COLOR0, 2); OUT_RING (0); OUT_RING (0); - OUT_RING (0x8006); - BEGIN_RING(kelvin, NV10TCL_STENCIL_MASK, 8); - OUT_RING (0xff); - OUT_RING (0x207); + BEGIN_RING(kelvin, NV20TCL_RC_CONSTANT_COLOR0(0), 4); + OUT_RING (0x035125a0); OUT_RING (0); - OUT_RING (0xff); - OUT_RING (0x1e00); - OUT_RING (0x1e00); - OUT_RING (0x1e00); - OUT_RING (0x1d01); - BEGIN_RING(kelvin, NV10TCL_NORMALIZE_ENABLE, 1); + OUT_RING (0x40002000); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_FOG_ENABLE, 2); + BEGIN_RING(kelvin, NV20TCL_MULTISAMPLE_CONTROL, 1); + OUT_RING (0xffff0000); + + BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1); OUT_RING (0); + BEGIN_RING(kelvin, NV20TCL_DITHER_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_LIGHT_MODEL, 1); + BEGIN_RING(kelvin, NV20TCL_STENCIL_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_COLOR_CONTROL, 1); + BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_SRC, 4); + OUT_RING (NV20TCL_BLEND_FUNC_SRC_ONE); + OUT_RING (NV20TCL_BLEND_FUNC_DST_ZERO); + OUT_RING (0); /* NV20TCL_BLEND_COLOR */ + OUT_RING (NV20TCL_BLEND_EQUATION_FUNC_ADD); + BEGIN_RING(kelvin, NV20TCL_STENCIL_MASK, 7); + OUT_RING (0xff); + OUT_RING (NV20TCL_STENCIL_FUNC_FUNC_ALWAYS); + OUT_RING (0); /* NV20TCL_STENCIL_FUNC_REF */ + OUT_RING (0xff); /* NV20TCL_STENCIL_FUNC_MASK */ + OUT_RING (NV20TCL_STENCIL_OP_FAIL_KEEP); + OUT_RING (NV20TCL_STENCIL_OP_ZFAIL_KEEP); + OUT_RING (NV20TCL_STENCIL_OP_ZPASS_KEEP); + + BEGIN_RING(kelvin, NV20TCL_COLOR_LOGIC_OP_ENABLE, 2); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_ENABLED_LIGHTS, 1); + OUT_RING (NV20TCL_COLOR_LOGIC_OP_OP_COPY); + BEGIN_RING(kelvin, 0x17cc, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_POLYGON_OFFSET_POINT_ENABLE, 3); + if (is_nv25tcl) { + BEGIN_RING(kelvin, 0x1d84, 1); + OUT_RING (1); + } + BEGIN_RING(kelvin, NV20TCL_LIGHTING_ENABLE, 1); OUT_RING (0); + BEGIN_RING(kelvin, NV20TCL_LIGHT_CONTROL, 1); + OUT_RING (0x00020000); + BEGIN_RING(kelvin, NV20TCL_SEPARATE_SPECULAR_ENABLE, 1); OUT_RING (0); + BEGIN_RING(kelvin, NV20TCL_LIGHT_MODEL_TWO_SIDE_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_DEPTH_FUNC, 1); - OUT_RING (0x201); - BEGIN_RING(kelvin, NV10TCL_DEPTH_WRITE_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_ENABLED_LIGHTS, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_DEPTH_TEST_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_NORMALIZE_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_POLYGON_OFFSET_FACTOR, 2); + BEGIN_RING(kelvin, NV20TCL_POLYGON_STIPPLE_PATTERN(0), + NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE); + for (i = 0; i < NV20TCL_POLYGON_STIPPLE_PATTERN__SIZE; ++i) { + OUT_RING(0xffffffff); + } + + BEGIN_RING(kelvin, NV20TCL_POLYGON_OFFSET_POINT_ENABLE, 3); OUT_RING (0); + OUT_RING (0); /* NV20TCL.POLYGON_OFFSET_LINE_ENABLE */ + OUT_RING (0); /* NV20TCL.POLYGON_OFFSET_FILL_ENABLE */ + BEGIN_RING(kelvin, NV20TCL_DEPTH_FUNC, 1); + OUT_RING (NV20TCL_DEPTH_FUNC_LESS); + BEGIN_RING(kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1); + OUT_RING (1); + BEGIN_RING(kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_POINT_SIZE, 1); + BEGIN_RING(kelvin, NV20TCL_POLYGON_OFFSET_FACTOR, 2); + OUT_RINGf (0.0); + OUT_RINGf (0.0); /* NV20TCL.POLYGON_OFFSET_UNITS */ + BEGIN_RING(kelvin, NV20TCL_DEPTH_UNK17D8, 1); + OUT_RING (1); + if (!is_nv25tcl) { + BEGIN_RING(kelvin, 0x1d84, 1); + OUT_RING (3); + } + BEGIN_RING(kelvin, NV20TCL_POINT_SIZE, 1); + if (!is_nv25tcl) { + OUT_RING (8); + } else { + OUT_RINGf (1.0); + } + if (!is_nv25tcl) { + BEGIN_RING(kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 2); + OUT_RING (0); + OUT_RING (0); /* NV20TCL.POINT_SMOOTH_ENABLE */ + } else { + BEGIN_RING(kelvin, NV20TCL_POINT_PARAMETERS_ENABLE, 1); + OUT_RING (0); + BEGIN_RING(kelvin, 0x0a1c, 1); + OUT_RING (0x800); + } + BEGIN_RING(kelvin, NV20TCL_LINE_WIDTH, 1); OUT_RING (8); - BEGIN_RING(kelvin, NV10TCL_POINT_PARAMETERS_ENABLE, 2); - OUT_RING (0); + BEGIN_RING(kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_LINE_WIDTH, 1); - OUT_RING (8); - BEGIN_RING(kelvin, NV10TCL_LINE_SMOOTH_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_POLYGON_MODE_FRONT, 2); + OUT_RING (NV20TCL_POLYGON_MODE_FRONT_FILL); + OUT_RING (NV20TCL_POLYGON_MODE_BACK_FILL); + BEGIN_RING(kelvin, NV20TCL_CULL_FACE, 2); + OUT_RING (NV20TCL_CULL_FACE_BACK); + OUT_RING (NV20TCL_FRONT_FACE_CCW); + BEGIN_RING(kelvin, NV20TCL_POLYGON_SMOOTH_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_POLYGON_MODE_FRONT, 2); - OUT_RING (0x1b02); - OUT_RING (0x1b02); - BEGIN_RING(kelvin, NV10TCL_CULL_FACE, 2); - OUT_RING (0x405); - OUT_RING (0x901); - BEGIN_RING(kelvin, NV10TCL_POLYGON_SMOOTH_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_CULL_FACE_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_CULL_FACE_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_SHADE_MODEL, 1); + OUT_RING (NV20TCL_SHADE_MODEL_SMOOTH); + BEGIN_RING(kelvin, NV20TCL_POLYGON_STIPPLE_ENABLE, 1); OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_TX_GEN_S(0), 8); - for (i=0;i<8;i++) { + BEGIN_RING(kelvin, NV20TCL_TX_GEN_S(0), 4 * NV20TCL_TX_GEN_S__SIZE); + for (i=0; i < 4 * NV20TCL_TX_GEN_S__SIZE; ++i) { + OUT_RING(0); + } + BEGIN_RING(kelvin, NV20TCL_FOG_EQUATION_CONSTANT, 3); + OUT_RINGf (1.5); + OUT_RINGf (-0.090168); /* NV20TCL.FOG_EQUATION_LINEAR */ + OUT_RINGf (0.0); /* NV20TCL.FOG_EQUATION_QUADRATIC */ + BEGIN_RING(kelvin, NV20TCL_FOG_MODE, 2); + OUT_RING (NV20TCL_FOG_MODE_EXP_2); + OUT_RING (NV20TCL_FOG_COORD_DIST_COORD_FOG); + BEGIN_RING(kelvin, NV20TCL_FOG_ENABLE, 2); + OUT_RING (0); + OUT_RING (0); /* NV20TCL.FOG_COLOR */ + BEGIN_RING(kelvin, NV20TCL_ENGINE, 1); + OUT_RING (NV20TCL_ENGINE_FIXED); + + for (i = 0; i < NV20TCL_TX_MATRIX_ENABLE__SIZE; ++i) { + BEGIN_RING(kelvin, NV20TCL_TX_MATRIX_ENABLE(i), 1); OUT_RING (0); } - BEGIN_RING(kelvin, NV10TCL_FOG_EQUATION_CONSTANT, 3); - OUT_RING (0x3fc00000); /* -1.50 */ - OUT_RING (0xbdb8aa0a); /* -0.09 */ - OUT_RING (0); /* 0.00 */ - BEGIN_RING(kelvin, NV10TCL_NOP, 1); - OUT_RING (0); + BEGIN_RING(kelvin, NV20TCL_VTX_ATTR_4F_X(1), 4 * 15); + OUT_RINGf(1.0); OUT_RINGf(0.0); OUT_RINGf(0.0); OUT_RINGf(1.0); + OUT_RINGf(0.0); OUT_RINGf(0.0); OUT_RINGf(1.0); OUT_RINGf(1.0); + OUT_RINGf(1.0); OUT_RINGf(1.0); OUT_RINGf(1.0); OUT_RINGf(1.0); + for (i = 4; i < 16; ++i) { + OUT_RINGf(0.0); OUT_RINGf(0.0); OUT_RINGf(0.0); OUT_RINGf(1.0); + } - BEGIN_RING(kelvin, NV10TCL_FOG_MODE, 2); - OUT_RING (0x802); - OUT_RING (2); - /* for some reason VIEW_MATRIX_ENABLE need to be 6 instead of 4 when - * using texturing, except when using the texture matrix - */ - BEGIN_RING(kelvin, NV10TCL_VIEW_MATRIX_ENABLE, 1); - OUT_RING (6); - BEGIN_RING(kelvin, NV10TCL_COLOR_MASK, 1); - OUT_RING (0x01010101); - - /* Set vertex component */ - BEGIN_RING(kelvin, NV10TCL_VERTEX_COL_4F_R, 4); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - OUT_RINGf (1.0); - BEGIN_RING(kelvin, NV10TCL_VERTEX_COL2_3F_R, 3); - OUT_RING (0); - OUT_RING (0); - OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_VERTEX_NOR_3F_X, 3); - OUT_RING (0); - OUT_RING (0); - OUT_RINGf (1.0); - BEGIN_RING(kelvin, NV10TCL_VERTEX_TX0_4F_S, 4); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (1.0); - BEGIN_RING(kelvin, NV10TCL_VERTEX_TX1_4F_S, 4); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (0.0); - OUT_RINGf (1.0); - BEGIN_RING(kelvin, NV10TCL_VERTEX_FOG_1F, 1); - OUT_RINGf (0.0); - BEGIN_RING(kelvin, NV10TCL_EDGEFLAG_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_EDGEFLAG_ENABLE, 1); OUT_RING (1); + BEGIN_RING(kelvin, NV20TCL_COLOR_MASK, 1); + OUT_RING (0x00010101); + BEGIN_RING(kelvin, NV20TCL_CLEAR_VALUE, 1); + OUT_RING (0); memset(projectionmatrix, 0, sizeof(projectionmatrix)); - BEGIN_RING(kelvin, NV10TCL_PROJECTION_MATRIX(0), 16); projectionmatrix[0*4+0] = 1.0; projectionmatrix[1*4+1] = 1.0; projectionmatrix[2*4+2] = 1.0; projectionmatrix[3*4+3] = 1.0; - for (i=0;i<16;i++) { + BEGIN_RING(kelvin, NV20TCL_PROJECTION_MATRIX(0), 16); + for (i = 0; i < 16; i++) { OUT_RINGf (projectionmatrix[i]); } - BEGIN_RING(kelvin, NV10TCL_DEPTH_RANGE_NEAR, 2); - OUT_RING (0.0); - OUT_RINGf (16777216.0); + BEGIN_RING(kelvin, NV20TCL_DEPTH_RANGE_NEAR, 2); + OUT_RINGf (0.0); + OUT_RINGf (16777216.0); /* bpp dependant? */ + + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_SCALE0_X, 4); + OUT_RINGf (-2048.0); + OUT_RINGf (-2048.0); + OUT_RINGf (16777215.0 * 0.5); + OUT_RING (0); - BEGIN_RING(kelvin, NV10TCL_VIEWPORT_SCALE_X, 4); + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_SCALE1_X, 4); OUT_RINGf (-2048.0); OUT_RINGf (-2048.0); OUT_RINGf (16777215.0 * 0.5); diff --git a/src/gallium/drivers/nv20/nv20_fragtex.c b/src/gallium/drivers/nv20/nv20_fragtex.c index 77c34897e2..94c64f76d5 100644 --- a/src/gallium/drivers/nv20/nv20_fragtex.c +++ b/src/gallium/drivers/nv20/nv20_fragtex.c @@ -30,7 +30,7 @@ static INLINE int log2i(int i) { \ TRUE, \ PIPE_FORMAT_##m, \ - NV10TCL_TX_FORMAT_FORMAT_##tf, \ + NV20TCL_TX_FORMAT_FORMAT_##tf, \ } struct nv20_texture_format { @@ -47,10 +47,10 @@ nv20_texture_formats[] = { _(L8_UNORM , L8 ), _(A8_UNORM , A8 ), _(A8L8_UNORM , A8L8 ), -// _(RGB_DXT1 , DXT1, ), -// _(RGBA_DXT1 , DXT1, ), -// _(RGBA_DXT3 , DXT3, ), -// _(RGBA_DXT5 , DXT5, ), +/* _(RGB_DXT1 , DXT1, ), */ +/* _(RGBA_DXT1 , DXT1, ), */ +/* _(RGBA_DXT3 , DXT3, ), */ +/* _(RGBA_DXT5 , DXT5, ), */ {}, }; diff --git a/src/gallium/drivers/nv20/nv20_prim_vbuf.c b/src/gallium/drivers/nv20/nv20_prim_vbuf.c index fd9cad177a..74540845a8 100644 --- a/src/gallium/drivers/nv20/nv20_prim_vbuf.c +++ b/src/gallium/drivers/nv20/nv20_prim_vbuf.c @@ -80,13 +80,15 @@ nv20_vbuf_render(struct vbuf_render *render) void nv20_vtxbuf_bind( struct nv20_context* nv20 ) { +#if 0 int i; - for(i = 0; i < 8; i++) { - BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_ATTRIB_OFFSET(i), 1); + for(i = 0; i < NV20TCL_VTXBUF_ADDRESS__SIZE; i++) { + BEGIN_RING(kelvin, NV20TCL_VTXBUF_ADDRESS(i), 1); OUT_RING(0/*nv20->vtxbuf*/); - BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT(i) ,1); + BEGIN_RING(kelvin, NV20TCL_VTXFMT(i) ,1); OUT_RING(0/*XXX*/); } +#endif } static const struct vertex_info * @@ -162,9 +164,9 @@ nv20_vbuf_render_set_primitive( struct vbuf_render *render, static uint32_t nv20__vtxhwformat(unsigned stride, unsigned fields, unsigned type) { - return (stride << NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_STRIDE_SHIFT) | - (fields << NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_FIELDS_SHIFT) | - (type << NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT_TYPE_SHIFT); + return (stride << NV20TCL_VTXFMT_STRIDE_SHIFT) | + (fields << NV20TCL_VTXFMT_SIZE_SHIFT) | + (type << NV20TCL_VTXFMT_TYPE_SHIFT); } static unsigned @@ -199,7 +201,7 @@ nv20__emit_format(struct nv20_context *nv20, enum attrib_emit type, int hwattr) return 0; } - BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT(hwattr), 1); + BEGIN_RING(kelvin, NV20TCL_VTXFMT(hwattr), 1); OUT_RING(hwfmt); return fields; } @@ -208,7 +210,7 @@ static unsigned nv20__emit_vertex_array_format(struct nv20_context *nv20) { struct vertex_info *vinfo = &nv20->vertex_info; - int hwattr = NV10TCL_VERTEX_ARRAY_ATTRIB_FORMAT__SIZE; + int hwattr = NV20TCL_VTXFMT__SIZE; int attr = 0; unsigned nr_fields = 0; @@ -220,8 +222,6 @@ nv20__emit_vertex_array_format(struct nv20_context *nv20) } else nv20__emit_format(nv20, EMIT_OMIT, hwattr); } - BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_VALIDATE, 1); - OUT_RING(0); return nr_fields; } @@ -240,7 +240,7 @@ nv20__draw_mbuffer(struct nv20_vbuf_render *nv20_render, nr_fields = nv20__emit_vertex_array_format(nv20); - BEGIN_RING(kelvin, NV10TCL_VERTEX_BEGIN_END, 1); + BEGIN_RING(kelvin, NV20TCL_VERTEX_BEGIN_END, 1); OUT_RING(nv20_render->hwprim); max_push = 1200 / nr_fields; @@ -248,8 +248,7 @@ nv20__draw_mbuffer(struct nv20_vbuf_render *nv20_render, int i; int push = MIN2(nr_indices, max_push); - BEGIN_RING_NI(kelvin, NV10TCL_VERTEX_ARRAY_DATA, - push * nr_fields); + BEGIN_RING_NI(kelvin, NV20TCL_VERTEX_DATA, push * nr_fields); for (i = 0; i < push; i++) { /* XXX: fixme to handle other than floats? */ int f = nr_fields; @@ -262,8 +261,8 @@ nv20__draw_mbuffer(struct nv20_vbuf_render *nv20_render, indices += push; } - BEGIN_RING(kelvin, NV10TCL_VERTEX_BEGIN_END, 1); - OUT_RING(NV10TCL_VERTEX_BEGIN_END_STOP); + BEGIN_RING(kelvin, NV20TCL_VERTEX_BEGIN_END, 1); + OUT_RING(NV20TCL_VERTEX_BEGIN_END_STOP); } static void @@ -274,6 +273,8 @@ nv20__draw_pbuffer(struct nv20_vbuf_render *nv20_render, struct nv20_context *nv20 = nv20_render->nv20; int push, i; + NOUVEAU_ERR("nv20__draw_pbuffer: this path is broken.\n"); + BEGIN_RING(kelvin, NV10TCL_VERTEX_ARRAY_OFFSET_POS, 1); OUT_RELOCl(nv20_render->pbuffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); diff --git a/src/gallium/drivers/nv20/nv20_screen.c b/src/gallium/drivers/nv20/nv20_screen.c index b7f5ea8512..c0a90f6c58 100644 --- a/src/gallium/drivers/nv20/nv20_screen.c +++ b/src/gallium/drivers/nv20/nv20_screen.c @@ -151,7 +151,7 @@ struct pipe_screen * nv20_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws) { struct nv20_screen *screen = CALLOC_STRUCT(nv20_screen); - unsigned celsius_class; + unsigned kelvin_class = 0; unsigned chipset = nvws->channel->device->chipset; int ret; @@ -160,21 +160,17 @@ nv20_screen_create(struct pipe_winsys *ws, struct nouveau_winsys *nvws) screen->nvws = nvws; /* 3D object */ - if (chipset>=0x20) - celsius_class=NV11TCL; - else if (chipset>=0x17) - celsius_class=NV17TCL; - else if (chipset>=0x11) - celsius_class=NV11TCL; - else - celsius_class=NV10TCL; - - if (!celsius_class) { - NOUVEAU_ERR("Unknown nv1x chipset: nv%02x\n", chipset); + if (chipset >= 0x25) + kelvin_class = NV25TCL; + else if (chipset >= 0x20) + kelvin_class = NV20TCL; + + if (!kelvin_class || chipset >= 0x30) { + NOUVEAU_ERR("Unknown nv2x chipset: nv%02x\n", chipset); return NULL; } - ret = nvws->grobj_alloc(nvws, celsius_class, &screen->kelvin); + ret = nvws->grobj_alloc(nvws, kelvin_class, &screen->kelvin); if (ret) { NOUVEAU_ERR("Error creating 3D object: %d\n", ret); return FALSE; diff --git a/src/gallium/drivers/nv20/nv20_state.c b/src/gallium/drivers/nv20/nv20_state.c index c3b87230b7..21bde5b81f 100644 --- a/src/gallium/drivers/nv20/nv20_state.c +++ b/src/gallium/drivers/nv20/nv20_state.c @@ -55,30 +55,30 @@ wrap_mode(unsigned wrap) { switch (wrap) { case PIPE_TEX_WRAP_REPEAT: - ret = NV10TCL_TX_FORMAT_WRAP_S_REPEAT; + ret = NV20TCL_TX_WRAP_S_REPEAT; break; case PIPE_TEX_WRAP_MIRROR_REPEAT: - ret = NV10TCL_TX_FORMAT_WRAP_S_MIRRORED_REPEAT; + ret = NV20TCL_TX_WRAP_S_MIRRORED_REPEAT; break; case PIPE_TEX_WRAP_CLAMP_TO_EDGE: - ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_EDGE; + ret = NV20TCL_TX_WRAP_S_CLAMP_TO_EDGE; break; case PIPE_TEX_WRAP_CLAMP_TO_BORDER: - ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP_TO_BORDER; + ret = NV20TCL_TX_WRAP_S_CLAMP_TO_BORDER; break; case PIPE_TEX_WRAP_CLAMP: - ret = NV10TCL_TX_FORMAT_WRAP_S_CLAMP; + ret = NV20TCL_TX_WRAP_S_CLAMP; break; case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: case PIPE_TEX_WRAP_MIRROR_CLAMP: default: NOUVEAU_ERR("unknown wrap mode: %d\n", wrap); - ret = NV10TCL_TX_FORMAT_WRAP_S_REPEAT; + ret = NV20TCL_TX_WRAP_S_REPEAT; break; } - return ret >> NV10TCL_TX_FORMAT_WRAP_S_SHIFT; + return (ret >> NV20TCL_TX_WRAP_S_SHIFT); } static void * @@ -90,43 +90,31 @@ nv20_sampler_state_create(struct pipe_context *pipe, ps = MALLOC(sizeof(struct nv20_sampler_state)); - ps->wrap = ((wrap_mode(cso->wrap_s) << NV10TCL_TX_FORMAT_WRAP_S_SHIFT) | - (wrap_mode(cso->wrap_t) << NV10TCL_TX_FORMAT_WRAP_T_SHIFT)); + ps->wrap = ((wrap_mode(cso->wrap_s) << NV20TCL_TX_WRAP_S_SHIFT) | + (wrap_mode(cso->wrap_t) << NV20TCL_TX_WRAP_T_SHIFT)); ps->en = 0; if (cso->max_anisotropy > 1.0) { /* no idea, binary driver sets it, works without it.. meh.. */ ps->wrap |= (1 << 5); -/* if (cso->max_anisotropy >= 16.0) { - ps->en |= NV10TCL_TX_ENABLE_ANISO_16X; - } else - if (cso->max_anisotropy >= 12.0) { - ps->en |= NV10TCL_TX_ENABLE_ANISO_12X; - } else - if (cso->max_anisotropy >= 10.0) { - ps->en |= NV10TCL_TX_ENABLE_ANISO_10X; - } else - if (cso->max_anisotropy >= 8.0) { - ps->en |= NV10TCL_TX_ENABLE_ANISO_8X; - } else - if (cso->max_anisotropy >= 6.0) { - ps->en |= NV10TCL_TX_ENABLE_ANISO_6X; +/* if (cso->max_anisotropy >= 8.0) { + ps->en |= NV20TCL_TX_ENABLE_ANISO_8X; } else if (cso->max_anisotropy >= 4.0) { - ps->en |= NV10TCL_TX_ENABLE_ANISO_4X; + ps->en |= NV20TCL_TX_ENABLE_ANISO_4X; } else { - ps->en |= NV10TCL_TX_ENABLE_ANISO_2X; + ps->en |= NV20TCL_TX_ENABLE_ANISO_2X; }*/ } switch (cso->mag_img_filter) { case PIPE_TEX_FILTER_LINEAR: - filter |= NV10TCL_TX_FILTER_MAGNIFY_LINEAR; + filter |= NV20TCL_TX_FILTER_MAGNIFY_LINEAR; break; case PIPE_TEX_FILTER_NEAREST: default: - filter |= NV10TCL_TX_FILTER_MAGNIFY_NEAREST; + filter |= NV20TCL_TX_FILTER_MAGNIFY_NEAREST; break; } @@ -134,14 +122,15 @@ nv20_sampler_state_create(struct pipe_context *pipe, case PIPE_TEX_FILTER_LINEAR: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST; + filter |= + NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR; + filter |= NV20TCL_TX_FILTER_MINIFY_LINEAR_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV10TCL_TX_FILTER_MINIFY_LINEAR; + filter |= NV20TCL_TX_FILTER_MINIFY_LINEAR; break; } break; @@ -149,14 +138,16 @@ nv20_sampler_state_create(struct pipe_context *pipe, default: switch (cso->min_mip_filter) { case PIPE_TEX_MIPFILTER_NEAREST: - filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST; + filter |= + NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_NEAREST; break; case PIPE_TEX_MIPFILTER_LINEAR: - filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR; + filter |= + NV20TCL_TX_FILTER_MINIFY_NEAREST_MIPMAP_LINEAR; break; case PIPE_TEX_MIPFILTER_NONE: default: - filter |= NV10TCL_TX_FILTER_MINIFY_NEAREST; + filter |= NV20TCL_TX_FILTER_MINIFY_NEAREST; break; } break; @@ -253,21 +244,23 @@ nv20_rasterizer_state_create(struct pipe_context *pipe, rs->templ = cso; - rs->shade_model = cso->flatshade ? 0x1d00 : 0x1d01; + rs->shade_model = cso->flatshade ? NV20TCL_SHADE_MODEL_FLAT : + NV20TCL_SHADE_MODEL_SMOOTH; rs->line_width = (unsigned char)(cso->line_width * 8.0) & 0xff; rs->line_smooth_en = cso->line_smooth ? 1 : 0; + /* XXX: nv20 and nv25 different! */ rs->point_size = *(uint32_t*)&cso->point_size; rs->poly_smooth_en = cso->poly_smooth ? 1 : 0; if (cso->front_winding == PIPE_WINDING_CCW) { - rs->front_face = NV10TCL_FRONT_FACE_CCW; + rs->front_face = NV20TCL_FRONT_FACE_CCW; rs->poly_mode_front = nvgl_polygon_mode(cso->fill_ccw); rs->poly_mode_back = nvgl_polygon_mode(cso->fill_cw); } else { - rs->front_face = NV10TCL_FRONT_FACE_CW; + rs->front_face = NV20TCL_FRONT_FACE_CW; rs->poly_mode_front = nvgl_polygon_mode(cso->fill_cw); rs->poly_mode_back = nvgl_polygon_mode(cso->fill_ccw); } @@ -276,20 +269,20 @@ nv20_rasterizer_state_create(struct pipe_context *pipe, case PIPE_WINDING_CCW: rs->cull_face_en = 1; if (cso->front_winding == PIPE_WINDING_CCW) - rs->cull_face = NV10TCL_CULL_FACE_FRONT; + rs->cull_face = NV20TCL_CULL_FACE_FRONT; else - rs->cull_face = NV10TCL_CULL_FACE_BACK; + rs->cull_face = NV20TCL_CULL_FACE_BACK; break; case PIPE_WINDING_CW: rs->cull_face_en = 1; if (cso->front_winding == PIPE_WINDING_CW) - rs->cull_face = NV10TCL_CULL_FACE_FRONT; + rs->cull_face = NV20TCL_CULL_FACE_FRONT; else - rs->cull_face = NV10TCL_CULL_FACE_BACK; + rs->cull_face = NV20TCL_CULL_FACE_BACK; break; case PIPE_WINDING_BOTH: rs->cull_face_en = 1; - rs->cull_face = NV10TCL_CULL_FACE_FRONT_AND_BACK; + rs->cull_face = NV20TCL_CULL_FACE_FRONT_AND_BACK; break; case PIPE_WINDING_NONE: default: diff --git a/src/gallium/drivers/nv20/nv20_state_emit.c b/src/gallium/drivers/nv20/nv20_state_emit.c index d0772c527b..5265bf3a31 100644 --- a/src/gallium/drivers/nv20/nv20_state_emit.c +++ b/src/gallium/drivers/nv20/nv20_state_emit.c @@ -6,15 +6,17 @@ static void nv20_state_emit_blend(struct nv20_context* nv20) { struct nv20_blend_state *b = nv20->blend; - BEGIN_RING(kelvin, NV10TCL_DITHER_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_DITHER_ENABLE, 1); OUT_RING (b->d_enable); - BEGIN_RING(kelvin, NV10TCL_BLEND_FUNC_ENABLE, 3); + BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_ENABLE, 1); OUT_RING (b->b_enable); + + BEGIN_RING(kelvin, NV20TCL_BLEND_FUNC_SRC, 2); OUT_RING (b->b_srcfunc); OUT_RING (b->b_dstfunc); - BEGIN_RING(kelvin, NV10TCL_COLOR_MASK, 1); + BEGIN_RING(kelvin, NV20TCL_COLOR_MASK, 1); OUT_RING (b->c_mask); } @@ -22,7 +24,7 @@ static void nv20_state_emit_blend_color(struct nv20_context* nv20) { struct pipe_blend_color *c = nv20->blend_color; - BEGIN_RING(kelvin, NV10TCL_BLEND_COLOR, 1); + BEGIN_RING(kelvin, NV20TCL_BLEND_COLOR, 1); OUT_RING ((float_to_ubyte(c->color[3]) << 24)| (float_to_ubyte(c->color[0]) << 16)| (float_to_ubyte(c->color[1]) << 8) | @@ -33,28 +35,28 @@ static void nv20_state_emit_rast(struct nv20_context* nv20) { struct nv20_rasterizer_state *r = nv20->rast; - BEGIN_RING(kelvin, NV10TCL_SHADE_MODEL, 2); + BEGIN_RING(kelvin, NV20TCL_SHADE_MODEL, 2); OUT_RING (r->shade_model); OUT_RING (r->line_width); - BEGIN_RING(kelvin, NV10TCL_POINT_SIZE, 1); + BEGIN_RING(kelvin, NV20TCL_POINT_SIZE, 1); OUT_RING (r->point_size); - BEGIN_RING(kelvin, NV10TCL_POLYGON_MODE_FRONT, 2); + BEGIN_RING(kelvin, NV20TCL_POLYGON_MODE_FRONT, 2); OUT_RING (r->poly_mode_front); OUT_RING (r->poly_mode_back); - BEGIN_RING(kelvin, NV10TCL_CULL_FACE, 2); + BEGIN_RING(kelvin, NV20TCL_CULL_FACE, 2); OUT_RING (r->cull_face); OUT_RING (r->front_face); - BEGIN_RING(kelvin, NV10TCL_LINE_SMOOTH_ENABLE, 2); + BEGIN_RING(kelvin, NV20TCL_LINE_SMOOTH_ENABLE, 2); OUT_RING (r->line_smooth_en); OUT_RING (r->poly_smooth_en); - BEGIN_RING(kelvin, NV10TCL_CULL_FACE_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_CULL_FACE_ENABLE, 1); OUT_RING (r->cull_face_en); } @@ -62,29 +64,29 @@ static void nv20_state_emit_dsa(struct nv20_context* nv20) { struct nv20_depth_stencil_alpha_state *d = nv20->dsa; - BEGIN_RING(kelvin, NV10TCL_DEPTH_FUNC, 1); + BEGIN_RING(kelvin, NV20TCL_DEPTH_FUNC, 1); OUT_RING (d->depth.func); - BEGIN_RING(kelvin, NV10TCL_DEPTH_WRITE_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_DEPTH_WRITE_ENABLE, 1); OUT_RING (d->depth.write_enable); - BEGIN_RING(kelvin, NV10TCL_DEPTH_TEST_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_DEPTH_TEST_ENABLE, 1); OUT_RING (d->depth.test_enable); #if 0 - BEGIN_RING(kelvin, NV10TCL_STENCIL_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_STENCIL_ENABLE, 1); OUT_RING (d->stencil.enable); - BEGIN_RING(kelvin, NV10TCL_STENCIL_MASK, 7); + BEGIN_RING(kelvin, NV20TCL_STENCIL_MASK, 7); OUT_RINGp ((uint32_t *)&(d->stencil.wmask), 7); #endif - BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_ENABLE, 1); + BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_ENABLE, 1); OUT_RING (d->alpha.enabled); - BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_FUNC, 1); + BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_FUNC, 1); OUT_RING (d->alpha.func); - BEGIN_RING(kelvin, NV10TCL_ALPHA_FUNC_REF, 1); + BEGIN_RING(kelvin, NV20TCL_ALPHA_FUNC_REF, 1); OUT_RING (d->alpha.ref); } @@ -94,9 +96,9 @@ static void nv20_state_emit_viewport(struct nv20_context* nv20) static void nv20_state_emit_scissor(struct nv20_context* nv20) { - // XXX this is so not working + /* NV20TCL_SCISSOR_* is probably a software method */ /* struct pipe_scissor_state *s = nv20->scissor; - BEGIN_RING(kelvin, NV10TCL_SCISSOR_HORIZ, 2); + BEGIN_RING(kelvin, NV20TCL_SCISSOR_HORIZ, 2); OUT_RING (((s->maxx - s->minx) << 16) | s->minx); OUT_RING (((s->maxy - s->miny) << 16) | s->miny);*/ } @@ -126,25 +128,25 @@ static void nv20_state_emit_framebuffer(struct nv20_context* nv20) zeta = fb->zsbuf; } - rt_format = NV10TCL_RT_FORMAT_TYPE_LINEAR; + rt_format = NV20TCL_RT_FORMAT_TYPE_LINEAR | 0x20; switch (colour_format) { case PIPE_FORMAT_A8R8G8B8_UNORM: case 0: - rt_format |= NV10TCL_RT_FORMAT_COLOR_A8R8G8B8; + rt_format |= NV20TCL_RT_FORMAT_COLOR_A8R8G8B8; break; case PIPE_FORMAT_R5G6B5_UNORM: - rt_format |= NV10TCL_RT_FORMAT_COLOR_R5G6B5; + rt_format |= NV20TCL_RT_FORMAT_COLOR_R5G6B5; break; default: assert(0); } if (zeta) { - BEGIN_RING(kelvin, NV10TCL_RT_PITCH, 1); + BEGIN_RING(kelvin, NV20TCL_RT_PITCH, 1); OUT_RING (rt->stride | (zeta->stride << 16)); } else { - BEGIN_RING(kelvin, NV10TCL_RT_PITCH, 1); + BEGIN_RING(kelvin, NV20TCL_RT_PITCH, 1); OUT_RING (rt->stride | (rt->stride << 16)); } @@ -155,13 +157,13 @@ static void nv20_state_emit_framebuffer(struct nv20_context* nv20) nv20->zeta = zeta->buffer; } - BEGIN_RING(kelvin, NV10TCL_RT_HORIZ, 3); + BEGIN_RING(kelvin, NV20TCL_RT_HORIZ, 3); OUT_RING ((w << 16) | 0); OUT_RING ((h << 16) | 0); OUT_RING (rt_format); - BEGIN_RING(kelvin, NV10TCL_VIEWPORT_CLIP_HORIZ(0), 2); - OUT_RING (((w - 1) << 16) | 0 | 0x08000800); - OUT_RING (((h - 1) << 16) | 0 | 0x08000800); + BEGIN_RING(kelvin, NV20TCL_VIEWPORT_CLIP_HORIZ(0), 2); + OUT_RING (((w - 1) << 16) | 0); + OUT_RING (((h - 1) << 16) | 0); } static void nv20_vertex_layout(struct nv20_context *nv20) @@ -317,17 +319,17 @@ nv20_emit_hw_state(struct nv20_context *nv20) */ /* Render target */ -// XXX figre out who's who for NV10TCL_DMA_* and fill accordingly -// BEGIN_RING(kelvin, NV10TCL_DMA_COLOR0, 1); -// OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(kelvin, NV10TCL_COLOR_OFFSET, 1); +/* XXX figre out who's who for NV10TCL_DMA_* and fill accordingly + * BEGIN_RING(kelvin, NV20TCL_DMA_COLOR0, 1); + * OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); */ + BEGIN_RING(kelvin, NV20TCL_COLOR_OFFSET, 1); OUT_RELOCl(nv20->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); if (nv20->zeta) { -// XXX -// BEGIN_RING(kelvin, NV10TCL_DMA_ZETA, 1); -// OUT_RELOCo(nv20->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(kelvin, NV10TCL_ZETA_OFFSET, 1); +/* XXX + * BEGIN_RING(kelvin, NV20TCL_DMA_ZETA, 1); + * OUT_RELOCo(nv20->zeta, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); */ + BEGIN_RING(kelvin, NV20TCL_ZETA_OFFSET, 1); OUT_RELOCl(nv20->zeta, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); /* XXX for when we allocate LMA on nv17 */ /* BEGIN_RING(kelvin, NV10TCL_LMA_DEPTH_BUFFER_OFFSET, 1); @@ -335,23 +337,23 @@ nv20_emit_hw_state(struct nv20_context *nv20) } /* Vertex buffer */ - BEGIN_RING(kelvin, NV10TCL_DMA_VTXBUF0, 1); + BEGIN_RING(kelvin, NV20TCL_DMA_VTXBUF0, 1); OUT_RELOCo(nv20->rt[0], NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); - BEGIN_RING(kelvin, NV10TCL_COLOR_OFFSET, 1); + BEGIN_RING(kelvin, NV20TCL_COLOR_OFFSET, 1); OUT_RELOCl(nv20->rt[0], 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); /* Texture images */ for (i = 0; i < 2; i++) { if (!(nv20->fp_samplers & (1 << i))) continue; - BEGIN_RING(kelvin, NV10TCL_TX_OFFSET(i), 1); + BEGIN_RING(kelvin, NV20TCL_TX_OFFSET(i), 1); OUT_RELOCl(nv20->tex[i].buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD); - BEGIN_RING(kelvin, NV10TCL_TX_FORMAT(i), 1); + BEGIN_RING(kelvin, NV20TCL_TX_FORMAT(i), 1); OUT_RELOCd(nv20->tex[i].buffer, nv20->tex[i].format, NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD | - NOUVEAU_BO_OR, NV10TCL_TX_FORMAT_DMA0, - NV10TCL_TX_FORMAT_DMA1); + NOUVEAU_BO_OR, NV20TCL_TX_FORMAT_DMA0, + NV20TCL_TX_FORMAT_DMA1); } } -- cgit v1.2.3 From a7e72231e3c76a9410d192441da309002ea6422d Mon Sep 17 00:00:00 2001 From: Zack Rusin Date: Mon, 26 Jan 2009 14:37:21 -0500 Subject: gallium: standardize naming of masks --- src/gallium/drivers/cell/ppu/cell_gen_fragment.c | 42 +++++++++++----------- .../drivers/cell/ppu/cell_state_per_fragment.c | 16 ++++----- src/gallium/drivers/i915simple/i915_state.c | 8 ++--- src/gallium/drivers/i965simple/brw_cc.c | 12 +++---- src/gallium/drivers/i965simple/brw_wm.c | 4 +-- src/gallium/drivers/nv10/nv10_state.c | 4 +-- src/gallium/drivers/nv20/nv20_state.c | 4 +-- src/gallium/drivers/nv30/nv30_state.c | 8 ++--- src/gallium/drivers/nv40/nv40_state.c | 8 ++--- src/gallium/drivers/nv50/nv50_state.c | 8 ++--- src/gallium/drivers/softpipe/sp_quad_stencil.c | 4 +-- src/gallium/drivers/trace/tr_state.c | 4 +-- src/gallium/include/pipe/p_state.h | 6 ++-- src/gallium/state_trackers/g3dvl/vl_context.c | 4 +-- src/mesa/state_tracker/st_atom_depth.c | 8 ++--- src/mesa/state_tracker/st_cb_clear.c | 4 +-- 16 files changed, 72 insertions(+), 72 deletions(-) (limited to 'src/gallium/drivers/nv20/nv20_state.c') diff --git a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c index 0ea8f017ef..9bdc71b676 100644 --- a/src/gallium/drivers/cell/ppu/cell_gen_fragment.c +++ b/src/gallium/drivers/cell/ppu/cell_gen_fragment.c @@ -1187,7 +1187,7 @@ gen_stencil_test(struct spe_function *f, */ switch (state->func) { case PIPE_FUNC_EQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (s == reference) */ spe_compare_equal_uint(f, stencil_pass_reg, fbS_reg, state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); @@ -1195,16 +1195,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ((s&mask) == (reference&mask)) */ uint tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_equal_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_NOTEQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & ~(s == reference) */ spe_compare_equal_uint(f, stencil_pass_reg, fbS_reg, state->ref_value); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); @@ -1212,16 +1212,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ~((s&mask) == (reference&mask)) */ int tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_equal_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_LESS: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference < s) */ spe_compare_greater_uint(f, stencil_pass_reg, fbS_reg, state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); @@ -1229,16 +1229,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ((reference&mask) < (s & mask)) */ int tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_greater_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_GREATER: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference > s) */ /* There's no convenient Compare Less Than Immediate instruction, so * we'll have to do this one the harder way, by loading a register and @@ -1255,8 +1255,8 @@ gen_stencil_test(struct spe_function *f, /* stencil_pass = fragment_mask & ((reference&mask) > (s&mask)) */ int tmp_reg = spe_allocate_available_register(f); int tmp_masked_stencil = spe_allocate_available_register(f); - spe_load_uint(f, tmp_reg, state->value_mask & state->ref_value); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_load_uint(f, tmp_reg, state->valuemask & state->ref_value); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_clgt(f, stencil_pass_reg, tmp_reg, tmp_masked_stencil); spe_and(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_reg); @@ -1265,7 +1265,7 @@ gen_stencil_test(struct spe_function *f, break; case PIPE_FUNC_GEQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference >= s) * = fragment_mask & ~(s > reference) */ spe_compare_greater_uint(f, stencil_pass_reg, fbS_reg, @@ -1275,16 +1275,16 @@ gen_stencil_test(struct spe_function *f, else { /* stencil_pass = fragment_mask & ~((s&mask) > (reference&mask)) */ int tmp_masked_stencil = spe_allocate_available_register(f); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_compare_greater_uint(f, stencil_pass_reg, tmp_masked_stencil, - state->value_mask & state->ref_value); + state->valuemask & state->ref_value); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_masked_stencil); } break; case PIPE_FUNC_LEQUAL: - if (state->value_mask == stencil_max_value) { + if (state->valuemask == stencil_max_value) { /* stencil_pass = fragment_mask & (reference <= s) ] * = fragment_mask & ~(reference > s) */ /* As above, we have to do this by loading a register */ @@ -1298,8 +1298,8 @@ gen_stencil_test(struct spe_function *f, /* stencil_pass = fragment_mask & ~((reference&mask) > (s&mask)) */ int tmp_reg = spe_allocate_available_register(f); int tmp_masked_stencil = spe_allocate_available_register(f); - spe_load_uint(f, tmp_reg, state->ref_value & state->value_mask); - spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->value_mask); + spe_load_uint(f, tmp_reg, state->ref_value & state->valuemask); + spe_and_uint(f, tmp_masked_stencil, fbS_reg, state->valuemask); spe_clgt(f, stencil_pass_reg, tmp_reg, tmp_masked_stencil); spe_andc(f, stencil_pass_reg, fragment_mask_reg, stencil_pass_reg); spe_release_register(f, tmp_reg); @@ -1600,14 +1600,14 @@ gen_stencil_depth_test(struct spe_function *f, need_to_calculate_stencil_values = FALSE; need_to_writemask_stencil_values = FALSE; } - else if (stencil->write_mask == 0x0) { + else if (stencil->writemask == 0x0) { /* All changes are writemasked out, so no need to calculate * what those changes might be, and no need to write anything back. */ need_to_calculate_stencil_values = FALSE; need_to_writemask_stencil_values = FALSE; } - else if (stencil->write_mask == 0xff) { + else if (stencil->writemask == 0xff) { /* Still trivial, but a little less so. We need to write the stencil * values, but we don't need to mask them. */ @@ -1627,7 +1627,7 @@ gen_stencil_depth_test(struct spe_function *f, */ spe_comment(f, 0, "Computing stencil writemask"); stencil_writemask_reg = spe_allocate_available_register(f); - spe_load_uint(f, stencil_writemask_reg, dsa->stencil[facing].write_mask); + spe_load_uint(f, stencil_writemask_reg, dsa->stencil[facing].writemask); } /* At least one-sided stenciling must be on. Generate code that diff --git a/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c b/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c index 78cb446c14..d97c22b2ef 100644 --- a/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c +++ b/src/gallium/drivers/cell/ppu/cell_state_per_fragment.c @@ -297,7 +297,7 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, int face_stencil = spe_allocate_available_register(f); int stencil_src = stencil; const unsigned ref = (dsa->stencil[face].ref_value - & dsa->stencil[face].value_mask); + & dsa->stencil[face].valuemask); boolean complement = FALSE; int stored; int tmp = spe_allocate_available_register(f); @@ -305,9 +305,9 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, if ((dsa->stencil[face].func != PIPE_FUNC_NEVER) && (dsa->stencil[face].func != PIPE_FUNC_ALWAYS) - && (dsa->stencil[face].value_mask != 0x0ff)) { + && (dsa->stencil[face].valuemask != 0x0ff)) { stored = spe_allocate_available_register(f); - spe_andi(f, stored, stencil, dsa->stencil[face].value_mask); + spe_andi(f, stored, stencil, dsa->stencil[face].valuemask); } else { stored = stencil; } @@ -395,7 +395,7 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, * - For depth-pass if the stencil test is NEVER * - Any of the 3 conditions if the operation is KEEP */ - if (dsa->stencil[face].write_mask != 0) { + if (dsa->stencil[face].writemask != 0) { if ((dsa->stencil[face].func != PIPE_FUNC_ALWAYS) && (dsa->stencil[face].fail_op != PIPE_STENCIL_OP_KEEP)) { if (complement) { @@ -449,10 +449,10 @@ emit_stencil_test(struct pipe_depth_stencil_alpha_state *dsa, */ if (stencil_src == stencil) { spe_release_register(f, face_stencil); - } else if (dsa->stencil[face].write_mask != 0x0ff) { + } else if (dsa->stencil[face].writemask != 0x0ff) { int tmp = spe_allocate_available_register(f); - spe_il(f, tmp, dsa->stencil[face].write_mask); + spe_il(f, tmp, dsa->stencil[face].writemask); spe_selb(f, stencil_src, stencil, stencil_src, tmp); spe_release_register(f, tmp); @@ -580,8 +580,8 @@ cell_generate_depth_stencil_test(struct cell_depth_stencil_alpha_state *cdsa) dsa->stencil[i].zpass_op); printf("# ref value / value mask / write mask: %02x %02x %02x\n", dsa->stencil[i].ref_value, - dsa->stencil[i].value_mask, - dsa->stencil[i].write_mask); + dsa->stencil[i].valuemask, + dsa->stencil[i].writemask); } printf("\t.text\n"); diff --git a/src/gallium/drivers/i915simple/i915_state.c b/src/gallium/drivers/i915simple/i915_state.c index d2487d8277..92365f6a7a 100644 --- a/src/gallium/drivers/i915simple/i915_state.c +++ b/src/gallium/drivers/i915simple/i915_state.c @@ -318,8 +318,8 @@ i915_create_depth_stencil_state(struct pipe_context *pipe, struct i915_depth_stencil_state *cso = CALLOC_STRUCT( i915_depth_stencil_state ); { - int testmask = depth_stencil->stencil[0].value_mask & 0xff; - int writemask = depth_stencil->stencil[0].write_mask & 0xff; + int testmask = depth_stencil->stencil[0].valuemask & 0xff; + int writemask = depth_stencil->stencil[0].writemask & 0xff; cso->stencil_modes4 |= (_3DSTATE_MODES_4_CMD | ENABLE_STENCIL_TEST_MASK | @@ -350,8 +350,8 @@ i915_create_depth_stencil_state(struct pipe_context *pipe, int dfop = i915_translate_stencil_op(depth_stencil->stencil[1].zfail_op); int dpop = i915_translate_stencil_op(depth_stencil->stencil[1].zpass_op); int ref = depth_stencil->stencil[1].ref_value & 0xff; - int tmask = depth_stencil->stencil[1].value_mask & 0xff; - int wmask = depth_stencil->stencil[1].write_mask & 0xff; + int tmask = depth_stencil->stencil[1].valuemask & 0xff; + int wmask = depth_stencil->stencil[1].writemask & 0xff; cso->bfo[0] = (_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_FUNCS | diff --git a/src/gallium/drivers/i965simple/brw_cc.c b/src/gallium/drivers/i965simple/brw_cc.c index 79d4150383..6191e73d12 100644 --- a/src/gallium/drivers/i965simple/brw_cc.c +++ b/src/gallium/drivers/i965simple/brw_cc.c @@ -166,8 +166,8 @@ static void upload_cc_unit( struct brw_context *brw ) cc.cc0.stencil_pass_depth_pass_op = brw_translate_stencil_op( brw->attribs.DepthStencil->stencil[0].zpass_op); cc.cc1.stencil_ref = brw->attribs.DepthStencil->stencil[0].ref_value; - cc.cc1.stencil_write_mask = brw->attribs.DepthStencil->stencil[0].write_mask; - cc.cc1.stencil_test_mask = brw->attribs.DepthStencil->stencil[0].value_mask; + cc.cc1.stencil_write_mask = brw->attribs.DepthStencil->stencil[0].writemask; + cc.cc1.stencil_test_mask = brw->attribs.DepthStencil->stencil[0].valuemask; if (brw->attribs.DepthStencil->stencil[1].enabled) { cc.cc0.bf_stencil_enable = brw->attribs.DepthStencil->stencil[1].enabled; @@ -180,14 +180,14 @@ static void upload_cc_unit( struct brw_context *brw ) cc.cc0.bf_stencil_pass_depth_pass_op = brw_translate_stencil_op( brw->attribs.DepthStencil->stencil[1].zpass_op); cc.cc1.bf_stencil_ref = brw->attribs.DepthStencil->stencil[1].ref_value; - cc.cc2.bf_stencil_write_mask = brw->attribs.DepthStencil->stencil[1].write_mask; - cc.cc2.bf_stencil_test_mask = brw->attribs.DepthStencil->stencil[1].value_mask; + cc.cc2.bf_stencil_write_mask = brw->attribs.DepthStencil->stencil[1].writemask; + cc.cc2.bf_stencil_test_mask = brw->attribs.DepthStencil->stencil[1].valuemask; } /* Not really sure about this: */ - if (brw->attribs.DepthStencil->stencil[0].write_mask || - brw->attribs.DepthStencil->stencil[1].write_mask) + if (brw->attribs.DepthStencil->stencil[0].writemask || + brw->attribs.DepthStencil->stencil[1].writemask) cc.cc0.stencil_write_enable = 1; } diff --git a/src/gallium/drivers/i965simple/brw_wm.c b/src/gallium/drivers/i965simple/brw_wm.c index 8de565b96c..10161f2d2f 100644 --- a/src/gallium/drivers/i965simple/brw_wm.c +++ b/src/gallium/drivers/i965simple/brw_wm.c @@ -111,8 +111,8 @@ static void brw_wm_populate_key( struct brw_context *brw, if (brw->attribs.DepthStencil->stencil[0].enabled) { lookup |= IZ_STENCIL_TEST_ENABLE_BIT; - if (brw->attribs.DepthStencil->stencil[0].write_mask || - brw->attribs.DepthStencil->stencil[1].write_mask) + if (brw->attribs.DepthStencil->stencil[0].writemask || + brw->attribs.DepthStencil->stencil[1].writemask) lookup |= IZ_STENCIL_WRITE_ENABLE_BIT; } diff --git a/src/gallium/drivers/nv10/nv10_state.c b/src/gallium/drivers/nv10/nv10_state.c index d2375aa2f6..e401b3590e 100644 --- a/src/gallium/drivers/nv10/nv10_state.c +++ b/src/gallium/drivers/nv10/nv10_state.c @@ -342,10 +342,10 @@ nv10_depth_stencil_alpha_state_create(struct pipe_context *pipe, hw->depth.test_enable = cso->depth.enabled ? 1 : 0; hw->stencil.enable = cso->stencil[0].enabled ? 1 : 0; - hw->stencil.wmask = cso->stencil[0].write_mask; + hw->stencil.wmask = cso->stencil[0].writemask; hw->stencil.func = nvgl_comparison_op(cso->stencil[0].func); hw->stencil.ref = cso->stencil[0].ref_value; - hw->stencil.vmask = cso->stencil[0].value_mask; + hw->stencil.vmask = cso->stencil[0].valuemask; hw->stencil.fail = nvgl_stencil_op(cso->stencil[0].fail_op); hw->stencil.zfail = nvgl_stencil_op(cso->stencil[0].zfail_op); hw->stencil.zpass = nvgl_stencil_op(cso->stencil[0].zpass_op); diff --git a/src/gallium/drivers/nv20/nv20_state.c b/src/gallium/drivers/nv20/nv20_state.c index 21bde5b81f..8eb2bee93d 100644 --- a/src/gallium/drivers/nv20/nv20_state.c +++ b/src/gallium/drivers/nv20/nv20_state.c @@ -335,10 +335,10 @@ nv20_depth_stencil_alpha_state_create(struct pipe_context *pipe, hw->depth.test_enable = cso->depth.enabled ? 1 : 0; hw->stencil.enable = cso->stencil[0].enabled ? 1 : 0; - hw->stencil.wmask = cso->stencil[0].write_mask; + hw->stencil.wmask = cso->stencil[0].writemask; hw->stencil.func = nvgl_comparison_op(cso->stencil[0].func); hw->stencil.ref = cso->stencil[0].ref_value; - hw->stencil.vmask = cso->stencil[0].value_mask; + hw->stencil.vmask = cso->stencil[0].valuemask; hw->stencil.fail = nvgl_stencil_op(cso->stencil[0].fail_op); hw->stencil.zfail = nvgl_stencil_op(cso->stencil[0].zfail_op); hw->stencil.zpass = nvgl_stencil_op(cso->stencil[0].zpass_op); diff --git a/src/gallium/drivers/nv30/nv30_state.c b/src/gallium/drivers/nv30/nv30_state.c index 47e1a625af..2ae66e7085 100644 --- a/src/gallium/drivers/nv30/nv30_state.c +++ b/src/gallium/drivers/nv30/nv30_state.c @@ -449,10 +449,10 @@ nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[0].enabled) { so_method(so, rankine, NV34TCL_STENCIL_FRONT_ENABLE, 8); so_data (so, cso->stencil[0].enabled ? 1 : 0); - so_data (so, cso->stencil[0].write_mask); + so_data (so, cso->stencil[0].writemask); so_data (so, nvgl_comparison_op(cso->stencil[0].func)); so_data (so, cso->stencil[0].ref_value); - so_data (so, cso->stencil[0].value_mask); + so_data (so, cso->stencil[0].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op)); @@ -464,10 +464,10 @@ nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[1].enabled) { so_method(so, rankine, NV34TCL_STENCIL_BACK_ENABLE, 8); so_data (so, cso->stencil[1].enabled ? 1 : 0); - so_data (so, cso->stencil[1].write_mask); + so_data (so, cso->stencil[1].writemask); so_data (so, nvgl_comparison_op(cso->stencil[1].func)); so_data (so, cso->stencil[1].ref_value); - so_data (so, cso->stencil[1].value_mask); + so_data (so, cso->stencil[1].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); diff --git a/src/gallium/drivers/nv40/nv40_state.c b/src/gallium/drivers/nv40/nv40_state.c index 255c4b294d..34d109f9af 100644 --- a/src/gallium/drivers/nv40/nv40_state.c +++ b/src/gallium/drivers/nv40/nv40_state.c @@ -459,10 +459,10 @@ nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[0].enabled) { so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 8); so_data (so, cso->stencil[0].enabled ? 1 : 0); - so_data (so, cso->stencil[0].write_mask); + so_data (so, cso->stencil[0].writemask); so_data (so, nvgl_comparison_op(cso->stencil[0].func)); so_data (so, cso->stencil[0].ref_value); - so_data (so, cso->stencil[0].value_mask); + so_data (so, cso->stencil[0].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[0].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[0].zpass_op)); @@ -474,10 +474,10 @@ nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe, if (cso->stencil[1].enabled) { so_method(so, curie, NV40TCL_STENCIL_BACK_ENABLE, 8); so_data (so, cso->stencil[1].enabled ? 1 : 0); - so_data (so, cso->stencil[1].write_mask); + so_data (so, cso->stencil[1].writemask); so_data (so, nvgl_comparison_op(cso->stencil[1].func)); so_data (so, cso->stencil[1].ref_value); - so_data (so, cso->stencil[1].value_mask); + so_data (so, cso->stencil[1].valuemask); so_data (so, nvgl_stencil_op(cso->stencil[1].fail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zfail_op)); so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); diff --git a/src/gallium/drivers/nv50/nv50_state.c b/src/gallium/drivers/nv50/nv50_state.c index 38c1d938b8..ac236db298 100644 --- a/src/gallium/drivers/nv50/nv50_state.c +++ b/src/gallium/drivers/nv50/nv50_state.c @@ -403,8 +403,8 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe, so_data (so, nvgl_comparison_op(cso->stencil[0].func)); so_method(so, tesla, NV50TCL_STENCIL_BACK_FUNC_REF, 3); so_data (so, cso->stencil[0].ref_value); - so_data (so, cso->stencil[0].write_mask); - so_data (so, cso->stencil[0].value_mask); + so_data (so, cso->stencil[0].writemask); + so_data (so, cso->stencil[0].valuemask); } else { so_method(so, tesla, NV50TCL_STENCIL_BACK_ENABLE, 1); so_data (so, 0); @@ -418,8 +418,8 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe, so_data (so, nvgl_stencil_op(cso->stencil[1].zpass_op)); so_data (so, nvgl_comparison_op(cso->stencil[1].func)); so_data (so, cso->stencil[1].ref_value); - so_data (so, cso->stencil[1].write_mask); - so_data (so, cso->stencil[1].value_mask); + so_data (so, cso->stencil[1].writemask); + so_data (so, cso->stencil[1].valuemask); } else { so_method(so, tesla, NV50TCL_STENCIL_FRONT_ENABLE, 1); so_data (so, 0); diff --git a/src/gallium/drivers/softpipe/sp_quad_stencil.c b/src/gallium/drivers/softpipe/sp_quad_stencil.c index abb5487748..7495515764 100644 --- a/src/gallium/drivers/softpipe/sp_quad_stencil.c +++ b/src/gallium/drivers/softpipe/sp_quad_stencil.c @@ -222,8 +222,8 @@ stencil_test_quad(struct quad_stage *qs, struct quad_header *quad) zFailOp = softpipe->depth_stencil->stencil[face].zfail_op; zPassOp = softpipe->depth_stencil->stencil[face].zpass_op; ref = softpipe->depth_stencil->stencil[face].ref_value; - wrtMask = softpipe->depth_stencil->stencil[face].write_mask; - valMask = softpipe->depth_stencil->stencil[face].value_mask; + wrtMask = softpipe->depth_stencil->stencil[face].writemask; + valMask = softpipe->depth_stencil->stencil[face].valuemask; assert(ps); /* shouldn't get here if there's no stencil buffer */ diff --git a/src/gallium/drivers/trace/tr_state.c b/src/gallium/drivers/trace/tr_state.c index 546231612f..8b147a8d37 100644 --- a/src/gallium/drivers/trace/tr_state.c +++ b/src/gallium/drivers/trace/tr_state.c @@ -281,8 +281,8 @@ void trace_dump_depth_stencil_alpha_state(const struct pipe_depth_stencil_alpha_ trace_dump_member(uint, &state->stencil[i], zpass_op); trace_dump_member(uint, &state->stencil[i], zfail_op); trace_dump_member(uint, &state->stencil[i], ref_value); - trace_dump_member(uint, &state->stencil[i], value_mask); - trace_dump_member(uint, &state->stencil[i], write_mask); + trace_dump_member(uint, &state->stencil[i], valuemask); + trace_dump_member(uint, &state->stencil[i], writemask); trace_dump_struct_end(); trace_dump_elem_end(); } diff --git a/src/gallium/include/pipe/p_state.h b/src/gallium/include/pipe/p_state.h index 46f62abf3f..0a0ca770da 100644 --- a/src/gallium/include/pipe/p_state.h +++ b/src/gallium/include/pipe/p_state.h @@ -188,9 +188,9 @@ struct pipe_stencil_state unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */ unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */ unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */ - ubyte ref_value; - ubyte value_mask; - ubyte write_mask; + ubyte ref_value; + ubyte valuemask; + ubyte writemask; }; diff --git a/src/gallium/state_trackers/g3dvl/vl_context.c b/src/gallium/state_trackers/g3dvl/vl_context.c index fbea1363d8..c4c4e23c15 100644 --- a/src/gallium/state_trackers/g3dvl/vl_context.c +++ b/src/gallium/state_trackers/g3dvl/vl_context.c @@ -81,8 +81,8 @@ static int vlInitCommon(struct vlContext *context) dsa.stencil[i].zpass_op = PIPE_STENCIL_OP_KEEP; dsa.stencil[i].zfail_op = PIPE_STENCIL_OP_KEEP; dsa.stencil[i].ref_value = 0; - dsa.stencil[i].value_mask = 0; - dsa.stencil[i].write_mask = 0; + dsa.stencil[i].valuemask = 0; + dsa.stencil[i].writemask = 0; } dsa.alpha.enabled = 0; dsa.alpha.func = PIPE_FUNC_ALWAYS; diff --git a/src/mesa/state_tracker/st_atom_depth.c b/src/mesa/state_tracker/st_atom_depth.c index 0e791ceb20..8b5f22d0ef 100644 --- a/src/mesa/state_tracker/st_atom_depth.c +++ b/src/mesa/state_tracker/st_atom_depth.c @@ -112,8 +112,8 @@ update_depth_stencil_alpha(struct st_context *st) dsa->stencil[0].zfail_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZFailFunc[0]); dsa->stencil[0].zpass_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZPassFunc[0]); dsa->stencil[0].ref_value = st->ctx->Stencil.Ref[0] & 0xff; - dsa->stencil[0].value_mask = st->ctx->Stencil.ValueMask[0] & 0xff; - dsa->stencil[0].write_mask = st->ctx->Stencil.WriteMask[0] & 0xff; + dsa->stencil[0].valuemask = st->ctx->Stencil.ValueMask[0] & 0xff; + dsa->stencil[0].writemask = st->ctx->Stencil.WriteMask[0] & 0xff; if (st->ctx->Stencil._TestTwoSide) { dsa->stencil[1].enabled = 1; @@ -122,8 +122,8 @@ update_depth_stencil_alpha(struct st_context *st) dsa->stencil[1].zfail_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZFailFunc[1]); dsa->stencil[1].zpass_op = gl_stencil_op_to_pipe(st->ctx->Stencil.ZPassFunc[1]); dsa->stencil[1].ref_value = st->ctx->Stencil.Ref[1] & 0xff; - dsa->stencil[1].value_mask = st->ctx->Stencil.ValueMask[1] & 0xff; - dsa->stencil[1].write_mask = st->ctx->Stencil.WriteMask[1] & 0xff; + dsa->stencil[1].valuemask = st->ctx->Stencil.ValueMask[1] & 0xff; + dsa->stencil[1].writemask = st->ctx->Stencil.WriteMask[1] & 0xff; } else { dsa->stencil[1] = dsa->stencil[0]; diff --git a/src/mesa/state_tracker/st_cb_clear.c b/src/mesa/state_tracker/st_cb_clear.c index fca1107d72..668c3f9ebf 100644 --- a/src/mesa/state_tracker/st_cb_clear.c +++ b/src/mesa/state_tracker/st_cb_clear.c @@ -287,8 +287,8 @@ clear_with_quad(GLcontext *ctx, depth_stencil.stencil[0].zpass_op = PIPE_STENCIL_OP_REPLACE; depth_stencil.stencil[0].zfail_op = PIPE_STENCIL_OP_REPLACE; depth_stencil.stencil[0].ref_value = ctx->Stencil.Clear; - depth_stencil.stencil[0].value_mask = 0xff; - depth_stencil.stencil[0].write_mask = ctx->Stencil.WriteMask[0] & 0xff; + depth_stencil.stencil[0].valuemask = 0xff; + depth_stencil.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff; } cso_set_depth_stencil_alpha(st->cso_context, &depth_stencil); -- cgit v1.2.3 From d6888e811d24eaa7e8d9093be606394f00435c05 Mon Sep 17 00:00:00 2001 From: Zack Rusin Date: Mon, 26 Jan 2009 15:07:08 -0500 Subject: gallium: it's a reference value, not a reference number --- src/gallium/drivers/i915simple/i915_state.c | 2 +- src/gallium/drivers/i965simple/brw_cc.c | 2 +- src/gallium/drivers/nv04/nv04_state.c | 2 +- src/gallium/drivers/nv10/nv10_state.c | 2 +- src/gallium/drivers/nv20/nv20_state.c | 2 +- src/gallium/drivers/nv30/nv30_state.c | 2 +- src/gallium/drivers/nv40/nv40_state.c | 2 +- src/gallium/drivers/nv50/nv50_state.c | 2 +- src/gallium/drivers/softpipe/sp_quad_alpha_test.c | 2 +- src/gallium/drivers/trace/tr_state.c | 2 +- src/gallium/include/pipe/p_state.h | 2 +- src/mesa/state_tracker/st_atom_depth.c | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) (limited to 'src/gallium/drivers/nv20/nv20_state.c') diff --git a/src/gallium/drivers/i915simple/i915_state.c b/src/gallium/drivers/i915simple/i915_state.c index 92365f6a7a..f46e46eb22 100644 --- a/src/gallium/drivers/i915simple/i915_state.c +++ b/src/gallium/drivers/i915simple/i915_state.c @@ -394,7 +394,7 @@ i915_create_depth_stencil_state(struct pipe_context *pipe, if (depth_stencil->alpha.enabled) { int test = i915_translate_compare_func(depth_stencil->alpha.func); - ubyte refByte = float_to_ubyte(depth_stencil->alpha.ref); + ubyte refByte = float_to_ubyte(depth_stencil->alpha.ref_value); cso->depth_LIS6 |= (S6_ALPHA_TEST_ENABLE | (test << S6_ALPHA_TEST_FUNC_SHIFT) | diff --git a/src/gallium/drivers/i965simple/brw_cc.c b/src/gallium/drivers/i965simple/brw_cc.c index 6191e73d12..3668123e2e 100644 --- a/src/gallium/drivers/i965simple/brw_cc.c +++ b/src/gallium/drivers/i965simple/brw_cc.c @@ -233,7 +233,7 @@ static void upload_cc_unit( struct brw_context *brw ) cc.cc3.alpha_test_func = brw_translate_compare_func(brw->attribs.DepthStencil->alpha.func); - cc.cc7.alpha_ref.ub[0] = float_to_ubyte(brw->attribs.DepthStencil->alpha.ref); + cc.cc7.alpha_ref.ub[0] = float_to_ubyte(brw->attribs.DepthStencil->alpha.ref_value); cc.cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8; } diff --git a/src/gallium/drivers/nv04/nv04_state.c b/src/gallium/drivers/nv04/nv04_state.c index ff1933b550..c07a86dd0e 100644 --- a/src/gallium/drivers/nv04/nv04_state.c +++ b/src/gallium/drivers/nv04/nv04_state.c @@ -227,7 +227,7 @@ nv04_depth_stencil_alpha_state_create(struct pipe_context *pipe, hw = MALLOC(sizeof(struct nv04_depth_stencil_alpha_state)); - hw->control = float_to_ubyte(cso->alpha.ref); + hw->control = float_to_ubyte(cso->alpha.ref_value); hw->control |= ( nv04_compare_func(cso->alpha.func) << NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_FUNC_SHIFT ); hw->control |= cso->alpha.enabled ? NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ALPHA_TEST_ENABLE : 0; hw->control |= NV04_DX5_TEXTURED_TRIANGLE_CONTROL_ORIGIN; diff --git a/src/gallium/drivers/nv10/nv10_state.c b/src/gallium/drivers/nv10/nv10_state.c index e401b3590e..622bcdf22e 100644 --- a/src/gallium/drivers/nv10/nv10_state.c +++ b/src/gallium/drivers/nv10/nv10_state.c @@ -352,7 +352,7 @@ nv10_depth_stencil_alpha_state_create(struct pipe_context *pipe, hw->alpha.enabled = cso->alpha.enabled ? 1 : 0; hw->alpha.func = nvgl_comparison_op(cso->alpha.func); - hw->alpha.ref = float_to_ubyte(cso->alpha.ref); + hw->alpha.ref = float_to_ubyte(cso->alpha.ref_value); return (void *)hw; } diff --git a/src/gallium/drivers/nv20/nv20_state.c b/src/gallium/drivers/nv20/nv20_state.c index 8eb2bee93d..e8dc9665e8 100644 --- a/src/gallium/drivers/nv20/nv20_state.c +++ b/src/gallium/drivers/nv20/nv20_state.c @@ -345,7 +345,7 @@ nv20_depth_stencil_alpha_state_create(struct pipe_context *pipe, hw->alpha.enabled = cso->alpha.enabled ? 1 : 0; hw->alpha.func = nvgl_comparison_op(cso->alpha.func); - hw->alpha.ref = float_to_ubyte(cso->alpha.ref); + hw->alpha.ref = float_to_ubyte(cso->alpha.ref_value); return (void *)hw; } diff --git a/src/gallium/drivers/nv30/nv30_state.c b/src/gallium/drivers/nv30/nv30_state.c index 2ae66e7085..63f5303166 100644 --- a/src/gallium/drivers/nv30/nv30_state.c +++ b/src/gallium/drivers/nv30/nv30_state.c @@ -444,7 +444,7 @@ nv30_depth_stencil_alpha_state_create(struct pipe_context *pipe, so_method(so, rankine, NV34TCL_ALPHA_FUNC_ENABLE, 3); so_data (so, cso->alpha.enabled ? 1 : 0); so_data (so, nvgl_comparison_op(cso->alpha.func)); - so_data (so, float_to_ubyte(cso->alpha.ref)); + so_data (so, float_to_ubyte(cso->alpha.ref_value)); if (cso->stencil[0].enabled) { so_method(so, rankine, NV34TCL_STENCIL_FRONT_ENABLE, 8); diff --git a/src/gallium/drivers/nv40/nv40_state.c b/src/gallium/drivers/nv40/nv40_state.c index 34d109f9af..d5d81b1371 100644 --- a/src/gallium/drivers/nv40/nv40_state.c +++ b/src/gallium/drivers/nv40/nv40_state.c @@ -454,7 +454,7 @@ nv40_depth_stencil_alpha_state_create(struct pipe_context *pipe, so_method(so, curie, NV40TCL_ALPHA_TEST_ENABLE, 3); so_data (so, cso->alpha.enabled ? 1 : 0); so_data (so, nvgl_comparison_op(cso->alpha.func)); - so_data (so, float_to_ubyte(cso->alpha.ref)); + so_data (so, float_to_ubyte(cso->alpha.ref_value)); if (cso->stencil[0].enabled) { so_method(so, curie, NV40TCL_STENCIL_FRONT_ENABLE, 8); diff --git a/src/gallium/drivers/nv50/nv50_state.c b/src/gallium/drivers/nv50/nv50_state.c index ac236db298..787ff958ec 100644 --- a/src/gallium/drivers/nv50/nv50_state.c +++ b/src/gallium/drivers/nv50/nv50_state.c @@ -429,7 +429,7 @@ nv50_depth_stencil_alpha_state_create(struct pipe_context *pipe, so_method(so, tesla, NV50TCL_ALPHA_TEST_ENABLE, 1); so_data (so, 1); so_method(so, tesla, NV50TCL_ALPHA_TEST_REF, 2); - so_data (so, fui(cso->alpha.ref)); + so_data (so, fui(cso->alpha.ref_value)); so_data (so, nvgl_comparison_op(cso->alpha.func)); } else { so_method(so, tesla, NV50TCL_ALPHA_TEST_ENABLE, 1); diff --git a/src/gallium/drivers/softpipe/sp_quad_alpha_test.c b/src/gallium/drivers/softpipe/sp_quad_alpha_test.c index 5bebd141e9..85c9f037a3 100644 --- a/src/gallium/drivers/softpipe/sp_quad_alpha_test.c +++ b/src/gallium/drivers/softpipe/sp_quad_alpha_test.c @@ -14,7 +14,7 @@ static void alpha_test_quad(struct quad_stage *qs, struct quad_header *quad) { struct softpipe_context *softpipe = qs->softpipe; - const float ref = softpipe->depth_stencil->alpha.ref; + const float ref = softpipe->depth_stencil->alpha.ref_value; unsigned passMask = 0x0, j; const uint cbuf = 0; /* only output[0].alpha is tested */ const float *aaaa = quad->output.color[cbuf][3]; diff --git a/src/gallium/drivers/trace/tr_state.c b/src/gallium/drivers/trace/tr_state.c index 155f1cb859..095b054bb5 100644 --- a/src/gallium/drivers/trace/tr_state.c +++ b/src/gallium/drivers/trace/tr_state.c @@ -293,7 +293,7 @@ void trace_dump_depth_stencil_alpha_state(const struct pipe_depth_stencil_alpha_ trace_dump_struct_begin("pipe_alpha_state"); trace_dump_member(bool, &state->alpha, enabled); trace_dump_member(uint, &state->alpha, func); - trace_dump_member(float, &state->alpha, ref); + trace_dump_member(float, &state->alpha, ref_value); trace_dump_struct_end(); trace_dump_member_end(); diff --git a/src/gallium/include/pipe/p_state.h b/src/gallium/include/pipe/p_state.h index 1f4dc3f7dc..866c8a82dc 100644 --- a/src/gallium/include/pipe/p_state.h +++ b/src/gallium/include/pipe/p_state.h @@ -198,7 +198,7 @@ struct pipe_alpha_state { unsigned enabled:1; unsigned func:3; /**< PIPE_FUNC_x */ - float ref; /**< reference value */ + float ref_value; /**< reference value */ }; diff --git a/src/mesa/state_tracker/st_atom_depth.c b/src/mesa/state_tracker/st_atom_depth.c index 8b5f22d0ef..2d617bd95d 100644 --- a/src/mesa/state_tracker/st_atom_depth.c +++ b/src/mesa/state_tracker/st_atom_depth.c @@ -134,7 +134,7 @@ update_depth_stencil_alpha(struct st_context *st) if (st->ctx->Color.AlphaEnabled) { dsa->alpha.enabled = 1; dsa->alpha.func = st_compare_func_to_pipe(st->ctx->Color.AlphaFunc); - dsa->alpha.ref = st->ctx->Color.AlphaRef; + dsa->alpha.ref_value = st->ctx->Color.AlphaRef; } cso_set_depth_stencil_alpha(st->cso_context, dsa); -- cgit v1.2.3 From 4f5308bdcb9e62f678975a77783a48096f6dfdc6 Mon Sep 17 00:00:00 2001 From: Zack Rusin Date: Mon, 26 Jan 2009 15:22:53 -0500 Subject: gallium: remove redundant size from the constant buffer reuse the size of the actual buffer --- src/gallium/drivers/i915simple/i915_state.c | 6 +++--- src/gallium/drivers/i965simple/brw_curbe.c | 6 +++--- src/gallium/drivers/nv10/nv10_state.c | 7 ++++--- src/gallium/drivers/nv20/nv20_state.c | 7 ++++--- src/gallium/drivers/nv30/nv30_state.c | 2 +- src/gallium/drivers/nv40/nv40_state.c | 2 +- src/gallium/drivers/softpipe/sp_draw_arrays.c | 6 +++--- src/gallium/drivers/softpipe/sp_state_fs.c | 1 - src/gallium/drivers/trace/tr_state.c | 1 - src/gallium/include/pipe/p_state.h | 1 - src/mesa/state_tracker/st_atom_constbuf.c | 2 -- 11 files changed, 19 insertions(+), 22 deletions(-) (limited to 'src/gallium/drivers/nv20/nv20_state.c') diff --git a/src/gallium/drivers/i915simple/i915_state.c b/src/gallium/drivers/i915simple/i915_state.c index f46e46eb22..19f194c027 100644 --- a/src/gallium/drivers/i915simple/i915_state.c +++ b/src/gallium/drivers/i915simple/i915_state.c @@ -535,13 +535,13 @@ static void i915_set_constant_buffer(struct pipe_context *pipe, */ if (buf) { void *mapped; - if (buf->size && + if (buf->buffer && buf->buffer->size && (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ))) { - memcpy(i915->current.constants[shader], mapped, buf->size); + memcpy(i915->current.constants[shader], mapped, buf->buffer->size); ws->buffer_unmap(ws, buf->buffer); i915->current.num_user_constants[shader] - = buf->size / (4 * sizeof(float)); + = buf->buffer->size / (4 * sizeof(float)); } else { i915->current.num_user_constants[shader] = 0; diff --git a/src/gallium/drivers/i965simple/brw_curbe.c b/src/gallium/drivers/i965simple/brw_curbe.c index 824ee7fd6d..5e1cce7530 100644 --- a/src/gallium/drivers/i965simple/brw_curbe.c +++ b/src/gallium/drivers/i965simple/brw_curbe.c @@ -257,13 +257,13 @@ static void upload_constant_buffer(struct brw_context *brw) if (brw->vs.prog_data->num_consts) { /* map the vertex constant buffer and copy to curbe: */ void *data = ws->buffer_map(ws, cbuffer->buffer, 0); - /* FIXME: this is wrong. the cbuffer->size currently + /* FIXME: this is wrong. the cbuffer->buffer->size currently * represents size of consts + immediates. so if we'll * have both we'll copy over the end of the buffer * with the subsequent memcpy */ - memcpy(&buf[offset], data, cbuffer->size); + memcpy(&buf[offset], data, cbuffer->buffer->size); ws->buffer_unmap(ws, cbuffer->buffer); - offset += cbuffer->size; + offset += cbuffer->buffer->size; } /*immediates*/ if (brw->vs.prog_data->num_imm) { diff --git a/src/gallium/drivers/nv10/nv10_state.c b/src/gallium/drivers/nv10/nv10_state.c index 622bcdf22e..119af66dfd 100644 --- a/src/gallium/drivers/nv10/nv10_state.c +++ b/src/gallium/drivers/nv10/nv10_state.c @@ -467,11 +467,12 @@ nv10_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, if (buf) { void *mapped; - if (buf->size && (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ))) + if (buf->buffer && buf->buffer->size && + (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ))) { - memcpy(nv10->constbuf[shader], mapped, buf->size); + memcpy(nv10->constbuf[shader], mapped, buf->buffer->size); nv10->constbuf_nr[shader] = - buf->size / (4 * sizeof(float)); + buf->buffer->size / (4 * sizeof(float)); ws->buffer_unmap(ws, buf->buffer); } } diff --git a/src/gallium/drivers/nv20/nv20_state.c b/src/gallium/drivers/nv20/nv20_state.c index e8dc9665e8..ecec4f49a0 100644 --- a/src/gallium/drivers/nv20/nv20_state.c +++ b/src/gallium/drivers/nv20/nv20_state.c @@ -460,11 +460,12 @@ nv20_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, if (buf) { void *mapped; - if (buf->size && (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ))) + if (buf->buffer && buf->buffer->size && + (mapped = ws->buffer_map(ws, buf->buffer, PIPE_BUFFER_USAGE_CPU_READ))) { - memcpy(nv20->constbuf[shader], mapped, buf->size); + memcpy(nv20->constbuf[shader], mapped, buf->buffer->size); nv20->constbuf_nr[shader] = - buf->size / (4 * sizeof(float)); + buf->buffer->size / (4 * sizeof(float)); ws->buffer_unmap(ws, buf->buffer); } } diff --git a/src/gallium/drivers/nv30/nv30_state.c b/src/gallium/drivers/nv30/nv30_state.c index 63f5303166..26147565a5 100644 --- a/src/gallium/drivers/nv30/nv30_state.c +++ b/src/gallium/drivers/nv30/nv30_state.c @@ -592,7 +592,7 @@ nv30_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, struct nv30_context *nv30 = nv30_context(pipe); nv30->constbuf[shader] = buf->buffer; - nv30->constbuf_nr[shader] = buf->size / (4 * sizeof(float)); + nv30->constbuf_nr[shader] = buf->buffer->size / (4 * sizeof(float)); if (shader == PIPE_SHADER_VERTEX) { nv30->dirty |= NV30_NEW_VERTPROG; diff --git a/src/gallium/drivers/nv40/nv40_state.c b/src/gallium/drivers/nv40/nv40_state.c index d5d81b1371..2eff25aa83 100644 --- a/src/gallium/drivers/nv40/nv40_state.c +++ b/src/gallium/drivers/nv40/nv40_state.c @@ -607,7 +607,7 @@ nv40_set_constant_buffer(struct pipe_context *pipe, uint shader, uint index, struct nv40_context *nv40 = nv40_context(pipe); nv40->constbuf[shader] = buf->buffer; - nv40->constbuf_nr[shader] = buf->size / (4 * sizeof(float)); + nv40->constbuf_nr[shader] = buf->buffer->size / (4 * sizeof(float)); if (shader == PIPE_SHADER_VERTEX) { nv40->dirty |= NV40_NEW_VERTPROG; diff --git a/src/gallium/drivers/softpipe/sp_draw_arrays.c b/src/gallium/drivers/softpipe/sp_draw_arrays.c index 424bd56846..ed3e8f95ae 100644 --- a/src/gallium/drivers/softpipe/sp_draw_arrays.c +++ b/src/gallium/drivers/softpipe/sp_draw_arrays.c @@ -49,14 +49,14 @@ softpipe_map_constant_buffers(struct softpipe_context *sp) struct pipe_winsys *ws = sp->pipe.winsys; uint i; for (i = 0; i < PIPE_SHADER_TYPES; i++) { - if (sp->constants[i].size) + if (sp->constants[i].buffer && sp->constants[i].buffer->size) sp->mapped_constants[i] = ws->buffer_map(ws, sp->constants[i].buffer, PIPE_BUFFER_USAGE_CPU_READ); } draw_set_mapped_constant_buffer(sp->draw, sp->mapped_constants[PIPE_SHADER_VERTEX], - sp->constants[PIPE_SHADER_VERTEX].size); + sp->constants[PIPE_SHADER_VERTEX].buffer->size); } static void @@ -73,7 +73,7 @@ softpipe_unmap_constant_buffers(struct softpipe_context *sp) draw_set_mapped_constant_buffer(sp->draw, NULL, 0); for (i = 0; i < 2; i++) { - if (sp->constants[i].size) + if (sp->constants[i].buffer && sp->constants[i].buffer->size) ws->buffer_unmap(ws, sp->constants[i].buffer); sp->mapped_constants[i] = NULL; } diff --git a/src/gallium/drivers/softpipe/sp_state_fs.c b/src/gallium/drivers/softpipe/sp_state_fs.c index e5b609cf6c..15815160ed 100644 --- a/src/gallium/drivers/softpipe/sp_state_fs.c +++ b/src/gallium/drivers/softpipe/sp_state_fs.c @@ -155,7 +155,6 @@ softpipe_set_constant_buffer(struct pipe_context *pipe, winsys_buffer_reference(ws, &softpipe->constants[shader].buffer, buf ? buf->buffer : NULL); - softpipe->constants[shader].size = buf ? buf->size : 0; softpipe->dirty |= SP_NEW_CONSTANTS; } diff --git a/src/gallium/drivers/trace/tr_state.c b/src/gallium/drivers/trace/tr_state.c index 095b054bb5..b23ccc1a3d 100644 --- a/src/gallium/drivers/trace/tr_state.c +++ b/src/gallium/drivers/trace/tr_state.c @@ -223,7 +223,6 @@ void trace_dump_constant_buffer(const struct pipe_constant_buffer *state) trace_dump_struct_begin("pipe_constant_buffer"); trace_dump_member(ptr, state, buffer); - trace_dump_member(uint, state, size); trace_dump_struct_end(); } diff --git a/src/gallium/include/pipe/p_state.h b/src/gallium/include/pipe/p_state.h index 866c8a82dc..13fa9ba848 100644 --- a/src/gallium/include/pipe/p_state.h +++ b/src/gallium/include/pipe/p_state.h @@ -162,7 +162,6 @@ struct pipe_clip_state struct pipe_constant_buffer { struct pipe_buffer *buffer; - unsigned size; /** in bytes (XXX: redundant!) */ }; diff --git a/src/mesa/state_tracker/st_atom_constbuf.c b/src/mesa/state_tracker/st_atom_constbuf.c index d02e51cb9a..514b10cd02 100644 --- a/src/mesa/state_tracker/st_atom_constbuf.c +++ b/src/mesa/state_tracker/st_atom_constbuf.c @@ -92,8 +92,6 @@ void st_upload_constants( struct st_context *st, pipe_buffer_unmap(pipe->screen, cbuf->buffer); } - cbuf->size = paramBytes; - st->pipe->set_constant_buffer(st->pipe, id, 0, cbuf); } else { -- cgit v1.2.3