From d673c92810636dcc6de33d3618d494ce9f5717c1 Mon Sep 17 00:00:00 2001 From: Luca Barbieri Date: Sat, 20 Feb 2010 18:34:00 +0100 Subject: nouveau: s/rankine/eng3d/g; s/curie/eng3d/g Result of running: perl -i -p -e 's/rankine/eng3d/g; s/curie/eng3d/g;' nv[34]0/*.[ch] This will allow to more easily unify nv30 and nv40. --- src/gallium/drivers/nv40/nv40_state_fb.c | 38 ++++++++++++++++---------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'src/gallium/drivers/nv40/nv40_state_fb.c') diff --git a/src/gallium/drivers/nv40/nv40_state_fb.c b/src/gallium/drivers/nv40/nv40_state_fb.c index 93e91b9e3b..207b70923e 100644 --- a/src/gallium/drivers/nv40/nv40_state_fb.c +++ b/src/gallium/drivers/nv40/nv40_state_fb.c @@ -14,7 +14,7 @@ static boolean nv40_state_framebuffer_validate(struct nv40_context *nv40) { struct nouveau_channel *chan = nv40->screen->base.channel; - struct nouveau_grobj *curie = nv40->screen->curie; + struct nouveau_grobj *eng3d = nv40->screen->eng3d; struct pipe_framebuffer_state *fb = &nv40->framebuffer; struct nv04_surface *rt[4], *zeta; uint32_t rt_enable, rt_format; @@ -85,11 +85,11 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) } if (rt_enable & NV40TCL_RT_ENABLE_COLOR0) { - so_method(so, curie, NV34TCL_DMA_COLOR0, 1); + so_method(so, eng3d, NV34TCL_DMA_COLOR0, 1); so_reloc (so, nv40_surface_buffer(&rt[0]->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV34TCL_COLOR0_PITCH, 2); + so_method(so, eng3d, NV34TCL_COLOR0_PITCH, 2); so_data (so, rt[0]->pitch); so_reloc (so, nv40_surface_buffer(&rt[0]->base), rt[0]->base.offset, rt_flags | NOUVEAU_BO_LOW, @@ -97,11 +97,11 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) } if (rt_enable & NV40TCL_RT_ENABLE_COLOR1) { - so_method(so, curie, NV34TCL_DMA_COLOR1, 1); + so_method(so, eng3d, NV34TCL_DMA_COLOR1, 1); so_reloc (so, nv40_surface_buffer(&rt[1]->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV34TCL_COLOR1_OFFSET, 2); + so_method(so, eng3d, NV34TCL_COLOR1_OFFSET, 2); so_reloc (so, nv40_surface_buffer(&rt[1]->base), rt[1]->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); @@ -109,56 +109,56 @@ nv40_state_framebuffer_validate(struct nv40_context *nv40) } if (rt_enable & NV40TCL_RT_ENABLE_COLOR2) { - so_method(so, curie, NV40TCL_DMA_COLOR2, 1); + so_method(so, eng3d, NV40TCL_DMA_COLOR2, 1); so_reloc (so, nv40_surface_buffer(&rt[2]->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV40TCL_COLOR2_OFFSET, 1); + so_method(so, eng3d, NV40TCL_COLOR2_OFFSET, 1); so_reloc (so, nv40_surface_buffer(&rt[2]->base), rt[2]->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); - so_method(so, curie, NV40TCL_COLOR2_PITCH, 1); + so_method(so, eng3d, NV40TCL_COLOR2_PITCH, 1); so_data (so, rt[2]->pitch); } if (rt_enable & NV40TCL_RT_ENABLE_COLOR3) { - so_method(so, curie, NV40TCL_DMA_COLOR3, 1); + so_method(so, eng3d, NV40TCL_DMA_COLOR3, 1); so_reloc (so, nv40_surface_buffer(&rt[3]->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV40TCL_COLOR3_OFFSET, 1); + so_method(so, eng3d, NV40TCL_COLOR3_OFFSET, 1); so_reloc (so, nv40_surface_buffer(&rt[3]->base), rt[3]->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); - so_method(so, curie, NV40TCL_COLOR3_PITCH, 1); + so_method(so, eng3d, NV40TCL_COLOR3_PITCH, 1); so_data (so, rt[3]->pitch); } if (zeta_format) { - so_method(so, curie, NV34TCL_DMA_ZETA, 1); + so_method(so, eng3d, NV34TCL_DMA_ZETA, 1); so_reloc (so, nv40_surface_buffer(&zeta->base), 0, rt_flags | NOUVEAU_BO_OR, chan->vram->handle, chan->gart->handle); - so_method(so, curie, NV34TCL_ZETA_OFFSET, 1); + so_method(so, eng3d, NV34TCL_ZETA_OFFSET, 1); so_reloc (so, nv40_surface_buffer(&zeta->base), zeta->base.offset, rt_flags | NOUVEAU_BO_LOW, 0, 0); - so_method(so, curie, NV40TCL_ZETA_PITCH, 1); + so_method(so, eng3d, NV40TCL_ZETA_PITCH, 1); so_data (so, zeta->pitch); } - so_method(so, curie, NV40TCL_RT_ENABLE, 1); + so_method(so, eng3d, NV40TCL_RT_ENABLE, 1); so_data (so, rt_enable); - so_method(so, curie, NV34TCL_RT_HORIZ, 3); + so_method(so, eng3d, NV34TCL_RT_HORIZ, 3); so_data (so, (w << 16) | 0); so_data (so, (h << 16) | 0); so_data (so, rt_format); - so_method(so, curie, NV34TCL_VIEWPORT_HORIZ, 2); + so_method(so, eng3d, NV34TCL_VIEWPORT_HORIZ, 2); so_data (so, (w << 16) | 0); so_data (so, (h << 16) | 0); - so_method(so, curie, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2); + so_method(so, eng3d, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2); so_data (so, ((w - 1) << 16) | 0); so_data (so, ((h - 1) << 16) | 0); - so_method(so, curie, 0x1d88, 1); + so_method(so, eng3d, 0x1d88, 1); so_data (so, (1 << 12) | h); so_ref(so, &nv40->state.hw[NV40_STATE_FB]); -- cgit v1.2.3