From da1928d4a6d48e915960798015ed1f0c1fa95f0c Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 5 Jan 2009 23:55:00 -0800 Subject: gallium-r300: Initial commit. Or should it be r300-gallium? Meh, whatever. --- src/gallium/drivers/r300/r300_context.c | 27 ++++++++ src/gallium/drivers/r300/r300_context.h | 4 ++ src/gallium/drivers/r300/r300_screen.c | 119 ++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_state.c | 22 ++++++ 4 files changed, 172 insertions(+) create mode 100644 src/gallium/drivers/r300/r300_context.c create mode 100644 src/gallium/drivers/r300/r300_context.h create mode 100644 src/gallium/drivers/r300/r300_screen.c create mode 100644 src/gallium/drivers/r300/r300_state.c (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c new file mode 100644 index 0000000000..a2ed0270cb --- /dev/null +++ b/src/gallium/drivers/r300/r300_context.c @@ -0,0 +1,27 @@ +#include "r300_context.h" + +static void r300_destroy_context(struct pipe_context* pipe) { + struct r300_context* context = r300_context(pipe); + + draw_destroy(context->draw); + + FREE(context); +} + +struct pipe_context* r300_create_context(struct pipe_screen* screen, + struct pipe_winsys* winsys, + struct amd_winsys* amd_winsys) +{ + struct r300_context* context = CALLOC_STRUCT(r300_context); + + if (!context) + return NULL; + + context->winsys = amd_winsys; + context->pipe.winsys = winsys; + context->pipe.screen = screen; + + context->pipe.destroy = r300_destroy_context; + + return &context->pipe; +} \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h new file mode 100644 index 0000000000..cd4b56c827 --- /dev/null +++ b/src/gallium/drivers/r300/r300_context.h @@ -0,0 +1,4 @@ +/* Convenience cast wrapper. */ +static struct r300_context* r300_context(struct pipe_context* pipe) { + return (struct r300_context*)pipe; +} \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c new file mode 100644 index 0000000000..a1f056b810 --- /dev/null +++ b/src/gallium/drivers/r300/r300_screen.c @@ -0,0 +1,119 @@ +/* XXX put a copyright here */ + +/* I know my style's weird, get used to it */ + +static const char* r300_get_vendor(struct pipe_screen* pscreen) { + return "X.Org R300 Project"; +} + +static const char* r300_get_name(struct pipe_screen* pscreen) { + /* XXX lazy */ + return "unknown"; +} + +static int r300_get_param(struct pipe_screen* pscreen, int param) { + switch (param) { + /* Cases marked "IN THEORY" are possible on the hardware, + * but haven't been implemented yet. */ + case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: + /* XXX I'm told this goes up to 16 */ + return 8; + case PIPE_CAP_NPOT_TEXTURES: + /* IN THEORY */ + return 0; + case PIPE_CAP_S3TC: + /* IN THEORY */ + return 0; + case PIPE_CAP_TWO_SIDED_STENCIL: + /* IN THEORY */ + return 0; + case PIPE_CAP_ANISOTROPIC_FILTER: + /* IN THEORY */ + return 0; + case PIPE_CAP_POINT_SPRITE: + /* IN THEORY */ + return 0; + case PIPE_CAP_OCCLUSION_QUERY: + /* IN THEORY */ + return 0; + case PIPE_CAP_TEXTURE_SHADOW_MAP: + /* IN THEORY */ + return 0; + case PIPE_CAP_GLSL: + /* IN THEORY */ + return 0; + case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: + /* 12 == 2048x2048 + * R500 can do 4096x4096 */ + return 12; + case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: + /* XXX educated guess */ + return 8; + case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: + /* XXX educated guess */ + return 11; + case PIPE_CAP_MAX_RENDER_TARGETS: + /* XXX 4 eventually */ + return 1; + default: + return 0; + } +} + +static float r300_get_paramf(struct pipe_screen* pscreen, float param) { + switch (param) { + case PIPE_CAP_MAX_LINE_WIDTH: + case PIPE_CAP_MAX_LINE_WIDTH_AA: + /* XXX look this up, lazy ass! */ + return 0.0; + case PIPE_CAP_MAX_POINT_WIDTH: + case PIPE_CAP_MAX_POINT_WIDTH_AA: + /* XXX see above */ + return 255.0; + case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: + return 16.0; + case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: + /* XXX again... */ + return 16.0; + default: + return 0.0; + } +} + +static boolean r300_is_format_supported(struct pipe_screen* pscreen, + enum pipe_format format, uint type) +{ + return FALSE; +} + +static r300_destroy_screen(struct pipe_screen* pscreen) { + FREE(pscreen); +} + +struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint pci_id) { + struct r300_screen* r300screen = CALLOC_STRUCT(r300_screen); + + if (!r300screen) + return NULL; + + /* XXX break this into its own function? */ + switch (pci_id) { + default: + debug_printf("%s: unknown PCI ID 0x%x, cannot create screen!\n", + __FUNCTION__, pci_id); + return NULL; + } + + r300screen->pci_id = pci_id; + r300screen->screen.winsys = winsys; + r300screen->screen.destroy = r300_destroy_screen; + r300screen->screen.get_name = r300_get_name; + r300screen->screen.get_vendor = r300_get_vendor; + r300screen->screen.get_param = r300_get_param; + r300screen->screen.get_paramf = r300_get_paramf; + r300screen->screen.is_format_supported = r300_is_format_supported; + r300screen->screen.surface_map = r300_surface_map; + r300screen->screen.surface_unmap = r300_surface_unmap; + + return &r300screen->screen; +} diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c new file mode 100644 index 0000000000..18b3d55752 --- /dev/null +++ b/src/gallium/drivers/r300/r300_state.c @@ -0,0 +1,22 @@ +#include "r300_context.h" + +static void* r300_create_vs_state(struct pipe_context* pipe, + struct pipe_shader_state* state) +{ + struct r300_context* context = r300_context(pipe); + /* XXX handing this off to Draw for now */ + return draw_create_vertex_shader(context->draw, state); +} + +static void r300_bind_vs_state(struct pipe_context* pipe, void* state) { + struct r300_context* context = r300_context(pipe); + /* XXX handing this off to Draw for now */ + draw_bind_vertex_shader(context->draw, (struct draw_vertex_shader*)state); +} + +static void r300_delete_vs_state(struct pipe_context* pipe, void* state) +{ + struct r300_context* context = r300_context(pipe); + /* XXX handing this off to Draw for now */ + draw_delete_vertex_shader(context->draw, (struct draw_vertex_shader*)state); +} \ No newline at end of file -- cgit v1.2.3 From aa96874c7abffa3fa9eef47ea36ab473ad2d2272 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 8 Jan 2009 14:41:29 -0800 Subject: gallium-r300: Add some headers. Oh yeah, we're cookin' now! --- src/gallium/drivers/r300/r300_context.h | 29 ++++++++++++++++++++++++++- src/gallium/drivers/r300/r300_screen.h | 35 +++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_state.h | 26 ++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 src/gallium/drivers/r300/r300_screen.h create mode 100644 src/gallium/drivers/r300/r300_state.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index cd4b56c827..28363fd36c 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -1,4 +1,31 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_CONTEXT_H +#define R300_CONTEXT_H + /* Convenience cast wrapper. */ static struct r300_context* r300_context(struct pipe_context* pipe) { return (struct r300_context*)pipe; -} \ No newline at end of file +} + +#endif /* R300_CONTEXT_H */ \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h new file mode 100644 index 0000000000..aa12c29a99 --- /dev/null +++ b/src/gallium/drivers/r300/r300_screen.h @@ -0,0 +1,35 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_SCREEN_H +#define R300_SCREEN_H + +struct r300_screen { + /* Parent class */ + struct pipe_screen screen; + + boolean is_r400; + boolean is_r500; + int pci_id; +} + +#endif /* R300_SCREEN_H */ diff --git a/src/gallium/drivers/r300/r300_state.h b/src/gallium/drivers/r300/r300_state.h new file mode 100644 index 0000000000..861425936a --- /dev/null +++ b/src/gallium/drivers/r300/r300_state.h @@ -0,0 +1,26 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_STATE_H +#define R300_STATE_H + +#endif /* R300_STATE_H */ \ No newline at end of file -- cgit v1.2.3 From 3e09a07a265d5ee75b110954d160a73d83793c40 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 8 Jan 2009 14:52:47 -0800 Subject: gallium-r300: Look less like i915. Todo: - Figure out how much code goes in winsys. - Make it build. - Make it suck less. --- src/gallium/drivers/r300/r300_context.c | 8 ++++---- src/gallium/drivers/r300/r300_context.h | 8 ++++++++ 2 files changed, 12 insertions(+), 4 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index a2ed0270cb..4aef5030fc 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -18,10 +18,10 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, return NULL; context->winsys = amd_winsys; - context->pipe.winsys = winsys; - context->pipe.screen = screen; + context->context.winsys = winsys; + context->context.screen = screen; - context->pipe.destroy = r300_destroy_context; + context->context.destroy = r300_destroy_context; - return &context->pipe; + return &context->context; } \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 28363fd36c..fd344361d9 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -23,6 +23,14 @@ #ifndef R300_CONTEXT_H #define R300_CONTEXT_H +struct r300_context { + /* Parent class */ + struct pipe_context context; + + struct amd_winsys* winsys; + struct draw_context* draw; +} + /* Convenience cast wrapper. */ static struct r300_context* r300_context(struct pipe_context* pipe) { return (struct r300_context*)pipe; -- cgit v1.2.3 From 3b37cb49b821dd0c59fd5361ada6c0df9ac07db8 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 8 Jan 2009 15:47:23 -0800 Subject: gallium-r300: Make it build. Still todo: - Sort out winsys. - Less suckage. --- src/gallium/drivers/r300/Makefile | 13 +++++++ src/gallium/drivers/r300/r300_context.c | 20 +++++----- src/gallium/drivers/r300/r300_context.h | 8 ++-- src/gallium/drivers/r300/r300_screen.c | 65 +++++++++++++++++++++++++++++---- src/gallium/drivers/r300/r300_screen.h | 13 +++++++ 5 files changed, 98 insertions(+), 21 deletions(-) create mode 100644 src/gallium/drivers/r300/Makefile (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile new file mode 100644 index 0000000000..b33e56f73d --- /dev/null +++ b/src/gallium/drivers/r300/Makefile @@ -0,0 +1,13 @@ +TOP = ../../../.. +include $(TOP)/configs/current + +LIBNAME = r300 + +C_SOURCES = \ + r300_context.c \ + r300_screen.c \ + r300_state.c + +include ../../Makefile.template + +symlinks: diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 4aef5030fc..569fdd3f0f 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -1,9 +1,9 @@ #include "r300_context.h" -static void r300_destroy_context(struct pipe_context* pipe) { - struct r300_context* context = r300_context(pipe); +static void r300_destroy_context(struct pipe_context* context) { + struct r300_context* r300 = r300_context(context); - draw_destroy(context->draw); + draw_destroy(r300->draw); FREE(context); } @@ -12,16 +12,16 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, struct pipe_winsys* winsys, struct amd_winsys* amd_winsys) { - struct r300_context* context = CALLOC_STRUCT(r300_context); + struct r300_context* r300 = CALLOC_STRUCT(r300_context); - if (!context) + if (!r300) return NULL; - context->winsys = amd_winsys; - context->context.winsys = winsys; - context->context.screen = screen; + r300->winsys = amd_winsys; + r300->context.winsys = winsys; + r300->context.screen = screen; - context->context.destroy = r300_destroy_context; + r300->context.destroy = r300_destroy_context; - return &context->context; + return &r300->context; } \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index fd344361d9..7c2055e43e 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -23,17 +23,19 @@ #ifndef R300_CONTEXT_H #define R300_CONTEXT_H +#include "pipe/p_context.h" + struct r300_context { /* Parent class */ struct pipe_context context; struct amd_winsys* winsys; struct draw_context* draw; -} +}; /* Convenience cast wrapper. */ -static struct r300_context* r300_context(struct pipe_context* pipe) { - return (struct r300_context*)pipe; +static struct r300_context* r300_context(struct pipe_context* context) { + return (struct r300_context*)context; } #endif /* R300_CONTEXT_H */ \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index a1f056b810..9c89623df3 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -1,6 +1,26 @@ -/* XXX put a copyright here */ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ -/* I know my style's weird, get used to it */ +#include "r300_screen.h" static const char* r300_get_vendor(struct pipe_screen* pscreen) { return "X.Org R300 Project"; @@ -12,6 +32,8 @@ static const char* r300_get_name(struct pipe_screen* pscreen) { } static int r300_get_param(struct pipe_screen* pscreen, int param) { + struct r300_screen* r300screen = r300_screen(pscreen); + switch (param) { /* Cases marked "IN THEORY" are possible on the hardware, * but haven't been implemented yet. */ @@ -43,9 +65,13 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) { /* IN THEORY */ return 0; case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: - /* 12 == 2048x2048 - * R500 can do 4096x4096 */ - return 12; + /* 12 == 2048x2048 */ + if (r300screen->is_r500) { + /* R500 can do 4096x4096 */ + return 13; + } else { + return 12; + } case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* XXX educated guess */ return 8; @@ -60,7 +86,7 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) { } } -static float r300_get_paramf(struct pipe_screen* pscreen, float param) { +static float r300_get_paramf(struct pipe_screen* pscreen, int param) { switch (param) { case PIPE_CAP_MAX_LINE_WIDTH: case PIPE_CAP_MAX_LINE_WIDTH_AA: @@ -81,12 +107,35 @@ static float r300_get_paramf(struct pipe_screen* pscreen, float param) { } static boolean r300_is_format_supported(struct pipe_screen* pscreen, - enum pipe_format format, uint type) + enum pipe_format format, + enum pipe_texture_target target, + unsigned tex_usage, + unsigned geom_flags) { return FALSE; } -static r300_destroy_screen(struct pipe_screen* pscreen) { +static void* r300_surface_map(struct pipe_screen* screen, + struct pipe_surface* surface, + unsigned flags) +{ + /* XXX is this all we need to do here? */ + char* map = pipe_buffer_map(screen, surface->buffer, flags); + + if (!map) { + return NULL; + } + + return map + surface->offset; +} + +static void r300_surface_unmap(struct pipe_screen* screen, + struct pipe_surface* surface) +{ + pipe_buffer_unmap(screen, surface->buffer); +} + +static void r300_destroy_screen(struct pipe_screen* pscreen) { FREE(pscreen); } diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index aa12c29a99..36fc5aa67d 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -23,6 +23,11 @@ #ifndef R300_SCREEN_H #define R300_SCREEN_H +#include "pipe/p_screen.h" +#include "util/u_memory.h" + +#include "r300_context.h" + struct r300_screen { /* Parent class */ struct pipe_screen screen; @@ -30,6 +35,14 @@ struct r300_screen { boolean is_r400; boolean is_r500; int pci_id; +}; + +/* Convenience cast wrapper. */ +static struct r300_screen* r300_screen(struct pipe_screen* screen) { + return (struct r300_screen*)screen; } +/* Creates a new r300 screen. */ +struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint pci_id); + #endif /* R300_SCREEN_H */ -- cgit v1.2.3 From 62363723001a63b86b7526d6528c19996a44463b Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 8 Jan 2009 16:33:29 -0800 Subject: gallium-r300: Add r300_clear. Todo: - Less suckage. - Re-read bo-cs stuff, figure out how the hell to emit state. - Blits. --- src/gallium/drivers/r300/Makefile | 1 + src/gallium/drivers/r300/r300_clear.c | 29 +++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_clear.h | 23 +++++++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 src/gallium/drivers/r300/r300_clear.c create mode 100644 src/gallium/drivers/r300/r300_clear.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index b33e56f73d..918eb8e1c4 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -4,6 +4,7 @@ include $(TOP)/configs/current LIBNAME = r300 C_SOURCES = \ + r300_clear.c \ r300_context.c \ r300_screen.c \ r300_state.c diff --git a/src/gallium/drivers/r300/r300_clear.c b/src/gallium/drivers/r300/r300_clear.c new file mode 100644 index 0000000000..f8f0e61931 --- /dev/null +++ b/src/gallium/drivers/r300/r300_clear.c @@ -0,0 +1,29 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* This gets its own file because Intel's is in its own file. + * I assume there's a good reason. */ +void r300_clear(struct pipe_context* pipe, struct pipe_surface* ps, unsigned val) +{ + pipe->surface_fill(pipe, ps, 0, 0, ps->width, ps->height, clearValue); + ps->status = PIPE_SURFACE_STATUS_DEFINED; +} \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_clear.h b/src/gallium/drivers/r300/r300_clear.h new file mode 100644 index 0000000000..58ac0a875c --- /dev/null +++ b/src/gallium/drivers/r300/r300_clear.h @@ -0,0 +1,23 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +void r300_clear(struct pipe_context* pipe, struct pipe_surface* ps, unsigned val); \ No newline at end of file -- cgit v1.2.3 From fb11fb897c2dc8cde64c84962d40e5fa6f384307 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 02:32:53 -0800 Subject: gallium-r300: Add copyrights, place (broken) CS. Todo: - Fill blits. - Less suck. - Ask glisse about how to get winsys+pipe talking right, so stuff like the CS can be set up right. --- src/gallium/drivers/r300/r300_context.c | 27 +++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_context.h | 7 +++++++ src/gallium/drivers/r300/r300_state.c | 22 ++++++++++++++++++++++ 3 files changed, 56 insertions(+) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 569fdd3f0f..7fde1404d9 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -1,3 +1,25 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + #include "r300_context.h" static void r300_destroy_context(struct pipe_context* context) { @@ -23,5 +45,10 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->context.destroy = r300_destroy_context; + /* XXX this is almost certainly wrong + * put this all in winsys, where we can get an FD + struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); + r300->cs = cs_gem_create(csm, 64 * 1024 / 4); */ + return &r300->context; } \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 7c2055e43e..f67823aa1e 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -31,6 +31,13 @@ struct r300_context { struct amd_winsys* winsys; struct draw_context* draw; + + /* CS object. This is very much like Intel's batchbuffer. + * Fill it full of dwords and relocs and then submit. + * Repeat as needed. */ + /* Note: Unlike Mesa's version of this, we don't keep a copy of the CSM + * that was used to create this CS. Is this a good idea? */ + struct radeon_cs* cs; }; /* Convenience cast wrapper. */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 18b3d55752..a853507fea 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -1,3 +1,25 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + #include "r300_context.h" static void* r300_create_vs_state(struct pipe_context* pipe, -- cgit v1.2.3 From d6cdb9db259d617ee21f1881c945e2ebaf6693b9 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 04:34:56 -0800 Subject: gallium-r300: Add r300_blit. Count the XXXs and weep? --- src/gallium/drivers/r300/r300_blit.c | 90 ++++++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_blit.h | 35 ++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 src/gallium/drivers/r300/r300_blit.c create mode 100644 src/gallium/drivers/r300/r300_blit.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c new file mode 100644 index 0000000000..c01855defa --- /dev/null +++ b/src/gallium/drivers/r300/r300_blit.c @@ -0,0 +1,90 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* Does a "paint" into the specified rectangle. + * Returns 1 on success, 0 on error. */ +int r300_fill_blit(struct r300_context* r300, + unsigned cpp, + short dst_pitch, + struct pipe_buffer* dst_buffer, + unsigned dst_offset, + short x, short y, + short w, short h, + unsigned color) +{ + uint32_t dest_type; + + /* Check for fallbacks. */ + /* XXX we can do YUV surfaces, too, but only in 3D mode. Hmm... */ + switch(cpp) { + case 2: + case 6: + dest_type = ATI_DATATYPE_CI8; + break; + case 4: + dest_type = ATI_DATATYPE_RGB565; + break; + case 8: + dest_type = ATI_DATATYPE_ARGB8888; + break; + default: + /* Whatever this is, we can't fill it. (Yet.) */ + return 0; + } + + /* XXX odds are *incredibly* good that we were in 3D just a bit ago, + * so flush here first. */ + + /* Set up the 2D engine. */ + OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, + RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); + /* XXX I have no idea what these flags mean, is this awesome? (y/n) */ + OUT_CS_REG(RADEON_DP_GUI_MASTER_CNTL, + RADEON_GMC_DST_PITCH_OFFSET_CNTL | + RADEON_GMC_BRUSH_SOLID_COLOR | + (dest_type << 8) | + RADEON_GMC_SRC_DATATYPE_COLOR | + /* XXX is this the right rop? */ + RADEON_ROP3_ONE | + RADEON_GMC_CLR_CMP_CNTL_DIS); + /* XXX pack this? */ + OUT_CS_REG(RADEON_DP_BRUSH_FRGD_CLR, color); + OUT_CS_REG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000); + OUT_CS_REG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); + OUT_CS_REG(RADEON_DP_SRC_BKGD_CLR, 0x00000000); + /* XXX what should this be? */ + OUT_CS_REG(RADEON_DP_WRITE_MASK, 0x00000000); + OUT_CS_REG(RADEON_DP_CNTL, + RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM); + OUT_CS_REG(RADEON_DST_PITCH_OFFSET, 0x0); + /* XXX fix this shit -> OUT_RELOC(dst, 0, RADEON_GEM_DOMAIN_VRAM) */ + + /* Do the actual paint. */ + OUT_CS_REG(RADEON_DST_Y_X, (y << 16) | x); + OUT_CS_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); + + /* Let the 2D engine settle. */ + OUT_CS_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); + OUT_CS_REG(RADEON_WAIT_UNTIL, + RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + return 1; +} diff --git a/src/gallium/drivers/r300/r300_blit.h b/src/gallium/drivers/r300/r300_blit.h new file mode 100644 index 0000000000..ac916ca062 --- /dev/null +++ b/src/gallium/drivers/r300/r300_blit.h @@ -0,0 +1,35 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_BLIT_H +#define R300_BLIT_H + +extern int r300_fill_blit(struct r300_context* r300, + unsigned cpp, + short dst_pitch, + struct pipe_buffer *dst_buffer, + unsigned dst_offset, + short x, short y, + short w, short h, + unsigned color); + +#endif /* R300_BLIT_H */ \ No newline at end of file -- cgit v1.2.3 From b1776eb14471e7a4d09d3c8a73f02b19b106883b Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 04:48:30 -0800 Subject: gallium-r300: Add r300_surface. Todo: - Hook up surface functions. - Take it for a spin and watch it crash 'n' burn. --- src/gallium/drivers/r300/r300_surface.c | 53 +++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_surface.h | 28 +++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 src/gallium/drivers/r300/r300_surface.c create mode 100644 src/gallium/drivers/r300/r300_surface.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c new file mode 100644 index 0000000000..4aa469b97e --- /dev/null +++ b/src/gallium/drivers/r300/r300_surface.c @@ -0,0 +1,53 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "r300_surface.h" + +/* Provides pipe_context's "surface_fill". */ +static void r300_surface_fill(struct pipe_context* context, + struct pipe_surface* dest, + unsigned x, unsigned y, + unsigned w, unsigned h, + unsigned color) +{ + /* Try accelerated fill first. */ + if (!r300_fill_blit(r300_context(context), + dest->block.size, + (short)dest->stride, + dest->buffer, + dest->offset, + (short)x, (short)y, + (short)w, (short)h, + color)) + { + /* Fallback. */ + void* dest_map = context->screen->surface_map(context->screen, dest, + PIPE_BUFFER_USAGE_CPU_WRITE); + pipe_fill_rect(dest_map, &dest->block, dest->stride, x, y, w, h, color); + context->screen->surface_unmap(context->screen, dest); + } +} + +void r300_init_surface_functions(struct r300_context* r300) +{ + r300->context.surface_fill = r300_surface_fill; +} diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h new file mode 100644 index 0000000000..3e3d813d99 --- /dev/null +++ b/src/gallium/drivers/r300/r300_surface.h @@ -0,0 +1,28 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_SURFACE_H +#define R300_SURFACE_H + +#include "r300_blit.h" + +#endif /* R300_SURFACE_H */ -- cgit v1.2.3 From afe2de0a235f8e4312ecbb7275640502098a8a81 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 05:11:19 -0800 Subject: gallium-r300: Fit it all together now. In theory, it could work, but there's still some very big gaps. Anything marked with XXX should be taken care of first, probably. --- src/gallium/drivers/r300/Makefile | 4 +++- src/gallium/drivers/r300/r300_blit.c | 2 ++ src/gallium/drivers/r300/r300_blit.h | 9 ++++++++- src/gallium/drivers/r300/r300_clear.c | 8 ++++++-- src/gallium/drivers/r300/r300_clear.h | 6 +++++- src/gallium/drivers/r300/r300_context.c | 4 +++- src/gallium/drivers/r300/r300_context.h | 2 ++ src/gallium/drivers/r300/r300_screen.c | 2 +- src/gallium/drivers/r300/r300_surface.h | 8 ++++++++ 9 files changed, 38 insertions(+), 7 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index 918eb8e1c4..bce7dcbf3a 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -4,10 +4,12 @@ include $(TOP)/configs/current LIBNAME = r300 C_SOURCES = \ + r300_blit.c \ r300_clear.c \ r300_context.c \ r300_screen.c \ - r300_state.c + r300_state.c \ + r300_surface.c include ../../Makefile.template diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index c01855defa..5f5eba90c1 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -20,6 +20,8 @@ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. */ +#include "r300_blit.h" + /* Does a "paint" into the specified rectangle. * Returns 1 on success, 0 on error. */ int r300_fill_blit(struct r300_context* r300, diff --git a/src/gallium/drivers/r300/r300_blit.h b/src/gallium/drivers/r300/r300_blit.h index ac916ca062..698b00083a 100644 --- a/src/gallium/drivers/r300/r300_blit.h +++ b/src/gallium/drivers/r300/r300_blit.h @@ -23,10 +23,17 @@ #ifndef R300_BLIT_H #define R300_BLIT_H +#include "pipe/p_state.h" + +#include "radeon_reg.h" + +/* Forward declarations. */ +struct r300_context; + extern int r300_fill_blit(struct r300_context* r300, unsigned cpp, short dst_pitch, - struct pipe_buffer *dst_buffer, + struct pipe_buffer* dst_buffer, unsigned dst_offset, short x, short y, short w, short h, diff --git a/src/gallium/drivers/r300/r300_clear.c b/src/gallium/drivers/r300/r300_clear.c index f8f0e61931..fd28437aaa 100644 --- a/src/gallium/drivers/r300/r300_clear.c +++ b/src/gallium/drivers/r300/r300_clear.c @@ -20,10 +20,14 @@ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. */ +#include "r300_clear.h" + /* This gets its own file because Intel's is in its own file. * I assume there's a good reason. */ -void r300_clear(struct pipe_context* pipe, struct pipe_surface* ps, unsigned val) +void r300_clear(struct pipe_context* pipe, + struct pipe_surface* ps, + unsigned color) { - pipe->surface_fill(pipe, ps, 0, 0, ps->width, ps->height, clearValue); + pipe->surface_fill(pipe, ps, 0, 0, ps->width, ps->height, color); ps->status = PIPE_SURFACE_STATUS_DEFINED; } \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_clear.h b/src/gallium/drivers/r300/r300_clear.h index 58ac0a875c..e24a0690c9 100644 --- a/src/gallium/drivers/r300/r300_clear.h +++ b/src/gallium/drivers/r300/r300_clear.h @@ -20,4 +20,8 @@ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. */ -void r300_clear(struct pipe_context* pipe, struct pipe_surface* ps, unsigned val); \ No newline at end of file +#include "pipe/p_context.h" + +void r300_clear(struct pipe_context* pipe, + struct pipe_surface* ps, + unsigned color); diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 7fde1404d9..21bee5beae 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -50,5 +50,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); r300->cs = cs_gem_create(csm, 64 * 1024 / 4); */ + r300_init_surface_functions(r300); + return &r300->context; -} \ No newline at end of file +} diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index f67823aa1e..ae2dab13ff 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -25,6 +25,8 @@ #include "pipe/p_context.h" +#include "r300_surface.h" + struct r300_context { /* Parent class */ struct pipe_context context; diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 9c89623df3..0a114bbc06 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -119,7 +119,7 @@ static void* r300_surface_map(struct pipe_screen* screen, struct pipe_surface* surface, unsigned flags) { - /* XXX is this all we need to do here? */ + /* XXX this is not quite right */ char* map = pipe_buffer_map(screen, surface->buffer, flags); if (!map) { diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index 3e3d813d99..29858eb541 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -23,6 +23,14 @@ #ifndef R300_SURFACE_H #define R300_SURFACE_H +#include "pipe/p_context.h" +#include "pipe/p_screen.h" + +#include "util/u_rect.h" + #include "r300_blit.h" +#include "r300_context.h" + +void r300_init_surface_functions(struct r300_context* r300); #endif /* R300_SURFACE_H */ -- cgit v1.2.3 From 32273c01bd9291dcc23ca2635b848586458a3c81 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 06:05:36 -0800 Subject: gallium-r300: Set right ROP for solid fills. Thanks to MrCooper for pointing me in the right direction. --- src/gallium/drivers/r300/r300_blit.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index 5f5eba90c1..415e6e0a16 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -59,14 +59,12 @@ int r300_fill_blit(struct r300_context* r300, /* Set up the 2D engine. */ OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); - /* XXX I have no idea what these flags mean, is this awesome? (y/n) */ OUT_CS_REG(RADEON_DP_GUI_MASTER_CNTL, RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_BRUSH_SOLID_COLOR | (dest_type << 8) | RADEON_GMC_SRC_DATATYPE_COLOR | - /* XXX is this the right rop? */ - RADEON_ROP3_ONE | + RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS); /* XXX pack this? */ OUT_CS_REG(RADEON_DP_BRUSH_FRGD_CLR, color); -- cgit v1.2.3 From ad14271425185c3535c389ca5bcd2d30c3368c32 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 13:08:19 -0800 Subject: gallium-r300: Max LOD bias is 16.0. --- src/gallium/drivers/r300/r300_screen.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 0a114bbc06..37a74b3c0a 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -99,7 +99,6 @@ static float r300_get_paramf(struct pipe_screen* pscreen, int param) { case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: return 16.0; case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: - /* XXX again... */ return 16.0; default: return 0.0; -- cgit v1.2.3 From 78b599fb4cac469f4208ae3057b2a33e3e9913c6 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 14:54:08 -0800 Subject: gallium-r300: Add primitive CS. Enough to get us up and running, I suppose. This needs to be pushed down into winsys! --- src/gallium/drivers/r300/r300_blit.c | 6 ++++ src/gallium/drivers/r300/r300_blit.h | 2 +- src/gallium/drivers/r300/r300_cs.h | 70 ++++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 src/gallium/drivers/r300/r300_cs.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index 415e6e0a16..c404a667b1 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -33,6 +33,7 @@ int r300_fill_blit(struct r300_context* r300, short w, short h, unsigned color) { + CS_LOCALS(r300); uint32_t dest_type; /* Check for fallbacks. */ @@ -56,6 +57,8 @@ int r300_fill_blit(struct r300_context* r300, /* XXX odds are *incredibly* good that we were in 3D just a bit ago, * so flush here first. */ + BEGIN_CS(10 + 2 + 2); + /* Set up the 2D engine. */ OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); @@ -86,5 +89,8 @@ int r300_fill_blit(struct r300_context* r300, OUT_CS_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); OUT_CS_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); + + END_CS; + return 1; } diff --git a/src/gallium/drivers/r300/r300_blit.h b/src/gallium/drivers/r300/r300_blit.h index 698b00083a..09cb566b95 100644 --- a/src/gallium/drivers/r300/r300_blit.h +++ b/src/gallium/drivers/r300/r300_blit.h @@ -25,7 +25,7 @@ #include "pipe/p_state.h" -#include "radeon_reg.h" +#include "r300_cs.h" /* Forward declarations. */ struct r300_context; diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h new file mode 100644 index 0000000000..ebd5324119 --- /dev/null +++ b/src/gallium/drivers/r300/r300_cs.h @@ -0,0 +1,70 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_CS_H +#define R300_CS_H + +#include "radeon_cs.h" +#include "radeon_reg.h" + +/* Yes, I know macros are ugly. However, they are much prettier than the code + * that they neatly hide away, and don't have the cost of function setup,so + * we're going to use them. */ + +#define MAX_CS_SIZE 64 * 1024 / 4 + +#define CP_PACKET0(register, count) \ + (RADEON_CP_PACKET0 | ((count) << 16) | ((register) >> 2)) + +#define CS_LOCALS(context) \ + struct radeon_cs* cs = context->cs + + +#define CHECK_CS(size) do { \ + if ((cs->cdw + (size) + 128) > MAX_CS_SIZE || radeon_cs_need_flush(cs)) { \ + /* XXX flush the CS */ \ + } } while (0) + +/* XXX radeon_cs_begin is currently unimplemented on the backend, but let's + * be future-proof, yeah? */ +#define BEGIN_CS(size) do { \ + CHECK_CS(size); \ + radeon_cs_begin(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ +} while (0) + +#define OUT_CS(value) \ + radeon_cs_write_dword(cs, value) + +#define OUT_CS_REG(register, value) do { \ + OUT_CS(CP_PACKET0(register, 0)); \ + OUT_CS(value); } while (0) + +#define OUT_CS_RELOC(bo, offset, rd, wd, flags) do { \ + radeon_cs_write_dword(cs, offset); \ + radeon_cs_write_reloc(cs, bo, rd, wd, flags); \ +} while (0) + +/* XXX more future-proofing */ +#define END_CS \ + radeon_cs_end(cs, __FILE__, __FUNCTION__, __LINE__) + +#endif /* R300_CS_H */ \ No newline at end of file -- cgit v1.2.3 From adb74f5c5262d22b3c60a555431c29d36e3170f7 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 18:57:02 -0800 Subject: r300: Hook up to winsys, add missing header. In theory it works, which of course means that it doesn't. --- src/gallium/drivers/r300/r300_context.c | 9 +- src/gallium/drivers/r300/radeon_reg.h | 5324 ++++++++++++++++++++++++++++++ src/gallium/winsys/drm/amd/amd_context.c | 8 +- 3 files changed, 5339 insertions(+), 2 deletions(-) create mode 100644 src/gallium/drivers/r300/radeon_reg.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 21bee5beae..68751dae17 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -41,10 +41,17 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->winsys = amd_winsys; r300->context.winsys = winsys; - r300->context.screen = screen; + if (screen) { + r300->context.screen = screen; + } else { + /* XXX second arg should be pciid, find a way to get it from winsys */ + r300->context.screen = r300_create_screen(winsys, 0x0); + } r300->context.destroy = r300_destroy_context; + r300->draw = draw_create(); + /* XXX this is almost certainly wrong * put this all in winsys, where we can get an FD struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); diff --git a/src/gallium/drivers/r300/radeon_reg.h b/src/gallium/drivers/r300/radeon_reg.h new file mode 100644 index 0000000000..e2fcb70a95 --- /dev/null +++ b/src/gallium/drivers/r300/radeon_reg.h @@ -0,0 +1,5324 @@ +/* + * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and + * VA Linux Systems Inc., Fremont, California. + * + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation on the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR + * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* + * Authors: + * Kevin E. Martin + * Rickard E. Faith + * Alan Hourihane + * + * References: + * + * !!!! FIXME !!!! + * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical + * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April + * 1999. + * + * !!!! FIXME !!!! + * RAGE 128 Software Development Manual (Technical Reference Manual P/N + * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. + * + */ + +/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h + * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT + * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ + +/* XXX clean this bitch up */ + +#ifndef _RADEON_REG_H_ +#define _RADEON_REG_H_ + +#define ATI_DATATYPE_VQ 0 +#define ATI_DATATYPE_CI4 1 +#define ATI_DATATYPE_CI8 2 +#define ATI_DATATYPE_ARGB1555 3 +#define ATI_DATATYPE_RGB565 4 +#define ATI_DATATYPE_RGB888 5 +#define ATI_DATATYPE_ARGB8888 6 +#define ATI_DATATYPE_RGB332 7 +#define ATI_DATATYPE_Y8 8 +#define ATI_DATATYPE_RGB8 9 +#define ATI_DATATYPE_CI16 10 +#define ATI_DATATYPE_VYUY_422 11 +#define ATI_DATATYPE_YVYU_422 12 +#define ATI_DATATYPE_AYUV_444 14 +#define ATI_DATATYPE_ARGB4444 15 + + /* Registers for 2D/Video/Overlay */ +#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ +#define RADEON_AGP_BASE 0x0170 +#define RADEON_AGP_CNTL 0x0174 +# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) +# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) +# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) +# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) +# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) +# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) +# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) +# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) +#define RADEON_STATUS_PCI_CONFIG 0x06 +# define RADEON_CAP_LIST 0x100000 +#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ +# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ +# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ +# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ +# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ +#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ +#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ +# define RADEON_AGP_ENABLE (1<<8) +#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ +#define RADEON_AGP_STATUS 0x0f5c /* PCI */ +# define RADEON_AGP_1X_MODE 0x01 +# define RADEON_AGP_2X_MODE 0x02 +# define RADEON_AGP_4X_MODE 0x04 +# define RADEON_AGP_FW_MODE 0x10 +# define RADEON_AGP_MODE_MASK 0x17 +# define RADEON_AGPv3_MODE 0x08 +# define RADEON_AGPv3_4X_MODE 0x01 +# define RADEON_AGPv3_8X_MODE 0x02 +#define RADEON_ATTRDR 0x03c1 /* VGA */ +#define RADEON_ATTRDW 0x03c0 /* VGA */ +#define RADEON_ATTRX 0x03c0 /* VGA */ +#define RADEON_AUX_SC_CNTL 0x1660 +# define RADEON_AUX1_SC_EN (1 << 0) +# define RADEON_AUX1_SC_MODE_OR (0 << 1) +# define RADEON_AUX1_SC_MODE_NAND (1 << 1) +# define RADEON_AUX2_SC_EN (1 << 2) +# define RADEON_AUX2_SC_MODE_OR (0 << 3) +# define RADEON_AUX2_SC_MODE_NAND (1 << 3) +# define RADEON_AUX3_SC_EN (1 << 4) +# define RADEON_AUX3_SC_MODE_OR (0 << 5) +# define RADEON_AUX3_SC_MODE_NAND (1 << 5) +#define RADEON_AUX1_SC_BOTTOM 0x1670 +#define RADEON_AUX1_SC_LEFT 0x1664 +#define RADEON_AUX1_SC_RIGHT 0x1668 +#define RADEON_AUX1_SC_TOP 0x166c +#define RADEON_AUX2_SC_BOTTOM 0x1680 +#define RADEON_AUX2_SC_LEFT 0x1674 +#define RADEON_AUX2_SC_RIGHT 0x1678 +#define RADEON_AUX2_SC_TOP 0x167c +#define RADEON_AUX3_SC_BOTTOM 0x1690 +#define RADEON_AUX3_SC_LEFT 0x1684 +#define RADEON_AUX3_SC_RIGHT 0x1688 +#define RADEON_AUX3_SC_TOP 0x168c +#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 +#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc + +#define RADEON_BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +# define RADEON_FP_PANEL_SCALABLE (1 << 16) +# define RADEON_FP_PANEL_SCALE_EN (1 << 17) +# define RADEON_FP_CHIP_SCALE_EN (1 << 18) +# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) +# define RADEON_DISPLAY_ROT_MASK (3 << 28) +# define RADEON_DISPLAY_ROT_00 (0 << 28) +# define RADEON_DISPLAY_ROT_90 (1 << 28) +# define RADEON_DISPLAY_ROT_180 (2 << 28) +# define RADEON_DISPLAY_ROT_270 (3 << 28) +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +# define RADEON_CRT1_ATTACHED_MASK (3 << 0) +# define RADEON_CRT1_ATTACHED_MONO (1 << 0) +# define RADEON_CRT1_ATTACHED_COLOR (2 << 0) +# define RADEON_LCD1_ATTACHED (1 << 2) +# define RADEON_DFP1_ATTACHED (1 << 3) +# define RADEON_TV1_ATTACHED_MASK (3 << 4) +# define RADEON_TV1_ATTACHED_COMP (1 << 4) +# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) +# define RADEON_CRT2_ATTACHED_MASK (3 << 8) +# define RADEON_CRT2_ATTACHED_MONO (1 << 8) +# define RADEON_CRT2_ATTACHED_COLOR (2 << 8) +# define RADEON_DFP2_ATTACHED (1 << 11) +#define RADEON_BIOS_5_SCRATCH 0x0024 +# define RADEON_LCD1_ON (1 << 0) +# define RADEON_CRT1_ON (1 << 1) +# define RADEON_TV1_ON (1 << 2) +# define RADEON_DFP1_ON (1 << 3) +# define RADEON_CRT2_ON (1 << 5) +# define RADEON_CV1_ON (1 << 6) +# define RADEON_DFP2_ON (1 << 7) +# define RADEON_LCD1_CRTC_MASK (1 << 8) +# define RADEON_LCD1_CRTC_SHIFT 8 +# define RADEON_CRT1_CRTC_MASK (1 << 9) +# define RADEON_CRT1_CRTC_SHIFT 9 +# define RADEON_TV1_CRTC_MASK (1 << 10) +# define RADEON_TV1_CRTC_SHIFT 10 +# define RADEON_DFP1_CRTC_MASK (1 << 11) +# define RADEON_DFP1_CRTC_SHIFT 11 +# define RADEON_CRT2_CRTC_MASK (1 << 12) +# define RADEON_CRT2_CRTC_SHIFT 12 +# define RADEON_CV1_CRTC_MASK (1 << 13) +# define RADEON_CV1_CRTC_SHIFT 13 +# define RADEON_DFP2_CRTC_MASK (1 << 14) +# define RADEON_DFP2_CRTC_SHIFT 14 +#define RADEON_BIOS_6_SCRATCH 0x0028 +# define RADEON_ACC_MODE_CHANGE (1 << 2) +# define RADEON_EXT_DESKTOP_MODE (1 << 3) +# define RADEON_LCD_DPMS_ON (1 << 20) +# define RADEON_CRT_DPMS_ON (1 << 21) +# define RADEON_TV_DPMS_ON (1 << 22) +# define RADEON_DFP_DPMS_ON (1 << 23) +# define RADEON_DPMS_MASK (3 << 24) +# define RADEON_DPMS_ON (0 << 24) +# define RADEON_DPMS_STANDBY (1 << 24) +# define RADEON_DPMS_SUSPEND (2 << 24) +# define RADEON_DPMS_OFF (3 << 24) +# define RADEON_SCREEN_BLANKING (1 << 26) +# define RADEON_DRIVER_CRITICAL (1 << 27) +# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) +#define RADEON_BIOS_7_SCRATCH 0x002c +# define RADEON_SYS_HOTKEY (1 << 10) +# define RADEON_DRV_LOADED (1 << 12) +#define RADEON_BIOS_ROM 0x0f30 /* PCI */ +#define RADEON_BIST 0x0f0f /* PCI */ +#define RADEON_BRUSH_DATA0 0x1480 +#define RADEON_BRUSH_DATA1 0x1484 +#define RADEON_BRUSH_DATA10 0x14a8 +#define RADEON_BRUSH_DATA11 0x14ac +#define RADEON_BRUSH_DATA12 0x14b0 +#define RADEON_BRUSH_DATA13 0x14b4 +#define RADEON_BRUSH_DATA14 0x14b8 +#define RADEON_BRUSH_DATA15 0x14bc +#define RADEON_BRUSH_DATA16 0x14c0 +#define RADEON_BRUSH_DATA17 0x14c4 +#define RADEON_BRUSH_DATA18 0x14c8 +#define RADEON_BRUSH_DATA19 0x14cc +#define RADEON_BRUSH_DATA2 0x1488 +#define RADEON_BRUSH_DATA20 0x14d0 +#define RADEON_BRUSH_DATA21 0x14d4 +#define RADEON_BRUSH_DATA22 0x14d8 +#define RADEON_BRUSH_DATA23 0x14dc +#define RADEON_BRUSH_DATA24 0x14e0 +#define RADEON_BRUSH_DATA25 0x14e4 +#define RADEON_BRUSH_DATA26 0x14e8 +#define RADEON_BRUSH_DATA27 0x14ec +#define RADEON_BRUSH_DATA28 0x14f0 +#define RADEON_BRUSH_DATA29 0x14f4 +#define RADEON_BRUSH_DATA3 0x148c +#define RADEON_BRUSH_DATA30 0x14f8 +#define RADEON_BRUSH_DATA31 0x14fc +#define RADEON_BRUSH_DATA32 0x1500 +#define RADEON_BRUSH_DATA33 0x1504 +#define RADEON_BRUSH_DATA34 0x1508 +#define RADEON_BRUSH_DATA35 0x150c +#define RADEON_BRUSH_DATA36 0x1510 +#define RADEON_BRUSH_DATA37 0x1514 +#define RADEON_BRUSH_DATA38 0x1518 +#define RADEON_BRUSH_DATA39 0x151c +#define RADEON_BRUSH_DATA4 0x1490 +#define RADEON_BRUSH_DATA40 0x1520 +#define RADEON_BRUSH_DATA41 0x1524 +#define RADEON_BRUSH_DATA42 0x1528 +#define RADEON_BRUSH_DATA43 0x152c +#define RADEON_BRUSH_DATA44 0x1530 +#define RADEON_BRUSH_DATA45 0x1534 +#define RADEON_BRUSH_DATA46 0x1538 +#define RADEON_BRUSH_DATA47 0x153c +#define RADEON_BRUSH_DATA48 0x1540 +#define RADEON_BRUSH_DATA49 0x1544 +#define RADEON_BRUSH_DATA5 0x1494 +#define RADEON_BRUSH_DATA50 0x1548 +#define RADEON_BRUSH_DATA51 0x154c +#define RADEON_BRUSH_DATA52 0x1550 +#define RADEON_BRUSH_DATA53 0x1554 +#define RADEON_BRUSH_DATA54 0x1558 +#define RADEON_BRUSH_DATA55 0x155c +#define RADEON_BRUSH_DATA56 0x1560 +#define RADEON_BRUSH_DATA57 0x1564 +#define RADEON_BRUSH_DATA58 0x1568 +#define RADEON_BRUSH_DATA59 0x156c +#define RADEON_BRUSH_DATA6 0x1498 +#define RADEON_BRUSH_DATA60 0x1570 +#define RADEON_BRUSH_DATA61 0x1574 +#define RADEON_BRUSH_DATA62 0x1578 +#define RADEON_BRUSH_DATA63 0x157c +#define RADEON_BRUSH_DATA7 0x149c +#define RADEON_BRUSH_DATA8 0x14a0 +#define RADEON_BRUSH_DATA9 0x14a4 +#define RADEON_BRUSH_SCALE 0x1470 +#define RADEON_BRUSH_Y_X 0x1474 +#define RADEON_BUS_CNTL 0x0030 +# define RADEON_BUS_MASTER_DIS (1 << 6) +# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) +# define RADEON_BUS_RD_DISCARD_EN (1 << 24) +# define RADEON_BUS_RD_ABORT_EN (1 << 25) +# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) +# define RADEON_BUS_WRT_BURST (1 << 29) +# define RADEON_BUS_READ_BURST (1 << 30) +#define RADEON_BUS_CNTL1 0x0034 +# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) + +#define RADEON_CACHE_CNTL 0x1724 +#define RADEON_CACHE_LINE 0x0f0c /* PCI */ +#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ +#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ +#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ +# define RADEON_SCLK_DYN_START_CNTL (1 << 15) +#define RADEON_CLOCK_CNTL_DATA 0x000c +#define RADEON_CLOCK_CNTL_INDEX 0x0008 +# define RADEON_PLL_WR_EN (1 << 7) +# define RADEON_PLL_DIV_SEL (3 << 8) +# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) +#define RADEON_CLK_PWRMGT_CNTL 0x0014 +# define RADEON_ENGIN_DYNCLK_MODE (1 << 12) +# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) +# define RADEON_ACTIVE_HILO_LAT_SHIFT 13 +# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) +# define RADEON_MC_BUSY (1 << 16) +# define RADEON_DLL_READY (1 << 19) +# define RADEON_CG_NO1_DEBUG_0 (1 << 24) +# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) +# define RADEON_DYN_STOP_MODE_MASK (7 << 21) +# define RADEON_TVPLL_PWRMGT_OFF (1 << 30) +# define RADEON_TVCLK_TURNOFF (1 << 31) +#define RADEON_PLL_PWRMGT_CNTL 0x0015 +# define RADEON_TCL_BYPASS_DISABLE (1 << 20) +#define RADEON_CLR_CMP_CLR_3D 0x1a24 +#define RADEON_CLR_CMP_CLR_DST 0x15c8 +#define RADEON_CLR_CMP_CLR_SRC 0x15c4 +#define RADEON_CLR_CMP_CNTL 0x15c0 +# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) +# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) +# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) +#define RADEON_CLR_CMP_MASK 0x15cc +# define RADEON_CLR_CMP_MSK 0xffffffff +#define RADEON_CLR_CMP_MASK_3D 0x1A28 +#define RADEON_COMMAND 0x0f04 /* PCI */ +#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c +#define RADEON_CONFIG_APER_0_BASE 0x0100 +#define RADEON_CONFIG_APER_1_BASE 0x0104 +#define RADEON_CONFIG_APER_SIZE 0x0108 +#define RADEON_CONFIG_BONDS 0x00e8 +#define RADEON_CONFIG_CNTL 0x00e0 +# define RADEON_CFG_ATI_REV_A11 (0 << 16) +# define RADEON_CFG_ATI_REV_A12 (1 << 16) +# define RADEON_CFG_ATI_REV_A13 (2 << 16) +# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) +#define RADEON_CONFIG_MEMSIZE 0x00f8 +#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 +#define RADEON_CONFIG_REG_1_BASE 0x010c +#define RADEON_CONFIG_REG_APER_SIZE 0x0110 +#define RADEON_CONFIG_XSTRAP 0x00e4 +#define RADEON_CONSTANT_COLOR_C 0x1d34 +# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff +# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff +# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 +#define RADEON_CRC_CMDFIFO_ADDR 0x0740 +#define RADEON_CRC_CMDFIFO_DOUT 0x0744 +#define RADEON_GRPH_BUFFER_CNTL 0x02f0 +# define RADEON_GRPH_START_REQ_MASK (0x7f) +# define RADEON_GRPH_START_REQ_SHIFT 0 +# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH_STOP_REQ_SHIFT 8 +# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH_BUFFER_SIZE (1<<29) +# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH_STOP_CNTL (1<<31) +#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 +# define RADEON_GRPH2_START_REQ_MASK (0x7f) +# define RADEON_GRPH2_START_REQ_SHIFT 0 +# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) +# define RADEON_GRPH2_STOP_REQ_SHIFT 8 +# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) +# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 +# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) +# define RADEON_GRPH2_BUFFER_SIZE (1<<29) +# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) +# define RADEON_GRPH2_STOP_CNTL (1<<31) +#define RADEON_CRTC_CRNT_FRAME 0x0214 +#define RADEON_CRTC_EXT_CNTL 0x0054 +# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) +# define RADEON_VGA_ATI_LINEAR (1 << 3) +# define RADEON_XCRT_CNT_EN (1 << 6) +# define RADEON_CRTC_HSYNC_DIS (1 << 8) +# define RADEON_CRTC_VSYNC_DIS (1 << 9) +# define RADEON_CRTC_DISPLAY_DIS (1 << 10) +# define RADEON_CRTC_SYNC_TRISTAT (1 << 11) +# define RADEON_CRTC_CRT_ON (1 << 15) +#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) +# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) +# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RADEON_CRTC_GEN_CNTL 0x0050 +# define RADEON_CRTC_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC_INTERLACE_EN (1 << 1) +# define RADEON_CRTC_CSYNC_EN (1 << 4) +# define RADEON_CRTC_ICON_EN (1 << 15) +# define RADEON_CRTC_CUR_EN (1 << 16) +# define RADEON_CRTC_CUR_MODE_MASK (7 << 20) +# define RADEON_CRTC_EXT_DISP_EN (1 << 24) +# define RADEON_CRTC_EN (1 << 25) +# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) +#define RADEON_CRTC2_GEN_CNTL 0x03f8 +# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) +# define RADEON_CRTC2_INTERLACE_EN (1 << 1) +# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) +# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) +# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) +# define RADEON_CRTC2_CRT2_ON (1 << 7) +# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 +# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) +# define RADEON_CRTC2_ICON_EN (1 << 15) +# define RADEON_CRTC2_CUR_EN (1 << 16) +# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) +# define RADEON_CRTC2_DISP_DIS (1 << 23) +# define RADEON_CRTC2_EN (1 << 25) +# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) +# define RADEON_CRTC2_CSYNC_EN (1 << 27) +# define RADEON_CRTC2_HSYNC_DIS (1 << 28) +# define RADEON_CRTC2_VSYNC_DIS (1 << 29) +#define RADEON_CRTC_MORE_CNTL 0x27c +# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) +# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) +# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 +#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 +# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_H_SYNC_POL (1 << 23) +#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 +# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) +# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_H_SYNC_POL (1 << 23) +#define RADEON_CRTC_H_TOTAL_DISP 0x0200 +# define RADEON_CRTC_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC_H_TOTAL_SHIFT 0 +# define RADEON_CRTC_H_DISP (0x01ff << 16) +# define RADEON_CRTC_H_DISP_SHIFT 16 +#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 +# define RADEON_CRTC2_H_TOTAL (0x03ff << 0) +# define RADEON_CRTC2_H_TOTAL_SHIFT 0 +# define RADEON_CRTC2_H_DISP (0x01ff << 16) +# define RADEON_CRTC2_H_DISP_SHIFT 16 + +#define RADEON_CRTC_OFFSET_RIGHT 0x0220 +#define RADEON_CRTC_OFFSET 0x0224 +# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) +# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) + +#define RADEON_CRTC2_OFFSET 0x0324 +# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) +# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) +#define RADEON_CRTC_OFFSET_CNTL 0x0228 +# define RADEON_CRTC_TILE_LINE_SHIFT 0 +# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 +# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) +# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) +# define R300_CRTC_X_Y_MODE_EN (1 << 9) +# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) +# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) +# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) +# define R300_CRTC_MICRO_TILE_EN (1 << 13) +# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) +# define R300_CRTC_MACRO_TILE_EN (1 << 15) +# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) +# define RADEON_CRTC_TILE_EN (1 << 15) +# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) +# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) + +#define R300_CRTC_TILE_X0_Y0 0x0350 +#define R300_CRTC2_TILE_X0_Y0 0x0358 + +#define RADEON_CRTC2_OFFSET_CNTL 0x0328 +# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) +# define RADEON_CRTC2_TILE_EN (1 << 15) +#define RADEON_CRTC_PITCH 0x022c +# define RADEON_CRTC_PITCH__SHIFT 0 +# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 + +#define RADEON_CRTC2_PITCH 0x032c +#define RADEON_CRTC_STATUS 0x005c +# define RADEON_CRTC_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC2_STATUS 0x03fc +# define RADEON_CRTC2_VBLANK_SAVE (1 << 1) +# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) +#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c +# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC_V_SYNC_POL (1 << 23) +#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c +# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) +# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 +# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) +# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 +# define RADEON_CRTC2_V_SYNC_POL (1 << 23) +#define RADEON_CRTC_V_TOTAL_DISP 0x0208 +# define RADEON_CRTC_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC_V_TOTAL_SHIFT 0 +# define RADEON_CRTC_V_DISP (0x07ff << 16) +# define RADEON_CRTC_V_DISP_SHIFT 16 +#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 +# define RADEON_CRTC2_V_TOTAL (0x07ff << 0) +# define RADEON_CRTC2_V_TOTAL_SHIFT 0 +# define RADEON_CRTC2_V_DISP (0x07ff << 16) +# define RADEON_CRTC2_V_DISP_SHIFT 16 +#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 +# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define RADEON_CRTC2_CRNT_FRAME 0x0314 +#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 +#define RADEON_CRTC2_STATUS 0x03fc +#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 +#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ +#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ +#define RADEON_CUR_CLR0 0x026c +#define RADEON_CUR_CLR1 0x0270 +#define RADEON_CUR_HORZ_VERT_OFF 0x0268 +#define RADEON_CUR_HORZ_VERT_POSN 0x0264 +#define RADEON_CUR_OFFSET 0x0260 +# define RADEON_CUR_LOCK (1 << 31) +#define RADEON_CUR2_CLR0 0x036c +#define RADEON_CUR2_CLR1 0x0370 +#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 +#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 +#define RADEON_CUR2_OFFSET 0x0360 +# define RADEON_CUR2_LOCK (1 << 31) + +#define RADEON_DAC_CNTL 0x0058 +# define RADEON_DAC_RANGE_CNTL (3 << 0) +# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) +# define RADEON_DAC_RANGE_CNTL_MASK 0x03 +# define RADEON_DAC_BLANKING (1 << 2) +# define RADEON_DAC_CMP_EN (1 << 3) +# define RADEON_DAC_CMP_OUTPUT (1 << 7) +# define RADEON_DAC_8BIT_EN (1 << 8) +# define RADEON_DAC_TVO_EN (1 << 10) +# define RADEON_DAC_VGA_ADR_EN (1 << 13) +# define RADEON_DAC_PDWN (1 << 15) +# define RADEON_DAC_MASK_ALL (0xff << 24) +#define RADEON_DAC_CNTL2 0x007c +# define RADEON_DAC2_TV_CLK_SEL (0 << 1) +# define RADEON_DAC2_DAC_CLK_SEL (1 << 0) +# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) +# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) +# define RADEON_DAC2_CMP_EN (1 << 7) +# define RADEON_DAC2_CMP_OUT_R (1 << 8) +# define RADEON_DAC2_CMP_OUT_G (1 << 9) +# define RADEON_DAC2_CMP_OUT_B (1 << 10) +# define RADEON_DAC2_CMP_OUTPUT (1 << 11) +#define RADEON_DAC_EXT_CNTL 0x0280 +# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) +# define RADEON_DAC2_FORCE_DATA_EN (1 << 1) +# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) +# define RADEON_DAC_FORCE_DATA_EN (1 << 5) +# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) +# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) +# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 +# define RADEON_DAC_FORCE_DATA_SHIFT 8 +#define RADEON_DAC_MACRO_CNTL 0x0d04 +# define RADEON_DAC_PDWN_R (1 << 16) +# define RADEON_DAC_PDWN_G (1 << 17) +# define RADEON_DAC_PDWN_B (1 << 18) +#define RADEON_TV_DAC_CNTL 0x088c +# define RADEON_TV_DAC_NBLANK (1 << 0) +# define RADEON_TV_DAC_NHOLD (1 << 1) +# define RADEON_TV_DAC_PEDESTAL (1 << 2) +# define RADEON_TV_MONITOR_DETECT_EN (1 << 4) +# define RADEON_TV_DAC_CMPOUT (1 << 5) +# define RADEON_TV_DAC_STD_MASK (3 << 8) +# define RADEON_TV_DAC_STD_PAL (0 << 8) +# define RADEON_TV_DAC_STD_NTSC (1 << 8) +# define RADEON_TV_DAC_STD_PS2 (2 << 8) +# define RADEON_TV_DAC_STD_RS343 (3 << 8) +# define RADEON_TV_DAC_BGSLEEP (1 << 6) +# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) +# define RADEON_TV_DAC_BGADJ_SHIFT 16 +# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) +# define RADEON_TV_DAC_DACADJ_SHIFT 20 +# define RADEON_TV_DAC_RDACPD (1 << 24) +# define RADEON_TV_DAC_GDACPD (1 << 25) +# define RADEON_TV_DAC_BDACPD (1 << 26) +# define RADEON_TV_DAC_RDACDET (1 << 29) +# define RADEON_TV_DAC_GDACDET (1 << 30) +# define RADEON_TV_DAC_BDACDET (1 << 31) +# define R420_TV_DAC_DACADJ_MASK (0x1f << 20) +# define R420_TV_DAC_RDACPD (1 << 25) +# define R420_TV_DAC_GDACPD (1 << 26) +# define R420_TV_DAC_BDACPD (1 << 27) +# define R420_TV_DAC_TVENABLE (1 << 28) +#define RADEON_DISP_HW_DEBUG 0x0d14 +# define RADEON_CRT2_DISP1_SEL (1 << 5) +#define RADEON_DISP_OUTPUT_CNTL 0x0d64 +# define RADEON_DISP_DAC_SOURCE_MASK 0x03 +# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c +# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 +# define RADEON_DISP_DAC_SOURCE_RMX 0x02 +# define RADEON_DISP_DAC_SOURCE_LTU 0x03 +# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 +# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) +# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 +# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) +# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) +# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) +# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) +# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) +# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) +# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) +# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ +# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ +#define RADEON_DISP_TV_OUT_CNTL 0x0d6c +# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) +# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) +#define RADEON_DAC_CRC_SIG 0x02cc +#define RADEON_DAC_DATA 0x03c9 /* VGA */ +#define RADEON_DAC_MASK 0x03c6 /* VGA */ +#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ +#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ +#define RADEON_DDA_CONFIG 0x02e0 +#define RADEON_DDA_ON_OFF 0x02e4 +#define RADEON_DEFAULT_OFFSET 0x16e0 +#define RADEON_DEFAULT_PITCH 0x16e4 +#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 +#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 +#define RADEON_DEVICE_ID 0x0f02 /* PCI */ +#define RADEON_DISP_MISC_CNTL 0x0d00 +# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) +#define RADEON_DISP_MERGE_CNTL 0x0d60 +# define RADEON_DISP_ALPHA_MODE_MASK 0x03 +# define RADEON_DISP_ALPHA_MODE_KEY 0 +# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 +# define RADEON_DISP_ALPHA_MODE_GLOBAL 2 +# define RADEON_DISP_RGB_OFFSET_EN (1 << 8) +# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) +# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) +# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) +#define RADEON_DISP2_MERGE_CNTL 0x0d68 +# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) +#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 +#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 +#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 +#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c +#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 +#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 +#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 +#define RADEON_DP_BRUSH_FRGD_CLR 0x147c +#define RADEON_DP_CNTL 0x16c0 +# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) +# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) +# define RADEON_DP_DST_TILE_LINEAR (0 << 3) +# define RADEON_DP_DST_TILE_MACRO (1 << 3) +# define RADEON_DP_DST_TILE_MICRO (2 << 3) +# define RADEON_DP_DST_TILE_BOTH (3 << 3) +#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +# define RADEON_DST_Y_MAJOR (1 << 2) +# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) +# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) +#define RADEON_DP_DATATYPE 0x16c4 +# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) +#define RADEON_DP_GUI_MASTER_CNTL 0x146c +# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) +# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) +# define RADEON_GMC_SRC_CLIPPING (1 << 2) +# define RADEON_GMC_DST_CLIPPING (1 << 3) +# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) +# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) +# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) +# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) +# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) +# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) +# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) +# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) +# define RADEON_GMC_BRUSH_NONE (15 << 4) +# define RADEON_GMC_DST_8BPP_CI (2 << 8) +# define RADEON_GMC_DST_15BPP (3 << 8) +# define RADEON_GMC_DST_16BPP (4 << 8) +# define RADEON_GMC_DST_24BPP (5 << 8) +# define RADEON_GMC_DST_32BPP (6 << 8) +# define RADEON_GMC_DST_8BPP_RGB (7 << 8) +# define RADEON_GMC_DST_Y8 (8 << 8) +# define RADEON_GMC_DST_RGB8 (9 << 8) +# define RADEON_GMC_DST_VYUY (11 << 8) +# define RADEON_GMC_DST_YVYU (12 << 8) +# define RADEON_GMC_DST_AYUV444 (14 << 8) +# define RADEON_GMC_DST_ARGB4444 (15 << 8) +# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) +# define RADEON_GMC_DST_DATATYPE_SHIFT 8 +# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) +# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) +# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) +# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) +# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) +# define RADEON_GMC_CONVERSION_TEMP (1 << 15) +# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) +# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) +# define RADEON_GMC_ROP3_MASK (0xff << 16) +# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) +# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) +# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) +# define RADEON_GMC_3D_FCN_EN (1 << 27) +# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) +# define RADEON_GMC_WR_MSK_DIS (1 << 30) +# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) +# define RADEON_ROP3_ZERO 0x00000000 +# define RADEON_ROP3_DSa 0x00880000 +# define RADEON_ROP3_SDna 0x00440000 +# define RADEON_ROP3_S 0x00cc0000 +# define RADEON_ROP3_DSna 0x00220000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DSx 0x00660000 +# define RADEON_ROP3_DSo 0x00ee0000 +# define RADEON_ROP3_DSon 0x00110000 +# define RADEON_ROP3_DSxn 0x00990000 +# define RADEON_ROP3_Dn 0x00550000 +# define RADEON_ROP3_SDno 0x00dd0000 +# define RADEON_ROP3_Sn 0x00330000 +# define RADEON_ROP3_DSno 0x00bb0000 +# define RADEON_ROP3_DSan 0x00770000 +# define RADEON_ROP3_ONE 0x00ff0000 +# define RADEON_ROP3_DPa 0x00a00000 +# define RADEON_ROP3_PDna 0x00500000 +# define RADEON_ROP3_P 0x00f00000 +# define RADEON_ROP3_DPna 0x000a0000 +# define RADEON_ROP3_D 0x00aa0000 +# define RADEON_ROP3_DPx 0x005a0000 +# define RADEON_ROP3_DPo 0x00fa0000 +# define RADEON_ROP3_DPon 0x00050000 +# define RADEON_ROP3_PDxn 0x00a50000 +# define RADEON_ROP3_PDno 0x00f50000 +# define RADEON_ROP3_Pn 0x000f0000 +# define RADEON_ROP3_DPno 0x00af0000 +# define RADEON_ROP3_DPan 0x005f0000 +#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 +#define RADEON_DP_MIX 0x16c8 +#define RADEON_DP_SRC_BKGD_CLR 0x15dc +#define RADEON_DP_SRC_FRGD_CLR 0x15d8 +#define RADEON_DP_WRITE_MASK 0x16cc +#define RADEON_DST_BRES_DEC 0x1630 +#define RADEON_DST_BRES_ERR 0x1628 +#define RADEON_DST_BRES_INC 0x162c +#define RADEON_DST_BRES_LNTH 0x1634 +#define RADEON_DST_BRES_LNTH_SUB 0x1638 +#define RADEON_DST_HEIGHT 0x1410 +#define RADEON_DST_HEIGHT_WIDTH 0x143c +#define RADEON_DST_HEIGHT_WIDTH_8 0x158c +#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 +#define RADEON_DST_HEIGHT_Y 0x15a0 +#define RADEON_DST_LINE_START 0x1600 +#define RADEON_DST_LINE_END 0x1604 +#define RADEON_DST_LINE_PATCOUNT 0x1608 +# define RADEON_BRES_CNTL_SHIFT 8 +#define RADEON_DST_OFFSET 0x1404 +#define RADEON_DST_PITCH 0x1408 +#define RADEON_DST_PITCH_OFFSET 0x142c +#define RADEON_DST_PITCH_OFFSET_C 0x1c80 +# define RADEON_PITCH_SHIFT 21 +# define RADEON_DST_TILE_LINEAR (0 << 30) +# define RADEON_DST_TILE_MACRO (1 << 30) +# define RADEON_DST_TILE_MICRO (2 << 30) +# define RADEON_DST_TILE_BOTH (3 << 30) +#define RADEON_DST_WIDTH 0x140c +#define RADEON_DST_WIDTH_HEIGHT 0x1598 +#define RADEON_DST_WIDTH_X 0x1588 +#define RADEON_DST_WIDTH_X_INCY 0x159c +#define RADEON_DST_X 0x141c +#define RADEON_DST_X_SUB 0x15a4 +#define RADEON_DST_X_Y 0x1594 +#define RADEON_DST_Y 0x1420 +#define RADEON_DST_Y_SUB 0x15a8 +#define RADEON_DST_Y_X 0x1438 + +#define RADEON_FCP_CNTL 0x0910 +# define RADEON_FCP0_SRC_PCICLK 0 +# define RADEON_FCP0_SRC_PCLK 1 +# define RADEON_FCP0_SRC_PCLKb 2 +# define RADEON_FCP0_SRC_HREF 3 +# define RADEON_FCP0_SRC_GND 4 +# define RADEON_FCP0_SRC_HREFb 5 +#define RADEON_FLUSH_1 0x1704 +#define RADEON_FLUSH_2 0x1708 +#define RADEON_FLUSH_3 0x170c +#define RADEON_FLUSH_4 0x1710 +#define RADEON_FLUSH_5 0x1714 +#define RADEON_FLUSH_6 0x1718 +#define RADEON_FLUSH_7 0x171c +#define RADEON_FOG_3D_TABLE_START 0x1810 +#define RADEON_FOG_3D_TABLE_END 0x1814 +#define RADEON_FOG_3D_TABLE_DENSITY 0x181c +#define RADEON_FOG_TABLE_INDEX 0x1a14 +#define RADEON_FOG_TABLE_DATA 0x1a18 +#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 +#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 +# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff +# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 +# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff +# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 +# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 +# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff +# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 +# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 +# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 +# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 +# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 +# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 +#define RADEON_FP_GEN_CNTL 0x0284 +# define RADEON_FP_FPON (1 << 0) +# define RADEON_FP_BLANK_EN (1 << 1) +# define RADEON_FP_TMDS_EN (1 << 2) +# define RADEON_FP_PANEL_FORMAT (1 << 3) +# define RADEON_FP_EN_TMDS (1 << 7) +# define RADEON_FP_DETECT_SENSE (1 << 8) +# define R200_FP_SOURCE_SEL_MASK (3 << 10) +# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP_SOURCE_SEL_RMX (2 << 10) +# define R200_FP_SOURCE_SEL_TRANS (3 << 10) +# define RADEON_FP_SEL_CRTC1 (0 << 13) +# define RADEON_FP_SEL_CRTC2 (1 << 13) +# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define RADEON_FP_DFP_SYNC_SEL (1 << 21) +# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) +# define RADEON_FP_CRT_SYNC_SEL (1 << 23) +# define RADEON_FP_USE_SHADOW_EN (1 << 24) +# define RADEON_FP_CRT_SYNC_ALT (1 << 26) +#define RADEON_FP2_GEN_CNTL 0x0288 +# define RADEON_FP2_BLANK_EN (1 << 1) +# define RADEON_FP2_ON (1 << 2) +# define RADEON_FP2_PANEL_FORMAT (1 << 3) +# define RADEON_FP2_DETECT_SENSE (1 << 8) +# define R200_FP2_SOURCE_SEL_MASK (3 << 10) +# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) +# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) +# define R200_FP2_SOURCE_SEL_RMX (2 << 10) +# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) +# define RADEON_FP2_SRC_SEL_MASK (3 << 13) +# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) +# define RADEON_FP2_FP_POL (1 << 16) +# define RADEON_FP2_LP_POL (1 << 17) +# define RADEON_FP2_SCK_POL (1 << 18) +# define RADEON_FP2_LCD_CNTL_MASK (7 << 19) +# define RADEON_FP2_PAD_FLOP_EN (1 << 22) +# define RADEON_FP2_CRC_EN (1 << 23) +# define RADEON_FP2_CRC_READ_EN (1 << 24) +# define RADEON_FP2_DVO_EN (1 << 25) +# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) +# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) +# define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) +# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) +#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 +#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 +#define RADEON_FP_HORZ_STRETCH 0x028c +#define RADEON_FP_HORZ2_STRETCH 0x038c +# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff +# define RADEON_HORZ_STRETCH_RATIO_MAX 4096 +# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) +# define RADEON_HORZ_PANEL_SHIFT 16 +# define RADEON_HORZ_STRETCH_PIXREP (0 << 25) +# define RADEON_HORZ_STRETCH_BLEND (1 << 26) +# define RADEON_HORZ_STRETCH_ENABLE (1 << 25) +# define RADEON_HORZ_AUTO_RATIO (1 << 27) +# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) +#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 +#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 +#define RADEON_FP_VERT_STRETCH 0x0290 +#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 +#define RADEON_FP_VERT2_STRETCH 0x0390 +# define RADEON_VERT_PANEL_SIZE (0xfff << 12) +# define RADEON_VERT_PANEL_SHIFT 12 +# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff +# define RADEON_VERT_STRETCH_RATIO_SHIFT 0 +# define RADEON_VERT_STRETCH_RATIO_MAX 4096 +# define RADEON_VERT_STRETCH_ENABLE (1 << 25) +# define RADEON_VERT_STRETCH_LINEREP (0 << 26) +# define RADEON_VERT_STRETCH_BLEND (1 << 26) +# define RADEON_VERT_AUTO_RATIO_EN (1 << 27) +# define RADEON_VERT_AUTO_RATIO_INC (1 << 31) +# define RADEON_VERT_STRETCH_RESERVED 0x71000000 +#define RS400_FP_2ND_GEN_CNTL 0x0384 +# define RS400_FP_2ND_ON (1 << 0) +# define RS400_FP_2ND_BLANK_EN (1 << 1) +# define RS400_TMDS_2ND_EN (1 << 2) +# define RS400_PANEL_FORMAT_2ND (1 << 3) +# define RS400_FP_2ND_EN_TMDS (1 << 7) +# define RS400_FP_2ND_DETECT_SENSE (1 << 8) +# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) +# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) +# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) +# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) +# define RS400_FP_2ND_DETECT_EN (1 << 12) +# define RS400_HPD_2ND_SEL (1 << 13) +#define RS400_FP2_2_GEN_CNTL 0x0388 +# define RS400_FP2_2_BLANK_EN (1 << 1) +# define RS400_FP2_2_ON (1 << 2) +# define RS400_FP2_2_PANEL_FORMAT (1 << 3) +# define RS400_FP2_2_DETECT_SENSE (1 << 8) +# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) +# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) +# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) +# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) +# define RS400_FP2_2_DVO2_EN (1 << 25) +#define RS400_TMDS2_CNTL 0x0394 +#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 +# define RS400_TMDS2_PLLEN (1 << 0) +# define RS400_TMDS2_PLLRST (1 << 1) + +#define RADEON_GEN_INT_CNTL 0x0040 +#define RADEON_GEN_INT_STATUS 0x0044 +# define RADEON_VSYNC_INT_AK (1 << 2) +# define RADEON_VSYNC_INT (1 << 2) +# define RADEON_VSYNC2_INT_AK (1 << 6) +# define RADEON_VSYNC2_INT (1 << 6) +#define RADEON_GENENB 0x03c3 /* VGA */ +#define RADEON_GENFC_RD 0x03ca /* VGA */ +#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ +#define RADEON_GENMO_RD 0x03cc /* VGA */ +#define RADEON_GENMO_WT 0x03c2 /* VGA */ +#define RADEON_GENS0 0x03c2 /* VGA */ +#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ +#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ +#define RADEON_GPIO_MONIDB 0x006c +#define RADEON_GPIO_CRT2_DDC 0x006c +#define RADEON_GPIO_DVI_DDC 0x0064 +#define RADEON_GPIO_VGA_DDC 0x0060 +# define RADEON_GPIO_A_0 (1 << 0) +# define RADEON_GPIO_A_1 (1 << 1) +# define RADEON_GPIO_Y_0 (1 << 8) +# define RADEON_GPIO_Y_1 (1 << 9) +# define RADEON_GPIO_Y_SHIFT_0 8 +# define RADEON_GPIO_Y_SHIFT_1 9 +# define RADEON_GPIO_EN_0 (1 << 16) +# define RADEON_GPIO_EN_1 (1 << 17) +# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ +# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ +#define RADEON_GRPH8_DATA 0x03cf /* VGA */ +#define RADEON_GRPH8_IDX 0x03ce /* VGA */ +#define RADEON_GUI_SCRATCH_REG0 0x15e0 +#define RADEON_GUI_SCRATCH_REG1 0x15e4 +#define RADEON_GUI_SCRATCH_REG2 0x15e8 +#define RADEON_GUI_SCRATCH_REG3 0x15ec +#define RADEON_GUI_SCRATCH_REG4 0x15f0 +#define RADEON_GUI_SCRATCH_REG5 0x15f4 + +#define RADEON_HEADER 0x0f0e /* PCI */ +#define RADEON_HOST_DATA0 0x17c0 +#define RADEON_HOST_DATA1 0x17c4 +#define RADEON_HOST_DATA2 0x17c8 +#define RADEON_HOST_DATA3 0x17cc +#define RADEON_HOST_DATA4 0x17d0 +#define RADEON_HOST_DATA5 0x17d4 +#define RADEON_HOST_DATA6 0x17d8 +#define RADEON_HOST_DATA7 0x17dc +#define RADEON_HOST_DATA_LAST 0x17e0 +#define RADEON_HOST_PATH_CNTL 0x0130 +# define RADEON_HDP_SOFT_RESET (1 << 26) +# define RADEON_HDP_APER_CNTL (1 << 23) +#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ +# define RADEON_HTOT_CNTL_VGA_EN (1 << 28) +#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ + + /* Multimedia I2C bus */ +#define RADEON_I2C_CNTL_0 0x0090 +#define RADEON_I2C_DONE (1<<0) +#define RADEON_I2C_NACK (1<<1) +#define RADEON_I2C_HALT (1<<2) +#define RADEON_I2C_SOFT_RST (1<<5) +#define RADEON_I2C_DRIVE_EN (1<<6) +#define RADEON_I2C_DRIVE_SEL (1<<7) +#define RADEON_I2C_START (1<<8) +#define RADEON_I2C_STOP (1<<9) +#define RADEON_I2C_RECEIVE (1<<10) +#define RADEON_I2C_ABORT (1<<11) +#define RADEON_I2C_GO (1<<12) +#define RADEON_I2C_CNTL_1 0x0094 +#define RADEON_I2C_SEL (1<<16) +#define RADEON_I2C_EN (1<<17) +#define RADEON_I2C_DATA 0x0098 + +#define RADEON_DVI_I2C_CNTL_0 0x02e0 +#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ +#define RADEON_DVI_I2C_DATA 0x02e8 + +#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ +#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ +#define RADEON_IO_BASE 0x0f14 /* PCI */ + +#define RADEON_LATENCY 0x0f0d /* PCI */ +#define RADEON_LEAD_BRES_DEC 0x1608 +#define RADEON_LEAD_BRES_LNTH 0x161c +#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 +#define RADEON_LVDS_GEN_CNTL 0x02d0 +# define RADEON_LVDS_ON (1 << 0) +# define RADEON_LVDS_DISPLAY_DIS (1 << 1) +# define RADEON_LVDS_PANEL_TYPE (1 << 2) +# define RADEON_LVDS_PANEL_FORMAT (1 << 3) +# define RADEON_LVDS_RST_FM (1 << 6) +# define RADEON_LVDS_EN (1 << 7) +# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 +# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) +# define RADEON_LVDS_BL_MOD_EN (1 << 16) +# define RADEON_LVDS_DIGON (1 << 18) +# define RADEON_LVDS_BLON (1 << 19) +# define RADEON_LVDS_SEL_CRTC2 (1 << 23) +#define RADEON_LVDS_PLL_CNTL 0x02d4 +# define RADEON_HSYNC_DELAY_SHIFT 28 +# define RADEON_HSYNC_DELAY_MASK (0xf << 28) +# define RADEON_LVDS_PLL_EN (1 << 16) +# define RADEON_LVDS_PLL_RESET (1 << 17) +# define R300_LVDS_SRC_SEL_MASK (3 << 18) +# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) +# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) +# define R300_LVDS_SRC_SEL_RMX (2 << 18) + +#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ +#define RADEON_MC_AGP_LOCATION 0x014c +#define RADEON_MC_FB_LOCATION 0x0148 +#define RADEON_DISPLAY_BASE_ADDR 0x23c +#define RADEON_DISPLAY2_BASE_ADDR 0x33c +#define RADEON_OV0_BASE_ADDR 0x43c +#define RADEON_NB_TOM 0x15c +#define R300_MC_INIT_MISC_LAT_TIMER 0x180 +# define R300_MC_DISP0R_INIT_LAT_SHIFT 8 +# define R300_MC_DISP0R_INIT_LAT_MASK 0xf +# define R300_MC_DISP1R_INIT_LAT_SHIFT 12 +# define R300_MC_DISP1R_INIT_LAT_MASK 0xf +#define RADEON_MCLK_CNTL 0x0012 /* PLL */ +# define RADEON_FORCEON_MCLKA (1 << 16) +# define RADEON_FORCEON_MCLKB (1 << 17) +# define RADEON_FORCEON_YCLKA (1 << 18) +# define RADEON_FORCEON_YCLKB (1 << 19) +# define RADEON_FORCEON_MC (1 << 20) +# define RADEON_FORCEON_AIC (1 << 21) +# define R300_DISABLE_MC_MCLKA (1 << 21) +# define R300_DISABLE_MC_MCLKB (1 << 21) +#define RADEON_MCLK_MISC 0x001f /* PLL */ +# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) +# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) +# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) +# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) +#define RADEON_LCD_GPIO_MASK 0x01a0 +#define RADEON_GPIOPAD_EN 0x01a0 +#define RADEON_LCD_GPIO_Y_REG 0x01a4 +#define RADEON_MDGPIO_A_REG 0x01ac +#define RADEON_MDGPIO_EN_REG 0x01b0 +#define RADEON_MDGPIO_MASK 0x0198 +#define RADEON_GPIOPAD_MASK 0x0198 +#define RADEON_GPIOPAD_A 0x019c +#define RADEON_MDGPIO_Y_REG 0x01b4 +#define RADEON_MEM_ADDR_CONFIG 0x0148 +#define RADEON_MEM_BASE 0x0f10 /* PCI */ +#define RADEON_MEM_CNTL 0x0140 +# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 +# define RADEON_MEM_USE_B_CH_ONLY (1 << 1) +# define RV100_HALF_MODE (1 << 3) +# define R300_MEM_NUM_CHANNELS_MASK 0x03 +# define R300_MEM_USE_CD_CH_ONLY (1 << 2) +#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ +#define RADEON_MEM_INIT_LAT_TIMER 0x0154 +#define RADEON_MEM_INTF_CNTL 0x014c +#define RADEON_MEM_SDRAM_MODE_REG 0x0158 +# define RADEON_SDRAM_MODE_MASK 0xffff0000 +# define RADEON_B3MEM_RESET_MASK 0x6fffffff +# define RADEON_MEM_CFG_TYPE_DDR (1 << 30) +#define RADEON_MEM_STR_CNTL 0x0150 +# define RADEON_MEM_PWRUP_COMPL_A (1 << 0) +# define RADEON_MEM_PWRUP_COMPL_B (1 << 1) +# define R300_MEM_PWRUP_COMPL_C (1 << 2) +# define R300_MEM_PWRUP_COMPL_D (1 << 3) +# define RADEON_MEM_PWRUP_COMPLETE 0x03 +# define R300_MEM_PWRUP_COMPLETE 0x0f +#define RADEON_MC_STATUS 0x0150 +# define RADEON_MC_IDLE (1 << 2) +# define R300_MC_IDLE (1 << 4) +#define RADEON_MEM_VGA_RP_SEL 0x003c +#define RADEON_MEM_VGA_WP_SEL 0x0038 +#define RADEON_MIN_GRANT 0x0f3e /* PCI */ +#define RADEON_MM_DATA 0x0004 +#define RADEON_MM_INDEX 0x0000 +#define RADEON_MPLL_CNTL 0x000e /* PLL */ +#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ +#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ +#define RADEON_SEPROM_CNTL1 0x01c0 +# define RADEON_SCK_PRESCALE_SHIFT 24 +# define RADEON_SCK_PRESCALE_MASK (0xff << 24) +#define R300_MC_IND_INDEX 0x01f8 +# define R300_MC_IND_ADDR_MASK 0x3f +# define R300_MC_IND_WR_EN (1 << 8) +#define R300_MC_IND_DATA 0x01fc +#define R300_MC_READ_CNTL_AB 0x017c +# define R300_MEM_RBS_POSITION_A_MASK 0x03 +#define R300_MC_READ_CNTL_CD_mcind 0x24 +# define R300_MEM_RBS_POSITION_C_MASK 0x03 + +#define RADEON_N_VIF_COUNT 0x0248 + +#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 + +#define RADEON_OV0_COLOUR_CNTL 0x04E0 +#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 +#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 +# define RADEON_EXCL_HORZ_START_MASK 0x000000ff +# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 +# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define RADEON_OV0_EXCLUSIVE_VERT 0x040C +# define RADEON_EXCL_VERT_START_MASK 0x000003ff +# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 +#define RADEON_OV0_FILTER_CNTL 0x04A0 +# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 +# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 +# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 +# define RADEON_FILTER_HC_COEF_VERT_Y 0x4 +# define RADEON_FILTER_HC_COEF_VERT_UV 0x8 +# define RADEON_FILTER_HARDCODED_COEF 0xf +# define RADEON_FILTER_COEF_MASK 0xf + +#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 +#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 +#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 +#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC +#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 +#define RADEON_OV0_FLAG_CNTL 0x04DC +#define RADEON_OV0_GAMMA_000_00F 0x0d40 +#define RADEON_OV0_GAMMA_010_01F 0x0d44 +#define RADEON_OV0_GAMMA_020_03F 0x0d48 +#define RADEON_OV0_GAMMA_040_07F 0x0d4c +#define RADEON_OV0_GAMMA_080_0BF 0x0e00 +#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 +#define RADEON_OV0_GAMMA_100_13F 0x0e08 +#define RADEON_OV0_GAMMA_140_17F 0x0e0c +#define RADEON_OV0_GAMMA_180_1BF 0x0e10 +#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 +#define RADEON_OV0_GAMMA_200_23F 0x0e18 +#define RADEON_OV0_GAMMA_240_27F 0x0e1c +#define RADEON_OV0_GAMMA_280_2BF 0x0e20 +#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 +#define RADEON_OV0_GAMMA_300_33F 0x0e28 +#define RADEON_OV0_GAMMA_340_37F 0x0e2c +#define RADEON_OV0_GAMMA_380_3BF 0x0d50 +#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 +#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC +#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 +#define RADEON_OV0_H_INC 0x0480 +#define RADEON_OV0_KEY_CNTL 0x04F4 +# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L +# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L +# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L +# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L +# define RADEON_VIDEO_KEY_FN_NE 0x00000003L +# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L +# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L +# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L +# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L +# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L +# define RADEON_CMP_MIX_MASK 0x00000100L +# define RADEON_CMP_MIX_OR 0x00000000L +# define RADEON_CMP_MIX_AND 0x00000100L +#define RADEON_OV0_LIN_TRANS_A 0x0d20 +#define RADEON_OV0_LIN_TRANS_B 0x0d24 +#define RADEON_OV0_LIN_TRANS_C 0x0d28 +#define RADEON_OV0_LIN_TRANS_D 0x0d2c +#define RADEON_OV0_LIN_TRANS_E 0x0d30 +#define RADEON_OV0_LIN_TRANS_F 0x0d34 +#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L +#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 +#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 +# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define RADEON_OV0_P1_X_START_END 0x0494 +#define RADEON_OV0_P2_X_START_END 0x0498 +#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L +#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C +#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C +#define RADEON_OV0_P3_X_START_END 0x049C +#define RADEON_OV0_REG_LOAD_CNTL 0x0410 +# define RADEON_REG_LD_CTL_LOCK 0x00000001L +# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L +# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L +#define RADEON_OV0_SCALE_CNTL 0x0420 +# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L +# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L +# define RADEON_SCALER_SIGNED_UV 0x00000010L +# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L +# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L +# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L +# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L +# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L +# define RADEON_SCALER_SOURCE_15BPP 0x00000300L +# define RADEON_SCALER_SOURCE_16BPP 0x00000400L +# define RADEON_SCALER_SOURCE_32BPP 0x00000600L +# define RADEON_SCALER_SOURCE_YUV9 0x00000900L +# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L +# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L +# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L +# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L +# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L +# define RADEON_SCALER_CRTC_SEL 0x00004000L +# define RADEON_SCALER_SMART_SWITCH 0x00008000L +# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L +# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L +# define RADEON_SCALER_DIS_LIMIT 0x08000000L +# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L +# define RADEON_SCALER_INT_EMU 0x20000000L +# define RADEON_SCALER_ENABLE 0x40000000L +# define RADEON_SCALER_SOFT_RESET 0x80000000L +#define RADEON_OV0_STEP_BY 0x0484 +#define RADEON_OV0_TEST 0x04F8 +#define RADEON_OV0_V_INC 0x0424 +#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 +# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 +# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 +# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L +# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L +# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C +#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 +#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 +#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 +#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 +#define RADEON_OV0_Y_X_START 0x0400 +#define RADEON_OV0_Y_X_END 0x0404 +#define RADEON_OV1_Y_X_START 0x0600 +#define RADEON_OV1_Y_X_END 0x0604 +#define RADEON_OVR_CLR 0x0230 +#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 +#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 + +/* first capture unit */ + +#define RADEON_CAP0_BUF0_OFFSET 0x0920 +#define RADEON_CAP0_BUF1_OFFSET 0x0924 +#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 +#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C + +#define RADEON_CAP0_BUF_PITCH 0x0930 +#define RADEON_CAP0_V_WINDOW 0x0934 +#define RADEON_CAP0_H_WINDOW 0x0938 +#define RADEON_CAP0_VBI0_OFFSET 0x093C +#define RADEON_CAP0_VBI1_OFFSET 0x0940 +#define RADEON_CAP0_VBI_V_WINDOW 0x0944 +#define RADEON_CAP0_VBI_H_WINDOW 0x0948 +#define RADEON_CAP0_PORT_MODE_CNTL 0x094C +#define RADEON_CAP0_TRIG_CNTL 0x0950 +#define RADEON_CAP0_DEBUG 0x0954 +#define RADEON_CAP0_CONFIG 0x0958 +# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 +# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 +# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 +# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 +# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 +# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C +#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 +#define RADEON_CAP0_ANC_H_WINDOW 0x0964 +#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 +#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C +#define RADEON_CAP0_BUF_STATUS 0x0970 +/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ +/* #define RADEON_CAP0_XSHARPNESS 0x097C */ +#define RADEON_CAP0_VBI2_OFFSET 0x0980 +#define RADEON_CAP0_VBI3_OFFSET 0x0984 +#define RADEON_CAP0_ANC2_OFFSET 0x0988 +#define RADEON_CAP0_ANC3_OFFSET 0x098C +#define RADEON_VID_BUFFER_CONTROL 0x0900 + +/* second capture unit */ + +#define RADEON_CAP1_BUF0_OFFSET 0x0990 +#define RADEON_CAP1_BUF1_OFFSET 0x0994 +#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 +#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C + +#define RADEON_CAP1_BUF_PITCH 0x09A0 +#define RADEON_CAP1_V_WINDOW 0x09A4 +#define RADEON_CAP1_H_WINDOW 0x09A8 +#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC +#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 +#define RADEON_CAP1_VBI_V_WINDOW 0x09B4 +#define RADEON_CAP1_VBI_H_WINDOW 0x09B8 +#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC +#define RADEON_CAP1_TRIG_CNTL 0x09C0 +#define RADEON_CAP1_DEBUG 0x09C4 +#define RADEON_CAP1_CONFIG 0x09C8 +#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC +#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 +#define RADEON_CAP1_ANC_H_WINDOW 0x09D4 +#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 +#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define RADEON_CAP1_BUF_STATUS 0x09E0 +#define RADEON_CAP1_DWNSC_XRATIO 0x09E8 +#define RADEON_CAP1_XSHARPNESS 0x09EC + +/* misc multimedia registers */ + +#define RADEON_IDCT_RUNS 0x1F80 +#define RADEON_IDCT_LEVELS 0x1F84 +#define RADEON_IDCT_CONTROL 0x1FBC +#define RADEON_IDCT_AUTH_CONTROL 0x1F88 +#define RADEON_IDCT_AUTH 0x1F8C + +#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ +# define RADEON_P2PLL_RESET (1 << 0) +# define RADEON_P2PLL_SLEEP (1 << 1) +# define RADEON_P2PLL_PVG_MASK (7 << 11) +# define RADEON_P2PLL_PVG_SHIFT 11 +# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_P2PLL_DIV_0 0x002c +# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff +# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 +#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ +# define RADEON_P2PLL_REF_DIV_MASK 0x03ff +# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +# define R300_PPLL_REF_DIV_ACC_SHIFT 18 +#define RADEON_PALETTE_DATA 0x00b4 +#define RADEON_PALETTE_30_DATA 0x00b8 +#define RADEON_PALETTE_INDEX 0x00b0 +#define RADEON_PCI_GART_PAGE 0x017c +#define RADEON_PIXCLKS_CNTL 0x002d +# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 +# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) +# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) +# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) +# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +# define R300_DVOCLK_ALWAYS_ONb (1 << 10) +# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) +# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) +# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) +# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) +# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) +#define RADEON_PLANE_3D_MASK_C 0x1d44 +#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ +# define RADEON_PLL_MASK_READ_B (1 << 9) +#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ +#define RADEON_PMI_DATA 0x0f63 /* PCI */ +#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ +#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ +#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ +#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ +#define RADEON_PPLL_CNTL 0x0002 /* PLL */ +# define RADEON_PPLL_RESET (1 << 0) +# define RADEON_PPLL_SLEEP (1 << 1) +# define RADEON_PPLL_PVG_MASK (7 << 11) +# define RADEON_PPLL_PVG_SHIFT 11 +# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ +#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ +#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ +#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ +# define RADEON_PPLL_FB3_DIV_MASK 0x07ff +# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 +#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ +# define RADEON_PPLL_REF_DIV_MASK 0x03ff +# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ + +#define RADEON_RBBM_GUICNTL 0x172c +# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) +# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) +# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) +# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) +#define RADEON_RBBM_SOFT_RESET 0x00f0 +# define RADEON_SOFT_RESET_CP (1 << 0) +# define RADEON_SOFT_RESET_HI (1 << 1) +# define RADEON_SOFT_RESET_SE (1 << 2) +# define RADEON_SOFT_RESET_RE (1 << 3) +# define RADEON_SOFT_RESET_PP (1 << 4) +# define RADEON_SOFT_RESET_E2 (1 << 5) +# define RADEON_SOFT_RESET_RB (1 << 6) +# define RADEON_SOFT_RESET_HDP (1 << 7) +#define RADEON_RBBM_STATUS 0x0e40 +# define RADEON_RBBM_FIFOCNT_MASK 0x007f +# define RADEON_RBBM_ACTIVE (1 << 31) +#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c +# define RADEON_RB2D_DC_FLUSH (3 << 0) +# define RADEON_RB2D_DC_FREE (3 << 2) +# define RADEON_RB2D_DC_FLUSH_ALL 0xf +# define RADEON_RB2D_DC_BUSY (1 << 31) +#define RADEON_RB2D_DSTCACHE_MODE 0x3428 +#define RADEON_DSTCACHE_CTLSTAT 0x1714 + +#define RADEON_RB3D_ZCACHE_MODE 0x3250 +#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 +# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 +#define RADEON_RB3D_DSTCACHE_MODE 0x3258 +# define RADEON_RB3D_DC_CACHE_ENABLE (0) +# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) +# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) +# define RADEON_RB3D_DC_CACHE_DISABLE (3) +# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) +# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) +# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) +# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) +# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) +# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) +# define RADEON_RB3D_DC_FORCE_RMW (1 << 16) +# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) +# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) + +#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C +# define RADEON_RB3D_DC_FLUSH (3 << 0) +# define RADEON_RB3D_DC_FREE (3 << 2) +# define RADEON_RB3D_DC_FLUSH_ALL 0xf +# define RADEON_RB3D_DC_BUSY (1 << 31) + +#define RADEON_REG_BASE 0x0f18 /* PCI */ +#define RADEON_REGPROG_INF 0x0f09 /* PCI */ +#define RADEON_REVISION_ID 0x0f08 /* PCI */ + +#define RADEON_SC_BOTTOM 0x164c +#define RADEON_SC_BOTTOM_RIGHT 0x16f0 +#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c +#define RADEON_SC_LEFT 0x1640 +#define RADEON_SC_RIGHT 0x1644 +#define RADEON_SC_TOP 0x1648 +#define RADEON_SC_TOP_LEFT 0x16ec +#define RADEON_SC_TOP_LEFT_C 0x1c88 +# define RADEON_SC_SIGN_MASK_LO 0x8000 +# define RADEON_SC_SIGN_MASK_HI 0x80000000 +#define RADEON_SCLK_CNTL 0x000d /* PLL */ +# define RADEON_SCLK_SRC_SEL_MASK 0x0007 +# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 +# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 +# define RADEON_SCLK_FORCEON_MASK 0xffff8000 +# define RADEON_SCLK_FORCE_DISP2 (1<<15) +# define RADEON_SCLK_FORCE_CP (1<<16) +# define RADEON_SCLK_FORCE_HDP (1<<17) +# define RADEON_SCLK_FORCE_DISP1 (1<<18) +# define RADEON_SCLK_FORCE_TOP (1<<19) +# define RADEON_SCLK_FORCE_E2 (1<<20) +# define RADEON_SCLK_FORCE_SE (1<<21) +# define RADEON_SCLK_FORCE_IDCT (1<<22) +# define RADEON_SCLK_FORCE_VIP (1<<23) +# define RADEON_SCLK_FORCE_RE (1<<24) +# define RADEON_SCLK_FORCE_PB (1<<25) +# define RADEON_SCLK_FORCE_TAM (1<<26) +# define RADEON_SCLK_FORCE_TDM (1<<27) +# define RADEON_SCLK_FORCE_RB (1<<28) +# define RADEON_SCLK_FORCE_TV_SCLK (1<<29) +# define RADEON_SCLK_FORCE_SUBPIC (1<<30) +# define RADEON_SCLK_FORCE_OV0 (1<<31) +# define R300_SCLK_FORCE_VAP (1<<21) +# define R300_SCLK_FORCE_SR (1<<25) +# define R300_SCLK_FORCE_PX (1<<26) +# define R300_SCLK_FORCE_TX (1<<27) +# define R300_SCLK_FORCE_US (1<<28) +# define R300_SCLK_FORCE_SU (1<<30) +#define R300_SCLK_CNTL2 0x1e /* PLL */ +# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) +# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) +# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) +# define R300_SCLK_FORCE_TCL (1<<13) +# define R300_SCLK_FORCE_CBA (1<<14) +# define R300_SCLK_FORCE_GA (1<<15) +#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ +# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 +# define RADEON_SCLK_MORE_FORCEON 0x0700 +#define RADEON_SDRAM_MODE_REG 0x0158 +#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ +#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ +#define RADEON_SNAPSHOT_F_COUNT 0x0244 +#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 +#define RADEON_SNAPSHOT_VIF_COUNT 0x024c +#define RADEON_SRC_OFFSET 0x15ac +#define RADEON_SRC_PITCH 0x15b0 +#define RADEON_SRC_PITCH_OFFSET 0x1428 +#define RADEON_SRC_SC_BOTTOM 0x165c +#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 +#define RADEON_SRC_SC_RIGHT 0x1654 +#define RADEON_SRC_X 0x1414 +#define RADEON_SRC_X_Y 0x1590 +#define RADEON_SRC_Y 0x1418 +#define RADEON_SRC_Y_X 0x1434 +#define RADEON_STATUS 0x0f06 /* PCI */ +#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ +#define RADEON_SUB_CLASS 0x0f0a /* PCI */ +#define RADEON_SURFACE_CNTL 0x0b00 +# define RADEON_SURF_TRANSLATION_DIS (1 << 8) +# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_INFO 0x0b0c +# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) +# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) +# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) +# define R200_SURF_TILE_NONE (0 << 16) +# define R200_SURF_TILE_COLOR_MACRO (1 << 16) +# define R200_SURF_TILE_COLOR_MICRO (2 << 16) +# define R200_SURF_TILE_COLOR_BOTH (3 << 16) +# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) +# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) +# define R300_SURF_TILE_NONE (0 << 16) +# define R300_SURF_TILE_COLOR_MACRO (1 << 16) +# define R300_SURF_TILE_DEPTH_32BPP (2 << 16) +# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) +# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) +# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) +# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) +#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 +#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 +#define RADEON_SURFACE1_INFO 0x0b1c +#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 +#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 +#define RADEON_SURFACE2_INFO 0x0b2c +#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 +#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 +#define RADEON_SURFACE3_INFO 0x0b3c +#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 +#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 +#define RADEON_SURFACE4_INFO 0x0b4c +#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 +#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 +#define RADEON_SURFACE5_INFO 0x0b5c +#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 +#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 +#define RADEON_SURFACE6_INFO 0x0b6c +#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 +#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 +#define RADEON_SURFACE7_INFO 0x0b7c +#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 +#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 +#define RADEON_SW_SEMAPHORE 0x013c + +#define RADEON_TEST_DEBUG_CNTL 0x0120 +#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RADEON_TEST_DEBUG_MUX 0x0124 +#define RADEON_TEST_DEBUG_OUT 0x012c +#define RADEON_TMDS_PLL_CNTL 0x02a8 +#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 +# define RADEON_TMDS_TRANSMITTER_PLLEN 1 +# define RADEON_TMDS_TRANSMITTER_PLLRST 2 +#define RADEON_TRAIL_BRES_DEC 0x1614 +#define RADEON_TRAIL_BRES_ERR 0x160c +#define RADEON_TRAIL_BRES_INC 0x1610 +#define RADEON_TRAIL_X 0x1618 +#define RADEON_TRAIL_X_SUB 0x1620 + +#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ +# define RADEON_VCLK_SRC_SEL_MASK 0x03 +# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 +# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 +# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 +# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 +# define RADEON_PIXCLK_ALWAYS_ONb (1<<6) +# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) +# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + +#define RADEON_VENDOR_ID 0x0f00 /* PCI */ +#define RADEON_VGA_DDA_CONFIG 0x02e8 +#define RADEON_VGA_DDA_ON_OFF 0x02ec +#define RADEON_VID_BUFFER_CONTROL 0x0900 +#define RADEON_VIDEOMUX_CNTL 0x0190 + + /* VIP bus */ +#define RADEON_VIPH_CH0_DATA 0x0c00 +#define RADEON_VIPH_CH1_DATA 0x0c04 +#define RADEON_VIPH_CH2_DATA 0x0c08 +#define RADEON_VIPH_CH3_DATA 0x0c0c +#define RADEON_VIPH_CH0_ADDR 0x0c10 +#define RADEON_VIPH_CH1_ADDR 0x0c14 +#define RADEON_VIPH_CH2_ADDR 0x0c18 +#define RADEON_VIPH_CH3_ADDR 0x0c1c +#define RADEON_VIPH_CH0_SBCNT 0x0c20 +#define RADEON_VIPH_CH1_SBCNT 0x0c24 +#define RADEON_VIPH_CH2_SBCNT 0x0c28 +#define RADEON_VIPH_CH3_SBCNT 0x0c2c +#define RADEON_VIPH_CH0_ABCNT 0x0c30 +#define RADEON_VIPH_CH1_ABCNT 0x0c34 +#define RADEON_VIPH_CH2_ABCNT 0x0c38 +#define RADEON_VIPH_CH3_ABCNT 0x0c3c +#define RADEON_VIPH_CONTROL 0x0c40 +# define RADEON_VIP_BUSY 0 +# define RADEON_VIP_IDLE 1 +# define RADEON_VIP_RESET 2 +# define RADEON_VIPH_EN (1 << 21) +#define RADEON_VIPH_DV_LAT 0x0c44 +#define RADEON_VIPH_BM_CHUNK 0x0c48 +#define RADEON_VIPH_DV_INT 0x0c4c +#define RADEON_VIPH_TIMEOUT_STAT 0x0c50 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 + +#define RADEON_VIPH_REG_DATA 0x0084 +#define RADEON_VIPH_REG_ADDR 0x0080 + + +#define RADEON_WAIT_UNTIL 0x1720 +# define RADEON_WAIT_CRTC_PFLIP (1 << 0) +# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) +# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) +# define RADEON_WAIT_CRTC_VLINE (1 << 3) +# define RADEON_WAIT_DMA_VID_IDLE (1 << 8) +# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) +# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ +# define RADEON_WAIT_OV0_FLIP (1 << 11) +# define RADEON_WAIT_AGP_FLUSH (1 << 13) +# define RADEON_WAIT_2D_IDLE (1 << 14) +# define RADEON_WAIT_3D_IDLE (1 << 15) +# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) +# define RADEON_CMDFIFO_ENTRIES_SHIFT 10 +# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f +# define RADEON_WAIT_VAP_IDLE (1 << 28) +# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) +# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) +# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) + +#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ +#define RADEON_XCLK_CNTL 0x000d /* PLL */ +#define RADEON_XDLL_CNTL 0x000c /* PLL */ +#define RADEON_XPLL_CNTL 0x000b /* PLL */ + + + + /* Registers for 3D/TCL */ +#define RADEON_PP_BORDER_COLOR_0 0x1d40 +#define RADEON_PP_BORDER_COLOR_1 0x1d44 +#define RADEON_PP_BORDER_COLOR_2 0x1d48 +#define RADEON_PP_CNTL 0x1c38 +# define RADEON_STIPPLE_ENABLE (1 << 0) +# define RADEON_SCISSOR_ENABLE (1 << 1) +# define RADEON_PATTERN_ENABLE (1 << 2) +# define RADEON_SHADOW_ENABLE (1 << 3) +# define RADEON_TEX_ENABLE_MASK (0xf << 4) +# define RADEON_TEX_0_ENABLE (1 << 4) +# define RADEON_TEX_1_ENABLE (1 << 5) +# define RADEON_TEX_2_ENABLE (1 << 6) +# define RADEON_TEX_3_ENABLE (1 << 7) +# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) +# define RADEON_TEX_BLEND_0_ENABLE (1 << 12) +# define RADEON_TEX_BLEND_1_ENABLE (1 << 13) +# define RADEON_TEX_BLEND_2_ENABLE (1 << 14) +# define RADEON_TEX_BLEND_3_ENABLE (1 << 15) +# define RADEON_PLANAR_YUV_ENABLE (1 << 20) +# define RADEON_SPECULAR_ENABLE (1 << 21) +# define RADEON_FOG_ENABLE (1 << 22) +# define RADEON_ALPHA_TEST_ENABLE (1 << 23) +# define RADEON_ANTI_ALIAS_NONE (0 << 24) +# define RADEON_ANTI_ALIAS_LINE (1 << 24) +# define RADEON_ANTI_ALIAS_POLY (2 << 24) +# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) +# define RADEON_BUMP_MAP_ENABLE (1 << 26) +# define RADEON_BUMPED_MAP_T0 (0 << 27) +# define RADEON_BUMPED_MAP_T1 (1 << 27) +# define RADEON_BUMPED_MAP_T2 (2 << 27) +# define RADEON_TEX_3D_ENABLE_0 (1 << 29) +# define RADEON_TEX_3D_ENABLE_1 (1 << 30) +# define RADEON_MC_ENABLE (1 << 31) +#define RADEON_PP_FOG_COLOR 0x1c18 +# define RADEON_FOG_COLOR_MASK 0x00ffffff +# define RADEON_FOG_VERTEX (0 << 24) +# define RADEON_FOG_TABLE (1 << 24) +# define RADEON_FOG_USE_DEPTH (0 << 25) +# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) +# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) +#define RADEON_PP_LUM_MATRIX 0x1d00 +#define RADEON_PP_MISC 0x1c14 +# define RADEON_REF_ALPHA_MASK 0x000000ff +# define RADEON_ALPHA_TEST_FAIL (0 << 8) +# define RADEON_ALPHA_TEST_LESS (1 << 8) +# define RADEON_ALPHA_TEST_LEQUAL (2 << 8) +# define RADEON_ALPHA_TEST_EQUAL (3 << 8) +# define RADEON_ALPHA_TEST_GEQUAL (4 << 8) +# define RADEON_ALPHA_TEST_GREATER (5 << 8) +# define RADEON_ALPHA_TEST_NEQUAL (6 << 8) +# define RADEON_ALPHA_TEST_PASS (7 << 8) +# define RADEON_ALPHA_TEST_OP_MASK (7 << 8) +# define RADEON_CHROMA_FUNC_FAIL (0 << 16) +# define RADEON_CHROMA_FUNC_PASS (1 << 16) +# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) +# define RADEON_CHROMA_FUNC_EQUAL (3 << 16) +# define RADEON_CHROMA_KEY_NEAREST (0 << 18) +# define RADEON_CHROMA_KEY_ZERO (1 << 18) +# define RADEON_SHADOW_ID_AUTO_INC (1 << 20) +# define RADEON_SHADOW_FUNC_EQUAL (0 << 21) +# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) +# define RADEON_SHADOW_PASS_1 (0 << 22) +# define RADEON_SHADOW_PASS_2 (1 << 22) +# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) +# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) +#define RADEON_PP_ROT_MATRIX_0 0x1d58 +#define RADEON_PP_ROT_MATRIX_1 0x1d5c +#define RADEON_PP_TXFILTER_0 0x1c54 +#define RADEON_PP_TXFILTER_1 0x1c6c +#define RADEON_PP_TXFILTER_2 0x1c84 +# define RADEON_MAG_FILTER_NEAREST (0 << 0) +# define RADEON_MAG_FILTER_LINEAR (1 << 0) +# define RADEON_MAG_FILTER_MASK (1 << 0) +# define RADEON_MIN_FILTER_NEAREST (0 << 1) +# define RADEON_MIN_FILTER_LINEAR (1 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define RADEON_MIN_FILTER_MASK (15 << 1) +# define RADEON_MAX_ANISO_1_TO_1 (0 << 5) +# define RADEON_MAX_ANISO_2_TO_1 (1 << 5) +# define RADEON_MAX_ANISO_4_TO_1 (2 << 5) +# define RADEON_MAX_ANISO_8_TO_1 (3 << 5) +# define RADEON_MAX_ANISO_16_TO_1 (4 << 5) +# define RADEON_MAX_ANISO_MASK (7 << 5) +# define RADEON_LOD_BIAS_MASK (0xff << 8) +# define RADEON_LOD_BIAS_SHIFT 8 +# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define RADEON_MAX_MIP_LEVEL_SHIFT 16 +# define RADEON_YUV_TO_RGB (1 << 20) +# define RADEON_YUV_TEMPERATURE_COOL (0 << 21) +# define RADEON_YUV_TEMPERATURE_HOT (1 << 21) +# define RADEON_YUV_TEMPERATURE_MASK (1 << 21) +# define RADEON_WRAPEN_S (1 << 22) +# define RADEON_CLAMP_S_WRAP (0 << 23) +# define RADEON_CLAMP_S_MIRROR (1 << 23) +# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define RADEON_CLAMP_S_CLAMP_GL (6 << 23) +# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define RADEON_CLAMP_S_MASK (7 << 23) +# define RADEON_WRAPEN_T (1 << 26) +# define RADEON_CLAMP_T_WRAP (0 << 27) +# define RADEON_CLAMP_T_MIRROR (1 << 27) +# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define RADEON_CLAMP_T_CLAMP_GL (6 << 27) +# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define RADEON_CLAMP_T_MASK (7 << 27) +# define RADEON_BORDER_MODE_OGL (0 << 31) +# define RADEON_BORDER_MODE_D3D (1 << 31) +#define RADEON_PP_TXFORMAT_0 0x1c58 +#define RADEON_PP_TXFORMAT_1 0x1c70 +#define RADEON_PP_TXFORMAT_2 0x1c88 +# define RADEON_TXFORMAT_I8 (0 << 0) +# define RADEON_TXFORMAT_AI88 (1 << 0) +# define RADEON_TXFORMAT_RGB332 (2 << 0) +# define RADEON_TXFORMAT_ARGB1555 (3 << 0) +# define RADEON_TXFORMAT_RGB565 (4 << 0) +# define RADEON_TXFORMAT_ARGB4444 (5 << 0) +# define RADEON_TXFORMAT_ARGB8888 (6 << 0) +# define RADEON_TXFORMAT_RGBA8888 (7 << 0) +# define RADEON_TXFORMAT_Y8 (8 << 0) +# define RADEON_TXFORMAT_VYUY422 (10 << 0) +# define RADEON_TXFORMAT_YVYU422 (11 << 0) +# define RADEON_TXFORMAT_DXT1 (12 << 0) +# define RADEON_TXFORMAT_DXT23 (14 << 0) +# define RADEON_TXFORMAT_DXT45 (15 << 0) +# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) +# define RADEON_TXFORMAT_FORMAT_SHIFT 0 +# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) +# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define RADEON_TXFORMAT_NON_POWER2 (1 << 7) +# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) +# define RADEON_TXFORMAT_WIDTH_SHIFT 8 +# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) +# define RADEON_TXFORMAT_HEIGHT_SHIFT 12 +# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) +# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 +# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) +# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) +# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) +# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) +# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) +#define RADEON_PP_CUBIC_FACES_0 0x1d24 +#define RADEON_PP_CUBIC_FACES_1 0x1d28 +#define RADEON_PP_CUBIC_FACES_2 0x1d2c +# define RADEON_FACE_WIDTH_1_SHIFT 0 +# define RADEON_FACE_HEIGHT_1_SHIFT 4 +# define RADEON_FACE_WIDTH_1_MASK (0xf << 0) +# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) +# define RADEON_FACE_WIDTH_2_SHIFT 8 +# define RADEON_FACE_HEIGHT_2_SHIFT 12 +# define RADEON_FACE_WIDTH_2_MASK (0xf << 8) +# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) +# define RADEON_FACE_WIDTH_3_SHIFT 16 +# define RADEON_FACE_HEIGHT_3_SHIFT 20 +# define RADEON_FACE_WIDTH_3_MASK (0xf << 16) +# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) +# define RADEON_FACE_WIDTH_4_SHIFT 24 +# define RADEON_FACE_HEIGHT_4_SHIFT 28 +# define RADEON_FACE_WIDTH_4_MASK (0xf << 24) +# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) + +#define RADEON_PP_TXOFFSET_0 0x1c5c +#define RADEON_PP_TXOFFSET_1 0x1c74 +#define RADEON_PP_TXOFFSET_2 0x1c8c +# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) +# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define RADEON_TXO_MACRO_LINEAR (0 << 2) +# define RADEON_TXO_MACRO_TILE (1 << 2) +# define RADEON_TXO_MICRO_LINEAR (0 << 3) +# define RADEON_TXO_MICRO_TILE_X2 (1 << 3) +# define RADEON_TXO_MICRO_TILE_OPT (2 << 3) +# define RADEON_TXO_OFFSET_MASK 0xffffffe0 +# define RADEON_TXO_OFFSET_SHIFT 5 + +#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ +#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 +#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 +#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc +#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 +#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 +#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 +#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 +#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c +#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 +#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 +#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 +#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c +#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 +#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 + +#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ +#define RADEON_PP_TEX_SIZE_1 0x1d0c +#define RADEON_PP_TEX_SIZE_2 0x1d14 +# define RADEON_TEX_USIZE_MASK (0x7ff << 0) +# define RADEON_TEX_USIZE_SHIFT 0 +# define RADEON_TEX_VSIZE_MASK (0x7ff << 16) +# define RADEON_TEX_VSIZE_SHIFT 16 +# define RADEON_SIGNED_RGB_MASK (1 << 30) +# define RADEON_SIGNED_RGB_SHIFT 30 +# define RADEON_SIGNED_ALPHA_MASK (1 << 31) +# define RADEON_SIGNED_ALPHA_SHIFT 31 +#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ +#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ +#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ +/* note: bits 13-5: 32 byte aligned stride of texture map */ + +#define RADEON_PP_TXCBLEND_0 0x1c60 +#define RADEON_PP_TXCBLEND_1 0x1c78 +#define RADEON_PP_TXCBLEND_2 0x1c90 +# define RADEON_COLOR_ARG_A_SHIFT 0 +# define RADEON_COLOR_ARG_A_MASK (0x1f << 0) +# define RADEON_COLOR_ARG_A_ZERO (0 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) +# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) +# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) +# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) +# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) +# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) +# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) +# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) +# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) +# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) +# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) +# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) +# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) +# define RADEON_COLOR_ARG_B_SHIFT 5 +# define RADEON_COLOR_ARG_B_MASK (0x1f << 5) +# define RADEON_COLOR_ARG_B_ZERO (0 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) +# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) +# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) +# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) +# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) +# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) +# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) +# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) +# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) +# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) +# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) +# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) +# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) +# define RADEON_COLOR_ARG_C_SHIFT 10 +# define RADEON_COLOR_ARG_C_MASK (0x1f << 10) +# define RADEON_COLOR_ARG_C_ZERO (0 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) +# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) +# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) +# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) +# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) +# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) +# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) +# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) +# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) +# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) +# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) +# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) +# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) +# define RADEON_COMP_ARG_A (1 << 15) +# define RADEON_COMP_ARG_A_SHIFT 15 +# define RADEON_COMP_ARG_B (1 << 16) +# define RADEON_COMP_ARG_B_SHIFT 16 +# define RADEON_COMP_ARG_C (1 << 17) +# define RADEON_COMP_ARG_C_SHIFT 17 +# define RADEON_BLEND_CTL_MASK (7 << 18) +# define RADEON_BLEND_CTL_ADD (0 << 18) +# define RADEON_BLEND_CTL_SUBTRACT (1 << 18) +# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) +# define RADEON_BLEND_CTL_BLEND (3 << 18) +# define RADEON_BLEND_CTL_DOT3 (4 << 18) +# define RADEON_SCALE_SHIFT 21 +# define RADEON_SCALE_MASK (3 << 21) +# define RADEON_SCALE_1X (0 << 21) +# define RADEON_SCALE_2X (1 << 21) +# define RADEON_SCALE_4X (2 << 21) +# define RADEON_CLAMP_TX (1 << 23) +# define RADEON_T0_EQ_TCUR (1 << 24) +# define RADEON_T1_EQ_TCUR (1 << 25) +# define RADEON_T2_EQ_TCUR (1 << 26) +# define RADEON_T3_EQ_TCUR (1 << 27) +# define RADEON_COLOR_ARG_MASK 0x1f +# define RADEON_COMP_ARG_SHIFT 15 +#define RADEON_PP_TXABLEND_0 0x1c64 +#define RADEON_PP_TXABLEND_1 0x1c7c +#define RADEON_PP_TXABLEND_2 0x1c94 +# define RADEON_ALPHA_ARG_A_SHIFT 0 +# define RADEON_ALPHA_ARG_A_MASK (0xf << 0) +# define RADEON_ALPHA_ARG_A_ZERO (0 << 0) +# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) +# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) +# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) +# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) +# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) +# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) +# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) +# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) +# define RADEON_ALPHA_ARG_B_SHIFT 4 +# define RADEON_ALPHA_ARG_B_MASK (0xf << 4) +# define RADEON_ALPHA_ARG_B_ZERO (0 << 4) +# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) +# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) +# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) +# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) +# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) +# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) +# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) +# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) +# define RADEON_ALPHA_ARG_C_SHIFT 8 +# define RADEON_ALPHA_ARG_C_MASK (0xf << 8) +# define RADEON_ALPHA_ARG_C_ZERO (0 << 8) +# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) +# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) +# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) +# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) +# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) +# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) +# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) +# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) +# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) +# define RADEON_ALPHA_ARG_MASK 0xf + +#define RADEON_PP_TFACTOR_0 0x1c68 +#define RADEON_PP_TFACTOR_1 0x1c80 +#define RADEON_PP_TFACTOR_2 0x1c98 + +#define RADEON_RB3D_BLENDCNTL 0x1c20 +# define RADEON_COMB_FCN_MASK (3 << 12) +# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) +# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) +# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) +# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) +# define RADEON_SRC_BLEND_GL_ZERO (32 << 16) +# define RADEON_SRC_BLEND_GL_ONE (33 << 16) +# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) +# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) +# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) +# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) +# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) +# define RADEON_SRC_BLEND_MASK (63 << 16) +# define RADEON_DST_BLEND_GL_ZERO (32 << 24) +# define RADEON_DST_BLEND_GL_ONE (33 << 24) +# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) +# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) +# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) +# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) +# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) +# define RADEON_DST_BLEND_MASK (63 << 24) +#define RADEON_RB3D_CNTL 0x1c3c +# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) +# define RADEON_PLANE_MASK_ENABLE (1 << 1) +# define RADEON_DITHER_ENABLE (1 << 2) +# define RADEON_ROUND_ENABLE (1 << 3) +# define RADEON_SCALE_DITHER_ENABLE (1 << 4) +# define RADEON_DITHER_INIT (1 << 5) +# define RADEON_ROP_ENABLE (1 << 6) +# define RADEON_STENCIL_ENABLE (1 << 7) +# define RADEON_Z_ENABLE (1 << 8) +# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) +# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) +# define RADEON_COLOR_FORMAT_RGB565 (4 << 10) +# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) +# define RADEON_COLOR_FORMAT_RGB332 (7 << 10) +# define RADEON_COLOR_FORMAT_Y8 (8 << 10) +# define RADEON_COLOR_FORMAT_RGB8 (9 << 10) +# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) +# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) +# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) +# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) +# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) +#define RADEON_RB3D_COLOROFFSET 0x1c40 +# define RADEON_COLOROFFSET_MASK 0xfffffff0 +#define RADEON_RB3D_COLORPITCH 0x1c48 +# define RADEON_COLORPITCH_MASK 0x000001ff8 +# define RADEON_COLOR_TILE_ENABLE (1 << 16) +# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) +# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_DEPTHOFFSET 0x1c24 +#define RADEON_RB3D_DEPTHPITCH 0x1c28 +# define RADEON_DEPTHPITCH_MASK 0x00001ff8 +# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) +# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) +# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) +#define RADEON_RB3D_PLANEMASK 0x1d84 +#define RADEON_RB3D_ROPCNTL 0x1d80 +# define RADEON_ROP_MASK (15 << 8) +# define RADEON_ROP_CLEAR (0 << 8) +# define RADEON_ROP_NOR (1 << 8) +# define RADEON_ROP_AND_INVERTED (2 << 8) +# define RADEON_ROP_COPY_INVERTED (3 << 8) +# define RADEON_ROP_AND_REVERSE (4 << 8) +# define RADEON_ROP_INVERT (5 << 8) +# define RADEON_ROP_XOR (6 << 8) +# define RADEON_ROP_NAND (7 << 8) +# define RADEON_ROP_AND (8 << 8) +# define RADEON_ROP_EQUIV (9 << 8) +# define RADEON_ROP_NOOP (10 << 8) +# define RADEON_ROP_OR_INVERTED (11 << 8) +# define RADEON_ROP_COPY (12 << 8) +# define RADEON_ROP_OR_REVERSE (13 << 8) +# define RADEON_ROP_OR (14 << 8) +# define RADEON_ROP_SET (15 << 8) +#define RADEON_RB3D_STENCILREFMASK 0x1d7c +# define RADEON_STENCIL_REF_SHIFT 0 +# define RADEON_STENCIL_REF_MASK (0xff << 0) +# define RADEON_STENCIL_MASK_SHIFT 16 +# define RADEON_STENCIL_VALUE_MASK (0xff << 16) +# define RADEON_STENCIL_WRITEMASK_SHIFT 24 +# define RADEON_STENCIL_WRITE_MASK (0xff << 24) +#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c +# define RADEON_DEPTH_FORMAT_MASK (0xf << 0) +# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) +# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) +# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) +# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) +# define RADEON_Z_TEST_NEVER (0 << 4) +# define RADEON_Z_TEST_LESS (1 << 4) +# define RADEON_Z_TEST_LEQUAL (2 << 4) +# define RADEON_Z_TEST_EQUAL (3 << 4) +# define RADEON_Z_TEST_GEQUAL (4 << 4) +# define RADEON_Z_TEST_GREATER (5 << 4) +# define RADEON_Z_TEST_NEQUAL (6 << 4) +# define RADEON_Z_TEST_ALWAYS (7 << 4) +# define RADEON_Z_TEST_MASK (7 << 4) +# define RADEON_STENCIL_TEST_NEVER (0 << 12) +# define RADEON_STENCIL_TEST_LESS (1 << 12) +# define RADEON_STENCIL_TEST_LEQUAL (2 << 12) +# define RADEON_STENCIL_TEST_EQUAL (3 << 12) +# define RADEON_STENCIL_TEST_GEQUAL (4 << 12) +# define RADEON_STENCIL_TEST_GREATER (5 << 12) +# define RADEON_STENCIL_TEST_NEQUAL (6 << 12) +# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) +# define RADEON_STENCIL_TEST_MASK (0x7 << 12) +# define RADEON_STENCIL_FAIL_KEEP (0 << 16) +# define RADEON_STENCIL_FAIL_ZERO (1 << 16) +# define RADEON_STENCIL_FAIL_REPLACE (2 << 16) +# define RADEON_STENCIL_FAIL_INC (3 << 16) +# define RADEON_STENCIL_FAIL_DEC (4 << 16) +# define RADEON_STENCIL_FAIL_INVERT (5 << 16) +# define RADEON_STENCIL_FAIL_MASK (0x7 << 16) +# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) +# define RADEON_STENCIL_ZPASS_ZERO (1 << 20) +# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) +# define RADEON_STENCIL_ZPASS_INC (3 << 20) +# define RADEON_STENCIL_ZPASS_DEC (4 << 20) +# define RADEON_STENCIL_ZPASS_INVERT (5 << 20) +# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) +# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) +# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) +# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) +# define RADEON_STENCIL_ZFAIL_INC (3 << 24) +# define RADEON_STENCIL_ZFAIL_DEC (4 << 24) +# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) +# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) +# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) +# define RADEON_FORCE_Z_DIRTY (1 << 29) +# define RADEON_Z_WRITE_ENABLE (1 << 30) +#define RADEON_RE_LINE_PATTERN 0x1cd0 +# define RADEON_LINE_PATTERN_MASK 0x0000ffff +# define RADEON_LINE_REPEAT_COUNT_SHIFT 16 +# define RADEON_LINE_PATTERN_START_SHIFT 24 +# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) +# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) +# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) +#define RADEON_RE_LINE_STATE 0x1cd4 +# define RADEON_LINE_CURRENT_PTR_SHIFT 0 +# define RADEON_LINE_CURRENT_COUNT_SHIFT 8 +#define RADEON_RE_MISC 0x26c4 +# define RADEON_STIPPLE_COORD_MASK 0x1f +# define RADEON_STIPPLE_X_OFFSET_SHIFT 0 +# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) +# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 +# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) +# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) +# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) +#define RADEON_RE_SOLID_COLOR 0x1c1c +#define RADEON_RE_TOP_LEFT 0x26c0 +# define RADEON_RE_LEFT_SHIFT 0 +# define RADEON_RE_TOP_SHIFT 16 +#define RADEON_RE_WIDTH_HEIGHT 0x1c44 +# define RADEON_RE_WIDTH_SHIFT 0 +# define RADEON_RE_HEIGHT_SHIFT 16 + +#define RADEON_SE_CNTL 0x1c4c +# define RADEON_FFACE_CULL_CW (0 << 0) +# define RADEON_FFACE_CULL_CCW (1 << 0) +# define RADEON_FFACE_CULL_DIR_MASK (1 << 0) +# define RADEON_BFACE_CULL (0 << 1) +# define RADEON_BFACE_SOLID (3 << 1) +# define RADEON_FFACE_CULL (0 << 3) +# define RADEON_FFACE_SOLID (3 << 3) +# define RADEON_FFACE_CULL_MASK (3 << 3) +# define RADEON_BADVTX_CULL_DISABLE (1 << 5) +# define RADEON_FLAT_SHADE_VTX_0 (0 << 6) +# define RADEON_FLAT_SHADE_VTX_1 (1 << 6) +# define RADEON_FLAT_SHADE_VTX_2 (2 << 6) +# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) +# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) +# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) +# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) +# define RADEON_DIFFUSE_SHADE_MASK (3 << 8) +# define RADEON_ALPHA_SHADE_SOLID (0 << 10) +# define RADEON_ALPHA_SHADE_FLAT (1 << 10) +# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) +# define RADEON_ALPHA_SHADE_MASK (3 << 10) +# define RADEON_SPECULAR_SHADE_SOLID (0 << 12) +# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) +# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) +# define RADEON_SPECULAR_SHADE_MASK (3 << 12) +# define RADEON_FOG_SHADE_SOLID (0 << 14) +# define RADEON_FOG_SHADE_FLAT (1 << 14) +# define RADEON_FOG_SHADE_GOURAUD (2 << 14) +# define RADEON_FOG_SHADE_MASK (3 << 14) +# define RADEON_ZBIAS_ENABLE_POINT (1 << 16) +# define RADEON_ZBIAS_ENABLE_LINE (1 << 17) +# define RADEON_ZBIAS_ENABLE_TRI (1 << 18) +# define RADEON_WIDELINE_ENABLE (1 << 20) +# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) +# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) +# define RADEON_VTX_PIX_CENTER_D3D (0 << 27) +# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) +# define RADEON_ROUND_MODE_TRUNC (0 << 28) +# define RADEON_ROUND_MODE_ROUND (1 << 28) +# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) +# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) +# define RADEON_ROUND_PREC_16TH_PIX (0 << 30) +# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) +# define RADEON_ROUND_PREC_4TH_PIX (2 << 30) +# define RADEON_ROUND_PREC_HALF_PIX (3 << 30) +#define R200_RE_CNTL 0x1c50 +# define R200_STIPPLE_ENABLE 0x1 +# define R200_SCISSOR_ENABLE 0x2 +# define R200_PATTERN_ENABLE 0x4 +# define R200_PERSPECTIVE_ENABLE 0x8 +# define R200_POINT_SMOOTH 0x20 +# define R200_VTX_STQ0_D3D 0x00010000 +# define R200_VTX_STQ1_D3D 0x00040000 +# define R200_VTX_STQ2_D3D 0x00100000 +# define R200_VTX_STQ3_D3D 0x00400000 +# define R200_VTX_STQ4_D3D 0x01000000 +# define R200_VTX_STQ5_D3D 0x04000000 +#define RADEON_SE_CNTL_STATUS 0x2140 +# define RADEON_VC_NO_SWAP (0 << 0) +# define RADEON_VC_16BIT_SWAP (1 << 0) +# define RADEON_VC_32BIT_SWAP (2 << 0) +# define RADEON_VC_HALF_DWORD_SWAP (3 << 0) +# define RADEON_TCL_BYPASS (1 << 8) +#define RADEON_SE_COORD_FMT 0x1c50 +# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) +# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) +# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) +# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) +# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) +# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) +# define RADEON_VTX_W0_NORMALIZE (1 << 12) +# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) +# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) +# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) +# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) +# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) +# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) +# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) +#define RADEON_SE_LINE_WIDTH 0x1db8 +#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c +# define RADEON_LIGHTING_ENABLE (1 << 0) +# define RADEON_LIGHT_IN_MODELSPACE (1 << 1) +# define RADEON_LOCAL_VIEWER (1 << 2) +# define RADEON_NORMALIZE_NORMALS (1 << 3) +# define RADEON_RESCALE_NORMALS (1 << 4) +# define RADEON_SPECULAR_LIGHTS (1 << 5) +# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) +# define RADEON_LIGHT_ALPHA (1 << 7) +# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) +# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) +# define RADEON_LM_SOURCE_STATE_PREMULT 0 +# define RADEON_LM_SOURCE_STATE_MULT 1 +# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 +# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 +# define RADEON_EMISSIVE_SOURCE_SHIFT 16 +# define RADEON_AMBIENT_SOURCE_SHIFT 18 +# define RADEON_DIFFUSE_SOURCE_SHIFT 20 +# define RADEON_SPECULAR_SOURCE_SHIFT 22 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 +#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 +#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 +#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c +#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 +#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c +#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c +# define RADEON_MODELVIEW_0_SHIFT 0 +# define RADEON_MODELVIEW_1_SHIFT 4 +# define RADEON_MODELVIEW_2_SHIFT 8 +# define RADEON_MODELVIEW_3_SHIFT 12 +# define RADEON_IT_MODELVIEW_0_SHIFT 16 +# define RADEON_IT_MODELVIEW_1_SHIFT 20 +# define RADEON_IT_MODELVIEW_2_SHIFT 24 +# define RADEON_IT_MODELVIEW_3_SHIFT 28 +#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 +# define RADEON_MODELPROJECT_0_SHIFT 0 +# define RADEON_MODELPROJECT_1_SHIFT 4 +# define RADEON_MODELPROJECT_2_SHIFT 8 +# define RADEON_MODELPROJECT_3_SHIFT 12 +# define RADEON_TEXMAT_0_SHIFT 16 +# define RADEON_TEXMAT_1_SHIFT 20 +# define RADEON_TEXMAT_2_SHIFT 24 +# define RADEON_TEXMAT_3_SHIFT 28 + + +#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 +# define RADEON_TCL_VTX_W0 (1 << 0) +# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) +# define RADEON_TCL_VTX_FP_ALPHA (1 << 2) +# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) +# define RADEON_TCL_VTX_FP_SPEC (1 << 4) +# define RADEON_TCL_VTX_FP_FOG (1 << 5) +# define RADEON_TCL_VTX_PK_SPEC (1 << 6) +# define RADEON_TCL_VTX_ST0 (1 << 7) +# define RADEON_TCL_VTX_ST1 (1 << 8) +# define RADEON_TCL_VTX_Q1 (1 << 9) +# define RADEON_TCL_VTX_ST2 (1 << 10) +# define RADEON_TCL_VTX_Q2 (1 << 11) +# define RADEON_TCL_VTX_ST3 (1 << 12) +# define RADEON_TCL_VTX_Q3 (1 << 13) +# define RADEON_TCL_VTX_Q0 (1 << 14) +# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 +# define RADEON_TCL_VTX_NORM0 (1 << 18) +# define RADEON_TCL_VTX_XY1 (1 << 27) +# define RADEON_TCL_VTX_Z1 (1 << 28) +# define RADEON_TCL_VTX_W1 (1 << 29) +# define RADEON_TCL_VTX_NORM1 (1 << 30) +# define RADEON_TCL_VTX_Z0 (1 << 31) + +#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 +# define RADEON_TCL_COMPUTE_XYZW (1 << 0) +# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) +# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) +# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) +# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) +# define RADEON_TCL_TEX_INPUT_TEX_0 0 +# define RADEON_TCL_TEX_INPUT_TEX_1 1 +# define RADEON_TCL_TEX_INPUT_TEX_2 2 +# define RADEON_TCL_TEX_INPUT_TEX_3 3 +# define RADEON_TCL_TEX_COMPUTED_TEX_0 8 +# define RADEON_TCL_TEX_COMPUTED_TEX_1 9 +# define RADEON_TCL_TEX_COMPUTED_TEX_2 10 +# define RADEON_TCL_TEX_COMPUTED_TEX_3 11 +# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 +# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 +# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 +# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 + +#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 +# define RADEON_LIGHT_0_ENABLE (1 << 0) +# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) +# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) +# define RADEON_LIGHT_0_IS_LOCAL (1 << 3) +# define RADEON_LIGHT_0_IS_SPOT (1 << 4) +# define RADEON_LIGHT_0_DUAL_CONE (1 << 5) +# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) +# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) +# define RADEON_LIGHT_0_SHIFT 0 +# define RADEON_LIGHT_1_ENABLE (1 << 16) +# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) +# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) +# define RADEON_LIGHT_1_IS_LOCAL (1 << 19) +# define RADEON_LIGHT_1_IS_SPOT (1 << 20) +# define RADEON_LIGHT_1_DUAL_CONE (1 << 21) +# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) +# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) +# define RADEON_LIGHT_1_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 +# define RADEON_LIGHT_2_SHIFT 0 +# define RADEON_LIGHT_3_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 +# define RADEON_LIGHT_4_SHIFT 0 +# define RADEON_LIGHT_5_SHIFT 16 +#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c +# define RADEON_LIGHT_6_SHIFT 0 +# define RADEON_LIGHT_7_SHIFT 16 + +#define RADEON_SE_TCL_SHININESS 0x2250 + +#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 +# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) +# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) +# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) +# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) +# define RADEON_TEXMAT_0_ENABLE (1 << 4) +# define RADEON_TEXMAT_1_ENABLE (1 << 5) +# define RADEON_TEXMAT_2_ENABLE (1 << 6) +# define RADEON_TEXMAT_3_ENABLE (1 << 7) +# define RADEON_TEXGEN_INPUT_MASK 0xf +# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 +# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 +# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 +# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 +# define RADEON_TEXGEN_INPUT_OBJ 4 +# define RADEON_TEXGEN_INPUT_EYE 5 +# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 +# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 +# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 +# define RADEON_TEXGEN_0_INPUT_SHIFT 16 +# define RADEON_TEXGEN_1_INPUT_SHIFT 20 +# define RADEON_TEXGEN_2_INPUT_SHIFT 24 +# define RADEON_TEXGEN_3_INPUT_SHIFT 28 + +#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 +# define RADEON_UCP_IN_CLIP_SPACE (1 << 0) +# define RADEON_UCP_IN_MODEL_SPACE (1 << 1) +# define RADEON_UCP_ENABLE_0 (1 << 2) +# define RADEON_UCP_ENABLE_1 (1 << 3) +# define RADEON_UCP_ENABLE_2 (1 << 4) +# define RADEON_UCP_ENABLE_3 (1 << 5) +# define RADEON_UCP_ENABLE_4 (1 << 6) +# define RADEON_UCP_ENABLE_5 (1 << 7) +# define RADEON_TCL_FOG_MASK (3 << 8) +# define RADEON_TCL_FOG_DISABLE (0 << 8) +# define RADEON_TCL_FOG_EXP (1 << 8) +# define RADEON_TCL_FOG_EXP2 (2 << 8) +# define RADEON_TCL_FOG_LINEAR (3 << 8) +# define RADEON_RNG_BASED_FOG (1 << 10) +# define RADEON_LIGHT_TWOSIDE (1 << 11) +# define RADEON_BLEND_OP_COUNT_MASK (7 << 12) +# define RADEON_BLEND_OP_COUNT_SHIFT 12 +# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) +# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) +# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) +# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) +# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) +# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) +# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) +# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) +# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) +# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) +# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) +# define RADEON_CULL_FRONT_IS_CW (0 << 28) +# define RADEON_CULL_FRONT_IS_CCW (1 << 28) +# define RADEON_CULL_FRONT (1 << 29) +# define RADEON_CULL_BACK (1 << 30) +# define RADEON_FORCE_W_TO_ONE (1 << 31) + +#define RADEON_SE_VPORT_XSCALE 0x1d98 +#define RADEON_SE_VPORT_XOFFSET 0x1d9c +#define RADEON_SE_VPORT_YSCALE 0x1da0 +#define RADEON_SE_VPORT_YOFFSET 0x1da4 +#define RADEON_SE_VPORT_ZSCALE 0x1da8 +#define RADEON_SE_VPORT_ZOFFSET 0x1dac +#define RADEON_SE_ZBIAS_FACTOR 0x1db0 +#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 + +#define RADEON_SE_VTX_FMT 0x2080 +# define RADEON_SE_VTX_FMT_XY 0x00000000 +# define RADEON_SE_VTX_FMT_W0 0x00000001 +# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 +# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 +# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 +# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 +# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 +# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 +# define RADEON_SE_VTX_FMT_ST0 0x00000080 +# define RADEON_SE_VTX_FMT_ST1 0x00000100 +# define RADEON_SE_VTX_FMT_Q1 0x00000200 +# define RADEON_SE_VTX_FMT_ST2 0x00000400 +# define RADEON_SE_VTX_FMT_Q2 0x00000800 +# define RADEON_SE_VTX_FMT_ST3 0x00001000 +# define RADEON_SE_VTX_FMT_Q3 0x00002000 +# define RADEON_SE_VTX_FMT_Q0 0x00004000 +# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 +# define RADEON_SE_VTX_FMT_N0 0x00040000 +# define RADEON_SE_VTX_FMT_XY1 0x08000000 +# define RADEON_SE_VTX_FMT_Z1 0x10000000 +# define RADEON_SE_VTX_FMT_W1 0x20000000 +# define RADEON_SE_VTX_FMT_N1 0x40000000 +# define RADEON_SE_VTX_FMT_Z 0x80000000 + +#define RADEON_SE_VF_CNTL 0x2084 +# define RADEON_VF_PRIM_TYPE_POINT_LIST 1 +# define RADEON_VF_PRIM_TYPE_LINE_LIST 2 +# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 +# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 +# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 +# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 +# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 +# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 +# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 +# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 +# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 +# define RADEON_VF_PRIM_TYPE_POLYGON 15 +# define RADEON_VF_PRIM_WALK_STATE (0<<4) +# define RADEON_VF_PRIM_WALK_INDEX (1<<4) +# define RADEON_VF_PRIM_WALK_LIST (2<<4) +# define RADEON_VF_PRIM_WALK_DATA (3<<4) +# define RADEON_VF_COLOR_ORDER_RGBA (1<<6) +# define RADEON_VF_RADEON_MODE (1<<8) +# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) +# define RADEON_VF_PROG_STREAM_ENA (1<<10) +# define RADEON_VF_INDEX_SIZE_SHIFT 11 +# define RADEON_VF_NUM_VERTICES_SHIFT 16 + +#define RADEON_SE_PORT_DATA0 0x2000 + +#define R200_SE_VAP_CNTL 0x2080 +# define R200_VAP_TCL_ENABLE 0x00000001 +# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 +# define R200_VAP_FORCE_W_TO_ONE 0x00010000 +# define R200_VAP_D3D_TEX_DEFAULT 0x00020000 +# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 +# define R200_VAP_VF_MAX_VTX_NUM (9 << 18) +# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 +#define R200_VF_MAX_VTX_INDX 0x210c +#define R200_VF_MIN_VTX_INDX 0x2110 +#define R200_SE_VTE_CNTL 0x20b0 +# define R200_VPORT_X_SCALE_ENA 0x00000001 +# define R200_VPORT_X_OFFSET_ENA 0x00000002 +# define R200_VPORT_Y_SCALE_ENA 0x00000004 +# define R200_VPORT_Y_OFFSET_ENA 0x00000008 +# define R200_VPORT_Z_SCALE_ENA 0x00000010 +# define R200_VPORT_Z_OFFSET_ENA 0x00000020 +# define R200_VTX_XY_FMT 0x00000100 +# define R200_VTX_Z_FMT 0x00000200 +# define R200_VTX_W0_FMT 0x00000400 +# define R200_VTX_W0_NORMALIZE 0x00000800 +# define R200_VTX_ST_DENORMALIZED 0x00001000 +#define R200_SE_VAP_CNTL_STATUS 0x2140 +# define R200_VC_NO_SWAP (0 << 0) +# define R200_VC_16BIT_SWAP (1 << 0) +# define R200_VC_32BIT_SWAP (2 << 0) +#define R200_PP_TXFILTER_0 0x2c00 +#define R200_PP_TXFILTER_1 0x2c20 +#define R200_PP_TXFILTER_2 0x2c40 +#define R200_PP_TXFILTER_3 0x2c60 +#define R200_PP_TXFILTER_4 0x2c80 +#define R200_PP_TXFILTER_5 0x2ca0 +# define R200_MAG_FILTER_NEAREST (0 << 0) +# define R200_MAG_FILTER_LINEAR (1 << 0) +# define R200_MAG_FILTER_MASK (1 << 0) +# define R200_MIN_FILTER_NEAREST (0 << 1) +# define R200_MIN_FILTER_LINEAR (1 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) +# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) +# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) +# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) +# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) +# define R200_MIN_FILTER_MASK (15 << 1) +# define R200_MAX_ANISO_1_TO_1 (0 << 5) +# define R200_MAX_ANISO_2_TO_1 (1 << 5) +# define R200_MAX_ANISO_4_TO_1 (2 << 5) +# define R200_MAX_ANISO_8_TO_1 (3 << 5) +# define R200_MAX_ANISO_16_TO_1 (4 << 5) +# define R200_MAX_ANISO_MASK (7 << 5) +# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) +# define R200_MAX_MIP_LEVEL_SHIFT 16 +# define R200_YUV_TO_RGB (1 << 20) +# define R200_YUV_TEMPERATURE_COOL (0 << 21) +# define R200_YUV_TEMPERATURE_HOT (1 << 21) +# define R200_YUV_TEMPERATURE_MASK (1 << 21) +# define R200_WRAPEN_S (1 << 22) +# define R200_CLAMP_S_WRAP (0 << 23) +# define R200_CLAMP_S_MIRROR (1 << 23) +# define R200_CLAMP_S_CLAMP_LAST (2 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) +# define R200_CLAMP_S_CLAMP_BORDER (4 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) +# define R200_CLAMP_S_CLAMP_GL (6 << 23) +# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) +# define R200_CLAMP_S_MASK (7 << 23) +# define R200_WRAPEN_T (1 << 26) +# define R200_CLAMP_T_WRAP (0 << 27) +# define R200_CLAMP_T_MIRROR (1 << 27) +# define R200_CLAMP_T_CLAMP_LAST (2 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) +# define R200_CLAMP_T_CLAMP_BORDER (4 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) +# define R200_CLAMP_T_CLAMP_GL (6 << 27) +# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) +# define R200_CLAMP_T_MASK (7 << 27) +# define R200_KILL_LT_ZERO (1 << 30) +# define R200_BORDER_MODE_OGL (0 << 31) +# define R200_BORDER_MODE_D3D (1 << 31) +#define R200_PP_TXFORMAT_0 0x2c04 +#define R200_PP_TXFORMAT_1 0x2c24 +#define R200_PP_TXFORMAT_2 0x2c44 +#define R200_PP_TXFORMAT_3 0x2c64 +#define R200_PP_TXFORMAT_4 0x2c84 +#define R200_PP_TXFORMAT_5 0x2ca4 +# define R200_TXFORMAT_I8 (0 << 0) +# define R200_TXFORMAT_AI88 (1 << 0) +# define R200_TXFORMAT_RGB332 (2 << 0) +# define R200_TXFORMAT_ARGB1555 (3 << 0) +# define R200_TXFORMAT_RGB565 (4 << 0) +# define R200_TXFORMAT_ARGB4444 (5 << 0) +# define R200_TXFORMAT_ARGB8888 (6 << 0) +# define R200_TXFORMAT_RGBA8888 (7 << 0) +# define R200_TXFORMAT_Y8 (8 << 0) +# define R200_TXFORMAT_AVYU4444 (9 << 0) +# define R200_TXFORMAT_VYUY422 (10 << 0) +# define R200_TXFORMAT_YVYU422 (11 << 0) +# define R200_TXFORMAT_DXT1 (12 << 0) +# define R200_TXFORMAT_DXT23 (14 << 0) +# define R200_TXFORMAT_DXT45 (15 << 0) +# define R200_TXFORMAT_ABGR8888 (22 << 0) +# define R200_TXFORMAT_FORMAT_MASK (31 << 0) +# define R200_TXFORMAT_FORMAT_SHIFT 0 +# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) +# define R200_TXFORMAT_NON_POWER2 (1 << 7) +# define R200_TXFORMAT_WIDTH_MASK (15 << 8) +# define R200_TXFORMAT_WIDTH_SHIFT 8 +# define R200_TXFORMAT_HEIGHT_MASK (15 << 12) +# define R200_TXFORMAT_HEIGHT_SHIFT 12 +# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ +# define R200_TXFORMAT_F5_WIDTH_SHIFT 16 +# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) +# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 +# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) +# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) +# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) +# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 +# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) +# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) +# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) +#define R200_PP_TXFORMAT_X_0 0x2c08 +#define R200_PP_TXFORMAT_X_1 0x2c28 +#define R200_PP_TXFORMAT_X_2 0x2c48 +#define R200_PP_TXFORMAT_X_3 0x2c68 +#define R200_PP_TXFORMAT_X_4 0x2c88 +#define R200_PP_TXFORMAT_X_5 0x2ca8 + +#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ +#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ +#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ +#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ +#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ +#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ + +#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ +#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ +#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ +#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ +#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ +#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ + +#define R200_PP_TXOFFSET_0 0x2d00 +# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) +# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) +# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) +# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define R200_TXO_MACRO_LINEAR (0 << 2) +# define R200_TXO_MACRO_TILE (1 << 2) +# define R200_TXO_MICRO_LINEAR (0 << 3) +# define R200_TXO_MICRO_TILE (1 << 3) +# define R200_TXO_OFFSET_MASK 0xffffffe0 +# define R200_TXO_OFFSET_SHIFT 5 +#define R200_PP_TXOFFSET_1 0x2d18 +#define R200_PP_TXOFFSET_2 0x2d30 +#define R200_PP_TXOFFSET_3 0x2d48 +#define R200_PP_TXOFFSET_4 0x2d60 +#define R200_PP_TXOFFSET_5 0x2d78 + +#define R200_PP_TFACTOR_0 0x2ee0 +#define R200_PP_TFACTOR_1 0x2ee4 +#define R200_PP_TFACTOR_2 0x2ee8 +#define R200_PP_TFACTOR_3 0x2eec +#define R200_PP_TFACTOR_4 0x2ef0 +#define R200_PP_TFACTOR_5 0x2ef4 + +#define R200_PP_TXCBLEND_0 0x2f00 +# define R200_TXC_ARG_A_ZERO (0) +# define R200_TXC_ARG_A_CURRENT_COLOR (2) +# define R200_TXC_ARG_A_CURRENT_ALPHA (3) +# define R200_TXC_ARG_A_DIFFUSE_COLOR (4) +# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) +# define R200_TXC_ARG_A_SPECULAR_COLOR (6) +# define R200_TXC_ARG_A_SPECULAR_ALPHA (7) +# define R200_TXC_ARG_A_TFACTOR_COLOR (8) +# define R200_TXC_ARG_A_TFACTOR_ALPHA (9) +# define R200_TXC_ARG_A_R0_COLOR (10) +# define R200_TXC_ARG_A_R0_ALPHA (11) +# define R200_TXC_ARG_A_R1_COLOR (12) +# define R200_TXC_ARG_A_R1_ALPHA (13) +# define R200_TXC_ARG_A_R2_COLOR (14) +# define R200_TXC_ARG_A_R2_ALPHA (15) +# define R200_TXC_ARG_A_R3_COLOR (16) +# define R200_TXC_ARG_A_R3_ALPHA (17) +# define R200_TXC_ARG_A_R4_COLOR (18) +# define R200_TXC_ARG_A_R4_ALPHA (19) +# define R200_TXC_ARG_A_R5_COLOR (20) +# define R200_TXC_ARG_A_R5_ALPHA (21) +# define R200_TXC_ARG_A_TFACTOR1_COLOR (26) +# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) +# define R200_TXC_ARG_A_MASK (31 << 0) +# define R200_TXC_ARG_A_SHIFT 0 +# define R200_TXC_ARG_B_ZERO (0 << 5) +# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) +# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) +# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) +# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) +# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) +# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) +# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) +# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) +# define R200_TXC_ARG_B_R0_COLOR (10 << 5) +# define R200_TXC_ARG_B_R0_ALPHA (11 << 5) +# define R200_TXC_ARG_B_R1_COLOR (12 << 5) +# define R200_TXC_ARG_B_R1_ALPHA (13 << 5) +# define R200_TXC_ARG_B_R2_COLOR (14 << 5) +# define R200_TXC_ARG_B_R2_ALPHA (15 << 5) +# define R200_TXC_ARG_B_R3_COLOR (16 << 5) +# define R200_TXC_ARG_B_R3_ALPHA (17 << 5) +# define R200_TXC_ARG_B_R4_COLOR (18 << 5) +# define R200_TXC_ARG_B_R4_ALPHA (19 << 5) +# define R200_TXC_ARG_B_R5_COLOR (20 << 5) +# define R200_TXC_ARG_B_R5_ALPHA (21 << 5) +# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) +# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) +# define R200_TXC_ARG_B_MASK (31 << 5) +# define R200_TXC_ARG_B_SHIFT 5 +# define R200_TXC_ARG_C_ZERO (0 << 10) +# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) +# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) +# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) +# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) +# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) +# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) +# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) +# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) +# define R200_TXC_ARG_C_R0_COLOR (10 << 10) +# define R200_TXC_ARG_C_R0_ALPHA (11 << 10) +# define R200_TXC_ARG_C_R1_COLOR (12 << 10) +# define R200_TXC_ARG_C_R1_ALPHA (13 << 10) +# define R200_TXC_ARG_C_R2_COLOR (14 << 10) +# define R200_TXC_ARG_C_R2_ALPHA (15 << 10) +# define R200_TXC_ARG_C_R3_COLOR (16 << 10) +# define R200_TXC_ARG_C_R3_ALPHA (17 << 10) +# define R200_TXC_ARG_C_R4_COLOR (18 << 10) +# define R200_TXC_ARG_C_R4_ALPHA (19 << 10) +# define R200_TXC_ARG_C_R5_COLOR (20 << 10) +# define R200_TXC_ARG_C_R5_ALPHA (21 << 10) +# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) +# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) +# define R200_TXC_ARG_C_MASK (31 << 10) +# define R200_TXC_ARG_C_SHIFT 10 +# define R200_TXC_COMP_ARG_A (1 << 16) +# define R200_TXC_COMP_ARG_A_SHIFT (16) +# define R200_TXC_BIAS_ARG_A (1 << 17) +# define R200_TXC_SCALE_ARG_A (1 << 18) +# define R200_TXC_NEG_ARG_A (1 << 19) +# define R200_TXC_COMP_ARG_B (1 << 20) +# define R200_TXC_COMP_ARG_B_SHIFT (20) +# define R200_TXC_BIAS_ARG_B (1 << 21) +# define R200_TXC_SCALE_ARG_B (1 << 22) +# define R200_TXC_NEG_ARG_B (1 << 23) +# define R200_TXC_COMP_ARG_C (1 << 24) +# define R200_TXC_COMP_ARG_C_SHIFT (24) +# define R200_TXC_BIAS_ARG_C (1 << 25) +# define R200_TXC_SCALE_ARG_C (1 << 26) +# define R200_TXC_NEG_ARG_C (1 << 27) +# define R200_TXC_OP_MADD (0 << 28) +# define R200_TXC_OP_CND0 (2 << 28) +# define R200_TXC_OP_LERP (3 << 28) +# define R200_TXC_OP_DOT3 (4 << 28) +# define R200_TXC_OP_DOT4 (5 << 28) +# define R200_TXC_OP_CONDITIONAL (6 << 28) +# define R200_TXC_OP_DOT2_ADD (7 << 28) +# define R200_TXC_OP_MASK (7 << 28) +#define R200_PP_TXCBLEND2_0 0x2f04 +# define R200_TXC_TFACTOR_SEL_SHIFT 0 +# define R200_TXC_TFACTOR_SEL_MASK 0x7 +# define R200_TXC_TFACTOR1_SEL_SHIFT 4 +# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXC_SCALE_SHIFT 8 +# define R200_TXC_SCALE_MASK (7 << 8) +# define R200_TXC_SCALE_1X (0 << 8) +# define R200_TXC_SCALE_2X (1 << 8) +# define R200_TXC_SCALE_4X (2 << 8) +# define R200_TXC_SCALE_8X (3 << 8) +# define R200_TXC_SCALE_INV2 (5 << 8) +# define R200_TXC_SCALE_INV4 (6 << 8) +# define R200_TXC_SCALE_INV8 (7 << 8) +# define R200_TXC_CLAMP_SHIFT 12 +# define R200_TXC_CLAMP_MASK (3 << 12) +# define R200_TXC_CLAMP_WRAP (0 << 12) +# define R200_TXC_CLAMP_0_1 (1 << 12) +# define R200_TXC_CLAMP_8_8 (2 << 12) +# define R200_TXC_OUTPUT_REG_MASK (7 << 16) +# define R200_TXC_OUTPUT_REG_NONE (0 << 16) +# define R200_TXC_OUTPUT_REG_R0 (1 << 16) +# define R200_TXC_OUTPUT_REG_R1 (2 << 16) +# define R200_TXC_OUTPUT_REG_R2 (3 << 16) +# define R200_TXC_OUTPUT_REG_R3 (4 << 16) +# define R200_TXC_OUTPUT_REG_R4 (5 << 16) +# define R200_TXC_OUTPUT_REG_R5 (6 << 16) +# define R200_TXC_OUTPUT_MASK_MASK (7 << 20) +# define R200_TXC_OUTPUT_MASK_RGB (0 << 20) +# define R200_TXC_OUTPUT_MASK_RG (1 << 20) +# define R200_TXC_OUTPUT_MASK_RB (2 << 20) +# define R200_TXC_OUTPUT_MASK_R (3 << 20) +# define R200_TXC_OUTPUT_MASK_GB (4 << 20) +# define R200_TXC_OUTPUT_MASK_G (5 << 20) +# define R200_TXC_OUTPUT_MASK_B (6 << 20) +# define R200_TXC_OUTPUT_MASK_NONE (7 << 20) +# define R200_TXC_REPL_NORMAL 0 +# define R200_TXC_REPL_RED 1 +# define R200_TXC_REPL_GREEN 2 +# define R200_TXC_REPL_BLUE 3 +# define R200_TXC_REPL_ARG_A_SHIFT 26 +# define R200_TXC_REPL_ARG_A_MASK (3 << 26) +# define R200_TXC_REPL_ARG_B_SHIFT 28 +# define R200_TXC_REPL_ARG_B_MASK (3 << 28) +# define R200_TXC_REPL_ARG_C_SHIFT 30 +# define R200_TXC_REPL_ARG_C_MASK (3 << 30) +#define R200_PP_TXABLEND_0 0x2f08 +# define R200_TXA_ARG_A_ZERO (0) +# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ +# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ +# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) +# define R200_TXA_ARG_A_DIFFUSE_BLUE (5) +# define R200_TXA_ARG_A_SPECULAR_ALPHA (6) +# define R200_TXA_ARG_A_SPECULAR_BLUE (7) +# define R200_TXA_ARG_A_TFACTOR_ALPHA (8) +# define R200_TXA_ARG_A_TFACTOR_BLUE (9) +# define R200_TXA_ARG_A_R0_ALPHA (10) +# define R200_TXA_ARG_A_R0_BLUE (11) +# define R200_TXA_ARG_A_R1_ALPHA (12) +# define R200_TXA_ARG_A_R1_BLUE (13) +# define R200_TXA_ARG_A_R2_ALPHA (14) +# define R200_TXA_ARG_A_R2_BLUE (15) +# define R200_TXA_ARG_A_R3_ALPHA (16) +# define R200_TXA_ARG_A_R3_BLUE (17) +# define R200_TXA_ARG_A_R4_ALPHA (18) +# define R200_TXA_ARG_A_R4_BLUE (19) +# define R200_TXA_ARG_A_R5_ALPHA (20) +# define R200_TXA_ARG_A_R5_BLUE (21) +# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) +# define R200_TXA_ARG_A_TFACTOR1_BLUE (27) +# define R200_TXA_ARG_A_MASK (31 << 0) +# define R200_TXA_ARG_A_SHIFT 0 +# define R200_TXA_ARG_B_ZERO (0 << 5) +# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ +# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ +# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) +# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) +# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) +# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) +# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) +# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) +# define R200_TXA_ARG_B_R0_ALPHA (10 << 5) +# define R200_TXA_ARG_B_R0_BLUE (11 << 5) +# define R200_TXA_ARG_B_R1_ALPHA (12 << 5) +# define R200_TXA_ARG_B_R1_BLUE (13 << 5) +# define R200_TXA_ARG_B_R2_ALPHA (14 << 5) +# define R200_TXA_ARG_B_R2_BLUE (15 << 5) +# define R200_TXA_ARG_B_R3_ALPHA (16 << 5) +# define R200_TXA_ARG_B_R3_BLUE (17 << 5) +# define R200_TXA_ARG_B_R4_ALPHA (18 << 5) +# define R200_TXA_ARG_B_R4_BLUE (19 << 5) +# define R200_TXA_ARG_B_R5_ALPHA (20 << 5) +# define R200_TXA_ARG_B_R5_BLUE (21 << 5) +# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) +# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) +# define R200_TXA_ARG_B_MASK (31 << 5) +# define R200_TXA_ARG_B_SHIFT 5 +# define R200_TXA_ARG_C_ZERO (0 << 10) +# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ +# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ +# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) +# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) +# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) +# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) +# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) +# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) +# define R200_TXA_ARG_C_R0_ALPHA (10 << 10) +# define R200_TXA_ARG_C_R0_BLUE (11 << 10) +# define R200_TXA_ARG_C_R1_ALPHA (12 << 10) +# define R200_TXA_ARG_C_R1_BLUE (13 << 10) +# define R200_TXA_ARG_C_R2_ALPHA (14 << 10) +# define R200_TXA_ARG_C_R2_BLUE (15 << 10) +# define R200_TXA_ARG_C_R3_ALPHA (16 << 10) +# define R200_TXA_ARG_C_R3_BLUE (17 << 10) +# define R200_TXA_ARG_C_R4_ALPHA (18 << 10) +# define R200_TXA_ARG_C_R4_BLUE (19 << 10) +# define R200_TXA_ARG_C_R5_ALPHA (20 << 10) +# define R200_TXA_ARG_C_R5_BLUE (21 << 10) +# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) +# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) +# define R200_TXA_ARG_C_MASK (31 << 10) +# define R200_TXA_ARG_C_SHIFT 10 +# define R200_TXA_COMP_ARG_A (1 << 16) +# define R200_TXA_COMP_ARG_A_SHIFT (16) +# define R200_TXA_BIAS_ARG_A (1 << 17) +# define R200_TXA_SCALE_ARG_A (1 << 18) +# define R200_TXA_NEG_ARG_A (1 << 19) +# define R200_TXA_COMP_ARG_B (1 << 20) +# define R200_TXA_COMP_ARG_B_SHIFT (20) +# define R200_TXA_BIAS_ARG_B (1 << 21) +# define R200_TXA_SCALE_ARG_B (1 << 22) +# define R200_TXA_NEG_ARG_B (1 << 23) +# define R200_TXA_COMP_ARG_C (1 << 24) +# define R200_TXA_COMP_ARG_C_SHIFT (24) +# define R200_TXA_BIAS_ARG_C (1 << 25) +# define R200_TXA_SCALE_ARG_C (1 << 26) +# define R200_TXA_NEG_ARG_C (1 << 27) +# define R200_TXA_OP_MADD (0 << 28) +# define R200_TXA_OP_CND0 (2 << 28) +# define R200_TXA_OP_LERP (3 << 28) +# define R200_TXA_OP_CONDITIONAL (6 << 28) +# define R200_TXA_OP_MASK (7 << 28) +#define R200_PP_TXABLEND2_0 0x2f0c +# define R200_TXA_TFACTOR_SEL_SHIFT 0 +# define R200_TXA_TFACTOR_SEL_MASK 0x7 +# define R200_TXA_TFACTOR1_SEL_SHIFT 4 +# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) +# define R200_TXA_SCALE_SHIFT 8 +# define R200_TXA_SCALE_MASK (7 << 8) +# define R200_TXA_SCALE_1X (0 << 8) +# define R200_TXA_SCALE_2X (1 << 8) +# define R200_TXA_SCALE_4X (2 << 8) +# define R200_TXA_SCALE_8X (3 << 8) +# define R200_TXA_SCALE_INV2 (5 << 8) +# define R200_TXA_SCALE_INV4 (6 << 8) +# define R200_TXA_SCALE_INV8 (7 << 8) +# define R200_TXA_CLAMP_SHIFT 12 +# define R200_TXA_CLAMP_MASK (3 << 12) +# define R200_TXA_CLAMP_WRAP (0 << 12) +# define R200_TXA_CLAMP_0_1 (1 << 12) +# define R200_TXA_CLAMP_8_8 (2 << 12) +# define R200_TXA_OUTPUT_REG_MASK (7 << 16) +# define R200_TXA_OUTPUT_REG_NONE (0 << 16) +# define R200_TXA_OUTPUT_REG_R0 (1 << 16) +# define R200_TXA_OUTPUT_REG_R1 (2 << 16) +# define R200_TXA_OUTPUT_REG_R2 (3 << 16) +# define R200_TXA_OUTPUT_REG_R3 (4 << 16) +# define R200_TXA_OUTPUT_REG_R4 (5 << 16) +# define R200_TXA_OUTPUT_REG_R5 (6 << 16) +# define R200_TXA_DOT_ALPHA (1 << 20) +# define R200_TXA_REPL_NORMAL 0 +# define R200_TXA_REPL_RED 1 +# define R200_TXA_REPL_GREEN 2 +# define R200_TXA_REPL_ARG_A_SHIFT 26 +# define R200_TXA_REPL_ARG_A_MASK (3 << 26) +# define R200_TXA_REPL_ARG_B_SHIFT 28 +# define R200_TXA_REPL_ARG_B_MASK (3 << 28) +# define R200_TXA_REPL_ARG_C_SHIFT 30 +# define R200_TXA_REPL_ARG_C_MASK (3 << 30) + +#define R200_SE_VTX_FMT_0 0x2088 +# define R200_VTX_XY 0 /* always have xy */ +# define R200_VTX_Z0 (1<<0) +# define R200_VTX_W0 (1<<1) +# define R200_VTX_WEIGHT_COUNT_SHIFT (2) +# define R200_VTX_PV_MATRIX_SEL (1<<5) +# define R200_VTX_N0 (1<<6) +# define R200_VTX_POINT_SIZE (1<<7) +# define R200_VTX_DISCRETE_FOG (1<<8) +# define R200_VTX_SHININESS_0 (1<<9) +# define R200_VTX_SHININESS_1 (1<<10) +# define R200_VTX_COLOR_NOT_PRESENT 0 +# define R200_VTX_PK_RGBA 1 +# define R200_VTX_FP_RGB 2 +# define R200_VTX_FP_RGBA 3 +# define R200_VTX_COLOR_MASK 3 +# define R200_VTX_COLOR_0_SHIFT 11 +# define R200_VTX_COLOR_1_SHIFT 13 +# define R200_VTX_COLOR_2_SHIFT 15 +# define R200_VTX_COLOR_3_SHIFT 17 +# define R200_VTX_COLOR_4_SHIFT 19 +# define R200_VTX_COLOR_5_SHIFT 21 +# define R200_VTX_COLOR_6_SHIFT 23 +# define R200_VTX_COLOR_7_SHIFT 25 +# define R200_VTX_XY1 (1<<28) +# define R200_VTX_Z1 (1<<29) +# define R200_VTX_W1 (1<<30) +# define R200_VTX_N1 (1<<31) +#define R200_SE_VTX_FMT_1 0x208c +# define R200_VTX_TEX0_COMP_CNT_SHIFT 0 +# define R200_VTX_TEX1_COMP_CNT_SHIFT 3 +# define R200_VTX_TEX2_COMP_CNT_SHIFT 6 +# define R200_VTX_TEX3_COMP_CNT_SHIFT 9 +# define R200_VTX_TEX4_COMP_CNT_SHIFT 12 +# define R200_VTX_TEX5_COMP_CNT_SHIFT 15 + +#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 +#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 +#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 +# define R200_OUTPUT_XYZW (1<<0) +# define R200_OUTPUT_COLOR_0 (1<<8) +# define R200_OUTPUT_COLOR_1 (1<<9) +# define R200_OUTPUT_TEX_0 (1<<16) +# define R200_OUTPUT_TEX_1 (1<<17) +# define R200_OUTPUT_TEX_2 (1<<18) +# define R200_OUTPUT_TEX_3 (1<<19) +# define R200_OUTPUT_TEX_4 (1<<20) +# define R200_OUTPUT_TEX_5 (1<<21) +# define R200_OUTPUT_TEX_MASK (0x3f<<16) +# define R200_OUTPUT_DISCRETE_FOG (1<<24) +# define R200_OUTPUT_PT_SIZE (1<<25) +# define R200_FORCE_INORDER_PROC (1<<31) +#define R200_PP_CNTL_X 0x2cc4 +#define R200_PP_TXMULTI_CTL_0 0x2c1c +#define R200_SE_VTX_STATE_CNTL 0x2180 +# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) + + /* Registers for CP and Microcode Engine */ +#define RADEON_CP_ME_RAM_ADDR 0x07d4 +#define RADEON_CP_ME_RAM_RADDR 0x07d8 +#define RADEON_CP_ME_RAM_DATAH 0x07dc +#define RADEON_CP_ME_RAM_DATAL 0x07e0 + +#define RADEON_CP_RB_BASE 0x0700 +#define RADEON_CP_RB_CNTL 0x0704 +#define RADEON_CP_RB_RPTR_ADDR 0x070c +#define RADEON_CP_RB_RPTR 0x0710 +#define RADEON_CP_RB_WPTR 0x0714 + +#define RADEON_CP_IB_BASE 0x0738 +#define RADEON_CP_IB_BUFSZ 0x073c + +#define RADEON_CP_CSQ_CNTL 0x0740 +# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) +# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) +# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) +# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) +# define RADEON_CSQ_PRIBM_INDBM (4 << 28) +# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) +#define RADEON_CP_CSQ_STAT 0x07f8 +# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) +# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) +# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) +# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) +#define RADEON_CP_CSQ_ADDR 0x07f0 +#define RADEON_CP_CSQ_DATA 0x07f4 +#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 +#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 + +#define RADEON_CP_RB_WPTR_DELAY 0x0718 +# define RADEON_PRE_WRITE_TIMER_SHIFT 0 +# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 + +#define RADEON_AIC_CNTL 0x01d0 +# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) +#define RADEON_AIC_LO_ADDR 0x01dc + + + + /* Constants */ +#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 +#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 + + + + /* CP packet types */ +#define RADEON_CP_PACKET0 0x00000000 +#define RADEON_CP_PACKET1 0x40000000 +#define RADEON_CP_PACKET2 0x80000000 +#define RADEON_CP_PACKET3 0xC0000000 +# define RADEON_CP_PACKET_MASK 0xC0000000 +# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 +# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) +# define RADEON_CP_PACKET0_REG_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff +# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 + +#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 + +#define RADEON_CP_PACKET3_NOP 0xC0001000 +#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 +#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 +#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 +#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 +#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 +#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 +#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 +#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 +#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 +#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 +#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 +#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 +#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 +#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 +#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 +#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 +#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 +#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 +#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 +#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 +#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 + + +#define RADEON_CP_VC_FRMT_XY 0x00000000 +#define RADEON_CP_VC_FRMT_W0 0x00000001 +#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 +#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 +#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 +#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 +#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 +#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 +#define RADEON_CP_VC_FRMT_ST0 0x00000080 +#define RADEON_CP_VC_FRMT_ST1 0x00000100 +#define RADEON_CP_VC_FRMT_Q1 0x00000200 +#define RADEON_CP_VC_FRMT_ST2 0x00000400 +#define RADEON_CP_VC_FRMT_Q2 0x00000800 +#define RADEON_CP_VC_FRMT_ST3 0x00001000 +#define RADEON_CP_VC_FRMT_Q3 0x00002000 +#define RADEON_CP_VC_FRMT_Q0 0x00004000 +#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 +#define RADEON_CP_VC_FRMT_N0 0x00040000 +#define RADEON_CP_VC_FRMT_XY1 0x08000000 +#define RADEON_CP_VC_FRMT_Z1 0x10000000 +#define RADEON_CP_VC_FRMT_W1 0x20000000 +#define RADEON_CP_VC_FRMT_N1 0x40000000 +#define RADEON_CP_VC_FRMT_Z 0x80000000 + +#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 +#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a +#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d +#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 +#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 +#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 +#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 +#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 +#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 +#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 +#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 +#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 +#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 + +#define RADEON_VS_MATRIX_0_ADDR 0 +#define RADEON_VS_MATRIX_1_ADDR 4 +#define RADEON_VS_MATRIX_2_ADDR 8 +#define RADEON_VS_MATRIX_3_ADDR 12 +#define RADEON_VS_MATRIX_4_ADDR 16 +#define RADEON_VS_MATRIX_5_ADDR 20 +#define RADEON_VS_MATRIX_6_ADDR 24 +#define RADEON_VS_MATRIX_7_ADDR 28 +#define RADEON_VS_MATRIX_8_ADDR 32 +#define RADEON_VS_MATRIX_9_ADDR 36 +#define RADEON_VS_MATRIX_10_ADDR 40 +#define RADEON_VS_MATRIX_11_ADDR 44 +#define RADEON_VS_MATRIX_12_ADDR 48 +#define RADEON_VS_MATRIX_13_ADDR 52 +#define RADEON_VS_MATRIX_14_ADDR 56 +#define RADEON_VS_MATRIX_15_ADDR 60 +#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 +#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 +#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 +#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 +#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 +#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 +#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 +#define RADEON_VS_UCP_ADDR 116 +#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 +#define RADEON_VS_FOG_PARAM_ADDR 123 +#define RADEON_VS_EYE_VECTOR_ADDR 124 + +#define RADEON_SS_LIGHT_DCD_ADDR 0 +#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 +#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 +#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 +#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 +#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 +#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 +#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 +#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 +#define RADEON_SS_SHININESS 60 + +#define RADEON_TV_MASTER_CNTL 0x0800 +# define RADEON_TV_ASYNC_RST (1 << 0) +# define RADEON_CRT_ASYNC_RST (1 << 1) +# define RADEON_RESTART_PHASE_FIX (1 << 3) +# define RADEON_TV_FIFO_ASYNC_RST (1 << 4) +# define RADEON_VIN_ASYNC_RST (1 << 5) +# define RADEON_AUD_ASYNC_RST (1 << 6) +# define RADEON_DVS_ASYNC_RST (1 << 7) +# define RADEON_CRT_FIFO_CE_EN (1 << 9) +# define RADEON_TV_FIFO_CE_EN (1 << 10) +# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) +# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) +# define RADEON_TV_ON (1 << 31) +#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 +# define RADEON_Y_RED_EN (1 << 0) +# define RADEON_C_GRN_EN (1 << 1) +# define RADEON_CMP_BLU_EN (1 << 2) +# define RADEON_DAC_DITHER_EN (1 << 3) +# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) +# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) +# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) +# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 +#define RADEON_TV_RGB_CNTL 0x0804 +# define RADEON_SWITCH_TO_BLUE (1 << 4) +# define RADEON_RGB_DITHER_EN (1 << 5) +# define RADEON_RGB_SRC_SEL_MASK (3 << 8) +# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) +# define RADEON_RGB_SRC_SEL_RMX (1 << 8) +# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) +# define RADEON_RGB_CONVERT_BY_PASS (1 << 10) +# define RADEON_UVRAM_READ_MARGIN_SHIFT 16 +# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 +# define RADEON_TVOUT_SCALE_EN (1 << 26) +#define RADEON_TV_SYNC_CNTL 0x0808 +# define RADEON_SYNC_OE (1 << 0) +# define RADEON_SYNC_OUT (1 << 1) +# define RADEON_SYNC_IN (1 << 2) +# define RADEON_SYNC_PUB (1 << 3) +# define RADEON_SYNC_PD (1 << 4) +# define RADEON_TV_SYNC_IO_DRIVE (1 << 5) +#define RADEON_TV_HTOTAL 0x080c +#define RADEON_TV_HDISP 0x0810 +#define RADEON_TV_HSTART 0x0818 +#define RADEON_TV_HCOUNT 0x081C +#define RADEON_TV_VTOTAL 0x0820 +#define RADEON_TV_VDISP 0x0824 +#define RADEON_TV_VCOUNT 0x0828 +#define RADEON_TV_FTOTAL 0x082c +#define RADEON_TV_FCOUNT 0x0830 +#define RADEON_TV_FRESTART 0x0834 +#define RADEON_TV_HRESTART 0x0838 +#define RADEON_TV_VRESTART 0x083c +#define RADEON_TV_HOST_READ_DATA 0x0840 +#define RADEON_TV_HOST_WRITE_DATA 0x0844 +#define RADEON_TV_HOST_RD_WT_CNTL 0x0848 +# define RADEON_HOST_FIFO_RD (1 << 12) +# define RADEON_HOST_FIFO_RD_ACK (1 << 13) +# define RADEON_HOST_FIFO_WT (1 << 14) +# define RADEON_HOST_FIFO_WT_ACK (1 << 15) +#define RADEON_TV_VSCALER_CNTL1 0x084c +# define RADEON_UV_INC_MASK 0xffff +# define RADEON_UV_INC_SHIFT 0 +# define RADEON_Y_W_EN (1 << 24) +# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ +# define RADEON_Y_DEL_W_SIG_SHIFT 26 +#define RADEON_TV_TIMING_CNTL 0x0850 +# define RADEON_H_INC_MASK 0xfff +# define RADEON_H_INC_SHIFT 0 +# define RADEON_REQ_Y_FIRST (1 << 19) +# define RADEON_FORCE_BURST_ALWAYS (1 << 21) +# define RADEON_UV_POST_SCALE_BYPASS (1 << 23) +# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 +#define RADEON_TV_VSCALER_CNTL2 0x0854 +# define RADEON_DITHER_MODE (1 << 0) +# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) +# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) +# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) +#define RADEON_TV_Y_FALL_CNTL 0x0858 +# define RADEON_Y_FALL_PING_PONG (1 << 16) +# define RADEON_Y_COEF_EN (1 << 17) +#define RADEON_TV_Y_RISE_CNTL 0x085c +# define RADEON_Y_RISE_PING_PONG (1 << 16) +#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 +#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 +# define RADEON_YUPSAMP_EN (1 << 0) +# define RADEON_UVUPSAMP_EN (1 << 2) +#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 +# define RADEON_Y_GAIN_LIMIT_SHIFT 0 +# define RADEON_UV_GAIN_LIMIT_SHIFT 16 +#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c +# define RADEON_Y_GAIN_SHIFT 0 +# define RADEON_UV_GAIN_SHIFT 16 +#define RADEON_TV_MODULATOR_CNTL1 0x0870 +# define RADEON_YFLT_EN (1 << 2) +# define RADEON_UVFLT_EN (1 << 3) +# define RADEON_ALT_PHASE_EN (1 << 6) +# define RADEON_SYNC_TIP_LEVEL (1 << 7) +# define RADEON_BLANK_LEVEL_SHIFT 8 +# define RADEON_SET_UP_LEVEL_SHIFT 16 +# define RADEON_SLEW_RATE_LIMIT (1 << 23) +# define RADEON_CY_FILT_BLEND_SHIFT 28 +#define RADEON_TV_MODULATOR_CNTL2 0x0874 +# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff +# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff +# define RADEON_TV_V_BURST_LEVEL_SHIFT 16 +#define RADEON_TV_CRC_CNTL 0x0890 +#define RADEON_TV_UV_ADR 0x08ac +# define RADEON_MAX_UV_ADR_MASK 0x000000ff +# define RADEON_MAX_UV_ADR_SHIFT 0 +# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 +# define RADEON_TABLE1_BOT_ADR_SHIFT 8 +# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 +# define RADEON_TABLE3_TOP_ADR_SHIFT 16 +# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 +# define RADEON_HCODE_TABLE_SEL_SHIFT 25 +# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 +# define RADEON_VCODE_TABLE_SEL_SHIFT 27 +# define RADEON_TV_MAX_FIFO_ADDR 0x1a7 +# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff +#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ +#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ +# define RADEON_TV_M0LO_MASK 0xff +# define RADEON_TV_M0HI_MASK 0x7 +# define RADEON_TV_M0HI_SHIFT 18 +# define RADEON_TV_N0LO_MASK 0x1ff +# define RADEON_TV_N0LO_SHIFT 8 +# define RADEON_TV_N0HI_MASK 0x3 +# define RADEON_TV_N0HI_SHIFT 21 +# define RADEON_TV_P_MASK 0xf +# define RADEON_TV_P_SHIFT 24 +# define RADEON_TV_SLIP_EN (1 << 23) +# define RADEON_TV_DTO_EN (1 << 28) +#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ +# define RADEON_TVPLL_RESET (1 << 1) +# define RADEON_TVPLL_SLEEP (1 << 3) +# define RADEON_TVPLL_REFCLK_SEL (1 << 4) +# define RADEON_TVPCP_SHIFT 8 +# define RADEON_TVPCP_MASK (7 << 8) +# define RADEON_TVPVG_SHIFT 11 +# define RADEON_TVPVG_MASK (7 << 11) +# define RADEON_TVPDC_SHIFT 14 +# define RADEON_TVPDC_MASK (3 << 14) +# define RADEON_TVPLL_TEST_DIS (1 << 31) +# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) + +#define RS400_DISP2_REQ_CNTL1 0xe30 +# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 +# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 +# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 +# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff +#define RS400_DISP2_REQ_CNTL2 0xe34 +# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 +# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff +# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 +# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff +#define RS400_DMIF_MEM_CNTL1 0xe38 +# define RS400_DISP2_START_ADR_SHIFT 0 +# define RS400_DISP2_START_ADR_MASK 0x3ff +# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 +# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff +# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 +# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff +#define RS400_DISP1_REQ_CNTL1 0xe3c +# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 +# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 +# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff +# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 +# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff + +#define RS690_MC_INDEX 0x78 +# define RS690_MC_INDEX_MASK 0x1ff +# define RS690_MC_INDEX_WR_EN (1 << 9) +# define RS690_MC_INDEX_WR_ACK 0x7f +#define RS690_MC_DATA 0x7c + +#define RS690_MC_FB_LOCATION 0x100 +#define RS690_MC_AGP_LOCATION 0x101 +#define RS690_MC_AGP_BASE 0x102 +#define RS690_MC_AGP_BASE_2 0x103 +#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 +#define RS690_MC_STATUS 0x90 +#define RS690_MC_STATUS_IDLE (1 << 0) + +#define RS600_MC_INDEX 0x78 +# define RS600_MC_INDEX_MASK 0xff +# define RS600_MC_INDEX_WR_EN (1 << 8) +# define RS600_MC_INDEX_WR_ACK 0xff +#define RS600_MC_DATA 0x7c + +#define RS600_MC_FB_LOCATION 0xA +#define RS600_MC_STATUS 0x0 +#define RS600_MC_STATUS_IDLE (1 << 0) + +#define AVIVO_MC_INDEX 0x0070 +#define R520_MC_STATUS 0x00 +# define R520_MC_STATUS_IDLE (1 << 1) +#define RV515_MC_STATUS 0x08 +# define RV515_MC_STATUS_IDLE (1 << 4) +#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 +#define AVIVO_MC_DATA 0x0074 + +#define RV515_MC_FB_LOCATION 0x1 +#define RV515_MC_AGP_LOCATION 0x2 +#define RV515_MC_AGP_BASE 0x3 +#define RV515_MC_AGP_BASE_2 0x4 +#define RV515_MC_CNTL 0x5 +# define RV515_MEM_NUM_CHANNELS_MASK 0x3 +#define R520_MC_FB_LOCATION 0x4 +#define R520_MC_AGP_LOCATION 0x5 +#define R520_MC_AGP_BASE 0x6 +#define R520_MC_AGP_BASE_2 0x7 +#define R520_MC_CNTL0 0x8 +# define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) +# define R520_MEM_NUM_CHANNELS_SHIFT 24 +# define R520_MC_CHANNEL_SIZE (1 << 23) + +#define R600_RAMCFG 0x2408 +# define R600_CHANSIZE (1 << 7) +# define R600_CHANSIZE_OVERRIDE (1 << 10) + +#define AVIVO_HDP_FB_LOCATION 0x134 + +#define AVIVO_VGA_RENDER_CONTROL 0x0300 +# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) +#define AVIVO_D1VGA_CONTROL 0x0330 +# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) +# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) +# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) +# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) +# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) +# define AVIVO_DVGA_CONTROL_ROTATE (1<<24) +#define AVIVO_D2VGA_CONTROL 0x0338 + +#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 +#define AVIVO_EXT1_PPLL_REF_DIV 0x404 +#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 +#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c + +#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 +#define AVIVO_EXT2_PPLL_REF_DIV 0x414 +#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 +#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c + +#define AVIVO_EXT1_PPLL_FB_DIV 0x430 +#define AVIVO_EXT2_PPLL_FB_DIV 0x434 + +#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 +#define AVIVO_EXT1_PPLL_POST_DIV 0x43c + +#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 +#define AVIVO_EXT2_PPLL_POST_DIV 0x444 + +#define AVIVO_EXT1_PPLL_CNTL 0x448 +#define AVIVO_EXT2_PPLL_CNTL 0x44c + +#define AVIVO_P1PLL_CNTL 0x450 +#define AVIVO_P2PLL_CNTL 0x454 +#define AVIVO_P1PLL_INT_SS_CNTL 0x458 +#define AVIVO_P2PLL_INT_SS_CNTL 0x45c +#define AVIVO_P1PLL_TMDSA_CNTL 0x460 +#define AVIVO_P2PLL_LVTMA_CNTL 0x464 + +#define AVIVO_PCLK_CRTC1_CNTL 0x480 +#define AVIVO_PCLK_CRTC2_CNTL 0x484 + +#define AVIVO_D1CRTC_H_TOTAL 0x6000 +#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 +#define AVIVO_D1CRTC_H_SYNC_A 0x6008 +#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c +#define AVIVO_D1CRTC_H_SYNC_B 0x6010 +#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 + +#define AVIVO_D1CRTC_V_TOTAL 0x6020 +#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 +#define AVIVO_D1CRTC_V_SYNC_A 0x6028 +#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c +#define AVIVO_D1CRTC_V_SYNC_B 0x6030 +#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 + +#define AVIVO_D1CRTC_CONTROL 0x6080 +# define AVIVO_CRTC_EN (1<<0) +#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 +#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 +#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c +#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 + +/* master controls */ +#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 +#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc + +#define AVIVO_D1GRPH_ENABLE 0x6100 +#define AVIVO_D1GRPH_CONTROL 0x6104 +# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) +# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) + +# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) + +# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) +# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) + +# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) +# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) + + +# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) + +# define AVIVO_D1GRPH_SWAP_RB (1<<16) +# define AVIVO_D1GRPH_TILED (1<<20) +# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) + +#define AVIVO_D1GRPH_LUT_SEL 0x6108 +#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 +#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 +#define AVIVO_D1GRPH_PITCH 0x6120 +#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 +#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 +#define AVIVO_D1GRPH_X_START 0x612c +#define AVIVO_D1GRPH_Y_START 0x6130 +#define AVIVO_D1GRPH_X_END 0x6134 +#define AVIVO_D1GRPH_Y_END 0x6138 +#define AVIVO_D1GRPH_UPDATE 0x6144 +# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) +#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 + +#define AVIVO_D1CUR_CONTROL 0x6400 +# define AVIVO_D1CURSOR_EN (1<<0) +# define AVIVO_D1CURSOR_MODE_SHIFT 8 +# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) +# define AVIVO_D1CURSOR_MODE_24BPP (0x2) +#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 +#define AVIVO_D1CUR_SIZE 0x6410 +#define AVIVO_D1CUR_POSITION 0x6414 +#define AVIVO_D1CUR_HOT_SPOT 0x6418 +#define AVIVO_D1CUR_UPDATE 0x6424 +# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) + +#define AVIVO_DC_LUT_RW_SELECT 0x6480 +#define AVIVO_DC_LUT_RW_MODE 0x6484 +#define AVIVO_DC_LUT_RW_INDEX 0x6488 +#define AVIVO_DC_LUT_SEQ_COLOR 0x648c +#define AVIVO_DC_LUT_PWL_DATA 0x6490 +#define AVIVO_DC_LUT_30_COLOR 0x6494 +#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 +#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c +#define AVIVO_DC_LUT_AUTOFILL 0x64a0 + +#define AVIVO_DC_LUTA_CONTROL 0x64c0 +#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 +#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 +#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc +#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 +#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 +#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 + +#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 +# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 +# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 +# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 +# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) +# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 +# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff + +#define AVIVO_D1MODE_DATA_FORMAT 0x6528 +# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) +#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c +#define AVIVO_D1MODE_VIEWPORT_START 0x6580 +#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 +#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 +#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c + +#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 +#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 +#define AVIVO_D1SCL_UPDATE 0x65cc +# define AVIVO_D1SCL_UPDATE_LOCK (1<<16) + +/* second crtc */ +#define AVIVO_D2CRTC_H_TOTAL 0x6800 +#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 +#define AVIVO_D2CRTC_H_SYNC_A 0x6808 +#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c +#define AVIVO_D2CRTC_H_SYNC_B 0x6810 +#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 + +#define AVIVO_D2CRTC_V_TOTAL 0x6820 +#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 +#define AVIVO_D2CRTC_V_SYNC_A 0x6828 +#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c +#define AVIVO_D2CRTC_V_SYNC_B 0x6830 +#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 + +#define AVIVO_D2CRTC_CONTROL 0x6880 +#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 +#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 +#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c +#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 + +#define AVIVO_D2GRPH_ENABLE 0x6900 +#define AVIVO_D2GRPH_CONTROL 0x6904 +#define AVIVO_D2GRPH_LUT_SEL 0x6908 +#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 +#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 +#define AVIVO_D2GRPH_PITCH 0x6920 +#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 +#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 +#define AVIVO_D2GRPH_X_START 0x692c +#define AVIVO_D2GRPH_Y_START 0x6930 +#define AVIVO_D2GRPH_X_END 0x6934 +#define AVIVO_D2GRPH_Y_END 0x6938 +#define AVIVO_D2GRPH_UPDATE 0x6944 +#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 + +#define AVIVO_D2CUR_CONTROL 0x6c00 +#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 +#define AVIVO_D2CUR_SIZE 0x6c10 +#define AVIVO_D2CUR_POSITION 0x6c14 + +#define AVIVO_D2MODE_DATA_FORMAT 0x6d28 +#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c +#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 +#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 +#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 +#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c + +#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 +#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 +#define AVIVO_D2SCL_UPDATE 0x6dcc + +#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 + +#define AVIVO_DACA_ENABLE 0x7800 +# define AVIVO_DAC_ENABLE (1 << 0) +#define AVIVO_DACA_SOURCE_SELECT 0x7804 +# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) +# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) +# define AVIVO_DAC_SOURCE_TV (2 << 0) + +#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACA_POWERDOWN 0x7850 +# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACA_POWERDOWN_RED (1 << 24) + +#define AVIVO_DACB_ENABLE 0x7a00 +#define AVIVO_DACB_SOURCE_SELECT 0x7a04 +#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) +# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) +#define AVIVO_DACB_POWERDOWN 0x7a50 +# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) +# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) +# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) +# define AVIVO_DACB_POWERDOWN_RED + +#define AVIVO_TMDSA_CNTL 0x7880 +# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) +# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) +#define AVIVO_TMDSA_SOURCE_SELECT 0x7884 +/* 78a8 appears to be some kind of (reasonably tolerant) clock? + * 78d0 definitely hits the transmitter, definitely clock. */ +/* MYSTERY1 This appears to control dithering? */ +#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) +#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 +# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) +#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 +#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define AVIVO_LVTMA_CNTL 0x7a80 +# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) +# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) +# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) +# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) +# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) +# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) +# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) +#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 +#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 +#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) +# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) + + + +#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 +# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) +# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) + +#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) +# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) +#define R500_LVTMA_CLOCK_ENABLE 0x7b00 +#define R600_LVTMA_CLOCK_ENABLE 0x7b04 + +#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 +#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) +# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) + +#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 +#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) +# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) + +#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 +#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 +# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) +# define AVIVO_LVTMA_SYNCEN (1 << 8) +# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) +# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) +# define AVIVO_LVTMA_DIGON (1 << 16) +# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) +# define AVIVO_LVTMA_DIGON_POL (1 << 18) +# define AVIVO_LVTMA_BLON (1 << 24) +# define AVIVO_LVTMA_BLON_OVRD (1 << 25) +# define AVIVO_LVTMA_BLON_POL (1 << 26) + +#define R500_LVTMA_PWRSEQ_STATE 0x7af4 +#define R600_LVTMA_PWRSEQ_STATE 0x7af8 +# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) +# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) +# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) +# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) +# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) +# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) + +#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 +# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) +# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 +# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 + +#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 + +#define AVIVO_GPIO_0 0x7e30 +#define AVIVO_GPIO_1 0x7e40 +#define AVIVO_GPIO_2 0x7e50 +#define AVIVO_GPIO_3 0x7e60 + +#define AVIVO_DC_GPIO_HPD_Y 0x7e9c + +#define AVIVO_I2C_STATUS 0x7d30 +# define AVIVO_I2C_STATUS_DONE (1 << 0) +# define AVIVO_I2C_STATUS_NACK (1 << 1) +# define AVIVO_I2C_STATUS_HALT (1 << 2) +# define AVIVO_I2C_STATUS_GO (1 << 3) +# define AVIVO_I2C_STATUS_MASK 0x7 +/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe + * DONE? */ +# define AVIVO_I2C_STATUS_CMD_RESET 0x7 +# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) +#define AVIVO_I2C_STOP 0x7d34 +#define AVIVO_I2C_START_CNTL 0x7d38 +# define AVIVO_I2C_START (1 << 8) +# define AVIVO_I2C_CONNECTOR0 (0 << 16) +# define AVIVO_I2C_CONNECTOR1 (1 << 16) +#define R520_I2C_START (1<<0) +#define R520_I2C_STOP (1<<1) +#define R520_I2C_RX (1<<2) +#define R520_I2C_EN (1<<8) +#define R520_I2C_DDC1 (0<<16) +#define R520_I2C_DDC2 (1<<16) +#define R520_I2C_DDC3 (2<<16) +#define R520_I2C_DDC_MASK (3<<16) +#define AVIVO_I2C_CONTROL2 0x7d3c +# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 +# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) +#define AVIVO_I2C_CONTROL3 0x7d40 +/* Reading is done 4 bytes at a time: read the bottom 8 bits from + * 7d44, four times in a row. + * Writing is a little more complex. First write DATA with + * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic + * magic number, zz is, I think, the slave address, and yy is the byte + * you want to write. */ +#define AVIVO_I2C_DATA 0x7d44 +#define R520_I2C_ADDR_COUNT_MASK (0x7) +#define R520_I2C_DATA_COUNT_SHIFT (8) +#define R520_I2C_DATA_COUNT_MASK (0xF00) +#define AVIVO_I2C_CNTL 0x7d50 +# define AVIVO_I2C_EN (1 << 0) +# define AVIVO_I2C_RESET (1 << 8) + +#define R600_GENERAL_PWRMGT 0x618 +# define R600_OPEN_DRAIN_PADS (1 << 11) + +#define R600_LOWER_GPIO_ENABLE 0x710 +#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 +#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c +#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 +#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 + +#define R600_MC_VM_FB_LOCATION 0x2180 +#define R600_MC_VM_AGP_TOP 0x2184 +#define R600_MC_VM_AGP_BOT 0x2188 +#define R600_MC_VM_AGP_BASE 0x218c +#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 +#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 +#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 + +#define R700_MC_VM_FB_LOCATION 0x2024 + +#define R600_HDP_NONSURFACE_BASE 0x2c04 + +#define R600_BUS_CNTL 0x5420 +#define R600_CONFIG_CNTL 0x5424 +#define R600_CONFIG_MEMSIZE 0x5428 +#define R600_CONFIG_F0_BASE 0x542C +#define R600_CONFIG_APER_SIZE 0x5430 + +#define R600_ROM_CNTL 0x1600 +# define R600_SCK_OVERWRITE (1 << 1) +# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 +# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) + +#define R600_BIOS_0_SCRATCH 0x1724 +#define R600_BIOS_1_SCRATCH 0x1728 +#define R600_BIOS_2_SCRATCH 0x172c +#define R600_BIOS_3_SCRATCH 0x1730 +#define R600_BIOS_4_SCRATCH 0x1734 +#define R600_BIOS_5_SCRATCH 0x1738 +#define R600_BIOS_6_SCRATCH 0x173c +#define R600_BIOS_7_SCRATCH 0x1740 + +#define R300_GB_TILE_CONFIG 0x4018 +# define R300_ENABLE_TILING (1 << 0) +# define R300_PIPE_COUNT_RV350 (0 << 1) +# define R300_PIPE_COUNT_R300 (3 << 1) +# define R300_PIPE_COUNT_R420_3P (6 << 1) +# define R300_PIPE_COUNT_R420 (7 << 1) +# define R300_TILE_SIZE_8 (0 << 4) +# define R300_TILE_SIZE_16 (1 << 4) +# define R300_TILE_SIZE_32 (2 << 4) +# define R300_SUBPIXEL_1_12 (0 << 16) +# define R300_SUBPIXEL_1_16 (1 << 16) +#define R300_GB_SELECT 0x401c +#define R300_GB_ENABLE 0x4008 +#define R300_GB_AA_CONFIG 0x4020 +#define R400_GB_PIPE_SELECT 0x402c +#define R300_GB_MSPOS0 0x4010 +# define R300_MS_X0_SHIFT 0 +# define R300_MS_Y0_SHIFT 4 +# define R300_MS_X1_SHIFT 8 +# define R300_MS_Y1_SHIFT 12 +# define R300_MS_X2_SHIFT 16 +# define R300_MS_Y2_SHIFT 20 +# define R300_MSBD0_Y_SHIFT 24 +# define R300_MSBD0_X_SHIFT 28 +#define R300_GB_MSPOS1 0x4014 +# define R300_MS_X3_SHIFT 0 +# define R300_MS_Y3_SHIFT 4 +# define R300_MS_X4_SHIFT 8 +# define R300_MS_Y4_SHIFT 12 +# define R300_MS_X5_SHIFT 16 +# define R300_MS_Y5_SHIFT 20 +# define R300_MSBD1_SHIFT 24 + +#define R300_GA_ENHANCE 0x4274 +# define R300_GA_DEADLOCK_CNTL (1 << 0) +# define R300_GA_FASTSYNC_CNTL (1 << 1) + +#define R300_GA_POLY_MODE 0x4288 +# define R300_FRONT_PTYPE_POINT (0 << 4) +# define R300_FRONT_PTYPE_LINE (1 << 4) +# define R300_FRONT_PTYPE_TRIANGE (2 << 4) +# define R300_BACK_PTYPE_POINT (0 << 7) +# define R300_BACK_PTYPE_LINE (1 << 7) +# define R300_BACK_PTYPE_TRIANGE (2 << 7) +#define R300_GA_ROUND_MODE 0x428c +# define R300_GEOMETRY_ROUND_TRUNC (0 << 0) +# define R300_GEOMETRY_ROUND_NEAREST (1 << 0) +# define R300_COLOR_ROUND_TRUNC (0 << 2) +# define R300_COLOR_ROUND_NEAREST (1 << 2) +#define R300_GA_COLOR_CONTROL 0x4278 +# define R300_RGB0_SHADING_SOLID (0 << 0) +# define R300_RGB0_SHADING_FLAT (1 << 0) +# define R300_RGB0_SHADING_GOURAUD (2 << 0) +# define R300_ALPHA0_SHADING_SOLID (0 << 2) +# define R300_ALPHA0_SHADING_FLAT (1 << 2) +# define R300_ALPHA0_SHADING_GOURAUD (2 << 2) +# define R300_RGB1_SHADING_SOLID (0 << 4) +# define R300_RGB1_SHADING_FLAT (1 << 4) +# define R300_RGB1_SHADING_GOURAUD (2 << 4) +# define R300_ALPHA1_SHADING_SOLID (0 << 6) +# define R300_ALPHA1_SHADING_FLAT (1 << 6) +# define R300_ALPHA1_SHADING_GOURAUD (2 << 6) +# define R300_RGB2_SHADING_SOLID (0 << 8) +# define R300_RGB2_SHADING_FLAT (1 << 8) +# define R300_RGB2_SHADING_GOURAUD (2 << 8) +# define R300_ALPHA2_SHADING_SOLID (0 << 10) +# define R300_ALPHA2_SHADING_FLAT (1 << 10) +# define R300_ALPHA2_SHADING_GOURAUD (2 << 10) +# define R300_RGB3_SHADING_SOLID (0 << 12) +# define R300_RGB3_SHADING_FLAT (1 << 12) +# define R300_RGB3_SHADING_GOURAUD (2 << 12) +# define R300_ALPHA3_SHADING_SOLID (0 << 14) +# define R300_ALPHA3_SHADING_FLAT (1 << 14) +# define R300_ALPHA3_SHADING_GOURAUD (2 << 14) +#define R300_GA_OFFSET 0x4290 + +#define R500_SU_REG_DEST 0x42c8 + +#define R300_VAP_CNTL_STATUS 0x2140 +# define R300_PVS_BYPASS (1 << 8) +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 +#define R300_VAP_CNTL 0x2080 +# define R300_PVS_NUM_SLOTS_SHIFT 0 +# define R300_PVS_NUM_CNTLRS_SHIFT 4 +# define R300_PVS_NUM_FPUS_SHIFT 8 +# define R300_VF_MAX_VTX_NUM_SHIFT 18 +# define R300_GL_CLIP_SPACE_DEF (0 << 22) +# define R300_DX_CLIP_SPACE_DEF (1 << 22) +# define R500_TCL_STATE_OPTIMIZATION (1 << 23) +#define R300_VAP_VTE_CNTL 0x20B0 +# define R300_VPORT_X_SCALE_ENA (1 << 0) +# define R300_VPORT_X_OFFSET_ENA (1 << 1) +# define R300_VPORT_Y_SCALE_ENA (1 << 2) +# define R300_VPORT_Y_OFFSET_ENA (1 << 3) +# define R300_VPORT_Z_SCALE_ENA (1 << 4) +# define R300_VPORT_Z_OFFSET_ENA (1 << 5) +# define R300_VTX_XY_FMT (1 << 8) +# define R300_VTX_Z_FMT (1 << 9) +# define R300_VTX_W0_FMT (1 << 10) +#define R300_VAP_VTX_STATE_CNTL 0x2180 +#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC +#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 +# define R300_DATA_TYPE_0_SHIFT 0 +# define R300_DATA_TYPE_FLOAT_1 0 +# define R300_DATA_TYPE_FLOAT_2 1 +# define R300_DATA_TYPE_FLOAT_3 2 +# define R300_DATA_TYPE_FLOAT_4 3 +# define R300_DATA_TYPE_BYTE 4 +# define R300_DATA_TYPE_D3DCOLOR 5 +# define R300_DATA_TYPE_SHORT_2 6 +# define R300_DATA_TYPE_SHORT_4 7 +# define R300_DATA_TYPE_VECTOR_3_TTT 8 +# define R300_DATA_TYPE_VECTOR_3_EET 9 +# define R300_SKIP_DWORDS_0_SHIFT 4 +# define R300_DST_VEC_LOC_0_SHIFT 8 +# define R300_LAST_VEC_0 (1 << 13) +# define R300_SIGNED_0 (1 << 14) +# define R300_NORMALIZE_0 (1 << 15) +# define R300_DATA_TYPE_1_SHIFT 16 +# define R300_SKIP_DWORDS_1_SHIFT 20 +# define R300_DST_VEC_LOC_1_SHIFT 24 +# define R300_LAST_VEC_1 (1 << 29) +# define R300_SIGNED_1 (1 << 30) +# define R300_NORMALIZE_1 (1 << 31) +#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 +# define R300_DATA_TYPE_2_SHIFT 0 +# define R300_SKIP_DWORDS_2_SHIFT 4 +# define R300_DST_VEC_LOC_2_SHIFT 8 +# define R300_LAST_VEC_2 (1 << 13) +# define R300_SIGNED_2 (1 << 14) +# define R300_NORMALIZE_2 (1 << 15) +# define R300_DATA_TYPE_3_SHIFT 16 +# define R300_SKIP_DWORDS_3_SHIFT 20 +# define R300_DST_VEC_LOC_3_SHIFT 24 +# define R300_LAST_VEC_3 (1 << 29) +# define R300_SIGNED_3 (1 << 30) +# define R300_NORMALIZE_3 (1 << 31) +#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 +# define R300_SWIZZLE_SELECT_X_0_SHIFT 0 +# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 +# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 +# define R300_SWIZZLE_SELECT_W_0_SHIFT 9 +# define R300_SWIZZLE_SELECT_X 0 +# define R300_SWIZZLE_SELECT_Y 1 +# define R300_SWIZZLE_SELECT_Z 2 +# define R300_SWIZZLE_SELECT_W 3 +# define R300_SWIZZLE_SELECT_FP_ZERO 4 +# define R300_SWIZZLE_SELECT_FP_ONE 5 +# define R300_WRITE_ENA_0_SHIFT 12 +# define R300_WRITE_ENA_X 1 +# define R300_WRITE_ENA_Y 2 +# define R300_WRITE_ENA_Z 4 +# define R300_WRITE_ENA_W 8 +# define R300_SWIZZLE_SELECT_X_1_SHIFT 16 +# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 +# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 +# define R300_SWIZZLE_SELECT_W_1_SHIFT 25 +# define R300_WRITE_ENA_1_SHIFT 28 +#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 +# define R300_SWIZZLE_SELECT_X_2_SHIFT 0 +# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 +# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 +# define R300_SWIZZLE_SELECT_W_2_SHIFT 9 +# define R300_WRITE_ENA_2_SHIFT 12 +# define R300_SWIZZLE_SELECT_X_3_SHIFT 16 +# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 +# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 +# define R300_SWIZZLE_SELECT_W_3_SHIFT 25 +# define R300_WRITE_ENA_3_SHIFT 28 +#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 +# define R300_PVS_FIRST_INST_SHIFT 0 +# define R300_PVS_XYZW_VALID_INST_SHIFT 10 +# define R300_PVS_LAST_INST_SHIFT 20 +#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 +# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 +#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 +#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 +/* PVS instructions */ +/* Opcode and dst instruction */ +#define R300_PVS_DST_OPCODE(x) (x << 0) +/* Vector ops */ +# define R300_VECTOR_NO_OP 0 +# define R300_VE_DOT_PRODUCT 1 +# define R300_VE_MULTIPLY 2 +# define R300_VE_ADD 3 +# define R300_VE_MULTIPLY_ADD 4 +# define R300_VE_DISTANCE_VECTOR 5 +# define R300_VE_FRACTION 6 +# define R300_VE_MAXIMUM 7 +# define R300_VE_MINIMUM 8 +# define R300_VE_SET_GREATER_THAN_EQUAL 9 +# define R300_VE_SET_LESS_THAN 10 +# define R300_VE_MULTIPLYX2_ADD 11 +# define R300_VE_MULTIPLY_CLAMP 12 +# define R300_VE_FLT2FIX_DX 13 +# define R300_VE_FLT2FIX_DX_RND 14 +/* R500 additions */ +# define R500_VE_PRED_SET_EQ_PUSH 15 +# define R500_VE_PRED_SET_GT_PUSH 16 +# define R500_VE_PRED_SET_GTE_PUSH 17 +# define R500_VE_PRED_SET_NEQ_PUSH 18 +# define R500_VE_COND_WRITE_EQ 19 +# define R500_VE_COND_WRITE_GT 20 +# define R500_VE_COND_WRITE_GTE 21 +# define R500_VE_COND_WRITE_NEQ 22 +# define R500_VE_COND_MUX_EQ 23 +# define R500_VE_COND_MUX_GT 24 +# define R500_VE_COND_MUX_GTE 25 +# define R500_VE_SET_GREATER_THAN 26 +# define R500_VE_SET_EQUAL 27 +# define R500_VE_SET_NOT_EQUAL 28 +/* Math ops */ +# define R300_MATH_NO_OP 0 +# define R300_ME_EXP_BASE2_DX 1 +# define R300_ME_LOG_BASE2_DX 2 +# define R300_ME_EXP_BASEE_FF 3 +# define R300_ME_LIGHT_COEFF_DX 4 +# define R300_ME_POWER_FUNC_FF 5 +# define R300_ME_RECIP_DX 6 +# define R300_ME_RECIP_FF 7 +# define R300_ME_RECIP_SQRT_DX 8 +# define R300_ME_RECIP_SQRT_FF 9 +# define R300_ME_MULTIPLY 10 +# define R300_ME_EXP_BASE2_FULL_DX 11 +# define R300_ME_LOG_BASE2_FULL_DX 12 +# define R300_ME_POWER_FUNC_FF_CLAMP_B 13 +# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 +# define R300_ME_POWER_FUNC_FF_CLAMP_01 15 +# define R300_ME_SIN 16 +# define R300_ME_COS 17 +/* R500 additions */ +# define R500_ME_LOG_BASE2_IEEE 18 +# define R500_ME_RECIP_IEEE 19 +# define R500_ME_RECIP_SQRT_IEEE 20 +# define R500_ME_PRED_SET_EQ 21 +# define R500_ME_PRED_SET_GT 22 +# define R500_ME_PRED_SET_GTE 23 +# define R500_ME_PRED_SET_NEQ 24 +# define R500_ME_PRED_SET_CLR 25 +# define R500_ME_PRED_SET_INV 26 +# define R500_ME_PRED_SET_POP 27 +# define R500_ME_PRED_SET_RESTORE 28 +/* macro */ +# define R300_PVS_MACRO_OP_2CLK_MADD 0 +# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 +#define R300_PVS_DST_MATH_INST (1 << 6) +#define R300_PVS_DST_MACRO_INST (1 << 7) +#define R300_PVS_DST_REG_TYPE(x) (x << 8) +# define R300_PVS_DST_REG_TEMPORARY 0 +# define R300_PVS_DST_REG_A0 1 +# define R300_PVS_DST_REG_OUT 2 +# define R500_PVS_DST_REG_OUT_REPL_X 3 +# define R300_PVS_DST_REG_ALT_TEMPORARY 4 +# define R300_PVS_DST_REG_INPUT 5 +#define R300_PVS_DST_ADDR_MODE_1 (1 << 12) +#define R300_PVS_DST_OFFSET(x) (x << 13) +#define R300_PVS_DST_WE_X (1 << 20) +#define R300_PVS_DST_WE_Y (1 << 21) +#define R300_PVS_DST_WE_Z (1 << 22) +#define R300_PVS_DST_WE_W (1 << 23) +#define R300_PVS_DST_VE_SAT (1 << 24) +#define R300_PVS_DST_ME_SAT (1 << 25) +#define R300_PVS_DST_PRED_ENABLE (1 << 26) +#define R300_PVS_DST_PRED_SENSE (1 << 27) +#define R300_PVS_DST_DUAL_MATH_OP (1 << 28) +#define R300_PVS_DST_ADDR_SEL(x) (x << 29) +#define R300_PVS_DST_ADDR_MODE_0 (1 << 31) +/* src operand instruction */ +#define R300_PVS_SRC_REG_TYPE(x) (x << 0) +# define R300_PVS_SRC_REG_TEMPORARY 0 +# define R300_PVS_SRC_REG_INPUT 1 +# define R300_PVS_SRC_REG_CONSTANT 2 +# define R300_PVS_SRC_REG_ALT_TEMPORARY 3 +#define R300_SPARE_0 (1 << 2) +#define R300_PVS_SRC_ABS_XYZW (1 << 3) +#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) +#define R300_PVS_SRC_OFFSET(x) (x << 5) +#define R300_PVS_SRC_SWIZZLE_X(x) (x << 13) +#define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16) +#define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19) +#define R300_PVS_SRC_SWIZZLE_W(x) (x << 22) +# define R300_PVS_SRC_SELECT_X 0 +# define R300_PVS_SRC_SELECT_Y 1 +# define R300_PVS_SRC_SELECT_Z 2 +# define R300_PVS_SRC_SELECT_W 3 +# define R300_PVS_SRC_SELECT_FORCE_0 4 +# define R300_PVS_SRC_SELECT_FORCE_1 5 +#define R300_PVS_SRC_NEG_X (1 << 25) +#define R300_PVS_SRC_NEG_Y (1 << 26) +#define R300_PVS_SRC_NEG_Z (1 << 27) +#define R300_PVS_SRC_NEG_W (1 << 28) +#define R300_PVS_SRC_ADDR_SEL(x) (x << 29) +#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) + +#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc +#define R300_VAP_OUT_VTX_FMT_0 0x2090 +# define R300_VTX_POS_PRESENT (1 << 0) +# define R300_VTX_COLOR_0_PRESENT (1 << 1) +# define R300_VTX_COLOR_1_PRESENT (1 << 2) +# define R300_VTX_COLOR_2_PRESENT (1 << 3) +# define R300_VTX_COLOR_3_PRESENT (1 << 4) +# define R300_VTX_PT_SIZE_PRESENT (1 << 16) +#define R300_VAP_OUT_VTX_FMT_1 0x2094 +# define R300_TEX_0_COMP_CNT_SHIFT 0 +# define R300_TEX_1_COMP_CNT_SHIFT 3 +# define R300_TEX_2_COMP_CNT_SHIFT 6 +# define R300_TEX_3_COMP_CNT_SHIFT 9 +# define R300_TEX_4_COMP_CNT_SHIFT 12 +# define R300_TEX_5_COMP_CNT_SHIFT 15 +# define R300_TEX_6_COMP_CNT_SHIFT 18 +# define R300_TEX_7_COMP_CNT_SHIFT 21 +#define R300_VAP_VTX_SIZE 0x20b4 +#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 +#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 +#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 +#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c +#define R300_VAP_CLIP_CNTL 0x221c +# define R300_UCP_ENA_0 (1 << 0) +# define R300_UCP_ENA_1 (1 << 1) +# define R300_UCP_ENA_2 (1 << 2) +# define R300_UCP_ENA_3 (1 << 3) +# define R300_UCP_ENA_4 (1 << 4) +# define R300_UCP_ENA_5 (1 << 5) +# define R300_PS_UCP_MODE_SHIFT 14 +# define R300_CLIP_DISABLE (1 << 16) +# define R300_UCP_CULL_ONLY_ENA (1 << 17) +# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 + +#define R500_VAP_INDEX_OFFSET 0x208c + +#define R300_SU_TEX_WRAP 0x42a0 +#define R300_SU_POLY_OFFSET_ENABLE 0x42b4 +#define R300_SU_CULL_MODE 0x42b8 +# define R300_CULL_FRONT (1 << 0) +# define R300_CULL_BACK (1 << 1) +# define R300_FACE_POS (0 << 2) +# define R300_FACE_NEG (1 << 2) +#define R300_SU_DEPTH_SCALE 0x42c0 +#define R300_SU_DEPTH_OFFSET 0x42c4 + +#define R300_RS_COUNT 0x4300 +# define R300_RS_COUNT_IT_COUNT_SHIFT 0 +# define R300_RS_COUNT_IC_COUNT_SHIFT 7 +# define R300_RS_COUNT_HIRES_EN (1 << 18) + +#define R300_RS_IP_0 0x4310 +#define R300_RS_IP_1 0x4314 +# define R300_RS_TEX_PTR(x) (x << 0) +# define R300_RS_COL_PTR(x) (x << 6) +# define R300_RS_COL_FMT(x) (x << 9) +# define R300_RS_COL_FMT_RGBA 0 +# define R300_RS_COL_FMT_RGB0 2 +# define R300_RS_COL_FMT_RGB1 3 +# define R300_RS_COL_FMT_000A 4 +# define R300_RS_COL_FMT_0000 5 +# define R300_RS_COL_FMT_0001 6 +# define R300_RS_COL_FMT_111A 8 +# define R300_RS_COL_FMT_1110 9 +# define R300_RS_COL_FMT_1111 10 +# define R300_RS_SEL_S(x) (x << 13) +# define R300_RS_SEL_T(x) (x << 16) +# define R300_RS_SEL_R(x) (x << 19) +# define R300_RS_SEL_Q(x) (x << 22) +# define R300_RS_SEL_C0 0 +# define R300_RS_SEL_C1 1 +# define R300_RS_SEL_C2 2 +# define R300_RS_SEL_C3 3 +# define R300_RS_SEL_K0 4 +# define R300_RS_SEL_K1 5 +#define R300_RS_INST_COUNT 0x4304 +# define R300_INST_COUNT_RS(x) (x << 0) +# define R300_RS_W_EN (1 << 4) +# define R300_TX_OFFSET_RS(x) (x << 5) +#define R300_RS_INST_0 0x4330 +#define R300_RS_INST_1 0x4334 +# define R300_INST_TEX_ID(x) (x << 0) +# define R300_RS_INST_TEX_CN_WRITE (1 << 3) +# define R300_INST_TEX_ADDR(x) (x << 6) + +#define R300_TX_INVALTAGS 0x4100 +#define R300_TX_FILTER0_0 0x4400 +#define R300_TX_FILTER0_1 0x4404 +# define R300_TX_CLAMP_S(x) (x << 0) +# define R300_TX_CLAMP_T(x) (x << 3) +# define R300_TX_CLAMP_R(x) (x << 6) +# define R300_TX_CLAMP_WRAP 0 +# define R300_TX_CLAMP_MIRROR 1 +# define R300_TX_CLAMP_CLAMP_LAST 2 +# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 +# define R300_TX_CLAMP_CLAMP_BORDER 4 +# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 +# define R300_TX_CLAMP_CLAMP_GL 6 +# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 +# define R300_TX_MAG_FILTER_NEAREST (1 << 9) +# define R300_TX_MIN_FILTER_NEAREST (1 << 11) +# define R300_TX_MAG_FILTER_LINEAR (2 << 9) +# define R300_TX_MIN_FILTER_LINEAR (2 << 11) +# define R300_TX_ID_SHIFT 28 +#define R300_TX_FILTER1_0 0x4440 +#define R300_TX_FILTER1_1 0x4444 +#define R300_TX_FORMAT0_0 0x4480 +#define R300_TX_FORMAT0_1 0x4484 +# define R300_TXWIDTH_SHIFT 0 +# define R300_TXHEIGHT_SHIFT 11 +# define R300_NUM_LEVELS_SHIFT 26 +# define R300_NUM_LEVELS_MASK 0x +# define R300_TXPROJECTED (1 << 30) +# define R300_TXPITCH_EN (1 << 31) +#define R300_TX_FORMAT1_0 0x44c0 +#define R300_TX_FORMAT1_1 0x44c4 +# define R300_TX_FORMAT_X8 0x0 +# define R300_TX_FORMAT_X16 0x1 +# define R300_TX_FORMAT_Y4X4 0x2 +# define R300_TX_FORMAT_Y8X8 0x3 +# define R300_TX_FORMAT_Y16X16 0x4 +# define R300_TX_FORMAT_Z3Y3X2 0x5 +# define R300_TX_FORMAT_Z5Y6X5 0x6 +# define R300_TX_FORMAT_Z6Y5X5 0x7 +# define R300_TX_FORMAT_Z11Y11X10 0x8 +# define R300_TX_FORMAT_Z10Y11X11 0x9 +# define R300_TX_FORMAT_W4Z4Y4X4 0xA +# define R300_TX_FORMAT_W1Z5Y5X5 0xB +# define R300_TX_FORMAT_W8Z8Y8X8 0xC +# define R300_TX_FORMAT_W2Z10Y10X10 0xD +# define R300_TX_FORMAT_W16Z16Y16X16 0xE +# define R300_TX_FORMAT_DXT1 0xF +# define R300_TX_FORMAT_DXT3 0x10 +# define R300_TX_FORMAT_DXT5 0x11 +# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ +# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ +# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ +# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ +# define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ +# define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ +# define R300_TX_FORMAT_X24_Y8 0x1e +# define R300_TX_FORMAT_X32 0x1e + /* Floating point formats */ + /* Note - hardware supports both 16 and 32 bit floating point */ +# define R300_TX_FORMAT_FL_I16 0x18 +# define R300_TX_FORMAT_FL_I16A16 0x19 +# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A +# define R300_TX_FORMAT_FL_I32 0x1B +# define R300_TX_FORMAT_FL_I32A32 0x1C +# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D + /* alpha modes, convenience mostly */ + /* if you have alpha, pick constant appropriate to the + number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ +# define R300_TX_FORMAT_ALPHA_1CH 0x000 +# define R300_TX_FORMAT_ALPHA_2CH 0x200 +# define R300_TX_FORMAT_ALPHA_4CH 0x600 +# define R300_TX_FORMAT_ALPHA_NONE 0xA00 + /* Swizzling */ + /* constants */ +# define R300_TX_FORMAT_X 0 +# define R300_TX_FORMAT_Y 1 +# define R300_TX_FORMAT_Z 2 +# define R300_TX_FORMAT_W 3 +# define R300_TX_FORMAT_ZERO 4 +# define R300_TX_FORMAT_ONE 5 + /* 2.0*Z, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_Z 6 + /* 2.0*W, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_W 7 + +# define R300_TX_FORMAT_B_SHIFT 18 +# define R300_TX_FORMAT_G_SHIFT 15 +# define R300_TX_FORMAT_R_SHIFT 12 +# define R300_TX_FORMAT_A_SHIFT 9 + + /* Convenience macro to take care of layout and swizzling */ +# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ + ((R300_TX_FORMAT_##B)<pipe_winsys, + (struct amd_pipe_winsys*)amd_context->pipe_winsys); + } else { + pipe = amd_create_softpipe(amd_context); + } amd_context->st_context = st_create_context(pipe, visual, shared_st_context); driInitExtensions(amd_context->st_context->ctx, -- cgit v1.2.3 From e9b08e7373c00306bce398ea8d34f42e54f98c6d Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 21:28:23 -0800 Subject: Make r300 and amd build in scons. --- SConstruct | 4 ++-- src/gallium/drivers/r300/SConscript | 17 +++++++++++++++++ src/gallium/drivers/r300/r300_blit.h | 1 + src/gallium/winsys/drm/amd/SConscript | 29 +++++++++++++++++++++++++++++ 4 files changed, 49 insertions(+), 2 deletions(-) create mode 100644 src/gallium/drivers/r300/SConscript create mode 100644 src/gallium/winsys/drm/amd/SConscript (limited to 'src/gallium/drivers/r300') diff --git a/SConstruct b/SConstruct index 88cdffa504..a22b9483da 100644 --- a/SConstruct +++ b/SConstruct @@ -46,9 +46,9 @@ common.AddOptions(opts) opts.Add(ListOption('statetrackers', 'state trackers to build', default_statetrackers, ['mesa', 'python'])) opts.Add(ListOption('drivers', 'pipe drivers to build', default_drivers, - ['softpipe', 'failover', 'i915simple', 'i965simple', 'cell', 'trace'])) + ['softpipe', 'failover', 'i915simple', 'i965simple', 'cell', 'trace', 'r300'])) opts.Add(ListOption('winsys', 'winsys drivers to build', default_winsys, - ['xlib', 'intel', 'gdi'])) + ['xlib', 'intel', 'gdi', 'amd'])) opts.Add(EnumOption('MSVS_VERSION', 'MS Visual C++ version', None, allowed_values=('7.1', '8.0', '9.0'))) diff --git a/src/gallium/drivers/r300/SConscript b/src/gallium/drivers/r300/SConscript new file mode 100644 index 0000000000..18684c3e7f --- /dev/null +++ b/src/gallium/drivers/r300/SConscript @@ -0,0 +1,17 @@ +Import('*') + +env = env.Clone() + +r300 = env.ConvenienceLibrary( + target = 'r300', + source = [ + 'r300_blit.c', + 'r300_clear.c', + 'r300_context.c', + 'r300_screen.c', + 'r300_state.c', + 'r300_surface.c', + ]) + +Export('r300') + diff --git a/src/gallium/drivers/r300/r300_blit.h b/src/gallium/drivers/r300/r300_blit.h index 09cb566b95..740cbcdea5 100644 --- a/src/gallium/drivers/r300/r300_blit.h +++ b/src/gallium/drivers/r300/r300_blit.h @@ -25,6 +25,7 @@ #include "pipe/p_state.h" +#include "r300_context.h" #include "r300_cs.h" /* Forward declarations. */ diff --git a/src/gallium/winsys/drm/amd/SConscript b/src/gallium/winsys/drm/amd/SConscript new file mode 100644 index 0000000000..a4856da23c --- /dev/null +++ b/src/gallium/winsys/drm/amd/SConscript @@ -0,0 +1,29 @@ +Import('*') + +if 'mesa' in env['statetrackers']: + + env = drienv.Clone() + + DRIVER_SOURCES = [ + 'amd_buffer.c', + 'amd_context.c', + 'amd_screen.c', + 'amd_winsys_softpipe.c', + ] + + sources = \ + COMMON_GALLIUM_SOURCES + \ + DRIVER_SOURCES + + drivers = [ + softpipe, + r300 + ] + + # TODO: write a wrapper function http://www.scons.org/wiki/WrapperFunctions + env.SharedLibrary( + target ='amd_dri.so', + source = sources, + LIBS = drivers + mesa + auxiliaries + env['LIBS'], + ) + -- cgit v1.2.3 From 4aaaecbfa6fa810899ef04de44f9f79ec4d8134f Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 9 Jan 2009 21:50:56 -0800 Subject: A bit of r300 cleanup. --- src/gallium/drivers/r300/r300_context.c | 7 +------ src/gallium/drivers/r300/r300_context.h | 11 +++++++++-- src/gallium/drivers/r300/r300_surface.h | 2 -- src/gallium/winsys/drm/amd/amd_context.c | 6 ++++-- 4 files changed, 14 insertions(+), 12 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 68751dae17..4050faa74a 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -41,12 +41,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->winsys = amd_winsys; r300->context.winsys = winsys; - if (screen) { - r300->context.screen = screen; - } else { - /* XXX second arg should be pciid, find a way to get it from winsys */ - r300->context.screen = r300_create_screen(winsys, 0x0); - } + r300->context.screen = screen; r300->context.destroy = r300_destroy_context; diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index ae2dab13ff..8393198200 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -23,9 +23,9 @@ #ifndef R300_CONTEXT_H #define R300_CONTEXT_H +#include "draw/draw_context.h" #include "pipe/p_context.h" - -#include "r300_surface.h" +#include "util/u_memory.h" struct r300_context { /* Parent class */ @@ -47,4 +47,11 @@ static struct r300_context* r300_context(struct pipe_context* context) { return (struct r300_context*)context; } +/* Context initialization. */ +void r300_init_surface_functions(struct r300_context* r300); + +struct pipe_context* r300_create_context(struct pipe_screen* screen, + struct pipe_winsys* winsys, + struct amd_winsys* amd_winsys); + #endif /* R300_CONTEXT_H */ \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index 29858eb541..0b2fd0b32b 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -31,6 +31,4 @@ #include "r300_blit.h" #include "r300_context.h" -void r300_init_surface_functions(struct r300_context* r300); - #endif /* R300_SURFACE_H */ diff --git a/src/gallium/winsys/drm/amd/amd_context.c b/src/gallium/winsys/drm/amd/amd_context.c index faca7d0c4b..5127cdf261 100644 --- a/src/gallium/winsys/drm/amd/amd_context.c +++ b/src/gallium/winsys/drm/amd/amd_context.c @@ -243,8 +243,10 @@ GLboolean amd_context_create(const __GLcontextModes *visual, } if (GL_TRUE) { - /* XXX "NULL" is a struct pipe_screen* just in case we ever need it... */ - pipe = r300_create_context(NULL, amd_context->pipe_winsys, + amd_context->pipe_screen = r300_create_screen(amd_context->pipe_winsys, + 0x0); + pipe = r300_create_context(amd_context->pipe_screen, + amd_context->pipe_winsys, (struct amd_pipe_winsys*)amd_context->pipe_winsys); } else { pipe = amd_create_softpipe(amd_context); -- cgit v1.2.3 From fbeeb6675733f5b2da36d40b0142dadf8cc953b4 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 12 Jan 2009 01:40:50 -0800 Subject: r300, amd: Make everything build. (Not necessarily work, mind you.) Lots of structural work, especially in getting the two parts to talk nicely. Todo: - Get damn blitter working. - Add CS flush. - Reverse order of above two items. --- configs/default | 2 +- src/gallium/drivers/r300/r300_blit.c | 2 +- src/gallium/drivers/r300/r300_context.c | 6 +-- src/gallium/drivers/r300/r300_context.h | 13 ++--- src/gallium/drivers/r300/r300_cs.h | 30 ++++++----- src/gallium/drivers/r300/r300_screen.c | 4 +- src/gallium/drivers/r300/r300_winsys.h | 87 ++++++++++++++++++++++++++++++++ src/gallium/winsys/drm/amd/Makefile | 6 ++- src/gallium/winsys/drm/amd/amd_context.c | 8 ++- src/gallium/winsys/drm/amd/amd_context.h | 2 + src/gallium/winsys/drm/amd/amd_r300.c | 55 ++++++++++++++++++++ src/gallium/winsys/drm/amd/amd_r300.h | 29 +++++++++++ 12 files changed, 208 insertions(+), 36 deletions(-) create mode 100644 src/gallium/drivers/r300/r300_winsys.h create mode 100644 src/gallium/winsys/drm/amd/amd_r300.c create mode 100644 src/gallium/winsys/drm/amd/amd_r300.h (limited to 'src/gallium/drivers/r300') diff --git a/configs/default b/configs/default index 40f3a2a02d..333f0fe985 100644 --- a/configs/default +++ b/configs/default @@ -91,7 +91,7 @@ EGL_DRIVERS_DIRS = demo # Gallium directories and GALLIUM_AUXILIARY_DIRS = draw translate cso_cache pipebuffer tgsi sct rtasm util GALLIUM_AUXILIARIES = $(foreach DIR,$(GALLIUM_AUXILIARY_DIRS),$(TOP)/src/gallium/auxiliary/$(DIR)/lib$(DIR).a) -GALLIUM_DRIVER_DIRS = softpipe i915simple i965simple nv04 nv10 nv20 nv30 nv40 nv50 failover trace +GALLIUM_DRIVER_DIRS = softpipe i915simple i965simple nv04 nv10 nv20 nv30 nv40 nv50 failover r300 GALLIUM_DRIVERS = $(foreach DIR,$(GALLIUM_DRIVER_DIRS),$(TOP)/src/gallium/drivers/$(DIR)/lib$(DIR).a) GALLIUM_WINSYS_DIRS = xlib egl_xlib diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index c404a667b1..b8ddf6677f 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -79,7 +79,7 @@ int r300_fill_blit(struct r300_context* r300, OUT_CS_REG(RADEON_DP_CNTL, RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM); OUT_CS_REG(RADEON_DST_PITCH_OFFSET, 0x0); - /* XXX fix this shit -> OUT_RELOC(dst, 0, RADEON_GEM_DOMAIN_VRAM) */ + OUT_CS_RELOC(dst_buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); /* Do the actual paint. */ OUT_CS_REG(RADEON_DST_Y_X, (y << 16) | x); diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 4050faa74a..b9a9c2e21c 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -32,16 +32,16 @@ static void r300_destroy_context(struct pipe_context* context) { struct pipe_context* r300_create_context(struct pipe_screen* screen, struct pipe_winsys* winsys, - struct amd_winsys* amd_winsys) + struct r300_winsys* r300_winsys) { struct r300_context* r300 = CALLOC_STRUCT(r300_context); if (!r300) return NULL; - r300->winsys = amd_winsys; + r300->winsys = r300_winsys; r300->context.winsys = winsys; - r300->context.screen = screen; + r300->context.screen = r300_create_screen(winsys, 0x0); r300->context.destroy = r300_destroy_context; diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 8393198200..119d46af58 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -31,15 +31,10 @@ struct r300_context { /* Parent class */ struct pipe_context context; - struct amd_winsys* winsys; + /* The interface to the windowing system, etc. */ + struct r300_winsys* winsys; + /* Draw module. Used mostly for SW TCL. */ struct draw_context* draw; - - /* CS object. This is very much like Intel's batchbuffer. - * Fill it full of dwords and relocs and then submit. - * Repeat as needed. */ - /* Note: Unlike Mesa's version of this, we don't keep a copy of the CSM - * that was used to create this CS. Is this a good idea? */ - struct radeon_cs* cs; }; /* Convenience cast wrapper. */ @@ -52,6 +47,6 @@ void r300_init_surface_functions(struct r300_context* r300); struct pipe_context* r300_create_context(struct pipe_screen* screen, struct pipe_winsys* winsys, - struct amd_winsys* amd_winsys); + struct r300_winsys* r300_winsys); #endif /* R300_CONTEXT_H */ \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index ebd5324119..1422842e0c 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -23,48 +23,50 @@ #ifndef R300_CS_H #define R300_CS_H -#include "radeon_cs.h" #include "radeon_reg.h" +#include "r300_winsys.h" + /* Yes, I know macros are ugly. However, they are much prettier than the code * that they neatly hide away, and don't have the cost of function setup,so * we're going to use them. */ #define MAX_CS_SIZE 64 * 1024 / 4 +/* XXX stolen from radeon_drm.h */ +#define RADEON_GEM_DOMAIN_CPU 0x1 +#define RADEON_GEM_DOMAIN_GTT 0x2 +#define RADEON_GEM_DOMAIN_VRAM 0x4 + #define CP_PACKET0(register, count) \ (RADEON_CP_PACKET0 | ((count) << 16) | ((register) >> 2)) #define CS_LOCALS(context) \ - struct radeon_cs* cs = context->cs + struct r300_winsys* cs_winsys = context->winsys; \ + struct radeon_cs* cs = cs_winsys->cs -#define CHECK_CS(size) do { \ - if ((cs->cdw + (size) + 128) > MAX_CS_SIZE || radeon_cs_need_flush(cs)) { \ - /* XXX flush the CS */ \ - } } while (0) +#define CHECK_CS(size) \ + cs_winsys->check_cs(cs, (size)) -/* XXX radeon_cs_begin is currently unimplemented on the backend, but let's - * be future-proof, yeah? */ #define BEGIN_CS(size) do { \ CHECK_CS(size); \ - radeon_cs_begin(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ + cs_winsys->begin_cs(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ } while (0) #define OUT_CS(value) \ - radeon_cs_write_dword(cs, value) + cs_winsys->write_cs_dword(cs, value) #define OUT_CS_REG(register, value) do { \ OUT_CS(CP_PACKET0(register, 0)); \ OUT_CS(value); } while (0) #define OUT_CS_RELOC(bo, offset, rd, wd, flags) do { \ - radeon_cs_write_dword(cs, offset); \ - radeon_cs_write_reloc(cs, bo, rd, wd, flags); \ + OUT_CS(offset); \ + cs_winsys->write_cs_reloc(cs, bo, rd, wd, flags); \ } while (0) -/* XXX more future-proofing */ #define END_CS \ - radeon_cs_end(cs, __FILE__, __FUNCTION__, __LINE__) + cs_winsys->end_cs(cs, __FILE__, __FUNCTION__, __LINE__) #endif /* R300_CS_H */ \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 37a74b3c0a..dacde27888 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -144,13 +144,13 @@ struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint pci_id) if (!r300screen) return NULL; - /* XXX break this into its own function? */ + /* XXX break this into its own function? switch (pci_id) { default: debug_printf("%s: unknown PCI ID 0x%x, cannot create screen!\n", __FUNCTION__, pci_id); return NULL; - } + } */ r300screen->pci_id = pci_id; r300screen->screen.winsys = winsys; diff --git a/src/gallium/drivers/r300/r300_winsys.h b/src/gallium/drivers/r300/r300_winsys.h new file mode 100644 index 0000000000..7048a9c88d --- /dev/null +++ b/src/gallium/drivers/r300/r300_winsys.h @@ -0,0 +1,87 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_WINSYS_H +#define R300_WINSYS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* The public interface header for the r300 pipe driver. + * Any winsys hosting this pipe needs to implement r300_winsys and then + * call r300_create_context to start things. */ + +#include "pipe/p_defines.h" +#include "pipe/p_state.h" + +struct radeon_cs; + +struct r300_winsys { + + /* CS object. This is very much like Intel's batchbuffer. + * Fill it full of dwords and relocs and then submit. + * Repeat as needed. */ + /* Note: Unlike Mesa's version of this, we don't keep a copy of the CSM + * that was used to create this CS. Is this a good idea? */ + /* Note: The pipe driver doesn't know how to use this. This is purely + * for the winsys. */ + struct radeon_cs* cs; + + /* Check to see if there's room for commands. */ + boolean (*check_cs)(struct radeon_cs* cs, int size); + + /* Start a command emit. */ + void (*begin_cs)(struct radeon_cs* cs, + int size, + const char* file, + const char* function, + int line); + + /* Write a dword to the command buffer. */ + /* XXX is this an okay name for this handle? */ + void (*write_cs_dword)(struct radeon_cs* cs, uint32_t dword); + + /* Write a relocated dword to the command buffer. */ + void (*write_cs_reloc)(struct radeon_cs* cs, + struct pipe_buffer* bo, + uint32_t rd, + uint32_t wd, + uint32_t flags); + + /* Finish a command emit. */ + void (*end_cs)(struct radeon_cs* cs, + const char* file, + const char* function, + int line); + +}; + +struct pipe_context* r300_create_context(struct pipe_screen* screen, + struct pipe_winsys* winsys, + struct r300_winsys* r300_winsys); + +#ifdef __cplusplus +} +#endif + +#endif /* R300_WINSYS_H */ \ No newline at end of file diff --git a/src/gallium/winsys/drm/amd/Makefile b/src/gallium/winsys/drm/amd/Makefile index 0f23e3446c..fb77873404 100644 --- a/src/gallium/winsys/drm/amd/Makefile +++ b/src/gallium/winsys/drm/amd/Makefile @@ -7,11 +7,13 @@ LIBNAME = amd_dri.so MINIGLX_SOURCES = PIPE_DRIVERS = \ - $(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a + $(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \ + $(TOP)/src/gallium/drivers/r300/libr300.a DRIVER_SOURCES = \ amd_buffer.c \ amd_context.c \ + amd_r300.c \ amd_screen.c \ amd_winsys_softpipe.c @@ -21,6 +23,8 @@ C_SOURCES = \ ASM_SOURCES = +DRIVER_DEFINES = -I../../../drivers/r300 + include ../Makefile.template DRI_LIB_DEPS += -ldrm_radeon diff --git a/src/gallium/winsys/drm/amd/amd_context.c b/src/gallium/winsys/drm/amd/amd_context.c index 632caec6a7..7784964867 100644 --- a/src/gallium/winsys/drm/amd/amd_context.c +++ b/src/gallium/winsys/drm/amd/amd_context.c @@ -243,12 +243,10 @@ GLboolean amd_context_create(const __GLcontextModes *visual, } if (GL_TRUE) { - /* XXX second arg should be PCI ID, but damned if I know why */ - amd_context->pipe_screen = r300_create_screen(amd_context->pipe_winsys, - 0x0); - pipe = r300_create_context(amd_context->pipe_screen, + fprintf(stderr, "Creating r300 context..."); + pipe = r300_create_context(NULL, amd_context->pipe_winsys, - (struct amd_pipe_winsys*)amd_context->pipe_winsys); + amd_create_r300_winsys(amd_context->drm_fd)); } else { pipe = amd_create_softpipe(amd_context); } diff --git a/src/gallium/winsys/drm/amd/amd_context.h b/src/gallium/winsys/drm/amd/amd_context.h index 54a831f15a..12557c40c4 100644 --- a/src/gallium/winsys/drm/amd/amd_context.h +++ b/src/gallium/winsys/drm/amd/amd_context.h @@ -35,6 +35,8 @@ #include "state_tracker/st_context.h" #include "amd_screen.h" +#include "amd_r300.h" + struct amd_framebuffer { struct st_framebuffer *st_framebuffer; unsigned attachments; diff --git a/src/gallium/winsys/drm/amd/amd_r300.c b/src/gallium/winsys/drm/amd/amd_r300.c new file mode 100644 index 0000000000..0bc0a842c1 --- /dev/null +++ b/src/gallium/winsys/drm/amd/amd_r300.c @@ -0,0 +1,55 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "amd_r300.h" + +static boolean amd_r300_check_cs(struct radeon_cs* cs, int size) +{ + /* XXX check size here, lazy ass! */ + return TRUE; +} + +static void amd_r300_write_cs_reloc(struct radeon_cs* cs, + struct pipe_buffer* pbuffer, + uint32_t rd, + uint32_t wd, + uint32_t flags) +{ + radeon_cs_write_reloc(cs, ((struct amd_pipe_buffer*)pbuffer)->bo, rd, wd, flags); +} + +struct r300_winsys* amd_create_r300_winsys(int fd) +{ + struct r300_winsys* winsys = calloc(1, sizeof(struct r300_winsys)); + + struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); + + winsys->cs = radeon_cs_create(csm, 1024 * 64 / 4); + + winsys->check_cs = amd_r300_check_cs; + winsys->begin_cs = radeon_cs_begin; + winsys->write_cs_dword = radeon_cs_write_dword; + winsys->write_cs_reloc = amd_r300_write_cs_reloc; + winsys->end_cs = radeon_cs_end; + + return winsys; +} \ No newline at end of file diff --git a/src/gallium/winsys/drm/amd/amd_r300.h b/src/gallium/winsys/drm/amd/amd_r300.h new file mode 100644 index 0000000000..ef269454b3 --- /dev/null +++ b/src/gallium/winsys/drm/amd/amd_r300.h @@ -0,0 +1,29 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "radeon_cs.h" + +#include "r300_winsys.h" + +#include "amd_buffer.h" + +struct r300_winsys* amd_create_r300_winsys(int fd); -- cgit v1.2.3 From 432ab001d042b816b5892398064e5735d0293955 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 13 Jan 2009 15:21:29 -0800 Subject: r300, amd: Add the ability to flush the CS. This is probably important, yeah? --- src/gallium/drivers/r300/r300_cs.h | 3 +++ src/gallium/drivers/r300/r300_winsys.h | 2 ++ src/gallium/winsys/drm/amd/amd_r300.c | 9 ++++++++- 3 files changed, 13 insertions(+), 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 1422842e0c..bd392afca3 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -69,4 +69,7 @@ #define END_CS \ cs_winsys->end_cs(cs, __FILE__, __FUNCTION__, __LINE__) +#define FLUSH_CS \ + cs_winsys->flush_cs(cs) + #endif /* R300_CS_H */ \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_winsys.h b/src/gallium/drivers/r300/r300_winsys.h index 7048a9c88d..7711dc792d 100644 --- a/src/gallium/drivers/r300/r300_winsys.h +++ b/src/gallium/drivers/r300/r300_winsys.h @@ -74,6 +74,8 @@ struct r300_winsys { const char* function, int line); + /* Flush the CS. */ + void (*flush_cs)(struct radeon_cs* cs); }; struct pipe_context* r300_create_context(struct pipe_screen* screen, diff --git a/src/gallium/winsys/drm/amd/amd_r300.c b/src/gallium/winsys/drm/amd/amd_r300.c index 0bc0a842c1..0f543df9e1 100644 --- a/src/gallium/winsys/drm/amd/amd_r300.c +++ b/src/gallium/winsys/drm/amd/amd_r300.c @@ -37,6 +37,12 @@ static void amd_r300_write_cs_reloc(struct radeon_cs* cs, radeon_cs_write_reloc(cs, ((struct amd_pipe_buffer*)pbuffer)->bo, rd, wd, flags); } +static void amd_r300_flush_cs(struct radeon_cs* cs) +{ + radeon_cs_emit(cs); + radeon_cs_erase(cs); +} + struct r300_winsys* amd_create_r300_winsys(int fd) { struct r300_winsys* winsys = calloc(1, sizeof(struct r300_winsys)); @@ -50,6 +56,7 @@ struct r300_winsys* amd_create_r300_winsys(int fd) winsys->write_cs_dword = radeon_cs_write_dword; winsys->write_cs_reloc = amd_r300_write_cs_reloc; winsys->end_cs = radeon_cs_end; + winsys->flush_cs = amd_r300_flush_cs; return winsys; -} \ No newline at end of file +} -- cgit v1.2.3 From 74288078eab1971cc6ce3ae00fa55eb917b5826a Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 13 Jan 2009 19:11:19 -0800 Subject: r300: Add blend state. Also switched to r300_reg instead of radeon_reg. Yay? --- src/gallium/drivers/r300/r300_blit.c | 4 +- src/gallium/drivers/r300/r300_context.h | 16 + src/gallium/drivers/r300/r300_cs.h | 3 +- src/gallium/drivers/r300/r300_reg.h | 3259 +++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_state.c | 121 ++ src/gallium/drivers/r300/r300_state.h | 2 + 6 files changed, 3401 insertions(+), 4 deletions(-) create mode 100644 src/gallium/drivers/r300/r300_reg.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c index b8ddf6677f..6bcfbc0d79 100644 --- a/src/gallium/drivers/r300/r300_blit.c +++ b/src/gallium/drivers/r300/r300_blit.c @@ -35,7 +35,7 @@ int r300_fill_blit(struct r300_context* r300, { CS_LOCALS(r300); uint32_t dest_type; - +#if 0 /* Check for fallbacks. */ /* XXX we can do YUV surfaces, too, but only in 3D mode. Hmm... */ switch(cpp) { @@ -91,6 +91,6 @@ int r300_fill_blit(struct r300_context* r300, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); END_CS; - +#endif return 1; } diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 119d46af58..b9fff0deab 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -27,6 +27,15 @@ #include "pipe/p_context.h" #include "util/u_memory.h" +struct r300_blend_state { + uint32_t blend_control; /* R300_RB3D_BLENDCNTL: 0x4e04 */ + uint32_t alpha_blend_control; /* R300_RB3D_ABLENDCNTL: 0x4e08 */ + uint32_t rop; /* R300_RB3D_ROPCNTL: 0x4e18 */ + uint32_t dither; /* R300_RB3D_DITHER_CTL: 0x4e50 */ +}; + +#define R300_NEW_BLEND 0x1 + struct r300_context { /* Parent class */ struct pipe_context context; @@ -35,6 +44,13 @@ struct r300_context { struct r300_winsys* winsys; /* Draw module. Used mostly for SW TCL. */ struct draw_context* draw; + + /* Various CSO state objects. */ + /* Blend state. */ + struct r300_blend_state* blend_state; + + /* Bitmask of dirty state objects. */ + uint32_t dirty_state; }; /* Convenience cast wrapper. */ diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index bd392afca3..92ed807657 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -23,8 +23,7 @@ #ifndef R300_CS_H #define R300_CS_H -#include "radeon_reg.h" - +#include "r300_reg.h" #include "r300_winsys.h" /* Yes, I know macros are ugly. However, they are much prettier than the code diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h new file mode 100644 index 0000000000..8b3fe431ab --- /dev/null +++ b/src/gallium/drivers/r300/r300_reg.h @@ -0,0 +1,3259 @@ +/************************************************************************** + +Copyright (C) 2004-2005 Nicolai Haehnle et al. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +on the rights to use, copy, modify, merge, publish, distribute, sub +license, and/or sell copies of the Software, and to permit persons to whom +the Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice (including the next +paragraph) shall be included in all copies or substantial portions of the +Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, +DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* *INDENT-OFF* */ + +#ifndef _R300_REG_H +#define _R300_REG_H + +#define R300_MC_INIT_MISC_LAT_TIMER 0x180 +# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 +# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 +# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 +# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 +# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 +# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 +# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 +# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 + + +#define R300_MC_INIT_GFX_LAT_TIMER 0x154 +# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 +# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 +# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 +# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 +# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 +# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 +# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 +# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 + +/* + * This file contains registers and constants for the R300. They have been + * found mostly by examining command buffers captured using glxtest, as well + * as by extrapolating some known registers and constants from the R200. + * I am fairly certain that they are correct unless stated otherwise + * in comments. + */ + +#define R300_SE_VPORT_XSCALE 0x1D98 +#define R300_SE_VPORT_XOFFSET 0x1D9C +#define R300_SE_VPORT_YSCALE 0x1DA0 +#define R300_SE_VPORT_YOFFSET 0x1DA4 +#define R300_SE_VPORT_ZSCALE 0x1DA8 +#define R300_SE_VPORT_ZOFFSET 0x1DAC + + +/* + * Vertex Array Processing (VAP) Control + */ +#define R300_VAP_CNTL 0x2080 +# define R300_PVS_NUM_SLOTS_SHIFT 0 +# define R300_PVS_NUM_CNTLRS_SHIFT 4 +# define R300_PVS_NUM_FPUS_SHIFT 8 +# define R300_VF_MAX_VTX_NUM_SHIFT 18 +# define R300_GL_CLIP_SPACE_DEF (0 << 22) +# define R300_DX_CLIP_SPACE_DEF (1 << 22) +# define R500_TCL_STATE_OPTIMIZATION (1 << 23) + +/* This register is written directly and also starts data section + * in many 3d CP_PACKET3's + */ +#define R300_VAP_VF_CNTL 0x2084 +# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 +# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) +# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) +# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) +# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) +# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) +# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) +# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) +# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) +# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) +# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) +# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) + +# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 + /* State based - direct writes to registers trigger vertex + generation */ +# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) +# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) +# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) +# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) + + /* I don't think I saw these three used.. */ +# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 +# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 +# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 + + /* index size - when not set the indices are assumed to be 16 bit */ +# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) + /* number of vertices */ +# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 + +#define R500_VAP_INDEX_OFFSET 0x208c + +#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 +# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT (1<<1) +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) +# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) +# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) + +#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 + /* each of the following is 3 bits wide, specifies number + of components */ +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 +# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 +# define R300_VAP_OUTPUT_VTX_FMT_1__NOT_PRESENT 0 +# define R300_VAP_OUTPUT_VTX_FMT_1__1_COMPONENT 1 +# define R300_VAP_OUTPUT_VTX_FMT_1__2_COMPONENTS 2 +# define R300_VAP_OUTPUT_VTX_FMT_1__3_COMPONENTS 3 +# define R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS 4 + +#define R300_SE_VTE_CNTL 0x20b0 +# define R300_VPORT_X_SCALE_ENA (1 << 0) +# define R300_VPORT_X_OFFSET_ENA (1 << 1) +# define R300_VPORT_Y_SCALE_ENA (1 << 2) +# define R300_VPORT_Y_OFFSET_ENA (1 << 3) +# define R300_VPORT_Z_SCALE_ENA (1 << 4) +# define R300_VPORT_Z_OFFSET_ENA (1 << 5) +# define R300_VTX_XY_FMT (1 << 8) +# define R300_VTX_Z_FMT (1 << 9) +# define R300_VTX_W0_FMT (1 << 10) +# define R300_SERIAL_PROC_ENA (1 << 11) + +/* BEGIN: Vertex data assembly - lots of uncertainties */ + +/* gap */ + +/* Maximum Vertex Indx Clamp */ +#define R300_VAP_VF_MAX_VTX_INDX 0x2134 +/* Minimum Vertex Indx Clamp */ +#define R300_VAP_VF_MIN_VTX_INDX 0x2138 + +/** Vertex assembler/processor control status */ +#define R300_VAP_CNTL_STATUS 0x2140 +/* No swap at all (default) */ +# define R300_VC_NO_SWAP (0 << 0) +/* 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC */ +# define R300_VC_16BIT_SWAP (1 << 0) +/* 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA */ +# define R300_VC_32BIT_SWAP (2 << 0) +/* Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB */ +# define R300_VC_HALF_DWORD_SWAP (3 << 0) +/* The TCL engine will not be used (as it is logically or even physically removed) */ +# define R300_VAP_TCL_BYPASS (1 << 8) +/* Read only flag if TCL engine is busy. */ +# define R300_VAP_PVS_BUSY (1 << 11) +/* TODO: gap for MAX_MPS */ +/* Read only flag if the vertex store is busy. */ +# define R300_VAP_VS_BUSY (1 << 24) +/* Read only flag if the reciprocal engine is busy. */ +# define R300_VAP_RCP_BUSY (1 << 25) +/* Read only flag if the viewport transform engine is busy. */ +# define R300_VAP_VTE_BUSY (1 << 26) +/* Read only flag if the memory interface unit is busy. */ +# define R300_VAP_MUI_BUSY (1 << 27) +/* Read only flag if the vertex cache is busy. */ +# define R300_VAP_VC_BUSY (1 << 28) +/* Read only flag if the vertex fetcher is busy. */ +# define R300_VAP_VF_BUSY (1 << 29) +/* Read only flag if the register pipeline is busy. */ +# define R300_VAP_REGPIPE_BUSY (1 << 30) +/* Read only flag if the VAP engine is busy. */ +# define R300_VAP_VAP_BUSY (1 << 31) + +/* gap */ + +/* Where do we get our vertex data? + * + * Vertex data either comes either from immediate mode registers or from + * vertex arrays. + * There appears to be no mixed mode (though we can force the pitch of + * vertex arrays to 0, effectively reusing the same element over and over + * again). + * + * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure + * if these registers influence vertex array processing. + * + * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. + * + * In both cases, vertex attributes are then passed through INPUT_ROUTE. + * + * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data + * into the vertex processor's input registers. + * The first word routes the first input, the second word the second, etc. + * The corresponding input is routed into the register with the given index. + * The list is ended by a word with INPUT_ROUTE_END set. + * + * Always set COMPONENTS_4 in immediate mode. + */ + +#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 +# define R300_DATA_TYPE_0_SHIFT 0 +# define R300_DATA_TYPE_FLOAT_1 0 +# define R300_DATA_TYPE_FLOAT_2 1 +# define R300_DATA_TYPE_FLOAT_3 2 +# define R300_DATA_TYPE_FLOAT_4 3 +# define R300_DATA_TYPE_BYTE 4 +# define R300_DATA_TYPE_D3DCOLOR 5 +# define R300_DATA_TYPE_SHORT_2 6 +# define R300_DATA_TYPE_SHORT_4 7 +# define R300_DATA_TYPE_VECTOR_3_TTT 8 +# define R300_DATA_TYPE_VECTOR_3_EET 9 +# define R300_SKIP_DWORDS_SHIFT 4 +# define R300_DST_VEC_LOC_SHIFT 8 +# define R300_LAST_VEC (1 << 13) +# define R300_SIGNED (1 << 14) +# define R300_NORMALIZE (1 << 15) +# define R300_DATA_TYPE_1_SHIFT 16 +#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 +#define R300_VAP_PROG_STREAM_CNTL_2 0x2158 +#define R300_VAP_PROG_STREAM_CNTL_3 0x215C +#define R300_VAP_PROG_STREAM_CNTL_4 0x2160 +#define R300_VAP_PROG_STREAM_CNTL_5 0x2164 +#define R300_VAP_PROG_STREAM_CNTL_6 0x2168 +#define R300_VAP_PROG_STREAM_CNTL_7 0x216C +/* gap */ + +/* Notes: + * - always set up to produce at least two attributes: + * if vertex program uses only position, fglrx will set normal, too + * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. + */ +#define R300_VAP_VTX_STATE_CNTL 0x2180 +# define R300_COLOR_0_ASSEMBLY_SHIFT 0 +# define R300_SEL_COLOR 0 +# define R300_SEL_USER_COLOR_0 1 +# define R300_SEL_USER_COLOR_1 2 +# define R300_COLOR_1_ASSEMBLY_SHIFT 2 +# define R300_COLOR_2_ASSEMBLY_SHIFT 4 +# define R300_COLOR_3_ASSEMBLY_SHIFT 6 +# define R300_COLOR_4_ASSEMBLY_SHIFT 8 +# define R300_COLOR_5_ASSEMBLY_SHIFT 10 +# define R300_COLOR_6_ASSEMBLY_SHIFT 12 +# define R300_COLOR_7_ASSEMBLY_SHIFT 14 +# define R300_UPDATE_USER_COLOR_0_ENA (1 << 16) + +/* + * Each bit in this field applies to the corresponding vector in the VSM + * memory (i.e. Bit 0 applies to VECTOR_0 (POSITION), etc.). If the bit + * is set, then the corresponding 4-Dword Vector is output into the Vertex Stream. + */ +#define R300_VAP_VSM_VTX_ASSM 0x2184 +# define R300_INPUT_CNTL_POS 0x00000001 +# define R300_INPUT_CNTL_NORMAL 0x00000002 +# define R300_INPUT_CNTL_COLOR 0x00000004 +# define R300_INPUT_CNTL_TC0 0x00000400 +# define R300_INPUT_CNTL_TC1 0x00000800 +# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ +# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ +# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ +# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ +# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ +# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ + +/* Programmable Stream Control Signed Normalize Control */ +#define R300_VAP_PSC_SGN_NORM_CNTL 0x21dc +# define SGN_NORM_ZERO 0 +# define SGN_NORM_ZERO_CLAMP_MINUS_ONE 1 +# define SGN_NORM_NO_ZERO 2 + +/* gap */ + +/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 + * are set to a swizzling bit pattern, other words are 0. + * + * In immediate mode, the pattern is always set to xyzw. In vertex array + * mode, the swizzling pattern is e.g. used to set zw components in texture + * coordinates with only tweo components. + */ +#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 +# define R300_SWIZZLE0_SHIFT 0 +# define R300_SWIZZLE_SELECT_X_SHIFT 0 +# define R300_SWIZZLE_SELECT_Y_SHIFT 3 +# define R300_SWIZZLE_SELECT_Z_SHIFT 6 +# define R300_SWIZZLE_SELECT_W_SHIFT 9 + +# define R300_SWIZZLE_SELECT_X 0 +# define R300_SWIZZLE_SELECT_Y 1 +# define R300_SWIZZLE_SELECT_Z 2 +# define R300_SWIZZLE_SELECT_W 3 +# define R300_SWIZZLE_SELECT_FP_ZERO 4 +# define R300_SWIZZLE_SELECT_FP_ONE 5 +/* alternate forms for r300_emit.c */ +# define R300_INPUT_ROUTE_SELECT_X 0 +# define R300_INPUT_ROUTE_SELECT_Y 1 +# define R300_INPUT_ROUTE_SELECT_Z 2 +# define R300_INPUT_ROUTE_SELECT_W 3 +# define R300_INPUT_ROUTE_SELECT_ZERO 4 +# define R300_INPUT_ROUTE_SELECT_ONE 5 + +# define R300_WRITE_ENA_SHIFT 12 +# define R300_WRITE_ENA_X 1 +# define R300_WRITE_ENA_Y 2 +# define R300_WRITE_ENA_Z 4 +# define R300_WRITE_ENA_W 8 +# define R300_SWIZZLE1_SHIFT 16 +#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 +#define R300_VAP_PROG_STREAM_CNTL_EXT_2 0x21e8 +#define R300_VAP_PROG_STREAM_CNTL_EXT_3 0x21ec +#define R300_VAP_PROG_STREAM_CNTL_EXT_4 0x21f0 +#define R300_VAP_PROG_STREAM_CNTL_EXT_5 0x21f4 +#define R300_VAP_PROG_STREAM_CNTL_EXT_6 0x21f8 +#define R300_VAP_PROG_STREAM_CNTL_EXT_7 0x21fc + +/* END: Vertex data assembly */ + +/* gap */ + +/* BEGIN: Upload vertex program and data */ + +/* + * The programmable vertex shader unit has a memory bank of unknown size + * that can be written to in 16 byte units by writing the address into + * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). + * + * Pointers into the memory bank are always in multiples of 16 bytes. + * + * The memory bank is divided into areas with fixed meaning. + * + * Starting at address UPLOAD_PROGRAM: Vertex program instructions. + * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), + * whereas the difference between known addresses suggests size 512. + * + * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. + * Native reported limits and the VPI layout suggest size 256, whereas + * difference between known addresses suggests size 512. + * + * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the + * floating point pointsize. The exact purpose of this state is uncertain, + * as there is also the R300_RE_POINTSIZE register. + * + * Multiple vertex programs and parameter sets can be loaded at once, + * which could explain the size discrepancy. + */ +#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 +# define R300_PVS_CODE_START 0 +# define R300_MAX_PVS_CODE_LINES 256 +# define R500_MAX_PVS_CODE_LINES 1024 +# define R300_PVS_CONST_START 512 +# define R500_PVS_CONST_START 1024 +# define R300_MAX_PVS_CONST_VECS 256 +# define R500_MAX_PVS_CONST_VECS 1024 +# define R300_PVS_UCP_START 1024 +# define R500_PVS_UCP_START 1536 +# define R300_POINT_VPORT_SCALE_OFFSET 1030 +# define R500_POINT_VPORT_SCALE_OFFSET 1542 +# define R300_POINT_GEN_TEX_OFFSET 1031 +# define R500_POINT_GEN_TEX_OFFSET 1543 + +/* + * These are obsolete defines form r300_context.h, but they might give some + * clues when investigating the addresses further... + */ +#if 0 +#define VSF_DEST_PROGRAM 0x0 +#define VSF_DEST_MATRIX0 0x200 +#define VSF_DEST_MATRIX1 0x204 +#define VSF_DEST_MATRIX2 0x208 +#define VSF_DEST_VECTOR0 0x20c +#define VSF_DEST_VECTOR1 0x20d +#define VSF_DEST_UNKNOWN1 0x400 +#define VSF_DEST_UNKNOWN2 0x406 +#endif + +/* gap */ + +#define R300_VAP_PVS_UPLOAD_DATA 0x2208 + +/* END: Upload vertex program and data */ + +/* gap */ + +/* I do not know the purpose of this register. However, I do know that + * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL + * for normal rendering. + * + * 2007-11-05: This register is the user clip plane control register, but there + * also seems to be a rendering mode control; the NORMAL/CLEAR defines. + * + * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view + */ +#define R300_VAP_CLIP_CNTL 0x221C +# define R300_VAP_UCP_ENABLE_0 (1 << 0) +# define R300_VAP_UCP_ENABLE_1 (1 << 1) +# define R300_VAP_UCP_ENABLE_2 (1 << 2) +# define R300_VAP_UCP_ENABLE_3 (1 << 3) +# define R300_VAP_UCP_ENABLE_4 (1 << 4) +# define R300_VAP_UCP_ENABLE_5 (1 << 5) +# define R300_PS_UCP_MODE_DIST_COP (0 << 14) +# define R300_PS_UCP_MODE_RADIUS_COP (1 << 14) +# define R300_PS_UCP_MODE_RADIUS_COP_CLIP (2 << 14) +# define R300_PS_UCP_MODE_CLIP_AS_TRIFAN (3 << 14) +# define R300_CLIP_DISABLE (1 << 16) +# define R300_UCP_CULL_ONLY_ENABLE (1 << 17) +# define R300_BOUNDARY_EDGE_FLAG_ENABLE (1 << 18) +# define R500_COLOR2_IS_TEXTURE (1 << 20) +# define R500_COLOR3_IS_TEXTURE (1 << 21) + +/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first + * plane is per-pixel and the second plane is per-vertex. + * + * This was determined by experimentation alone but I believe it is correct. + * + * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. + */ +#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 +#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 +#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 +#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c + +/* gap */ + +/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between + * rendering commands and overwriting vertex program parameters. + * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and + * avoids bugs caused by still running shaders reading bad data from memory. + */ +#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 + +/* This register is used to define the number of core clocks to wait for a + * vertex to be received by the VAP input controller (while the primitive + * path is backed up) before forcing any accumulated vertices to be submitted + * to the vertex processing path. + */ +#define VAP_PVS_VTX_TIMEOUT_REG 0x2288 +# define R300_2288_R300 0x00750000 /* -- nh */ +# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ + +/* gap */ + +/* Addresses are relative to the vertex program instruction area of the + * memory bank. PROGRAM_END points to the last instruction of the active + * program + * + * The meaning of the two UNKNOWN fields is obviously not known. However, + * experiments so far have shown that both *must* point to an instruction + * inside the vertex program, otherwise the GPU locks up. + * + * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and + * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to + * position takes place. + * + * Most likely this is used to ignore rest of the program in cases + * where group of verts arent visible. For some reason this "section" + * is sometimes accepted other instruction that have no relationship with + * position calculations. + */ +#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 +# define R300_PVS_FIRST_INST_SHIFT 0 +# define R300_PVS_XYZW_VALID_INST_SHIFT 10 +# define R300_PVS_LAST_INST_SHIFT 20 +/* Addresses are relative the the vertex program parameters area. */ +#define R300_VAP_PVS_CONST_CNTL 0x22D4 +# define R300_PVS_CONST_BASE_OFFSET_SHIFT 0 +# define R300_PVS_MAX_CONST_ADDR_SHIFT 16 +#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 +# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 +#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22DC + +/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for + * immediate vertices + */ +#define R300_VAP_VTX_COLOR_R 0x2464 +#define R300_VAP_VTX_COLOR_G 0x2468 +#define R300_VAP_VTX_COLOR_B 0x246C +#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ +#define R300_VAP_VTX_POS_0_Y_1 0x2494 +#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ +#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ +#define R300_VAP_VTX_POS_0_Y_2 0x24A4 +#define R300_VAP_VTX_POS_0_Z_2 0x24A8 +/* write 0 to indicate end of packet? */ +#define R300_VAP_VTX_END_OF_PKT 0x24AC + +/* gap */ + +/* These are values from r300_reg/r300_reg.h - they are known to be correct + * and are here so we can use one register file instead of several + * - Vladimir + */ +#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 +# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) +# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) +# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) + +#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 + /* each of the following is 3 bits wide, specifies number + of components */ +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 +# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 + +/* UNK30 seems to enables point to quad transformation on textures + * (or something closely related to that). + * This bit is rather fatal at the time being due to lackings at pixel + * shader side + * Specifies top of Raster pipe specific enable controls. + */ +#define R300_GB_ENABLE 0x4008 +# define R300_GB_POINT_STUFF_DISABLE (0 << 0) +# define R300_GB_POINT_STUFF_ENABLE (1 << 0) /* Specifies if points will have stuffed texture coordinates. */ +# define R300_GB_LINE_STUFF_DISABLE (0 << 1) +# define R300_GB_LINE_STUFF_ENABLE (1 << 1) /* Specifies if lines will have stuffed texture coordinates. */ +# define R300_GB_TRIANGLE_STUFF_DISABLE (0 << 2) +# define R300_GB_TRIANGLE_STUFF_ENABLE (1 << 2) /* Specifies if triangles will have stuffed texture coordinates. */ +# define R300_GB_STENCIL_AUTO_DISABLE (0 << 4) +# define R300_GB_STENCIL_AUTO_ENABLE (1 << 4) /* Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit. */ +# define R300_GB_STENCIL_AUTO_FORCE (2 << 4) /* Force 0 into dzy low bit. */ + + /* each of the following is 2 bits wide */ +#define R300_GB_TEX_REPLICATE 0 /* Replicate VAP source texture coordinates (S,T,[R,Q]). */ +#define R300_GB_TEX_ST 1 /* Stuff with source texture coordinates (S,T). */ +#define R300_GB_TEX_STR 2 /* Stuff with source texture coordinates (S,T,R). */ +# define R300_GB_TEX0_SOURCE_SHIFT 16 +# define R300_GB_TEX1_SOURCE_SHIFT 18 +# define R300_GB_TEX2_SOURCE_SHIFT 20 +# define R300_GB_TEX3_SOURCE_SHIFT 22 +# define R300_GB_TEX4_SOURCE_SHIFT 24 +# define R300_GB_TEX5_SOURCE_SHIFT 26 +# define R300_GB_TEX6_SOURCE_SHIFT 28 +# define R300_GB_TEX7_SOURCE_SHIFT 30 + +/* MSPOS - positions for multisample antialiasing (?) */ +#define R300_GB_MSPOS0 0x4010 + /* shifts - each of the fields is 4 bits */ +# define R300_GB_MSPOS0__MS_X0_SHIFT 0 +# define R300_GB_MSPOS0__MS_Y0_SHIFT 4 +# define R300_GB_MSPOS0__MS_X1_SHIFT 8 +# define R300_GB_MSPOS0__MS_Y1_SHIFT 12 +# define R300_GB_MSPOS0__MS_X2_SHIFT 16 +# define R300_GB_MSPOS0__MS_Y2_SHIFT 20 +# define R300_GB_MSPOS0__MSBD0_Y 24 +# define R300_GB_MSPOS0__MSBD0_X 28 + +#define R300_GB_MSPOS1 0x4014 +# define R300_GB_MSPOS1__MS_X3_SHIFT 0 +# define R300_GB_MSPOS1__MS_Y3_SHIFT 4 +# define R300_GB_MSPOS1__MS_X4_SHIFT 8 +# define R300_GB_MSPOS1__MS_Y4_SHIFT 12 +# define R300_GB_MSPOS1__MS_X5_SHIFT 16 +# define R300_GB_MSPOS1__MS_Y5_SHIFT 20 +# define R300_GB_MSPOS1__MSBD1 24 + +/* Specifies the graphics pipeline configuration for rasterization. */ +#define R300_GB_TILE_CONFIG 0x4018 +# define R300_GB_TILE_DISABLE (0 << 0) +# define R300_GB_TILE_ENABLE (1 << 0) +# define R300_GB_TILE_PIPE_COUNT_RV300 (0 << 1) /* RV350 (1 pipe, 1 ctx) */ +# define R300_GB_TILE_PIPE_COUNT_R300 (3 << 1) /* R300 (2 pipes, 1 ctx) */ +# define R300_GB_TILE_PIPE_COUNT_R420_3P (6 << 1) /* R420-3P (3 pipes, 1 ctx) */ +# define R300_GB_TILE_PIPE_COUNT_R420 (7 << 1) /* R420 (4 pipes, 1 ctx) */ +# define R300_GB_TILE_SIZE_8 (0 << 4) +# define R300_GB_TILE_SIZE_16 (1 << 4) +# define R300_GB_TILE_SIZE_32 (2 << 4) +# define R300_GB_SUPER_SIZE_1 (0 << 6) +# define R300_GB_SUPER_SIZE_2 (1 << 6) +# define R300_GB_SUPER_SIZE_4 (2 << 6) +# define R300_GB_SUPER_SIZE_8 (3 << 6) +# define R300_GB_SUPER_SIZE_16 (4 << 6) +# define R300_GB_SUPER_SIZE_32 (5 << 6) +# define R300_GB_SUPER_SIZE_64 (6 << 6) +# define R300_GB_SUPER_SIZE_128 (7 << 6) +# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ +# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ +# define R300_GB_SUPER_TILE_A (0 << 15) +# define R300_GB_SUPER_TILE_B (1 << 15) +# define R300_GB_SUBPIXEL_1_12 (0 << 16) +# define R300_GB_SUBPIXEL_1_16 (1 << 16) +# define GB_TILE_CONFIG_QUADS_PER_RAS_4 (0 << 17) +# define GB_TILE_CONFIG_QUADS_PER_RAS_8 (1 << 17) +# define GB_TILE_CONFIG_QUADS_PER_RAS_16 (2 << 17) +# define GB_TILE_CONFIG_QUADS_PER_RAS_32 (3 << 17) +# define GB_TILE_CONFIG_BB_SCAN_INTERCEPT (0 << 19) +# define GB_TILE_CONFIG_BB_SCAN_BOUND_BOX (1 << 19) +# define GB_TILE_CONFIG_ALT_SCAN_EN_LR (0 << 20) +# define GB_TILE_CONFIG_ALT_SCAN_EN_LRL (1 << 20) +# define GB_TILE_CONFIG_ALT_OFFSET (0 << 21) +# define GB_TILE_CONFIG_SUBPRECISION (0 << 22) +# define GB_TILE_CONFIG_ALT_TILING_DEF (0 << 23) +# define GB_TILE_CONFIG_ALT_TILING_3_2 (1 << 23) +# define GB_TILE_CONFIG_Z_EXTENDED_24_1 (0 << 24) +# define GB_TILE_CONFIG_Z_EXTENDED_S25_1 (1 << 24) + +/* Specifies the sizes of the various FIFO`s in the sc/rs/us. This register must be the first one written */ +#define R300_GB_FIFO_SIZE 0x4024 + /* each of the following is 2 bits wide */ +#define R300_GB_FIFO_SIZE_32 0 +#define R300_GB_FIFO_SIZE_64 1 +#define R300_GB_FIFO_SIZE_128 2 +#define R300_GB_FIFO_SIZE_256 3 +# define R300_SC_IFIFO_SIZE_SHIFT 0 +# define R300_SC_TZFIFO_SIZE_SHIFT 2 +# define R300_SC_BFIFO_SIZE_SHIFT 4 + +# define R300_US_OFIFO_SIZE_SHIFT 12 +# define R300_US_WFIFO_SIZE_SHIFT 14 + /* the following use the same constants as above, but meaning is + is times 2 (i.e. instead of 32 words it means 64 */ +# define R300_RS_TFIFO_SIZE_SHIFT 6 +# define R300_RS_CFIFO_SIZE_SHIFT 8 +# define R300_US_RAM_SIZE_SHIFT 10 + /* watermarks, 3 bits wide */ +# define R300_RS_HIGHWATER_COL_SHIFT 16 +# define R300_RS_HIGHWATER_TEX_SHIFT 19 +# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ +# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 + +#define GB_Z_PEQ_CONFIG 0x4028 +# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_4_4 (0 << 0) +# define GB_Z_PEQ_CONFIG_Z_PEQ_SIZE_8_8 (1 << 0) + +/* Specifies various polygon specific selects (fog, depth, perspective). */ +#define R300_GB_SELECT 0x401c +# define R300_GB_FOG_SELECT_C0A (0 << 0) +# define R300_GB_FOG_SELECT_C1A (1 << 0) +# define R300_GB_FOG_SELECT_C2A (2 << 0) +# define R300_GB_FOG_SELECT_C3A (3 << 0) +# define R300_GB_FOG_SELECT_1_1_W (4 << 0) +# define R300_GB_FOG_SELECT_Z (5 << 0) +# define R300_GB_DEPTH_SELECT_Z (0 << 3 +# define R300_GB_DEPTH_SELECT_1_1_W (1 << 3) +# define R300_GB_W_SELECT_1_W (0 << 4) +# define R300_GB_W_SELECT_1 (1 << 4) +# define R300_GB_FOG_STUFF_DISABLE (0 << 5) +# define R300_GB_FOG_STUFF_ENABLE (1 << 5) +# define R300_GB_FOG_STUFF_TEX_SHIFT 6 +# define R300_GB_FOG_STUFF_TEX_MASK 0x000003c0 +# define R300_GB_FOG_STUFF_COMP_SHIFT 10 +# define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00 + +/* Specifies the graphics pipeline configuration for antialiasing. */ +#define GB_AA_CONFIG 0x4020 +# define GB_AA_CONFIG_AA_DISABLE (0 << 0) +# define GB_AA_CONFIG_AA_ENABLE (1 << 0) +# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2 (0 << 1) +# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3 (1 << 1) +# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4 (2 << 1) +# define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6 (3 << 1) + +/* Selects which of 4 pipes are active. */ +#define GB_PIPE_SELECT 0x402c +# define GB_PIPE_SELECT_PIPE0_ID_SHIFT 0 +# define GB_PIPE_SELECT_PIPE1_ID_SHIFT 2 +# define GB_PIPE_SELECT_PIPE2_ID_SHIFT 4 +# define GB_PIPE_SELECT_PIPE3_ID_SHIFT 6 +# define GB_PIPE_SELECT_PIPE_MASK_SHIFT 8 +# define GB_PIPE_SELECT_MAX_PIPE 12 +# define GB_PIPE_SELECT_BAD_PIPES 14 +# define GB_PIPE_SELECT_CONFIG_PIPES 18 + + +/* Specifies the sizes of the various FIFO`s in the sc/rs. */ +#define GB_FIFO_SIZE1 0x4070 +/* High water mark for SC input fifo */ +# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_SHIFT 0 +# define GB_FIFO_SIZE1_SC_HIGHWATER_IFIFO_MASK 0x0000003f +/* High water mark for SC input fifo (B) */ +# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_SHIFT 6 +# define GB_FIFO_SIZE1_SC_HIGHWATER_BFIFO_MASK 0x00000fc0 +/* High water mark for RS colors' fifo */ +# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_SHIFT 12 +# define GB_FIFO_SIZE1_SC_HIGHWATER_COL_MASK 0x0003f000 +/* High water mark for RS textures' fifo */ +# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_SHIFT 18 +# define GB_FIFO_SIZE1_SC_HIGHWATER_TEX_MASK 0x00fc0000 + +/* This table specifies the source location and format for up to 16 texture + * addresses (i[0]:i[15]) and four colors (c[0]:c[3]) + */ +#define R500_RS_IP_0 0x4074 +#define R500_RS_IP_1 0x4078 +#define R500_RS_IP_2 0x407C +#define R500_RS_IP_3 0x4080 +#define R500_RS_IP_4 0x4084 +#define R500_RS_IP_5 0x4088 +#define R500_RS_IP_6 0x408C +#define R500_RS_IP_7 0x4090 +#define R500_RS_IP_8 0x4094 +#define R500_RS_IP_9 0x4098 +#define R500_RS_IP_10 0x409C +#define R500_RS_IP_11 0x40A0 +#define R500_RS_IP_12 0x40A4 +#define R500_RS_IP_13 0x40A8 +#define R500_RS_IP_14 0x40AC +#define R500_RS_IP_15 0x40B0 +#define R500_RS_IP_PTR_K0 62 +#define R500_RS_IP_PTR_K1 63 +#define R500_RS_IP_TEX_PTR_S_SHIFT 0 +#define R500_RS_IP_TEX_PTR_T_SHIFT 6 +#define R500_RS_IP_TEX_PTR_R_SHIFT 12 +#define R500_RS_IP_TEX_PTR_Q_SHIFT 18 +#define R500_RS_IP_COL_PTR_SHIFT 24 +#define R500_RS_IP_COL_FMT_SHIFT 27 +# define R500_RS_COL_PTR(x) (x << 24) +# define R500_RS_COL_FMT(x) (x << 27) +/* gap */ +#define R500_RS_IP_OFFSET_DIS (0 << 31) +#define R500_RS_IP_OFFSET_EN (1 << 31) + +/* gap */ + +/* Zero to flush caches. */ +#define R300_TX_INVALTAGS 0x4100 +#define R300_TX_FLUSH 0x0 + +/* The upper enable bits are guessed, based on fglrx reported limits. */ +#define R300_TX_ENABLE 0x4104 +# define R300_TX_ENABLE_0 (1 << 0) +# define R300_TX_ENABLE_1 (1 << 1) +# define R300_TX_ENABLE_2 (1 << 2) +# define R300_TX_ENABLE_3 (1 << 3) +# define R300_TX_ENABLE_4 (1 << 4) +# define R300_TX_ENABLE_5 (1 << 5) +# define R300_TX_ENABLE_6 (1 << 6) +# define R300_TX_ENABLE_7 (1 << 7) +# define R300_TX_ENABLE_8 (1 << 8) +# define R300_TX_ENABLE_9 (1 << 9) +# define R300_TX_ENABLE_10 (1 << 10) +# define R300_TX_ENABLE_11 (1 << 11) +# define R300_TX_ENABLE_12 (1 << 12) +# define R300_TX_ENABLE_13 (1 << 13) +# define R300_TX_ENABLE_14 (1 << 14) +# define R300_TX_ENABLE_15 (1 << 15) + +#define R500_TX_FILTER_4 0x4110 +# define R500_TX_WEIGHT_1_SHIFT (0) +# define R500_TX_WEIGHT_0_SHIFT (11) +# define R500_TX_WEIGHT_PAIR (1<<22) +# define R500_TX_PHASE_SHIFT (23) +# define R500_TX_DIRECTION_HORIZONTAL (0<<27) +# define R500_TX_DIRECTION_VERITCAL (1<<27) + +/* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ +#define R300_GA_POINT_S0 0x4200 + +/* T Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ +#define R300_GA_POINT_T0 0x4204 + +/* S Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ +#define R300_GA_POINT_S1 0x4208 + +/* T Texture Coordinate of Vertex 2 for Point texture stuffing (URC) */ +#define R300_GA_POINT_T1 0x420c + +/* Specifies amount to shift integer position of vertex (screen space) before + * converting to float for triangle stipple. + */ +#define R300_GA_TRIANGLE_STIPPLE 0x4214 +# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_SHIFT 0 +# define R300_GA_TRIANGLE_STIPPLE_X_SHIFT_MASK 0x0000000f +# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT 16 +# define R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_MASK 0x000f0000 + +/* The pointsize is given in multiples of 6. The pointsize can be enormous: + * Clear() renders a single point that fills the entire framebuffer. + * 1/2 Height of point; fixed (16.0), subpixel format (1/12 or 1/16, even if in + * 8b precision). + */ +#define R300_GA_POINT_SIZE 0x421C +# define R300_POINTSIZE_Y_SHIFT 0 +# define R300_POINTSIZE_Y_MASK 0x0000ffff +# define R300_POINTSIZE_X_SHIFT 16 +# define R300_POINTSIZE_X_MASK 0xffff0000 +# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) + +/* Blue fill color */ +#define R500_GA_FILL_R 0x4220 + +/* Blue fill color */ +#define R500_GA_FILL_G 0x4224 + +/* Blue fill color */ +#define R500_GA_FILL_B 0x4228 + +/* Alpha fill color */ +#define R500_GA_FILL_A 0x422c + + +/* Specifies maximum and minimum point & sprite sizes for per vertex size + * specification. The lower part (15:0) is MIN and (31:16) is max. + */ +#define R300_GA_POINT_MINMAX 0x4230 +# define R300_GA_POINT_MINMAX_MIN_SHIFT 0 +# define R300_GA_POINT_MINMAX_MIN_MASK (0xFFFF << 0) +# define R300_GA_POINT_MINMAX_MAX_SHIFT 16 +# define R300_GA_POINT_MINMAX_MAX_MASK (0xFFFF << 16) + +/* 1/2 width of line, in subpixels (1/12 or 1/16 only, even in 8b + * subprecision); (16.0) fixed format. + * + * The line width is given in multiples of 6. + * In default mode lines are classified as vertical lines. + * HO: horizontal + * VE: vertical or horizontal + * HO & VE: no classification + */ +#define R300_GA_LINE_CNTL 0x4234 +# define R300_GA_LINE_CNTL_WIDTH_SHIFT 0 +# define R300_GA_LINE_CNTL_WIDTH_MASK 0x0000ffff +# define R300_GA_LINE_CNTL_END_TYPE_HOR (0 << 16) +# define R300_GA_LINE_CNTL_END_TYPE_VER (1 << 16) +# define R300_GA_LINE_CNTL_END_TYPE_SQR (2 << 16) /* horizontal or vertical depending upon slope */ +# define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */ +# define R500_GA_LINE_CNTL_SORT_NO (0 << 18) +# define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18) +/** TODO: looks wrong */ +# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6) +/** TODO: looks wrong */ +# define R300_LINE_CNT_HO (1 << 16) +/** TODO: looks wrong */ +# define R300_LINE_CNT_VE (1 << 17) + +/* Line Stipple configuration information. */ +#define R300_GA_LINE_STIPPLE_CONFIG 0x4238 +# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_NO (0 << 0) +# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE (1 << 0) +# define R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_PACKET (2 << 0) +# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_SHIFT 2 +# define R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK 0xfffffffc + +/* Used to load US instructions and constants */ +#define R500_GA_US_VECTOR_INDEX 0x4250 +# define R500_GA_US_VECTOR_INDEX_SHIFT 0 +# define R500_GA_US_VECTOR_INDEX_MASK 0x000000ff +# define R500_GA_US_VECTOR_INDEX_TYPE_INSTR (0 << 16) +# define R500_GA_US_VECTOR_INDEX_TYPE_CONST (1 << 16) +# define R500_GA_US_VECTOR_INDEX_CLAMP_NO (0 << 17) +# define R500_GA_US_VECTOR_INDEX_CLAMP_CONST (1 << 17) + +/* Data register for loading US instructions and constants */ +#define R500_GA_US_VECTOR_DATA 0x4254 + +/* Specifies color properties and mappings of textures. */ +#define R500_GA_COLOR_CONTROL_PS3 0x4258 +# define R500_TEX0_SHADING_PS3_SOLID (0 << 0) +# define R500_TEX0_SHADING_PS3_FLAT (1 << 0) +# define R500_TEX0_SHADING_PS3_GOURAUD (2 << 0) +# define R500_TEX1_SHADING_PS3_SOLID (0 << 2) +# define R500_TEX1_SHADING_PS3_FLAT (1 << 2) +# define R500_TEX1_SHADING_PS3_GOURAUD (2 << 2) +# define R500_TEX2_SHADING_PS3_SOLID (0 << 4) +# define R500_TEX2_SHADING_PS3_FLAT (1 << 4) +# define R500_TEX2_SHADING_PS3_GOURAUD (2 << 4) +# define R500_TEX3_SHADING_PS3_SOLID (0 << 6) +# define R500_TEX3_SHADING_PS3_FLAT (1 << 6) +# define R500_TEX3_SHADING_PS3_GOURAUD (2 << 6) +# define R500_TEX4_SHADING_PS3_SOLID (0 << 8) +# define R500_TEX4_SHADING_PS3_FLAT (1 << 8) +# define R500_TEX4_SHADING_PS3_GOURAUD (2 << 8) +# define R500_TEX5_SHADING_PS3_SOLID (0 << 10) +# define R500_TEX5_SHADING_PS3_FLAT (1 << 10) +# define R500_TEX5_SHADING_PS3_GOURAUD (2 << 10) +# define R500_TEX6_SHADING_PS3_SOLID (0 << 12) +# define R500_TEX6_SHADING_PS3_FLAT (1 << 12) +# define R500_TEX6_SHADING_PS3_GOURAUD (2 << 12) +# define R500_TEX7_SHADING_PS3_SOLID (0 << 14) +# define R500_TEX7_SHADING_PS3_FLAT (1 << 14) +# define R500_TEX7_SHADING_PS3_GOURAUD (2 << 14) +# define R500_TEX8_SHADING_PS3_SOLID (0 << 16) +# define R500_TEX8_SHADING_PS3_FLAT (1 << 16) +# define R500_TEX8_SHADING_PS3_GOURAUD (2 << 16) +# define R500_TEX9_SHADING_PS3_SOLID (0 << 18) +# define R500_TEX9_SHADING_PS3_FLAT (1 << 18) +# define R500_TEX9_SHADING_PS3_GOURAUD (2 << 18) +# define R500_TEX10_SHADING_PS3_SOLID (0 << 20) +# define R500_TEX10_SHADING_PS3_FLAT (1 << 20) +# define R500_TEX10_SHADING_PS3_GOURAUD (2 << 20) +# define R500_COLOR0_TEX_OVERRIDE_NO (0 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_0 (1 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_1 (2 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_2 (3 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_3 (4 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_4 (5 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_5 (6 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_6 (7 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_7 (8 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_8_C2 (9 << 22) +# define R500_COLOR0_TEX_OVERRIDE_TEX_9_C3 (10 << 22) +# define R500_COLOR1_TEX_OVERRIDE_NO (0 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_0 (1 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_1 (2 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_2 (3 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_3 (4 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_4 (5 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_5 (6 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_6 (7 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_7 (8 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_8_C2 (9 << 26) +# define R500_COLOR1_TEX_OVERRIDE_TEX_9_C3 (10 << 26) + +/* Returns idle status of various G3D block, captured when GA_IDLE written or + * when hard or soft reset asserted. + */ +#define R500_GA_IDLE 0x425c +# define R500_GA_IDLE_PIPE3_Z_IDLE (0 << 0) +# define R500_GA_IDLE_PIPE2_Z_IDLE (0 << 1) +# define R500_GA_IDLE_PIPE3_CD_IDLE (0 << 2) +# define R500_GA_IDLE_PIPE2_CD_IDLE (0 << 3) +# define R500_GA_IDLE_PIPE3_FG_IDLE (0 << 4) +# define R500_GA_IDLE_PIPE2_FG_IDLE (0 << 5) +# define R500_GA_IDLE_PIPE3_US_IDLE (0 << 6) +# define R500_GA_IDLE_PIPE2_US_IDLE (0 << 7) +# define R500_GA_IDLE_PIPE3_SC_IDLE (0 << 8) +# define R500_GA_IDLE_PIPE2_SC_IDLE (0 << 9) +# define R500_GA_IDLE_PIPE3_RS_IDLE (0 << 10) +# define R500_GA_IDLE_PIPE2_RS_IDLE (0 << 11) +# define R500_GA_IDLE_PIPE1_Z_IDLE (0 << 12) +# define R500_GA_IDLE_PIPE0_Z_IDLE (0 << 13) +# define R500_GA_IDLE_PIPE1_CD_IDLE (0 << 14) +# define R500_GA_IDLE_PIPE0_CD_IDLE (0 << 15) +# define R500_GA_IDLE_PIPE1_FG_IDLE (0 << 16) +# define R500_GA_IDLE_PIPE0_FG_IDLE (0 << 17) +# define R500_GA_IDLE_PIPE1_US_IDLE (0 << 18) +# define R500_GA_IDLE_PIPE0_US_IDLE (0 << 19) +# define R500_GA_IDLE_PIPE1_SC_IDLE (0 << 20) +# define R500_GA_IDLE_PIPE0_SC_IDLE (0 << 21) +# define R500_GA_IDLE_PIPE1_RS_IDLE (0 << 22) +# define R500_GA_IDLE_PIPE0_RS_IDLE (0 << 23) +# define R500_GA_IDLE_SU_IDLE (0 << 24) +# define R500_GA_IDLE_GA_IDLE (0 << 25) +# define R500_GA_IDLE_GA_UNIT2_IDLE (0 << 26) + +/* Current value of stipple accumulator. */ +#define R300_GA_LINE_STIPPLE_VALUE 0x4260 + +/* S Texture Coordinate Value for Vertex 0 of Line (stuff textures -- i.e. AA) */ +#define R300_GA_LINE_S0 0x4264 +/* S Texture Coordinate Value for Vertex 1 of Lines (V2 of parallelogram -- stuff textures -- i.e. AA) */ +#define R300_GA_LINE_S1 0x4268 + +/* GA Input fifo high water marks */ +#define R500_GA_FIFO_CNTL 0x4270 +# define R500_GA_FIFO_CNTL_VERTEX_FIFO_MASK 0x00000007 +# define R500_GA_FIFO_CNTL_VERTEX_FIFO_SHIFT 0 +# define R500_GA_FIFO_CNTL_VERTEX_INDEX_MASK 0x00000038 +# define R500_GA_FIFO_CNTL_VERTEX_INDEX_SHIFT 3 +# define R500_GA_FIFO_CNTL_VERTEX_REG_MASK 0x00003fc0 +# define R500_GA_FIFO_CNTL_VERTEX_REG_SHIFT 6 + +/* GA enhance/tweaks */ +#define R300_GA_ENHANCE 0x4274 +# define R300_GA_ENHANCE_DEADLOCK_CNTL_NO_EFFECT (0 << 0) +# define R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL (1 << 0) /* Prevents TCL interface from deadlocking on GA side. */ +# define R300_GA_ENHANCE_FASTSYNC_CNTL_NO_EFFECT (0 << 1) +# define R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE (1 << 1) /* Enables high-performance register/primitive switching. */ +# define R500_GA_ENHANCE_REG_READWRITE_NO_EFFECT (0 << 2) /* R520+ only */ +# define R500_GA_ENHANCE_REG_READWRITE_ENABLE (1 << 2) /* R520+ only, Enables GA support of simultaneous register reads and writes. */ +# define R500_GA_ENHANCE_REG_NOSTALL_NO_EFFECT (0 << 3) +# define R500_GA_ENHANCE_REG_NOSTALL_ENABLE (1 << 3) /* Enables GA support of no-stall reads for register read back. */ + +#define R300_GA_COLOR_CONTROL 0x4278 +# define R300_GA_COLOR_CONTROL_RGB0_SHADING_SOLID (0 << 0) +# define R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT (1 << 0) +# define R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD (2 << 0) +# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_SOLID (0 << 2) +# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT (1 << 2) +# define R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD (2 << 2) +# define R300_GA_COLOR_CONTROL_RGB1_SHADING_SOLID (0 << 4) +# define R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT (1 << 4) +# define R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD (2 << 4) +# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_SOLID (0 << 6) +# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_FLAT (1 << 6) +# define R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD (2 << 6) +# define R300_GA_COLOR_CONTROL_RGB2_SHADING_SOLID (0 << 8) +# define R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT (1 << 8) +# define R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD (2 << 8) +# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_SOLID (0 << 10) +# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT (1 << 10) +# define R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD (2 << 10) +# define R300_GA_COLOR_CONTROL_RGB3_SHADING_SOLID (0 << 12) +# define R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT (1 << 12) +# define R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD (2 << 12) +# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_SOLID (0 << 14) +# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_FLAT (1 << 14) +# define R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD (2 << 14) +# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_FIRST (0 << 16) +# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_SECOND (1 << 16) +# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_THIRD (2 << 16) +# define R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST (3 << 16) + +/** TODO: might be candidate for removal */ +# define R300_RE_SHADE_MODEL_SMOOTH ( \ + R300_GA_COLOR_CONTROL_RGB0_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_GOURAUD | \ + R300_GA_COLOR_CONTROL_RGB1_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ + R300_GA_COLOR_CONTROL_RGB2_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_GOURAUD | \ + R300_GA_COLOR_CONTROL_RGB3_SHADING_GOURAUD | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \ + R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST ) +/** TODO: might be candidate for removal, the GOURAUD stuff also looks buggy to me */ +# define R300_RE_SHADE_MODEL_FLAT ( \ + R300_GA_COLOR_CONTROL_RGB0_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA0_SHADING_FLAT | \ + R300_GA_COLOR_CONTROL_RGB1_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA1_SHADING_GOURAUD | \ + R300_GA_COLOR_CONTROL_RGB2_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA2_SHADING_FLAT | \ + R300_GA_COLOR_CONTROL_RGB3_SHADING_FLAT | R300_GA_COLOR_CONTROL_ALPHA3_SHADING_GOURAUD | \ + R300_GA_COLOR_CONTROL_PROVOKING_VERTEX_LAST ) + +/* Specifies red & green components of fill color -- S312 format -- Backwards comp. */ +#define R300_GA_SOLID_RG 0x427c +# define GA_SOLID_RG_COLOR_GREEN_SHIFT 0 +# define GA_SOLID_RG_COLOR_GREEN_MASK 0x0000ffff +# define GA_SOLID_RG_COLOR_RED_SHIFT 16 +# define GA_SOLID_RG_COLOR_RED_MASK 0xffff0000 +/* Specifies blue & alpha components of fill color -- S312 format -- Backwards comp. */ +#define R300_GA_SOLID_BA 0x4280 +# define GA_SOLID_BA_COLOR_ALPHA_SHIFT 0 +# define GA_SOLID_BA_COLOR_ALPHA_MASK 0x0000ffff +# define GA_SOLID_BA_COLOR_BLUE_SHIFT 16 +# define GA_SOLID_BA_COLOR_BLUE_MASK 0xffff0000 + +/* Polygon Mode + * Dangerous + */ +#define R300_GA_POLY_MODE 0x4288 +# define R300_GA_POLY_MODE_DISABLE (0 << 0) +# define R300_GA_POLY_MODE_DUAL (1 << 0) /* send 2 sets of 3 polys with specified poly type */ +/* reserved */ +# define R300_GA_POLY_MODE_FRONT_PTYPE_POINT (0 << 4) +# define R300_GA_POLY_MODE_FRONT_PTYPE_LINE (1 << 4) +# define R300_GA_POLY_MODE_FRONT_PTYPE_TRI (2 << 4) +/* reserved */ +# define R300_GA_POLY_MODE_BACK_PTYPE_POINT (0 << 7) +# define R300_GA_POLY_MODE_BACK_PTYPE_LINE (1 << 7) +# define R300_GA_POLY_MODE_BACK_PTYPE_TRI (2 << 7) +/* reserved */ + +/* Specifies the rouding mode for geometry & color SPFP to FP conversions. */ +#define R300_GA_ROUND_MODE 0x428c +# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_TRUNC (0 << 0) +# define R300_GA_ROUND_MODE_GEOMETRY_ROUND_NEAREST (1 << 0) +# define R300_GA_ROUND_MODE_COLOR_ROUND_TRUNC (0 << 2) +# define R300_GA_ROUND_MODE_COLOR_ROUND_NEAREST (1 << 2) +# define R300_GA_ROUND_MODE_RGB_CLAMP_RGB (0 << 4) +# define R300_GA_ROUND_MODE_RGB_CLAMP_FP20 (1 << 4) +# define R300_GA_ROUND_MODE_ALPHA_CLAMP_RGB (0 << 5) +# define R300_GA_ROUND_MODE_ALPHA_CLAMP_FP20 (1 << 5) +# define R500_GA_ROUND_MODE_GEOMETRY_MASK_SHIFT 6 +# define R500_GA_ROUND_MODE_GEOMETRY_MASK_MASK 0x000003c0 + +/* Specifies x & y offsets for vertex data after conversion to FP. + * Offsets are in S15 format (subpixels -- 1/12 or 1/16, even in 8b + * subprecision). + */ +#define R300_GA_OFFSET 0x4290 +# define R300_GA_OFFSET_X_OFFSET_SHIFT 0 +# define R300_GA_OFFSET_X_OFFSET_MASK 0x0000ffff +# define R300_GA_OFFSET_Y_OFFSET_SHIFT 16 +# define R300_GA_OFFSET_Y_OFFSET_MASK 0xffff0000 + +/* Specifies the scale to apply to fog. */ +#define R300_GA_FOG_SCALE 0x4294 +/* Specifies the offset to apply to fog. */ +#define R300_GA_FOG_OFFSET 0x4298 +/* Specifies number of cycles to assert reset, and also causes RB3D soft reset to assert. */ +#define R300_GA_SOFT_RESET 0x429c + +/* Not sure why there are duplicate of factor and constant values. + * My best guess so far is that there are seperate zbiases for test and write. + * Ordering might be wrong. + * Some of the tests indicate that fgl has a fallback implementation of zbias + * via pixel shaders. + */ +#define R300_SU_TEX_WRAP 0x42A0 +#define R300_SU_POLY_OFFSET_FRONT_SCALE 0x42A4 +#define R300_SU_POLY_OFFSET_FRONT_OFFSET 0x42A8 +#define R300_SU_POLY_OFFSET_BACK_SCALE 0x42AC +#define R300_SU_POLY_OFFSET_BACK_OFFSET 0x42B0 + +/* This register needs to be set to (1<<1) for RV350 to correctly + * perform depth test (see --vb-triangles in r300_demo) + * Don't know about other chips. - Vladimir + * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. + * My guess is that there are two bits for each zbias primitive + * (FILL, LINE, POINT). + * One to enable depth test and one for depth write. + * Yet this doesnt explain why depth writes work ... + */ +#define R300_SU_POLY_OFFSET_ENABLE 0x42B4 +# define R300_FRONT_ENABLE (1 << 0) +# define R300_BACK_ENABLE (1 << 1) +# define R300_PARA_ENABLE (1 << 2) + +#define R300_SU_CULL_MODE 0x42B8 +# define R300_CULL_FRONT (1 << 0) +# define R300_CULL_BACK (1 << 1) +# define R300_FRONT_FACE_CCW (0 << 2) +# define R300_FRONT_FACE_CW (1 << 2) + +/* SU Depth Scale value */ +#define R300_SU_DEPTH_SCALE 0x42c0 +/* SU Depth Offset value */ +#define R300_SU_DEPTH_OFFSET 0x42c4 + + +/* BEGIN: Rasterization / Interpolators - many guesses */ + +/* + * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends + * on the vertex program, *not* the fragment program) + */ +#define R300_RS_COUNT 0x4300 +# define R300_IT_COUNT_SHIFT 0 +# define R300_IT_COUNT_MASK 0x0000007f +# define R300_IC_COUNT_SHIFT 7 +# define R300_IC_COUNT_MASK 0x00000780 +# define R300_W_ADDR_SHIFT 12 +# define R300_W_ADDR_MASK 0x0003f000 +# define R300_HIRES_DIS (0 << 18) +# define R300_HIRES_EN (1 << 18) + +#define R300_RS_INST_COUNT 0x4304 +# define R300_RS_INST_COUNT_SHIFT 0 +# define R300_RS_INST_COUNT_MASK 0x0000000f +# define R300_RS_TX_OFFSET_SHIFT 5 +# define R300_RS_TX_OFFSET_MASK 0x000000e0 + +/* gap */ + +/* Only used for texture coordinates. + * Use the source field to route texture coordinate input from the + * vertex program to the desired interpolator. Note that the source + * field is relative to the outputs the vertex program *actually* + * writes. If a vertex program only writes texcoord[1], this will + * be source index 0. + * Set INTERP_USED on all interpolators that produce data used by + * the fragment program. INTERP_USED looks like a swizzling mask, + * but I haven't seen it used that way. + * + * Note: The _UNKNOWN constants are always set in their respective + * register. I don't know if this is necessary. + */ +#define R300_RS_IP_0 0x4310 +#define R300_RS_IP_1 0x4314 +#define R300_RS_IP_2 0x4318 +#define R300_RS_IP_3 0x431C +# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */ +# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */ +# define R300_RS_TEX_PTR(x) (x << 0) +# define R300_RS_COL_PTR(x) (x << 6) +# define R300_RS_COL_FMT(x) (x << 9) +# define R300_RS_COL_FMT_RGBA 0 +# define R300_RS_COL_FMT_RGB0 1 +# define R300_RS_COL_FMT_RGB1 2 +# define R300_RS_COL_FMT_000A 4 +# define R300_RS_COL_FMT_0000 5 +# define R300_RS_COL_FMT_0001 6 +# define R300_RS_COL_FMT_111A 8 +# define R300_RS_COL_FMT_1110 9 +# define R300_RS_COL_FMT_1111 10 +# define R300_RS_SEL_S(x) (x << 13) +# define R300_RS_SEL_T(x) (x << 16) +# define R300_RS_SEL_R(x) (x << 19) +# define R300_RS_SEL_Q(x) (x << 22) +# define R300_RS_SEL_C0 0 +# define R300_RS_SEL_C1 1 +# define R300_RS_SEL_C2 2 +# define R300_RS_SEL_C3 3 +# define R300_RS_SEL_K0 4 +# define R300_RS_SEL_K1 5 + + +/* */ +#define R500_RS_INST_0 0x4320 +#define R500_RS_INST_1 0x4324 +#define R500_RS_INST_2 0x4328 +#define R500_RS_INST_3 0x432c +#define R500_RS_INST_4 0x4330 +#define R500_RS_INST_5 0x4334 +#define R500_RS_INST_6 0x4338 +#define R500_RS_INST_7 0x433c +#define R500_RS_INST_8 0x4340 +#define R500_RS_INST_9 0x4344 +#define R500_RS_INST_10 0x4348 +#define R500_RS_INST_11 0x434c +#define R500_RS_INST_12 0x4350 +#define R500_RS_INST_13 0x4354 +#define R500_RS_INST_14 0x4358 +#define R500_RS_INST_15 0x435c +#define R500_RS_INST_TEX_ID_SHIFT 0 +#define R500_RS_INST_TEX_CN_WRITE (1 << 4) +#define R500_RS_INST_TEX_ADDR_SHIFT 5 +#define R500_RS_INST_COL_ID_SHIFT 12 +#define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) +#define R500_RS_INST_COL_CN_WRITE (1 << 16) +#define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) +#define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) +#define R500_RS_INST_COL_ADDR_SHIFT 18 +#define R500_RS_INST_TEX_ADJ (1 << 25) +#define R500_RS_INST_W_CN (1 << 26) + +/* These DWORDs control how vertex data is routed into fragment program + * registers, after interpolators. + */ +#define R300_RS_INST_0 0x4330 +#define R300_RS_INST_1 0x4334 +#define R300_RS_INST_2 0x4338 +#define R300_RS_INST_3 0x433C /* GUESS */ +#define R300_RS_INST_4 0x4340 /* GUESS */ +#define R300_RS_INST_5 0x4344 /* GUESS */ +#define R300_RS_INST_6 0x4348 /* GUESS */ +#define R300_RS_INST_7 0x434C /* GUESS */ +# define R300_RS_INST_TEX_ID(x) ((x) << 0) +# define R300_RS_INST_TEX_CN_WRITE (1 << 3) +# define R300_RS_INST_TEX_ADDR_SHIFT 6 +# define R300_RS_INST_COL_ID(x) ((x) << 11) +# define R300_RS_INST_COL_CN_WRITE (1 << 14) +# define R300_RS_INST_COL_ADDR_SHIFT 17 +# define R300_RS_INST_TEX_ADJ (1 << 22) +# define R300_RS_COL_BIAS_UNUSED_SHIFT 23 + +/* END: Rasterization / Interpolators - many guesses */ + +/* Hierarchical Z Enable */ +#define R300_SC_HYPERZ 0x43a4 +# define R300_SC_HYPERZ_DISABLE (0 << 0) +# define R300_SC_HYPERZ_ENABLE (1 << 0) +# define R300_SC_HYPERZ_MIN (0 << 1) +# define R300_SC_HYPERZ_MAX (1 << 1) +# define R300_SC_HYPERZ_ADJ_256 (0 << 2) +# define R300_SC_HYPERZ_ADJ_128 (1 << 2) +# define R300_SC_HYPERZ_ADJ_64 (2 << 2) +# define R300_SC_HYPERZ_ADJ_32 (3 << 2) +# define R300_SC_HYPERZ_ADJ_16 (4 << 2) +# define R300_SC_HYPERZ_ADJ_8 (5 << 2) +# define R300_SC_HYPERZ_ADJ_4 (6 << 2) +# define R300_SC_HYPERZ_ADJ_2 (7 << 2) +# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) +# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) +# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) +# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) + +#define R300_SC_EDGERULE 0x43a8 + +/* BEGIN: Scissors and cliprects */ + +/* There are four clipping rectangles. Their corner coordinates are inclusive. + * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending + * on whether the pixel is inside cliprects 0-3, respectively. For example, + * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned + * the number 3 (binary 0011). + * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, + * the pixel is rasterized. + * + * In addition to this, there is a scissors rectangle. Only pixels inside the + * scissors rectangle are drawn. (coordinates are inclusive) + * + * For some reason, the top-left corner of the framebuffer is at (1440, 1440) + * for the purpose of clipping and scissors. + */ +#define R300_SC_CLIPRECT_TL_0 0x43B0 +#define R300_SC_CLIPRECT_BR_0 0x43B4 +#define R300_SC_CLIPRECT_TL_1 0x43B8 +#define R300_SC_CLIPRECT_BR_1 0x43BC +#define R300_SC_CLIPRECT_TL_2 0x43C0 +#define R300_SC_CLIPRECT_BR_2 0x43C4 +#define R300_SC_CLIPRECT_TL_3 0x43C8 +#define R300_SC_CLIPRECT_BR_3 0x43CC +# define R300_CLIPRECT_OFFSET 1440 +# define R300_CLIPRECT_MASK 0x1FFF +# define R300_CLIPRECT_X_SHIFT 0 +# define R300_CLIPRECT_X_MASK (0x1FFF << 0) +# define R300_CLIPRECT_Y_SHIFT 13 +# define R300_CLIPRECT_Y_MASK (0x1FFF << 13) +#define R300_SC_CLIP_RULE 0x43D0 +# define R300_CLIP_OUT (1 << 0) +# define R300_CLIP_0 (1 << 1) +# define R300_CLIP_1 (1 << 2) +# define R300_CLIP_10 (1 << 3) +# define R300_CLIP_2 (1 << 4) +# define R300_CLIP_20 (1 << 5) +# define R300_CLIP_21 (1 << 6) +# define R300_CLIP_210 (1 << 7) +# define R300_CLIP_3 (1 << 8) +# define R300_CLIP_30 (1 << 9) +# define R300_CLIP_31 (1 << 10) +# define R300_CLIP_310 (1 << 11) +# define R300_CLIP_32 (1 << 12) +# define R300_CLIP_320 (1 << 13) +# define R300_CLIP_321 (1 << 14) +# define R300_CLIP_3210 (1 << 15) + +/* gap */ + +#define R300_SC_SCISSORS_TL 0x43E0 +#define R300_SC_SCISSORS_BR 0x43E4 +# define R300_SCISSORS_OFFSET 1440 +# define R300_SCISSORS_X_SHIFT 0 +# define R300_SCISSORS_X_MASK (0x1FFF << 0) +# define R300_SCISSORS_Y_SHIFT 13 +# define R300_SCISSORS_Y_MASK (0x1FFF << 13) + +/* Screen door sample mask */ +#define R300_SC_SCREENDOOR 0x43e8 + +/* END: Scissors and cliprects */ + +/* BEGIN: Texture specification */ + +/* + * The texture specification dwords are grouped by meaning and not by texture + * unit. This means that e.g. the offset for texture image unit N is found in + * register TX_OFFSET_0 + (4*N) + */ +#define R300_TX_FILTER0_0 0x4400 +#define R300_TX_FILTER0_1 0x4404 +#define R300_TX_FILTER0_2 0x4408 +#define R300_TX_FILTER0_3 0x440c +#define R300_TX_FILTER0_4 0x4410 +#define R300_TX_FILTER0_5 0x4414 +#define R300_TX_FILTER0_6 0x4418 +#define R300_TX_FILTER0_7 0x441c +#define R300_TX_FILTER0_8 0x4420 +#define R300_TX_FILTER0_9 0x4424 +#define R300_TX_FILTER0_10 0x4428 +#define R300_TX_FILTER0_11 0x442c +#define R300_TX_FILTER0_12 0x4430 +#define R300_TX_FILTER0_13 0x4434 +#define R300_TX_FILTER0_14 0x4438 +#define R300_TX_FILTER0_15 0x443c +# define R300_TX_REPEAT 0 +# define R300_TX_MIRRORED 1 +# define R300_TX_CLAMP_TO_EDGE 2 +# define R300_TX_MIRROR_ONCE_TO_EDGE 3 +# define R300_TX_CLAMP 4 +# define R300_TX_MIRROR_ONCE 5 +# define R300_TX_CLAMP_TO_BORDER 6 +# define R300_TX_MIRROR_ONCE_TO_BORDER 7 +# define R300_TX_WRAP_S_SHIFT 0 +# define R300_TX_WRAP_S_MASK (7 << 0) +# define R300_TX_WRAP_T_SHIFT 3 +# define R300_TX_WRAP_T_MASK (7 << 3) +# define R300_TX_WRAP_R_SHIFT 6 +# define R300_TX_WRAP_R_MASK (7 << 6) +# define R300_TX_MAG_FILTER_4 (0 << 9) +# define R300_TX_MAG_FILTER_NEAREST (1 << 9) +# define R300_TX_MAG_FILTER_LINEAR (2 << 9) +# define R300_TX_MAG_FILTER_ANISO (3 << 9) +# define R300_TX_MAG_FILTER_MASK (3 << 9) +# define R300_TX_MIN_FILTER_NEAREST (1 << 11) +# define R300_TX_MIN_FILTER_LINEAR (2 << 11) +# define R300_TX_MIN_FILTER_ANISO (3 << 11) +# define R300_TX_MIN_FILTER_MASK (3 << 11) +# define R300_TX_MIN_FILTER_MIP_NONE (0 << 13) +# define R300_TX_MIN_FILTER_MIP_NEAREST (1 << 13) +# define R300_TX_MIN_FILTER_MIP_LINEAR (2 << 13) +# define R300_TX_MIN_FILTER_MIP_MASK (3 << 13) +# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) +# define R300_TX_MAX_ANISO_2_TO_1 (1 << 21) +# define R300_TX_MAX_ANISO_4_TO_1 (2 << 21) +# define R300_TX_MAX_ANISO_8_TO_1 (3 << 21) +# define R300_TX_MAX_ANISO_16_TO_1 (4 << 21) +# define R300_TX_MAX_ANISO_MASK (7 << 21) + +#define R300_TX_FILTER1_0 0x4440 +# define R300_CHROMA_KEY_MODE_DISABLE 0 +# define R300_CHROMA_KEY_FORCE 1 +# define R300_CHROMA_KEY_BLEND 2 +# define R300_MC_ROUND_NORMAL (0<<2) +# define R300_MC_ROUND_MPEG4 (1<<2) +# define R300_LOD_BIAS_SHIFT 3 +# define R300_LOD_BIAS_MASK 0x1ff8 +# define R300_EDGE_ANISO_EDGE_DIAG (0<<13) +# define R300_EDGE_ANISO_EDGE_ONLY (1<<13) +# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) +# define R300_MC_COORD_TRUNCATE_MPEG (1<<14) +# define R300_TX_TRI_PERF_0_8 (0<<15) +# define R300_TX_TRI_PERF_1_8 (1<<15) +# define R300_TX_TRI_PERF_1_4 (2<<15) +# define R300_TX_TRI_PERF_3_8 (3<<15) +# define R300_ANISO_THRESHOLD_MASK (7<<17) + +# define R500_MACRO_SWITCH (1<<22) +# define R500_BORDER_FIX (1<<31) + +#define R300_TX_SIZE_0 0x4480 +# define R300_TX_WIDTHMASK_SHIFT 0 +# define R300_TX_WIDTHMASK_MASK (2047 << 0) +# define R300_TX_HEIGHTMASK_SHIFT 11 +# define R300_TX_HEIGHTMASK_MASK (2047 << 11) +# define R300_TX_DEPTHMASK_SHIFT 22 +# define R300_TX_DEPTHMASK_MASK (0xf << 22) +# define R300_TX_MAX_MIP_LEVEL_SHIFT 26 +# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26) +# define R300_TX_SIZE_PROJECTED (1<<30) +# define R300_TX_SIZE_TXPITCH_EN (1<<31) +#define R300_TX_FORMAT_0 0x44C0 + /* The interpretation of the format word by Wladimir van der Laan */ + /* The X, Y, Z and W refer to the layout of the components. + They are given meanings as R, G, B and Alpha by the swizzle + specification */ +# define R300_TX_FORMAT_X8 0x0 +# define R500_TX_FORMAT_X1 0x0 // bit set in format 2 +# define R300_TX_FORMAT_X16 0x1 +# define R500_TX_FORMAT_X1_REV 0x0 // bit set in format 2 +# define R300_TX_FORMAT_Y4X4 0x2 +# define R300_TX_FORMAT_Y8X8 0x3 +# define R300_TX_FORMAT_Y16X16 0x4 +# define R300_TX_FORMAT_Z3Y3X2 0x5 +# define R300_TX_FORMAT_Z5Y6X5 0x6 +# define R300_TX_FORMAT_Z6Y5X5 0x7 +# define R300_TX_FORMAT_Z11Y11X10 0x8 +# define R300_TX_FORMAT_Z10Y11X11 0x9 +# define R300_TX_FORMAT_W4Z4Y4X4 0xA +# define R300_TX_FORMAT_W1Z5Y5X5 0xB +# define R300_TX_FORMAT_W8Z8Y8X8 0xC +# define R300_TX_FORMAT_W2Z10Y10X10 0xD +# define R300_TX_FORMAT_W16Z16Y16X16 0xE +# define R300_TX_FORMAT_DXT1 0xF +# define R300_TX_FORMAT_DXT3 0x10 +# define R300_TX_FORMAT_DXT5 0x11 +# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ +# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ +# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ +# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ + + /* These two values are wrong, but they're the only values that + * produce any even vaguely correct results. Can r300 only do 16-bit + * depth textures? + */ +# define R300_TX_FORMAT_X24_Y8 0x1e +# define R300_TX_FORMAT_X32 0x1e + + /* 0x16 - some 16 bit green format.. ?? */ +# define R300_TX_FORMAT_3D (1 << 25) +# define R300_TX_FORMAT_CUBIC_MAP (2 << 25) + + /* gap */ + /* Floating point formats */ + /* Note - hardware supports both 16 and 32 bit floating point */ +# define R300_TX_FORMAT_FL_I16 0x18 +# define R300_TX_FORMAT_FL_I16A16 0x19 +# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A +# define R300_TX_FORMAT_FL_I32 0x1B +# define R300_TX_FORMAT_FL_I32A32 0x1C +# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D + /* alpha modes, convenience mostly */ + /* if you have alpha, pick constant appropriate to the + number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ +# define R300_TX_FORMAT_ALPHA_1CH 0x000 +# define R300_TX_FORMAT_ALPHA_2CH 0x200 +# define R300_TX_FORMAT_ALPHA_4CH 0x600 +# define R300_TX_FORMAT_ALPHA_NONE 0xA00 + /* Swizzling */ + /* constants */ +# define R300_TX_FORMAT_X 0 +# define R300_TX_FORMAT_Y 1 +# define R300_TX_FORMAT_Z 2 +# define R300_TX_FORMAT_W 3 +# define R300_TX_FORMAT_ZERO 4 +# define R300_TX_FORMAT_ONE 5 + /* 2.0*Z, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_Z 6 + /* 2.0*W, everything above 1.0 is set to 0.0 */ +# define R300_TX_FORMAT_CUT_W 7 + +# define R300_TX_FORMAT_B_SHIFT 18 +# define R300_TX_FORMAT_G_SHIFT 15 +# define R300_TX_FORMAT_R_SHIFT 12 +# define R300_TX_FORMAT_A_SHIFT 9 + /* Convenience macro to take care of layout and swizzling */ +# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ + ((R300_TX_FORMAT_##B)< 0.5, return ARG0, else return ARG1 + * - CMP: If ARG2 < 0, return ARG1, else return ARG0 + * - FLR: use FRC+MAD + * - XPD: use MAD+MAD + * - SGE, SLT: use MAD+CMP + * - RSQ: use ABS modifier for argument + * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation + * (e.g. RCP) into color register + * - apparently, there's no quick DST operation + * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" + * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" + * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" + * + * Operand selection + * First stage selects three sources from the available registers and + * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). + * fglrx sorts the three source fields: Registers before constants, + * lower indices before higher indices; I do not know whether this is + * necessary. + * + * fglrx fills unused sources with "read constant 0" + * According to specs, you cannot select more than two different constants. + * + * Second stage selects the operands from the sources. This is defined in + * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants + * zero and one. + * Swizzling and negation happens in this stage, as well. + * + * Important: Color and alpha seem to be mostly separate, i.e. their sources + * selection appears to be fully independent (the register storage is probably + * physically split into a color and an alpha section). + * However (because of the apparent physical split), there is some interaction + * WRT swizzling. If, for example, you want to load an R component into an + * Alpha operand, this R component is taken from a *color* source, not from + * an alpha source. The corresponding register doesn't even have to appear in + * the alpha sources list. (I hope this all makes sense to you) + * + * Destination selection + * The destination register index is in FPI1 (color) and FPI3 (alpha) + * together with enable bits. + * There are separate enable bits for writing into temporary registers + * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* + * /DSTA_OUTPUT). You can write to both at once, or not write at all (the + * same index must be used for both). + * + * Note: There is a special form for LRP + * - Argument order is the same as in ARB_fragment_program. + * - Operation is MAD + * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP + * - Set FPI0/FPI2_SPECIAL_LRP + * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD + */ +#define R300_US_ALU_RGB_ADDR_0 0x46C0 +# define R300_ALU_SRC0C_SHIFT 0 +# define R300_ALU_SRC0C_MASK (31 << 0) +# define R300_ALU_SRC0C_CONST (1 << 5) +# define R300_ALU_SRC1C_SHIFT 6 +# define R300_ALU_SRC1C_MASK (31 << 6) +# define R300_ALU_SRC1C_CONST (1 << 11) +# define R300_ALU_SRC2C_SHIFT 12 +# define R300_ALU_SRC2C_MASK (31 << 12) +# define R300_ALU_SRC2C_CONST (1 << 17) +# define R300_ALU_SRC_MASK 0x0003ffff +# define R300_ALU_DSTC_SHIFT 18 +# define R300_ALU_DSTC_MASK (31 << 18) +# define R300_ALU_DSTC_REG_MASK_SHIFT 23 +# define R300_ALU_DSTC_REG_X (1 << 23) +# define R300_ALU_DSTC_REG_Y (1 << 24) +# define R300_ALU_DSTC_REG_Z (1 << 25) +# define R300_ALU_DSTC_OUTPUT_MASK_SHIFT 26 +# define R300_ALU_DSTC_OUTPUT_X (1 << 26) +# define R300_ALU_DSTC_OUTPUT_Y (1 << 27) +# define R300_ALU_DSTC_OUTPUT_Z (1 << 28) + +#define R300_US_ALU_ALPHA_ADDR_0 0x47C0 +# define R300_ALU_SRC0A_SHIFT 0 +# define R300_ALU_SRC0A_MASK (31 << 0) +# define R300_ALU_SRC0A_CONST (1 << 5) +# define R300_ALU_SRC1A_SHIFT 6 +# define R300_ALU_SRC1A_MASK (31 << 6) +# define R300_ALU_SRC1A_CONST (1 << 11) +# define R300_ALU_SRC2A_SHIFT 12 +# define R300_ALU_SRC2A_MASK (31 << 12) +# define R300_ALU_SRC2A_CONST (1 << 17) +# define R300_ALU_SRC_MASK 0x0003ffff +# define R300_ALU_DSTA_SHIFT 18 +# define R300_ALU_DSTA_MASK (31 << 18) +# define R300_ALU_DSTA_REG (1 << 23) +# define R300_ALU_DSTA_OUTPUT (1 << 24) +# define R300_ALU_DSTA_DEPTH (1 << 27) + +#define R300_US_ALU_RGB_INST_0 0x48C0 +# define R300_ALU_ARGC_SRC0C_XYZ 0 +# define R300_ALU_ARGC_SRC0C_XXX 1 +# define R300_ALU_ARGC_SRC0C_YYY 2 +# define R300_ALU_ARGC_SRC0C_ZZZ 3 +# define R300_ALU_ARGC_SRC1C_XYZ 4 +# define R300_ALU_ARGC_SRC1C_XXX 5 +# define R300_ALU_ARGC_SRC1C_YYY 6 +# define R300_ALU_ARGC_SRC1C_ZZZ 7 +# define R300_ALU_ARGC_SRC2C_XYZ 8 +# define R300_ALU_ARGC_SRC2C_XXX 9 +# define R300_ALU_ARGC_SRC2C_YYY 10 +# define R300_ALU_ARGC_SRC2C_ZZZ 11 +# define R300_ALU_ARGC_SRC0A 12 +# define R300_ALU_ARGC_SRC1A 13 +# define R300_ALU_ARGC_SRC2A 14 +# define R300_ALU_ARGC_SRCP_XYZ 15 +# define R300_ALU_ARGC_SRCP_XXX 16 +# define R300_ALU_ARGC_SRCP_YYY 17 +# define R300_ALU_ARGC_SRCP_ZZZ 18 +# define R300_ALU_ARGC_SRCP_WWW 19 +# define R300_ALU_ARGC_ZERO 20 +# define R300_ALU_ARGC_ONE 21 +# define R300_ALU_ARGC_HALF 22 +# define R300_ALU_ARGC_SRC0C_YZX 23 +# define R300_ALU_ARGC_SRC1C_YZX 24 +# define R300_ALU_ARGC_SRC2C_YZX 25 +# define R300_ALU_ARGC_SRC0C_ZXY 26 +# define R300_ALU_ARGC_SRC1C_ZXY 27 +# define R300_ALU_ARGC_SRC2C_ZXY 28 +# define R300_ALU_ARGC_SRC0CA_WZY 29 +# define R300_ALU_ARGC_SRC1CA_WZY 30 +# define R300_ALU_ARGC_SRC2CA_WZY 31 + +# define R300_ALU_ARG0C_SHIFT 0 +# define R300_ALU_ARG0C_MASK (31 << 0) +# define R300_ALU_ARG0C_NOP (0 << 5) +# define R300_ALU_ARG0C_NEG (1 << 5) +# define R300_ALU_ARG0C_ABS (2 << 5) +# define R300_ALU_ARG0C_NAB (3 << 5) +# define R300_ALU_ARG1C_SHIFT 7 +# define R300_ALU_ARG1C_MASK (31 << 7) +# define R300_ALU_ARG1C_NOP (0 << 12) +# define R300_ALU_ARG1C_NEG (1 << 12) +# define R300_ALU_ARG1C_ABS (2 << 12) +# define R300_ALU_ARG1C_NAB (3 << 12) +# define R300_ALU_ARG2C_SHIFT 14 +# define R300_ALU_ARG2C_MASK (31 << 14) +# define R300_ALU_ARG2C_NOP (0 << 19) +# define R300_ALU_ARG2C_NEG (1 << 19) +# define R300_ALU_ARG2C_ABS (2 << 19) +# define R300_ALU_ARG2C_NAB (3 << 19) +# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21) +# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21) +# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21) +# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21) + +# define R300_ALU_OUTC_MAD (0 << 23) +# define R300_ALU_OUTC_DP3 (1 << 23) +# define R300_ALU_OUTC_DP4 (2 << 23) +# define R300_ALU_OUTC_D2A (3 << 23) +# define R300_ALU_OUTC_MIN (4 << 23) +# define R300_ALU_OUTC_MAX (5 << 23) +# define R300_ALU_OUTC_CMPH (7 << 23) +# define R300_ALU_OUTC_CMP (8 << 23) +# define R300_ALU_OUTC_FRC (9 << 23) +# define R300_ALU_OUTC_REPL_ALPHA (10 << 23) + +# define R300_ALU_OUTC_MOD_NOP (0 << 27) +# define R300_ALU_OUTC_MOD_MUL2 (1 << 27) +# define R300_ALU_OUTC_MOD_MUL4 (2 << 27) +# define R300_ALU_OUTC_MOD_MUL8 (3 << 27) +# define R300_ALU_OUTC_MOD_DIV2 (4 << 27) +# define R300_ALU_OUTC_MOD_DIV4 (5 << 27) +# define R300_ALU_OUTC_MOD_DIV8 (6 << 27) + +# define R300_ALU_OUTC_CLAMP (1 << 30) +# define R300_ALU_INSERT_NOP (1 << 31) + +#define R300_US_ALU_ALPHA_INST_0 0x49C0 +# define R300_ALU_ARGA_SRC0C_X 0 +# define R300_ALU_ARGA_SRC0C_Y 1 +# define R300_ALU_ARGA_SRC0C_Z 2 +# define R300_ALU_ARGA_SRC1C_X 3 +# define R300_ALU_ARGA_SRC1C_Y 4 +# define R300_ALU_ARGA_SRC1C_Z 5 +# define R300_ALU_ARGA_SRC2C_X 6 +# define R300_ALU_ARGA_SRC2C_Y 7 +# define R300_ALU_ARGA_SRC2C_Z 8 +# define R300_ALU_ARGA_SRC0A 9 +# define R300_ALU_ARGA_SRC1A 10 +# define R300_ALU_ARGA_SRC2A 11 +# define R300_ALU_ARGA_SRCP_X 12 +# define R300_ALU_ARGA_SRCP_Y 13 +# define R300_ALU_ARGA_SRCP_Z 14 +# define R300_ALU_ARGA_SRCP_W 15 + +# define R300_ALU_ARGA_ZERO 16 +# define R300_ALU_ARGA_ONE 17 +# define R300_ALU_ARGA_HALF 18 +# define R300_ALU_ARG0A_SHIFT 0 +# define R300_ALU_ARG0A_MASK (31 << 0) +# define R300_ALU_ARG0A_NOP (0 << 5) +# define R300_ALU_ARG0A_NEG (1 << 5) +# define R300_ALU_ARG0A_ABS (2 << 5) +# define R300_ALU_ARG0A_NAB (3 << 5) +# define R300_ALU_ARG1A_SHIFT 7 +# define R300_ALU_ARG1A_MASK (31 << 7) +# define R300_ALU_ARG1A_NOP (0 << 12) +# define R300_ALU_ARG1A_NEG (1 << 12) +# define R300_ALU_ARG1A_ABS (2 << 12) +# define R300_ALU_ARG1A_NAB (3 << 12) +# define R300_ALU_ARG2A_SHIFT 14 +# define R300_ALU_ARG2A_MASK (31 << 14) +# define R300_ALU_ARG2A_NOP (0 << 19) +# define R300_ALU_ARG2A_NEG (1 << 19) +# define R300_ALU_ARG2A_ABS (2 << 19) +# define R300_ALU_ARG2A_NAB (3 << 19) +# define R300_ALU_SRCP_1_MINUS_2_SRC0 (0 << 21) +# define R300_ALU_SRCP_SRC1_MINUS_SRC0 (1 << 21) +# define R300_ALU_SRCP_SRC1_PLUS_SRC0 (2 << 21) +# define R300_ALU_SRCP_1_MINUS_SRC0 (3 << 21) + +# define R300_ALU_OUTA_MAD (0 << 23) +# define R300_ALU_OUTA_DP4 (1 << 23) +# define R300_ALU_OUTA_MIN (2 << 23) +# define R300_ALU_OUTA_MAX (3 << 23) +# define R300_ALU_OUTA_CND (5 << 23) +# define R300_ALU_OUTA_CMP (6 << 23) +# define R300_ALU_OUTA_FRC (7 << 23) +# define R300_ALU_OUTA_EX2 (8 << 23) +# define R300_ALU_OUTA_LG2 (9 << 23) +# define R300_ALU_OUTA_RCP (10 << 23) +# define R300_ALU_OUTA_RSQ (11 << 23) + +# define R300_ALU_OUTA_MOD_NOP (0 << 27) +# define R300_ALU_OUTA_MOD_MUL2 (1 << 27) +# define R300_ALU_OUTA_MOD_MUL4 (2 << 27) +# define R300_ALU_OUTA_MOD_MUL8 (3 << 27) +# define R300_ALU_OUTA_MOD_DIV2 (4 << 27) +# define R300_ALU_OUTA_MOD_DIV4 (5 << 27) +# define R300_ALU_OUTA_MOD_DIV8 (6 << 27) + +# define R300_ALU_OUTA_CLAMP (1 << 30) +/* END: Fragment program instruction set */ + +/* Fog: Fog Blending Enable */ +#define R300_FG_FOG_BLEND 0x4bc0 +# define R300_FG_FOG_BLEND_DISABLE (0 << 0) +# define R300_FG_FOG_BLEND_ENABLE (1 << 0) +# define R300_FG_FOG_BLEND_FN_LINEAR (0 << 1) +# define R300_FG_FOG_BLEND_FN_EXP (1 << 1) +# define R300_FG_FOG_BLEND_FN_EXP2 (2 << 1) +# define R300_FG_FOG_BLEND_FN_CONSTANT (3 << 1) +# define R300_FG_FOG_BLEND_FN_MASK (3 << 1) + +/* Fog: Red Component of Fog Color */ +#define R300_FG_FOG_COLOR_R 0x4bc8 +/* Fog: Green Component of Fog Color */ +#define R300_FG_FOG_COLOR_G 0x4bcc +/* Fog: Blue Component of Fog Color */ +#define R300_FG_FOG_COLOR_B 0x4bd0 +# define R300_FG_FOG_COLOR_MASK 0x000003ff + +/* Fog: Constant Factor for Fog Blending */ +#define R300_FG_FOG_FACTOR 0x4bc4 +# define FG_FOG_FACTOR_MASK 0x000003ff + +/* Fog: Alpha function */ +#define R300_FG_ALPHA_FUNC 0x4bd4 +# define R300_FG_ALPHA_FUNC_VAL_MASK 0x000000ff +# define R300_FG_ALPHA_FUNC_NEVER (0 << 8) +# define R300_FG_ALPHA_FUNC_LESS (1 << 8) +# define R300_FG_ALPHA_FUNC_EQUAL (2 << 8) +# define R300_FG_ALPHA_FUNC_LE (3 << 8) +# define R300_FG_ALPHA_FUNC_GREATER (4 << 8) +# define R300_FG_ALPHA_FUNC_NOTEQUAL (5 << 8) +# define R300_FG_ALPHA_FUNC_GE (6 << 8) +# define R300_FG_ALPHA_FUNC_ALWAYS (7 << 8) +# define R300_ALPHA_TEST_OP_MASK (7 << 8) +# define R300_FG_ALPHA_FUNC_DISABLE (0 << 11) +# define R300_FG_ALPHA_FUNC_ENABLE (1 << 11) + +# define R500_FG_ALPHA_FUNC_10BIT (0 << 12) +# define R500_FG_ALPHA_FUNC_8BIT (1 << 12) + +# define R300_FG_ALPHA_FUNC_MASK_DISABLE (0 << 16) +# define R300_FG_ALPHA_FUNC_MASK_ENABLE (1 << 16) +# define R300_FG_ALPHA_FUNC_CFG_2_OF_4 (0 << 17) +# define R300_FG_ALPHA_FUNC_CFG_3_OF_6 (1 << 17) + +# define R300_FG_ALPHA_FUNC_DITH_DISABLE (0 << 20) +# define R300_FG_ALPHA_FUNC_DITH_ENABLE (1 << 20) + +# define R500_FG_ALPHA_FUNC_OFFSET_DISABLE (0 << 24) +# define R500_FG_ALPHA_FUNC_OFFSET_ENABLE (1 << 24) /* Not supported in R520 */ +# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_DISABLE (0 << 25) +# define R500_FG_ALPHA_FUNC_DISC_ZERO_MASK_ENABLE (1 << 25) + +# define R500_FG_ALPHA_FUNC_FP16_DISABLE (0 << 28) +# define R500_FG_ALPHA_FUNC_FP16_ENABLE (1 << 28) + + +/* Fog: Where does the depth come from? */ +#define R300_FG_DEPTH_SRC 0x4bd8 +# define R300_FG_DEPTH_SRC_SCAN (0 << 0) +# define R300_FG_DEPTH_SRC_SHADER (1 << 0) + +/* Fog: Alpha Compare Value */ +#define R500_FG_ALPHA_VALUE 0x4be0 +# define R500_FG_ALPHA_VALUE_MASK 0x0000ffff + +/* gap */ + +/* Fragment program parameters in 7.16 floating point */ +#define R300_PFS_PARAM_0_X 0x4C00 +#define R300_PFS_PARAM_0_Y 0x4C04 +#define R300_PFS_PARAM_0_Z 0x4C08 +#define R300_PFS_PARAM_0_W 0x4C0C +/* last consts */ +#define R300_PFS_PARAM_31_X 0x4DF0 +#define R300_PFS_PARAM_31_Y 0x4DF4 +#define R300_PFS_PARAM_31_Z 0x4DF8 +#define R300_PFS_PARAM_31_W 0x4DFC + +/* Unpipelined. */ +#define R300_RB3D_CCTL 0x4e00 +# define R300_RB3D_CCTL_NUM_MULTIWRITES_1_BUFFER (0 << 5) +# define R300_RB3D_CCTL_NUM_MULTIWRITES_2_BUFFERS (1 << 5) +# define R300_RB3D_CCTL_NUM_MULTIWRITES_3_BUFFERS (2 << 5) +# define R300_RB3D_CCTL_NUM_MULTIWRITES_4_BUFFERS (3 << 5) +# define R300_RB3D_CCTL_CLRCMP_FLIPE_DISABLE (0 << 7) +# define R300_RB3D_CCTL_CLRCMP_FLIPE_ENABLE (1 << 7) +# define R300_RB3D_CCTL_AA_COMPRESSION_DISABLE (0 << 9) +# define R300_RB3D_CCTL_AA_COMPRESSION_ENABLE (1 << 9) +# define R300_RB3D_CCTL_CMASK_DISABLE (0 << 10) +# define R300_RB3D_CCTL_CMASK_ENABLE (1 << 10) +/* reserved */ +# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_DISABLE (0 << 12) +# define R300_RB3D_CCTL_INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE (1 << 12) +# define R300_RB3D_CCTL_WRITE_COMPRESSION_ENABLE (0 << 13) +# define R300_RB3D_CCTL_WRITE_COMPRESSION_DISABLE (1 << 13) +# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_DISABLE (0 << 14) +# define R300_RB3D_CCTL_INDEPENDENT_COLORFORMAT_ENABLE_ENABLE (1 << 14) + + +/* Notes: + * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in + * the application + * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND + * are set to the same + * function (both registers are always set up completely in any case) + * - Most blend flags are simply copied from R200 and not tested yet + */ +#define R300_RB3D_CBLEND 0x4E04 +#define R300_RB3D_ABLEND 0x4E08 +/* the following only appear in CBLEND */ +# define R300_ALPHA_BLEND_ENABLE (1 << 0) +# define R300_SEPARATE_ALPHA_ENABLE (1 << 1) +# define R300_READ_ENABLE (1 << 2) +# define R300_DISCARD_SRC_PIXELS_DIS (0 << 3) +# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0 (1 << 3) +# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_0 (2 << 3) +# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0 (3 << 3) +# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1 (4 << 3) +# define R300_DISCARD_SRC_PIXELS_SRC_COLOR_1 (5 << 3) +# define R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1 (6 << 3) + +/* the following are shared between CBLEND and ABLEND */ +# define R300_FCN_MASK (3 << 12) +# define R300_COMB_FCN_ADD_CLAMP (0 << 12) +# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) +# define R300_COMB_FCN_SUB_CLAMP (2 << 12) +# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) +# define R300_COMB_FCN_MIN (4 << 12) +# define R300_COMB_FCN_MAX (5 << 12) +# define R300_COMB_FCN_RSUB_CLAMP (6 << 12) +# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12) +# define R300_BLEND_GL_ZERO (32) +# define R300_BLEND_GL_ONE (33) +# define R300_BLEND_GL_SRC_COLOR (34) +# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35) +# define R300_BLEND_GL_DST_COLOR (36) +# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37) +# define R300_BLEND_GL_SRC_ALPHA (38) +# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) +# define R300_BLEND_GL_DST_ALPHA (40) +# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41) +# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42) +# define R300_BLEND_GL_CONST_COLOR (43) +# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44) +# define R300_BLEND_GL_CONST_ALPHA (45) +# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) +# define R300_BLEND_MASK (63) +# define R300_SRC_BLEND_SHIFT (16) +# define R300_DST_BLEND_SHIFT (24) + +/* Constant color used by the blender. Pipelined through the blender. + * Note: For R520, this field is ignored, use RB3D_CONSTANT_COLOR_GB__BLUE, + * RB3D_CONSTANT_COLOR_GB__GREEN, etc. instead. + */ +#define R300_RB3D_BLEND_COLOR 0x4E10 + + +/* 3D Color Channel Mask. If all the channels used in the current color format + * are disabled, then the cb will discard all the incoming quads. Pipelined + * through the blender. + */ +#define RB3D_COLOR_CHANNEL_MASK 0x4E0C +# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK0 (1 << 0) +# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK0 (1 << 1) +# define RB3D_COLOR_CHANNEL_MASK_RED_MASK0 (1 << 2) +# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK0 (1 << 3) +# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK1 (1 << 4) +# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK1 (1 << 5) +# define RB3D_COLOR_CHANNEL_MASK_RED_MASK1 (1 << 6) +# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK1 (1 << 7) +# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK2 (1 << 8) +# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK2 (1 << 9) +# define RB3D_COLOR_CHANNEL_MASK_RED_MASK2 (1 << 10) +# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK2 (1 << 11) +# define RB3D_COLOR_CHANNEL_MASK_BLUE_MASK3 (1 << 12) +# define RB3D_COLOR_CHANNEL_MASK_GREEN_MASK3 (1 << 13) +# define RB3D_COLOR_CHANNEL_MASK_RED_MASK3 (1 << 14) +# define RB3D_COLOR_CHANNEL_MASK_ALPHA_MASK3 (1 << 15) + +/* Clear color that is used when the color mask is set to 00. Unpipelined. + * Program this register with a 32-bit value in ARGB8888 or ARGB2101010 + * formats, ignoring the fields. + */ +#define RB3D_COLOR_CLEAR_VALUE 0x4e14 + +/* gap */ + +/* Color Compare Color. Stalls the 2d/3d datapath until it is idle. */ +#define RB3D_CLRCMP_CLR 0x4e20 + +/* Color Compare Mask. Stalls the 2d/3d datapath until it is idle. */ +#define RB3D_CLRCMP_MSK 0x4e24 + +/* Color Buffer Address Offset of multibuffer 0. Unpipelined. */ +#define R300_RB3D_COLOROFFSET0 0x4E28 +# define R300_COLOROFFSET_MASK 0xFFFFFFE0 +/* Color Buffer Address Offset of multibuffer 1. Unpipelined. */ +#define R300_RB3D_COLOROFFSET1 0x4E2C +/* Color Buffer Address Offset of multibuffer 2. Unpipelined. */ +#define R300_RB3D_COLOROFFSET2 0x4E30 +/* Color Buffer Address Offset of multibuffer 3. Unpipelined. */ +#define R300_RB3D_COLOROFFSET3 0x4E34 + +/* Color buffer format and tiling control for all the multibuffers and the + * pitch of multibuffer 0 to 3. Unpipelined. The cache must be empty before any + * of the registers are changed. + * + * Bit 16: Larger tiles + * Bit 17: 4x2 tiles + * Bit 18: Extremely weird tile like, but some pixels duplicated? + */ +#define R300_RB3D_COLORPITCH0 0x4E38 +# define R300_COLORPITCH_MASK 0x00003FFE +# define R300_COLOR_TILE_DISABLE (0 << 16) +# define R300_COLOR_TILE_ENABLE (1 << 16) +# define R300_COLOR_MICROTILE_DISABLE (0 << 17) +# define R300_COLOR_MICROTILE_ENABLE (1 << 17) +# define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */ +# define R300_COLOR_ENDIAN_NO_SWAP (0 << 19) +# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 19) +# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 19) +# define R300_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19) +# define R500_COLOR_FORMAT_ARGB10101010 (0 << 21) +# define R500_COLOR_FORMAT_UV1010 (1 << 21) +# define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */ +# define R300_COLOR_FORMAT_ARGB1555 (3 << 21) +# define R300_COLOR_FORMAT_RGB565 (4 << 21) +# define R500_COLOR_FORMAT_ARGB2101010 (5 << 21) +# define R300_COLOR_FORMAT_ARGB8888 (6 << 21) +# define R300_COLOR_FORMAT_ARGB32323232 (7 << 21) +/* reserved */ +# define R300_COLOR_FORMAT_I8 (9 << 21) +# define R300_COLOR_FORMAT_ARGB16161616 (10 << 21) +# define R300_COLOR_FORMAT_VYUY (11 << 21) +# define R300_COLOR_FORMAT_YVYU (12 << 21) +# define R300_COLOR_FORMAT_UV88 (13 << 21) +# define R500_COLOR_FORMAT_I10 (14 << 21) +# define R300_COLOR_FORMAT_ARGB4444 (15 << 21) +#define R300_RB3D_COLORPITCH1 0x4E3C +#define R300_RB3D_COLORPITCH2 0x4E40 +#define R300_RB3D_COLORPITCH3 0x4E44 + +/* gap */ + +/* Destination Color Buffer Cache Control/Status. If the cb is in e2 mode, then + * a flush or free will not occur upon a write to this register, but a sync + * will be immediately sent if one is requested. If both DC_FLUSH and DC_FREE + * are zero but DC_FINISH is one, then a sync will be sent immediately -- the + * cb will not wait for all the previous operations to complete before sending + * the sync. Unpipelined except when DC_FINISH and DC_FREE are both set to + * zero. + * + * Set to 0A before 3D operations, set to 02 afterwards. + */ +#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT (0 << 0) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_NO_EFFECT_1 (1 << 0) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D (2 << 0) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D_1 (3 << 0) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT (0 << 2) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_NO_EFFECT_1 (1 << 2) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS (2 << 2) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS_1 (3 << 2) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_NO_SIGNAL (0 << 4) +# define R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL (1 << 4) + +#define R300_RB3D_DITHER_CTL 0x4E50 +# define R300_RB3D_DITHER_CTL_DITHER_MODE_TRUNCATE (0 << 0) +# define R300_RB3D_DITHER_CTL_DITHER_MODE_ROUND (1 << 0) +# define R300_RB3D_DITHER_CTL_DITHER_MODE_LUT (2 << 0) +/* reserved */ +# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_TRUNCATE (0 << 2) +# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_ROUND (1 << 2) +# define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2) +/* reserved */ + +/* Resolve buffer destination address. The cache must be empty before changing + * this register if the cb is in resolve mode. Unpipelined + */ +#define R300_RB3D_AARESOLVE_OFFSET 0x4e80 +# define R300_RB3D_AARESOLVE_OFFSET_SHIFT 5 +# define R300_RB3D_AARESOLVE_OFFSET_MASK 0xffffffe0 /* At least according to the calculations of Christoph Brill */ + +/* Resolve Buffer Pitch and Tiling Control. The cache must be empty before + * changing this register if the cb is in resolve mode. Unpipelined + */ +#define R300_RB3D_AARESOLVE_PITCH 0x4e84 +# define R300_RB3D_AARESOLVE_PITCH_SHIFT 1 +# define R300_RB3D_AARESOLVE_PITCH_MASK 0x00003ffe /* At least according to the calculations of Christoph Brill */ + +/* Resolve Buffer Control. Unpipelined */ +#define R300_RB3D_AARESOLVE_CTL 0x4e88 +# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_NORMAL (0 << 0) +# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_MODE_RESOLVE (1 << 0) +# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_10 (0 << 1) +# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_GAMMA_22 (1 << 1) +# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_SAMPLE0 (0 << 2) +# define R300_RB3D_AARESOLVE_CTL_AARESOLVE_ALPHA_AVERAGE (1 << 2) + + +/* Discard src pixels less than or equal to threshold. */ +#define R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0 +/* Discard src pixels greater than or equal to threshold. */ +#define R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4 +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_SHIFT 0 +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_BLUE_MASK 0x000000ff +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_SHIFT 8 +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_GREEN_MASK 0x0000ff00 +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_SHIFT 16 +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_RED_MASK 0x00ff0000 +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_SHIFT 24 +# define R500_RB3D_DISCARD_SRC_PIXEL_THRESHOLD_ALPHA_MASK 0xff000000 + +/* 3D ROP Control. Stalls the 2d/3d datapath until it is idle. */ +#define R300_RB3D_ROPCNTL 0x4e18 +# define R300_RB3D_ROPCNTL_ROP_ENABLE 0x00000004 +# define R300_RB3D_ROPCNTL_ROP_MASK (15 << 8) +# define R300_RB3D_ROPCNTL_ROP_SHIFT 8 + +/* Color Compare Flip. Stalls the 2d/3d datapath until it is idle. */ +#define R300_RB3D_CLRCMP_FLIPE 0x4e1c + +/* Sets the fifo sizes */ +#define R500_RB3D_FIFO_SIZE 0x4ef4 +# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0) +# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0) +# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0) +# define R500_RB3D_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (3 << 0) + +/* Constant color used by the blender. Pipelined through the blender. */ +#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 +# define R500_RB3D_CONSTANT_COLOR_AR_RED_MASK 0x0000ffff +# define R500_RB3D_CONSTANT_COLOR_AR_RED_SHIFT 0 +# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_MASK 0xffff0000 +# define R500_RB3D_CONSTANT_COLOR_AR_ALPHA_SHIFT 16 + +/* Constant color used by the blender. Pipelined through the blender. */ +#define R500_RB3D_CONSTANT_COLOR_GB 0x4efc +# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_MASK 0x0000ffff +# define R500_RB3D_CONSTANT_COLOR_AR_BLUE_SHIFT 0 +# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_MASK 0xffff0000 +# define R500_RB3D_CONSTANT_COLOR_AR_GREEN_SHIFT 16 + +/* gap */ +/* There seems to be no "write only" setting, so use Z-test = ALWAYS + * for this. + * Bit (1<<8) is the "test" bit. so plain write is 6 - vd + */ +#define R300_ZB_CNTL 0x4F00 +# define R300_STENCIL_ENABLE (1 << 0) +# define R300_Z_ENABLE (1 << 1) +# define R300_Z_WRITE_ENABLE (1 << 2) +# define R300_Z_SIGNED_COMPARE (1 << 3) +# define R300_STENCIL_FRONT_BACK (1 << 4) + +#define R300_ZB_ZSTENCILCNTL 0x4f04 + /* functions */ +# define R300_ZS_NEVER 0 +# define R300_ZS_LESS 1 +# define R300_ZS_LEQUAL 2 +# define R300_ZS_EQUAL 3 +# define R300_ZS_GEQUAL 4 +# define R300_ZS_GREATER 5 +# define R300_ZS_NOTEQUAL 6 +# define R300_ZS_ALWAYS 7 +# define R300_ZS_MASK 7 + /* operations */ +# define R300_ZS_KEEP 0 +# define R300_ZS_ZERO 1 +# define R300_ZS_REPLACE 2 +# define R300_ZS_INCR 3 +# define R300_ZS_DECR 4 +# define R300_ZS_INVERT 5 +# define R300_ZS_INCR_WRAP 6 +# define R300_ZS_DECR_WRAP 7 +# define R300_Z_FUNC_SHIFT 0 + /* front and back refer to operations done for front + and back faces, i.e. separate stencil function support */ +# define R300_S_FRONT_FUNC_SHIFT 3 +# define R300_S_FRONT_SFAIL_OP_SHIFT 6 +# define R300_S_FRONT_ZPASS_OP_SHIFT 9 +# define R300_S_FRONT_ZFAIL_OP_SHIFT 12 +# define R300_S_BACK_FUNC_SHIFT 15 +# define R300_S_BACK_SFAIL_OP_SHIFT 18 +# define R300_S_BACK_ZPASS_OP_SHIFT 21 +# define R300_S_BACK_ZFAIL_OP_SHIFT 24 + +#define R300_ZB_STENCILREFMASK 0x4f08 +# define R300_STENCILREF_SHIFT 0 +# define R300_STENCILREF_MASK 0x000000ff +# define R300_STENCILMASK_SHIFT 8 +# define R300_STENCILMASK_MASK 0x0000ff00 +# define R300_STENCILWRITEMASK_SHIFT 16 +# define R300_STENCILWRITEMASK_MASK 0x00ff0000 + +/* gap */ + +#define R300_ZB_FORMAT 0x4f10 +# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) +# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) +# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) +/* reserved up to (15 << 0) */ +# define R300_INVERT_13E3_LEADING_ONES (0 << 4) +# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) + +#define R300_ZB_ZTOP 0x4F14 +# define R300_ZTOP_DISABLE (0 << 0) +# define R300_ZTOP_ENABLE (1 << 0) + +/* gap */ + +#define R300_ZB_ZCACHE_CTLSTAT 0x4f18 +# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) +# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) + +#define R300_ZB_BW_CNTL 0x4f1c +# define R300_HIZ_DISABLE (0 << 0) +# define R300_HIZ_ENABLE (1 << 0) +# define R300_HIZ_MIN (0 << 1) +# define R300_HIZ_MAX (1 << 1) +# define R300_FAST_FILL_DISABLE (0 << 2) +# define R300_FAST_FILL_ENABLE (1 << 2) +# define R300_RD_COMP_DISABLE (0 << 3) +# define R300_RD_COMP_ENABLE (1 << 3) +# define R300_WR_COMP_DISABLE (0 << 4) +# define R300_WR_COMP_ENABLE (1 << 4) +# define R300_ZB_CB_CLEAR_RMW (0 << 5) +# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) +# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) +# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) + +# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) +# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) +# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) +# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) + +# define R500_BMASK_ENABLE (0 << 10) +# define R500_BMASK_DISABLE (1 << 10) +# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) +# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) +# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) +# define R500_HIZ_FP_EXP_BITS_1 (1 << 12) +# define R500_HIZ_FP_EXP_BITS_2 (2 << 12) +# define R500_HIZ_FP_EXP_BITS_3 (3 << 12) +# define R500_HIZ_FP_EXP_BITS_4 (4 << 12) +# define R500_HIZ_FP_EXP_BITS_5 (5 << 12) +# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) +# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) +# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) +# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) +# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) +# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) +# define R500_PEQ_PACKING_DISABLE (0 << 18) +# define R500_PEQ_PACKING_ENABLE (1 << 18) +# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) +# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) + + +/* gap */ + +/* Z Buffer Address Offset. + * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. + */ +#define R300_ZB_DEPTHOFFSET 0x4f20 + +/* Z Buffer Pitch and Endian Control */ +#define R300_ZB_DEPTHPITCH 0x4f24 +# define R300_DEPTHPITCH_MASK 0x00003FFC +# define R300_DEPTHMACROTILE_DISABLE (0 << 16) +# define R300_DEPTHMACROTILE_ENABLE (1 << 16) +# define R300_DEPTHMICROTILE_LINEAR (0 << 17) +# define R300_DEPTHMICROTILE_TILED (1 << 17) +# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) +# define R300_DEPTHENDIAN_NO_SWAP (0 << 18) +# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) +# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) +# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) + +/* Z Buffer Clear Value */ +#define R300_ZB_DEPTHCLEARVALUE 0x4f28 + +/* Hierarchical Z Memory Offset */ +#define R300_ZB_HIZ_OFFSET 0x4f44 + +/* Hierarchical Z Write Index */ +#define R300_ZB_HIZ_WRINDEX 0x4f48 + +/* Hierarchical Z Data */ +#define R300_ZB_HIZ_DWORD 0x4f4c + +/* Hierarchical Z Read Index */ +#define R300_ZB_HIZ_RDINDEX 0x4f50 + +/* Hierarchical Z Pitch */ +#define R300_ZB_HIZ_PITCH 0x4f54 + +/* Z Buffer Z Pass Counter Data */ +#define R300_ZB_ZPASS_DATA 0x4f58 + +/* Z Buffer Z Pass Counter Address */ +#define R300_ZB_ZPASS_ADDR 0x4f5c + +/* Depth buffer X and Y coordinate offset */ +#define R300_ZB_DEPTHXY_OFFSET 0x4f60 +# define R300_DEPTHX_OFFSET_SHIFT 1 +# define R300_DEPTHX_OFFSET_MASK 0x000007FE +# define R300_DEPTHY_OFFSET_SHIFT 17 +# define R300_DEPTHY_OFFSET_MASK 0x07FE0000 + +/* Sets the fifo sizes */ +#define R500_ZB_FIFO_SIZE 0x4fd0 +# define R500_OP_FIFO_SIZE_FULL (0 << 0) +# define R500_OP_FIFO_SIZE_HALF (1 << 0) +# define R500_OP_FIFO_SIZE_QUATER (2 << 0) +# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) + +/* Stencil Reference Value and Mask for backfacing quads */ +/* R300_ZB_STENCILREFMASK handles front face */ +#define R500_ZB_STENCILREFMASK_BF 0x4fd4 +# define R500_STENCILREF_SHIFT 0 +# define R500_STENCILREF_MASK 0x000000ff +# define R500_STENCILMASK_SHIFT 8 +# define R500_STENCILMASK_MASK 0x0000ff00 +# define R500_STENCILWRITEMASK_SHIFT 16 +# define R500_STENCILWRITEMASK_MASK 0x00ff0000 + +/** + * \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION + * + * The PVS_DST_MATH_INST is used to identify whether the instruction is a Vector + * Engine instruction or a Math Engine instruction. + */ + +/*\{*/ + +enum { + /* R3XX */ + VECTOR_NO_OP = 0, + VE_DOT_PRODUCT = 1, + VE_MULTIPLY = 2, + VE_ADD = 3, + VE_MULTIPLY_ADD = 4, + VE_DISTANCE_VECTOR = 5, + VE_FRACTION = 6, + VE_MAXIMUM = 7, + VE_MINIMUM = 8, + VE_SET_GREATER_THAN_EQUAL = 9, + VE_SET_LESS_THAN = 10, + VE_MULTIPLYX2_ADD = 11, + VE_MULTIPLY_CLAMP = 12, + VE_FLT2FIX_DX = 13, + VE_FLT2FIX_DX_RND = 14, + /* R5XX */ + VE_PRED_SET_EQ_PUSH = 15, + VE_PRED_SET_GT_PUSH = 16, + VE_PRED_SET_GTE_PUSH = 17, + VE_PRED_SET_NEQ_PUSH = 18, + VE_COND_WRITE_EQ = 19, + VE_COND_WRITE_GT = 20, + VE_COND_WRITE_GTE = 21, + VE_COND_WRITE_NEQ = 22, + VE_COND_MUX_EQ = 23, + VE_COND_MUX_GT = 24, + VE_COND_MUX_GTE = 25, + VE_SET_GREATER_THAN = 26, + VE_SET_EQUAL = 27, + VE_SET_NOT_EQUAL = 28, +}; + +enum { + /* R3XX */ + MATH_NO_OP = 0, + ME_EXP_BASE2_DX = 1, + ME_LOG_BASE2_DX = 2, + ME_EXP_BASEE_FF = 3, + ME_LIGHT_COEFF_DX = 4, + ME_POWER_FUNC_FF = 5, + ME_RECIP_DX = 6, + ME_RECIP_FF = 7, + ME_RECIP_SQRT_DX = 8, + ME_RECIP_SQRT_FF = 9, + ME_MULTIPLY = 10, + ME_EXP_BASE2_FULL_DX = 11, + ME_LOG_BASE2_FULL_DX = 12, + ME_POWER_FUNC_FF_CLAMP_B = 13, + ME_POWER_FUNC_FF_CLAMP_B1 = 14, + ME_POWER_FUNC_FF_CLAMP_01 = 15, + ME_SIN = 16, + ME_COS = 17, + /* R5XX */ + ME_LOG_BASE2_IEEE = 18, + ME_RECIP_IEEE = 19, + ME_RECIP_SQRT_IEEE = 20, + ME_PRED_SET_EQ = 21, + ME_PRED_SET_GT = 22, + ME_PRED_SET_GTE = 23, + ME_PRED_SET_NEQ = 24, + ME_PRED_SET_CLR = 25, + ME_PRED_SET_INV = 26, + ME_PRED_SET_POP = 27, + ME_PRED_SET_RESTORE = 28, +}; + +enum { + /* R3XX */ + PVS_MACRO_OP_2CLK_MADD = 0, + PVS_MACRO_OP_2CLK_M2X_ADD = 1, +}; + +enum { + PVS_SRC_REG_TEMPORARY = 0, /* Intermediate Storage */ + PVS_SRC_REG_INPUT = 1, /* Input Vertex Storage */ + PVS_SRC_REG_CONSTANT = 2, /* Constant State Storage */ + PVS_SRC_REG_ALT_TEMPORARY = 3, /* Alternate Intermediate Storage */ +}; + +enum { + PVS_DST_REG_TEMPORARY = 0, /* Intermediate Storage */ + PVS_DST_REG_A0 = 1, /* Address Register Storage */ + PVS_DST_REG_OUT = 2, /* Output Memory. Used for all outputs */ + PVS_DST_REG_OUT_REPL_X = 3, /* Output Memory & Replicate X to all channels */ + PVS_DST_REG_ALT_TEMPORARY = 4, /* Alternate Intermediate Storage */ + PVS_DST_REG_INPUT = 5, /* Output Memory & Replicate X to all channels */ +}; + +enum { + PVS_SRC_SELECT_X = 0, /* Select X Component */ + PVS_SRC_SELECT_Y = 1, /* Select Y Component */ + PVS_SRC_SELECT_Z = 2, /* Select Z Component */ + PVS_SRC_SELECT_W = 3, /* Select W Component */ + PVS_SRC_SELECT_FORCE_0 = 4, /* Force Component to 0.0 */ + PVS_SRC_SELECT_FORCE_1 = 5, /* Force Component to 1.0 */ +}; + +/* PVS Opcode & Destination Operand Description */ + +enum { + PVS_DST_OPCODE_MASK = 0x3f, + PVS_DST_OPCODE_SHIFT = 0, + PVS_DST_MATH_INST_MASK = 0x1, + PVS_DST_MATH_INST_SHIFT = 6, + PVS_DST_MACRO_INST_MASK = 0x1, + PVS_DST_MACRO_INST_SHIFT = 7, + PVS_DST_REG_TYPE_MASK = 0xf, + PVS_DST_REG_TYPE_SHIFT = 8, + PVS_DST_ADDR_MODE_1_MASK = 0x1, + PVS_DST_ADDR_MODE_1_SHIFT = 12, + PVS_DST_OFFSET_MASK = 0x7f, + PVS_DST_OFFSET_SHIFT = 13, + PVS_DST_WE_X_MASK = 0x1, + PVS_DST_WE_X_SHIFT = 20, + PVS_DST_WE_Y_MASK = 0x1, + PVS_DST_WE_Y_SHIFT = 21, + PVS_DST_WE_Z_MASK = 0x1, + PVS_DST_WE_Z_SHIFT = 22, + PVS_DST_WE_W_MASK = 0x1, + PVS_DST_WE_W_SHIFT = 23, + PVS_DST_VE_SAT_MASK = 0x1, + PVS_DST_VE_SAT_SHIFT = 24, + PVS_DST_ME_SAT_MASK = 0x1, + PVS_DST_ME_SAT_SHIFT = 25, + PVS_DST_PRED_ENABLE_MASK = 0x1, + PVS_DST_PRED_ENABLE_SHIFT = 26, + PVS_DST_PRED_SENSE_MASK = 0x1, + PVS_DST_PRED_SENSE_SHIFT = 27, + PVS_DST_DUAL_MATH_OP_MASK = 0x3, + PVS_DST_DUAL_MATH_OP_SHIFT = 27, + PVS_DST_ADDR_SEL_MASK = 0x3, + PVS_DST_ADDR_SEL_SHIFT = 29, + PVS_DST_ADDR_MODE_0_MASK = 0x1, + PVS_DST_ADDR_MODE_0_SHIFT = 31, +}; + +/* PVS Source Operand Description */ + +enum { + PVS_SRC_REG_TYPE_MASK = 0x3, + PVS_SRC_REG_TYPE_SHIFT = 0, + SPARE_0_MASK = 0x1, + SPARE_0_SHIFT = 2, + PVS_SRC_ABS_XYZW_MASK = 0x1, + PVS_SRC_ABS_XYZW_SHIFT = 3, + PVS_SRC_ADDR_MODE_0_MASK = 0x1, + PVS_SRC_ADDR_MODE_0_SHIFT = 4, + PVS_SRC_OFFSET_MASK = 0xff, + PVS_SRC_OFFSET_SHIFT = 5, + PVS_SRC_SWIZZLE_X_MASK = 0x7, + PVS_SRC_SWIZZLE_X_SHIFT = 13, + PVS_SRC_SWIZZLE_Y_MASK = 0x7, + PVS_SRC_SWIZZLE_Y_SHIFT = 16, + PVS_SRC_SWIZZLE_Z_MASK = 0x7, + PVS_SRC_SWIZZLE_Z_SHIFT = 19, + PVS_SRC_SWIZZLE_W_MASK = 0x7, + PVS_SRC_SWIZZLE_W_SHIFT = 22, + PVS_SRC_MODIFIER_X_MASK = 0x1, + PVS_SRC_MODIFIER_X_SHIFT = 25, + PVS_SRC_MODIFIER_Y_MASK = 0x1, + PVS_SRC_MODIFIER_Y_SHIFT = 26, + PVS_SRC_MODIFIER_Z_MASK = 0x1, + PVS_SRC_MODIFIER_Z_SHIFT = 27, + PVS_SRC_MODIFIER_W_MASK = 0x1, + PVS_SRC_MODIFIER_W_SHIFT = 28, + PVS_SRC_ADDR_SEL_MASK = 0x3, + PVS_SRC_ADDR_SEL_SHIFT = 29, + PVS_SRC_ADDR_MODE_1_MASK = 0x0, + PVS_SRC_ADDR_MODE_1_SHIFT = 32, +}; + +/*\}*/ + +/* BEGIN: Packet 3 commands */ + +/* A primitive emission dword. */ +#define R300_PRIM_TYPE_NONE (0 << 0) +#define R300_PRIM_TYPE_POINT (1 << 0) +#define R300_PRIM_TYPE_LINE (2 << 0) +#define R300_PRIM_TYPE_LINE_STRIP (3 << 0) +#define R300_PRIM_TYPE_TRI_LIST (4 << 0) +#define R300_PRIM_TYPE_TRI_FAN (5 << 0) +#define R300_PRIM_TYPE_TRI_STRIP (6 << 0) +#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) +#define R300_PRIM_TYPE_RECT_LIST (8 << 0) +#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) +#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) + /* GUESS (based on r200) */ +#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) +#define R300_PRIM_TYPE_LINE_LOOP (12 << 0) +#define R300_PRIM_TYPE_QUADS (13 << 0) +#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) +#define R300_PRIM_TYPE_POLYGON (15 << 0) +#define R300_PRIM_TYPE_MASK 0xF +#define R300_PRIM_WALK_IND (1 << 4) +#define R300_PRIM_WALK_LIST (2 << 4) +#define R300_PRIM_WALK_RING (3 << 4) +#define R300_PRIM_WALK_MASK (3 << 4) + /* GUESS (based on r200) */ +#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) +#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) +#define R300_PRIM_NUM_VERTICES_SHIFT 16 +#define R300_PRIM_NUM_VERTICES_MASK 0xffff + + + +/* + * The R500 unified shader (US) registers come in banks of 512 each, one + * for each instruction slot in the shader. You can't touch them directly. + * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive + * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the + * instruction is fully specified. + */ +#define R500_US_ALU_ALPHA_INST_0 0xa800 +# define R500_ALPHA_OP_MAD 0 +# define R500_ALPHA_OP_DP 1 +# define R500_ALPHA_OP_MIN 2 +# define R500_ALPHA_OP_MAX 3 +/* #define R500_ALPHA_OP_RESERVED 4 */ +# define R500_ALPHA_OP_CND 5 +# define R500_ALPHA_OP_CMP 6 +# define R500_ALPHA_OP_FRC 7 +# define R500_ALPHA_OP_EX2 8 +# define R500_ALPHA_OP_LN2 9 +# define R500_ALPHA_OP_RCP 10 +# define R500_ALPHA_OP_RSQ 11 +# define R500_ALPHA_OP_SIN 12 +# define R500_ALPHA_OP_COS 13 +# define R500_ALPHA_OP_MDH 14 +# define R500_ALPHA_OP_MDV 15 +# define R500_ALPHA_ADDRD(x) (x << 4) +# define R500_ALPHA_ADDRD_REL (1 << 11) +# define R500_ALPHA_SEL_A_SHIFT 12 +# define R500_ALPHA_SEL_A_SRC0 (0 << 12) +# define R500_ALPHA_SEL_A_SRC1 (1 << 12) +# define R500_ALPHA_SEL_A_SRC2 (2 << 12) +# define R500_ALPHA_SEL_A_SRCP (3 << 12) +# define R500_ALPHA_SWIZ_A_R (0 << 14) +# define R500_ALPHA_SWIZ_A_G (1 << 14) +# define R500_ALPHA_SWIZ_A_B (2 << 14) +# define R500_ALPHA_SWIZ_A_A (3 << 14) +# define R500_ALPHA_SWIZ_A_0 (4 << 14) +# define R500_ALPHA_SWIZ_A_HALF (5 << 14) +# define R500_ALPHA_SWIZ_A_1 (6 << 14) +/* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */ +# define R500_ALPHA_MOD_A_NOP (0 << 17) +# define R500_ALPHA_MOD_A_NEG (1 << 17) +# define R500_ALPHA_MOD_A_ABS (2 << 17) +# define R500_ALPHA_MOD_A_NAB (3 << 17) +# define R500_ALPHA_SEL_B_SHIFT 19 +# define R500_ALPHA_SEL_B_SRC0 (0 << 19) +# define R500_ALPHA_SEL_B_SRC1 (1 << 19) +# define R500_ALPHA_SEL_B_SRC2 (2 << 19) +# define R500_ALPHA_SEL_B_SRCP (3 << 19) +# define R500_ALPHA_SWIZ_B_R (0 << 21) +# define R500_ALPHA_SWIZ_B_G (1 << 21) +# define R500_ALPHA_SWIZ_B_B (2 << 21) +# define R500_ALPHA_SWIZ_B_A (3 << 21) +# define R500_ALPHA_SWIZ_B_0 (4 << 21) +# define R500_ALPHA_SWIZ_B_HALF (5 << 21) +# define R500_ALPHA_SWIZ_B_1 (6 << 21) +/* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */ +# define R500_ALPHA_MOD_B_NOP (0 << 24) +# define R500_ALPHA_MOD_B_NEG (1 << 24) +# define R500_ALPHA_MOD_B_ABS (2 << 24) +# define R500_ALPHA_MOD_B_NAB (3 << 24) +# define R500_ALPHA_OMOD_IDENTITY (0 << 26) +# define R500_ALPHA_OMOD_MUL_2 (1 << 26) +# define R500_ALPHA_OMOD_MUL_4 (2 << 26) +# define R500_ALPHA_OMOD_MUL_8 (3 << 26) +# define R500_ALPHA_OMOD_DIV_2 (4 << 26) +# define R500_ALPHA_OMOD_DIV_4 (5 << 26) +# define R500_ALPHA_OMOD_DIV_8 (6 << 26) +# define R500_ALPHA_OMOD_DISABLE (7 << 26) +# define R500_ALPHA_TARGET(x) (x << 29) +# define R500_ALPHA_W_OMASK (1 << 31) +#define R500_US_ALU_ALPHA_ADDR_0 0x9800 +# define R500_ALPHA_ADDR0(x) (x << 0) +# define R500_ALPHA_ADDR0_CONST (1 << 8) +# define R500_ALPHA_ADDR0_REL (1 << 9) +# define R500_ALPHA_ADDR1(x) (x << 10) +# define R500_ALPHA_ADDR1_CONST (1 << 18) +# define R500_ALPHA_ADDR1_REL (1 << 19) +# define R500_ALPHA_ADDR2(x) (x << 20) +# define R500_ALPHA_ADDR2_CONST (1 << 28) +# define R500_ALPHA_ADDR2_REL (1 << 29) +# define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) +# define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) +# define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) +# define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30) +#define R500_US_ALU_RGBA_INST_0 0xb000 +# define R500_ALU_RGBA_OP_MAD (0 << 0) +# define R500_ALU_RGBA_OP_DP3 (1 << 0) +# define R500_ALU_RGBA_OP_DP4 (2 << 0) +# define R500_ALU_RGBA_OP_D2A (3 << 0) +# define R500_ALU_RGBA_OP_MIN (4 << 0) +# define R500_ALU_RGBA_OP_MAX (5 << 0) +/* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */ +# define R500_ALU_RGBA_OP_CND (7 << 0) +# define R500_ALU_RGBA_OP_CMP (8 << 0) +# define R500_ALU_RGBA_OP_FRC (9 << 0) +# define R500_ALU_RGBA_OP_SOP (10 << 0) +# define R500_ALU_RGBA_OP_MDH (11 << 0) +# define R500_ALU_RGBA_OP_MDV (12 << 0) +# define R500_ALU_RGBA_ADDRD(x) (x << 4) +# define R500_ALU_RGBA_ADDRD_REL (1 << 11) +# define R500_ALU_RGBA_SEL_C_SHIFT 12 +# define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) +# define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) +# define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12) +# define R500_ALU_RGBA_SEL_C_SRCP (3 << 12) +# define R500_ALU_RGBA_R_SWIZ_R (0 << 14) +# define R500_ALU_RGBA_R_SWIZ_G (1 << 14) +# define R500_ALU_RGBA_R_SWIZ_B (2 << 14) +# define R500_ALU_RGBA_R_SWIZ_A (3 << 14) +# define R500_ALU_RGBA_R_SWIZ_0 (4 << 14) +# define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14) +# define R500_ALU_RGBA_R_SWIZ_1 (6 << 14) +/* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */ +# define R500_ALU_RGBA_G_SWIZ_R (0 << 17) +# define R500_ALU_RGBA_G_SWIZ_G (1 << 17) +# define R500_ALU_RGBA_G_SWIZ_B (2 << 17) +# define R500_ALU_RGBA_G_SWIZ_A (3 << 17) +# define R500_ALU_RGBA_G_SWIZ_0 (4 << 17) +# define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17) +# define R500_ALU_RGBA_G_SWIZ_1 (6 << 17) +/* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */ +# define R500_ALU_RGBA_B_SWIZ_R (0 << 20) +# define R500_ALU_RGBA_B_SWIZ_G (1 << 20) +# define R500_ALU_RGBA_B_SWIZ_B (2 << 20) +# define R500_ALU_RGBA_B_SWIZ_A (3 << 20) +# define R500_ALU_RGBA_B_SWIZ_0 (4 << 20) +# define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20) +# define R500_ALU_RGBA_B_SWIZ_1 (6 << 20) +/* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */ +# define R500_ALU_RGBA_MOD_C_NOP (0 << 23) +# define R500_ALU_RGBA_MOD_C_NEG (1 << 23) +# define R500_ALU_RGBA_MOD_C_ABS (2 << 23) +# define R500_ALU_RGBA_MOD_C_NAB (3 << 23) +# define R500_ALU_RGBA_ALPHA_SEL_C_SHIFT 25 +# define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25) +# define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25) +# define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25) +# define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25) +# define R500_ALU_RGBA_A_SWIZ_R (0 << 27) +# define R500_ALU_RGBA_A_SWIZ_G (1 << 27) +# define R500_ALU_RGBA_A_SWIZ_B (2 << 27) +# define R500_ALU_RGBA_A_SWIZ_A (3 << 27) +# define R500_ALU_RGBA_A_SWIZ_0 (4 << 27) +# define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27) +# define R500_ALU_RGBA_A_SWIZ_1 (6 << 27) +/* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */ +# define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30) +# define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30) +# define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30) +# define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30) +#define R500_US_ALU_RGB_INST_0 0xa000 +# define R500_ALU_RGB_SEL_A_SHIFT 0 +# define R500_ALU_RGB_SEL_A_SRC0 (0 << 0) +# define R500_ALU_RGB_SEL_A_SRC1 (1 << 0) +# define R500_ALU_RGB_SEL_A_SRC2 (2 << 0) +# define R500_ALU_RGB_SEL_A_SRCP (3 << 0) +# define R500_ALU_RGB_R_SWIZ_A_R (0 << 2) +# define R500_ALU_RGB_R_SWIZ_A_G (1 << 2) +# define R500_ALU_RGB_R_SWIZ_A_B (2 << 2) +# define R500_ALU_RGB_R_SWIZ_A_A (3 << 2) +# define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2) +# define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2) +# define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2) +/* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */ +# define R500_ALU_RGB_G_SWIZ_A_R (0 << 5) +# define R500_ALU_RGB_G_SWIZ_A_G (1 << 5) +# define R500_ALU_RGB_G_SWIZ_A_B (2 << 5) +# define R500_ALU_RGB_G_SWIZ_A_A (3 << 5) +# define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5) +# define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5) +# define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5) +/* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */ +# define R500_ALU_RGB_B_SWIZ_A_R (0 << 8) +# define R500_ALU_RGB_B_SWIZ_A_G (1 << 8) +# define R500_ALU_RGB_B_SWIZ_A_B (2 << 8) +# define R500_ALU_RGB_B_SWIZ_A_A (3 << 8) +# define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8) +# define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8) +# define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8) +/* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */ +# define R500_ALU_RGB_MOD_A_NOP (0 << 11) +# define R500_ALU_RGB_MOD_A_NEG (1 << 11) +# define R500_ALU_RGB_MOD_A_ABS (2 << 11) +# define R500_ALU_RGB_MOD_A_NAB (3 << 11) +# define R500_ALU_RGB_SEL_B_SHIFT 13 +# define R500_ALU_RGB_SEL_B_SRC0 (0 << 13) +# define R500_ALU_RGB_SEL_B_SRC1 (1 << 13) +# define R500_ALU_RGB_SEL_B_SRC2 (2 << 13) +# define R500_ALU_RGB_SEL_B_SRCP (3 << 13) +# define R500_ALU_RGB_R_SWIZ_B_R (0 << 15) +# define R500_ALU_RGB_R_SWIZ_B_G (1 << 15) +# define R500_ALU_RGB_R_SWIZ_B_B (2 << 15) +# define R500_ALU_RGB_R_SWIZ_B_A (3 << 15) +# define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15) +# define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15) +# define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15) +/* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */ +# define R500_ALU_RGB_G_SWIZ_B_R (0 << 18) +# define R500_ALU_RGB_G_SWIZ_B_G (1 << 18) +# define R500_ALU_RGB_G_SWIZ_B_B (2 << 18) +# define R500_ALU_RGB_G_SWIZ_B_A (3 << 18) +# define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18) +# define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18) +# define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18) +/* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */ +# define R500_ALU_RGB_B_SWIZ_B_R (0 << 21) +# define R500_ALU_RGB_B_SWIZ_B_G (1 << 21) +# define R500_ALU_RGB_B_SWIZ_B_B (2 << 21) +# define R500_ALU_RGB_B_SWIZ_B_A (3 << 21) +# define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21) +# define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21) +# define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21) +/* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */ +# define R500_ALU_RGB_MOD_B_NOP (0 << 24) +# define R500_ALU_RGB_MOD_B_NEG (1 << 24) +# define R500_ALU_RGB_MOD_B_ABS (2 << 24) +# define R500_ALU_RGB_MOD_B_NAB (3 << 24) +# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26) +# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26) +# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26) +# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26) +# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26) +# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26) +# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26) +# define R500_ALU_RGB_OMOD_DISABLE (7 << 26) +# define R500_ALU_RGB_TARGET(x) (x << 29) +# define R500_ALU_RGB_WMASK (1 << 31) +#define R500_US_ALU_RGB_ADDR_0 0x9000 +# define R500_RGB_ADDR0(x) (x << 0) +# define R500_RGB_ADDR0_CONST (1 << 8) +# define R500_RGB_ADDR0_REL (1 << 9) +# define R500_RGB_ADDR1(x) (x << 10) +# define R500_RGB_ADDR1_CONST (1 << 18) +# define R500_RGB_ADDR1_REL (1 << 19) +# define R500_RGB_ADDR2(x) (x << 20) +# define R500_RGB_ADDR2_CONST (1 << 28) +# define R500_RGB_ADDR2_REL (1 << 29) +# define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) +# define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) +# define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) +# define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) +#define R500_US_CMN_INST_0 0xb800 +# define R500_INST_TYPE_MASK (3 << 0) +# define R500_INST_TYPE_ALU (0 << 0) +# define R500_INST_TYPE_OUT (1 << 0) +# define R500_INST_TYPE_FC (2 << 0) +# define R500_INST_TYPE_TEX (3 << 0) +# define R500_INST_TEX_SEM_WAIT (1 << 2) +# define R500_INST_RGB_PRED_SEL_NONE (0 << 3) +# define R500_INST_RGB_PRED_SEL_RGBA (1 << 3) +# define R500_INST_RGB_PRED_SEL_RRRR (2 << 3) +# define R500_INST_RGB_PRED_SEL_GGGG (3 << 3) +# define R500_INST_RGB_PRED_SEL_BBBB (4 << 3) +# define R500_INST_RGB_PRED_SEL_AAAA (5 << 3) +# define R500_INST_RGB_PRED_INV (1 << 6) +# define R500_INST_WRITE_INACTIVE (1 << 7) +# define R500_INST_LAST (1 << 8) +# define R500_INST_NOP (1 << 9) +# define R500_INST_ALU_WAIT (1 << 10) +# define R500_INST_RGB_WMASK_R (1 << 11) +# define R500_INST_RGB_WMASK_G (1 << 12) +# define R500_INST_RGB_WMASK_B (1 << 13) +# define R500_INST_ALPHA_WMASK (1 << 14) +# define R500_INST_RGB_OMASK_R (1 << 15) +# define R500_INST_RGB_OMASK_G (1 << 16) +# define R500_INST_RGB_OMASK_B (1 << 17) +# define R500_INST_ALPHA_OMASK (1 << 18) +# define R500_INST_RGB_CLAMP (1 << 19) +# define R500_INST_ALPHA_CLAMP (1 << 20) +# define R500_INST_ALU_RESULT_SEL (1 << 21) +# define R500_INST_ALPHA_PRED_INV (1 << 22) +# define R500_INST_ALU_RESULT_OP_EQ (0 << 23) +# define R500_INST_ALU_RESULT_OP_LT (1 << 23) +# define R500_INST_ALU_RESULT_OP_GE (2 << 23) +# define R500_INST_ALU_RESULT_OP_NE (3 << 23) +# define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25) +# define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25) +# define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25) +# define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25) +# define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25) +# define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25) +/* XXX next four are kind of guessed */ +# define R500_INST_STAT_WE_R (1 << 28) +# define R500_INST_STAT_WE_G (1 << 29) +# define R500_INST_STAT_WE_B (1 << 30) +# define R500_INST_STAT_WE_A (1 << 31) + +/* note that these are 8 bit lengths, despite the offsets, at least for R500 */ +#define R500_US_CODE_ADDR 0x4630 +# define R500_US_CODE_START_ADDR(x) (x << 0) +# define R500_US_CODE_END_ADDR(x) (x << 16) +#define R500_US_CODE_OFFSET 0x4638 +# define R500_US_CODE_OFFSET_ADDR(x) (x << 0) +#define R500_US_CODE_RANGE 0x4634 +# define R500_US_CODE_RANGE_ADDR(x) (x << 0) +# define R500_US_CODE_RANGE_SIZE(x) (x << 16) +#define R500_US_CONFIG 0x4600 +# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) +#define R500_US_FC_ADDR_0 0xa000 +# define R500_FC_BOOL_ADDR(x) (x << 0) +# define R500_FC_INT_ADDR(x) (x << 8) +# define R500_FC_JUMP_ADDR(x) (x << 16) +# define R500_FC_JUMP_GLOBAL (1 << 31) +#define R500_US_FC_BOOL_CONST 0x4620 +# define R500_FC_KBOOL(x) (x) +#define R500_US_FC_CTRL 0x4624 +# define R500_FC_TEST_EN (1 << 30) +# define R500_FC_FULL_FC_EN (1 << 31) +#define R500_US_FC_INST_0 0x9800 +# define R500_FC_OP_JUMP (0 << 0) +# define R500_FC_OP_LOOP (1 << 0) +# define R500_FC_OP_ENDLOOP (2 << 0) +# define R500_FC_OP_REP (3 << 0) +# define R500_FC_OP_ENDREP (4 << 0) +# define R500_FC_OP_BREAKLOOP (5 << 0) +# define R500_FC_OP_BREAKREP (6 << 0) +# define R500_FC_OP_CONTINUE (7 << 0) +# define R500_FC_B_ELSE (1 << 4) +# define R500_FC_JUMP_ANY (1 << 5) +# define R500_FC_A_OP_NONE (0 << 6) +# define R500_FC_A_OP_POP (1 << 6) +# define R500_FC_A_OP_PUSH (2 << 6) +# define R500_FC_JUMP_FUNC(x) (x << 8) +# define R500_FC_B_POP_CNT(x) (x << 16) +# define R500_FC_B_OP0_NONE (0 << 24) +# define R500_FC_B_OP0_DECR (1 << 24) +# define R500_FC_B_OP0_INCR (2 << 24) +# define R500_FC_B_OP1_DECR (0 << 26) +# define R500_FC_B_OP1_NONE (1 << 26) +# define R500_FC_B_OP1_INCR (2 << 26) +# define R500_FC_IGNORE_UNCOVERED (1 << 28) +#define R500_US_FC_INT_CONST_0 0x4c00 +# define R500_FC_INT_CONST_KR(x) (x << 0) +# define R500_FC_INT_CONST_KG(x) (x << 8) +# define R500_FC_INT_CONST_KB(x) (x << 16) +/* _0 through _15 */ +#define R500_US_FORMAT0_0 0x4640 +# define R500_FORMAT_TXWIDTH(x) (x << 0) +# define R500_FORMAT_TXHEIGHT(x) (x << 11) +# define R500_FORMAT_TXDEPTH(x) (x << 22) +/* _0 through _3 */ +#define R500_US_OUT_FMT_0 0x46a4 +# define R500_OUT_FMT_C4_8 (0 << 0) +# define R500_OUT_FMT_C4_10 (1 << 0) +# define R500_OUT_FMT_C4_10_GAMMA (2 << 0) +# define R500_OUT_FMT_C_16 (3 << 0) +# define R500_OUT_FMT_C2_16 (4 << 0) +# define R500_OUT_FMT_C4_16 (5 << 0) +# define R500_OUT_FMT_C_16_MPEG (6 << 0) +# define R500_OUT_FMT_C2_16_MPEG (7 << 0) +# define R500_OUT_FMT_C2_4 (8 << 0) +# define R500_OUT_FMT_C_3_3_2 (9 << 0) +# define R500_OUT_FMT_C_6_5_6 (10 << 0) +# define R500_OUT_FMT_C_11_11_10 (11 << 0) +# define R500_OUT_FMT_C_10_11_11 (12 << 0) +# define R500_OUT_FMT_C_2_10_10_10 (13 << 0) +/* #define R500_OUT_FMT_RESERVED (14 << 0) */ +# define R500_OUT_FMT_UNUSED (15 << 0) +# define R500_OUT_FMT_C_16_FP (16 << 0) +# define R500_OUT_FMT_C2_16_FP (17 << 0) +# define R500_OUT_FMT_C4_16_FP (18 << 0) +# define R500_OUT_FMT_C_32_FP (19 << 0) +# define R500_OUT_FMT_C2_32_FP (20 << 0) +# define R500_OUT_FMT_C4_32_FP (21 << 0) +# define R500_C0_SEL_A (0 << 8) +# define R500_C0_SEL_R (1 << 8) +# define R500_C0_SEL_G (2 << 8) +# define R500_C0_SEL_B (3 << 8) +# define R500_C1_SEL_A (0 << 10) +# define R500_C1_SEL_R (1 << 10) +# define R500_C1_SEL_G (2 << 10) +# define R500_C1_SEL_B (3 << 10) +# define R500_C2_SEL_A (0 << 12) +# define R500_C2_SEL_R (1 << 12) +# define R500_C2_SEL_G (2 << 12) +# define R500_C2_SEL_B (3 << 12) +# define R500_C3_SEL_A (0 << 14) +# define R500_C3_SEL_R (1 << 14) +# define R500_C3_SEL_G (2 << 14) +# define R500_C3_SEL_B (3 << 14) +# define R500_OUT_SIGN(x) (x << 16) +# define R500_ROUND_ADJ (1 << 20) +#define R500_US_PIXSIZE 0x4604 +# define R500_PIX_SIZE(x) (x) +#define R500_US_TEX_ADDR_0 0x9800 +# define R500_TEX_SRC_ADDR(x) (x << 0) +# define R500_TEX_SRC_ADDR_REL (1 << 7) +# define R500_TEX_SRC_S_SWIZ_R (0 << 8) +# define R500_TEX_SRC_S_SWIZ_G (1 << 8) +# define R500_TEX_SRC_S_SWIZ_B (2 << 8) +# define R500_TEX_SRC_S_SWIZ_A (3 << 8) +# define R500_TEX_SRC_T_SWIZ_R (0 << 10) +# define R500_TEX_SRC_T_SWIZ_G (1 << 10) +# define R500_TEX_SRC_T_SWIZ_B (2 << 10) +# define R500_TEX_SRC_T_SWIZ_A (3 << 10) +# define R500_TEX_SRC_R_SWIZ_R (0 << 12) +# define R500_TEX_SRC_R_SWIZ_G (1 << 12) +# define R500_TEX_SRC_R_SWIZ_B (2 << 12) +# define R500_TEX_SRC_R_SWIZ_A (3 << 12) +# define R500_TEX_SRC_Q_SWIZ_R (0 << 14) +# define R500_TEX_SRC_Q_SWIZ_G (1 << 14) +# define R500_TEX_SRC_Q_SWIZ_B (2 << 14) +# define R500_TEX_SRC_Q_SWIZ_A (3 << 14) +# define R500_TEX_DST_ADDR(x) (x << 16) +# define R500_TEX_DST_ADDR_REL (1 << 23) +# define R500_TEX_DST_R_SWIZ_R (0 << 24) +# define R500_TEX_DST_R_SWIZ_G (1 << 24) +# define R500_TEX_DST_R_SWIZ_B (2 << 24) +# define R500_TEX_DST_R_SWIZ_A (3 << 24) +# define R500_TEX_DST_G_SWIZ_R (0 << 26) +# define R500_TEX_DST_G_SWIZ_G (1 << 26) +# define R500_TEX_DST_G_SWIZ_B (2 << 26) +# define R500_TEX_DST_G_SWIZ_A (3 << 26) +# define R500_TEX_DST_B_SWIZ_R (0 << 28) +# define R500_TEX_DST_B_SWIZ_G (1 << 28) +# define R500_TEX_DST_B_SWIZ_B (2 << 28) +# define R500_TEX_DST_B_SWIZ_A (3 << 28) +# define R500_TEX_DST_A_SWIZ_R (0 << 30) +# define R500_TEX_DST_A_SWIZ_G (1 << 30) +# define R500_TEX_DST_A_SWIZ_B (2 << 30) +# define R500_TEX_DST_A_SWIZ_A (3 << 30) +#define R500_US_TEX_ADDR_DXDY_0 0xa000 +# define R500_DX_ADDR(x) (x << 0) +# define R500_DX_ADDR_REL (1 << 7) +# define R500_DX_S_SWIZ_R (0 << 8) +# define R500_DX_S_SWIZ_G (1 << 8) +# define R500_DX_S_SWIZ_B (2 << 8) +# define R500_DX_S_SWIZ_A (3 << 8) +# define R500_DX_T_SWIZ_R (0 << 10) +# define R500_DX_T_SWIZ_G (1 << 10) +# define R500_DX_T_SWIZ_B (2 << 10) +# define R500_DX_T_SWIZ_A (3 << 10) +# define R500_DX_R_SWIZ_R (0 << 12) +# define R500_DX_R_SWIZ_G (1 << 12) +# define R500_DX_R_SWIZ_B (2 << 12) +# define R500_DX_R_SWIZ_A (3 << 12) +# define R500_DX_Q_SWIZ_R (0 << 14) +# define R500_DX_Q_SWIZ_G (1 << 14) +# define R500_DX_Q_SWIZ_B (2 << 14) +# define R500_DX_Q_SWIZ_A (3 << 14) +# define R500_DY_ADDR(x) (x << 16) +# define R500_DY_ADDR_REL (1 << 17) +# define R500_DY_S_SWIZ_R (0 << 24) +# define R500_DY_S_SWIZ_G (1 << 24) +# define R500_DY_S_SWIZ_B (2 << 24) +# define R500_DY_S_SWIZ_A (3 << 24) +# define R500_DY_T_SWIZ_R (0 << 26) +# define R500_DY_T_SWIZ_G (1 << 26) +# define R500_DY_T_SWIZ_B (2 << 26) +# define R500_DY_T_SWIZ_A (3 << 26) +# define R500_DY_R_SWIZ_R (0 << 28) +# define R500_DY_R_SWIZ_G (1 << 28) +# define R500_DY_R_SWIZ_B (2 << 28) +# define R500_DY_R_SWIZ_A (3 << 28) +# define R500_DY_Q_SWIZ_R (0 << 30) +# define R500_DY_Q_SWIZ_G (1 << 30) +# define R500_DY_Q_SWIZ_B (2 << 30) +# define R500_DY_Q_SWIZ_A (3 << 30) +#define R500_US_TEX_INST_0 0x9000 +# define R500_TEX_ID(x) (x << 16) +# define R500_TEX_INST_NOP (0 << 22) +# define R500_TEX_INST_LD (1 << 22) +# define R500_TEX_INST_TEXKILL (2 << 22) +# define R500_TEX_INST_PROJ (3 << 22) +# define R500_TEX_INST_LODBIAS (4 << 22) +# define R500_TEX_INST_LOD (5 << 22) +# define R500_TEX_INST_DXDY (6 << 22) +# define R500_TEX_SEM_ACQUIRE (1 << 25) +# define R500_TEX_IGNORE_UNCOVERED (1 << 26) +# define R500_TEX_UNSCALED (1 << 27) +#define R300_US_W_FMT 0x46b4 +# define R300_W_FMT_W0 (0 << 0) +# define R300_W_FMT_W24 (1 << 0) +# define R300_W_FMT_W24FP (2 << 0) +# define R300_W_SRC_US (0 << 2) +# define R300_W_SRC_RAS (1 << 2) + + +/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. + * Two parameter dwords: + * 0. VAP_VTX_FMT: The first parameter is not written to hardware + * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. + */ +#define R300_PACKET3_3D_DRAW_VBUF 0x00002800 + +/* Draw a primitive from immediate vertices in this packet + * Up to 16382 dwords: + * 0. VAP_VTX_FMT: The first parameter is not written to hardware + * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. + * 2 to end: Up to 16380 dwords of vertex data. + */ +#define R300_PACKET3_3D_DRAW_IMMD 0x00002900 + +/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR and + * immediate vertices in this packet + * Up to 16382 dwords: + * 0. VAP_VTX_FMT: The first parameter is not written to hardware + * 1. VAP_VF_CTL: The second parameter is a standard primitive emission dword. + * 2 to end: Up to 16380 dwords of vertex data. + */ +#define R300_PACKET3_3D_DRAW_INDX 0x00002A00 + + +/* Specify the full set of vertex arrays as (address, stride). + * The first parameter is the number of vertex arrays specified. + * The rest of the command is a variable length list of blocks, where + * each block is three dwords long and specifies two arrays. + * The first dword of a block is split into two words, the lower significant + * word refers to the first array, the more significant word to the second + * array in the block. + * The low byte of each word contains the size of an array entry in dwords, + * the high byte contains the stride of the array. + * The second dword of a block contains the pointer to the first array, + * the third dword of a block contains the pointer to the second array. + * Note that if the total number of arrays is odd, the third dword of + * the last block is omitted. + */ +#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 + +#define R300_PACKET3_INDX_BUFFER 0x00003300 +# define R300_EB_UNK1_SHIFT 24 +# define R300_EB_UNK1 (0x80<<24) +# define R300_EB_UNK2 0x0810 + +/* Same as R300_PACKET3_3D_DRAW_VBUF but without VAP_VTX_FMT */ +#define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 +/* Same as R300_PACKET3_3D_DRAW_IMMD but without VAP_VTX_FMT */ +#define R300_PACKET3_3D_DRAW_IMMD_2 0x00003500 +/* Same as R300_PACKET3_3D_DRAW_INDX but without VAP_VTX_FMT */ +#define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 + +/* Clears a portion of hierachical Z RAM + * 3 dword parameters + * 0. START + * 1. COUNT: 13:0 (max is 0x3FFF) + * 2. CLEAR_VALUE: Value to write into HIZ RAM. + */ +#define R300_PACKET3_3D_CLEAR_HIZ 0x00003700 + +/* Draws a set of primitives using vertex buffers pointed by the state data. + * At least 2 Parameters: + * 0. VAP_VF_CNTL: The first parameter is a standard primitive emission dword. + * 2 to end: Data or indices (see other 3D_DRAW_* packets for details) + */ +#define R300_PACKET3_3D_DRAW_128 0x00003900 + +/* END: Packet 3 commands */ + + +/* Color formats for 2d packets + */ +#define R300_CP_COLOR_FORMAT_CI8 2 +#define R300_CP_COLOR_FORMAT_ARGB1555 3 +#define R300_CP_COLOR_FORMAT_RGB565 4 +#define R300_CP_COLOR_FORMAT_ARGB8888 6 +#define R300_CP_COLOR_FORMAT_RGB332 7 +#define R300_CP_COLOR_FORMAT_RGB8 9 +#define R300_CP_COLOR_FORMAT_ARGB4444 15 + +/* + * CP type-3 packets + */ +#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 + +#endif /* _R300_REG_H */ + +/* *INDENT-ON* */ + +/* vim: set foldenable foldmarker=\\{,\\} foldmethod=marker : */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index a853507fea..93441f624e 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -21,6 +21,127 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "r300_context.h" +#include "r300_state.h" + +static uint32_t translate_blend_function(int blend_func) { + switch (blend_func) { + case PIPE_BLEND_ADD: + return R300_COMB_FCN_ADD_CLAMP; + case PIPE_BLEND_SUBTRACT: + return R300_COMB_FCN_SUB_CLAMP; + case PIPE_BLEND_REVERSE_SUBTRACT: + return R300_COMB_FCN_RSUB_CLAMP; + case PIPE_BLEND_MIN: + return R300_COMB_FCN_MIN; + case PIPE_BLEND_MAX: + return R300_COMB_FCN_MAX; + default: + /* XXX should be unreachable, handle this */ + break; + } + return 0; +} + +/* XXX we can also offer the D3D versions of some of these... */ +static uint32_t translate_blend_factor(int blend_fact) { + switch (blend_fact) { + case PIPE_BLENDFACTOR_ONE: + return R300_BLEND_GL_ONE; + case PIPE_BLENDFACTOR_SRC_COLOR: + return R300_BLEND_GL_SRC_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA: + return R300_BLEND_GL_SRC_ALPHA; + case PIPE_BLENDFACTOR_DST_ALPHA: + return R300_BLEND_GL_DST_ALPHA; + case PIPE_BLENDFACTOR_DST_COLOR: + return R300_BLEND_GL_DST_COLOR; + case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: + return R300_BLEND_GL_SRC_ALPHA_SATURATE; + case PIPE_BLENDFACTOR_CONST_COLOR: + return R300_BLEND_GL_CONST_COLOR; + case PIPE_BLENDFACTOR_CONST_ALPHA: + return R300_BLEND_GL_CONST_ALPHA; + /* XXX WTF are these? + case PIPE_BLENDFACTOR_SRC1_COLOR: + case PIPE_BLENDFACTOR_SRC1_ALPHA: */ + case PIPE_BLENDFACTOR_ZERO: + return R300_BLEND_GL_ZERO; + case PIPE_BLENDFACTOR_INV_SRC_COLOR: + return R300_BLEND_GL_ONE_MINUS_SRC_COLOR; + case PIPE_BLENDFACTOR_INV_SRC_ALPHA: + return R300_BLEND_GL_ONE_MINUS_SRC_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_ALPHA: + return R300_BLEND_GL_ONE_MINUS_DST_ALPHA; + case PIPE_BLENDFACTOR_INV_DST_COLOR: + return R300_BLEND_GL_ONE_MINUS_DST_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_COLOR: + return R300_BLEND_GL_ONE_MINUS_CONST_COLOR; + case PIPE_BLENDFACTOR_INV_CONST_ALPHA: + return R300_BLEND_GL_ONE_MINUS_CONST_ALPHA; + /* XXX see above + case PIPE_BLENDFACTOR_INV_SRC1_COLOR: + case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: */ + default: + /* XXX the mythical 0x16 blend factor! */ + break; + } + return 0; +} + +static void* r300_create_blend_state(struct pipe_context* pipe, + struct pipe_blend_state* state) +{ + struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); + + if (state->blend_enable) { + /* XXX for now, always do separate alpha... + * is it faster to do it with one reg? */ + blend->blend_control = R300_ALPHA_BLEND_ENABLE | + R300_SEPARATE_ALPHA_ENABLE | + R300_READ_ENABLE | + translate_blend_function(state->rgb_func) | + (translate_blend_factor(state->rgb_src_factor) << + R300_SRC_BLEND_SHIFT) | + (translate_blend_factor(state->rgb_dst_factor) << + R300_DST_BLEND_SHIFT); + blend->alpha_blend_control = + translate_blend_function(state->alpha_func) | + (translate_blend_factor(state->alpha_src_factor) << + R300_SRC_BLEND_SHIFT) | + (translate_blend_factor(state->alpha_dst_factor) << + R300_DST_BLEND_SHIFT); + } + + /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ + /* XXX are logicops still allowed if blending's disabled? + * Does Gallium take care of it for us? */ + if (state->logicop_enable) { + blend->rop = R300_RB3D_ROPCNTL_ROP_ENABLE | + (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; + } + + if (state->dither) { + blend->dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | + R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; + } + + return (void*)blend; +} + +static void r300_bind_blend_state(struct pipe_context* pipe, + void* state) +{ + struct r300_context* r300 = r300_context(pipe); + + r300->blend_state = (struct r300_blend_state*)state; + r300->dirty_state |= R300_NEW_BLEND; +} + +static void r300_delete_blend_state(struct pipe_context* pipe, + void* state) +{ + FREE(state); +} static void* r300_create_vs_state(struct pipe_context* pipe, struct pipe_shader_state* state) diff --git a/src/gallium/drivers/r300/r300_state.h b/src/gallium/drivers/r300/r300_state.h index 861425936a..ad363bf2af 100644 --- a/src/gallium/drivers/r300/r300_state.h +++ b/src/gallium/drivers/r300/r300_state.h @@ -23,4 +23,6 @@ #ifndef R300_STATE_H #define R300_STATE_H +#include "r300_reg.h" + #endif /* R300_STATE_H */ \ No newline at end of file -- cgit v1.2.3 From 28bb7f3206f023a9d3cfa020da344a57118a2efb Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 14 Jan 2009 00:49:48 -0800 Subject: r300: Add scissor state, fix build. --- src/gallium/drivers/r300/r300_context.h | 10 ++++++- src/gallium/drivers/r300/r300_state.c | 47 +++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index b9fff0deab..6c64c9fa83 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -34,7 +34,13 @@ struct r300_blend_state { uint32_t dither; /* R300_RB3D_DITHER_CTL: 0x4e50 */ }; -#define R300_NEW_BLEND 0x1 +struct r300_scissor_state { + uint32_t scissor_top_left; /* R300_SC_SCISSORS_TL: 0x43e0 */ + uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ +}; + +#define R300_NEW_BLEND 0x1 +#define R300_NEW_SCISSOR 0x2 struct r300_context { /* Parent class */ @@ -48,6 +54,8 @@ struct r300_context { /* Various CSO state objects. */ /* Blend state. */ struct r300_blend_state* blend_state; + /* Scissor state. */ + struct r300_scissor_state* scissor_state; /* Bitmask of dirty state objects. */ uint32_t dirty_state; diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 93441f624e..2e19955454 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -88,6 +88,9 @@ static uint32_t translate_blend_factor(int blend_fact) { return 0; } +/* Create a new blend state based on the CSO blend state. + * + * This encompasses alpha blending, logic/raster ops, and blend dithering. */ static void* r300_create_blend_state(struct pipe_context* pipe, struct pipe_blend_state* state) { @@ -128,6 +131,7 @@ static void* r300_create_blend_state(struct pipe_context* pipe, return (void*)blend; } +/* Bind blend state. */ static void r300_bind_blend_state(struct pipe_context* pipe, void* state) { @@ -137,12 +141,55 @@ static void r300_bind_blend_state(struct pipe_context* pipe, r300->dirty_state |= R300_NEW_BLEND; } +/* Free blend state. */ static void r300_delete_blend_state(struct pipe_context* pipe, void* state) { FREE(state); } +/* Create a new scissor state based on the CSO scissor state. + * + * This is only for the fragment scissors. */ +static void* r300_create_scissor_state(struct pipe_context* pipe, + struct pipe_scissor_state* state) +{ + uint32_t left, top, right, bottom; + struct r300_scissor_state* scissor = CALLOC_STRUCT(r300_scissor_state); + + /* So, a bit of info. The scissors are offset by R300_SCISSORS_OFFSET in + * both directions for all values, and can only be 13 bits wide. Why? + * We may never know. */ + left = (state->minx + R300_SCISSORS_OFFSET) & 0x1fff; + top = (state->miny + R300_SCISSORS_OFFSET) & 0x1fff; + right = (state->maxx + R300_SCISSORS_OFFSET) & 0x1fff; + bottom = (state->maxy + R300_SCISSORS_OFFSET) & 0x1fff; + + scissor->scissor_top_left = (left << R300_SCISSORS_X_SHIFT) | + (top << R300_SCISSORS_Y_SHIFT); + scissor->scissor_bottom_right = (right << R300_SCISSORS_X_SHIFT) | + (bottom << R300_SCISSORS_Y_SHIFT); + + return (void*)scissor; +} + +/* Bind scissor state.*/ +static void r300_bind_scissor_state(struct pipe_context* pipe, + void* state) +{ + struct r300_context* r300 = r300_context(pipe); + + r300->scissor_state = (struct r300_scissor_state*)state; + r300->dirty_state |= R300_NEW_SCISSOR; +} + +/* Delete scissor state. */ +static void r300_delete_scissor_state(struct pipe_context* pipe, + void* state) +{ + FREE(state); +} + static void* r300_create_vs_state(struct pipe_context* pipe, struct pipe_shader_state* state) { -- cgit v1.2.3 From bbb1c6f6298fcb1125a8170f22646f326b0ca74c Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 14 Jan 2009 04:37:36 -0800 Subject: r300: Add DSA state. That's it for now. Just the "easy" stuff. Todo: - Rasterizer state, which is a lot more than just the RS. - Miscellaneous state which doesn't currently belong to any state object. - Shader assemblers? - Fix dynamic loading bugs. --- src/gallium/drivers/r300/r300_context.h | 15 ++- src/gallium/drivers/r300/r300_state.c | 162 ++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_state.h | 2 + 3 files changed, 178 insertions(+), 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 6c64c9fa83..81c559cedf 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -34,13 +34,24 @@ struct r300_blend_state { uint32_t dither; /* R300_RB3D_DITHER_CTL: 0x4e50 */ }; +struct r300_dsa_state { + uint32_t alpha_function; /* R300_FG_ALPHA_FUNC: 0x4bd4 */ + uint32_t alpha_reference; /* R500_FG_ALPHA_VALUE: 0x4be0 */ + uint32_t z_buffer_control; /* R300_ZB_CNTL: 0x4f00 */ + uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */ + uint32_t stencil_ref_mask; /* R300_ZB_STENCILREFMASK: 0x4f08 */ + uint32_t z_buffer_top; /* R300_ZB_ZTOP: 0x4f14 */ + uint32_t stencil_ref_bf; /* R300_ZB_STENCILREFMASK_BF: 0x4fd4 */ +}; + struct r300_scissor_state { uint32_t scissor_top_left; /* R300_SC_SCISSORS_TL: 0x43e0 */ uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ }; #define R300_NEW_BLEND 0x1 -#define R300_NEW_SCISSOR 0x2 +#define R300_NEW_DSA 0x2 +#define R300_NEW_SCISSOR 0x4 struct r300_context { /* Parent class */ @@ -54,6 +65,8 @@ struct r300_context { /* Various CSO state objects. */ /* Blend state. */ struct r300_blend_state* blend_state; + /* Depth, stencil, and alpha state. */ + struct r300_dsa_state* dsa_state; /* Scissor state. */ struct r300_scissor_state* scissor_state; diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 2e19955454..0f0660c403 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -148,6 +148,168 @@ static void r300_delete_blend_state(struct pipe_context* pipe, FREE(state); } +static uint32_t translate_depth_stencil_function(int zs_func) { + switch (zs_func) { + case PIPE_FUNC_NEVER: + return R300_ZS_NEVER; + case PIPE_FUNC_LESS: + return R300_ZS_LESS; + case PIPE_FUNC_EQUAL: + return R300_ZS_EQUAL; + case PIPE_FUNC_LEQUAL: + return R300_ZS_LEQUAL; + case PIPE_FUNC_GREATER: + return R300_ZS_GREATER; + case PIPE_FUNC_NOTEQUAL: + return R300_ZS_NOTEQUAL; + case PIPE_FUNC_GEQUAL: + return R300_ZS_GEQUAL; + case PIPE_FUNC_ALWAYS: + return R300_ZS_ALWAYS; + default: + /* XXX shouldn't be reachable */ + break; + } + return 0; +} + +static uint32_t translate_stencil_op(int s_op) { + switch (s_op) { + case PIPE_STENCIL_OP_KEEP: + return R300_ZS_KEEP; + case PIPE_STENCIL_OP_ZERO: + return R300_ZS_ZERO; + case PIPE_STENCIL_OP_REPLACE: + return R300_ZS_REPLACE; + case PIPE_STENCIL_OP_INCR: + return R300_ZS_INCR; + case PIPE_STENCIL_OP_DECR: + return R300_ZS_DECR; + case PIPE_STENCIL_OP_INCR_WRAP: + return R300_ZS_INCR_WRAP; + case PIPE_STENCIL_OP_DECR_WRAP: + return R300_ZS_DECR_WRAP; + case PIPE_STENCIL_OP_INVERT: + return R300_ZS_INVERT; + default: + /* XXX shouldn't be reachable */ + break; + } + return 0; +} + +static uint32_t translate_alpha_function(int alpha_func) { + switch (alpha_func) { + case PIPE_FUNC_NEVER: + return R300_FG_ALPHA_FUNC_NEVER; + case PIPE_FUNC_LESS: + return R300_FG_ALPHA_FUNC_LESS; + case PIPE_FUNC_EQUAL: + return R300_FG_ALPHA_FUNC_EQUAL; + case PIPE_FUNC_LEQUAL: + return R300_FG_ALPHA_FUNC_LE; + case PIPE_FUNC_GREATER: + return R300_FG_ALPHA_FUNC_GREATER; + case PIPE_FUNC_NOTEQUAL: + return R300_FG_ALPHA_FUNC_NOTEQUAL; + case PIPE_FUNC_GEQUAL: + return R300_FG_ALPHA_FUNC_GE; + case PIPE_FUNC_ALWAYS: + return R300_FG_ALPHA_FUNC_ALWAYS; + default: + /* XXX shouldn't be reachable */ + break; + } + return 0; +} + +/* Create a new depth, stencil, and alpha state based on the CSO dsa state. + * + * This contains the depth buffer, stencil buffer, alpha test, and such. + * On the Radeon, depth and stencil buffer setup are intertwined, which is + * the reason for some of the strange-looking assignments across registers. */ +static void* r300_create_dsa_state(struct pipe_context* pipe, + struct pipe_depth_stencil_alpha_state* state) +{ + struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); + + /* Depth test setup. */ + if (state->depth.enabled) { + dsa->z_buffer_control |= R300_Z_ENABLE; + + if (state->depth.writemask) { + dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; + } + + dsa->z_stencil_control |= + (translate_depth_stencil_function(state->depth.func) << + R300_Z_FUNC_SHIFT); + } + + /* Stencil buffer setup. */ + if (state->stencil[0].enabled) { + dsa->z_buffer_control |= R300_STENCIL_ENABLE; + dsa->z_stencil_control |= + (translate_depth_stencil_function(state->stencil[0].func) << + R300_S_FRONT_FUNC_SHIFT) | + (translate_stencil_op(state->stencil[0].fail_op) << + R300_S_FRONT_SFAIL_OP_SHIFT) | + (translate_stencil_op(state->stencil[0].zpass_op) << + R300_S_FRONT_ZPASS_OP_SHIFT) | + (translate_stencil_op(state->stencil[0].zfail_op) << + R300_S_FRONT_ZFAIL_OP_SHIFT); + + dsa->stencil_ref_mask = (state->stencil[0].ref_value) | + (state->stencil[0].value_mask << R300_STENCILMASK_SHIFT) | + (state->stencil[0].write_mask << R300_STENCILWRITEMASK_SHIFT); + + if (state->stencil[1].enabled) { + dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; + dsa->z_stencil_control |= + (translate_depth_stencil_function(state->stencil[1].func) << + R300_S_BACK_FUNC_SHIFT) | + (translate_stencil_op(state->stencil[1].fail_op) << + R300_S_BACK_SFAIL_OP_SHIFT) | + (translate_stencil_op(state->stencil[1].zpass_op) << + R300_S_BACK_ZPASS_OP_SHIFT) | + (translate_stencil_op(state->stencil[1].zfail_op) << + R300_S_BACK_ZFAIL_OP_SHIFT); + + dsa->stencil_ref_bf = (state->stencil[1].ref_value) | + (state->stencil[1].value_mask << R300_STENCILMASK_SHIFT) | + (state->stencil[1].write_mask << R300_STENCILWRITEMASK_SHIFT); + } + } + + /* Alpha test setup. */ + if (state->alpha.enabled) { + dsa->alpha_function = translate_alpha_function(state->alpha.func) | + R300_FG_ALPHA_FUNC_ENABLE; + dsa->alpha_reference = CLAMP(state->alpha.ref * 1023.0f, 0, 1023); + } else { + dsa->z_buffer_top = R300_ZTOP_ENABLE; + } + + return (void*)dsa; +} + +/* Bind DSA state. */ +static void r300_bind_dsa_state(struct pipe_context* pipe, + void* state) +{ + struct r300_context* r300 = r300_context(pipe); + + r300->dsa_state = (struct r300_dsa_state*)state; + r300->dirty_state |= R300_NEW_DSA; +} + +/* Free DSA state. */ +static void r300_delete_dsa_state(struct pipe_context* pipe, + void* state) +{ + FREE(state); +} + /* Create a new scissor state based on the CSO scissor state. * * This is only for the fragment scissors. */ diff --git a/src/gallium/drivers/r300/r300_state.h b/src/gallium/drivers/r300/r300_state.h index ad363bf2af..c8b742281e 100644 --- a/src/gallium/drivers/r300/r300_state.h +++ b/src/gallium/drivers/r300/r300_state.h @@ -25,4 +25,6 @@ #include "r300_reg.h" +#include "util/u_math.h" + #endif /* R300_STATE_H */ \ No newline at end of file -- cgit v1.2.3 From 21a5a133fff3ab1a068a11a32144dcb63f1d5020 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 14 Jan 2009 05:00:22 -0800 Subject: r300: Hook up state functions. Haha, should not have attempted the scissors. --- src/gallium/drivers/r300/r300_context.c | 2 ++ src/gallium/drivers/r300/r300_context.h | 8 ++--- src/gallium/drivers/r300/r300_state.c | 60 +++++++++++++-------------------- 3 files changed, 27 insertions(+), 43 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index b9a9c2e21c..67cc1e4586 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -54,5 +54,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300_init_surface_functions(r300); + r300_init_state_functions(r300); + return &r300->context; } diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 81c559cedf..40c310abca 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -44,11 +44,6 @@ struct r300_dsa_state { uint32_t stencil_ref_bf; /* R300_ZB_STENCILREFMASK_BF: 0x4fd4 */ }; -struct r300_scissor_state { - uint32_t scissor_top_left; /* R300_SC_SCISSORS_TL: 0x43e0 */ - uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ -}; - #define R300_NEW_BLEND 0x1 #define R300_NEW_DSA 0x2 #define R300_NEW_SCISSOR 0x4 @@ -68,7 +63,7 @@ struct r300_context { /* Depth, stencil, and alpha state. */ struct r300_dsa_state* dsa_state; /* Scissor state. */ - struct r300_scissor_state* scissor_state; + struct pipe_scissor_state* scissor_state; /* Bitmask of dirty state objects. */ uint32_t dirty_state; @@ -80,6 +75,7 @@ static struct r300_context* r300_context(struct pipe_context* context) { } /* Context initialization. */ +void r300_init_state_functions(struct r300_context* r300); void r300_init_surface_functions(struct r300_context* r300); struct pipe_context* r300_create_context(struct pipe_screen* screen, diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 0f0660c403..122e06c6e6 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -92,7 +92,7 @@ static uint32_t translate_blend_factor(int blend_fact) { * * This encompasses alpha blending, logic/raster ops, and blend dithering. */ static void* r300_create_blend_state(struct pipe_context* pipe, - struct pipe_blend_state* state) + const struct pipe_blend_state* state) { struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); @@ -310,48 +310,17 @@ static void r300_delete_dsa_state(struct pipe_context* pipe, FREE(state); } -/* Create a new scissor state based on the CSO scissor state. - * - * This is only for the fragment scissors. */ -static void* r300_create_scissor_state(struct pipe_context* pipe, - struct pipe_scissor_state* state) -{ - uint32_t left, top, right, bottom; - struct r300_scissor_state* scissor = CALLOC_STRUCT(r300_scissor_state); - - /* So, a bit of info. The scissors are offset by R300_SCISSORS_OFFSET in - * both directions for all values, and can only be 13 bits wide. Why? - * We may never know. */ - left = (state->minx + R300_SCISSORS_OFFSET) & 0x1fff; - top = (state->miny + R300_SCISSORS_OFFSET) & 0x1fff; - right = (state->maxx + R300_SCISSORS_OFFSET) & 0x1fff; - bottom = (state->maxy + R300_SCISSORS_OFFSET) & 0x1fff; - - scissor->scissor_top_left = (left << R300_SCISSORS_X_SHIFT) | - (top << R300_SCISSORS_Y_SHIFT); - scissor->scissor_bottom_right = (right << R300_SCISSORS_X_SHIFT) | - (bottom << R300_SCISSORS_Y_SHIFT); - - return (void*)scissor; -} - -/* Bind scissor state.*/ -static void r300_bind_scissor_state(struct pipe_context* pipe, - void* state) +static void r300_set_scissor_state(struct pipe_context* pipe, + struct pipe_scissor_state* state) { struct r300_context* r300 = r300_context(pipe); + draw_flush(r300->draw); - r300->scissor_state = (struct r300_scissor_state*)state; + /* XXX figure out how this memory doesn't get lost in space + memcpy(r300->scissor, scissor, sizeof(struct pipe_scissor_state)); */ r300->dirty_state |= R300_NEW_SCISSOR; } -/* Delete scissor state. */ -static void r300_delete_scissor_state(struct pipe_context* pipe, - void* state) -{ - FREE(state); -} - static void* r300_create_vs_state(struct pipe_context* pipe, struct pipe_shader_state* state) { @@ -371,4 +340,21 @@ static void r300_delete_vs_state(struct pipe_context* pipe, void* state) struct r300_context* context = r300_context(pipe); /* XXX handing this off to Draw for now */ draw_delete_vertex_shader(context->draw, (struct draw_vertex_shader*)state); +} + +void r300_init_state_functions(struct r300_context* r300) { + + r300->context.create_blend_state = r300_create_blend_state; + r300->context.bind_blend_state = r300_bind_blend_state; + r300->context.delete_blend_state = r300_delete_blend_state; + + r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; + r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; + r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; + + r300->context.set_scissor_state = r300_set_scissor_state; + + r300->context.create_vs_state = r300_create_vs_state; + r300->context.bind_vs_state = r300_bind_vs_state; + r300->context.delete_vs_state = r300_delete_vs_state; } \ No newline at end of file -- cgit v1.2.3 From 4ce81294943177eed99d7418f1a2f88573b578fe Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 14 Jan 2009 12:51:47 -0800 Subject: r300: Fix errant inlines. This should unbreak dynamic loading. --- src/gallium/drivers/r300/r300_context.h | 4 +++- src/gallium/drivers/r300/r300_screen.h | 3 +-- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 40c310abca..0551275dcc 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -27,6 +27,8 @@ #include "pipe/p_context.h" #include "util/u_memory.h" +#include "r300_screen.h" + struct r300_blend_state { uint32_t blend_control; /* R300_RB3D_BLENDCNTL: 0x4e04 */ uint32_t alpha_blend_control; /* R300_RB3D_ABLENDCNTL: 0x4e08 */ @@ -82,4 +84,4 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, struct pipe_winsys* winsys, struct r300_winsys* r300_winsys); -#endif /* R300_CONTEXT_H */ \ No newline at end of file +#endif /* R300_CONTEXT_H */ diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index 36fc5aa67d..a1b97f218e 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -23,11 +23,10 @@ #ifndef R300_SCREEN_H #define R300_SCREEN_H +#include "pipe/p_inlines.h" #include "pipe/p_screen.h" #include "util/u_memory.h" -#include "r300_context.h" - struct r300_screen { /* Parent class */ struct pipe_screen screen; -- cgit v1.2.3 From a08a830fd3c22bdbad1ee840e4e56302152375f1 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 17 Jan 2009 01:41:52 -0800 Subject: r300: Add more state. pipe_rasterizer_state is big, and I'm still processing it. Todo: - LOL EVERYTHING - Moar cough syrup. - Even moar cough syrup. --- src/gallium/drivers/r300/r300_context.c | 8 +- src/gallium/drivers/r300/r300_context.h | 21 ++++- src/gallium/drivers/r300/r300_state.c | 136 +++++++++++++++++++++++++++++++- 3 files changed, 155 insertions(+), 10 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 67cc1e4586..6dfc9ed624 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -27,7 +27,8 @@ static void r300_destroy_context(struct pipe_context* context) { draw_destroy(r300->draw); - FREE(context); + FREE(r300->scissor_state); + FREE(r300); } struct pipe_context* r300_create_context(struct pipe_screen* screen, @@ -47,10 +48,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->draw = draw_create(); - /* XXX this is almost certainly wrong - * put this all in winsys, where we can get an FD - struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); - r300->cs = cs_gem_create(csm, 64 * 1024 / 4); */ + r300->scissor_state = CALLOC_STRUCT(r300_scissor_state); r300_init_surface_functions(r300); diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 0551275dcc..ea057bcab7 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -46,9 +46,24 @@ struct r300_dsa_state { uint32_t stencil_ref_bf; /* R300_ZB_STENCILREFMASK_BF: 0x4fd4 */ }; +struct r300_rs_state { + uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ + uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ + uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */ + uint32_t depth_offset_front; /* R300_SU_POLY_OFFSET_FRONT_OFFSET: 0x42a8 */ + uint32_t depth_scale_back; /* R300_SU_POLY_OFFSET_BACK_SCALE: 0x42ac */ + uint32_t depth_offset_back; /* R300_SU_POLY_OFFSET_BACK_OFFSET: 0x42b0 */ +}; + +struct r300_scissor_state { + uint32_t scissor_top_left; /* R300_SC_SCISSORS_TL: 0x43e0 */ + uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ +}; + #define R300_NEW_BLEND 0x1 #define R300_NEW_DSA 0x2 -#define R300_NEW_SCISSOR 0x4 +#define R300_NEW_RS 0x4 +#define R300_NEW_SCISSOR 0x8 struct r300_context { /* Parent class */ @@ -64,8 +79,10 @@ struct r300_context { struct r300_blend_state* blend_state; /* Depth, stencil, and alpha state. */ struct r300_dsa_state* dsa_state; + /* Rasterizer state. */ + struct r300_rs_state* rs_state; /* Scissor state. */ - struct pipe_scissor_state* scissor_state; + struct r300_scissor_state* scissor_state; /* Bitmask of dirty state objects. */ uint32_t dirty_state; diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 122e06c6e6..7668b14c63 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -23,6 +23,23 @@ #include "r300_context.h" #include "r300_state.h" +/* r300_state: Functions used to intialize state context by translating + * Gallium state objects into semi-native r300 state objects. + * + * XXX break this file up into pieces if it gets too big! */ + +/* Pack a float into a dword. */ +static uint32_t pack_float_32(float f) +{ + union { + float f; + uint32_t u; + } u; + + u.f = f; + return u.u; +} + static uint32_t translate_blend_function(int blend_func) { switch (blend_func) { case PIPE_BLEND_ADD: @@ -229,7 +246,7 @@ static uint32_t translate_alpha_function(int alpha_func) { * On the Radeon, depth and stencil buffer setup are intertwined, which is * the reason for some of the strange-looking assignments across registers. */ static void* r300_create_dsa_state(struct pipe_context* pipe, - struct pipe_depth_stencil_alpha_state* state) + struct pipe_depth_stencil_alpha_state* state) { struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); @@ -309,6 +326,102 @@ static void r300_delete_dsa_state(struct pipe_context* pipe, { FREE(state); } +#if 0 +struct pipe_rasterizer_state +{ + unsigned flatshade:1; + unsigned light_twoside:1; + unsigned fill_cw:2; /**< PIPE_POLYGON_MODE_x */ + unsigned fill_ccw:2; /**< PIPE_POLYGON_MODE_x */ + unsigned scissor:1; + unsigned poly_smooth:1; + unsigned poly_stipple_enable:1; + unsigned point_smooth:1; + unsigned point_sprite:1; + unsigned point_size_per_vertex:1; /**< size computed in vertex shader */ + unsigned multisample:1; /* XXX maybe more ms state in future */ + unsigned line_smooth:1; + unsigned line_stipple_enable:1; + unsigned line_stipple_factor:8; /**< [1..256] actually */ + unsigned line_stipple_pattern:16; + unsigned line_last_pixel:1; + unsigned bypass_clipping:1; + unsigned bypass_vs:1; /**< Skip the vertex shader. Note that the shader is + still needed though, to indicate inputs/outputs */ + unsigned origin_lower_left:1; /**< Is (0,0) the lower-left corner? */ + unsigned flatshade_first:1; /**< take color attribute from the first vertex of a primitive */ + unsigned gl_rasterization_rules:1; /**< enable tweaks for GL rasterization? */ + + float line_width; + float point_size; /**< used when no per-vertex size */ + float point_size_min; /* XXX - temporary, will go away */ + float point_size_max; /* XXX - temporary, will go away */ + ubyte sprite_coord_mode[PIPE_MAX_SHADER_OUTPUTS]; /**< PIPE_SPRITE_COORD_ */ +}; +#endif +/* Create a new rasterizer state based on the CSO rasterizer state. + * + * This is a very large chunk of state, and covers most of the graphics + * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. + * + * In a not entirely unironic sidenote, this state has nearly nothing to do + * with the actual block on the Radeon called the rasterizer (RS). */ +static void* r300_create_rs_state(struct pipe_context* pipe, + struct pipe_rasterizer_state* state) +{ + struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); + + /* Radeons don't think in "CW/CCW", they think in "front/back". */ + if (state->front_winding == PIPE_WINDING_CW) { + rs->cull_mode = R300_FRONT_FACE_CW; + + if (state->offset_cw) { + rs->polygon_offset_enable |= R300_FRONT_ENABLE; + } + if (state->offset_ccw) { + rs->polygon_offset_enable |= R300_BACK_ENABLE; + } + } else { + rs->cull_mode = R300_FRONT_FACE_CCW; + + if (state->offset_ccw) { + rs->polygon_offset_enable |= R300_FRONT_ENABLE; + } + if (state->offset_cw) { + rs->polygon_offset_enable |= R300_BACK_ENABLE; + } + } + if (state->front_winding & state->cull_mode) { + rs->cull_mode |= R300_CULL_FRONT; + } + if (~(state->front_winding) & state->cull_mode) { + rs->cull_mode |= R300_CULL_BACK; + } + + if (rs->polygon_offset_enable) { + rs->depth_offset_front = rs->depth_offset_back = + pack_float_32(state->offset_units); + rs->depth_scale_front = rs->depth_scale_back = + pack_float_32(state->offset_scale); + } + + return (void*)rs; +} + +/* Bind rasterizer state. */ +static void r300_bind_rs_state(struct pipe_context* pipe, void* state) +{ + struct r300_context* r300 = r300_context(pipe); + + r300->rs_state = (struct r300_rs_state*)state; + r300->dirty_state |= R300_NEW_RS; +} + +/* Free rasterizer state. */ +static void r300_delete_rs_state(struct pipe_context* pipe, void* state) +{ + FREE(state); +} static void r300_set_scissor_state(struct pipe_context* pipe, struct pipe_scissor_state* state) @@ -316,8 +429,21 @@ static void r300_set_scissor_state(struct pipe_context* pipe, struct r300_context* r300 = r300_context(pipe); draw_flush(r300->draw); - /* XXX figure out how this memory doesn't get lost in space - memcpy(r300->scissor, scissor, sizeof(struct pipe_scissor_state)); */ + uint32_t left, top, right, bottom; + + /* So, a bit of info. The scissors are offset by R300_SCISSORS_OFFSET in + * both directions for all values, and can only be 13 bits wide. Why? + * We may never know. */ + left = (state->minx + R300_SCISSORS_OFFSET) & 0x1fff; + top = (state->miny + R300_SCISSORS_OFFSET) & 0x1fff; + right = (state->maxx + R300_SCISSORS_OFFSET) & 0x1fff; + bottom = (state->maxy + R300_SCISSORS_OFFSET) & 0x1fff; + + r300->scissor_state->scissor_top_left = (left << R300_SCISSORS_X_SHIFT) | + (top << R300_SCISSORS_Y_SHIFT); + r300->scissor_state->scissor_bottom_right = (right << R300_SCISSORS_X_SHIFT) | + (bottom << R300_SCISSORS_Y_SHIFT); + r300->dirty_state |= R300_NEW_SCISSOR; } @@ -348,6 +474,10 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.bind_blend_state = r300_bind_blend_state; r300->context.delete_blend_state = r300_delete_blend_state; + r300->context.create_rasterizer_state = r300_create_rs_state; + r300->context.bind_rasterizer_state = r300_bind_rs_state; + r300->context.delete_rasterizer_state = r300_delete_rs_state; + r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; -- cgit v1.2.3 From f3b53a5cb6a04b86ccd75cc38c73c8e3dd117894 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 17 Jan 2009 02:25:52 -0800 Subject: r300: Add blend color. --- src/gallium/drivers/r300/r300_context.c | 2 ++ src/gallium/drivers/r300/r300_context.h | 19 +++++++++++++++---- src/gallium/drivers/r300/r300_state.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 4 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 6dfc9ed624..b072179f5b 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -27,6 +27,7 @@ static void r300_destroy_context(struct pipe_context* context) { draw_destroy(r300->draw); + FREE(r300->blend_color_state); FREE(r300->scissor_state); FREE(r300); } @@ -48,6 +49,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->draw = draw_create(); + r300->blend_color_state = CALLOC_STRUCT(r300_blend_color_state); r300->scissor_state = CALLOC_STRUCT(r300_scissor_state); r300_init_surface_functions(r300); diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index ea057bcab7..4cbbf96fb1 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -36,6 +36,14 @@ struct r300_blend_state { uint32_t dither; /* R300_RB3D_DITHER_CTL: 0x4e50 */ }; +struct r300_blend_color_state { + /* RV515 and earlier */ + uint32_t blend_color; /* R300_RB3D_BLEND_COLOR: 0x4e10 */ + /* R520 and newer */ + uint32_t blend_color_red_alpha; /* R500_RB3D_CONSTANT_COLOR_AR: 0x4ef8 */ + uint32_t blend_color_green_blue; /* R500_RB3D_CONSTANT_COLOR_GB: 0x4efc */ +}; + struct r300_dsa_state { uint32_t alpha_function; /* R300_FG_ALPHA_FUNC: 0x4bd4 */ uint32_t alpha_reference; /* R500_FG_ALPHA_VALUE: 0x4be0 */ @@ -60,10 +68,11 @@ struct r300_scissor_state { uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ }; -#define R300_NEW_BLEND 0x1 -#define R300_NEW_DSA 0x2 -#define R300_NEW_RS 0x4 -#define R300_NEW_SCISSOR 0x8 +#define R300_NEW_BLEND 0x01 +#define R300_NEW_BLEND_COLOR 0x02 +#define R300_NEW_DSA 0x04 +#define R300_NEW_RS 0x08 +#define R300_NEW_SCISSOR 0x10 struct r300_context { /* Parent class */ @@ -77,6 +86,8 @@ struct r300_context { /* Various CSO state objects. */ /* Blend state. */ struct r300_blend_state* blend_state; + /* Blend color state. */ + struct r300_blend_color_state* blend_color_state; /* Depth, stencil, and alpha state. */ struct r300_dsa_state* dsa_state; /* Rasterizer state. */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 7668b14c63..4392078e74 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -165,6 +165,33 @@ static void r300_delete_blend_state(struct pipe_context* pipe, FREE(state); } +/* Set blend color. + * Setup both R300 and R500 registers, figure out later which one to write. */ +static void r300_set_blend_color(struct pipe_context* pipe, + const struct pipe_blend_color* color) +{ + struct r300_context* r300 = r300_context(pipe); + uint32_t r, g, b, a; + ubyte ur, ug, ub, ua; + + r = util_iround(color->color[0] * 1023.0f); + g = util_iround(color->color[1] * 1023.0f); + b = util_iround(color->color[2] * 1023.0f); + a = util_iround(color->color[3] * 1023.0f); + + ur = float_to_ubyte(color->color[0]); + ug = float_to_ubyte(color->color[1]); + ub = float_to_ubyte(color->color[2]); + ua = float_to_ubyte(color->color[3]); + + r300->blend_color_state->blend_color = (a << 24) | (r << 16) | (g << 8) | b; + + r300->blend_color_state->blend_color_red_alpha = ur | (ua << 16); + r300->blend_color_state->blend_color_green_blue = ub | (ug << 16); + + r300->dirty_state |= R300_NEW_BLEND_COLOR; +} + static uint32_t translate_depth_stencil_function(int zs_func) { switch (zs_func) { case PIPE_FUNC_NEVER: @@ -474,6 +501,8 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.bind_blend_state = r300_bind_blend_state; r300->context.delete_blend_state = r300_delete_blend_state; + r300->context.set_blend_color = r300_set_blend_color; + r300->context.create_rasterizer_state = r300_create_rs_state; r300->context.bind_rasterizer_state = r300_bind_rs_state; r300->context.delete_rasterizer_state = r300_delete_rs_state; -- cgit v1.2.3 From 4ea17301c60a805394b8938174d8f436dc3deb6d Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 17 Jan 2009 02:27:33 -0800 Subject: r300: Remove r300_state.h --- src/gallium/drivers/r300/r300_state.c | 4 +++- src/gallium/drivers/r300/r300_state.h | 30 ------------------------------ 2 files changed, 3 insertions(+), 31 deletions(-) delete mode 100644 src/gallium/drivers/r300/r300_state.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 4392078e74..cff4b30d16 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -20,8 +20,10 @@ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. */ +#include "util/u_math.h" + #include "r300_context.h" -#include "r300_state.h" +#include "r300_reg.h" /* r300_state: Functions used to intialize state context by translating * Gallium state objects into semi-native r300 state objects. diff --git a/src/gallium/drivers/r300/r300_state.h b/src/gallium/drivers/r300/r300_state.h deleted file mode 100644 index c8b742281e..0000000000 --- a/src/gallium/drivers/r300/r300_state.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright 2008 Corbin Simpson - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef R300_STATE_H -#define R300_STATE_H - -#include "r300_reg.h" - -#include "util/u_math.h" - -#endif /* R300_STATE_H */ \ No newline at end of file -- cgit v1.2.3 From 7961974fc28257b293961d35f15c0ce7a85f2669 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 17 Jan 2009 03:20:48 -0800 Subject: r300: Add a basic dirty state emit. I feel strangely unproductive. Must be the cold. --- src/gallium/drivers/r300/Makefile | 1 + src/gallium/drivers/r300/r300_context.h | 11 ++-- src/gallium/drivers/r300/r300_cs.h | 3 ++ src/gallium/drivers/r300/r300_emit.c | 92 +++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_screen.c | 7 ++- 5 files changed, 108 insertions(+), 6 deletions(-) create mode 100644 src/gallium/drivers/r300/r300_emit.c (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index bce7dcbf3a..644e6d0ba3 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -7,6 +7,7 @@ C_SOURCES = \ r300_blit.c \ r300_clear.c \ r300_context.c \ + r300_emit.c \ r300_screen.c \ r300_state.c \ r300_surface.c diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 4cbbf96fb1..ad1e4fc7c4 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -30,8 +30,8 @@ #include "r300_screen.h" struct r300_blend_state { - uint32_t blend_control; /* R300_RB3D_BLENDCNTL: 0x4e04 */ - uint32_t alpha_blend_control; /* R300_RB3D_ABLENDCNTL: 0x4e08 */ + uint32_t blend_control; /* R300_RB3D_CBLEND: 0x4e04 */ + uint32_t alpha_blend_control; /* R300_RB3D_ABLEND: 0x4e08 */ uint32_t rop; /* R300_RB3D_ROPCNTL: 0x4e18 */ uint32_t dither; /* R300_RB3D_DITHER_CTL: 0x4e50 */ }; @@ -51,16 +51,16 @@ struct r300_dsa_state { uint32_t z_stencil_control; /* R300_ZB_ZSTENCILCNTL: 0x4f04 */ uint32_t stencil_ref_mask; /* R300_ZB_STENCILREFMASK: 0x4f08 */ uint32_t z_buffer_top; /* R300_ZB_ZTOP: 0x4f14 */ - uint32_t stencil_ref_bf; /* R300_ZB_STENCILREFMASK_BF: 0x4fd4 */ + uint32_t stencil_ref_bf; /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */ }; struct r300_rs_state { - uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ - uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */ uint32_t depth_offset_front; /* R300_SU_POLY_OFFSET_FRONT_OFFSET: 0x42a8 */ uint32_t depth_scale_back; /* R300_SU_POLY_OFFSET_BACK_SCALE: 0x42ac */ uint32_t depth_offset_back; /* R300_SU_POLY_OFFSET_BACK_OFFSET: 0x42b0 */ + uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ + uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ }; struct r300_scissor_state { @@ -73,6 +73,7 @@ struct r300_scissor_state { #define R300_NEW_DSA 0x04 #define R300_NEW_RS 0x08 #define R300_NEW_SCISSOR 0x10 +#define R300_NEW_KITCHEN_SINK 0x1f struct r300_context { /* Parent class */ diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 92ed807657..3dacf25380 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -37,6 +37,9 @@ #define RADEON_GEM_DOMAIN_GTT 0x2 #define RADEON_GEM_DOMAIN_VRAM 0x4 +/* XXX stolen from radeon_reg.h */ +#define RADEON_CP_PACKET0 0x0 + #define CP_PACKET0(register, count) \ (RADEON_CP_PACKET0 | ((count) << 16) | ((register) >> 2)) diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c new file mode 100644 index 0000000000..8662830ee2 --- /dev/null +++ b/src/gallium/drivers/r300/r300_emit.c @@ -0,0 +1,92 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* r300_emit: Functions for emitting state. */ + +#include "r300_context.h" +#include "r300_cs.h" +#include "r300_screen.h" + +static void r300_emit_dirty_state(struct r300_context* r300) +{ + struct r300_screen* r300screen = (struct r300_screen*)r300->context.screen; + CS_LOCALS(r300); + + /* XXX check size */ + + if (r300->dirty_state & R300_NEW_BLEND) { + struct r300_blend_state* blend = r300->blend_state; + /* XXX next two are contiguous regs */ + OUT_CS_REG(R300_RB3D_CBLEND, blend->blend_control); + OUT_CS_REG(R300_RB3D_ABLEND, blend->alpha_blend_control); + OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop); + OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither); + } + + if (r300->dirty_state & R300_NEW_BLEND_COLOR) { + struct r300_blend_color_state* blend_color = r300->blend_color_state; + if (r300screen->is_r500) { + /* XXX next two are contiguous regs */ + OUT_CS_REG(R500_RB3D_CONSTANT_COLOR_AR, + blend_color->blend_color_red_alpha); + OUT_CS_REG(R500_RB3D_CONSTANT_COLOR_GB, + blend_color->blend_color_green_blue); + } else { + OUT_CS_REG(R300_RB3D_BLEND_COLOR, + blend_color->blend_color); + } + } + + if (r300->dirty_state & R300_NEW_DSA) { + struct r300_dsa_state* dsa = r300->dsa_state; + OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); + OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); + /* XXX next three are contiguous regs */ + OUT_CS_REG(R300_ZB_CNTL, dsa->z_buffer_control); + OUT_CS_REG(R300_ZB_ZSTENCILCNTL, dsa->z_stencil_control); + OUT_CS_REG(R300_ZB_STENCILREFMASK, dsa->stencil_ref_mask); + OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top); + if (r300screen->is_r500) { + OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); + } + } + + if (r300->dirty_state & R300_NEW_RS) { + struct r300_rs_state* rs = r300->rs_state; + /* XXX next six are contiguous regs */ + OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, rs->depth_scale_front); + OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, rs->depth_offset_front); + OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, rs->depth_scale_back); + OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, rs->depth_offset_back); + OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, rs->polygon_offset_enable); + OUT_CS_REG(R300_SU_CULL_MODE, rs->cull_mode); + } + + if (r300->dirty_state & R300_NEW_SCISSOR) { + struct r300_scissor_state* scissor = r300->scissor_state; + /* XXX next two are contiguous regs */ + OUT_CS_REG(R300_SC_SCISSORS_TL, scissor->scissor_top_left); + OUT_CS_REG(R300_SC_SCISSORS_BR, scissor->scissor_bottom_right); + } + + r300->dirty_state = 0; +} diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index dacde27888..5074e3e6fa 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -35,7 +35,7 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) { struct r300_screen* r300screen = r300_screen(pscreen); switch (param) { - /* Cases marked "IN THEORY" are possible on the hardware, + /* XXX cases marked "IN THEORY" are possible on the hardware, * but haven't been implemented yet. */ case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS: /* XXX I'm told this goes up to 16 */ @@ -48,6 +48,11 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) { return 0; case PIPE_CAP_TWO_SIDED_STENCIL: /* IN THEORY */ + /* if (r300screen->is_r500) { + * return 1; + * } else { + * return 0; + * } */ return 0; case PIPE_CAP_ANISOTROPIC_FILTER: /* IN THEORY */ -- cgit v1.2.3 From 2e09845277ce75fa7d29020c5b119ad749522592 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 19 Jan 2009 21:03:24 -0800 Subject: r300: Various flags, small state tracking things. Getting these out of the way so more stuff can be put in. --- src/gallium/drivers/r300/r300_context.c | 3 +++ src/gallium/drivers/r300/r300_context.h | 3 +++ src/gallium/drivers/r300/r300_emit.c | 5 +++++ src/gallium/drivers/r300/r300_screen.c | 1 - src/gallium/drivers/r300/r300_state.c | 4 ++++ 5 files changed, 15 insertions(+), 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index b072179f5b..798d6bdc6f 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -56,5 +56,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300_init_state_functions(r300); + r300->dirty_state = R300_NEW_KITCHEN_SINK; + r300->dirty_hw++; + return &r300->context; } diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index ad1e4fc7c4..be6214b7ae 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -55,6 +55,7 @@ struct r300_dsa_state { }; struct r300_rs_state { + uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */ uint32_t depth_offset_front; /* R300_SU_POLY_OFFSET_FRONT_OFFSET: 0x42a8 */ uint32_t depth_scale_back; /* R300_SU_POLY_OFFSET_BACK_SCALE: 0x42ac */ @@ -98,6 +99,8 @@ struct r300_context { /* Bitmask of dirty state objects. */ uint32_t dirty_state; + /* Flag indicating whether or not the HW is dirty. */ + uint32_t dirty_hw; }; /* Convenience cast wrapper. */ diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 8662830ee2..3c59a270b3 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -31,6 +31,10 @@ static void r300_emit_dirty_state(struct r300_context* r300) struct r300_screen* r300screen = (struct r300_screen*)r300->context.screen; CS_LOCALS(r300); + if (!(r300->dirty_state) && !(r300->dirty_hw)) { + return; + } + /* XXX check size */ if (r300->dirty_state & R300_NEW_BLEND) { @@ -72,6 +76,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) if (r300->dirty_state & R300_NEW_RS) { struct r300_rs_state* rs = r300->rs_state; + OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status); /* XXX next six are contiguous regs */ OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, rs->depth_scale_front); OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, rs->depth_offset_front); diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 5074e3e6fa..5c1bab386f 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -123,7 +123,6 @@ static void* r300_surface_map(struct pipe_screen* screen, struct pipe_surface* surface, unsigned flags) { - /* XXX this is not quite right */ char* map = pipe_buffer_map(screen, surface->buffer, flags); if (!map) { diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index cff4b30d16..d73f4483db 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -434,6 +434,10 @@ static void* r300_create_rs_state(struct pipe_context* pipe, pack_float_32(state->offset_scale); } + /* XXX this is part of HW TCL */ + /* XXX endian control */ + rs->vap_control_status = R300_VAP_TCL_BYPASS; + return (void*)rs; } -- cgit v1.2.3 From 538a8149af3fc773a3d1e15d113cb4e3fadc57cd Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 20 Jan 2009 00:31:43 -0800 Subject: r300: Add chipset sorting and capabilities. Part one: Capabilities from classic Mesa. Damn, if only we didn't have so many fucking Radeons! --- src/gallium/drivers/r300/Makefile | 1 + src/gallium/drivers/r300/r300_chipset.c | 391 ++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_chipset.h | 100 ++++++++ src/gallium/drivers/r300/r300_emit.c | 4 +- src/gallium/drivers/r300/r300_screen.c | 23 +- src/gallium/drivers/r300/r300_screen.h | 7 +- 6 files changed, 505 insertions(+), 21 deletions(-) create mode 100644 src/gallium/drivers/r300/r300_chipset.c create mode 100644 src/gallium/drivers/r300/r300_chipset.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index 644e6d0ba3..ad792e9aa8 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -5,6 +5,7 @@ LIBNAME = r300 C_SOURCES = \ r300_blit.c \ + r300_chipset.c \ r300_clear.c \ r300_context.c \ r300_emit.c \ diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c new file mode 100644 index 0000000000..926a9dda50 --- /dev/null +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -0,0 +1,391 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "r300_chipset.h" + +/* r300_chipset: A file all to itself for deducing the various properties of + * Radeons. */ + +/* Parse a PCI ID and fill an r300_capabilities struct with information. */ +void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) +{ + caps->pci_id = pci_id; + + /* Note: These are not ordered by PCI ID. I leave that task to GCC, + * which will perform the ordering while collating jump tables. Instead, + * I've tried to group them according to capabilities and age. */ + switch (pci_id) { + case 0x4144: + caps->family = CHIP_FAMILY_R300; + caps->num_pipes = 1; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x4145: + case 0x4146: + case 0x4147: + case 0x4E44: + case 0x4E45: + case 0x4E46: + case 0x4E47: + caps->family = CHIP_FAMILY_R300; + caps->num_pipes = 2; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x4150: + case 0x4151: + case 0x4152: + case 0x4153: + case 0x4154: + case 0x4155: + case 0x4156: + case 0x4E50: + case 0x4E51: + case 0x4E52: + case 0x4E53: + case 0x4E54: + case 0x4E56: + caps->family = CHIP_FAMILY_RV350; + caps->num_pipes = 1; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x4148: + case 0x4149: + case 0x414A: + case 0x414B: + case 0x4E48: + case 0x4E49: + case 0x4E4B: + caps->family = CHIP_FAMILY_R350; + caps->num_pipes = 2; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x4E4A: + caps->family = CHIP_FAMILY_R360; + caps->num_pipes = 2; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x5460: + case 0x5462: + case 0x5464: + case 0x5B60: + case 0x5B62: + case 0x5B63: + case 0x5B64: + case 0x5B65: + caps->family = CHIP_FAMILY_RV370; + caps->num_pipes = 1; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x3150: + case 0x3152: + case 0x3154: + case 0x3E50: + case 0x3E54: + caps->family = CHIP_FAMILY_RV380; + caps->num_pipes = 1; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x4A48: + case 0x4A49: + case 0x4A4A: + case 0x4A4B: + case 0x4A4C: + case 0x4A4D: + case 0x4A4E: + case 0x4A4F: + case 0x4A50: + case 0x4A54: + caps->family = CHIP_FAMILY_R420; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x5548: + case 0x5549: + case 0x554A: + case 0x554B: + case 0x5550: + case 0x5551: + case 0x5552: + case 0x5554: + case 0x5D57: + caps->family = CHIP_FAMILY_R423; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x554C: + case 0x554D: + case 0x554E: + case 0x554F: + case 0x5D48: + case 0x5D49: + case 0x5D4A: + caps->family = CHIP_FAMILY_R430; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x5D4C: + case 0x5D4D: + case 0x5D4E: + case 0x5D4F: + case 0x5D50: + case 0x5D52: + caps->family = CHIP_FAMILY_R480; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x4B49: + case 0x4B4A: + case 0x4B4B: + case 0x4B4C: + caps->family = CHIP_FAMILY_R481; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x5E4C: + case 0x5E4F: + case 0x564A: + case 0x564B: + case 0x564F: + case 0x5652: + case 0x5653: + case 0x5657: + case 0x5E48: + case 0x5E4A: + case 0x5E4B: + case 0x5E4D: + caps->family = CHIP_FAMILY_RV410; + caps->num_pipes = 1; + caps->has_tcl = TRUE; + caps->has_us = FALSE; + break; + + case 0x5954: + case 0x5955: + caps->family = CHIP_FAMILY_RS480; + caps->num_pipes = 1; /* CHECK ME */ + caps->has_tcl = FALSE; + caps->has_us = FALSE; + break; + + case 0x5974: + case 0x5975: + caps->family = CHIP_FAMILY_RS482; + caps->num_pipes = 1; /* CHECK ME */ + caps->has_tcl = FALSE; + caps->has_us = FALSE; + break; + + case 0x5A41: + case 0x5A42: + caps->family = CHIP_FAMILY_RS400; + caps->num_pipes = 1; /* CHECK ME */ + caps->has_tcl = FALSE; + caps->has_us = FALSE; + break; + + case 0x5A61: + case 0x5A62: + caps->family = CHIP_FAMILY_RC410; + caps->num_pipes = 1; /* CHECK ME */ + caps->has_tcl = FALSE; + caps->has_us = FALSE; + break; + + case 0x791E: + case 0x791F: + caps->family = CHIP_FAMILY_RS690; + caps->num_pipes = 1; /* CHECK ME */ + caps->has_tcl = FALSE; + caps->has_us = FALSE; /* CHECK ME */ + break; + + case 0x796C: + case 0x796D: + case 0x796E: + case 0x796F: + caps->family = CHIP_FAMILY_RS740; + caps->num_pipes = 1; /* CHECK ME */ + caps->has_tcl = FALSE; + caps->has_us = FALSE; /* CHECK ME */ + break; + + case 0x7100: + case 0x7101: + case 0x7102: + case 0x7103: + case 0x7104: + case 0x7105: + case 0x7106: + case 0x7108: + case 0x7109: + case 0x710A: + case 0x710B: + case 0x710C: + case 0x710E: + case 0x710F: + caps->family = CHIP_FAMILY_R520; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = TRUE; + break; + + case 0x7140: + case 0x7141: + case 0x7142: + case 0x7143: + case 0x7144: + case 0x7145: + case 0x7146: + case 0x7147: + case 0x7149: + case 0x714A: + case 0x714B: + case 0x714C: + case 0x714D: + case 0x714E: + case 0x714F: + case 0x7151: + case 0x7152: + case 0x7153: + case 0x715E: + case 0x715F: + case 0x7180: + case 0x7181: + case 0x7183: + case 0x7186: + case 0x7187: + case 0x7188: + case 0x718A: + case 0x718B: + case 0x718C: + case 0x718D: + case 0x718F: + case 0x7193: + case 0x7196: + case 0x719B: + case 0x719F: + case 0x7200: + case 0x7210: + case 0x7211: + caps->family = CHIP_FAMILY_RV515; + caps->num_pipes = 1; + caps->has_tcl = TRUE; + caps->has_us = TRUE; + break; + + case 0x71C0: + case 0x71C1: + case 0x71C2: + case 0x71C3: + case 0x71C4: + case 0x71C5: + case 0x71C6: + case 0x71C7: + case 0x71CD: + case 0x71CE: + case 0x71D2: + case 0x71D4: + case 0x71D5: + case 0x71D6: + case 0x71DA: + case 0x71DE: + caps->family = CHIP_FAMILY_RV530; + caps->num_pipes = 1; + caps->has_tcl = TRUE; + caps->has_us = TRUE; + break; + + case 0x7240: + case 0x7243: + case 0x7244: + case 0x7245: + case 0x7246: + case 0x7247: + case 0x7248: + case 0x7249: + case 0x724A: + case 0x724B: + case 0x724C: + case 0x724D: + case 0x724E: + case 0x724F: + case 0x7284: + caps->family = CHIP_FAMILY_R580; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = TRUE; + break; + + case 0x7280: + caps->family = CHIP_FAMILY_RV570; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = TRUE; + break; + + case 0x7281: + case 0x7283: + case 0x7287: + case 0x7288: + case 0x7289: + case 0x728B: + case 0x728C: + case 0x7290: + case 0x7291: + case 0x7293: + case 0x7297: + caps->family = CHIP_FAMILY_RV560; + caps->num_pipes = 4; + caps->has_tcl = TRUE; + caps->has_us = TRUE; + break; + + default: + /* XXX not an r300?! */ + assert(0); + break; + } +} diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h new file mode 100644 index 0000000000..98963db17e --- /dev/null +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -0,0 +1,100 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_CHIPSET_H +#define R300_CHIPSET_H + +#include "pipe/p_compiler.h" + +/* Structure containing all the possible information about a specific Radeon + * in the R3xx, R4xx, and R5xx families. */ +struct r300_capabilities { + /* PCI ID */ + uint32_t pci_id; + /* Chipset family */ + int family; + /* The number of Graphics Backend (GB) pipes */ + int num_pipes; + /* Whether or not TCL is physically present */ + boolean has_tcl; + /* Whether or not Universal Shaders (US) are used for fragment shaders */ + boolean has_us; +}; + +/* Enumeration for legibility and also telling which card we're running on. */ +enum { + CHIP_FAMILY_R300 = 0, + CHIP_FAMILY_R350, + CHIP_FAMILY_R360, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV370, + CHIP_FAMILY_RV380, + CHIP_FAMILY_R420, + CHIP_FAMILY_R423, + CHIP_FAMILY_R430, + CHIP_FAMILY_R480, + CHIP_FAMILY_R481, + CHIP_FAMILY_RV410, + CHIP_FAMILY_RS400, + CHIP_FAMILY_RC410, + CHIP_FAMILY_RS480, + CHIP_FAMILY_RS482, + CHIP_FAMILY_RS690, + CHIP_FAMILY_RS740, + CHIP_FAMILY_RV515, + CHIP_FAMILY_R520, + CHIP_FAMILY_RV530, + CHIP_FAMILY_R580, + CHIP_FAMILY_RV560, + CHIP_FAMILY_RV570 +}; + +static const char* chip_families[] = { + "R300", + "R350", + "R360", + "RV350", + "RV370", + "RV380", + "R420", + "R423", + "R430", + "R480", + "R481", + "RV410", + "RS400", + "RC410", + "RS480", + "RS482", + "RS690", + "RS740", + "RV515", + "R520", + "RV530", + "R580", + "RV560", + "RV570" +}; + +void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps); + +#endif /* R300_CHIPSET_H */ \ No newline at end of file diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 3c59a270b3..42096a9235 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -48,7 +48,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) if (r300->dirty_state & R300_NEW_BLEND_COLOR) { struct r300_blend_color_state* blend_color = r300->blend_color_state; - if (r300screen->is_r500) { + if (FALSE /*XXX*/) { /* XXX next two are contiguous regs */ OUT_CS_REG(R500_RB3D_CONSTANT_COLOR_AR, blend_color->blend_color_red_alpha); @@ -69,7 +69,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) OUT_CS_REG(R300_ZB_ZSTENCILCNTL, dsa->z_stencil_control); OUT_CS_REG(R300_ZB_STENCILREFMASK, dsa->stencil_ref_mask); OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top); - if (r300screen->is_r500) { + if (FALSE /*XXX*/) { OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); } } diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 5c1bab386f..c75ff9414b 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -71,12 +71,7 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) { return 0; case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: /* 12 == 2048x2048 */ - if (r300screen->is_r500) { - /* R500 can do 4096x4096 */ - return 13; - } else { - return 12; - } + return 12; case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* XXX educated guess */ return 8; @@ -142,21 +137,17 @@ static void r300_destroy_screen(struct pipe_screen* pscreen) { FREE(pscreen); } -struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint pci_id) { +struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint32_t pci_id) +{ struct r300_screen* r300screen = CALLOC_STRUCT(r300_screen); + struct r300_capabilities* caps = CALLOC_STRUCT(r300_capabilities); - if (!r300screen) + if (!r300screen || !caps) return NULL; - /* XXX break this into its own function? - switch (pci_id) { - default: - debug_printf("%s: unknown PCI ID 0x%x, cannot create screen!\n", - __FUNCTION__, pci_id); - return NULL; - } */ + r300_parse_chipset(pci_id, caps); - r300screen->pci_id = pci_id; + r300screen->caps = caps; r300screen->screen.winsys = winsys; r300screen->screen.destroy = r300_destroy_screen; r300screen->screen.get_name = r300_get_name; diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index a1b97f218e..b6c3d1f462 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -27,13 +27,14 @@ #include "pipe/p_screen.h" #include "util/u_memory.h" +#include "r300_chipset.h" + struct r300_screen { /* Parent class */ struct pipe_screen screen; - boolean is_r400; - boolean is_r500; - int pci_id; + /* Chipset capabilities */ + struct r300_capabilities* caps; }; /* Convenience cast wrapper. */ -- cgit v1.2.3 From 43f20357c8db2c90ae1f8360dbc2c71762a0478e Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 20 Jan 2009 01:11:08 -0800 Subject: r300: Use chip caps for something. Step two: Integration. Yay? Time to stop messing around with this and actually go do things. --- src/gallium/drivers/r300/r300_chipset.c | 54 ++++++--------------------------- src/gallium/drivers/r300/r300_chipset.h | 9 ++++-- src/gallium/drivers/r300/r300_emit.c | 4 +-- src/gallium/drivers/r300/r300_screen.c | 5 +-- 4 files changed, 20 insertions(+), 52 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index 926a9dda50..1dc9b8cf3c 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -28,7 +28,10 @@ /* Parse a PCI ID and fill an r300_capabilities struct with information. */ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) { + /* Reasonable defaults */ caps->pci_id = pci_id; + caps->has_tcl = TRUE; + caps->is_r500 = FALSE; /* Note: These are not ordered by PCI ID. I leave that task to GCC, * which will perform the ordering while collating jump tables. Instead, @@ -37,8 +40,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4144: caps->family = CHIP_FAMILY_R300; caps->num_pipes = 1; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x4145: @@ -50,8 +51,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4E47: caps->family = CHIP_FAMILY_R300; caps->num_pipes = 2; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x4150: @@ -69,8 +68,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4E56: caps->family = CHIP_FAMILY_RV350; caps->num_pipes = 1; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x4148: @@ -82,15 +79,11 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4E4B: caps->family = CHIP_FAMILY_R350; caps->num_pipes = 2; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x4E4A: caps->family = CHIP_FAMILY_R360; caps->num_pipes = 2; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x5460: @@ -103,8 +96,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5B65: caps->family = CHIP_FAMILY_RV370; caps->num_pipes = 1; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x3150: @@ -114,8 +105,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x3E54: caps->family = CHIP_FAMILY_RV380; caps->num_pipes = 1; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x4A48: @@ -130,8 +119,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4A54: caps->family = CHIP_FAMILY_R420; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x5548: @@ -145,8 +132,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5D57: caps->family = CHIP_FAMILY_R423; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x554C: @@ -158,8 +143,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5D4A: caps->family = CHIP_FAMILY_R430; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x5D4C: @@ -170,8 +153,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5D52: caps->family = CHIP_FAMILY_R480; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x4B49: @@ -180,8 +161,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4B4C: caps->family = CHIP_FAMILY_R481; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x5E4C: @@ -198,8 +177,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5E4D: caps->family = CHIP_FAMILY_RV410; caps->num_pipes = 1; - caps->has_tcl = TRUE; - caps->has_us = FALSE; break; case 0x5954: @@ -207,7 +184,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->family = CHIP_FAMILY_RS480; caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; - caps->has_us = FALSE; break; case 0x5974: @@ -215,7 +191,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->family = CHIP_FAMILY_RS482; caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; - caps->has_us = FALSE; break; case 0x5A41: @@ -223,7 +198,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->family = CHIP_FAMILY_RS400; caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; - caps->has_us = FALSE; break; case 0x5A61: @@ -231,7 +205,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->family = CHIP_FAMILY_RC410; caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; - caps->has_us = FALSE; break; case 0x791E: @@ -239,7 +212,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->family = CHIP_FAMILY_RS690; caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; - caps->has_us = FALSE; /* CHECK ME */ break; case 0x796C: @@ -249,7 +221,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->family = CHIP_FAMILY_RS740; caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; - caps->has_us = FALSE; /* CHECK ME */ break; case 0x7100: @@ -268,8 +239,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x710F: caps->family = CHIP_FAMILY_R520; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = TRUE; + caps->is_r500 = TRUE; break; case 0x7140: @@ -312,8 +282,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x7211: caps->family = CHIP_FAMILY_RV515; caps->num_pipes = 1; - caps->has_tcl = TRUE; - caps->has_us = TRUE; + caps->is_r500 = TRUE; break; case 0x71C0: @@ -334,8 +303,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x71DE: caps->family = CHIP_FAMILY_RV530; caps->num_pipes = 1; - caps->has_tcl = TRUE; - caps->has_us = TRUE; + caps->is_r500 = TRUE; break; case 0x7240: @@ -355,15 +323,13 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x7284: caps->family = CHIP_FAMILY_R580; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = TRUE; + caps->is_r500 = TRUE; break; case 0x7280: caps->family = CHIP_FAMILY_RV570; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = TRUE; + caps->is_r500 = TRUE; break; case 0x7281: @@ -379,13 +345,11 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x7297: caps->family = CHIP_FAMILY_RV560; caps->num_pipes = 4; - caps->has_tcl = TRUE; - caps->has_us = TRUE; + caps->is_r500 = TRUE; break; default: /* XXX not an r300?! */ - assert(0); break; } } diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h index 98963db17e..c2d7ad3414 100644 --- a/src/gallium/drivers/r300/r300_chipset.h +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -36,11 +36,14 @@ struct r300_capabilities { int num_pipes; /* Whether or not TCL is physically present */ boolean has_tcl; - /* Whether or not Universal Shaders (US) are used for fragment shaders */ - boolean has_us; + /* Whether or not this is an RV515 or newer; R500s have many features: + * - Extra bit on texture sizes + * - Blend color is split across two registers + * - Universal Shader (US) block used for fragment shaders */ + boolean is_r500; }; -/* Enumeration for legibility and also telling which card we're running on. */ +/* Enumerations for legibility and telling which card we're running on. */ enum { CHIP_FAMILY_R300 = 0, CHIP_FAMILY_R350, diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 42096a9235..bf6fd3224e 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -48,7 +48,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) if (r300->dirty_state & R300_NEW_BLEND_COLOR) { struct r300_blend_color_state* blend_color = r300->blend_color_state; - if (FALSE /*XXX*/) { + if (r300screen->caps->is_r500) { /* XXX next two are contiguous regs */ OUT_CS_REG(R500_RB3D_CONSTANT_COLOR_AR, blend_color->blend_color_red_alpha); @@ -69,7 +69,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) OUT_CS_REG(R300_ZB_ZSTENCILCNTL, dsa->z_stencil_control); OUT_CS_REG(R300_ZB_STENCILREFMASK, dsa->stencil_ref_mask); OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top); - if (FALSE /*XXX*/) { + if (r300screen->caps->is_r500) { OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); } } diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index c75ff9414b..7bba567e83 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -27,8 +27,9 @@ static const char* r300_get_vendor(struct pipe_screen* pscreen) { } static const char* r300_get_name(struct pipe_screen* pscreen) { - /* XXX lazy */ - return "unknown"; + struct r300_screen* r300screen = r300_screen(pscreen); + + return chip_families[r300screen->caps->family]; } static int r300_get_param(struct pipe_screen* pscreen, int param) { -- cgit v1.2.3 From 502ddfcd57ff7ed1f2dac9171f51c45893ea3d92 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 20 Jan 2009 01:49:34 -0800 Subject: r300: Add path for pci_id in winsys. Needs to be hooked up to the getparam from the kernel. --- src/gallium/drivers/r300/r300_context.c | 2 +- src/gallium/drivers/r300/r300_context.h | 1 + src/gallium/drivers/r300/r300_winsys.h | 3 +++ src/gallium/winsys/drm/amd/amd_context.c | 4 +++- src/gallium/winsys/drm/amd/amd_r300.c | 4 +++- src/gallium/winsys/drm/amd/amd_r300.h | 2 +- 6 files changed, 12 insertions(+), 4 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 798d6bdc6f..467594ec9b 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -43,7 +43,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->winsys = r300_winsys; r300->context.winsys = winsys; - r300->context.screen = r300_create_screen(winsys, 0x0); + r300->context.screen = r300_create_screen(winsys, r300_winsys->pci_id); r300->context.destroy = r300_destroy_context; diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index be6214b7ae..f4d801480a 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -28,6 +28,7 @@ #include "util/u_memory.h" #include "r300_screen.h" +#include "r300_winsys.h" struct r300_blend_state { uint32_t blend_control; /* R300_RB3D_CBLEND: 0x4e04 */ diff --git a/src/gallium/drivers/r300/r300_winsys.h b/src/gallium/drivers/r300/r300_winsys.h index 7711dc792d..319152c853 100644 --- a/src/gallium/drivers/r300/r300_winsys.h +++ b/src/gallium/drivers/r300/r300_winsys.h @@ -38,6 +38,9 @@ struct radeon_cs; struct r300_winsys { + /* PCI ID */ + uint32_t pci_id; + /* CS object. This is very much like Intel's batchbuffer. * Fill it full of dwords and relocs and then submit. * Repeat as needed. */ diff --git a/src/gallium/winsys/drm/amd/amd_context.c b/src/gallium/winsys/drm/amd/amd_context.c index 7784964867..53311684de 100644 --- a/src/gallium/winsys/drm/amd/amd_context.c +++ b/src/gallium/winsys/drm/amd/amd_context.c @@ -244,9 +244,11 @@ GLboolean amd_context_create(const __GLcontextModes *visual, if (GL_TRUE) { fprintf(stderr, "Creating r300 context..."); + /* XXX today we pretend to be a very lame R300 vvvvvv */ pipe = r300_create_context(NULL, amd_context->pipe_winsys, - amd_create_r300_winsys(amd_context->drm_fd)); + amd_create_r300_winsys(amd_context->drm_fd, + 0x4144)); } else { pipe = amd_create_softpipe(amd_context); } diff --git a/src/gallium/winsys/drm/amd/amd_r300.c b/src/gallium/winsys/drm/amd/amd_r300.c index 0f543df9e1..a7a70fdd7f 100644 --- a/src/gallium/winsys/drm/amd/amd_r300.c +++ b/src/gallium/winsys/drm/amd/amd_r300.c @@ -43,12 +43,14 @@ static void amd_r300_flush_cs(struct radeon_cs* cs) radeon_cs_erase(cs); } -struct r300_winsys* amd_create_r300_winsys(int fd) +struct r300_winsys* amd_create_r300_winsys(int fd, uint32_t pci_id) { struct r300_winsys* winsys = calloc(1, sizeof(struct r300_winsys)); struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); + winsys->pci_id = pci_id; + winsys->cs = radeon_cs_create(csm, 1024 * 64 / 4); winsys->check_cs = amd_r300_check_cs; diff --git a/src/gallium/winsys/drm/amd/amd_r300.h b/src/gallium/winsys/drm/amd/amd_r300.h index ef269454b3..0d229fe0c4 100644 --- a/src/gallium/winsys/drm/amd/amd_r300.h +++ b/src/gallium/winsys/drm/amd/amd_r300.h @@ -26,4 +26,4 @@ #include "amd_buffer.h" -struct r300_winsys* amd_create_r300_winsys(int fd); +struct r300_winsys* amd_create_r300_winsys(int fd, uint32_t pci_id); -- cgit v1.2.3 From 2b9ecaa6dd7d4282f1f8796d151bdda0390ab51f Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 20 Jan 2009 15:26:41 -0800 Subject: r300: Fix missing free(). --- src/gallium/drivers/r300/r300_screen.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 7bba567e83..04b5a7772b 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -135,7 +135,10 @@ static void r300_surface_unmap(struct pipe_screen* screen, } static void r300_destroy_screen(struct pipe_screen* pscreen) { - FREE(pscreen); + struct r300_screen* r300screen = r300_screen(pscreen); + + FREE(r300screen->caps); + FREE(r300screen); } struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint32_t pci_id) -- cgit v1.2.3 From 54d137e079b9420e8aca55f37307ece45e9b71d8 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 20 Jan 2009 15:27:46 -0800 Subject: r300: Fix indenting. --- src/gallium/drivers/r300/r300_screen.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 04b5a7772b..3cb61b4c4e 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -22,17 +22,20 @@ #include "r300_screen.h" -static const char* r300_get_vendor(struct pipe_screen* pscreen) { +static const char* r300_get_vendor(struct pipe_screen* pscreen) +{ return "X.Org R300 Project"; } -static const char* r300_get_name(struct pipe_screen* pscreen) { +static const char* r300_get_name(struct pipe_screen* pscreen) +{ struct r300_screen* r300screen = r300_screen(pscreen); return chip_families[r300screen->caps->family]; } -static int r300_get_param(struct pipe_screen* pscreen, int param) { +static int r300_get_param(struct pipe_screen* pscreen, int param) +{ struct r300_screen* r300screen = r300_screen(pscreen); switch (param) { @@ -87,7 +90,8 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) { } } -static float r300_get_paramf(struct pipe_screen* pscreen, int param) { +static float r300_get_paramf(struct pipe_screen* pscreen, int param) +{ switch (param) { case PIPE_CAP_MAX_LINE_WIDTH: case PIPE_CAP_MAX_LINE_WIDTH_AA: @@ -134,7 +138,8 @@ static void r300_surface_unmap(struct pipe_screen* screen, pipe_buffer_unmap(screen, surface->buffer); } -static void r300_destroy_screen(struct pipe_screen* pscreen) { +static void r300_destroy_screen(struct pipe_screen* pscreen) +{ struct r300_screen* r300screen = r300_screen(pscreen); FREE(r300screen->caps); -- cgit v1.2.3 From 8d1f386dcbdabaa4edf0301267f881e3831ad18a Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 20 Jan 2009 15:38:43 -0800 Subject: r300: Set floating-point params. Note: I took those numbers from classic Mesa. I know that points are routinely used to clear buffers, but line width is probably wrong. --- src/gallium/drivers/r300/r300_screen.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 3cb61b4c4e..a241d606c0 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -95,18 +95,21 @@ static float r300_get_paramf(struct pipe_screen* pscreen, int param) switch (param) { case PIPE_CAP_MAX_LINE_WIDTH: case PIPE_CAP_MAX_LINE_WIDTH_AA: - /* XXX look this up, lazy ass! */ - return 0.0; + /* XXX this is the biggest thing that will fit in that register. + * Perhaps the actual rendering limits are less? */ + return 10922.0f; case PIPE_CAP_MAX_POINT_WIDTH: case PIPE_CAP_MAX_POINT_WIDTH_AA: - /* XXX see above */ - return 255.0; + /* XXX this is the biggest thing that will fit in that register. + * Perhaps the actual rendering limits are less? */ + return 10922.0f; case PIPE_CAP_MAX_TEXTURE_ANISOTROPY: - return 16.0; + return 16.0f; case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: - return 16.0; + return 16.0f; default: - return 0.0; + /* XXX implementation error? */ + return 0.0f; } } -- cgit v1.2.3 From 6885560de54db26683eb813756e09fa3822c3492 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 20 Jan 2009 15:42:11 -0800 Subject: r300: Fix constness, compile warnings, indentation in r300_state. --- src/gallium/drivers/r300/r300_state.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index d73f4483db..3978ca12b3 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -274,8 +274,9 @@ static uint32_t translate_alpha_function(int alpha_func) { * This contains the depth buffer, stencil buffer, alpha test, and such. * On the Radeon, depth and stencil buffer setup are intertwined, which is * the reason for some of the strange-looking assignments across registers. */ -static void* r300_create_dsa_state(struct pipe_context* pipe, - struct pipe_depth_stencil_alpha_state* state) +static void* + r300_create_dsa_state(struct pipe_context* pipe, + const struct pipe_depth_stencil_alpha_state* state) { struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); @@ -341,7 +342,7 @@ static void* r300_create_dsa_state(struct pipe_context* pipe, /* Bind DSA state. */ static void r300_bind_dsa_state(struct pipe_context* pipe, - void* state) + void* state) { struct r300_context* r300 = r300_context(pipe); @@ -351,7 +352,7 @@ static void r300_bind_dsa_state(struct pipe_context* pipe, /* Free DSA state. */ static void r300_delete_dsa_state(struct pipe_context* pipe, - void* state) + void* state) { FREE(state); } @@ -396,7 +397,7 @@ struct pipe_rasterizer_state * In a not entirely unironic sidenote, this state has nearly nothing to do * with the actual block on the Radeon called the rasterizer (RS). */ static void* r300_create_rs_state(struct pipe_context* pipe, - struct pipe_rasterizer_state* state) + const struct pipe_rasterizer_state* state) { struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); @@ -457,7 +458,7 @@ static void r300_delete_rs_state(struct pipe_context* pipe, void* state) } static void r300_set_scissor_state(struct pipe_context* pipe, - struct pipe_scissor_state* state) + const struct pipe_scissor_state* state) { struct r300_context* r300 = r300_context(pipe); draw_flush(r300->draw); @@ -481,7 +482,7 @@ static void r300_set_scissor_state(struct pipe_context* pipe, } static void* r300_create_vs_state(struct pipe_context* pipe, - struct pipe_shader_state* state) + const struct pipe_shader_state* state) { struct r300_context* context = r300_context(pipe); /* XXX handing this off to Draw for now */ -- cgit v1.2.3 From 22877265f4fdf66c75df391d6de95bd5c1584ea3 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 21 Jan 2009 02:21:09 -0800 Subject: [BROKEN] r300: Add initial clear/fill code. Copied from mesa and still broken. Gimme a few to clean it up. --- src/gallium/drivers/r300/r300_cs.h | 24 ++- src/gallium/drivers/r300/r300_surface.c | 357 ++++++++++++++++++++++++++++++-- src/gallium/drivers/r300/r300_surface.h | 2 +- 3 files changed, 364 insertions(+), 19 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 3dacf25380..59ca985f40 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -26,6 +26,18 @@ #include "r300_reg.h" #include "r300_winsys.h" +/* Pack a 32-bit float into a dword. */ +static uint32_t pack_float_32(float f) +{ + union { + float f; + uint32_t u; + } u; + + u.f = f; + return u.u; +} + /* Yes, I know macros are ugly. However, they are much prettier than the code * that they neatly hide away, and don't have the cost of function setup,so * we're going to use them. */ @@ -47,7 +59,6 @@ struct r300_winsys* cs_winsys = context->winsys; \ struct radeon_cs* cs = cs_winsys->cs - #define CHECK_CS(size) \ cs_winsys->check_cs(cs, (size)) @@ -59,10 +70,19 @@ #define OUT_CS(value) \ cs_winsys->write_cs_dword(cs, value) +#define OUT_CS_32F(value) \ + cs_winsys->write_cs_dword(cs, pack_float_32(value)) + #define OUT_CS_REG(register, value) do { \ OUT_CS(CP_PACKET0(register, 0)); \ OUT_CS(value); } while (0) +/* Note: This expects count to be the number of registers, + * not the actual packet0 count! */ +#define OUT_CS_REG_SEQ(register, count) do { \ + OUT_CS(CP_PACKET0(register, ((count) - 1))); \ +} while (0) + #define OUT_CS_RELOC(bo, offset, rd, wd, flags) do { \ OUT_CS(offset); \ cs_winsys->write_cs_reloc(cs, bo, rd, wd, flags); \ @@ -74,4 +94,4 @@ #define FLUSH_CS \ cs_winsys->flush_cs(cs) -#endif /* R300_CS_H */ \ No newline at end of file +#endif /* R300_CS_H */ diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 4aa469b97e..60efe78c0b 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -22,29 +22,354 @@ #include "r300_surface.h" -/* Provides pipe_context's "surface_fill". */ -static void r300_surface_fill(struct pipe_context* context, +/* Provides pipe_context's "surface_fill". Commonly used for clearing + * buffers. */ +static void r300_surface_fill(struct pipe_context* pipe, struct pipe_surface* dest, unsigned x, unsigned y, unsigned w, unsigned h, unsigned color) { - /* Try accelerated fill first. */ - if (!r300_fill_blit(r300_context(context), - dest->block.size, - (short)dest->stride, - dest->buffer, - dest->offset, - (short)x, (short)y, - (short)w, (short)h, - color)) + struct r300_context* context = r300_context(pipe); + CS_LOCALS(context); + boolean has_tcl = FALSE; + boolean is_r500 = FALSE; + /* Emit a shitload of state, and then draw a point to clear the buffer. + * XXX it goes without saying that this needs to be cleaned up and + * shifted around to work with the rest of the driver's state handling. + */ + /* Sequence starting at R300_VAP_PROG_STREAM_CNTL_0 */ + OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 1); + if (has_tcl) { + OUT_CS(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << + R300_DATA_TYPE_0_SHIFT) | ((R300_LAST_VEC | (1 << + R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << + R300_DATA_TYPE_1_SHIFT))); + } else { + OUT_CS(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << + R300_DATA_TYPE_0_SHIFT) | ((R300_LAST_VEC | (2 << + R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << + R300_DATA_TYPE_1_SHIFT))); + } + + /* Disable fog */ + OUT_CS_REG(R300_FG_FOG_BLEND, 0); + OUT_CS_REG(R300_FG_ALPHA_FUNC, 0); + + OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, + ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | + (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | + (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | + R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << + R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE0_SHIFT) | + (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | + (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | + (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | + (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | + ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | + R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << + R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT))); + /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */ + OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2); + OUT_CS((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT)); + OUT_CS(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0); + + /* comes from fglrx startup of clear */ + OUT_CS_REG_SEQ(R300_SE_VTE_CNTL, 2); + OUT_CS(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA | + R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | + R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | + R300_VPORT_Z_OFFSET_ENA); + OUT_CS(0x8); + + OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); + + OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); + OUT_CS(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | + R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT); + OUT_CS(0); /* no textures */ + + OUT_CS_REG(R300_TX_ENABLE, 0); + + OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6); + OUT_CS_32F(1.0); + OUT_CS_32F(x); + OUT_CS_32F(1.0); + OUT_CS_32F(y); + OUT_CS_32F(1.0); + OUT_CS_32F(0.0); + + OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2); + OUT_CS(0x0); + OUT_CS(0x0); + + OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE); + + OUT_CS_REG(R300_GA_POINT_SIZE, ((w * 6) << R300_POINTSIZE_X_SHIFT) | + ((h * 6) << R300_POINTSIZE_Y_SHIFT)); + + if (is_r500) { + OUT_CS_REG_SEQ(R500_RS_IP_0, 8); + for (i = 0; i < 8; ++i) { + OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); + } + + OUT_CS_REG_SEQ(R300_RS_COUNT, 2); + /* XXX could hires be disabled for a speed boost? */ + OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_CS(0x0); + + OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); + } else { + OUT_CS_REG(R300_RS_IP_0, 8); + for (i = 0; i < 8; ++i) { + OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); + } + + OUT_CS_REG_SEQ(R300_RS_COUNT, 2); + /* XXX could hires be disabled for a speed boost? */ + OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_CS(0x0); + + OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE); + } + + if (is_r500) { + OUT_CS_REG_SEQ(R500_US_CONFIG, 2); + OUT_CS(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); + OUT_CS(0x0); + OUT_CS_REG_SEQ(R500_US_CODE_ADDR, 3); + OUT_CS(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); + OUT_CS(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); + OUT_CS(R500_US_CODE_OFFSET_ADDR(0)); + + OUT_CS_REG(R500_GA_US_VECTOR_INDEX, 0x0); + + OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_OUT | + R500_INST_TEX_SEM_WAIT | + R500_INST_LAST | + R500_INST_RGB_OMASK_R | + R500_INST_RGB_OMASK_G | + R500_INST_RGB_OMASK_B | + R500_INST_ALPHA_OMASK | + R500_INST_RGB_CLAMP | + R500_INST_ALPHA_CLAMP); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_RGB_ADDR0(0) | + R500_RGB_ADDR1(0) | + R500_RGB_ADDR1_CONST | + R500_RGB_ADDR2(0) | + R500_RGB_ADDR2_CONST); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR1(0) | + R500_ALPHA_ADDR1_CONST | + R500_ALPHA_ADDR2(0) | + R500_ALPHA_ADDR2_CONST); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC0 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_G | + R500_ALU_RGB_G_SWIZ_B_B); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_OP_CMP | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_A); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGBA_OP_CMP | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0); + + } else { + OUT_CS_REG_SEQ(R300_US_CONFIG, 3); + OUT_CS(0x0); + OUT_CS(0x0); + OUT_CS(0x0); + OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4); + OUT_CS(0x0); + OUT_CS(0x0); + OUT_CS(0x0); + OUT_CS(R300_RGBA_OUT); + + OUT_CS_REG(R300_US_ALU_RGB_INST_0, + FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); + OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, + FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); + OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, + FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); + OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, + FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); + } + + /* XXX */ + uint32_t vap_cntl; + OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); + if (has_tcl) { + vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | + (5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (12 << R300_VF_MAX_VTX_NUM_SHIFT)); + if (CHIP_FAMILY_RV515) + vap_cntl |= R500_TCL_STATE_OPTIMIZATION; + } else { + vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | + (5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (5 << R300_VF_MAX_VTX_NUM_SHIFT)); + } + + if (CHIP_FAMILY_RV515) + vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); + else if ((CHIP_FAMILY_RV530) || + (CHIP_FAMILY_RV560) || + (CHIP_FAMILY_RV570)) + vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); + else if ((CHIP_FAMILY_RV410) || + (CHIP_FAMILY_R420)) + vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); + else if ((CHIP_FAMILY_R520) || + (CHIP_FAMILY_R580)) + vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); + else + vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); + + OUT_CS_REG(R300_VAP_CNTL, vap_cntl); + + if (has_tcl) { + OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3); + OUT_CS((0 << R300_PVS_FIRST_INST_SHIFT) | + (0 << R300_PVS_XYZW_VALID_INST_SHIFT) | + (1 << R300_PVS_LAST_INST_SHIFT)); + OUT_CS((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | + (0 << R300_PVS_MAX_CONST_ADDR_SHIFT)); + OUT_CS(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT); + + OUT_CS_REG(R300_SC_SCREENDOOR, 0x0); + OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 28)); + OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); + OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_ADDRESS, 0x0); + + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, + 0, 0xf, PVS_DST_REG_OUT)); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, + PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, + PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); + + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, + PVS_DST_REG_OUT)); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, + PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, + PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, + VSF_FLAG_NONE)); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_SELECT_FORCE_0, + PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); + } + /* Do the actual emit. */ + if (rrb) { + cbpitch = (rrb->pitch / rrb->cpp); + if (rrb->cpp == 4) + cbpitch |= R300_COLOR_FORMAT_ARGB8888; + else + cbpitch |= R300_COLOR_FORMAT_RGB565; + + if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ + cbpitch |= R300_COLOR_TILE_ENABLE; + } + } + + /* TODO in bufmgr */ + cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); + end_3d(rmesa); + + if (flags & CLEARBUFFER_COLOR) { + assert(rrb != 0); + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); + OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); + END_BATCH(); + } +#if 0 + if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) { + assert(rrbd != 0); + cbpitch = (rrbd->pitch / rrbd->cpp); + if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ + cbpitch |= R300_DEPTHMACROTILE_ENABLE; + } + if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ + cbpitch |= R300_DEPTHMICROTILE_TILED; + } + BEGIN_BATCH_NO_AUTOSTATE(4); + OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); + OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); + END_BATCH(); + } + { - /* Fallback. */ - void* dest_map = context->screen->surface_map(context->screen, dest, - PIPE_BUFFER_USAGE_CPU_WRITE); - pipe_fill_rect(dest_map, &dest->block, dest->stride, x, y, w, h, color); - context->screen->surface_unmap(context->screen, dest); + uint32_t t1, t2; + + t1 = 0x0; + t2 = 0x0; + + if (flags & CLEARBUFFER_DEPTH) { + t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE; + t2 |= + (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT); + } + + if (flags & CLEARBUFFER_STENCIL) { + t1 |= R300_STENCIL_ENABLE; + t2 |= + (R300_ZS_ALWAYS << + R300_S_FRONT_FUNC_SHIFT) | + (R300_ZS_REPLACE << + R300_S_FRONT_SFAIL_OP_SHIFT) | + (R300_ZS_REPLACE << + R300_S_FRONT_ZPASS_OP_SHIFT) | + (R300_ZS_REPLACE << + R300_S_FRONT_ZFAIL_OP_SHIFT); + } + + OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); + OUT_BATCH(t1); + OUT_BATCH(t2); + OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << + R300_STENCILWRITEMASK_SHIFT) | + (ctx->Stencil.Clear & R300_STENCILREF_MASK)); + END_BATCH(); } +#endif + + OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); + OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | + (1 << R300_PRIM_NUM_VERTICES_SHIFT)); + OUT_CS_32F(w / 2.0); + OUT_CS_32F(h / 2.0); + /* XXX this should be the depth value to clear to */ + OUT_CS_32F(1.0); + OUT_CS_32F(1.0); + OUT_CS_32F(color); + OUT_CS_32F(color); + OUT_CS_32F(color); + OUT_CS_32F(color); + + /* XXX cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN); */ } void r300_init_surface_functions(struct r300_context* r300) diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index 0b2fd0b32b..e807edd0e3 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -28,7 +28,7 @@ #include "util/u_rect.h" -#include "r300_blit.h" #include "r300_context.h" +#include "r300_cs.h" #endif /* R300_SURFACE_H */ -- cgit v1.2.3 From 7d63ff93cbf0f342c3736f4c8fae75157a62f0ea Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 21 Jan 2009 23:12:40 -0800 Subject: r300: Unbreak build, finish clear state. Completely untested, of course. --- src/gallium/drivers/r300/r300_reg.h | 12 +++++++++ src/gallium/drivers/r300/r300_surface.c | 43 +++++++++++++-------------------- src/gallium/drivers/r300/r300_surface.h | 3 +++ 3 files changed, 32 insertions(+), 26 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index 8b3fe431ab..7f4a508b1b 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -3252,6 +3252,18 @@ enum { */ #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 +/* XXX Corbin's stuff from radeon and r200 */ + +#define RADEON_WAIT_UNTIL 0x1720 +# define RADEON_WAIT_CRTC_PFLIP (1 << 0) +# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) +# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) +# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) + +#define RADEON_CP_PACKET3 0xC0000000 + +#define R200_3D_DRAW_IMMD_2 0xC0003500 + #endif /* _R300_REG_H */ /* *INDENT-ON* */ diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 60efe78c0b..8a507d56e6 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -34,6 +34,8 @@ static void r300_surface_fill(struct pipe_context* pipe, CS_LOCALS(context); boolean has_tcl = FALSE; boolean is_r500 = FALSE; + /* For the for loops. */ + int i; /* Emit a shitload of state, and then draw a point to clear the buffer. * XXX it goes without saying that this needs to be cleaned up and * shifted around to work with the rest of the driver's state handling. @@ -239,6 +241,7 @@ static void r300_surface_fill(struct pipe_context* pipe, OUT_CS_REG(R300_VAP_CNTL, vap_cntl); + /* XXX unbreak this if (has_tcl) { OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3); OUT_CS((0 << R300_PVS_FIRST_INST_SHIFT) | @@ -252,7 +255,7 @@ static void r300_surface_fill(struct pipe_context* pipe, OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 28)); OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_ADDRESS, 0x0); + OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_CODE_START); OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 0, 0xf, PVS_DST_REG_OUT)); @@ -278,32 +281,17 @@ static void r300_surface_fill(struct pipe_context* pipe, PVS_SRC_SELECT_FORCE_0, PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); - } - /* Do the actual emit. */ - if (rrb) { - cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->cpp == 4) - cbpitch |= R300_COLOR_FORMAT_ARGB8888; - else - cbpitch |= R300_COLOR_FORMAT_RGB565; - - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ - cbpitch |= R300_COLOR_TILE_ENABLE; - } - } + } */ /* TODO in bufmgr */ - cp_wait(r300, R300_WAIT_3D | R300_WAIT_3D_CLEAN); - end_3d(rmesa); - - if (flags & CLEARBUFFER_COLOR) { - assert(rrb != 0); - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGVAL(R300_RB3D_COLORPITCH0, cbpitch); - END_BATCH(); - } + /* XXX this should be split off, also figure out WTF with the numbers */ + OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); + /* XXX might have to switch to 2D */ + + OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); + OUT_CS_RELOC(0, dest->buffer, 0, RADEON_GEM_DOMAIN_VRAM, 0); + /* XXX this needs more TLC (or TCL, as it were) */ + OUT_CS_REG(R300_RB3D_COLORPITCH0, R300_COLOR_FORMAT_ARGB8888); #if 0 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) { assert(rrbd != 0); @@ -369,7 +357,10 @@ static void r300_surface_fill(struct pipe_context* pipe, OUT_CS_32F(color); OUT_CS_32F(color); - /* XXX cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN); */ + /* XXX this should be split off, also figure out WTF with the numbers */ + OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); + + FLUSH_CS; } void r300_init_surface_functions(struct r300_context* r300) diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index e807edd0e3..2d64a95412 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -31,4 +31,7 @@ #include "r300_context.h" #include "r300_cs.h" +/* XXX integrate this into r300_reg */ +#include "r300_fragprog.h" + #endif /* R300_SURFACE_H */ -- cgit v1.2.3 From 0ff7cb7c89f0c9ac4e363296e53eada008717252 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 21 Jan 2009 23:48:47 -0800 Subject: r300: Add num_vert_pipes (and remove busted num_pipes.) --- src/gallium/drivers/r300/r300_chipset.c | 39 ++++++++++++--------------------- src/gallium/drivers/r300/r300_chipset.h | 8 ++++--- src/gallium/drivers/r300/r300_cs.h | 3 +++ src/gallium/drivers/r300/r300_surface.c | 27 ++++++++--------------- 4 files changed, 31 insertions(+), 46 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index 1dc9b8cf3c..b7de2359cb 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -32,6 +32,8 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) caps->pci_id = pci_id; caps->has_tcl = TRUE; caps->is_r500 = FALSE; + caps->num_vert_pipes = 4; + /* Note: These are not ordered by PCI ID. I leave that task to GCC, * which will perform the ordering while collating jump tables. Instead, @@ -39,7 +41,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) switch (pci_id) { case 0x4144: caps->family = CHIP_FAMILY_R300; - caps->num_pipes = 1; break; case 0x4145: @@ -50,7 +51,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4E46: case 0x4E47: caps->family = CHIP_FAMILY_R300; - caps->num_pipes = 2; break; case 0x4150: @@ -67,7 +67,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4E54: case 0x4E56: caps->family = CHIP_FAMILY_RV350; - caps->num_pipes = 1; break; case 0x4148: @@ -78,12 +77,10 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4E49: case 0x4E4B: caps->family = CHIP_FAMILY_R350; - caps->num_pipes = 2; break; case 0x4E4A: caps->family = CHIP_FAMILY_R360; - caps->num_pipes = 2; break; case 0x5460: @@ -95,7 +92,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5B64: case 0x5B65: caps->family = CHIP_FAMILY_RV370; - caps->num_pipes = 1; break; case 0x3150: @@ -104,7 +100,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x3E50: case 0x3E54: caps->family = CHIP_FAMILY_RV380; - caps->num_pipes = 1; break; case 0x4A48: @@ -118,7 +113,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4A50: case 0x4A54: caps->family = CHIP_FAMILY_R420; - caps->num_pipes = 4; + caps->num_vert_pipes = 6; break; case 0x5548: @@ -131,7 +126,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5554: case 0x5D57: caps->family = CHIP_FAMILY_R423; - caps->num_pipes = 4; + caps->num_vert_pipes = 6; break; case 0x554C: @@ -142,7 +137,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5D49: case 0x5D4A: caps->family = CHIP_FAMILY_R430; - caps->num_pipes = 4; + caps->num_vert_pipes = 6; break; case 0x5D4C: @@ -152,7 +147,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5D50: case 0x5D52: caps->family = CHIP_FAMILY_R480; - caps->num_pipes = 4; + caps->num_vert_pipes = 6; break; case 0x4B49: @@ -160,7 +155,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x4B4B: case 0x4B4C: caps->family = CHIP_FAMILY_R481; - caps->num_pipes = 4; + caps->num_vert_pipes = 6; break; case 0x5E4C: @@ -176,41 +171,36 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x5E4B: case 0x5E4D: caps->family = CHIP_FAMILY_RV410; - caps->num_pipes = 1; + caps->num_vert_pipes = 6; break; case 0x5954: case 0x5955: caps->family = CHIP_FAMILY_RS480; - caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; break; case 0x5974: case 0x5975: caps->family = CHIP_FAMILY_RS482; - caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; break; case 0x5A41: case 0x5A42: caps->family = CHIP_FAMILY_RS400; - caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; break; case 0x5A61: case 0x5A62: caps->family = CHIP_FAMILY_RC410; - caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; break; case 0x791E: case 0x791F: caps->family = CHIP_FAMILY_RS690; - caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; break; @@ -219,7 +209,6 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x796E: case 0x796F: caps->family = CHIP_FAMILY_RS740; - caps->num_pipes = 1; /* CHECK ME */ caps->has_tcl = FALSE; break; @@ -238,7 +227,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x710E: case 0x710F: caps->family = CHIP_FAMILY_R520; - caps->num_pipes = 4; + caps->num_vert_pipes = 8; caps->is_r500 = TRUE; break; @@ -281,7 +270,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x7210: case 0x7211: caps->family = CHIP_FAMILY_RV515; - caps->num_pipes = 1; + caps->num_vert_pipes = 2; caps->is_r500 = TRUE; break; @@ -302,7 +291,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x71DA: case 0x71DE: caps->family = CHIP_FAMILY_RV530; - caps->num_pipes = 1; + caps->num_vert_pipes = 5; caps->is_r500 = TRUE; break; @@ -322,13 +311,13 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x724F: case 0x7284: caps->family = CHIP_FAMILY_R580; - caps->num_pipes = 4; + caps->num_vert_pipes = 8; caps->is_r500 = TRUE; break; case 0x7280: caps->family = CHIP_FAMILY_RV570; - caps->num_pipes = 4; + caps->num_vert_pipes = 5; caps->is_r500 = TRUE; break; @@ -344,7 +333,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) case 0x7293: case 0x7297: caps->family = CHIP_FAMILY_RV560; - caps->num_pipes = 4; + caps->num_vert_pipes = 5; caps->is_r500 = TRUE; break; diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h index c2d7ad3414..548d7a6c50 100644 --- a/src/gallium/drivers/r300/r300_chipset.h +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -32,8 +32,10 @@ struct r300_capabilities { uint32_t pci_id; /* Chipset family */ int family; - /* The number of Graphics Backend (GB) pipes */ - int num_pipes; + /* The number of vertex pipes */ + int num_vert_pipes; + /* The number of fragment pipes */ + int num_frag_pipes; /* Whether or not TCL is physically present */ boolean has_tcl; /* Whether or not this is an RV515 or newer; R500s have many features: @@ -100,4 +102,4 @@ static const char* chip_families[] = { void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps); -#endif /* R300_CHIPSET_H */ \ No newline at end of file +#endif /* R300_CHIPSET_H */ diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 59ca985f40..67cb5ee7d1 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -55,6 +55,9 @@ static uint32_t pack_float_32(float f) #define CP_PACKET0(register, count) \ (RADEON_CP_PACKET0 | ((count) << 16) | ((register) >> 2)) +#define CP_PACKET3(op, count) \ + (RADEON_CP_PACKET3 | (op) | ((count) << 16)) + #define CS_LOCALS(context) \ struct r300_winsys* cs_winsys = context->winsys; \ struct radeon_cs* cs = cs_winsys->cs diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 8a507d56e6..dd1c8862a7 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -30,10 +30,11 @@ static void r300_surface_fill(struct pipe_context* pipe, unsigned w, unsigned h, unsigned color) { - struct r300_context* context = r300_context(pipe); - CS_LOCALS(context); - boolean has_tcl = FALSE; - boolean is_r500 = FALSE; + struct r300_context* r300 = r300_context(pipe); + CS_LOCALS(r300); + struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps; + boolean has_tcl = caps->has_tcl; + boolean is_r500 = caps->is_r500; /* For the for loops. */ int i; /* Emit a shitload of state, and then draw a point to clear the buffer. @@ -224,20 +225,8 @@ static void r300_surface_fill(struct pipe_context* pipe, (5 << R300_VF_MAX_VTX_NUM_SHIFT)); } - if (CHIP_FAMILY_RV515) - vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); - else if ((CHIP_FAMILY_RV530) || - (CHIP_FAMILY_RV560) || - (CHIP_FAMILY_RV570)) - vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); - else if ((CHIP_FAMILY_RV410) || - (CHIP_FAMILY_R420)) - vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); - else if ((CHIP_FAMILY_R520) || - (CHIP_FAMILY_R580)) - vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); - else - vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); + vap_cntl |= (caps->num_vert_pipes << + R300_PVS_NUM_FPUS_SHIFT); OUT_CS_REG(R300_VAP_CNTL, vap_cntl); @@ -361,6 +350,8 @@ static void r300_surface_fill(struct pipe_context* pipe, OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); FLUSH_CS; + + r300->dirty_state = R300_NEW_KITCHEN_SINK; } void r300_init_surface_functions(struct r300_context* r300) -- cgit v1.2.3 From 90a96cb2addf48b3b48c039a8dc6de9e53bfb6df Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 22 Jan 2009 03:45:14 -0800 Subject: r300: Add sampler state skeleton. Heh, serendipitous sibilance. Anyway, need to flesh this out. --- src/gallium/drivers/r300/r300_context.h | 20 +++++++++----- src/gallium/drivers/r300/r300_state.c | 47 ++++++++++++++++++++++++++++++--- 2 files changed, 56 insertions(+), 11 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index f4d801480a..3877c9855d 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -65,17 +65,21 @@ struct r300_rs_state { uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ }; +struct r300_sampler_state { +}; + struct r300_scissor_state { uint32_t scissor_top_left; /* R300_SC_SCISSORS_TL: 0x43e0 */ uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ }; -#define R300_NEW_BLEND 0x01 -#define R300_NEW_BLEND_COLOR 0x02 -#define R300_NEW_DSA 0x04 -#define R300_NEW_RS 0x08 -#define R300_NEW_SCISSOR 0x10 -#define R300_NEW_KITCHEN_SINK 0x1f +#define R300_NEW_BLEND 0x0001 +#define R300_NEW_BLEND_COLOR 0x0002 +#define R300_NEW_DSA 0x0004 +#define R300_NEW_RS 0x0008 +#define R300_NEW_SAMPLER 0x0010 +#define R300_NEW_SCISSOR 0x1000 +#define R300_NEW_KITCHEN_SINK 0x1fff struct r300_context { /* Parent class */ @@ -95,9 +99,11 @@ struct r300_context { struct r300_dsa_state* dsa_state; /* Rasterizer state. */ struct r300_rs_state* rs_state; + /* Sampler states. */ + struct r300_sampler_state* sampler_states[8]; + int sampler_count; /* Scissor state. */ struct r300_scissor_state* scissor_state; - /* Bitmask of dirty state objects. */ uint32_t dirty_state; /* Flag indicating whether or not the HW is dirty. */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 3978ca12b3..7fb0fc2eba 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -457,6 +457,41 @@ static void r300_delete_rs_state(struct pipe_context* pipe, void* state) FREE(state); } +static void* + r300_create_sampler_state(struct pipe_context* pipe, + const struct pipe_sampler_state* state) +{ + struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); + + return (void*)sampler; +} + +static void r300_bind_sampler_states(struct pipe_context* pipe, + unsigned count, + void** states) +{ + struct r300_context* r300 = r300_context(pipe); + int i = 0; + + if (count > 8) { + return; + } + + for (i; i < count; i++) { + if (r300->sampler_states[i] != states[i]) { + r300->sampler_states[i] = states[i]; + r300->dirty_state |= (R300_NEW_SAMPLER << i); + } + } + + r300->sampler_count = count; +} + +static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) +{ + FREE(state); +} + static void r300_set_scissor_state(struct pipe_context* pipe, const struct pipe_scissor_state* state) { @@ -510,17 +545,21 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.set_blend_color = r300_set_blend_color; + r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; + r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; + r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; + r300->context.create_rasterizer_state = r300_create_rs_state; r300->context.bind_rasterizer_state = r300_bind_rs_state; r300->context.delete_rasterizer_state = r300_delete_rs_state; - r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; - r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; - r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; + r300->context.create_sampler_state = r300_create_sampler_state; + r300->context.bind_sampler_states = r300_bind_sampler_states; + r300->context.delete_sampler_state = r300_delete_sampler_state; r300->context.set_scissor_state = r300_set_scissor_state; r300->context.create_vs_state = r300_create_vs_state; r300->context.bind_vs_state = r300_bind_vs_state; r300->context.delete_vs_state = r300_delete_vs_state; -} \ No newline at end of file +} -- cgit v1.2.3 From ecb7f29f74c8f7456302267fe31b1de4bcc103c5 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 22 Jan 2009 13:34:21 -0800 Subject: amd/r300: Wire up GETPARAM ioctls. Whoo, stuff is starting to look cleaner and cleaner. --- src/gallium/drivers/r300/r300_chipset.c | 5 ++--- src/gallium/drivers/r300/r300_chipset.h | 2 +- src/gallium/drivers/r300/r300_context.c | 2 +- src/gallium/drivers/r300/r300_screen.c | 8 +++++-- src/gallium/drivers/r300/r300_screen.h | 4 +++- src/gallium/drivers/r300/r300_winsys.h | 5 ++++- src/gallium/winsys/drm/amd/amd_context.c | 9 ++++---- src/gallium/winsys/drm/amd/amd_r300.c | 38 +++++++++++++++++++++++++++++--- src/gallium/winsys/drm/amd/amd_r300.h | 7 +++++- 9 files changed, 62 insertions(+), 18 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index b7de2359cb..f2dc8aedaa 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -26,10 +26,9 @@ * Radeons. */ /* Parse a PCI ID and fill an r300_capabilities struct with information. */ -void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) +void r300_parse_chipset(struct r300_capabilities* caps) { /* Reasonable defaults */ - caps->pci_id = pci_id; caps->has_tcl = TRUE; caps->is_r500 = FALSE; caps->num_vert_pipes = 4; @@ -38,7 +37,7 @@ void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps) /* Note: These are not ordered by PCI ID. I leave that task to GCC, * which will perform the ordering while collating jump tables. Instead, * I've tried to group them according to capabilities and age. */ - switch (pci_id) { + switch (caps->pci_id) { case 0x4144: caps->family = CHIP_FAMILY_R300; break; diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h index 548d7a6c50..f1502ff76c 100644 --- a/src/gallium/drivers/r300/r300_chipset.h +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -100,6 +100,6 @@ static const char* chip_families[] = { "RV570" }; -void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps); +void r300_parse_chipset(struct r300_capabilities* caps); #endif /* R300_CHIPSET_H */ diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 467594ec9b..f254b2f2a3 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -43,7 +43,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->winsys = r300_winsys; r300->context.winsys = winsys; - r300->context.screen = r300_create_screen(winsys, r300_winsys->pci_id); + r300->context.screen = r300_create_screen(winsys, r300_winsys); r300->context.destroy = r300_destroy_context; diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index a241d606c0..63ddd3b6a6 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -149,7 +149,8 @@ static void r300_destroy_screen(struct pipe_screen* pscreen) FREE(r300screen); } -struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint32_t pci_id) +struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, + struct r300_winsys* r300_winsys) { struct r300_screen* r300screen = CALLOC_STRUCT(r300_screen); struct r300_capabilities* caps = CALLOC_STRUCT(r300_capabilities); @@ -157,7 +158,10 @@ struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint32_t pci_ if (!r300screen || !caps) return NULL; - r300_parse_chipset(pci_id, caps); + caps->pci_id = r300_winsys->pci_id; + caps->num_frag_pipes = r300_winsys->gb_pipes; + + r300_parse_chipset(caps); r300screen->caps = caps; r300screen->screen.winsys = winsys; diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index b6c3d1f462..83d5a75d0a 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -28,6 +28,7 @@ #include "util/u_memory.h" #include "r300_chipset.h" +#include "r300_winsys.h" struct r300_screen { /* Parent class */ @@ -43,6 +44,7 @@ static struct r300_screen* r300_screen(struct pipe_screen* screen) { } /* Creates a new r300 screen. */ -struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, uint pci_id); +struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, + struct r300_winsys* r300_winsys); #endif /* R300_SCREEN_H */ diff --git a/src/gallium/drivers/r300/r300_winsys.h b/src/gallium/drivers/r300/r300_winsys.h index 319152c853..867d65b7de 100644 --- a/src/gallium/drivers/r300/r300_winsys.h +++ b/src/gallium/drivers/r300/r300_winsys.h @@ -41,6 +41,9 @@ struct r300_winsys { /* PCI ID */ uint32_t pci_id; + /* GB pipe count */ + uint32_t gb_pipes; + /* CS object. This is very much like Intel's batchbuffer. * Fill it full of dwords and relocs and then submit. * Repeat as needed. */ @@ -89,4 +92,4 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, } #endif -#endif /* R300_WINSYS_H */ \ No newline at end of file +#endif /* R300_WINSYS_H */ diff --git a/src/gallium/winsys/drm/amd/amd_context.c b/src/gallium/winsys/drm/amd/amd_context.c index 53311684de..7a486c93a5 100644 --- a/src/gallium/winsys/drm/amd/amd_context.c +++ b/src/gallium/winsys/drm/amd/amd_context.c @@ -244,11 +244,10 @@ GLboolean amd_context_create(const __GLcontextModes *visual, if (GL_TRUE) { fprintf(stderr, "Creating r300 context..."); - /* XXX today we pretend to be a very lame R300 vvvvvv */ - pipe = r300_create_context(NULL, - amd_context->pipe_winsys, - amd_create_r300_winsys(amd_context->drm_fd, - 0x4144)); + pipe = + r300_create_context(NULL, + amd_context->pipe_winsys, + amd_create_r300_winsys(amd_context->drm_fd)); } else { pipe = amd_create_softpipe(amd_context); } diff --git a/src/gallium/winsys/drm/amd/amd_r300.c b/src/gallium/winsys/drm/amd/amd_r300.c index a7a70fdd7f..04295e8281 100644 --- a/src/gallium/winsys/drm/amd/amd_r300.c +++ b/src/gallium/winsys/drm/amd/amd_r300.c @@ -43,13 +43,45 @@ static void amd_r300_flush_cs(struct radeon_cs* cs) radeon_cs_erase(cs); } -struct r300_winsys* amd_create_r300_winsys(int fd, uint32_t pci_id) +/* Helper function to do the ioctls needed for setup and init. */ +static void do_ioctls(struct r300_winsys* winsys, int fd) +{ + drm_radeon_getparam_t gp; + uint32_t target; + int retval; + + /* XXX is this cast safe? */ + gp.value = (int*)⌖ + + /* First, get PCI ID */ + gp.param = RADEON_PARAM_DEVICE_ID; + retval = drmCommandWriteRead(fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + if (retval) { + fprintf(stderr, "%s: Failed to get PCI ID, error number %d", + __FUNCTION__, retval); + exit(1); + } + winsys->pci_id = target; + + /* Then, get the number of pixel pipes */ + gp.param = RADEON_PARAM_NUM_GB_PIPES; + retval = drmCommandWriteRead(fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); + if (retval) { + fprintf(stderr, "%s: Failed to get GB pipe count, error number %d", + __FUNCTION__, retval); + exit(1); + } + winsys->gb_pipes = target; + +} + +struct r300_winsys* amd_create_r300_winsys(int fd) { struct r300_winsys* winsys = calloc(1, sizeof(struct r300_winsys)); - struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); + do_ioctls(winsys, fd); - winsys->pci_id = pci_id; + struct radeon_cs_manager* csm = radeon_cs_manager_gem_ctor(fd); winsys->cs = radeon_cs_create(csm, 1024 * 64 / 4); diff --git a/src/gallium/winsys/drm/amd/amd_r300.h b/src/gallium/winsys/drm/amd/amd_r300.h index 0d229fe0c4..d80c23594c 100644 --- a/src/gallium/winsys/drm/amd/amd_r300.h +++ b/src/gallium/winsys/drm/amd/amd_r300.h @@ -20,10 +20,15 @@ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. */ +/* XXX WTF is this! I shouldn't have to include those first three! FUCK! */ +#include +#include +#include "drm.h" +#include "radeon_drm.h" #include "radeon_cs.h" #include "r300_winsys.h" #include "amd_buffer.h" -struct r300_winsys* amd_create_r300_winsys(int fd, uint32_t pci_id); +struct r300_winsys* amd_create_r300_winsys(int fd); -- cgit v1.2.3 From 0648bc9f65f1c6700b442e57ac0e82404fb60c2d Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 22 Jan 2009 16:51:34 -0800 Subject: r300: Add texture stubs. --- src/gallium/drivers/r300/Makefile | 3 ++- src/gallium/drivers/r300/r300_screen.c | 23 ++++++++++++++++++++++ src/gallium/drivers/r300/r300_screen.h | 1 + src/gallium/drivers/r300/r300_texture.c | 35 +++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_texture.h | 33 +++++++++++++++++++++++++++++++ 5 files changed, 94 insertions(+), 1 deletion(-) create mode 100644 src/gallium/drivers/r300/r300_texture.c create mode 100644 src/gallium/drivers/r300/r300_texture.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index ad792e9aa8..f1b1a615b8 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -11,7 +11,8 @@ C_SOURCES = \ r300_emit.c \ r300_screen.c \ r300_state.c \ - r300_surface.c + r300_surface.c \ + r300_texture.c include ../../Makefile.template diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 63ddd3b6a6..2b83ae060c 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -113,12 +113,33 @@ static float r300_get_paramf(struct pipe_screen* pscreen, int param) } } +/* XXX moar formats */ +static boolean check_tex_2d_format(enum pipe_format format) +{ + switch (format) { + case PIPE_FORMAT_I8_UNORM: + return TRUE; + default: + break; + } + + return FALSE; +} + +/* XXX moar targets */ static boolean r300_is_format_supported(struct pipe_screen* pscreen, enum pipe_format format, enum pipe_texture_target target, unsigned tex_usage, unsigned geom_flags) { + switch (target) { + case PIPE_TEXTURE_2D: + return check_tex_2d_format(format); + default: + break; + } + return FALSE; } @@ -174,5 +195,7 @@ struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, r300screen->screen.surface_map = r300_surface_map; r300screen->screen.surface_unmap = r300_surface_unmap; + r300_init_screen_texture_functions(&r300screen->screen); + return &r300screen->screen; } diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index 83d5a75d0a..b45ce5e8c6 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -28,6 +28,7 @@ #include "util/u_memory.h" #include "r300_chipset.h" +#include "r300_texture.h" #include "r300_winsys.h" struct r300_screen { diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c new file mode 100644 index 0000000000..30d9e64b4c --- /dev/null +++ b/src/gallium/drivers/r300/r300_texture.c @@ -0,0 +1,35 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "r300_texture.h" + +/* Create a new texture. */ +static struct pipe_texture* + r300_texture_create(struct pipe_screen* screen, + const struct pipe_texture* template) +{ +} + +void r300_init_screen_texture_functions(struct pipe_screen* screen) +{ + screen->texture_create = r300_texture_create; +} diff --git a/src/gallium/drivers/r300/r300_texture.h b/src/gallium/drivers/r300/r300_texture.h new file mode 100644 index 0000000000..9d14cf81a6 --- /dev/null +++ b/src/gallium/drivers/r300/r300_texture.h @@ -0,0 +1,33 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_TEXTURE_H +#define R300_TEXTURE_H + +#include "pipe/p_screen.h" + +struct r300_texture { +}; + +void r300_init_screen_texture_functions(struct pipe_screen* screen); + +#endif /* R300_TEXTURE_H */ -- cgit v1.2.3 From 2f37387786f1d0d6beded5afc29d36f744f1c948 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 22 Jan 2009 21:47:05 -0800 Subject: r300: Add texture sampler state. Easy compared to the actual texture handling code. --- src/gallium/drivers/r300/r300_context.h | 3 + src/gallium/drivers/r300/r300_state.c | 113 ++++++++++++++++++++++++++++++-- 2 files changed, 111 insertions(+), 5 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 3877c9855d..3cb5df4e20 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -66,6 +66,9 @@ struct r300_rs_state { }; struct r300_sampler_state { + uint32_t filter0; /* R300_TX_FILTER0: 0x4400 */ + uint32_t filter1; /* R300_TX_FILTER1: 0x4440 */ + uint32_t border_color; /* R300_TX_BORDER_COLOR: 0x45c0 */ }; struct r300_scissor_state { diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 7fb0fc2eba..8e15a429fb 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -21,6 +21,7 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "util/u_math.h" +#include "util/u_pack_color.h" #include "r300_context.h" #include "r300_reg.h" @@ -457,11 +458,113 @@ static void r300_delete_rs_state(struct pipe_context* pipe, void* state) FREE(state); } +static uint32_t translate_wrap(int wrap) { + switch (wrap) { + case PIPE_TEX_WRAP_REPEAT: + return R300_TX_REPEAT; + case PIPE_TEX_WRAP_CLAMP: + return R300_TX_CLAMP; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: + return R300_TX_CLAMP_TO_EDGE; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: + return R300_TX_CLAMP_TO_BORDER; + case PIPE_TEX_WRAP_MIRROR_REPEAT: + return R300_TX_REPEAT | R300_TX_MIRRORED; + case PIPE_TEX_WRAP_MIRROR_CLAMP: + return R300_TX_CLAMP | R300_TX_MIRRORED; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: + return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: + return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; + default: + /* XXX handle this? */ + return 0; + } +} + +static uint32_t translate_tex_filters(int min, int mag, int mip) { + uint32_t retval = 0; + switch (min) { + case PIPE_TEX_FILTER_NEAREST: + retval |= R300_TX_MIN_FILTER_NEAREST; + case PIPE_TEX_FILTER_LINEAR: + retval |= R300_TX_MIN_FILTER_LINEAR; + case PIPE_TEX_FILTER_ANISO: + retval |= R300_TX_MIN_FILTER_ANISO; + default: + /* XXX WTF?! */ + break; + } + switch (mag) { + case PIPE_TEX_FILTER_NEAREST: + retval |= R300_TX_MAG_FILTER_NEAREST; + case PIPE_TEX_FILTER_LINEAR: + retval |= R300_TX_MAG_FILTER_LINEAR; + case PIPE_TEX_FILTER_ANISO: + retval |= R300_TX_MAG_FILTER_ANISO; + default: + /* XXX WTF?! */ + break; + } + switch (mip) { + case PIPE_TEX_MIPFILTER_NONE: + retval |= R300_TX_MIN_FILTER_MIP_NONE; + case PIPE_TEX_MIPFILTER_NEAREST: + retval |= R300_TX_MIN_FILTER_MIP_NEAREST; + case PIPE_TEX_MIPFILTER_LINEAR: + retval |= R300_TX_MIN_FILTER_MIP_LINEAR; + default: + /* XXX WTF?! */ + break; + } + + return retval; +} + +static uint32_t anisotropy(float max_aniso) { + if (max_aniso >= 16.0f) { + return R300_TX_MAX_ANISO_16_TO_1; + } else if (max_aniso >= 8.0f) { + return R300_TX_MAX_ANISO_8_TO_1; + } else if (max_aniso >= 4.0f) { + return R300_TX_MAX_ANISO_4_TO_1; + } else if (max_aniso >= 2.0f) { + return R300_TX_MAX_ANISO_2_TO_1; + } else { + return R300_TX_MAX_ANISO_1_TO_1; + } +} + static void* r300_create_sampler_state(struct pipe_context* pipe, const struct pipe_sampler_state* state) { + struct r300_context* r300 = r300_context(pipe); struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); + int lod_bias; + + sampler->filter0 |= + (translate_wrap(state->wrap_s) << R300_TX_WRAP_S_SHIFT) | + (translate_wrap(state->wrap_t) << R300_TX_WRAP_T_SHIFT) | + (translate_wrap(state->wrap_r) << R300_TX_WRAP_R_SHIFT); + + sampler->filter0 |= translate_tex_filters(state->min_img_filter, + state->mag_img_filter, + state->min_mip_filter); + + lod_bias = CLAMP((int)(state->lod_bias * 32), -(1 << 9), (1 << 9) - 1); + + sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT; + + sampler->filter1 |= anisotropy(state->max_anisotropy); + + util_pack_color(state->border_color, PIPE_FORMAT_A8R8G8B8_UNORM, + &sampler->border_color); + + /* R500-specific fixups and optimizations */ + if (r300_screen(r300->context.screen)->caps->is_r500) { + sampler->filter1 |= R500_BORDER_FIX; + } return (void*)sampler; } @@ -471,15 +574,15 @@ static void r300_bind_sampler_states(struct pipe_context* pipe, void** states) { struct r300_context* r300 = r300_context(pipe); - int i = 0; + int i; if (count > 8) { return; } - for (i; i < count; i++) { + for (i = 0; i < count; i++) { if (r300->sampler_states[i] != states[i]) { - r300->sampler_states[i] = states[i]; + r300->sampler_states[i] = (struct r300_sampler_state*)states[i]; r300->dirty_state |= (R300_NEW_SAMPLER << i); } } @@ -510,8 +613,8 @@ static void r300_set_scissor_state(struct pipe_context* pipe, r300->scissor_state->scissor_top_left = (left << R300_SCISSORS_X_SHIFT) | (top << R300_SCISSORS_Y_SHIFT); - r300->scissor_state->scissor_bottom_right = (right << R300_SCISSORS_X_SHIFT) | - (bottom << R300_SCISSORS_Y_SHIFT); + r300->scissor_state->scissor_bottom_right = + (right << R300_SCISSORS_X_SHIFT) | (bottom << R300_SCISSORS_Y_SHIFT); r300->dirty_state |= R300_NEW_SCISSOR; } -- cgit v1.2.3 From 8e11e0121466efa34cfc14d299b43455a30b198c Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 23 Jan 2009 02:46:52 -0800 Subject: r300: Add initial pipe_texture handling. Still primitive and needing to be fleshed out, but it's a start. --- src/gallium/drivers/r300/r300_context.h | 14 ++++++ src/gallium/drivers/r300/r300_texture.c | 76 +++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_texture.h | 5 ++- 3 files changed, 93 insertions(+), 2 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 3cb5df4e20..f162aa4b64 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -84,6 +84,20 @@ struct r300_scissor_state { #define R300_NEW_SCISSOR 0x1000 #define R300_NEW_KITCHEN_SINK 0x1fff +struct r300_texture { + /* Parent class */ + struct pipe_texture tex; + + /* Offsets into the buffer. */ + unsigned offset[PIPE_MAX_TEXTURE_LEVELS]; + + /* Total size of this texture, in bytes. */ + unsigned size; + + /* Pipe buffer backing this texture. */ + struct pipe_buffer* buffer; +}; + struct r300_context { /* Parent class */ struct pipe_context context; diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 30d9e64b4c..2f6c52b137 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -22,14 +22,90 @@ #include "r300_texture.h" +static int minify(int i) +{ + return MAX2(1, i >> 1); +} + +static void r300_setup_miptree(struct r300_texture* tex) +{ + struct pipe_texture* base = &tex->tex; + int stride, size, offset; + + for (int i = 0; i <= base->last_level; i++) { + if (i > 0) { + base->width[i] = minify(base->width[i-1]); + base->height[i] = minify(base->height[i-1]); + base->depth[i] = minify(base->depth[i-1]); + } + + base->nblocksx[i] = pf_get_nblocksx(&base->block, base->width[i]); + base->nblocksy[i] = pf_get_nblocksy(&base->block, base->width[i]); + + /* Radeons enjoy things in multiples of 32. */ + /* XXX NPOT -> 64, not 32 */ + stride = (base->nblocksx[i] * base->block.size + 31) & ~31; + size = stride * base->nblocksy[i] * base->depth[i]; + + /* XXX 64 for NPOT */ + tex->offset[i] = (tex->size + 31) & ~31; + tex->size = tex->offset[i] + size; + } +} + /* Create a new texture. */ static struct pipe_texture* r300_texture_create(struct pipe_screen* screen, const struct pipe_texture* template) { + struct r300_screen* r300screen = r300_screen(screen); + + struct r300_texture* tex = CALLOC_STRUCT(r300_texture); + + if (!tex) { + return NULL; + } + + tex->tex = *template; + tex->tex.refcount = 1; + tex->tex.screen = screen; + + r300_setup_miptree(tex); + + tex->buffer = screen->winsys->buffer_create(screen->winsys, 32, + PIPE_BUFFER_USAGE_PIXEL, + tex->size); + + if (!tex->buffer) { + FREE(tex); + return NULL; + } + + return (struct pipe_texture*)tex; +} + +static void r300_texture_release(struct pipe_screen* screen, + struct pipe_texture** texture) +{ + if (!*texture) { + return; + } + + (*texture)->refcount--; + + if ((*texture)->refcount <= 0) { + struct r300_texture* tex = (struct r300_texture*)*texture; + + pipe_buffer_reference(screen, &tex->buffer, NULL); + + FREE(tex); + } + + *texture = NULL; } void r300_init_screen_texture_functions(struct pipe_screen* screen) { screen->texture_create = r300_texture_create; + screen->texture_release = r300_texture_release; } diff --git a/src/gallium/drivers/r300/r300_texture.h b/src/gallium/drivers/r300/r300_texture.h index 9d14cf81a6..7964229a94 100644 --- a/src/gallium/drivers/r300/r300_texture.h +++ b/src/gallium/drivers/r300/r300_texture.h @@ -25,8 +25,9 @@ #include "pipe/p_screen.h" -struct r300_texture { -}; +#include "util/u_math.h" + +#include "r300_context.h" void r300_init_screen_texture_functions(struct pipe_screen* screen); -- cgit v1.2.3 From 471129c7a14fb585ede198970e59270c4afa5310 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 23 Jan 2009 03:09:15 -0800 Subject: r300: Add more pipe_texture stuff. This is enough to sate glxinfo, for now. --- src/gallium/drivers/r300/r300_texture.c | 54 +++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 2f6c52b137..c1df905033 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -104,8 +104,62 @@ static void r300_texture_release(struct pipe_screen* screen, *texture = NULL; } +static struct pipe_surface* r300_get_tex_surface(struct pipe_screen* screen, + struct pipe_texture* texture, + unsigned face, + unsigned level, + unsigned zslice, + unsigned flags) +{ + struct r300_texture* tex = (struct r300_texture*)texture; + struct pipe_surface* surface = CALLOC_STRUCT(pipe_surface); + unsigned offset; + + /* XXX this is certainly dependent on tex target */ + offset = tex->offset[level]; + + if (surface) { + surface->refcount = 1; + surface->winsys = screen->winsys; + pipe_texture_reference(&surface->texture, texture); + pipe_buffer_reference(screen, &surface->buffer, tex->buffer); + surface->format = texture->format; + surface->width = texture->width[level]; + surface->height = texture->height[level]; + surface->block = texture->block; + surface->nblocksx = texture->nblocksx[level]; + surface->nblocksy = texture->nblocksy[level]; + /* XXX save the actual stride instead plz kthnxbai */ + surface->stride = + (texture->nblocksx[level] * texture->block.size + 31) & ~31; + surface->offset = offset; + surface->usage = flags; + surface->status = PIPE_SURFACE_STATUS_DEFINED; + } + + return surface; +} + +static void r300_tex_surface_release(struct pipe_screen* screen, + struct pipe_surface** surface) +{ + struct pipe_surface* s = *surface; + + s->refcount--; + + if (s->refcount <= 0) { + pipe_texture_reference(&s->texture, NULL); + pipe_buffer_reference(screen, &s->buffer, NULL); + FREE(s); + } + + *surface = NULL; +} + void r300_init_screen_texture_functions(struct pipe_screen* screen) { screen->texture_create = r300_texture_create; screen->texture_release = r300_texture_release; + screen->get_tex_surface = r300_get_tex_surface; + screen->tex_surface_release = r300_tex_surface_release; } -- cgit v1.2.3 From 45cb94217ebd55a4d38264ce83806062ba25a478 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 23 Jan 2009 15:08:27 -0800 Subject: r300: Add fragment shader stubs. Not looking forward to filling these out at all. --- src/gallium/drivers/r300/r300_context.h | 21 ++++++++++++++------- src/gallium/drivers/r300/r300_emit.c | 2 +- src/gallium/drivers/r300/r300_state.c | 32 +++++++++++++++++++++++++++++++- 3 files changed, 46 insertions(+), 9 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index f162aa4b64..0d7ba581cc 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -55,6 +55,9 @@ struct r300_dsa_state { uint32_t stencil_ref_bf; /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */ }; +struct r300_fs_state { +}; + struct r300_rs_state { uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */ @@ -76,13 +79,15 @@ struct r300_scissor_state { uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ }; -#define R300_NEW_BLEND 0x0001 -#define R300_NEW_BLEND_COLOR 0x0002 -#define R300_NEW_DSA 0x0004 -#define R300_NEW_RS 0x0008 -#define R300_NEW_SAMPLER 0x0010 -#define R300_NEW_SCISSOR 0x1000 -#define R300_NEW_KITCHEN_SINK 0x1fff +#define R300_NEW_BLEND 0x0001 +#define R300_NEW_BLEND_COLOR 0x0002 +#define R300_NEW_DSA 0x0004 +#define R300_NEW_FRAGMENT_SHADER 0x0008 +#define R300_NEW_RASTERIZER 0x0010 +#define R300_NEW_SAMPLER 0x0020 +#define R300_NEW_SCISSOR 0x2000 +#define R300_NEW_VERTEX_SHADER 0x4000 +#define R300_NEW_KITCHEN_SINK 0x7fff struct r300_texture { /* Parent class */ @@ -114,6 +119,8 @@ struct r300_context { struct r300_blend_color_state* blend_color_state; /* Depth, stencil, and alpha state. */ struct r300_dsa_state* dsa_state; + /* Fragment shader state. */ + struct r300_fs_state* fs_state; /* Rasterizer state. */ struct r300_rs_state* rs_state; /* Sampler states. */ diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index bf6fd3224e..19bfcbdd5b 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -74,7 +74,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) } } - if (r300->dirty_state & R300_NEW_RS) { + if (r300->dirty_state & R300_NEW_RASTERIZER) { struct r300_rs_state* rs = r300->rs_state; OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status); /* XXX next six are contiguous regs */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 8e15a429fb..9d9a4ec202 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -357,6 +357,32 @@ static void r300_delete_dsa_state(struct pipe_context* pipe, { FREE(state); } + +/* Create fragment shader state. */ +static void* r300_create_fs_state(struct pipe_context* pipe, + const struct pipe_shader_state* state) +{ + struct r300_fs_state* fs = CALLOC_STRUCT(r300_fs_state); + + return (void*)fs; +} + +/* Bind fragment shader state. */ +static void r300_bind_fs_state(struct pipe_context* pipe, void* state) +{ + struct r300_context* r300 = r300_context(pipe); + + r300->fs_state = (struct r300_fs_state*)state; + + r300->dirty_state |= R300_NEW_FRAGMENT_SHADER; +} + +/* Delect fragment shader state. */ +static void r300_delete_fs_state(struct pipe_context* pipe, void* state) +{ + FREE(state); +} + #if 0 struct pipe_rasterizer_state { @@ -449,7 +475,7 @@ static void r300_bind_rs_state(struct pipe_context* pipe, void* state) struct r300_context* r300 = r300_context(pipe); r300->rs_state = (struct r300_rs_state*)state; - r300->dirty_state |= R300_NEW_RS; + r300->dirty_state |= R300_NEW_RASTERIZER; } /* Free rasterizer state. */ @@ -652,6 +678,10 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; + r300->context.create_fs_state = r300_create_fs_state; + r300->context.bind_fs_state = r300_bind_fs_state; + r300->context.delete_fs_state = r300_delete_fs_state; + r300->context.create_rasterizer_state = r300_create_rs_state; r300->context.bind_rasterizer_state = r300_bind_rs_state; r300->context.delete_rasterizer_state = r300_delete_rs_state; -- cgit v1.2.3 From 1a5eea0c1e9ce6162ed6b07c337bffe62cb3c221 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 23 Jan 2009 17:01:04 -0800 Subject: r300: Finish basic state setup. I have successfully fooled glxinfo into believing that I am a competent writer of code. Next step is to trick trivial/clear. --- src/gallium/drivers/r300/Makefile | 1 + src/gallium/drivers/r300/r300_context.c | 2 ++ src/gallium/drivers/r300/r300_screen.c | 1 + src/gallium/drivers/r300/r300_texture.c | 31 +++++++++++++++++++++++++++++++ 4 files changed, 35 insertions(+) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index f1b1a615b8..1f67692166 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -9,6 +9,7 @@ C_SOURCES = \ r300_clear.c \ r300_context.c \ r300_emit.c \ + r300_flush.c \ r300_screen.c \ r300_state.c \ r300_surface.c \ diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index f254b2f2a3..314b2f0a11 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -52,6 +52,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->blend_color_state = CALLOC_STRUCT(r300_blend_color_state); r300->scissor_state = CALLOC_STRUCT(r300_scissor_state); + r300_init_flush_functions(r300); + r300_init_surface_functions(r300); r300_init_state_functions(r300); diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 2b83ae060c..bd5aa4f466 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -117,6 +117,7 @@ static float r300_get_paramf(struct pipe_screen* pscreen, int param) static boolean check_tex_2d_format(enum pipe_format format) { switch (format) { + case PIPE_FORMAT_A8R8G8B8_UNORM: case PIPE_FORMAT_I8_UNORM: return TRUE; default: diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index c1df905033..4adfe478c3 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -156,10 +156,41 @@ static void r300_tex_surface_release(struct pipe_screen* screen, *surface = NULL; } +static struct pipe_texture* + r300_texture_blanket(struct pipe_screen* screen, + const struct pipe_texture* base, + const unsigned* stride, + struct pipe_buffer* buffer) +{ + struct r300_texture* tex; + + if (base->target != PIPE_TEXTURE_2D || + base->last_level != 0 || + base->depth[0] != 1) { + return NULL; + } + + tex = CALLOC_STRUCT(r300_texture); + if (!tex) { + return NULL; + } + + tex->tex = *base; + tex->tex.refcount = 1; + tex->tex.screen = screen; + + /* XXX tex->stride = *stride; */ + + pipe_buffer_reference(screen, &tex->buffer, buffer); + + return (struct pipe_texture*)tex; +} + void r300_init_screen_texture_functions(struct pipe_screen* screen) { screen->texture_create = r300_texture_create; screen->texture_release = r300_texture_release; screen->get_tex_surface = r300_get_tex_surface; screen->tex_surface_release = r300_tex_surface_release; + screen->texture_blanket = r300_texture_blanket; } -- cgit v1.2.3 From 1a503019d73701ed311b15107f314bc84968bdb7 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 01:32:14 -0800 Subject: r300: Moar state handlers. Ah, my code's so bad. It's amazing. --- src/gallium/drivers/r300/r300_chipset.c | 3 ++ src/gallium/drivers/r300/r300_context.h | 9 ++++ src/gallium/drivers/r300/r300_state.c | 76 +++++++++++++++++++++++++++++++++ 3 files changed, 88 insertions(+) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index f2dc8aedaa..494c9e54c0 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -340,4 +340,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) /* XXX not an r300?! */ break; } + + /* Force off TCL for now */ + caps->has_tcl = FALSE; } diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 0d7ba581cc..52ddfa1df9 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -79,6 +79,9 @@ struct r300_scissor_state { uint32_t scissor_bottom_right; /* R300_SC_SCISSORS_BR: 0x43e4 */ }; +struct r300_texture_state { +}; + #define R300_NEW_BLEND 0x0001 #define R300_NEW_BLEND_COLOR 0x0002 #define R300_NEW_DSA 0x0004 @@ -121,6 +124,8 @@ struct r300_context { struct r300_dsa_state* dsa_state; /* Fragment shader state. */ struct r300_fs_state* fs_state; + /* Framebuffer state. We currently don't need our own version of this. */ + struct pipe_framebuffer_state framebuffer_state; /* Rasterizer state. */ struct r300_rs_state* rs_state; /* Sampler states. */ @@ -128,6 +133,10 @@ struct r300_context { int sampler_count; /* Scissor state. */ struct r300_scissor_state* scissor_state; + /* Texture states. */ + struct r300_texture* textures[8]; + struct r300_texture_state* texture_states[8]; + int texture_count; /* Bitmask of dirty state objects. */ uint32_t dirty_state; /* Flag indicating whether or not the HW is dirty. */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 9d9a4ec202..4f9d44bbfd 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -195,6 +195,15 @@ static void r300_set_blend_color(struct pipe_context* pipe, r300->dirty_state |= R300_NEW_BLEND_COLOR; } +static void r300_set_clip_state(struct pipe_context* pipe, + const struct pipe_clip_state* state) +{ + struct r300_context* r300 = r300_context(pipe); + /* XXX Draw */ + draw_flush(r300->draw); + draw_set_clip_state(r300->draw, state); +} + static uint32_t translate_depth_stencil_function(int zs_func) { switch (zs_func) { case PIPE_FUNC_NEVER: @@ -358,6 +367,19 @@ static void r300_delete_dsa_state(struct pipe_context* pipe, FREE(state); } +static void + r300_set_framebuffer_state(struct pipe_context* pipe, + const struct pipe_framebuffer_state* state) +{ + struct r300_context* r300 = r300_context(pipe); + + draw_flush(r300->draw); + + r300->framebuffer_state = *state; + + /* XXX do we need to mark dirty state? */ +} + /* Create fragment shader state. */ static void* r300_create_fs_state(struct pipe_context* pipe, const struct pipe_shader_state* state) @@ -383,6 +405,12 @@ static void r300_delete_fs_state(struct pipe_context* pipe, void* state) FREE(state); } +static void r300_set_polygon_stipple(struct pipe_context* pipe, + const struct pipe_poly_stipple* state) +{ + /* XXX */ +} + #if 0 struct pipe_rasterizer_state { @@ -621,6 +649,36 @@ static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) FREE(state); } +static void r300_set_sampler_textures(struct pipe_context* pipe, + unsigned count, + struct pipe_texture** texture) +{ + struct r300_context* r300 = r300_context(pipe); + int i; + + /* XXX magic num */ + if (count > 8) { + return; + } + + for (i = 0; i < count; i++) { + if (r300->textures[i] != (struct r300_texture*)texture[i]) { + pipe_texture_reference((struct pipe_texture**)&r300->textures[i], + texture[i]); + /* XXX NEW_TEXTURE instead? */ + r300->dirty_state |= (R300_NEW_SAMPLER << i); + } + } + + for (i = count; i < 8; i++) { + /* XXX also state change? */ + pipe_texture_reference((struct pipe_texture**)&r300->textures[i], + NULL); + } + + r300->texture_count = count; +} + static void r300_set_scissor_state(struct pipe_context* pipe, const struct pipe_scissor_state* state) { @@ -645,6 +703,14 @@ static void r300_set_scissor_state(struct pipe_context* pipe, r300->dirty_state |= R300_NEW_SCISSOR; } +static void r300_set_viewport_state(struct pipe_context* pipe, + const struct pipe_viewport_state* state) +{ + struct r300_context* r300 = r300_context(pipe); + /* XXX handing this off to Draw for now */ + draw_set_viewport_state(r300->draw, state); +} + static void* r300_create_vs_state(struct pipe_context* pipe, const struct pipe_shader_state* state) { @@ -674,14 +740,20 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.set_blend_color = r300_set_blend_color; + r300->context.set_clip_state = r300_set_clip_state; + r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; + r300->context.set_framebuffer_state = r300_set_framebuffer_state; + r300->context.create_fs_state = r300_create_fs_state; r300->context.bind_fs_state = r300_bind_fs_state; r300->context.delete_fs_state = r300_delete_fs_state; + r300->context.set_polygon_stipple = r300_set_polygon_stipple; + r300->context.create_rasterizer_state = r300_create_rs_state; r300->context.bind_rasterizer_state = r300_bind_rs_state; r300->context.delete_rasterizer_state = r300_delete_rs_state; @@ -690,8 +762,12 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.bind_sampler_states = r300_bind_sampler_states; r300->context.delete_sampler_state = r300_delete_sampler_state; + r300->context.set_sampler_textures = r300_set_sampler_textures; + r300->context.set_scissor_state = r300_set_scissor_state; + r300->context.set_viewport_state = r300_set_viewport_state; + r300->context.create_vs_state = r300_create_vs_state; r300->context.bind_vs_state = r300_bind_vs_state; r300->context.delete_vs_state = r300_delete_vs_state; -- cgit v1.2.3 From 7d3d3c75cc1bade8eeb7cbbabd290e2b30dc3100 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 01:49:57 -0800 Subject: r300: Plan for the next state setters. --- src/gallium/drivers/r300/r300_state.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 4f9d44bbfd..e52d8ec9c2 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -732,8 +732,8 @@ static void r300_delete_vs_state(struct pipe_context* pipe, void* state) draw_delete_vertex_shader(context->draw, (struct draw_vertex_shader*)state); } -void r300_init_state_functions(struct r300_context* r300) { - +void r300_init_state_functions(struct r300_context* r300) +{ r300->context.create_blend_state = r300_create_blend_state; r300->context.bind_blend_state = r300_bind_blend_state; r300->context.delete_blend_state = r300_delete_blend_state; @@ -742,10 +742,14 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.set_clip_state = r300_set_clip_state; + /* XXX r300->context.set_constant_buffer = r300_set_constant_buffer; */ + r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; + /* XXX r300->context.set_edgeflags = r300_set_edgeflags; */ + r300->context.set_framebuffer_state = r300_set_framebuffer_state; r300->context.create_fs_state = r300_create_fs_state; @@ -768,6 +772,9 @@ void r300_init_state_functions(struct r300_context* r300) { r300->context.set_viewport_state = r300_set_viewport_state; + /* XXX r300->context.set_vertex_buffers = r300_set_vertex_buffers; + * XXX r300->context.set_vertex_elements = r300_set_vertex_elements; */ + r300->context.create_vs_state = r300_create_vs_state; r300->context.bind_vs_state = r300_bind_vs_state; r300->context.delete_vs_state = r300_delete_vs_state; -- cgit v1.2.3 From 1aa2ecf3533154337947dbac2ace54fadf031692 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 02:03:35 -0800 Subject: r300: Put r300_blit to bed. Not going to be using the blitter. Period. --- src/gallium/drivers/r300/Makefile | 1 - src/gallium/drivers/r300/r300_blit.c | 96 ------------------------------------ src/gallium/drivers/r300/r300_blit.h | 43 ---------------- 3 files changed, 140 deletions(-) delete mode 100644 src/gallium/drivers/r300/r300_blit.c delete mode 100644 src/gallium/drivers/r300/r300_blit.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index 1f67692166..1d61b31605 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -4,7 +4,6 @@ include $(TOP)/configs/current LIBNAME = r300 C_SOURCES = \ - r300_blit.c \ r300_chipset.c \ r300_clear.c \ r300_context.c \ diff --git a/src/gallium/drivers/r300/r300_blit.c b/src/gallium/drivers/r300/r300_blit.c deleted file mode 100644 index 6bcfbc0d79..0000000000 --- a/src/gallium/drivers/r300/r300_blit.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2008 Corbin Simpson - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#include "r300_blit.h" - -/* Does a "paint" into the specified rectangle. - * Returns 1 on success, 0 on error. */ -int r300_fill_blit(struct r300_context* r300, - unsigned cpp, - short dst_pitch, - struct pipe_buffer* dst_buffer, - unsigned dst_offset, - short x, short y, - short w, short h, - unsigned color) -{ - CS_LOCALS(r300); - uint32_t dest_type; -#if 0 - /* Check for fallbacks. */ - /* XXX we can do YUV surfaces, too, but only in 3D mode. Hmm... */ - switch(cpp) { - case 2: - case 6: - dest_type = ATI_DATATYPE_CI8; - break; - case 4: - dest_type = ATI_DATATYPE_RGB565; - break; - case 8: - dest_type = ATI_DATATYPE_ARGB8888; - break; - default: - /* Whatever this is, we can't fill it. (Yet.) */ - return 0; - } - - /* XXX odds are *incredibly* good that we were in 3D just a bit ago, - * so flush here first. */ - - BEGIN_CS(10 + 2 + 2); - - /* Set up the 2D engine. */ - OUT_CS_REG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, - RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); - OUT_CS_REG(RADEON_DP_GUI_MASTER_CNTL, - RADEON_GMC_DST_PITCH_OFFSET_CNTL | - RADEON_GMC_BRUSH_SOLID_COLOR | - (dest_type << 8) | - RADEON_GMC_SRC_DATATYPE_COLOR | - RADEON_ROP3_P | - RADEON_GMC_CLR_CMP_CNTL_DIS); - /* XXX pack this? */ - OUT_CS_REG(RADEON_DP_BRUSH_FRGD_CLR, color); - OUT_CS_REG(RADEON_DP_BRUSH_BKGD_CLR, 0x00000000); - OUT_CS_REG(RADEON_DP_SRC_FRGD_CLR, 0xffffffff); - OUT_CS_REG(RADEON_DP_SRC_BKGD_CLR, 0x00000000); - /* XXX what should this be? */ - OUT_CS_REG(RADEON_DP_WRITE_MASK, 0x00000000); - OUT_CS_REG(RADEON_DP_CNTL, - RADEON_DST_X_LEFT_TO_RIGHT | RADEON_DST_Y_TOP_TO_BOTTOM); - OUT_CS_REG(RADEON_DST_PITCH_OFFSET, 0x0); - OUT_CS_RELOC(dst_buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - - /* Do the actual paint. */ - OUT_CS_REG(RADEON_DST_Y_X, (y << 16) | x); - OUT_CS_REG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); - - /* Let the 2D engine settle. */ - OUT_CS_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); - OUT_CS_REG(RADEON_WAIT_UNTIL, - RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE); - - END_CS; -#endif - return 1; -} diff --git a/src/gallium/drivers/r300/r300_blit.h b/src/gallium/drivers/r300/r300_blit.h deleted file mode 100644 index 740cbcdea5..0000000000 --- a/src/gallium/drivers/r300/r300_blit.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2008 Corbin Simpson - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. */ - -#ifndef R300_BLIT_H -#define R300_BLIT_H - -#include "pipe/p_state.h" - -#include "r300_context.h" -#include "r300_cs.h" - -/* Forward declarations. */ -struct r300_context; - -extern int r300_fill_blit(struct r300_context* r300, - unsigned cpp, - short dst_pitch, - struct pipe_buffer* dst_buffer, - unsigned dst_offset, - short x, short y, - short w, short h, - unsigned color); - -#endif /* R300_BLIT_H */ \ No newline at end of file -- cgit v1.2.3 From e54732eb3db8452a99fcc2ad68fb644cecba6a20 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 02:12:55 -0800 Subject: r300: Remove radeon_reg. Wonder why this was ever committed... --- src/gallium/drivers/r300/radeon_reg.h | 5324 --------------------------------- 1 file changed, 5324 deletions(-) delete mode 100644 src/gallium/drivers/r300/radeon_reg.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/radeon_reg.h b/src/gallium/drivers/r300/radeon_reg.h deleted file mode 100644 index e2fcb70a95..0000000000 --- a/src/gallium/drivers/r300/radeon_reg.h +++ /dev/null @@ -1,5324 +0,0 @@ -/* - * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and - * VA Linux Systems Inc., Fremont, California. - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation on the rights to use, copy, modify, merge, - * publish, distribute, sublicense, and/or sell copies of the Software, - * and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR - * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -/* - * Authors: - * Kevin E. Martin - * Rickard E. Faith - * Alan Hourihane - * - * References: - * - * !!!! FIXME !!!! - * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical - * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April - * 1999. - * - * !!!! FIXME !!!! - * RAGE 128 Software Development Manual (Technical Reference Manual P/N - * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. - * - */ - -/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h - * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT - * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ - -/* XXX clean this bitch up */ - -#ifndef _RADEON_REG_H_ -#define _RADEON_REG_H_ - -#define ATI_DATATYPE_VQ 0 -#define ATI_DATATYPE_CI4 1 -#define ATI_DATATYPE_CI8 2 -#define ATI_DATATYPE_ARGB1555 3 -#define ATI_DATATYPE_RGB565 4 -#define ATI_DATATYPE_RGB888 5 -#define ATI_DATATYPE_ARGB8888 6 -#define ATI_DATATYPE_RGB332 7 -#define ATI_DATATYPE_Y8 8 -#define ATI_DATATYPE_RGB8 9 -#define ATI_DATATYPE_CI16 10 -#define ATI_DATATYPE_VYUY_422 11 -#define ATI_DATATYPE_YVYU_422 12 -#define ATI_DATATYPE_AYUV_444 14 -#define ATI_DATATYPE_ARGB4444 15 - - /* Registers for 2D/Video/Overlay */ -#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ -#define RADEON_AGP_BASE 0x0170 -#define RADEON_AGP_CNTL 0x0174 -# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) -# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) -# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) -# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) -# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) -# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) -# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) -# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) -#define RADEON_STATUS_PCI_CONFIG 0x06 -# define RADEON_CAP_LIST 0x100000 -#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ -# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ -# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ -# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ -# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ -#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ -#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ -# define RADEON_AGP_ENABLE (1<<8) -#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ -#define RADEON_AGP_STATUS 0x0f5c /* PCI */ -# define RADEON_AGP_1X_MODE 0x01 -# define RADEON_AGP_2X_MODE 0x02 -# define RADEON_AGP_4X_MODE 0x04 -# define RADEON_AGP_FW_MODE 0x10 -# define RADEON_AGP_MODE_MASK 0x17 -# define RADEON_AGPv3_MODE 0x08 -# define RADEON_AGPv3_4X_MODE 0x01 -# define RADEON_AGPv3_8X_MODE 0x02 -#define RADEON_ATTRDR 0x03c1 /* VGA */ -#define RADEON_ATTRDW 0x03c0 /* VGA */ -#define RADEON_ATTRX 0x03c0 /* VGA */ -#define RADEON_AUX_SC_CNTL 0x1660 -# define RADEON_AUX1_SC_EN (1 << 0) -# define RADEON_AUX1_SC_MODE_OR (0 << 1) -# define RADEON_AUX1_SC_MODE_NAND (1 << 1) -# define RADEON_AUX2_SC_EN (1 << 2) -# define RADEON_AUX2_SC_MODE_OR (0 << 3) -# define RADEON_AUX2_SC_MODE_NAND (1 << 3) -# define RADEON_AUX3_SC_EN (1 << 4) -# define RADEON_AUX3_SC_MODE_OR (0 << 5) -# define RADEON_AUX3_SC_MODE_NAND (1 << 5) -#define RADEON_AUX1_SC_BOTTOM 0x1670 -#define RADEON_AUX1_SC_LEFT 0x1664 -#define RADEON_AUX1_SC_RIGHT 0x1668 -#define RADEON_AUX1_SC_TOP 0x166c -#define RADEON_AUX2_SC_BOTTOM 0x1680 -#define RADEON_AUX2_SC_LEFT 0x1674 -#define RADEON_AUX2_SC_RIGHT 0x1678 -#define RADEON_AUX2_SC_TOP 0x167c -#define RADEON_AUX3_SC_BOTTOM 0x1690 -#define RADEON_AUX3_SC_LEFT 0x1684 -#define RADEON_AUX3_SC_RIGHT 0x1688 -#define RADEON_AUX3_SC_TOP 0x168c -#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 -#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc - -#define RADEON_BASE_CODE 0x0f0b -#define RADEON_BIOS_0_SCRATCH 0x0010 -# define RADEON_FP_PANEL_SCALABLE (1 << 16) -# define RADEON_FP_PANEL_SCALE_EN (1 << 17) -# define RADEON_FP_CHIP_SCALE_EN (1 << 18) -# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) -# define RADEON_DISPLAY_ROT_MASK (3 << 28) -# define RADEON_DISPLAY_ROT_00 (0 << 28) -# define RADEON_DISPLAY_ROT_90 (1 << 28) -# define RADEON_DISPLAY_ROT_180 (2 << 28) -# define RADEON_DISPLAY_ROT_270 (3 << 28) -#define RADEON_BIOS_1_SCRATCH 0x0014 -#define RADEON_BIOS_2_SCRATCH 0x0018 -#define RADEON_BIOS_3_SCRATCH 0x001c -#define RADEON_BIOS_4_SCRATCH 0x0020 -# define RADEON_CRT1_ATTACHED_MASK (3 << 0) -# define RADEON_CRT1_ATTACHED_MONO (1 << 0) -# define RADEON_CRT1_ATTACHED_COLOR (2 << 0) -# define RADEON_LCD1_ATTACHED (1 << 2) -# define RADEON_DFP1_ATTACHED (1 << 3) -# define RADEON_TV1_ATTACHED_MASK (3 << 4) -# define RADEON_TV1_ATTACHED_COMP (1 << 4) -# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) -# define RADEON_CRT2_ATTACHED_MASK (3 << 8) -# define RADEON_CRT2_ATTACHED_MONO (1 << 8) -# define RADEON_CRT2_ATTACHED_COLOR (2 << 8) -# define RADEON_DFP2_ATTACHED (1 << 11) -#define RADEON_BIOS_5_SCRATCH 0x0024 -# define RADEON_LCD1_ON (1 << 0) -# define RADEON_CRT1_ON (1 << 1) -# define RADEON_TV1_ON (1 << 2) -# define RADEON_DFP1_ON (1 << 3) -# define RADEON_CRT2_ON (1 << 5) -# define RADEON_CV1_ON (1 << 6) -# define RADEON_DFP2_ON (1 << 7) -# define RADEON_LCD1_CRTC_MASK (1 << 8) -# define RADEON_LCD1_CRTC_SHIFT 8 -# define RADEON_CRT1_CRTC_MASK (1 << 9) -# define RADEON_CRT1_CRTC_SHIFT 9 -# define RADEON_TV1_CRTC_MASK (1 << 10) -# define RADEON_TV1_CRTC_SHIFT 10 -# define RADEON_DFP1_CRTC_MASK (1 << 11) -# define RADEON_DFP1_CRTC_SHIFT 11 -# define RADEON_CRT2_CRTC_MASK (1 << 12) -# define RADEON_CRT2_CRTC_SHIFT 12 -# define RADEON_CV1_CRTC_MASK (1 << 13) -# define RADEON_CV1_CRTC_SHIFT 13 -# define RADEON_DFP2_CRTC_MASK (1 << 14) -# define RADEON_DFP2_CRTC_SHIFT 14 -#define RADEON_BIOS_6_SCRATCH 0x0028 -# define RADEON_ACC_MODE_CHANGE (1 << 2) -# define RADEON_EXT_DESKTOP_MODE (1 << 3) -# define RADEON_LCD_DPMS_ON (1 << 20) -# define RADEON_CRT_DPMS_ON (1 << 21) -# define RADEON_TV_DPMS_ON (1 << 22) -# define RADEON_DFP_DPMS_ON (1 << 23) -# define RADEON_DPMS_MASK (3 << 24) -# define RADEON_DPMS_ON (0 << 24) -# define RADEON_DPMS_STANDBY (1 << 24) -# define RADEON_DPMS_SUSPEND (2 << 24) -# define RADEON_DPMS_OFF (3 << 24) -# define RADEON_SCREEN_BLANKING (1 << 26) -# define RADEON_DRIVER_CRITICAL (1 << 27) -# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) -#define RADEON_BIOS_7_SCRATCH 0x002c -# define RADEON_SYS_HOTKEY (1 << 10) -# define RADEON_DRV_LOADED (1 << 12) -#define RADEON_BIOS_ROM 0x0f30 /* PCI */ -#define RADEON_BIST 0x0f0f /* PCI */ -#define RADEON_BRUSH_DATA0 0x1480 -#define RADEON_BRUSH_DATA1 0x1484 -#define RADEON_BRUSH_DATA10 0x14a8 -#define RADEON_BRUSH_DATA11 0x14ac -#define RADEON_BRUSH_DATA12 0x14b0 -#define RADEON_BRUSH_DATA13 0x14b4 -#define RADEON_BRUSH_DATA14 0x14b8 -#define RADEON_BRUSH_DATA15 0x14bc -#define RADEON_BRUSH_DATA16 0x14c0 -#define RADEON_BRUSH_DATA17 0x14c4 -#define RADEON_BRUSH_DATA18 0x14c8 -#define RADEON_BRUSH_DATA19 0x14cc -#define RADEON_BRUSH_DATA2 0x1488 -#define RADEON_BRUSH_DATA20 0x14d0 -#define RADEON_BRUSH_DATA21 0x14d4 -#define RADEON_BRUSH_DATA22 0x14d8 -#define RADEON_BRUSH_DATA23 0x14dc -#define RADEON_BRUSH_DATA24 0x14e0 -#define RADEON_BRUSH_DATA25 0x14e4 -#define RADEON_BRUSH_DATA26 0x14e8 -#define RADEON_BRUSH_DATA27 0x14ec -#define RADEON_BRUSH_DATA28 0x14f0 -#define RADEON_BRUSH_DATA29 0x14f4 -#define RADEON_BRUSH_DATA3 0x148c -#define RADEON_BRUSH_DATA30 0x14f8 -#define RADEON_BRUSH_DATA31 0x14fc -#define RADEON_BRUSH_DATA32 0x1500 -#define RADEON_BRUSH_DATA33 0x1504 -#define RADEON_BRUSH_DATA34 0x1508 -#define RADEON_BRUSH_DATA35 0x150c -#define RADEON_BRUSH_DATA36 0x1510 -#define RADEON_BRUSH_DATA37 0x1514 -#define RADEON_BRUSH_DATA38 0x1518 -#define RADEON_BRUSH_DATA39 0x151c -#define RADEON_BRUSH_DATA4 0x1490 -#define RADEON_BRUSH_DATA40 0x1520 -#define RADEON_BRUSH_DATA41 0x1524 -#define RADEON_BRUSH_DATA42 0x1528 -#define RADEON_BRUSH_DATA43 0x152c -#define RADEON_BRUSH_DATA44 0x1530 -#define RADEON_BRUSH_DATA45 0x1534 -#define RADEON_BRUSH_DATA46 0x1538 -#define RADEON_BRUSH_DATA47 0x153c -#define RADEON_BRUSH_DATA48 0x1540 -#define RADEON_BRUSH_DATA49 0x1544 -#define RADEON_BRUSH_DATA5 0x1494 -#define RADEON_BRUSH_DATA50 0x1548 -#define RADEON_BRUSH_DATA51 0x154c -#define RADEON_BRUSH_DATA52 0x1550 -#define RADEON_BRUSH_DATA53 0x1554 -#define RADEON_BRUSH_DATA54 0x1558 -#define RADEON_BRUSH_DATA55 0x155c -#define RADEON_BRUSH_DATA56 0x1560 -#define RADEON_BRUSH_DATA57 0x1564 -#define RADEON_BRUSH_DATA58 0x1568 -#define RADEON_BRUSH_DATA59 0x156c -#define RADEON_BRUSH_DATA6 0x1498 -#define RADEON_BRUSH_DATA60 0x1570 -#define RADEON_BRUSH_DATA61 0x1574 -#define RADEON_BRUSH_DATA62 0x1578 -#define RADEON_BRUSH_DATA63 0x157c -#define RADEON_BRUSH_DATA7 0x149c -#define RADEON_BRUSH_DATA8 0x14a0 -#define RADEON_BRUSH_DATA9 0x14a4 -#define RADEON_BRUSH_SCALE 0x1470 -#define RADEON_BRUSH_Y_X 0x1474 -#define RADEON_BUS_CNTL 0x0030 -# define RADEON_BUS_MASTER_DIS (1 << 6) -# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) -# define RADEON_BUS_RD_DISCARD_EN (1 << 24) -# define RADEON_BUS_RD_ABORT_EN (1 << 25) -# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) -# define RADEON_BUS_WRT_BURST (1 << 29) -# define RADEON_BUS_READ_BURST (1 << 30) -#define RADEON_BUS_CNTL1 0x0034 -# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) - -#define RADEON_CACHE_CNTL 0x1724 -#define RADEON_CACHE_LINE 0x0f0c /* PCI */ -#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ -#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ -#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ -# define RADEON_SCLK_DYN_START_CNTL (1 << 15) -#define RADEON_CLOCK_CNTL_DATA 0x000c -#define RADEON_CLOCK_CNTL_INDEX 0x0008 -# define RADEON_PLL_WR_EN (1 << 7) -# define RADEON_PLL_DIV_SEL (3 << 8) -# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) -#define RADEON_CLK_PWRMGT_CNTL 0x0014 -# define RADEON_ENGIN_DYNCLK_MODE (1 << 12) -# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) -# define RADEON_ACTIVE_HILO_LAT_SHIFT 13 -# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) -# define RADEON_MC_BUSY (1 << 16) -# define RADEON_DLL_READY (1 << 19) -# define RADEON_CG_NO1_DEBUG_0 (1 << 24) -# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) -# define RADEON_DYN_STOP_MODE_MASK (7 << 21) -# define RADEON_TVPLL_PWRMGT_OFF (1 << 30) -# define RADEON_TVCLK_TURNOFF (1 << 31) -#define RADEON_PLL_PWRMGT_CNTL 0x0015 -# define RADEON_TCL_BYPASS_DISABLE (1 << 20) -#define RADEON_CLR_CMP_CLR_3D 0x1a24 -#define RADEON_CLR_CMP_CLR_DST 0x15c8 -#define RADEON_CLR_CMP_CLR_SRC 0x15c4 -#define RADEON_CLR_CMP_CNTL 0x15c0 -# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) -# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) -# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) -#define RADEON_CLR_CMP_MASK 0x15cc -# define RADEON_CLR_CMP_MSK 0xffffffff -#define RADEON_CLR_CMP_MASK_3D 0x1A28 -#define RADEON_COMMAND 0x0f04 /* PCI */ -#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c -#define RADEON_CONFIG_APER_0_BASE 0x0100 -#define RADEON_CONFIG_APER_1_BASE 0x0104 -#define RADEON_CONFIG_APER_SIZE 0x0108 -#define RADEON_CONFIG_BONDS 0x00e8 -#define RADEON_CONFIG_CNTL 0x00e0 -# define RADEON_CFG_ATI_REV_A11 (0 << 16) -# define RADEON_CFG_ATI_REV_A12 (1 << 16) -# define RADEON_CFG_ATI_REV_A13 (2 << 16) -# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) -#define RADEON_CONFIG_MEMSIZE 0x00f8 -#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 -#define RADEON_CONFIG_REG_1_BASE 0x010c -#define RADEON_CONFIG_REG_APER_SIZE 0x0110 -#define RADEON_CONFIG_XSTRAP 0x00e4 -#define RADEON_CONSTANT_COLOR_C 0x1d34 -# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff -# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff -# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 -#define RADEON_CRC_CMDFIFO_ADDR 0x0740 -#define RADEON_CRC_CMDFIFO_DOUT 0x0744 -#define RADEON_GRPH_BUFFER_CNTL 0x02f0 -# define RADEON_GRPH_START_REQ_MASK (0x7f) -# define RADEON_GRPH_START_REQ_SHIFT 0 -# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) -# define RADEON_GRPH_STOP_REQ_SHIFT 8 -# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) -# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 -# define RADEON_GRPH_CRITICAL_CNTL (1<<28) -# define RADEON_GRPH_BUFFER_SIZE (1<<29) -# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) -# define RADEON_GRPH_STOP_CNTL (1<<31) -#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 -# define RADEON_GRPH2_START_REQ_MASK (0x7f) -# define RADEON_GRPH2_START_REQ_SHIFT 0 -# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) -# define RADEON_GRPH2_STOP_REQ_SHIFT 8 -# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) -# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 -# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) -# define RADEON_GRPH2_BUFFER_SIZE (1<<29) -# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) -# define RADEON_GRPH2_STOP_CNTL (1<<31) -#define RADEON_CRTC_CRNT_FRAME 0x0214 -#define RADEON_CRTC_EXT_CNTL 0x0054 -# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) -# define RADEON_VGA_ATI_LINEAR (1 << 3) -# define RADEON_XCRT_CNT_EN (1 << 6) -# define RADEON_CRTC_HSYNC_DIS (1 << 8) -# define RADEON_CRTC_VSYNC_DIS (1 << 9) -# define RADEON_CRTC_DISPLAY_DIS (1 << 10) -# define RADEON_CRTC_SYNC_TRISTAT (1 << 11) -# define RADEON_CRTC_CRT_ON (1 << 15) -#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 -# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) -# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) -# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) -#define RADEON_CRTC_GEN_CNTL 0x0050 -# define RADEON_CRTC_DBL_SCAN_EN (1 << 0) -# define RADEON_CRTC_INTERLACE_EN (1 << 1) -# define RADEON_CRTC_CSYNC_EN (1 << 4) -# define RADEON_CRTC_ICON_EN (1 << 15) -# define RADEON_CRTC_CUR_EN (1 << 16) -# define RADEON_CRTC_CUR_MODE_MASK (7 << 20) -# define RADEON_CRTC_EXT_DISP_EN (1 << 24) -# define RADEON_CRTC_EN (1 << 25) -# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) -#define RADEON_CRTC2_GEN_CNTL 0x03f8 -# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) -# define RADEON_CRTC2_INTERLACE_EN (1 << 1) -# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) -# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) -# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) -# define RADEON_CRTC2_CRT2_ON (1 << 7) -# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 -# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) -# define RADEON_CRTC2_ICON_EN (1 << 15) -# define RADEON_CRTC2_CUR_EN (1 << 16) -# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) -# define RADEON_CRTC2_DISP_DIS (1 << 23) -# define RADEON_CRTC2_EN (1 << 25) -# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) -# define RADEON_CRTC2_CSYNC_EN (1 << 27) -# define RADEON_CRTC2_HSYNC_DIS (1 << 28) -# define RADEON_CRTC2_VSYNC_DIS (1 << 29) -#define RADEON_CRTC_MORE_CNTL 0x27c -# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) -# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) -# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) -#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 -#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 -# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) -# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) -# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 -# define RADEON_CRTC_H_SYNC_WID (0x3f << 16) -# define RADEON_CRTC_H_SYNC_WID_SHIFT 16 -# define RADEON_CRTC_H_SYNC_POL (1 << 23) -#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 -# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) -# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) -# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 -# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) -# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 -# define RADEON_CRTC2_H_SYNC_POL (1 << 23) -#define RADEON_CRTC_H_TOTAL_DISP 0x0200 -# define RADEON_CRTC_H_TOTAL (0x03ff << 0) -# define RADEON_CRTC_H_TOTAL_SHIFT 0 -# define RADEON_CRTC_H_DISP (0x01ff << 16) -# define RADEON_CRTC_H_DISP_SHIFT 16 -#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 -# define RADEON_CRTC2_H_TOTAL (0x03ff << 0) -# define RADEON_CRTC2_H_TOTAL_SHIFT 0 -# define RADEON_CRTC2_H_DISP (0x01ff << 16) -# define RADEON_CRTC2_H_DISP_SHIFT 16 - -#define RADEON_CRTC_OFFSET_RIGHT 0x0220 -#define RADEON_CRTC_OFFSET 0x0224 -# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) -# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) - -#define RADEON_CRTC2_OFFSET 0x0324 -# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) -# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) -#define RADEON_CRTC_OFFSET_CNTL 0x0228 -# define RADEON_CRTC_TILE_LINE_SHIFT 0 -# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 -# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) -# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) -# define R300_CRTC_X_Y_MODE_EN (1 << 9) -# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) -# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) -# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) -# define R300_CRTC_MICRO_TILE_EN (1 << 13) -# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) -# define R300_CRTC_MACRO_TILE_EN (1 << 15) -# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) -# define RADEON_CRTC_TILE_EN (1 << 15) -# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) -# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) - -#define R300_CRTC_TILE_X0_Y0 0x0350 -#define R300_CRTC2_TILE_X0_Y0 0x0358 - -#define RADEON_CRTC2_OFFSET_CNTL 0x0328 -# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) -# define RADEON_CRTC2_TILE_EN (1 << 15) -#define RADEON_CRTC_PITCH 0x022c -# define RADEON_CRTC_PITCH__SHIFT 0 -# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 - -#define RADEON_CRTC2_PITCH 0x032c -#define RADEON_CRTC_STATUS 0x005c -# define RADEON_CRTC_VBLANK_SAVE (1 << 1) -# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) -#define RADEON_CRTC2_STATUS 0x03fc -# define RADEON_CRTC2_VBLANK_SAVE (1 << 1) -# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) -#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c -# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) -# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 -# define RADEON_CRTC_V_SYNC_WID (0x1f << 16) -# define RADEON_CRTC_V_SYNC_WID_SHIFT 16 -# define RADEON_CRTC_V_SYNC_POL (1 << 23) -#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c -# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) -# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 -# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) -# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 -# define RADEON_CRTC2_V_SYNC_POL (1 << 23) -#define RADEON_CRTC_V_TOTAL_DISP 0x0208 -# define RADEON_CRTC_V_TOTAL (0x07ff << 0) -# define RADEON_CRTC_V_TOTAL_SHIFT 0 -# define RADEON_CRTC_V_DISP (0x07ff << 16) -# define RADEON_CRTC_V_DISP_SHIFT 16 -#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 -# define RADEON_CRTC2_V_TOTAL (0x07ff << 0) -# define RADEON_CRTC2_V_TOTAL_SHIFT 0 -# define RADEON_CRTC2_V_DISP (0x07ff << 16) -# define RADEON_CRTC2_V_DISP_SHIFT 16 -#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 -# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) -#define RADEON_CRTC2_CRNT_FRAME 0x0314 -#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 -#define RADEON_CRTC2_STATUS 0x03fc -#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 -#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ -#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ -#define RADEON_CUR_CLR0 0x026c -#define RADEON_CUR_CLR1 0x0270 -#define RADEON_CUR_HORZ_VERT_OFF 0x0268 -#define RADEON_CUR_HORZ_VERT_POSN 0x0264 -#define RADEON_CUR_OFFSET 0x0260 -# define RADEON_CUR_LOCK (1 << 31) -#define RADEON_CUR2_CLR0 0x036c -#define RADEON_CUR2_CLR1 0x0370 -#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 -#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 -#define RADEON_CUR2_OFFSET 0x0360 -# define RADEON_CUR2_LOCK (1 << 31) - -#define RADEON_DAC_CNTL 0x0058 -# define RADEON_DAC_RANGE_CNTL (3 << 0) -# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) -# define RADEON_DAC_RANGE_CNTL_MASK 0x03 -# define RADEON_DAC_BLANKING (1 << 2) -# define RADEON_DAC_CMP_EN (1 << 3) -# define RADEON_DAC_CMP_OUTPUT (1 << 7) -# define RADEON_DAC_8BIT_EN (1 << 8) -# define RADEON_DAC_TVO_EN (1 << 10) -# define RADEON_DAC_VGA_ADR_EN (1 << 13) -# define RADEON_DAC_PDWN (1 << 15) -# define RADEON_DAC_MASK_ALL (0xff << 24) -#define RADEON_DAC_CNTL2 0x007c -# define RADEON_DAC2_TV_CLK_SEL (0 << 1) -# define RADEON_DAC2_DAC_CLK_SEL (1 << 0) -# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) -# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) -# define RADEON_DAC2_CMP_EN (1 << 7) -# define RADEON_DAC2_CMP_OUT_R (1 << 8) -# define RADEON_DAC2_CMP_OUT_G (1 << 9) -# define RADEON_DAC2_CMP_OUT_B (1 << 10) -# define RADEON_DAC2_CMP_OUTPUT (1 << 11) -#define RADEON_DAC_EXT_CNTL 0x0280 -# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) -# define RADEON_DAC2_FORCE_DATA_EN (1 << 1) -# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) -# define RADEON_DAC_FORCE_DATA_EN (1 << 5) -# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) -# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) -# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 -# define RADEON_DAC_FORCE_DATA_SHIFT 8 -#define RADEON_DAC_MACRO_CNTL 0x0d04 -# define RADEON_DAC_PDWN_R (1 << 16) -# define RADEON_DAC_PDWN_G (1 << 17) -# define RADEON_DAC_PDWN_B (1 << 18) -#define RADEON_TV_DAC_CNTL 0x088c -# define RADEON_TV_DAC_NBLANK (1 << 0) -# define RADEON_TV_DAC_NHOLD (1 << 1) -# define RADEON_TV_DAC_PEDESTAL (1 << 2) -# define RADEON_TV_MONITOR_DETECT_EN (1 << 4) -# define RADEON_TV_DAC_CMPOUT (1 << 5) -# define RADEON_TV_DAC_STD_MASK (3 << 8) -# define RADEON_TV_DAC_STD_PAL (0 << 8) -# define RADEON_TV_DAC_STD_NTSC (1 << 8) -# define RADEON_TV_DAC_STD_PS2 (2 << 8) -# define RADEON_TV_DAC_STD_RS343 (3 << 8) -# define RADEON_TV_DAC_BGSLEEP (1 << 6) -# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) -# define RADEON_TV_DAC_BGADJ_SHIFT 16 -# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) -# define RADEON_TV_DAC_DACADJ_SHIFT 20 -# define RADEON_TV_DAC_RDACPD (1 << 24) -# define RADEON_TV_DAC_GDACPD (1 << 25) -# define RADEON_TV_DAC_BDACPD (1 << 26) -# define RADEON_TV_DAC_RDACDET (1 << 29) -# define RADEON_TV_DAC_GDACDET (1 << 30) -# define RADEON_TV_DAC_BDACDET (1 << 31) -# define R420_TV_DAC_DACADJ_MASK (0x1f << 20) -# define R420_TV_DAC_RDACPD (1 << 25) -# define R420_TV_DAC_GDACPD (1 << 26) -# define R420_TV_DAC_BDACPD (1 << 27) -# define R420_TV_DAC_TVENABLE (1 << 28) -#define RADEON_DISP_HW_DEBUG 0x0d14 -# define RADEON_CRT2_DISP1_SEL (1 << 5) -#define RADEON_DISP_OUTPUT_CNTL 0x0d64 -# define RADEON_DISP_DAC_SOURCE_MASK 0x03 -# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c -# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 -# define RADEON_DISP_DAC_SOURCE_RMX 0x02 -# define RADEON_DISP_DAC_SOURCE_LTU 0x03 -# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 -# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) -# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 -# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) -# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) -# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) -# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) -# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) -# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) -# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) -# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ -# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ -#define RADEON_DISP_TV_OUT_CNTL 0x0d6c -# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) -# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) -#define RADEON_DAC_CRC_SIG 0x02cc -#define RADEON_DAC_DATA 0x03c9 /* VGA */ -#define RADEON_DAC_MASK 0x03c6 /* VGA */ -#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ -#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ -#define RADEON_DDA_CONFIG 0x02e0 -#define RADEON_DDA_ON_OFF 0x02e4 -#define RADEON_DEFAULT_OFFSET 0x16e0 -#define RADEON_DEFAULT_PITCH 0x16e4 -#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 -# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) -#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 -#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 -#define RADEON_DEVICE_ID 0x0f02 /* PCI */ -#define RADEON_DISP_MISC_CNTL 0x0d00 -# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) -#define RADEON_DISP_MERGE_CNTL 0x0d60 -# define RADEON_DISP_ALPHA_MODE_MASK 0x03 -# define RADEON_DISP_ALPHA_MODE_KEY 0 -# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 -# define RADEON_DISP_ALPHA_MODE_GLOBAL 2 -# define RADEON_DISP_RGB_OFFSET_EN (1 << 8) -# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) -# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) -# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) -#define RADEON_DISP2_MERGE_CNTL 0x0d68 -# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) -#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 -#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 -#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 -#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c -#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 -#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 -#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 -#define RADEON_DP_BRUSH_FRGD_CLR 0x147c -#define RADEON_DP_CNTL 0x16c0 -# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) -# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) -# define RADEON_DP_DST_TILE_LINEAR (0 << 3) -# define RADEON_DP_DST_TILE_MACRO (1 << 3) -# define RADEON_DP_DST_TILE_MICRO (2 << 3) -# define RADEON_DP_DST_TILE_BOTH (3 << 3) -#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 -# define RADEON_DST_Y_MAJOR (1 << 2) -# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) -# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) -#define RADEON_DP_DATATYPE 0x16c4 -# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) -#define RADEON_DP_GUI_MASTER_CNTL 0x146c -# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) -# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) -# define RADEON_GMC_SRC_CLIPPING (1 << 2) -# define RADEON_GMC_DST_CLIPPING (1 << 3) -# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) -# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) -# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) -# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) -# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) -# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) -# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) -# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) -# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) -# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) -# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) -# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) -# define RADEON_GMC_BRUSH_NONE (15 << 4) -# define RADEON_GMC_DST_8BPP_CI (2 << 8) -# define RADEON_GMC_DST_15BPP (3 << 8) -# define RADEON_GMC_DST_16BPP (4 << 8) -# define RADEON_GMC_DST_24BPP (5 << 8) -# define RADEON_GMC_DST_32BPP (6 << 8) -# define RADEON_GMC_DST_8BPP_RGB (7 << 8) -# define RADEON_GMC_DST_Y8 (8 << 8) -# define RADEON_GMC_DST_RGB8 (9 << 8) -# define RADEON_GMC_DST_VYUY (11 << 8) -# define RADEON_GMC_DST_YVYU (12 << 8) -# define RADEON_GMC_DST_AYUV444 (14 << 8) -# define RADEON_GMC_DST_ARGB4444 (15 << 8) -# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) -# define RADEON_GMC_DST_DATATYPE_SHIFT 8 -# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) -# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) -# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) -# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) -# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) -# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) -# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) -# define RADEON_GMC_CONVERSION_TEMP (1 << 15) -# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) -# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) -# define RADEON_GMC_ROP3_MASK (0xff << 16) -# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) -# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) -# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) -# define RADEON_GMC_3D_FCN_EN (1 << 27) -# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) -# define RADEON_GMC_WR_MSK_DIS (1 << 30) -# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) -# define RADEON_ROP3_ZERO 0x00000000 -# define RADEON_ROP3_DSa 0x00880000 -# define RADEON_ROP3_SDna 0x00440000 -# define RADEON_ROP3_S 0x00cc0000 -# define RADEON_ROP3_DSna 0x00220000 -# define RADEON_ROP3_D 0x00aa0000 -# define RADEON_ROP3_DSx 0x00660000 -# define RADEON_ROP3_DSo 0x00ee0000 -# define RADEON_ROP3_DSon 0x00110000 -# define RADEON_ROP3_DSxn 0x00990000 -# define RADEON_ROP3_Dn 0x00550000 -# define RADEON_ROP3_SDno 0x00dd0000 -# define RADEON_ROP3_Sn 0x00330000 -# define RADEON_ROP3_DSno 0x00bb0000 -# define RADEON_ROP3_DSan 0x00770000 -# define RADEON_ROP3_ONE 0x00ff0000 -# define RADEON_ROP3_DPa 0x00a00000 -# define RADEON_ROP3_PDna 0x00500000 -# define RADEON_ROP3_P 0x00f00000 -# define RADEON_ROP3_DPna 0x000a0000 -# define RADEON_ROP3_D 0x00aa0000 -# define RADEON_ROP3_DPx 0x005a0000 -# define RADEON_ROP3_DPo 0x00fa0000 -# define RADEON_ROP3_DPon 0x00050000 -# define RADEON_ROP3_PDxn 0x00a50000 -# define RADEON_ROP3_PDno 0x00f50000 -# define RADEON_ROP3_Pn 0x000f0000 -# define RADEON_ROP3_DPno 0x00af0000 -# define RADEON_ROP3_DPan 0x005f0000 -#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 -#define RADEON_DP_MIX 0x16c8 -#define RADEON_DP_SRC_BKGD_CLR 0x15dc -#define RADEON_DP_SRC_FRGD_CLR 0x15d8 -#define RADEON_DP_WRITE_MASK 0x16cc -#define RADEON_DST_BRES_DEC 0x1630 -#define RADEON_DST_BRES_ERR 0x1628 -#define RADEON_DST_BRES_INC 0x162c -#define RADEON_DST_BRES_LNTH 0x1634 -#define RADEON_DST_BRES_LNTH_SUB 0x1638 -#define RADEON_DST_HEIGHT 0x1410 -#define RADEON_DST_HEIGHT_WIDTH 0x143c -#define RADEON_DST_HEIGHT_WIDTH_8 0x158c -#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 -#define RADEON_DST_HEIGHT_Y 0x15a0 -#define RADEON_DST_LINE_START 0x1600 -#define RADEON_DST_LINE_END 0x1604 -#define RADEON_DST_LINE_PATCOUNT 0x1608 -# define RADEON_BRES_CNTL_SHIFT 8 -#define RADEON_DST_OFFSET 0x1404 -#define RADEON_DST_PITCH 0x1408 -#define RADEON_DST_PITCH_OFFSET 0x142c -#define RADEON_DST_PITCH_OFFSET_C 0x1c80 -# define RADEON_PITCH_SHIFT 21 -# define RADEON_DST_TILE_LINEAR (0 << 30) -# define RADEON_DST_TILE_MACRO (1 << 30) -# define RADEON_DST_TILE_MICRO (2 << 30) -# define RADEON_DST_TILE_BOTH (3 << 30) -#define RADEON_DST_WIDTH 0x140c -#define RADEON_DST_WIDTH_HEIGHT 0x1598 -#define RADEON_DST_WIDTH_X 0x1588 -#define RADEON_DST_WIDTH_X_INCY 0x159c -#define RADEON_DST_X 0x141c -#define RADEON_DST_X_SUB 0x15a4 -#define RADEON_DST_X_Y 0x1594 -#define RADEON_DST_Y 0x1420 -#define RADEON_DST_Y_SUB 0x15a8 -#define RADEON_DST_Y_X 0x1438 - -#define RADEON_FCP_CNTL 0x0910 -# define RADEON_FCP0_SRC_PCICLK 0 -# define RADEON_FCP0_SRC_PCLK 1 -# define RADEON_FCP0_SRC_PCLKb 2 -# define RADEON_FCP0_SRC_HREF 3 -# define RADEON_FCP0_SRC_GND 4 -# define RADEON_FCP0_SRC_HREFb 5 -#define RADEON_FLUSH_1 0x1704 -#define RADEON_FLUSH_2 0x1708 -#define RADEON_FLUSH_3 0x170c -#define RADEON_FLUSH_4 0x1710 -#define RADEON_FLUSH_5 0x1714 -#define RADEON_FLUSH_6 0x1718 -#define RADEON_FLUSH_7 0x171c -#define RADEON_FOG_3D_TABLE_START 0x1810 -#define RADEON_FOG_3D_TABLE_END 0x1814 -#define RADEON_FOG_3D_TABLE_DENSITY 0x181c -#define RADEON_FOG_TABLE_INDEX 0x1a14 -#define RADEON_FOG_TABLE_DATA 0x1a18 -#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 -#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 -# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff -# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 -# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff -# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 -# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 -# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff -# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 -# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 -# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 -# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 -# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 -# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 -# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 -# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 -#define RADEON_FP_GEN_CNTL 0x0284 -# define RADEON_FP_FPON (1 << 0) -# define RADEON_FP_BLANK_EN (1 << 1) -# define RADEON_FP_TMDS_EN (1 << 2) -# define RADEON_FP_PANEL_FORMAT (1 << 3) -# define RADEON_FP_EN_TMDS (1 << 7) -# define RADEON_FP_DETECT_SENSE (1 << 8) -# define R200_FP_SOURCE_SEL_MASK (3 << 10) -# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) -# define R200_FP_SOURCE_SEL_RMX (2 << 10) -# define R200_FP_SOURCE_SEL_TRANS (3 << 10) -# define RADEON_FP_SEL_CRTC1 (0 << 13) -# define RADEON_FP_SEL_CRTC2 (1 << 13) -# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) -# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) -# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -# define RADEON_FP_DFP_SYNC_SEL (1 << 21) -# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) -# define RADEON_FP_CRT_SYNC_SEL (1 << 23) -# define RADEON_FP_USE_SHADOW_EN (1 << 24) -# define RADEON_FP_CRT_SYNC_ALT (1 << 26) -#define RADEON_FP2_GEN_CNTL 0x0288 -# define RADEON_FP2_BLANK_EN (1 << 1) -# define RADEON_FP2_ON (1 << 2) -# define RADEON_FP2_PANEL_FORMAT (1 << 3) -# define RADEON_FP2_DETECT_SENSE (1 << 8) -# define R200_FP2_SOURCE_SEL_MASK (3 << 10) -# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) -# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) -# define R200_FP2_SOURCE_SEL_RMX (2 << 10) -# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) -# define RADEON_FP2_SRC_SEL_MASK (3 << 13) -# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) -# define RADEON_FP2_FP_POL (1 << 16) -# define RADEON_FP2_LP_POL (1 << 17) -# define RADEON_FP2_SCK_POL (1 << 18) -# define RADEON_FP2_LCD_CNTL_MASK (7 << 19) -# define RADEON_FP2_PAD_FLOP_EN (1 << 22) -# define RADEON_FP2_CRC_EN (1 << 23) -# define RADEON_FP2_CRC_READ_EN (1 << 24) -# define RADEON_FP2_DVO_EN (1 << 25) -# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) -# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) -# define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) -# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) -#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 -#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 -#define RADEON_FP_HORZ_STRETCH 0x028c -#define RADEON_FP_HORZ2_STRETCH 0x038c -# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff -# define RADEON_HORZ_STRETCH_RATIO_MAX 4096 -# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) -# define RADEON_HORZ_PANEL_SHIFT 16 -# define RADEON_HORZ_STRETCH_PIXREP (0 << 25) -# define RADEON_HORZ_STRETCH_BLEND (1 << 26) -# define RADEON_HORZ_STRETCH_ENABLE (1 << 25) -# define RADEON_HORZ_AUTO_RATIO (1 << 27) -# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) -# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) -#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 -#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 -#define RADEON_FP_VERT_STRETCH 0x0290 -#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 -#define RADEON_FP_VERT2_STRETCH 0x0390 -# define RADEON_VERT_PANEL_SIZE (0xfff << 12) -# define RADEON_VERT_PANEL_SHIFT 12 -# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff -# define RADEON_VERT_STRETCH_RATIO_SHIFT 0 -# define RADEON_VERT_STRETCH_RATIO_MAX 4096 -# define RADEON_VERT_STRETCH_ENABLE (1 << 25) -# define RADEON_VERT_STRETCH_LINEREP (0 << 26) -# define RADEON_VERT_STRETCH_BLEND (1 << 26) -# define RADEON_VERT_AUTO_RATIO_EN (1 << 27) -# define RADEON_VERT_AUTO_RATIO_INC (1 << 31) -# define RADEON_VERT_STRETCH_RESERVED 0x71000000 -#define RS400_FP_2ND_GEN_CNTL 0x0384 -# define RS400_FP_2ND_ON (1 << 0) -# define RS400_FP_2ND_BLANK_EN (1 << 1) -# define RS400_TMDS_2ND_EN (1 << 2) -# define RS400_PANEL_FORMAT_2ND (1 << 3) -# define RS400_FP_2ND_EN_TMDS (1 << 7) -# define RS400_FP_2ND_DETECT_SENSE (1 << 8) -# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) -# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) -# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) -# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) -# define RS400_FP_2ND_DETECT_EN (1 << 12) -# define RS400_HPD_2ND_SEL (1 << 13) -#define RS400_FP2_2_GEN_CNTL 0x0388 -# define RS400_FP2_2_BLANK_EN (1 << 1) -# define RS400_FP2_2_ON (1 << 2) -# define RS400_FP2_2_PANEL_FORMAT (1 << 3) -# define RS400_FP2_2_DETECT_SENSE (1 << 8) -# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) -# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) -# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) -# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) -# define RS400_FP2_2_DVO2_EN (1 << 25) -#define RS400_TMDS2_CNTL 0x0394 -#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 -# define RS400_TMDS2_PLLEN (1 << 0) -# define RS400_TMDS2_PLLRST (1 << 1) - -#define RADEON_GEN_INT_CNTL 0x0040 -#define RADEON_GEN_INT_STATUS 0x0044 -# define RADEON_VSYNC_INT_AK (1 << 2) -# define RADEON_VSYNC_INT (1 << 2) -# define RADEON_VSYNC2_INT_AK (1 << 6) -# define RADEON_VSYNC2_INT (1 << 6) -#define RADEON_GENENB 0x03c3 /* VGA */ -#define RADEON_GENFC_RD 0x03ca /* VGA */ -#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ -#define RADEON_GENMO_RD 0x03cc /* VGA */ -#define RADEON_GENMO_WT 0x03c2 /* VGA */ -#define RADEON_GENS0 0x03c2 /* VGA */ -#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ -#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ -#define RADEON_GPIO_MONIDB 0x006c -#define RADEON_GPIO_CRT2_DDC 0x006c -#define RADEON_GPIO_DVI_DDC 0x0064 -#define RADEON_GPIO_VGA_DDC 0x0060 -# define RADEON_GPIO_A_0 (1 << 0) -# define RADEON_GPIO_A_1 (1 << 1) -# define RADEON_GPIO_Y_0 (1 << 8) -# define RADEON_GPIO_Y_1 (1 << 9) -# define RADEON_GPIO_Y_SHIFT_0 8 -# define RADEON_GPIO_Y_SHIFT_1 9 -# define RADEON_GPIO_EN_0 (1 << 16) -# define RADEON_GPIO_EN_1 (1 << 17) -# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ -# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ -#define RADEON_GRPH8_DATA 0x03cf /* VGA */ -#define RADEON_GRPH8_IDX 0x03ce /* VGA */ -#define RADEON_GUI_SCRATCH_REG0 0x15e0 -#define RADEON_GUI_SCRATCH_REG1 0x15e4 -#define RADEON_GUI_SCRATCH_REG2 0x15e8 -#define RADEON_GUI_SCRATCH_REG3 0x15ec -#define RADEON_GUI_SCRATCH_REG4 0x15f0 -#define RADEON_GUI_SCRATCH_REG5 0x15f4 - -#define RADEON_HEADER 0x0f0e /* PCI */ -#define RADEON_HOST_DATA0 0x17c0 -#define RADEON_HOST_DATA1 0x17c4 -#define RADEON_HOST_DATA2 0x17c8 -#define RADEON_HOST_DATA3 0x17cc -#define RADEON_HOST_DATA4 0x17d0 -#define RADEON_HOST_DATA5 0x17d4 -#define RADEON_HOST_DATA6 0x17d8 -#define RADEON_HOST_DATA7 0x17dc -#define RADEON_HOST_DATA_LAST 0x17e0 -#define RADEON_HOST_PATH_CNTL 0x0130 -# define RADEON_HDP_SOFT_RESET (1 << 26) -# define RADEON_HDP_APER_CNTL (1 << 23) -#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ -# define RADEON_HTOT_CNTL_VGA_EN (1 << 28) -#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ - - /* Multimedia I2C bus */ -#define RADEON_I2C_CNTL_0 0x0090 -#define RADEON_I2C_DONE (1<<0) -#define RADEON_I2C_NACK (1<<1) -#define RADEON_I2C_HALT (1<<2) -#define RADEON_I2C_SOFT_RST (1<<5) -#define RADEON_I2C_DRIVE_EN (1<<6) -#define RADEON_I2C_DRIVE_SEL (1<<7) -#define RADEON_I2C_START (1<<8) -#define RADEON_I2C_STOP (1<<9) -#define RADEON_I2C_RECEIVE (1<<10) -#define RADEON_I2C_ABORT (1<<11) -#define RADEON_I2C_GO (1<<12) -#define RADEON_I2C_CNTL_1 0x0094 -#define RADEON_I2C_SEL (1<<16) -#define RADEON_I2C_EN (1<<17) -#define RADEON_I2C_DATA 0x0098 - -#define RADEON_DVI_I2C_CNTL_0 0x02e0 -#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ -#define RADEON_DVI_I2C_DATA 0x02e8 - -#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ -#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ -#define RADEON_IO_BASE 0x0f14 /* PCI */ - -#define RADEON_LATENCY 0x0f0d /* PCI */ -#define RADEON_LEAD_BRES_DEC 0x1608 -#define RADEON_LEAD_BRES_LNTH 0x161c -#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 -#define RADEON_LVDS_GEN_CNTL 0x02d0 -# define RADEON_LVDS_ON (1 << 0) -# define RADEON_LVDS_DISPLAY_DIS (1 << 1) -# define RADEON_LVDS_PANEL_TYPE (1 << 2) -# define RADEON_LVDS_PANEL_FORMAT (1 << 3) -# define RADEON_LVDS_RST_FM (1 << 6) -# define RADEON_LVDS_EN (1 << 7) -# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 -# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) -# define RADEON_LVDS_BL_MOD_EN (1 << 16) -# define RADEON_LVDS_DIGON (1 << 18) -# define RADEON_LVDS_BLON (1 << 19) -# define RADEON_LVDS_SEL_CRTC2 (1 << 23) -#define RADEON_LVDS_PLL_CNTL 0x02d4 -# define RADEON_HSYNC_DELAY_SHIFT 28 -# define RADEON_HSYNC_DELAY_MASK (0xf << 28) -# define RADEON_LVDS_PLL_EN (1 << 16) -# define RADEON_LVDS_PLL_RESET (1 << 17) -# define R300_LVDS_SRC_SEL_MASK (3 << 18) -# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) -# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) -# define R300_LVDS_SRC_SEL_RMX (2 << 18) - -#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ -#define RADEON_MC_AGP_LOCATION 0x014c -#define RADEON_MC_FB_LOCATION 0x0148 -#define RADEON_DISPLAY_BASE_ADDR 0x23c -#define RADEON_DISPLAY2_BASE_ADDR 0x33c -#define RADEON_OV0_BASE_ADDR 0x43c -#define RADEON_NB_TOM 0x15c -#define R300_MC_INIT_MISC_LAT_TIMER 0x180 -# define R300_MC_DISP0R_INIT_LAT_SHIFT 8 -# define R300_MC_DISP0R_INIT_LAT_MASK 0xf -# define R300_MC_DISP1R_INIT_LAT_SHIFT 12 -# define R300_MC_DISP1R_INIT_LAT_MASK 0xf -#define RADEON_MCLK_CNTL 0x0012 /* PLL */ -# define RADEON_FORCEON_MCLKA (1 << 16) -# define RADEON_FORCEON_MCLKB (1 << 17) -# define RADEON_FORCEON_YCLKA (1 << 18) -# define RADEON_FORCEON_YCLKB (1 << 19) -# define RADEON_FORCEON_MC (1 << 20) -# define RADEON_FORCEON_AIC (1 << 21) -# define R300_DISABLE_MC_MCLKA (1 << 21) -# define R300_DISABLE_MC_MCLKB (1 << 21) -#define RADEON_MCLK_MISC 0x001f /* PLL */ -# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) -# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) -# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) -# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) -#define RADEON_LCD_GPIO_MASK 0x01a0 -#define RADEON_GPIOPAD_EN 0x01a0 -#define RADEON_LCD_GPIO_Y_REG 0x01a4 -#define RADEON_MDGPIO_A_REG 0x01ac -#define RADEON_MDGPIO_EN_REG 0x01b0 -#define RADEON_MDGPIO_MASK 0x0198 -#define RADEON_GPIOPAD_MASK 0x0198 -#define RADEON_GPIOPAD_A 0x019c -#define RADEON_MDGPIO_Y_REG 0x01b4 -#define RADEON_MEM_ADDR_CONFIG 0x0148 -#define RADEON_MEM_BASE 0x0f10 /* PCI */ -#define RADEON_MEM_CNTL 0x0140 -# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 -# define RADEON_MEM_USE_B_CH_ONLY (1 << 1) -# define RV100_HALF_MODE (1 << 3) -# define R300_MEM_NUM_CHANNELS_MASK 0x03 -# define R300_MEM_USE_CD_CH_ONLY (1 << 2) -#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ -#define RADEON_MEM_INIT_LAT_TIMER 0x0154 -#define RADEON_MEM_INTF_CNTL 0x014c -#define RADEON_MEM_SDRAM_MODE_REG 0x0158 -# define RADEON_SDRAM_MODE_MASK 0xffff0000 -# define RADEON_B3MEM_RESET_MASK 0x6fffffff -# define RADEON_MEM_CFG_TYPE_DDR (1 << 30) -#define RADEON_MEM_STR_CNTL 0x0150 -# define RADEON_MEM_PWRUP_COMPL_A (1 << 0) -# define RADEON_MEM_PWRUP_COMPL_B (1 << 1) -# define R300_MEM_PWRUP_COMPL_C (1 << 2) -# define R300_MEM_PWRUP_COMPL_D (1 << 3) -# define RADEON_MEM_PWRUP_COMPLETE 0x03 -# define R300_MEM_PWRUP_COMPLETE 0x0f -#define RADEON_MC_STATUS 0x0150 -# define RADEON_MC_IDLE (1 << 2) -# define R300_MC_IDLE (1 << 4) -#define RADEON_MEM_VGA_RP_SEL 0x003c -#define RADEON_MEM_VGA_WP_SEL 0x0038 -#define RADEON_MIN_GRANT 0x0f3e /* PCI */ -#define RADEON_MM_DATA 0x0004 -#define RADEON_MM_INDEX 0x0000 -#define RADEON_MPLL_CNTL 0x000e /* PLL */ -#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ -#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ -#define RADEON_SEPROM_CNTL1 0x01c0 -# define RADEON_SCK_PRESCALE_SHIFT 24 -# define RADEON_SCK_PRESCALE_MASK (0xff << 24) -#define R300_MC_IND_INDEX 0x01f8 -# define R300_MC_IND_ADDR_MASK 0x3f -# define R300_MC_IND_WR_EN (1 << 8) -#define R300_MC_IND_DATA 0x01fc -#define R300_MC_READ_CNTL_AB 0x017c -# define R300_MEM_RBS_POSITION_A_MASK 0x03 -#define R300_MC_READ_CNTL_CD_mcind 0x24 -# define R300_MEM_RBS_POSITION_C_MASK 0x03 - -#define RADEON_N_VIF_COUNT 0x0248 - -#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 -# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 -# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 -# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 -# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 -# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 -# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 -# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 - -#define RADEON_OV0_COLOUR_CNTL 0x04E0 -#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 -#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 -# define RADEON_EXCL_HORZ_START_MASK 0x000000ff -# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 -# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 -# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 -#define RADEON_OV0_EXCLUSIVE_VERT 0x040C -# define RADEON_EXCL_VERT_START_MASK 0x000003ff -# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 -#define RADEON_OV0_FILTER_CNTL 0x04A0 -# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 -# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 -# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 -# define RADEON_FILTER_HC_COEF_VERT_Y 0x4 -# define RADEON_FILTER_HC_COEF_VERT_UV 0x8 -# define RADEON_FILTER_HARDCODED_COEF 0xf -# define RADEON_FILTER_COEF_MASK 0xf - -#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 -#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 -#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 -#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC -#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 -#define RADEON_OV0_FLAG_CNTL 0x04DC -#define RADEON_OV0_GAMMA_000_00F 0x0d40 -#define RADEON_OV0_GAMMA_010_01F 0x0d44 -#define RADEON_OV0_GAMMA_020_03F 0x0d48 -#define RADEON_OV0_GAMMA_040_07F 0x0d4c -#define RADEON_OV0_GAMMA_080_0BF 0x0e00 -#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 -#define RADEON_OV0_GAMMA_100_13F 0x0e08 -#define RADEON_OV0_GAMMA_140_17F 0x0e0c -#define RADEON_OV0_GAMMA_180_1BF 0x0e10 -#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 -#define RADEON_OV0_GAMMA_200_23F 0x0e18 -#define RADEON_OV0_GAMMA_240_27F 0x0e1c -#define RADEON_OV0_GAMMA_280_2BF 0x0e20 -#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 -#define RADEON_OV0_GAMMA_300_33F 0x0e28 -#define RADEON_OV0_GAMMA_340_37F 0x0e2c -#define RADEON_OV0_GAMMA_380_3BF 0x0d50 -#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 -#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC -#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 -#define RADEON_OV0_H_INC 0x0480 -#define RADEON_OV0_KEY_CNTL 0x04F4 -# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L -# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L -# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L -# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L -# define RADEON_VIDEO_KEY_FN_NE 0x00000003L -# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L -# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L -# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L -# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L -# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L -# define RADEON_CMP_MIX_MASK 0x00000100L -# define RADEON_CMP_MIX_OR 0x00000000L -# define RADEON_CMP_MIX_AND 0x00000100L -#define RADEON_OV0_LIN_TRANS_A 0x0d20 -#define RADEON_OV0_LIN_TRANS_B 0x0d24 -#define RADEON_OV0_LIN_TRANS_C 0x0d28 -#define RADEON_OV0_LIN_TRANS_D 0x0d2c -#define RADEON_OV0_LIN_TRANS_E 0x0d30 -#define RADEON_OV0_LIN_TRANS_F 0x0d34 -#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 -# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL -# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L -#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 -#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 -# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L -# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L -#define RADEON_OV0_P1_X_START_END 0x0494 -#define RADEON_OV0_P2_X_START_END 0x0498 -#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 -# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL -# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L -#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C -#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C -#define RADEON_OV0_P3_X_START_END 0x049C -#define RADEON_OV0_REG_LOAD_CNTL 0x0410 -# define RADEON_REG_LD_CTL_LOCK 0x00000001L -# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L -# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L -# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L -# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L -#define RADEON_OV0_SCALE_CNTL 0x0420 -# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L -# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L -# define RADEON_SCALER_SIGNED_UV 0x00000010L -# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L -# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L -# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L -# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L -# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L -# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L -# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L -# define RADEON_SCALER_SOURCE_15BPP 0x00000300L -# define RADEON_SCALER_SOURCE_16BPP 0x00000400L -# define RADEON_SCALER_SOURCE_32BPP 0x00000600L -# define RADEON_SCALER_SOURCE_YUV9 0x00000900L -# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L -# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L -# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L -# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L -# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L -# define RADEON_SCALER_CRTC_SEL 0x00004000L -# define RADEON_SCALER_SMART_SWITCH 0x00008000L -# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L -# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L -# define RADEON_SCALER_DIS_LIMIT 0x08000000L -# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L -# define RADEON_SCALER_INT_EMU 0x20000000L -# define RADEON_SCALER_ENABLE 0x40000000L -# define RADEON_SCALER_SOFT_RESET 0x80000000L -#define RADEON_OV0_STEP_BY 0x0484 -#define RADEON_OV0_TEST 0x04F8 -#define RADEON_OV0_V_INC 0x0424 -#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 -# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L -#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 -# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L -#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 -# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L -# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L -# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L -# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L -#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C -#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 -#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 -#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 -#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 -#define RADEON_OV0_Y_X_START 0x0400 -#define RADEON_OV0_Y_X_END 0x0404 -#define RADEON_OV1_Y_X_START 0x0600 -#define RADEON_OV1_Y_X_END 0x0604 -#define RADEON_OVR_CLR 0x0230 -#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 -#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 - -/* first capture unit */ - -#define RADEON_CAP0_BUF0_OFFSET 0x0920 -#define RADEON_CAP0_BUF1_OFFSET 0x0924 -#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 -#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C - -#define RADEON_CAP0_BUF_PITCH 0x0930 -#define RADEON_CAP0_V_WINDOW 0x0934 -#define RADEON_CAP0_H_WINDOW 0x0938 -#define RADEON_CAP0_VBI0_OFFSET 0x093C -#define RADEON_CAP0_VBI1_OFFSET 0x0940 -#define RADEON_CAP0_VBI_V_WINDOW 0x0944 -#define RADEON_CAP0_VBI_H_WINDOW 0x0948 -#define RADEON_CAP0_PORT_MODE_CNTL 0x094C -#define RADEON_CAP0_TRIG_CNTL 0x0950 -#define RADEON_CAP0_DEBUG 0x0954 -#define RADEON_CAP0_CONFIG 0x0958 -# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 -# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 -# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 -# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 -# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 -# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 -# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 -# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 -# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 -# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 -# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 -# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 -# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 -# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 -# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 -# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 -# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 -# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 -# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 -# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 -# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 -# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 -# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 -# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 -# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 -# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 -# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 -# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 -# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 -# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 -# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 -# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 -# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 -#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C -#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 -#define RADEON_CAP0_ANC_H_WINDOW 0x0964 -#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 -#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C -#define RADEON_CAP0_BUF_STATUS 0x0970 -/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ -/* #define RADEON_CAP0_XSHARPNESS 0x097C */ -#define RADEON_CAP0_VBI2_OFFSET 0x0980 -#define RADEON_CAP0_VBI3_OFFSET 0x0984 -#define RADEON_CAP0_ANC2_OFFSET 0x0988 -#define RADEON_CAP0_ANC3_OFFSET 0x098C -#define RADEON_VID_BUFFER_CONTROL 0x0900 - -/* second capture unit */ - -#define RADEON_CAP1_BUF0_OFFSET 0x0990 -#define RADEON_CAP1_BUF1_OFFSET 0x0994 -#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 -#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C - -#define RADEON_CAP1_BUF_PITCH 0x09A0 -#define RADEON_CAP1_V_WINDOW 0x09A4 -#define RADEON_CAP1_H_WINDOW 0x09A8 -#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC -#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 -#define RADEON_CAP1_VBI_V_WINDOW 0x09B4 -#define RADEON_CAP1_VBI_H_WINDOW 0x09B8 -#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC -#define RADEON_CAP1_TRIG_CNTL 0x09C0 -#define RADEON_CAP1_DEBUG 0x09C4 -#define RADEON_CAP1_CONFIG 0x09C8 -#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC -#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 -#define RADEON_CAP1_ANC_H_WINDOW 0x09D4 -#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 -#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC -#define RADEON_CAP1_BUF_STATUS 0x09E0 -#define RADEON_CAP1_DWNSC_XRATIO 0x09E8 -#define RADEON_CAP1_XSHARPNESS 0x09EC - -/* misc multimedia registers */ - -#define RADEON_IDCT_RUNS 0x1F80 -#define RADEON_IDCT_LEVELS 0x1F84 -#define RADEON_IDCT_CONTROL 0x1FBC -#define RADEON_IDCT_AUTH_CONTROL 0x1F88 -#define RADEON_IDCT_AUTH 0x1F8C - -#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ -# define RADEON_P2PLL_RESET (1 << 0) -# define RADEON_P2PLL_SLEEP (1 << 1) -# define RADEON_P2PLL_PVG_MASK (7 << 11) -# define RADEON_P2PLL_PVG_SHIFT 11 -# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) -# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define RADEON_P2PLL_DIV_0 0x002c -# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff -# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 -#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ -# define RADEON_P2PLL_REF_DIV_MASK 0x03ff -# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ -# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) -# define R300_PPLL_REF_DIV_ACC_SHIFT 18 -#define RADEON_PALETTE_DATA 0x00b4 -#define RADEON_PALETTE_30_DATA 0x00b8 -#define RADEON_PALETTE_INDEX 0x00b0 -#define RADEON_PCI_GART_PAGE 0x017c -#define RADEON_PIXCLKS_CNTL 0x002d -# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 -# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 -# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 -# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 -# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 -# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) -# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) -# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) -# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -# define R300_DVOCLK_ALWAYS_ONb (1 << 10) -# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) -# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) -# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) -# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) -# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -# define R300_P2G2CLK_ALWAYS_ONb (1 << 18) -# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) -#define RADEON_PLANE_3D_MASK_C 0x1d44 -#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ -# define RADEON_PLL_MASK_READ_B (1 << 9) -#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ -#define RADEON_PMI_DATA 0x0f63 /* PCI */ -#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ -#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ -#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ -#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ -#define RADEON_PPLL_CNTL 0x0002 /* PLL */ -# define RADEON_PPLL_RESET (1 << 0) -# define RADEON_PPLL_SLEEP (1 << 1) -# define RADEON_PPLL_PVG_MASK (7 << 11) -# define RADEON_PPLL_PVG_SHIFT 11 -# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) -# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ -#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ -#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ -#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ -# define RADEON_PPLL_FB3_DIV_MASK 0x07ff -# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 -#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ -# define RADEON_PPLL_REF_DIV_MASK 0x03ff -# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ -#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ - -#define RADEON_RBBM_GUICNTL 0x172c -# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) -# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) -# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) -# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) -#define RADEON_RBBM_SOFT_RESET 0x00f0 -# define RADEON_SOFT_RESET_CP (1 << 0) -# define RADEON_SOFT_RESET_HI (1 << 1) -# define RADEON_SOFT_RESET_SE (1 << 2) -# define RADEON_SOFT_RESET_RE (1 << 3) -# define RADEON_SOFT_RESET_PP (1 << 4) -# define RADEON_SOFT_RESET_E2 (1 << 5) -# define RADEON_SOFT_RESET_RB (1 << 6) -# define RADEON_SOFT_RESET_HDP (1 << 7) -#define RADEON_RBBM_STATUS 0x0e40 -# define RADEON_RBBM_FIFOCNT_MASK 0x007f -# define RADEON_RBBM_ACTIVE (1 << 31) -#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c -# define RADEON_RB2D_DC_FLUSH (3 << 0) -# define RADEON_RB2D_DC_FREE (3 << 2) -# define RADEON_RB2D_DC_FLUSH_ALL 0xf -# define RADEON_RB2D_DC_BUSY (1 << 31) -#define RADEON_RB2D_DSTCACHE_MODE 0x3428 -#define RADEON_DSTCACHE_CTLSTAT 0x1714 - -#define RADEON_RB3D_ZCACHE_MODE 0x3250 -#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 -# define RADEON_RB3D_ZC_FLUSH_ALL 0x5 -#define RADEON_RB3D_DSTCACHE_MODE 0x3258 -# define RADEON_RB3D_DC_CACHE_ENABLE (0) -# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) -# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) -# define RADEON_RB3D_DC_CACHE_DISABLE (3) -# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) -# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) -# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) -# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) -# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) -# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) -# define RADEON_RB3D_DC_FORCE_RMW (1 << 16) -# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) -# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) - -#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C -# define RADEON_RB3D_DC_FLUSH (3 << 0) -# define RADEON_RB3D_DC_FREE (3 << 2) -# define RADEON_RB3D_DC_FLUSH_ALL 0xf -# define RADEON_RB3D_DC_BUSY (1 << 31) - -#define RADEON_REG_BASE 0x0f18 /* PCI */ -#define RADEON_REGPROG_INF 0x0f09 /* PCI */ -#define RADEON_REVISION_ID 0x0f08 /* PCI */ - -#define RADEON_SC_BOTTOM 0x164c -#define RADEON_SC_BOTTOM_RIGHT 0x16f0 -#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c -#define RADEON_SC_LEFT 0x1640 -#define RADEON_SC_RIGHT 0x1644 -#define RADEON_SC_TOP 0x1648 -#define RADEON_SC_TOP_LEFT 0x16ec -#define RADEON_SC_TOP_LEFT_C 0x1c88 -# define RADEON_SC_SIGN_MASK_LO 0x8000 -# define RADEON_SC_SIGN_MASK_HI 0x80000000 -#define RADEON_SCLK_CNTL 0x000d /* PLL */ -# define RADEON_SCLK_SRC_SEL_MASK 0x0007 -# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 -# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 -# define RADEON_SCLK_FORCEON_MASK 0xffff8000 -# define RADEON_SCLK_FORCE_DISP2 (1<<15) -# define RADEON_SCLK_FORCE_CP (1<<16) -# define RADEON_SCLK_FORCE_HDP (1<<17) -# define RADEON_SCLK_FORCE_DISP1 (1<<18) -# define RADEON_SCLK_FORCE_TOP (1<<19) -# define RADEON_SCLK_FORCE_E2 (1<<20) -# define RADEON_SCLK_FORCE_SE (1<<21) -# define RADEON_SCLK_FORCE_IDCT (1<<22) -# define RADEON_SCLK_FORCE_VIP (1<<23) -# define RADEON_SCLK_FORCE_RE (1<<24) -# define RADEON_SCLK_FORCE_PB (1<<25) -# define RADEON_SCLK_FORCE_TAM (1<<26) -# define RADEON_SCLK_FORCE_TDM (1<<27) -# define RADEON_SCLK_FORCE_RB (1<<28) -# define RADEON_SCLK_FORCE_TV_SCLK (1<<29) -# define RADEON_SCLK_FORCE_SUBPIC (1<<30) -# define RADEON_SCLK_FORCE_OV0 (1<<31) -# define R300_SCLK_FORCE_VAP (1<<21) -# define R300_SCLK_FORCE_SR (1<<25) -# define R300_SCLK_FORCE_PX (1<<26) -# define R300_SCLK_FORCE_TX (1<<27) -# define R300_SCLK_FORCE_US (1<<28) -# define R300_SCLK_FORCE_SU (1<<30) -#define R300_SCLK_CNTL2 0x1e /* PLL */ -# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) -# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) -# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) -# define R300_SCLK_FORCE_TCL (1<<13) -# define R300_SCLK_FORCE_CBA (1<<14) -# define R300_SCLK_FORCE_GA (1<<15) -#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ -# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 -# define RADEON_SCLK_MORE_FORCEON 0x0700 -#define RADEON_SDRAM_MODE_REG 0x0158 -#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ -#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ -#define RADEON_SNAPSHOT_F_COUNT 0x0244 -#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 -#define RADEON_SNAPSHOT_VIF_COUNT 0x024c -#define RADEON_SRC_OFFSET 0x15ac -#define RADEON_SRC_PITCH 0x15b0 -#define RADEON_SRC_PITCH_OFFSET 0x1428 -#define RADEON_SRC_SC_BOTTOM 0x165c -#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 -#define RADEON_SRC_SC_RIGHT 0x1654 -#define RADEON_SRC_X 0x1414 -#define RADEON_SRC_X_Y 0x1590 -#define RADEON_SRC_Y 0x1418 -#define RADEON_SRC_Y_X 0x1434 -#define RADEON_STATUS 0x0f06 /* PCI */ -#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ -#define RADEON_SUB_CLASS 0x0f0a /* PCI */ -#define RADEON_SURFACE_CNTL 0x0b00 -# define RADEON_SURF_TRANSLATION_DIS (1 << 8) -# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) -# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) -# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) -# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) -#define RADEON_SURFACE0_INFO 0x0b0c -# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) -# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) -# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) -# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) -# define R200_SURF_TILE_NONE (0 << 16) -# define R200_SURF_TILE_COLOR_MACRO (1 << 16) -# define R200_SURF_TILE_COLOR_MICRO (2 << 16) -# define R200_SURF_TILE_COLOR_BOTH (3 << 16) -# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) -# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) -# define R300_SURF_TILE_NONE (0 << 16) -# define R300_SURF_TILE_COLOR_MACRO (1 << 16) -# define R300_SURF_TILE_DEPTH_32BPP (2 << 16) -# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) -# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) -# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) -# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) -#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 -#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 -#define RADEON_SURFACE1_INFO 0x0b1c -#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 -#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 -#define RADEON_SURFACE2_INFO 0x0b2c -#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 -#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 -#define RADEON_SURFACE3_INFO 0x0b3c -#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 -#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 -#define RADEON_SURFACE4_INFO 0x0b4c -#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 -#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 -#define RADEON_SURFACE5_INFO 0x0b5c -#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 -#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 -#define RADEON_SURFACE6_INFO 0x0b6c -#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 -#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 -#define RADEON_SURFACE7_INFO 0x0b7c -#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 -#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 -#define RADEON_SW_SEMAPHORE 0x013c - -#define RADEON_TEST_DEBUG_CNTL 0x0120 -#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 - -#define RADEON_TEST_DEBUG_MUX 0x0124 -#define RADEON_TEST_DEBUG_OUT 0x012c -#define RADEON_TMDS_PLL_CNTL 0x02a8 -#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 -# define RADEON_TMDS_TRANSMITTER_PLLEN 1 -# define RADEON_TMDS_TRANSMITTER_PLLRST 2 -#define RADEON_TRAIL_BRES_DEC 0x1614 -#define RADEON_TRAIL_BRES_ERR 0x160c -#define RADEON_TRAIL_BRES_INC 0x1610 -#define RADEON_TRAIL_X 0x1618 -#define RADEON_TRAIL_X_SUB 0x1620 - -#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ -# define RADEON_VCLK_SRC_SEL_MASK 0x03 -# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 -# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 -# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 -# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 -# define RADEON_PIXCLK_ALWAYS_ONb (1<<6) -# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) -# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) - -#define RADEON_VENDOR_ID 0x0f00 /* PCI */ -#define RADEON_VGA_DDA_CONFIG 0x02e8 -#define RADEON_VGA_DDA_ON_OFF 0x02ec -#define RADEON_VID_BUFFER_CONTROL 0x0900 -#define RADEON_VIDEOMUX_CNTL 0x0190 - - /* VIP bus */ -#define RADEON_VIPH_CH0_DATA 0x0c00 -#define RADEON_VIPH_CH1_DATA 0x0c04 -#define RADEON_VIPH_CH2_DATA 0x0c08 -#define RADEON_VIPH_CH3_DATA 0x0c0c -#define RADEON_VIPH_CH0_ADDR 0x0c10 -#define RADEON_VIPH_CH1_ADDR 0x0c14 -#define RADEON_VIPH_CH2_ADDR 0x0c18 -#define RADEON_VIPH_CH3_ADDR 0x0c1c -#define RADEON_VIPH_CH0_SBCNT 0x0c20 -#define RADEON_VIPH_CH1_SBCNT 0x0c24 -#define RADEON_VIPH_CH2_SBCNT 0x0c28 -#define RADEON_VIPH_CH3_SBCNT 0x0c2c -#define RADEON_VIPH_CH0_ABCNT 0x0c30 -#define RADEON_VIPH_CH1_ABCNT 0x0c34 -#define RADEON_VIPH_CH2_ABCNT 0x0c38 -#define RADEON_VIPH_CH3_ABCNT 0x0c3c -#define RADEON_VIPH_CONTROL 0x0c40 -# define RADEON_VIP_BUSY 0 -# define RADEON_VIP_IDLE 1 -# define RADEON_VIP_RESET 2 -# define RADEON_VIPH_EN (1 << 21) -#define RADEON_VIPH_DV_LAT 0x0c44 -#define RADEON_VIPH_BM_CHUNK 0x0c48 -#define RADEON_VIPH_DV_INT 0x0c4c -#define RADEON_VIPH_TIMEOUT_STAT 0x0c50 -#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 -#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 -#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 - -#define RADEON_VIPH_REG_DATA 0x0084 -#define RADEON_VIPH_REG_ADDR 0x0080 - - -#define RADEON_WAIT_UNTIL 0x1720 -# define RADEON_WAIT_CRTC_PFLIP (1 << 0) -# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) -# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) -# define RADEON_WAIT_CRTC_VLINE (1 << 3) -# define RADEON_WAIT_DMA_VID_IDLE (1 << 8) -# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) -# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ -# define RADEON_WAIT_OV0_FLIP (1 << 11) -# define RADEON_WAIT_AGP_FLUSH (1 << 13) -# define RADEON_WAIT_2D_IDLE (1 << 14) -# define RADEON_WAIT_3D_IDLE (1 << 15) -# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) -# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) -# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) -# define RADEON_CMDFIFO_ENTRIES_SHIFT 10 -# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f -# define RADEON_WAIT_VAP_IDLE (1 << 28) -# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) -# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) -# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) - -#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ -#define RADEON_XCLK_CNTL 0x000d /* PLL */ -#define RADEON_XDLL_CNTL 0x000c /* PLL */ -#define RADEON_XPLL_CNTL 0x000b /* PLL */ - - - - /* Registers for 3D/TCL */ -#define RADEON_PP_BORDER_COLOR_0 0x1d40 -#define RADEON_PP_BORDER_COLOR_1 0x1d44 -#define RADEON_PP_BORDER_COLOR_2 0x1d48 -#define RADEON_PP_CNTL 0x1c38 -# define RADEON_STIPPLE_ENABLE (1 << 0) -# define RADEON_SCISSOR_ENABLE (1 << 1) -# define RADEON_PATTERN_ENABLE (1 << 2) -# define RADEON_SHADOW_ENABLE (1 << 3) -# define RADEON_TEX_ENABLE_MASK (0xf << 4) -# define RADEON_TEX_0_ENABLE (1 << 4) -# define RADEON_TEX_1_ENABLE (1 << 5) -# define RADEON_TEX_2_ENABLE (1 << 6) -# define RADEON_TEX_3_ENABLE (1 << 7) -# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) -# define RADEON_TEX_BLEND_0_ENABLE (1 << 12) -# define RADEON_TEX_BLEND_1_ENABLE (1 << 13) -# define RADEON_TEX_BLEND_2_ENABLE (1 << 14) -# define RADEON_TEX_BLEND_3_ENABLE (1 << 15) -# define RADEON_PLANAR_YUV_ENABLE (1 << 20) -# define RADEON_SPECULAR_ENABLE (1 << 21) -# define RADEON_FOG_ENABLE (1 << 22) -# define RADEON_ALPHA_TEST_ENABLE (1 << 23) -# define RADEON_ANTI_ALIAS_NONE (0 << 24) -# define RADEON_ANTI_ALIAS_LINE (1 << 24) -# define RADEON_ANTI_ALIAS_POLY (2 << 24) -# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) -# define RADEON_BUMP_MAP_ENABLE (1 << 26) -# define RADEON_BUMPED_MAP_T0 (0 << 27) -# define RADEON_BUMPED_MAP_T1 (1 << 27) -# define RADEON_BUMPED_MAP_T2 (2 << 27) -# define RADEON_TEX_3D_ENABLE_0 (1 << 29) -# define RADEON_TEX_3D_ENABLE_1 (1 << 30) -# define RADEON_MC_ENABLE (1 << 31) -#define RADEON_PP_FOG_COLOR 0x1c18 -# define RADEON_FOG_COLOR_MASK 0x00ffffff -# define RADEON_FOG_VERTEX (0 << 24) -# define RADEON_FOG_TABLE (1 << 24) -# define RADEON_FOG_USE_DEPTH (0 << 25) -# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) -# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) -#define RADEON_PP_LUM_MATRIX 0x1d00 -#define RADEON_PP_MISC 0x1c14 -# define RADEON_REF_ALPHA_MASK 0x000000ff -# define RADEON_ALPHA_TEST_FAIL (0 << 8) -# define RADEON_ALPHA_TEST_LESS (1 << 8) -# define RADEON_ALPHA_TEST_LEQUAL (2 << 8) -# define RADEON_ALPHA_TEST_EQUAL (3 << 8) -# define RADEON_ALPHA_TEST_GEQUAL (4 << 8) -# define RADEON_ALPHA_TEST_GREATER (5 << 8) -# define RADEON_ALPHA_TEST_NEQUAL (6 << 8) -# define RADEON_ALPHA_TEST_PASS (7 << 8) -# define RADEON_ALPHA_TEST_OP_MASK (7 << 8) -# define RADEON_CHROMA_FUNC_FAIL (0 << 16) -# define RADEON_CHROMA_FUNC_PASS (1 << 16) -# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) -# define RADEON_CHROMA_FUNC_EQUAL (3 << 16) -# define RADEON_CHROMA_KEY_NEAREST (0 << 18) -# define RADEON_CHROMA_KEY_ZERO (1 << 18) -# define RADEON_SHADOW_ID_AUTO_INC (1 << 20) -# define RADEON_SHADOW_FUNC_EQUAL (0 << 21) -# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) -# define RADEON_SHADOW_PASS_1 (0 << 22) -# define RADEON_SHADOW_PASS_2 (1 << 22) -# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) -# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) -#define RADEON_PP_ROT_MATRIX_0 0x1d58 -#define RADEON_PP_ROT_MATRIX_1 0x1d5c -#define RADEON_PP_TXFILTER_0 0x1c54 -#define RADEON_PP_TXFILTER_1 0x1c6c -#define RADEON_PP_TXFILTER_2 0x1c84 -# define RADEON_MAG_FILTER_NEAREST (0 << 0) -# define RADEON_MAG_FILTER_LINEAR (1 << 0) -# define RADEON_MAG_FILTER_MASK (1 << 0) -# define RADEON_MIN_FILTER_NEAREST (0 << 1) -# define RADEON_MIN_FILTER_LINEAR (1 << 1) -# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) -# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) -# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) -# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) -# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) -# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) -# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) -# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) -# define RADEON_MIN_FILTER_MASK (15 << 1) -# define RADEON_MAX_ANISO_1_TO_1 (0 << 5) -# define RADEON_MAX_ANISO_2_TO_1 (1 << 5) -# define RADEON_MAX_ANISO_4_TO_1 (2 << 5) -# define RADEON_MAX_ANISO_8_TO_1 (3 << 5) -# define RADEON_MAX_ANISO_16_TO_1 (4 << 5) -# define RADEON_MAX_ANISO_MASK (7 << 5) -# define RADEON_LOD_BIAS_MASK (0xff << 8) -# define RADEON_LOD_BIAS_SHIFT 8 -# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) -# define RADEON_MAX_MIP_LEVEL_SHIFT 16 -# define RADEON_YUV_TO_RGB (1 << 20) -# define RADEON_YUV_TEMPERATURE_COOL (0 << 21) -# define RADEON_YUV_TEMPERATURE_HOT (1 << 21) -# define RADEON_YUV_TEMPERATURE_MASK (1 << 21) -# define RADEON_WRAPEN_S (1 << 22) -# define RADEON_CLAMP_S_WRAP (0 << 23) -# define RADEON_CLAMP_S_MIRROR (1 << 23) -# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) -# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) -# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) -# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) -# define RADEON_CLAMP_S_CLAMP_GL (6 << 23) -# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) -# define RADEON_CLAMP_S_MASK (7 << 23) -# define RADEON_WRAPEN_T (1 << 26) -# define RADEON_CLAMP_T_WRAP (0 << 27) -# define RADEON_CLAMP_T_MIRROR (1 << 27) -# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) -# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) -# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) -# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) -# define RADEON_CLAMP_T_CLAMP_GL (6 << 27) -# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) -# define RADEON_CLAMP_T_MASK (7 << 27) -# define RADEON_BORDER_MODE_OGL (0 << 31) -# define RADEON_BORDER_MODE_D3D (1 << 31) -#define RADEON_PP_TXFORMAT_0 0x1c58 -#define RADEON_PP_TXFORMAT_1 0x1c70 -#define RADEON_PP_TXFORMAT_2 0x1c88 -# define RADEON_TXFORMAT_I8 (0 << 0) -# define RADEON_TXFORMAT_AI88 (1 << 0) -# define RADEON_TXFORMAT_RGB332 (2 << 0) -# define RADEON_TXFORMAT_ARGB1555 (3 << 0) -# define RADEON_TXFORMAT_RGB565 (4 << 0) -# define RADEON_TXFORMAT_ARGB4444 (5 << 0) -# define RADEON_TXFORMAT_ARGB8888 (6 << 0) -# define RADEON_TXFORMAT_RGBA8888 (7 << 0) -# define RADEON_TXFORMAT_Y8 (8 << 0) -# define RADEON_TXFORMAT_VYUY422 (10 << 0) -# define RADEON_TXFORMAT_YVYU422 (11 << 0) -# define RADEON_TXFORMAT_DXT1 (12 << 0) -# define RADEON_TXFORMAT_DXT23 (14 << 0) -# define RADEON_TXFORMAT_DXT45 (15 << 0) -# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) -# define RADEON_TXFORMAT_FORMAT_SHIFT 0 -# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) -# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) -# define RADEON_TXFORMAT_NON_POWER2 (1 << 7) -# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) -# define RADEON_TXFORMAT_WIDTH_SHIFT 8 -# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) -# define RADEON_TXFORMAT_HEIGHT_SHIFT 12 -# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) -# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 -# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) -# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 -# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) -# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) -# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) -# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) -# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) -# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) -# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) -# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) -# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) -# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) -# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) -# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) -#define RADEON_PP_CUBIC_FACES_0 0x1d24 -#define RADEON_PP_CUBIC_FACES_1 0x1d28 -#define RADEON_PP_CUBIC_FACES_2 0x1d2c -# define RADEON_FACE_WIDTH_1_SHIFT 0 -# define RADEON_FACE_HEIGHT_1_SHIFT 4 -# define RADEON_FACE_WIDTH_1_MASK (0xf << 0) -# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) -# define RADEON_FACE_WIDTH_2_SHIFT 8 -# define RADEON_FACE_HEIGHT_2_SHIFT 12 -# define RADEON_FACE_WIDTH_2_MASK (0xf << 8) -# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) -# define RADEON_FACE_WIDTH_3_SHIFT 16 -# define RADEON_FACE_HEIGHT_3_SHIFT 20 -# define RADEON_FACE_WIDTH_3_MASK (0xf << 16) -# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) -# define RADEON_FACE_WIDTH_4_SHIFT 24 -# define RADEON_FACE_HEIGHT_4_SHIFT 28 -# define RADEON_FACE_WIDTH_4_MASK (0xf << 24) -# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) - -#define RADEON_PP_TXOFFSET_0 0x1c5c -#define RADEON_PP_TXOFFSET_1 0x1c74 -#define RADEON_PP_TXOFFSET_2 0x1c8c -# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) -# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) -# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) -# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) -# define RADEON_TXO_MACRO_LINEAR (0 << 2) -# define RADEON_TXO_MACRO_TILE (1 << 2) -# define RADEON_TXO_MICRO_LINEAR (0 << 3) -# define RADEON_TXO_MICRO_TILE_X2 (1 << 3) -# define RADEON_TXO_MICRO_TILE_OPT (2 << 3) -# define RADEON_TXO_OFFSET_MASK 0xffffffe0 -# define RADEON_TXO_OFFSET_SHIFT 5 - -#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ -#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 -#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 -#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc -#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 -#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 -#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 -#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 -#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c -#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 -#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 -#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 -#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c -#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 -#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 - -#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ -#define RADEON_PP_TEX_SIZE_1 0x1d0c -#define RADEON_PP_TEX_SIZE_2 0x1d14 -# define RADEON_TEX_USIZE_MASK (0x7ff << 0) -# define RADEON_TEX_USIZE_SHIFT 0 -# define RADEON_TEX_VSIZE_MASK (0x7ff << 16) -# define RADEON_TEX_VSIZE_SHIFT 16 -# define RADEON_SIGNED_RGB_MASK (1 << 30) -# define RADEON_SIGNED_RGB_SHIFT 30 -# define RADEON_SIGNED_ALPHA_MASK (1 << 31) -# define RADEON_SIGNED_ALPHA_SHIFT 31 -#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ -#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ -#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ -/* note: bits 13-5: 32 byte aligned stride of texture map */ - -#define RADEON_PP_TXCBLEND_0 0x1c60 -#define RADEON_PP_TXCBLEND_1 0x1c78 -#define RADEON_PP_TXCBLEND_2 0x1c90 -# define RADEON_COLOR_ARG_A_SHIFT 0 -# define RADEON_COLOR_ARG_A_MASK (0x1f << 0) -# define RADEON_COLOR_ARG_A_ZERO (0 << 0) -# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) -# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) -# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) -# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) -# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) -# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) -# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) -# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) -# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) -# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) -# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) -# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) -# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) -# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) -# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) -# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) -# define RADEON_COLOR_ARG_B_SHIFT 5 -# define RADEON_COLOR_ARG_B_MASK (0x1f << 5) -# define RADEON_COLOR_ARG_B_ZERO (0 << 5) -# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) -# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) -# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) -# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) -# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) -# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) -# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) -# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) -# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) -# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) -# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) -# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) -# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) -# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) -# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) -# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) -# define RADEON_COLOR_ARG_C_SHIFT 10 -# define RADEON_COLOR_ARG_C_MASK (0x1f << 10) -# define RADEON_COLOR_ARG_C_ZERO (0 << 10) -# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) -# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) -# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) -# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) -# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) -# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) -# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) -# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) -# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) -# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) -# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) -# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) -# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) -# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) -# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) -# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) -# define RADEON_COMP_ARG_A (1 << 15) -# define RADEON_COMP_ARG_A_SHIFT 15 -# define RADEON_COMP_ARG_B (1 << 16) -# define RADEON_COMP_ARG_B_SHIFT 16 -# define RADEON_COMP_ARG_C (1 << 17) -# define RADEON_COMP_ARG_C_SHIFT 17 -# define RADEON_BLEND_CTL_MASK (7 << 18) -# define RADEON_BLEND_CTL_ADD (0 << 18) -# define RADEON_BLEND_CTL_SUBTRACT (1 << 18) -# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) -# define RADEON_BLEND_CTL_BLEND (3 << 18) -# define RADEON_BLEND_CTL_DOT3 (4 << 18) -# define RADEON_SCALE_SHIFT 21 -# define RADEON_SCALE_MASK (3 << 21) -# define RADEON_SCALE_1X (0 << 21) -# define RADEON_SCALE_2X (1 << 21) -# define RADEON_SCALE_4X (2 << 21) -# define RADEON_CLAMP_TX (1 << 23) -# define RADEON_T0_EQ_TCUR (1 << 24) -# define RADEON_T1_EQ_TCUR (1 << 25) -# define RADEON_T2_EQ_TCUR (1 << 26) -# define RADEON_T3_EQ_TCUR (1 << 27) -# define RADEON_COLOR_ARG_MASK 0x1f -# define RADEON_COMP_ARG_SHIFT 15 -#define RADEON_PP_TXABLEND_0 0x1c64 -#define RADEON_PP_TXABLEND_1 0x1c7c -#define RADEON_PP_TXABLEND_2 0x1c94 -# define RADEON_ALPHA_ARG_A_SHIFT 0 -# define RADEON_ALPHA_ARG_A_MASK (0xf << 0) -# define RADEON_ALPHA_ARG_A_ZERO (0 << 0) -# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) -# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) -# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) -# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) -# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) -# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) -# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) -# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) -# define RADEON_ALPHA_ARG_B_SHIFT 4 -# define RADEON_ALPHA_ARG_B_MASK (0xf << 4) -# define RADEON_ALPHA_ARG_B_ZERO (0 << 4) -# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) -# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) -# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) -# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) -# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) -# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) -# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) -# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) -# define RADEON_ALPHA_ARG_C_SHIFT 8 -# define RADEON_ALPHA_ARG_C_MASK (0xf << 8) -# define RADEON_ALPHA_ARG_C_ZERO (0 << 8) -# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) -# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) -# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) -# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) -# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) -# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) -# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) -# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) -# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) -# define RADEON_ALPHA_ARG_MASK 0xf - -#define RADEON_PP_TFACTOR_0 0x1c68 -#define RADEON_PP_TFACTOR_1 0x1c80 -#define RADEON_PP_TFACTOR_2 0x1c98 - -#define RADEON_RB3D_BLENDCNTL 0x1c20 -# define RADEON_COMB_FCN_MASK (3 << 12) -# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) -# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) -# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) -# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) -# define RADEON_SRC_BLEND_GL_ZERO (32 << 16) -# define RADEON_SRC_BLEND_GL_ONE (33 << 16) -# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) -# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) -# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) -# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) -# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) -# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) -# define RADEON_SRC_BLEND_MASK (63 << 16) -# define RADEON_DST_BLEND_GL_ZERO (32 << 24) -# define RADEON_DST_BLEND_GL_ONE (33 << 24) -# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) -# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) -# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) -# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) -# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) -# define RADEON_DST_BLEND_MASK (63 << 24) -#define RADEON_RB3D_CNTL 0x1c3c -# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) -# define RADEON_PLANE_MASK_ENABLE (1 << 1) -# define RADEON_DITHER_ENABLE (1 << 2) -# define RADEON_ROUND_ENABLE (1 << 3) -# define RADEON_SCALE_DITHER_ENABLE (1 << 4) -# define RADEON_DITHER_INIT (1 << 5) -# define RADEON_ROP_ENABLE (1 << 6) -# define RADEON_STENCIL_ENABLE (1 << 7) -# define RADEON_Z_ENABLE (1 << 8) -# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) -# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) -# define RADEON_COLOR_FORMAT_RGB565 (4 << 10) -# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) -# define RADEON_COLOR_FORMAT_RGB332 (7 << 10) -# define RADEON_COLOR_FORMAT_Y8 (8 << 10) -# define RADEON_COLOR_FORMAT_RGB8 (9 << 10) -# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) -# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) -# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) -# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) -# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) -#define RADEON_RB3D_COLOROFFSET 0x1c40 -# define RADEON_COLOROFFSET_MASK 0xfffffff0 -#define RADEON_RB3D_COLORPITCH 0x1c48 -# define RADEON_COLORPITCH_MASK 0x000001ff8 -# define RADEON_COLOR_TILE_ENABLE (1 << 16) -# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) -# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) -# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) -# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) -#define RADEON_RB3D_DEPTHOFFSET 0x1c24 -#define RADEON_RB3D_DEPTHPITCH 0x1c28 -# define RADEON_DEPTHPITCH_MASK 0x00001ff8 -# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) -# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) -# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) -#define RADEON_RB3D_PLANEMASK 0x1d84 -#define RADEON_RB3D_ROPCNTL 0x1d80 -# define RADEON_ROP_MASK (15 << 8) -# define RADEON_ROP_CLEAR (0 << 8) -# define RADEON_ROP_NOR (1 << 8) -# define RADEON_ROP_AND_INVERTED (2 << 8) -# define RADEON_ROP_COPY_INVERTED (3 << 8) -# define RADEON_ROP_AND_REVERSE (4 << 8) -# define RADEON_ROP_INVERT (5 << 8) -# define RADEON_ROP_XOR (6 << 8) -# define RADEON_ROP_NAND (7 << 8) -# define RADEON_ROP_AND (8 << 8) -# define RADEON_ROP_EQUIV (9 << 8) -# define RADEON_ROP_NOOP (10 << 8) -# define RADEON_ROP_OR_INVERTED (11 << 8) -# define RADEON_ROP_COPY (12 << 8) -# define RADEON_ROP_OR_REVERSE (13 << 8) -# define RADEON_ROP_OR (14 << 8) -# define RADEON_ROP_SET (15 << 8) -#define RADEON_RB3D_STENCILREFMASK 0x1d7c -# define RADEON_STENCIL_REF_SHIFT 0 -# define RADEON_STENCIL_REF_MASK (0xff << 0) -# define RADEON_STENCIL_MASK_SHIFT 16 -# define RADEON_STENCIL_VALUE_MASK (0xff << 16) -# define RADEON_STENCIL_WRITEMASK_SHIFT 24 -# define RADEON_STENCIL_WRITE_MASK (0xff << 24) -#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c -# define RADEON_DEPTH_FORMAT_MASK (0xf << 0) -# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) -# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) -# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) -# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) -# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) -# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) -# define RADEON_Z_TEST_NEVER (0 << 4) -# define RADEON_Z_TEST_LESS (1 << 4) -# define RADEON_Z_TEST_LEQUAL (2 << 4) -# define RADEON_Z_TEST_EQUAL (3 << 4) -# define RADEON_Z_TEST_GEQUAL (4 << 4) -# define RADEON_Z_TEST_GREATER (5 << 4) -# define RADEON_Z_TEST_NEQUAL (6 << 4) -# define RADEON_Z_TEST_ALWAYS (7 << 4) -# define RADEON_Z_TEST_MASK (7 << 4) -# define RADEON_STENCIL_TEST_NEVER (0 << 12) -# define RADEON_STENCIL_TEST_LESS (1 << 12) -# define RADEON_STENCIL_TEST_LEQUAL (2 << 12) -# define RADEON_STENCIL_TEST_EQUAL (3 << 12) -# define RADEON_STENCIL_TEST_GEQUAL (4 << 12) -# define RADEON_STENCIL_TEST_GREATER (5 << 12) -# define RADEON_STENCIL_TEST_NEQUAL (6 << 12) -# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) -# define RADEON_STENCIL_TEST_MASK (0x7 << 12) -# define RADEON_STENCIL_FAIL_KEEP (0 << 16) -# define RADEON_STENCIL_FAIL_ZERO (1 << 16) -# define RADEON_STENCIL_FAIL_REPLACE (2 << 16) -# define RADEON_STENCIL_FAIL_INC (3 << 16) -# define RADEON_STENCIL_FAIL_DEC (4 << 16) -# define RADEON_STENCIL_FAIL_INVERT (5 << 16) -# define RADEON_STENCIL_FAIL_MASK (0x7 << 16) -# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) -# define RADEON_STENCIL_ZPASS_ZERO (1 << 20) -# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) -# define RADEON_STENCIL_ZPASS_INC (3 << 20) -# define RADEON_STENCIL_ZPASS_DEC (4 << 20) -# define RADEON_STENCIL_ZPASS_INVERT (5 << 20) -# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) -# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) -# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) -# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) -# define RADEON_STENCIL_ZFAIL_INC (3 << 24) -# define RADEON_STENCIL_ZFAIL_DEC (4 << 24) -# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) -# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) -# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) -# define RADEON_FORCE_Z_DIRTY (1 << 29) -# define RADEON_Z_WRITE_ENABLE (1 << 30) -#define RADEON_RE_LINE_PATTERN 0x1cd0 -# define RADEON_LINE_PATTERN_MASK 0x0000ffff -# define RADEON_LINE_REPEAT_COUNT_SHIFT 16 -# define RADEON_LINE_PATTERN_START_SHIFT 24 -# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) -# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) -# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) -#define RADEON_RE_LINE_STATE 0x1cd4 -# define RADEON_LINE_CURRENT_PTR_SHIFT 0 -# define RADEON_LINE_CURRENT_COUNT_SHIFT 8 -#define RADEON_RE_MISC 0x26c4 -# define RADEON_STIPPLE_COORD_MASK 0x1f -# define RADEON_STIPPLE_X_OFFSET_SHIFT 0 -# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) -# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 -# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) -# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) -# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) -#define RADEON_RE_SOLID_COLOR 0x1c1c -#define RADEON_RE_TOP_LEFT 0x26c0 -# define RADEON_RE_LEFT_SHIFT 0 -# define RADEON_RE_TOP_SHIFT 16 -#define RADEON_RE_WIDTH_HEIGHT 0x1c44 -# define RADEON_RE_WIDTH_SHIFT 0 -# define RADEON_RE_HEIGHT_SHIFT 16 - -#define RADEON_SE_CNTL 0x1c4c -# define RADEON_FFACE_CULL_CW (0 << 0) -# define RADEON_FFACE_CULL_CCW (1 << 0) -# define RADEON_FFACE_CULL_DIR_MASK (1 << 0) -# define RADEON_BFACE_CULL (0 << 1) -# define RADEON_BFACE_SOLID (3 << 1) -# define RADEON_FFACE_CULL (0 << 3) -# define RADEON_FFACE_SOLID (3 << 3) -# define RADEON_FFACE_CULL_MASK (3 << 3) -# define RADEON_BADVTX_CULL_DISABLE (1 << 5) -# define RADEON_FLAT_SHADE_VTX_0 (0 << 6) -# define RADEON_FLAT_SHADE_VTX_1 (1 << 6) -# define RADEON_FLAT_SHADE_VTX_2 (2 << 6) -# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) -# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) -# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) -# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) -# define RADEON_DIFFUSE_SHADE_MASK (3 << 8) -# define RADEON_ALPHA_SHADE_SOLID (0 << 10) -# define RADEON_ALPHA_SHADE_FLAT (1 << 10) -# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) -# define RADEON_ALPHA_SHADE_MASK (3 << 10) -# define RADEON_SPECULAR_SHADE_SOLID (0 << 12) -# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) -# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) -# define RADEON_SPECULAR_SHADE_MASK (3 << 12) -# define RADEON_FOG_SHADE_SOLID (0 << 14) -# define RADEON_FOG_SHADE_FLAT (1 << 14) -# define RADEON_FOG_SHADE_GOURAUD (2 << 14) -# define RADEON_FOG_SHADE_MASK (3 << 14) -# define RADEON_ZBIAS_ENABLE_POINT (1 << 16) -# define RADEON_ZBIAS_ENABLE_LINE (1 << 17) -# define RADEON_ZBIAS_ENABLE_TRI (1 << 18) -# define RADEON_WIDELINE_ENABLE (1 << 20) -# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) -# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) -# define RADEON_VTX_PIX_CENTER_D3D (0 << 27) -# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) -# define RADEON_ROUND_MODE_TRUNC (0 << 28) -# define RADEON_ROUND_MODE_ROUND (1 << 28) -# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) -# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) -# define RADEON_ROUND_PREC_16TH_PIX (0 << 30) -# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) -# define RADEON_ROUND_PREC_4TH_PIX (2 << 30) -# define RADEON_ROUND_PREC_HALF_PIX (3 << 30) -#define R200_RE_CNTL 0x1c50 -# define R200_STIPPLE_ENABLE 0x1 -# define R200_SCISSOR_ENABLE 0x2 -# define R200_PATTERN_ENABLE 0x4 -# define R200_PERSPECTIVE_ENABLE 0x8 -# define R200_POINT_SMOOTH 0x20 -# define R200_VTX_STQ0_D3D 0x00010000 -# define R200_VTX_STQ1_D3D 0x00040000 -# define R200_VTX_STQ2_D3D 0x00100000 -# define R200_VTX_STQ3_D3D 0x00400000 -# define R200_VTX_STQ4_D3D 0x01000000 -# define R200_VTX_STQ5_D3D 0x04000000 -#define RADEON_SE_CNTL_STATUS 0x2140 -# define RADEON_VC_NO_SWAP (0 << 0) -# define RADEON_VC_16BIT_SWAP (1 << 0) -# define RADEON_VC_32BIT_SWAP (2 << 0) -# define RADEON_VC_HALF_DWORD_SWAP (3 << 0) -# define RADEON_TCL_BYPASS (1 << 8) -#define RADEON_SE_COORD_FMT 0x1c50 -# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) -# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) -# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) -# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) -# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) -# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) -# define RADEON_VTX_W0_NORMALIZE (1 << 12) -# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) -# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) -# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) -# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) -# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) -# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) -# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) -#define RADEON_SE_LINE_WIDTH 0x1db8 -#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c -# define RADEON_LIGHTING_ENABLE (1 << 0) -# define RADEON_LIGHT_IN_MODELSPACE (1 << 1) -# define RADEON_LOCAL_VIEWER (1 << 2) -# define RADEON_NORMALIZE_NORMALS (1 << 3) -# define RADEON_RESCALE_NORMALS (1 << 4) -# define RADEON_SPECULAR_LIGHTS (1 << 5) -# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) -# define RADEON_LIGHT_ALPHA (1 << 7) -# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) -# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) -# define RADEON_LM_SOURCE_STATE_PREMULT 0 -# define RADEON_LM_SOURCE_STATE_MULT 1 -# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 -# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 -# define RADEON_EMISSIVE_SOURCE_SHIFT 16 -# define RADEON_AMBIENT_SOURCE_SHIFT 18 -# define RADEON_DIFFUSE_SOURCE_SHIFT 20 -# define RADEON_SPECULAR_SOURCE_SHIFT 22 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 -#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 -#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 -#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c -#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 -#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 -#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 -#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c -#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c -# define RADEON_MODELVIEW_0_SHIFT 0 -# define RADEON_MODELVIEW_1_SHIFT 4 -# define RADEON_MODELVIEW_2_SHIFT 8 -# define RADEON_MODELVIEW_3_SHIFT 12 -# define RADEON_IT_MODELVIEW_0_SHIFT 16 -# define RADEON_IT_MODELVIEW_1_SHIFT 20 -# define RADEON_IT_MODELVIEW_2_SHIFT 24 -# define RADEON_IT_MODELVIEW_3_SHIFT 28 -#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 -# define RADEON_MODELPROJECT_0_SHIFT 0 -# define RADEON_MODELPROJECT_1_SHIFT 4 -# define RADEON_MODELPROJECT_2_SHIFT 8 -# define RADEON_MODELPROJECT_3_SHIFT 12 -# define RADEON_TEXMAT_0_SHIFT 16 -# define RADEON_TEXMAT_1_SHIFT 20 -# define RADEON_TEXMAT_2_SHIFT 24 -# define RADEON_TEXMAT_3_SHIFT 28 - - -#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 -# define RADEON_TCL_VTX_W0 (1 << 0) -# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) -# define RADEON_TCL_VTX_FP_ALPHA (1 << 2) -# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) -# define RADEON_TCL_VTX_FP_SPEC (1 << 4) -# define RADEON_TCL_VTX_FP_FOG (1 << 5) -# define RADEON_TCL_VTX_PK_SPEC (1 << 6) -# define RADEON_TCL_VTX_ST0 (1 << 7) -# define RADEON_TCL_VTX_ST1 (1 << 8) -# define RADEON_TCL_VTX_Q1 (1 << 9) -# define RADEON_TCL_VTX_ST2 (1 << 10) -# define RADEON_TCL_VTX_Q2 (1 << 11) -# define RADEON_TCL_VTX_ST3 (1 << 12) -# define RADEON_TCL_VTX_Q3 (1 << 13) -# define RADEON_TCL_VTX_Q0 (1 << 14) -# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 -# define RADEON_TCL_VTX_NORM0 (1 << 18) -# define RADEON_TCL_VTX_XY1 (1 << 27) -# define RADEON_TCL_VTX_Z1 (1 << 28) -# define RADEON_TCL_VTX_W1 (1 << 29) -# define RADEON_TCL_VTX_NORM1 (1 << 30) -# define RADEON_TCL_VTX_Z0 (1 << 31) - -#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 -# define RADEON_TCL_COMPUTE_XYZW (1 << 0) -# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) -# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) -# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) -# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) -# define RADEON_TCL_TEX_INPUT_TEX_0 0 -# define RADEON_TCL_TEX_INPUT_TEX_1 1 -# define RADEON_TCL_TEX_INPUT_TEX_2 2 -# define RADEON_TCL_TEX_INPUT_TEX_3 3 -# define RADEON_TCL_TEX_COMPUTED_TEX_0 8 -# define RADEON_TCL_TEX_COMPUTED_TEX_1 9 -# define RADEON_TCL_TEX_COMPUTED_TEX_2 10 -# define RADEON_TCL_TEX_COMPUTED_TEX_3 11 -# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 -# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 -# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 -# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 - -#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 -# define RADEON_LIGHT_0_ENABLE (1 << 0) -# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) -# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) -# define RADEON_LIGHT_0_IS_LOCAL (1 << 3) -# define RADEON_LIGHT_0_IS_SPOT (1 << 4) -# define RADEON_LIGHT_0_DUAL_CONE (1 << 5) -# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) -# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) -# define RADEON_LIGHT_0_SHIFT 0 -# define RADEON_LIGHT_1_ENABLE (1 << 16) -# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) -# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) -# define RADEON_LIGHT_1_IS_LOCAL (1 << 19) -# define RADEON_LIGHT_1_IS_SPOT (1 << 20) -# define RADEON_LIGHT_1_DUAL_CONE (1 << 21) -# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) -# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) -# define RADEON_LIGHT_1_SHIFT 16 -#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 -# define RADEON_LIGHT_2_SHIFT 0 -# define RADEON_LIGHT_3_SHIFT 16 -#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 -# define RADEON_LIGHT_4_SHIFT 0 -# define RADEON_LIGHT_5_SHIFT 16 -#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c -# define RADEON_LIGHT_6_SHIFT 0 -# define RADEON_LIGHT_7_SHIFT 16 - -#define RADEON_SE_TCL_SHININESS 0x2250 - -#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 -# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) -# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) -# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) -# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) -# define RADEON_TEXMAT_0_ENABLE (1 << 4) -# define RADEON_TEXMAT_1_ENABLE (1 << 5) -# define RADEON_TEXMAT_2_ENABLE (1 << 6) -# define RADEON_TEXMAT_3_ENABLE (1 << 7) -# define RADEON_TEXGEN_INPUT_MASK 0xf -# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 -# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 -# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 -# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 -# define RADEON_TEXGEN_INPUT_OBJ 4 -# define RADEON_TEXGEN_INPUT_EYE 5 -# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 -# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 -# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 -# define RADEON_TEXGEN_0_INPUT_SHIFT 16 -# define RADEON_TEXGEN_1_INPUT_SHIFT 20 -# define RADEON_TEXGEN_2_INPUT_SHIFT 24 -# define RADEON_TEXGEN_3_INPUT_SHIFT 28 - -#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 -# define RADEON_UCP_IN_CLIP_SPACE (1 << 0) -# define RADEON_UCP_IN_MODEL_SPACE (1 << 1) -# define RADEON_UCP_ENABLE_0 (1 << 2) -# define RADEON_UCP_ENABLE_1 (1 << 3) -# define RADEON_UCP_ENABLE_2 (1 << 4) -# define RADEON_UCP_ENABLE_3 (1 << 5) -# define RADEON_UCP_ENABLE_4 (1 << 6) -# define RADEON_UCP_ENABLE_5 (1 << 7) -# define RADEON_TCL_FOG_MASK (3 << 8) -# define RADEON_TCL_FOG_DISABLE (0 << 8) -# define RADEON_TCL_FOG_EXP (1 << 8) -# define RADEON_TCL_FOG_EXP2 (2 << 8) -# define RADEON_TCL_FOG_LINEAR (3 << 8) -# define RADEON_RNG_BASED_FOG (1 << 10) -# define RADEON_LIGHT_TWOSIDE (1 << 11) -# define RADEON_BLEND_OP_COUNT_MASK (7 << 12) -# define RADEON_BLEND_OP_COUNT_SHIFT 12 -# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) -# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) -# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) -# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) -# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) -# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) -# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) -# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) -# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) -# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) -# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) -# define RADEON_CULL_FRONT_IS_CW (0 << 28) -# define RADEON_CULL_FRONT_IS_CCW (1 << 28) -# define RADEON_CULL_FRONT (1 << 29) -# define RADEON_CULL_BACK (1 << 30) -# define RADEON_FORCE_W_TO_ONE (1 << 31) - -#define RADEON_SE_VPORT_XSCALE 0x1d98 -#define RADEON_SE_VPORT_XOFFSET 0x1d9c -#define RADEON_SE_VPORT_YSCALE 0x1da0 -#define RADEON_SE_VPORT_YOFFSET 0x1da4 -#define RADEON_SE_VPORT_ZSCALE 0x1da8 -#define RADEON_SE_VPORT_ZOFFSET 0x1dac -#define RADEON_SE_ZBIAS_FACTOR 0x1db0 -#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 - -#define RADEON_SE_VTX_FMT 0x2080 -# define RADEON_SE_VTX_FMT_XY 0x00000000 -# define RADEON_SE_VTX_FMT_W0 0x00000001 -# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 -# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 -# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 -# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 -# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 -# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 -# define RADEON_SE_VTX_FMT_ST0 0x00000080 -# define RADEON_SE_VTX_FMT_ST1 0x00000100 -# define RADEON_SE_VTX_FMT_Q1 0x00000200 -# define RADEON_SE_VTX_FMT_ST2 0x00000400 -# define RADEON_SE_VTX_FMT_Q2 0x00000800 -# define RADEON_SE_VTX_FMT_ST3 0x00001000 -# define RADEON_SE_VTX_FMT_Q3 0x00002000 -# define RADEON_SE_VTX_FMT_Q0 0x00004000 -# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 -# define RADEON_SE_VTX_FMT_N0 0x00040000 -# define RADEON_SE_VTX_FMT_XY1 0x08000000 -# define RADEON_SE_VTX_FMT_Z1 0x10000000 -# define RADEON_SE_VTX_FMT_W1 0x20000000 -# define RADEON_SE_VTX_FMT_N1 0x40000000 -# define RADEON_SE_VTX_FMT_Z 0x80000000 - -#define RADEON_SE_VF_CNTL 0x2084 -# define RADEON_VF_PRIM_TYPE_POINT_LIST 1 -# define RADEON_VF_PRIM_TYPE_LINE_LIST 2 -# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 -# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 -# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 -# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 -# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 -# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 -# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 -# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 -# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 -# define RADEON_VF_PRIM_TYPE_POLYGON 15 -# define RADEON_VF_PRIM_WALK_STATE (0<<4) -# define RADEON_VF_PRIM_WALK_INDEX (1<<4) -# define RADEON_VF_PRIM_WALK_LIST (2<<4) -# define RADEON_VF_PRIM_WALK_DATA (3<<4) -# define RADEON_VF_COLOR_ORDER_RGBA (1<<6) -# define RADEON_VF_RADEON_MODE (1<<8) -# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) -# define RADEON_VF_PROG_STREAM_ENA (1<<10) -# define RADEON_VF_INDEX_SIZE_SHIFT 11 -# define RADEON_VF_NUM_VERTICES_SHIFT 16 - -#define RADEON_SE_PORT_DATA0 0x2000 - -#define R200_SE_VAP_CNTL 0x2080 -# define R200_VAP_TCL_ENABLE 0x00000001 -# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 -# define R200_VAP_FORCE_W_TO_ONE 0x00010000 -# define R200_VAP_D3D_TEX_DEFAULT 0x00020000 -# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 -# define R200_VAP_VF_MAX_VTX_NUM (9 << 18) -# define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 -#define R200_VF_MAX_VTX_INDX 0x210c -#define R200_VF_MIN_VTX_INDX 0x2110 -#define R200_SE_VTE_CNTL 0x20b0 -# define R200_VPORT_X_SCALE_ENA 0x00000001 -# define R200_VPORT_X_OFFSET_ENA 0x00000002 -# define R200_VPORT_Y_SCALE_ENA 0x00000004 -# define R200_VPORT_Y_OFFSET_ENA 0x00000008 -# define R200_VPORT_Z_SCALE_ENA 0x00000010 -# define R200_VPORT_Z_OFFSET_ENA 0x00000020 -# define R200_VTX_XY_FMT 0x00000100 -# define R200_VTX_Z_FMT 0x00000200 -# define R200_VTX_W0_FMT 0x00000400 -# define R200_VTX_W0_NORMALIZE 0x00000800 -# define R200_VTX_ST_DENORMALIZED 0x00001000 -#define R200_SE_VAP_CNTL_STATUS 0x2140 -# define R200_VC_NO_SWAP (0 << 0) -# define R200_VC_16BIT_SWAP (1 << 0) -# define R200_VC_32BIT_SWAP (2 << 0) -#define R200_PP_TXFILTER_0 0x2c00 -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFILTER_5 0x2ca0 -# define R200_MAG_FILTER_NEAREST (0 << 0) -# define R200_MAG_FILTER_LINEAR (1 << 0) -# define R200_MAG_FILTER_MASK (1 << 0) -# define R200_MIN_FILTER_NEAREST (0 << 1) -# define R200_MIN_FILTER_LINEAR (1 << 1) -# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) -# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) -# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) -# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) -# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) -# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) -# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) -# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) -# define R200_MIN_FILTER_MASK (15 << 1) -# define R200_MAX_ANISO_1_TO_1 (0 << 5) -# define R200_MAX_ANISO_2_TO_1 (1 << 5) -# define R200_MAX_ANISO_4_TO_1 (2 << 5) -# define R200_MAX_ANISO_8_TO_1 (3 << 5) -# define R200_MAX_ANISO_16_TO_1 (4 << 5) -# define R200_MAX_ANISO_MASK (7 << 5) -# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) -# define R200_MAX_MIP_LEVEL_SHIFT 16 -# define R200_YUV_TO_RGB (1 << 20) -# define R200_YUV_TEMPERATURE_COOL (0 << 21) -# define R200_YUV_TEMPERATURE_HOT (1 << 21) -# define R200_YUV_TEMPERATURE_MASK (1 << 21) -# define R200_WRAPEN_S (1 << 22) -# define R200_CLAMP_S_WRAP (0 << 23) -# define R200_CLAMP_S_MIRROR (1 << 23) -# define R200_CLAMP_S_CLAMP_LAST (2 << 23) -# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) -# define R200_CLAMP_S_CLAMP_BORDER (4 << 23) -# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) -# define R200_CLAMP_S_CLAMP_GL (6 << 23) -# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) -# define R200_CLAMP_S_MASK (7 << 23) -# define R200_WRAPEN_T (1 << 26) -# define R200_CLAMP_T_WRAP (0 << 27) -# define R200_CLAMP_T_MIRROR (1 << 27) -# define R200_CLAMP_T_CLAMP_LAST (2 << 27) -# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) -# define R200_CLAMP_T_CLAMP_BORDER (4 << 27) -# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) -# define R200_CLAMP_T_CLAMP_GL (6 << 27) -# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) -# define R200_CLAMP_T_MASK (7 << 27) -# define R200_KILL_LT_ZERO (1 << 30) -# define R200_BORDER_MODE_OGL (0 << 31) -# define R200_BORDER_MODE_D3D (1 << 31) -#define R200_PP_TXFORMAT_0 0x2c04 -#define R200_PP_TXFORMAT_1 0x2c24 -#define R200_PP_TXFORMAT_2 0x2c44 -#define R200_PP_TXFORMAT_3 0x2c64 -#define R200_PP_TXFORMAT_4 0x2c84 -#define R200_PP_TXFORMAT_5 0x2ca4 -# define R200_TXFORMAT_I8 (0 << 0) -# define R200_TXFORMAT_AI88 (1 << 0) -# define R200_TXFORMAT_RGB332 (2 << 0) -# define R200_TXFORMAT_ARGB1555 (3 << 0) -# define R200_TXFORMAT_RGB565 (4 << 0) -# define R200_TXFORMAT_ARGB4444 (5 << 0) -# define R200_TXFORMAT_ARGB8888 (6 << 0) -# define R200_TXFORMAT_RGBA8888 (7 << 0) -# define R200_TXFORMAT_Y8 (8 << 0) -# define R200_TXFORMAT_AVYU4444 (9 << 0) -# define R200_TXFORMAT_VYUY422 (10 << 0) -# define R200_TXFORMAT_YVYU422 (11 << 0) -# define R200_TXFORMAT_DXT1 (12 << 0) -# define R200_TXFORMAT_DXT23 (14 << 0) -# define R200_TXFORMAT_DXT45 (15 << 0) -# define R200_TXFORMAT_ABGR8888 (22 << 0) -# define R200_TXFORMAT_FORMAT_MASK (31 << 0) -# define R200_TXFORMAT_FORMAT_SHIFT 0 -# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) -# define R200_TXFORMAT_NON_POWER2 (1 << 7) -# define R200_TXFORMAT_WIDTH_MASK (15 << 8) -# define R200_TXFORMAT_WIDTH_SHIFT 8 -# define R200_TXFORMAT_HEIGHT_MASK (15 << 12) -# define R200_TXFORMAT_HEIGHT_SHIFT 12 -# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ -# define R200_TXFORMAT_F5_WIDTH_SHIFT 16 -# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) -# define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 -# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) -# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) -# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) -# define R200_TXFORMAT_ST_ROUTE_SHIFT 24 -# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) -# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) -# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) -#define R200_PP_TXFORMAT_X_0 0x2c08 -#define R200_PP_TXFORMAT_X_1 0x2c28 -#define R200_PP_TXFORMAT_X_2 0x2c48 -#define R200_PP_TXFORMAT_X_3 0x2c68 -#define R200_PP_TXFORMAT_X_4 0x2c88 -#define R200_PP_TXFORMAT_X_5 0x2ca8 - -#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ -#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ -#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ -#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ -#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ -#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ - -#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ -#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ -#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ -#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ -#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ -#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ - -#define R200_PP_TXOFFSET_0 0x2d00 -# define R200_TXO_ENDIAN_NO_SWAP (0 << 0) -# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) -# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) -# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) -# define R200_TXO_MACRO_LINEAR (0 << 2) -# define R200_TXO_MACRO_TILE (1 << 2) -# define R200_TXO_MICRO_LINEAR (0 << 3) -# define R200_TXO_MICRO_TILE (1 << 3) -# define R200_TXO_OFFSET_MASK 0xffffffe0 -# define R200_TXO_OFFSET_SHIFT 5 -#define R200_PP_TXOFFSET_1 0x2d18 -#define R200_PP_TXOFFSET_2 0x2d30 -#define R200_PP_TXOFFSET_3 0x2d48 -#define R200_PP_TXOFFSET_4 0x2d60 -#define R200_PP_TXOFFSET_5 0x2d78 - -#define R200_PP_TFACTOR_0 0x2ee0 -#define R200_PP_TFACTOR_1 0x2ee4 -#define R200_PP_TFACTOR_2 0x2ee8 -#define R200_PP_TFACTOR_3 0x2eec -#define R200_PP_TFACTOR_4 0x2ef0 -#define R200_PP_TFACTOR_5 0x2ef4 - -#define R200_PP_TXCBLEND_0 0x2f00 -# define R200_TXC_ARG_A_ZERO (0) -# define R200_TXC_ARG_A_CURRENT_COLOR (2) -# define R200_TXC_ARG_A_CURRENT_ALPHA (3) -# define R200_TXC_ARG_A_DIFFUSE_COLOR (4) -# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) -# define R200_TXC_ARG_A_SPECULAR_COLOR (6) -# define R200_TXC_ARG_A_SPECULAR_ALPHA (7) -# define R200_TXC_ARG_A_TFACTOR_COLOR (8) -# define R200_TXC_ARG_A_TFACTOR_ALPHA (9) -# define R200_TXC_ARG_A_R0_COLOR (10) -# define R200_TXC_ARG_A_R0_ALPHA (11) -# define R200_TXC_ARG_A_R1_COLOR (12) -# define R200_TXC_ARG_A_R1_ALPHA (13) -# define R200_TXC_ARG_A_R2_COLOR (14) -# define R200_TXC_ARG_A_R2_ALPHA (15) -# define R200_TXC_ARG_A_R3_COLOR (16) -# define R200_TXC_ARG_A_R3_ALPHA (17) -# define R200_TXC_ARG_A_R4_COLOR (18) -# define R200_TXC_ARG_A_R4_ALPHA (19) -# define R200_TXC_ARG_A_R5_COLOR (20) -# define R200_TXC_ARG_A_R5_ALPHA (21) -# define R200_TXC_ARG_A_TFACTOR1_COLOR (26) -# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) -# define R200_TXC_ARG_A_MASK (31 << 0) -# define R200_TXC_ARG_A_SHIFT 0 -# define R200_TXC_ARG_B_ZERO (0 << 5) -# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) -# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) -# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) -# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) -# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) -# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) -# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) -# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) -# define R200_TXC_ARG_B_R0_COLOR (10 << 5) -# define R200_TXC_ARG_B_R0_ALPHA (11 << 5) -# define R200_TXC_ARG_B_R1_COLOR (12 << 5) -# define R200_TXC_ARG_B_R1_ALPHA (13 << 5) -# define R200_TXC_ARG_B_R2_COLOR (14 << 5) -# define R200_TXC_ARG_B_R2_ALPHA (15 << 5) -# define R200_TXC_ARG_B_R3_COLOR (16 << 5) -# define R200_TXC_ARG_B_R3_ALPHA (17 << 5) -# define R200_TXC_ARG_B_R4_COLOR (18 << 5) -# define R200_TXC_ARG_B_R4_ALPHA (19 << 5) -# define R200_TXC_ARG_B_R5_COLOR (20 << 5) -# define R200_TXC_ARG_B_R5_ALPHA (21 << 5) -# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) -# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) -# define R200_TXC_ARG_B_MASK (31 << 5) -# define R200_TXC_ARG_B_SHIFT 5 -# define R200_TXC_ARG_C_ZERO (0 << 10) -# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) -# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) -# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) -# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) -# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) -# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) -# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) -# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) -# define R200_TXC_ARG_C_R0_COLOR (10 << 10) -# define R200_TXC_ARG_C_R0_ALPHA (11 << 10) -# define R200_TXC_ARG_C_R1_COLOR (12 << 10) -# define R200_TXC_ARG_C_R1_ALPHA (13 << 10) -# define R200_TXC_ARG_C_R2_COLOR (14 << 10) -# define R200_TXC_ARG_C_R2_ALPHA (15 << 10) -# define R200_TXC_ARG_C_R3_COLOR (16 << 10) -# define R200_TXC_ARG_C_R3_ALPHA (17 << 10) -# define R200_TXC_ARG_C_R4_COLOR (18 << 10) -# define R200_TXC_ARG_C_R4_ALPHA (19 << 10) -# define R200_TXC_ARG_C_R5_COLOR (20 << 10) -# define R200_TXC_ARG_C_R5_ALPHA (21 << 10) -# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) -# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) -# define R200_TXC_ARG_C_MASK (31 << 10) -# define R200_TXC_ARG_C_SHIFT 10 -# define R200_TXC_COMP_ARG_A (1 << 16) -# define R200_TXC_COMP_ARG_A_SHIFT (16) -# define R200_TXC_BIAS_ARG_A (1 << 17) -# define R200_TXC_SCALE_ARG_A (1 << 18) -# define R200_TXC_NEG_ARG_A (1 << 19) -# define R200_TXC_COMP_ARG_B (1 << 20) -# define R200_TXC_COMP_ARG_B_SHIFT (20) -# define R200_TXC_BIAS_ARG_B (1 << 21) -# define R200_TXC_SCALE_ARG_B (1 << 22) -# define R200_TXC_NEG_ARG_B (1 << 23) -# define R200_TXC_COMP_ARG_C (1 << 24) -# define R200_TXC_COMP_ARG_C_SHIFT (24) -# define R200_TXC_BIAS_ARG_C (1 << 25) -# define R200_TXC_SCALE_ARG_C (1 << 26) -# define R200_TXC_NEG_ARG_C (1 << 27) -# define R200_TXC_OP_MADD (0 << 28) -# define R200_TXC_OP_CND0 (2 << 28) -# define R200_TXC_OP_LERP (3 << 28) -# define R200_TXC_OP_DOT3 (4 << 28) -# define R200_TXC_OP_DOT4 (5 << 28) -# define R200_TXC_OP_CONDITIONAL (6 << 28) -# define R200_TXC_OP_DOT2_ADD (7 << 28) -# define R200_TXC_OP_MASK (7 << 28) -#define R200_PP_TXCBLEND2_0 0x2f04 -# define R200_TXC_TFACTOR_SEL_SHIFT 0 -# define R200_TXC_TFACTOR_SEL_MASK 0x7 -# define R200_TXC_TFACTOR1_SEL_SHIFT 4 -# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) -# define R200_TXC_SCALE_SHIFT 8 -# define R200_TXC_SCALE_MASK (7 << 8) -# define R200_TXC_SCALE_1X (0 << 8) -# define R200_TXC_SCALE_2X (1 << 8) -# define R200_TXC_SCALE_4X (2 << 8) -# define R200_TXC_SCALE_8X (3 << 8) -# define R200_TXC_SCALE_INV2 (5 << 8) -# define R200_TXC_SCALE_INV4 (6 << 8) -# define R200_TXC_SCALE_INV8 (7 << 8) -# define R200_TXC_CLAMP_SHIFT 12 -# define R200_TXC_CLAMP_MASK (3 << 12) -# define R200_TXC_CLAMP_WRAP (0 << 12) -# define R200_TXC_CLAMP_0_1 (1 << 12) -# define R200_TXC_CLAMP_8_8 (2 << 12) -# define R200_TXC_OUTPUT_REG_MASK (7 << 16) -# define R200_TXC_OUTPUT_REG_NONE (0 << 16) -# define R200_TXC_OUTPUT_REG_R0 (1 << 16) -# define R200_TXC_OUTPUT_REG_R1 (2 << 16) -# define R200_TXC_OUTPUT_REG_R2 (3 << 16) -# define R200_TXC_OUTPUT_REG_R3 (4 << 16) -# define R200_TXC_OUTPUT_REG_R4 (5 << 16) -# define R200_TXC_OUTPUT_REG_R5 (6 << 16) -# define R200_TXC_OUTPUT_MASK_MASK (7 << 20) -# define R200_TXC_OUTPUT_MASK_RGB (0 << 20) -# define R200_TXC_OUTPUT_MASK_RG (1 << 20) -# define R200_TXC_OUTPUT_MASK_RB (2 << 20) -# define R200_TXC_OUTPUT_MASK_R (3 << 20) -# define R200_TXC_OUTPUT_MASK_GB (4 << 20) -# define R200_TXC_OUTPUT_MASK_G (5 << 20) -# define R200_TXC_OUTPUT_MASK_B (6 << 20) -# define R200_TXC_OUTPUT_MASK_NONE (7 << 20) -# define R200_TXC_REPL_NORMAL 0 -# define R200_TXC_REPL_RED 1 -# define R200_TXC_REPL_GREEN 2 -# define R200_TXC_REPL_BLUE 3 -# define R200_TXC_REPL_ARG_A_SHIFT 26 -# define R200_TXC_REPL_ARG_A_MASK (3 << 26) -# define R200_TXC_REPL_ARG_B_SHIFT 28 -# define R200_TXC_REPL_ARG_B_MASK (3 << 28) -# define R200_TXC_REPL_ARG_C_SHIFT 30 -# define R200_TXC_REPL_ARG_C_MASK (3 << 30) -#define R200_PP_TXABLEND_0 0x2f08 -# define R200_TXA_ARG_A_ZERO (0) -# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ -# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ -# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) -# define R200_TXA_ARG_A_DIFFUSE_BLUE (5) -# define R200_TXA_ARG_A_SPECULAR_ALPHA (6) -# define R200_TXA_ARG_A_SPECULAR_BLUE (7) -# define R200_TXA_ARG_A_TFACTOR_ALPHA (8) -# define R200_TXA_ARG_A_TFACTOR_BLUE (9) -# define R200_TXA_ARG_A_R0_ALPHA (10) -# define R200_TXA_ARG_A_R0_BLUE (11) -# define R200_TXA_ARG_A_R1_ALPHA (12) -# define R200_TXA_ARG_A_R1_BLUE (13) -# define R200_TXA_ARG_A_R2_ALPHA (14) -# define R200_TXA_ARG_A_R2_BLUE (15) -# define R200_TXA_ARG_A_R3_ALPHA (16) -# define R200_TXA_ARG_A_R3_BLUE (17) -# define R200_TXA_ARG_A_R4_ALPHA (18) -# define R200_TXA_ARG_A_R4_BLUE (19) -# define R200_TXA_ARG_A_R5_ALPHA (20) -# define R200_TXA_ARG_A_R5_BLUE (21) -# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) -# define R200_TXA_ARG_A_TFACTOR1_BLUE (27) -# define R200_TXA_ARG_A_MASK (31 << 0) -# define R200_TXA_ARG_A_SHIFT 0 -# define R200_TXA_ARG_B_ZERO (0 << 5) -# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ -# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ -# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) -# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) -# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) -# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) -# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) -# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) -# define R200_TXA_ARG_B_R0_ALPHA (10 << 5) -# define R200_TXA_ARG_B_R0_BLUE (11 << 5) -# define R200_TXA_ARG_B_R1_ALPHA (12 << 5) -# define R200_TXA_ARG_B_R1_BLUE (13 << 5) -# define R200_TXA_ARG_B_R2_ALPHA (14 << 5) -# define R200_TXA_ARG_B_R2_BLUE (15 << 5) -# define R200_TXA_ARG_B_R3_ALPHA (16 << 5) -# define R200_TXA_ARG_B_R3_BLUE (17 << 5) -# define R200_TXA_ARG_B_R4_ALPHA (18 << 5) -# define R200_TXA_ARG_B_R4_BLUE (19 << 5) -# define R200_TXA_ARG_B_R5_ALPHA (20 << 5) -# define R200_TXA_ARG_B_R5_BLUE (21 << 5) -# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) -# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) -# define R200_TXA_ARG_B_MASK (31 << 5) -# define R200_TXA_ARG_B_SHIFT 5 -# define R200_TXA_ARG_C_ZERO (0 << 10) -# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ -# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ -# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) -# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) -# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) -# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) -# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) -# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) -# define R200_TXA_ARG_C_R0_ALPHA (10 << 10) -# define R200_TXA_ARG_C_R0_BLUE (11 << 10) -# define R200_TXA_ARG_C_R1_ALPHA (12 << 10) -# define R200_TXA_ARG_C_R1_BLUE (13 << 10) -# define R200_TXA_ARG_C_R2_ALPHA (14 << 10) -# define R200_TXA_ARG_C_R2_BLUE (15 << 10) -# define R200_TXA_ARG_C_R3_ALPHA (16 << 10) -# define R200_TXA_ARG_C_R3_BLUE (17 << 10) -# define R200_TXA_ARG_C_R4_ALPHA (18 << 10) -# define R200_TXA_ARG_C_R4_BLUE (19 << 10) -# define R200_TXA_ARG_C_R5_ALPHA (20 << 10) -# define R200_TXA_ARG_C_R5_BLUE (21 << 10) -# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) -# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) -# define R200_TXA_ARG_C_MASK (31 << 10) -# define R200_TXA_ARG_C_SHIFT 10 -# define R200_TXA_COMP_ARG_A (1 << 16) -# define R200_TXA_COMP_ARG_A_SHIFT (16) -# define R200_TXA_BIAS_ARG_A (1 << 17) -# define R200_TXA_SCALE_ARG_A (1 << 18) -# define R200_TXA_NEG_ARG_A (1 << 19) -# define R200_TXA_COMP_ARG_B (1 << 20) -# define R200_TXA_COMP_ARG_B_SHIFT (20) -# define R200_TXA_BIAS_ARG_B (1 << 21) -# define R200_TXA_SCALE_ARG_B (1 << 22) -# define R200_TXA_NEG_ARG_B (1 << 23) -# define R200_TXA_COMP_ARG_C (1 << 24) -# define R200_TXA_COMP_ARG_C_SHIFT (24) -# define R200_TXA_BIAS_ARG_C (1 << 25) -# define R200_TXA_SCALE_ARG_C (1 << 26) -# define R200_TXA_NEG_ARG_C (1 << 27) -# define R200_TXA_OP_MADD (0 << 28) -# define R200_TXA_OP_CND0 (2 << 28) -# define R200_TXA_OP_LERP (3 << 28) -# define R200_TXA_OP_CONDITIONAL (6 << 28) -# define R200_TXA_OP_MASK (7 << 28) -#define R200_PP_TXABLEND2_0 0x2f0c -# define R200_TXA_TFACTOR_SEL_SHIFT 0 -# define R200_TXA_TFACTOR_SEL_MASK 0x7 -# define R200_TXA_TFACTOR1_SEL_SHIFT 4 -# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) -# define R200_TXA_SCALE_SHIFT 8 -# define R200_TXA_SCALE_MASK (7 << 8) -# define R200_TXA_SCALE_1X (0 << 8) -# define R200_TXA_SCALE_2X (1 << 8) -# define R200_TXA_SCALE_4X (2 << 8) -# define R200_TXA_SCALE_8X (3 << 8) -# define R200_TXA_SCALE_INV2 (5 << 8) -# define R200_TXA_SCALE_INV4 (6 << 8) -# define R200_TXA_SCALE_INV8 (7 << 8) -# define R200_TXA_CLAMP_SHIFT 12 -# define R200_TXA_CLAMP_MASK (3 << 12) -# define R200_TXA_CLAMP_WRAP (0 << 12) -# define R200_TXA_CLAMP_0_1 (1 << 12) -# define R200_TXA_CLAMP_8_8 (2 << 12) -# define R200_TXA_OUTPUT_REG_MASK (7 << 16) -# define R200_TXA_OUTPUT_REG_NONE (0 << 16) -# define R200_TXA_OUTPUT_REG_R0 (1 << 16) -# define R200_TXA_OUTPUT_REG_R1 (2 << 16) -# define R200_TXA_OUTPUT_REG_R2 (3 << 16) -# define R200_TXA_OUTPUT_REG_R3 (4 << 16) -# define R200_TXA_OUTPUT_REG_R4 (5 << 16) -# define R200_TXA_OUTPUT_REG_R5 (6 << 16) -# define R200_TXA_DOT_ALPHA (1 << 20) -# define R200_TXA_REPL_NORMAL 0 -# define R200_TXA_REPL_RED 1 -# define R200_TXA_REPL_GREEN 2 -# define R200_TXA_REPL_ARG_A_SHIFT 26 -# define R200_TXA_REPL_ARG_A_MASK (3 << 26) -# define R200_TXA_REPL_ARG_B_SHIFT 28 -# define R200_TXA_REPL_ARG_B_MASK (3 << 28) -# define R200_TXA_REPL_ARG_C_SHIFT 30 -# define R200_TXA_REPL_ARG_C_MASK (3 << 30) - -#define R200_SE_VTX_FMT_0 0x2088 -# define R200_VTX_XY 0 /* always have xy */ -# define R200_VTX_Z0 (1<<0) -# define R200_VTX_W0 (1<<1) -# define R200_VTX_WEIGHT_COUNT_SHIFT (2) -# define R200_VTX_PV_MATRIX_SEL (1<<5) -# define R200_VTX_N0 (1<<6) -# define R200_VTX_POINT_SIZE (1<<7) -# define R200_VTX_DISCRETE_FOG (1<<8) -# define R200_VTX_SHININESS_0 (1<<9) -# define R200_VTX_SHININESS_1 (1<<10) -# define R200_VTX_COLOR_NOT_PRESENT 0 -# define R200_VTX_PK_RGBA 1 -# define R200_VTX_FP_RGB 2 -# define R200_VTX_FP_RGBA 3 -# define R200_VTX_COLOR_MASK 3 -# define R200_VTX_COLOR_0_SHIFT 11 -# define R200_VTX_COLOR_1_SHIFT 13 -# define R200_VTX_COLOR_2_SHIFT 15 -# define R200_VTX_COLOR_3_SHIFT 17 -# define R200_VTX_COLOR_4_SHIFT 19 -# define R200_VTX_COLOR_5_SHIFT 21 -# define R200_VTX_COLOR_6_SHIFT 23 -# define R200_VTX_COLOR_7_SHIFT 25 -# define R200_VTX_XY1 (1<<28) -# define R200_VTX_Z1 (1<<29) -# define R200_VTX_W1 (1<<30) -# define R200_VTX_N1 (1<<31) -#define R200_SE_VTX_FMT_1 0x208c -# define R200_VTX_TEX0_COMP_CNT_SHIFT 0 -# define R200_VTX_TEX1_COMP_CNT_SHIFT 3 -# define R200_VTX_TEX2_COMP_CNT_SHIFT 6 -# define R200_VTX_TEX3_COMP_CNT_SHIFT 9 -# define R200_VTX_TEX4_COMP_CNT_SHIFT 12 -# define R200_VTX_TEX5_COMP_CNT_SHIFT 15 - -#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 -#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 -#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 -# define R200_OUTPUT_XYZW (1<<0) -# define R200_OUTPUT_COLOR_0 (1<<8) -# define R200_OUTPUT_COLOR_1 (1<<9) -# define R200_OUTPUT_TEX_0 (1<<16) -# define R200_OUTPUT_TEX_1 (1<<17) -# define R200_OUTPUT_TEX_2 (1<<18) -# define R200_OUTPUT_TEX_3 (1<<19) -# define R200_OUTPUT_TEX_4 (1<<20) -# define R200_OUTPUT_TEX_5 (1<<21) -# define R200_OUTPUT_TEX_MASK (0x3f<<16) -# define R200_OUTPUT_DISCRETE_FOG (1<<24) -# define R200_OUTPUT_PT_SIZE (1<<25) -# define R200_FORCE_INORDER_PROC (1<<31) -#define R200_PP_CNTL_X 0x2cc4 -#define R200_PP_TXMULTI_CTL_0 0x2c1c -#define R200_SE_VTX_STATE_CNTL 0x2180 -# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) - - /* Registers for CP and Microcode Engine */ -#define RADEON_CP_ME_RAM_ADDR 0x07d4 -#define RADEON_CP_ME_RAM_RADDR 0x07d8 -#define RADEON_CP_ME_RAM_DATAH 0x07dc -#define RADEON_CP_ME_RAM_DATAL 0x07e0 - -#define RADEON_CP_RB_BASE 0x0700 -#define RADEON_CP_RB_CNTL 0x0704 -#define RADEON_CP_RB_RPTR_ADDR 0x070c -#define RADEON_CP_RB_RPTR 0x0710 -#define RADEON_CP_RB_WPTR 0x0714 - -#define RADEON_CP_IB_BASE 0x0738 -#define RADEON_CP_IB_BUFSZ 0x073c - -#define RADEON_CP_CSQ_CNTL 0x0740 -# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) -# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) -# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) -# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) -# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) -# define RADEON_CSQ_PRIBM_INDBM (4 << 28) -# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) -#define RADEON_CP_CSQ_STAT 0x07f8 -# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) -# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) -# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) -# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) -#define RADEON_CP_CSQ_ADDR 0x07f0 -#define RADEON_CP_CSQ_DATA 0x07f4 -#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 -#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 - -#define RADEON_CP_RB_WPTR_DELAY 0x0718 -# define RADEON_PRE_WRITE_TIMER_SHIFT 0 -# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 - -#define RADEON_AIC_CNTL 0x01d0 -# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) -#define RADEON_AIC_LO_ADDR 0x01dc - - - - /* Constants */ -#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 -#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 - - - - /* CP packet types */ -#define RADEON_CP_PACKET0 0x00000000 -#define RADEON_CP_PACKET1 0x40000000 -#define RADEON_CP_PACKET2 0x80000000 -#define RADEON_CP_PACKET3 0xC0000000 -# define RADEON_CP_PACKET_MASK 0xC0000000 -# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 -# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) -# define RADEON_CP_PACKET0_REG_MASK 0x000007ff -# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff -# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 - -#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 - -#define RADEON_CP_PACKET3_NOP 0xC0001000 -#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 -#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 -#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 -#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 -#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 -#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 -#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 -#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 -#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 -#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 -#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 -#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 -#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 -#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 -#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 -#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 -#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 -#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 -#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 -#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 -#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 - - -#define RADEON_CP_VC_FRMT_XY 0x00000000 -#define RADEON_CP_VC_FRMT_W0 0x00000001 -#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 -#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 -#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 -#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 -#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 -#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 -#define RADEON_CP_VC_FRMT_ST0 0x00000080 -#define RADEON_CP_VC_FRMT_ST1 0x00000100 -#define RADEON_CP_VC_FRMT_Q1 0x00000200 -#define RADEON_CP_VC_FRMT_ST2 0x00000400 -#define RADEON_CP_VC_FRMT_Q2 0x00000800 -#define RADEON_CP_VC_FRMT_ST3 0x00001000 -#define RADEON_CP_VC_FRMT_Q3 0x00002000 -#define RADEON_CP_VC_FRMT_Q0 0x00004000 -#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 -#define RADEON_CP_VC_FRMT_N0 0x00040000 -#define RADEON_CP_VC_FRMT_XY1 0x08000000 -#define RADEON_CP_VC_FRMT_Z1 0x10000000 -#define RADEON_CP_VC_FRMT_W1 0x20000000 -#define RADEON_CP_VC_FRMT_N1 0x40000000 -#define RADEON_CP_VC_FRMT_Z 0x80000000 - -#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 -#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a -#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d -#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 -#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 -#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 -#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 -#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 -#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 -#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 -#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 -#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 -#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 -#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 - -#define RADEON_VS_MATRIX_0_ADDR 0 -#define RADEON_VS_MATRIX_1_ADDR 4 -#define RADEON_VS_MATRIX_2_ADDR 8 -#define RADEON_VS_MATRIX_3_ADDR 12 -#define RADEON_VS_MATRIX_4_ADDR 16 -#define RADEON_VS_MATRIX_5_ADDR 20 -#define RADEON_VS_MATRIX_6_ADDR 24 -#define RADEON_VS_MATRIX_7_ADDR 28 -#define RADEON_VS_MATRIX_8_ADDR 32 -#define RADEON_VS_MATRIX_9_ADDR 36 -#define RADEON_VS_MATRIX_10_ADDR 40 -#define RADEON_VS_MATRIX_11_ADDR 44 -#define RADEON_VS_MATRIX_12_ADDR 48 -#define RADEON_VS_MATRIX_13_ADDR 52 -#define RADEON_VS_MATRIX_14_ADDR 56 -#define RADEON_VS_MATRIX_15_ADDR 60 -#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 -#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 -#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 -#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 -#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 -#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 -#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 -#define RADEON_VS_UCP_ADDR 116 -#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 -#define RADEON_VS_FOG_PARAM_ADDR 123 -#define RADEON_VS_EYE_VECTOR_ADDR 124 - -#define RADEON_SS_LIGHT_DCD_ADDR 0 -#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 -#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 -#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 -#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 -#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 -#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 -#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 -#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 -#define RADEON_SS_SHININESS 60 - -#define RADEON_TV_MASTER_CNTL 0x0800 -# define RADEON_TV_ASYNC_RST (1 << 0) -# define RADEON_CRT_ASYNC_RST (1 << 1) -# define RADEON_RESTART_PHASE_FIX (1 << 3) -# define RADEON_TV_FIFO_ASYNC_RST (1 << 4) -# define RADEON_VIN_ASYNC_RST (1 << 5) -# define RADEON_AUD_ASYNC_RST (1 << 6) -# define RADEON_DVS_ASYNC_RST (1 << 7) -# define RADEON_CRT_FIFO_CE_EN (1 << 9) -# define RADEON_TV_FIFO_CE_EN (1 << 10) -# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) -# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) -# define RADEON_TV_ON (1 << 31) -#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 -# define RADEON_Y_RED_EN (1 << 0) -# define RADEON_C_GRN_EN (1 << 1) -# define RADEON_CMP_BLU_EN (1 << 2) -# define RADEON_DAC_DITHER_EN (1 << 3) -# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) -# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) -# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) -# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 -#define RADEON_TV_RGB_CNTL 0x0804 -# define RADEON_SWITCH_TO_BLUE (1 << 4) -# define RADEON_RGB_DITHER_EN (1 << 5) -# define RADEON_RGB_SRC_SEL_MASK (3 << 8) -# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) -# define RADEON_RGB_SRC_SEL_RMX (1 << 8) -# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) -# define RADEON_RGB_CONVERT_BY_PASS (1 << 10) -# define RADEON_UVRAM_READ_MARGIN_SHIFT 16 -# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 -# define RADEON_TVOUT_SCALE_EN (1 << 26) -#define RADEON_TV_SYNC_CNTL 0x0808 -# define RADEON_SYNC_OE (1 << 0) -# define RADEON_SYNC_OUT (1 << 1) -# define RADEON_SYNC_IN (1 << 2) -# define RADEON_SYNC_PUB (1 << 3) -# define RADEON_SYNC_PD (1 << 4) -# define RADEON_TV_SYNC_IO_DRIVE (1 << 5) -#define RADEON_TV_HTOTAL 0x080c -#define RADEON_TV_HDISP 0x0810 -#define RADEON_TV_HSTART 0x0818 -#define RADEON_TV_HCOUNT 0x081C -#define RADEON_TV_VTOTAL 0x0820 -#define RADEON_TV_VDISP 0x0824 -#define RADEON_TV_VCOUNT 0x0828 -#define RADEON_TV_FTOTAL 0x082c -#define RADEON_TV_FCOUNT 0x0830 -#define RADEON_TV_FRESTART 0x0834 -#define RADEON_TV_HRESTART 0x0838 -#define RADEON_TV_VRESTART 0x083c -#define RADEON_TV_HOST_READ_DATA 0x0840 -#define RADEON_TV_HOST_WRITE_DATA 0x0844 -#define RADEON_TV_HOST_RD_WT_CNTL 0x0848 -# define RADEON_HOST_FIFO_RD (1 << 12) -# define RADEON_HOST_FIFO_RD_ACK (1 << 13) -# define RADEON_HOST_FIFO_WT (1 << 14) -# define RADEON_HOST_FIFO_WT_ACK (1 << 15) -#define RADEON_TV_VSCALER_CNTL1 0x084c -# define RADEON_UV_INC_MASK 0xffff -# define RADEON_UV_INC_SHIFT 0 -# define RADEON_Y_W_EN (1 << 24) -# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ -# define RADEON_Y_DEL_W_SIG_SHIFT 26 -#define RADEON_TV_TIMING_CNTL 0x0850 -# define RADEON_H_INC_MASK 0xfff -# define RADEON_H_INC_SHIFT 0 -# define RADEON_REQ_Y_FIRST (1 << 19) -# define RADEON_FORCE_BURST_ALWAYS (1 << 21) -# define RADEON_UV_POST_SCALE_BYPASS (1 << 23) -# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 -#define RADEON_TV_VSCALER_CNTL2 0x0854 -# define RADEON_DITHER_MODE (1 << 0) -# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) -# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) -# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) -#define RADEON_TV_Y_FALL_CNTL 0x0858 -# define RADEON_Y_FALL_PING_PONG (1 << 16) -# define RADEON_Y_COEF_EN (1 << 17) -#define RADEON_TV_Y_RISE_CNTL 0x085c -# define RADEON_Y_RISE_PING_PONG (1 << 16) -#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 -#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 -# define RADEON_YUPSAMP_EN (1 << 0) -# define RADEON_UVUPSAMP_EN (1 << 2) -#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 -# define RADEON_Y_GAIN_LIMIT_SHIFT 0 -# define RADEON_UV_GAIN_LIMIT_SHIFT 16 -#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c -# define RADEON_Y_GAIN_SHIFT 0 -# define RADEON_UV_GAIN_SHIFT 16 -#define RADEON_TV_MODULATOR_CNTL1 0x0870 -# define RADEON_YFLT_EN (1 << 2) -# define RADEON_UVFLT_EN (1 << 3) -# define RADEON_ALT_PHASE_EN (1 << 6) -# define RADEON_SYNC_TIP_LEVEL (1 << 7) -# define RADEON_BLANK_LEVEL_SHIFT 8 -# define RADEON_SET_UP_LEVEL_SHIFT 16 -# define RADEON_SLEW_RATE_LIMIT (1 << 23) -# define RADEON_CY_FILT_BLEND_SHIFT 28 -#define RADEON_TV_MODULATOR_CNTL2 0x0874 -# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff -# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff -# define RADEON_TV_V_BURST_LEVEL_SHIFT 16 -#define RADEON_TV_CRC_CNTL 0x0890 -#define RADEON_TV_UV_ADR 0x08ac -# define RADEON_MAX_UV_ADR_MASK 0x000000ff -# define RADEON_MAX_UV_ADR_SHIFT 0 -# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 -# define RADEON_TABLE1_BOT_ADR_SHIFT 8 -# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 -# define RADEON_TABLE3_TOP_ADR_SHIFT 16 -# define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 -# define RADEON_HCODE_TABLE_SEL_SHIFT 25 -# define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 -# define RADEON_VCODE_TABLE_SEL_SHIFT 27 -# define RADEON_TV_MAX_FIFO_ADDR 0x1a7 -# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff -#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ -#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ -# define RADEON_TV_M0LO_MASK 0xff -# define RADEON_TV_M0HI_MASK 0x7 -# define RADEON_TV_M0HI_SHIFT 18 -# define RADEON_TV_N0LO_MASK 0x1ff -# define RADEON_TV_N0LO_SHIFT 8 -# define RADEON_TV_N0HI_MASK 0x3 -# define RADEON_TV_N0HI_SHIFT 21 -# define RADEON_TV_P_MASK 0xf -# define RADEON_TV_P_SHIFT 24 -# define RADEON_TV_SLIP_EN (1 << 23) -# define RADEON_TV_DTO_EN (1 << 28) -#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ -# define RADEON_TVPLL_RESET (1 << 1) -# define RADEON_TVPLL_SLEEP (1 << 3) -# define RADEON_TVPLL_REFCLK_SEL (1 << 4) -# define RADEON_TVPCP_SHIFT 8 -# define RADEON_TVPCP_MASK (7 << 8) -# define RADEON_TVPVG_SHIFT 11 -# define RADEON_TVPVG_MASK (7 << 11) -# define RADEON_TVPDC_SHIFT 14 -# define RADEON_TVPDC_MASK (3 << 14) -# define RADEON_TVPLL_TEST_DIS (1 << 31) -# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) - -#define RS400_DISP2_REQ_CNTL1 0xe30 -# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 -# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 -# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 -# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff -#define RS400_DISP2_REQ_CNTL2 0xe34 -# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 -# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff -# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 -# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff -#define RS400_DMIF_MEM_CNTL1 0xe38 -# define RS400_DISP2_START_ADR_SHIFT 0 -# define RS400_DISP2_START_ADR_MASK 0x3ff -# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 -# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff -# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 -# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff -#define RS400_DISP1_REQ_CNTL1 0xe3c -# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 -# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 -# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff -# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 -# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff - -#define RS690_MC_INDEX 0x78 -# define RS690_MC_INDEX_MASK 0x1ff -# define RS690_MC_INDEX_WR_EN (1 << 9) -# define RS690_MC_INDEX_WR_ACK 0x7f -#define RS690_MC_DATA 0x7c - -#define RS690_MC_FB_LOCATION 0x100 -#define RS690_MC_AGP_LOCATION 0x101 -#define RS690_MC_AGP_BASE 0x102 -#define RS690_MC_AGP_BASE_2 0x103 -#define RS690_MC_INIT_MISC_LAT_TIMER 0x104 -#define RS690_MC_STATUS 0x90 -#define RS690_MC_STATUS_IDLE (1 << 0) - -#define RS600_MC_INDEX 0x78 -# define RS600_MC_INDEX_MASK 0xff -# define RS600_MC_INDEX_WR_EN (1 << 8) -# define RS600_MC_INDEX_WR_ACK 0xff -#define RS600_MC_DATA 0x7c - -#define RS600_MC_FB_LOCATION 0xA -#define RS600_MC_STATUS 0x0 -#define RS600_MC_STATUS_IDLE (1 << 0) - -#define AVIVO_MC_INDEX 0x0070 -#define R520_MC_STATUS 0x00 -# define R520_MC_STATUS_IDLE (1 << 1) -#define RV515_MC_STATUS 0x08 -# define RV515_MC_STATUS_IDLE (1 << 4) -#define RV515_MC_INIT_MISC_LAT_TIMER 0x09 -#define AVIVO_MC_DATA 0x0074 - -#define RV515_MC_FB_LOCATION 0x1 -#define RV515_MC_AGP_LOCATION 0x2 -#define RV515_MC_AGP_BASE 0x3 -#define RV515_MC_AGP_BASE_2 0x4 -#define RV515_MC_CNTL 0x5 -# define RV515_MEM_NUM_CHANNELS_MASK 0x3 -#define R520_MC_FB_LOCATION 0x4 -#define R520_MC_AGP_LOCATION 0x5 -#define R520_MC_AGP_BASE 0x6 -#define R520_MC_AGP_BASE_2 0x7 -#define R520_MC_CNTL0 0x8 -# define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) -# define R520_MEM_NUM_CHANNELS_SHIFT 24 -# define R520_MC_CHANNEL_SIZE (1 << 23) - -#define R600_RAMCFG 0x2408 -# define R600_CHANSIZE (1 << 7) -# define R600_CHANSIZE_OVERRIDE (1 << 10) - -#define AVIVO_HDP_FB_LOCATION 0x134 - -#define AVIVO_VGA_RENDER_CONTROL 0x0300 -# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) -#define AVIVO_D1VGA_CONTROL 0x0330 -# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) -# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) -# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) -# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) -# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) -# define AVIVO_DVGA_CONTROL_ROTATE (1<<24) -#define AVIVO_D2VGA_CONTROL 0x0338 - -#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 -#define AVIVO_EXT1_PPLL_REF_DIV 0x404 -#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 -#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c - -#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 -#define AVIVO_EXT2_PPLL_REF_DIV 0x414 -#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 -#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c - -#define AVIVO_EXT1_PPLL_FB_DIV 0x430 -#define AVIVO_EXT2_PPLL_FB_DIV 0x434 - -#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 -#define AVIVO_EXT1_PPLL_POST_DIV 0x43c - -#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 -#define AVIVO_EXT2_PPLL_POST_DIV 0x444 - -#define AVIVO_EXT1_PPLL_CNTL 0x448 -#define AVIVO_EXT2_PPLL_CNTL 0x44c - -#define AVIVO_P1PLL_CNTL 0x450 -#define AVIVO_P2PLL_CNTL 0x454 -#define AVIVO_P1PLL_INT_SS_CNTL 0x458 -#define AVIVO_P2PLL_INT_SS_CNTL 0x45c -#define AVIVO_P1PLL_TMDSA_CNTL 0x460 -#define AVIVO_P2PLL_LVTMA_CNTL 0x464 - -#define AVIVO_PCLK_CRTC1_CNTL 0x480 -#define AVIVO_PCLK_CRTC2_CNTL 0x484 - -#define AVIVO_D1CRTC_H_TOTAL 0x6000 -#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 -#define AVIVO_D1CRTC_H_SYNC_A 0x6008 -#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c -#define AVIVO_D1CRTC_H_SYNC_B 0x6010 -#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 - -#define AVIVO_D1CRTC_V_TOTAL 0x6020 -#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 -#define AVIVO_D1CRTC_V_SYNC_A 0x6028 -#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c -#define AVIVO_D1CRTC_V_SYNC_B 0x6030 -#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 - -#define AVIVO_D1CRTC_CONTROL 0x6080 -# define AVIVO_CRTC_EN (1<<0) -#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 -#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 -#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c -#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 - -/* master controls */ -#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 -#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc - -#define AVIVO_D1GRPH_ENABLE 0x6100 -#define AVIVO_D1GRPH_CONTROL 0x6104 -# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) -# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) -# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) -# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) - -# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) - -# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) -# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) - -# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) -# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) -# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) -# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) - - -# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) - -# define AVIVO_D1GRPH_SWAP_RB (1<<16) -# define AVIVO_D1GRPH_TILED (1<<20) -# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) - -#define AVIVO_D1GRPH_LUT_SEL 0x6108 -#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 -#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 -#define AVIVO_D1GRPH_PITCH 0x6120 -#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 -#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 -#define AVIVO_D1GRPH_X_START 0x612c -#define AVIVO_D1GRPH_Y_START 0x6130 -#define AVIVO_D1GRPH_X_END 0x6134 -#define AVIVO_D1GRPH_Y_END 0x6138 -#define AVIVO_D1GRPH_UPDATE 0x6144 -# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) -#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 - -#define AVIVO_D1CUR_CONTROL 0x6400 -# define AVIVO_D1CURSOR_EN (1<<0) -# define AVIVO_D1CURSOR_MODE_SHIFT 8 -# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) -# define AVIVO_D1CURSOR_MODE_24BPP (0x2) -#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 -#define AVIVO_D1CUR_SIZE 0x6410 -#define AVIVO_D1CUR_POSITION 0x6414 -#define AVIVO_D1CUR_HOT_SPOT 0x6418 -#define AVIVO_D1CUR_UPDATE 0x6424 -# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) - -#define AVIVO_DC_LUT_RW_SELECT 0x6480 -#define AVIVO_DC_LUT_RW_MODE 0x6484 -#define AVIVO_DC_LUT_RW_INDEX 0x6488 -#define AVIVO_DC_LUT_SEQ_COLOR 0x648c -#define AVIVO_DC_LUT_PWL_DATA 0x6490 -#define AVIVO_DC_LUT_30_COLOR 0x6494 -#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 -#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c -#define AVIVO_DC_LUT_AUTOFILL 0x64a0 - -#define AVIVO_DC_LUTA_CONTROL 0x64c0 -#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 -#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 -#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc -#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 -#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 -#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 - -#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 -# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 -# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 -# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 -# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) -# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 -# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff - -#define AVIVO_D1MODE_DATA_FORMAT 0x6528 -# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) -#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c -#define AVIVO_D1MODE_VIEWPORT_START 0x6580 -#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 -#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 -#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c - -#define AVIVO_D1SCL_SCALER_ENABLE 0x6590 -#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 -#define AVIVO_D1SCL_UPDATE 0x65cc -# define AVIVO_D1SCL_UPDATE_LOCK (1<<16) - -/* second crtc */ -#define AVIVO_D2CRTC_H_TOTAL 0x6800 -#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 -#define AVIVO_D2CRTC_H_SYNC_A 0x6808 -#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c -#define AVIVO_D2CRTC_H_SYNC_B 0x6810 -#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 - -#define AVIVO_D2CRTC_V_TOTAL 0x6820 -#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 -#define AVIVO_D2CRTC_V_SYNC_A 0x6828 -#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c -#define AVIVO_D2CRTC_V_SYNC_B 0x6830 -#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 - -#define AVIVO_D2CRTC_CONTROL 0x6880 -#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 -#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 -#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c -#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 - -#define AVIVO_D2GRPH_ENABLE 0x6900 -#define AVIVO_D2GRPH_CONTROL 0x6904 -#define AVIVO_D2GRPH_LUT_SEL 0x6908 -#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 -#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 -#define AVIVO_D2GRPH_PITCH 0x6920 -#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 -#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 -#define AVIVO_D2GRPH_X_START 0x692c -#define AVIVO_D2GRPH_Y_START 0x6930 -#define AVIVO_D2GRPH_X_END 0x6934 -#define AVIVO_D2GRPH_Y_END 0x6938 -#define AVIVO_D2GRPH_UPDATE 0x6944 -#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 - -#define AVIVO_D2CUR_CONTROL 0x6c00 -#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 -#define AVIVO_D2CUR_SIZE 0x6c10 -#define AVIVO_D2CUR_POSITION 0x6c14 - -#define AVIVO_D2MODE_DATA_FORMAT 0x6d28 -#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c -#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 -#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 -#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 -#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c - -#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 -#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 -#define AVIVO_D2SCL_UPDATE 0x6dcc - -#define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 - -#define AVIVO_DACA_ENABLE 0x7800 -# define AVIVO_DAC_ENABLE (1 << 0) -#define AVIVO_DACA_SOURCE_SELECT 0x7804 -# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) -# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) -# define AVIVO_DAC_SOURCE_TV (2 << 0) - -#define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) -# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) -#define AVIVO_DACA_POWERDOWN 0x7850 -# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) -# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) -# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) -# define AVIVO_DACA_POWERDOWN_RED (1 << 24) - -#define AVIVO_DACB_ENABLE 0x7a00 -#define AVIVO_DACB_SOURCE_SELECT 0x7a04 -#define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) -# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) -#define AVIVO_DACB_POWERDOWN 0x7a50 -# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) -# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) -# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) -# define AVIVO_DACB_POWERDOWN_RED - -#define AVIVO_TMDSA_CNTL 0x7880 -# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) -# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) -# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) -# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) -# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) -# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) -# define AVIVO_TMDSA_CNTL_SWAP (1 << 28) -#define AVIVO_TMDSA_SOURCE_SELECT 0x7884 -/* 78a8 appears to be some kind of (reasonably tolerant) clock? - * 78d0 definitely hits the transmitter, definitely clock. */ -/* MYSTERY1 This appears to control dithering? */ -#define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) -# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) -#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 -# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) -# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) -# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) -# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) -#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 -# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) -# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) -#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 -#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) -# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) - -#define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) -# define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) - -#define AVIVO_LVTMA_CNTL 0x7a80 -# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) -# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) -# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) -# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) -# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) -# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) -# define AVIVO_LVTMA_CNTL_SWAP (1 << 28) -#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 -#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 -#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) -# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) - - - -#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 -# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) -# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) -# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) -# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) - -#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 -# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) -# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) -#define R500_LVTMA_CLOCK_ENABLE 0x7b00 -#define R600_LVTMA_CLOCK_ENABLE 0x7b04 - -#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 -#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) -# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) - -#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 -#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) -# define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) - -#define R500_LVTMA_PWRSEQ_CNTL 0x7af0 -#define R600_LVTMA_PWRSEQ_CNTL 0x7af4 -# define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) -# define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) -# define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) -# define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) -# define AVIVO_LVTMA_SYNCEN (1 << 8) -# define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) -# define AVIVO_LVTMA_SYNCEN_POL (1 << 10) -# define AVIVO_LVTMA_DIGON (1 << 16) -# define AVIVO_LVTMA_DIGON_OVRD (1 << 17) -# define AVIVO_LVTMA_DIGON_POL (1 << 18) -# define AVIVO_LVTMA_BLON (1 << 24) -# define AVIVO_LVTMA_BLON_OVRD (1 << 25) -# define AVIVO_LVTMA_BLON_POL (1 << 26) - -#define R500_LVTMA_PWRSEQ_STATE 0x7af4 -#define R600_LVTMA_PWRSEQ_STATE 0x7af8 -# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) -# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) -# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) -# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) -# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) -# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) - -#define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 -# define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) -# define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 -# define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 - -#define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 - -#define AVIVO_GPIO_0 0x7e30 -#define AVIVO_GPIO_1 0x7e40 -#define AVIVO_GPIO_2 0x7e50 -#define AVIVO_GPIO_3 0x7e60 - -#define AVIVO_DC_GPIO_HPD_Y 0x7e9c - -#define AVIVO_I2C_STATUS 0x7d30 -# define AVIVO_I2C_STATUS_DONE (1 << 0) -# define AVIVO_I2C_STATUS_NACK (1 << 1) -# define AVIVO_I2C_STATUS_HALT (1 << 2) -# define AVIVO_I2C_STATUS_GO (1 << 3) -# define AVIVO_I2C_STATUS_MASK 0x7 -/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe - * DONE? */ -# define AVIVO_I2C_STATUS_CMD_RESET 0x7 -# define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) -#define AVIVO_I2C_STOP 0x7d34 -#define AVIVO_I2C_START_CNTL 0x7d38 -# define AVIVO_I2C_START (1 << 8) -# define AVIVO_I2C_CONNECTOR0 (0 << 16) -# define AVIVO_I2C_CONNECTOR1 (1 << 16) -#define R520_I2C_START (1<<0) -#define R520_I2C_STOP (1<<1) -#define R520_I2C_RX (1<<2) -#define R520_I2C_EN (1<<8) -#define R520_I2C_DDC1 (0<<16) -#define R520_I2C_DDC2 (1<<16) -#define R520_I2C_DDC3 (2<<16) -#define R520_I2C_DDC_MASK (3<<16) -#define AVIVO_I2C_CONTROL2 0x7d3c -# define AVIVO_I2C_7D3C_SIZE_SHIFT 8 -# define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) -#define AVIVO_I2C_CONTROL3 0x7d40 -/* Reading is done 4 bytes at a time: read the bottom 8 bits from - * 7d44, four times in a row. - * Writing is a little more complex. First write DATA with - * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic - * magic number, zz is, I think, the slave address, and yy is the byte - * you want to write. */ -#define AVIVO_I2C_DATA 0x7d44 -#define R520_I2C_ADDR_COUNT_MASK (0x7) -#define R520_I2C_DATA_COUNT_SHIFT (8) -#define R520_I2C_DATA_COUNT_MASK (0xF00) -#define AVIVO_I2C_CNTL 0x7d50 -# define AVIVO_I2C_EN (1 << 0) -# define AVIVO_I2C_RESET (1 << 8) - -#define R600_GENERAL_PWRMGT 0x618 -# define R600_OPEN_DRAIN_PADS (1 << 11) - -#define R600_LOWER_GPIO_ENABLE 0x710 -#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 -#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c -#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 -#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 - -#define R600_MC_VM_FB_LOCATION 0x2180 -#define R600_MC_VM_AGP_TOP 0x2184 -#define R600_MC_VM_AGP_BOT 0x2188 -#define R600_MC_VM_AGP_BASE 0x218c -#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 -#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 -#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 - -#define R700_MC_VM_FB_LOCATION 0x2024 - -#define R600_HDP_NONSURFACE_BASE 0x2c04 - -#define R600_BUS_CNTL 0x5420 -#define R600_CONFIG_CNTL 0x5424 -#define R600_CONFIG_MEMSIZE 0x5428 -#define R600_CONFIG_F0_BASE 0x542C -#define R600_CONFIG_APER_SIZE 0x5430 - -#define R600_ROM_CNTL 0x1600 -# define R600_SCK_OVERWRITE (1 << 1) -# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 -# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) - -#define R600_BIOS_0_SCRATCH 0x1724 -#define R600_BIOS_1_SCRATCH 0x1728 -#define R600_BIOS_2_SCRATCH 0x172c -#define R600_BIOS_3_SCRATCH 0x1730 -#define R600_BIOS_4_SCRATCH 0x1734 -#define R600_BIOS_5_SCRATCH 0x1738 -#define R600_BIOS_6_SCRATCH 0x173c -#define R600_BIOS_7_SCRATCH 0x1740 - -#define R300_GB_TILE_CONFIG 0x4018 -# define R300_ENABLE_TILING (1 << 0) -# define R300_PIPE_COUNT_RV350 (0 << 1) -# define R300_PIPE_COUNT_R300 (3 << 1) -# define R300_PIPE_COUNT_R420_3P (6 << 1) -# define R300_PIPE_COUNT_R420 (7 << 1) -# define R300_TILE_SIZE_8 (0 << 4) -# define R300_TILE_SIZE_16 (1 << 4) -# define R300_TILE_SIZE_32 (2 << 4) -# define R300_SUBPIXEL_1_12 (0 << 16) -# define R300_SUBPIXEL_1_16 (1 << 16) -#define R300_GB_SELECT 0x401c -#define R300_GB_ENABLE 0x4008 -#define R300_GB_AA_CONFIG 0x4020 -#define R400_GB_PIPE_SELECT 0x402c -#define R300_GB_MSPOS0 0x4010 -# define R300_MS_X0_SHIFT 0 -# define R300_MS_Y0_SHIFT 4 -# define R300_MS_X1_SHIFT 8 -# define R300_MS_Y1_SHIFT 12 -# define R300_MS_X2_SHIFT 16 -# define R300_MS_Y2_SHIFT 20 -# define R300_MSBD0_Y_SHIFT 24 -# define R300_MSBD0_X_SHIFT 28 -#define R300_GB_MSPOS1 0x4014 -# define R300_MS_X3_SHIFT 0 -# define R300_MS_Y3_SHIFT 4 -# define R300_MS_X4_SHIFT 8 -# define R300_MS_Y4_SHIFT 12 -# define R300_MS_X5_SHIFT 16 -# define R300_MS_Y5_SHIFT 20 -# define R300_MSBD1_SHIFT 24 - -#define R300_GA_ENHANCE 0x4274 -# define R300_GA_DEADLOCK_CNTL (1 << 0) -# define R300_GA_FASTSYNC_CNTL (1 << 1) - -#define R300_GA_POLY_MODE 0x4288 -# define R300_FRONT_PTYPE_POINT (0 << 4) -# define R300_FRONT_PTYPE_LINE (1 << 4) -# define R300_FRONT_PTYPE_TRIANGE (2 << 4) -# define R300_BACK_PTYPE_POINT (0 << 7) -# define R300_BACK_PTYPE_LINE (1 << 7) -# define R300_BACK_PTYPE_TRIANGE (2 << 7) -#define R300_GA_ROUND_MODE 0x428c -# define R300_GEOMETRY_ROUND_TRUNC (0 << 0) -# define R300_GEOMETRY_ROUND_NEAREST (1 << 0) -# define R300_COLOR_ROUND_TRUNC (0 << 2) -# define R300_COLOR_ROUND_NEAREST (1 << 2) -#define R300_GA_COLOR_CONTROL 0x4278 -# define R300_RGB0_SHADING_SOLID (0 << 0) -# define R300_RGB0_SHADING_FLAT (1 << 0) -# define R300_RGB0_SHADING_GOURAUD (2 << 0) -# define R300_ALPHA0_SHADING_SOLID (0 << 2) -# define R300_ALPHA0_SHADING_FLAT (1 << 2) -# define R300_ALPHA0_SHADING_GOURAUD (2 << 2) -# define R300_RGB1_SHADING_SOLID (0 << 4) -# define R300_RGB1_SHADING_FLAT (1 << 4) -# define R300_RGB1_SHADING_GOURAUD (2 << 4) -# define R300_ALPHA1_SHADING_SOLID (0 << 6) -# define R300_ALPHA1_SHADING_FLAT (1 << 6) -# define R300_ALPHA1_SHADING_GOURAUD (2 << 6) -# define R300_RGB2_SHADING_SOLID (0 << 8) -# define R300_RGB2_SHADING_FLAT (1 << 8) -# define R300_RGB2_SHADING_GOURAUD (2 << 8) -# define R300_ALPHA2_SHADING_SOLID (0 << 10) -# define R300_ALPHA2_SHADING_FLAT (1 << 10) -# define R300_ALPHA2_SHADING_GOURAUD (2 << 10) -# define R300_RGB3_SHADING_SOLID (0 << 12) -# define R300_RGB3_SHADING_FLAT (1 << 12) -# define R300_RGB3_SHADING_GOURAUD (2 << 12) -# define R300_ALPHA3_SHADING_SOLID (0 << 14) -# define R300_ALPHA3_SHADING_FLAT (1 << 14) -# define R300_ALPHA3_SHADING_GOURAUD (2 << 14) -#define R300_GA_OFFSET 0x4290 - -#define R500_SU_REG_DEST 0x42c8 - -#define R300_VAP_CNTL_STATUS 0x2140 -# define R300_PVS_BYPASS (1 << 8) -#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 -#define R300_VAP_CNTL 0x2080 -# define R300_PVS_NUM_SLOTS_SHIFT 0 -# define R300_PVS_NUM_CNTLRS_SHIFT 4 -# define R300_PVS_NUM_FPUS_SHIFT 8 -# define R300_VF_MAX_VTX_NUM_SHIFT 18 -# define R300_GL_CLIP_SPACE_DEF (0 << 22) -# define R300_DX_CLIP_SPACE_DEF (1 << 22) -# define R500_TCL_STATE_OPTIMIZATION (1 << 23) -#define R300_VAP_VTE_CNTL 0x20B0 -# define R300_VPORT_X_SCALE_ENA (1 << 0) -# define R300_VPORT_X_OFFSET_ENA (1 << 1) -# define R300_VPORT_Y_SCALE_ENA (1 << 2) -# define R300_VPORT_Y_OFFSET_ENA (1 << 3) -# define R300_VPORT_Z_SCALE_ENA (1 << 4) -# define R300_VPORT_Z_OFFSET_ENA (1 << 5) -# define R300_VTX_XY_FMT (1 << 8) -# define R300_VTX_Z_FMT (1 << 9) -# define R300_VTX_W0_FMT (1 << 10) -#define R300_VAP_VTX_STATE_CNTL 0x2180 -#define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC -#define R300_VAP_PROG_STREAM_CNTL_0 0x2150 -# define R300_DATA_TYPE_0_SHIFT 0 -# define R300_DATA_TYPE_FLOAT_1 0 -# define R300_DATA_TYPE_FLOAT_2 1 -# define R300_DATA_TYPE_FLOAT_3 2 -# define R300_DATA_TYPE_FLOAT_4 3 -# define R300_DATA_TYPE_BYTE 4 -# define R300_DATA_TYPE_D3DCOLOR 5 -# define R300_DATA_TYPE_SHORT_2 6 -# define R300_DATA_TYPE_SHORT_4 7 -# define R300_DATA_TYPE_VECTOR_3_TTT 8 -# define R300_DATA_TYPE_VECTOR_3_EET 9 -# define R300_SKIP_DWORDS_0_SHIFT 4 -# define R300_DST_VEC_LOC_0_SHIFT 8 -# define R300_LAST_VEC_0 (1 << 13) -# define R300_SIGNED_0 (1 << 14) -# define R300_NORMALIZE_0 (1 << 15) -# define R300_DATA_TYPE_1_SHIFT 16 -# define R300_SKIP_DWORDS_1_SHIFT 20 -# define R300_DST_VEC_LOC_1_SHIFT 24 -# define R300_LAST_VEC_1 (1 << 29) -# define R300_SIGNED_1 (1 << 30) -# define R300_NORMALIZE_1 (1 << 31) -#define R300_VAP_PROG_STREAM_CNTL_1 0x2154 -# define R300_DATA_TYPE_2_SHIFT 0 -# define R300_SKIP_DWORDS_2_SHIFT 4 -# define R300_DST_VEC_LOC_2_SHIFT 8 -# define R300_LAST_VEC_2 (1 << 13) -# define R300_SIGNED_2 (1 << 14) -# define R300_NORMALIZE_2 (1 << 15) -# define R300_DATA_TYPE_3_SHIFT 16 -# define R300_SKIP_DWORDS_3_SHIFT 20 -# define R300_DST_VEC_LOC_3_SHIFT 24 -# define R300_LAST_VEC_3 (1 << 29) -# define R300_SIGNED_3 (1 << 30) -# define R300_NORMALIZE_3 (1 << 31) -#define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 -# define R300_SWIZZLE_SELECT_X_0_SHIFT 0 -# define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 -# define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 -# define R300_SWIZZLE_SELECT_W_0_SHIFT 9 -# define R300_SWIZZLE_SELECT_X 0 -# define R300_SWIZZLE_SELECT_Y 1 -# define R300_SWIZZLE_SELECT_Z 2 -# define R300_SWIZZLE_SELECT_W 3 -# define R300_SWIZZLE_SELECT_FP_ZERO 4 -# define R300_SWIZZLE_SELECT_FP_ONE 5 -# define R300_WRITE_ENA_0_SHIFT 12 -# define R300_WRITE_ENA_X 1 -# define R300_WRITE_ENA_Y 2 -# define R300_WRITE_ENA_Z 4 -# define R300_WRITE_ENA_W 8 -# define R300_SWIZZLE_SELECT_X_1_SHIFT 16 -# define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 -# define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 -# define R300_SWIZZLE_SELECT_W_1_SHIFT 25 -# define R300_WRITE_ENA_1_SHIFT 28 -#define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 -# define R300_SWIZZLE_SELECT_X_2_SHIFT 0 -# define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 -# define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 -# define R300_SWIZZLE_SELECT_W_2_SHIFT 9 -# define R300_WRITE_ENA_2_SHIFT 12 -# define R300_SWIZZLE_SELECT_X_3_SHIFT 16 -# define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 -# define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 -# define R300_SWIZZLE_SELECT_W_3_SHIFT 25 -# define R300_WRITE_ENA_3_SHIFT 28 -#define R300_VAP_PVS_CODE_CNTL_0 0x22D0 -# define R300_PVS_FIRST_INST_SHIFT 0 -# define R300_PVS_XYZW_VALID_INST_SHIFT 10 -# define R300_PVS_LAST_INST_SHIFT 20 -#define R300_VAP_PVS_CODE_CNTL_1 0x22D8 -# define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 -#define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 -#define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 -/* PVS instructions */ -/* Opcode and dst instruction */ -#define R300_PVS_DST_OPCODE(x) (x << 0) -/* Vector ops */ -# define R300_VECTOR_NO_OP 0 -# define R300_VE_DOT_PRODUCT 1 -# define R300_VE_MULTIPLY 2 -# define R300_VE_ADD 3 -# define R300_VE_MULTIPLY_ADD 4 -# define R300_VE_DISTANCE_VECTOR 5 -# define R300_VE_FRACTION 6 -# define R300_VE_MAXIMUM 7 -# define R300_VE_MINIMUM 8 -# define R300_VE_SET_GREATER_THAN_EQUAL 9 -# define R300_VE_SET_LESS_THAN 10 -# define R300_VE_MULTIPLYX2_ADD 11 -# define R300_VE_MULTIPLY_CLAMP 12 -# define R300_VE_FLT2FIX_DX 13 -# define R300_VE_FLT2FIX_DX_RND 14 -/* R500 additions */ -# define R500_VE_PRED_SET_EQ_PUSH 15 -# define R500_VE_PRED_SET_GT_PUSH 16 -# define R500_VE_PRED_SET_GTE_PUSH 17 -# define R500_VE_PRED_SET_NEQ_PUSH 18 -# define R500_VE_COND_WRITE_EQ 19 -# define R500_VE_COND_WRITE_GT 20 -# define R500_VE_COND_WRITE_GTE 21 -# define R500_VE_COND_WRITE_NEQ 22 -# define R500_VE_COND_MUX_EQ 23 -# define R500_VE_COND_MUX_GT 24 -# define R500_VE_COND_MUX_GTE 25 -# define R500_VE_SET_GREATER_THAN 26 -# define R500_VE_SET_EQUAL 27 -# define R500_VE_SET_NOT_EQUAL 28 -/* Math ops */ -# define R300_MATH_NO_OP 0 -# define R300_ME_EXP_BASE2_DX 1 -# define R300_ME_LOG_BASE2_DX 2 -# define R300_ME_EXP_BASEE_FF 3 -# define R300_ME_LIGHT_COEFF_DX 4 -# define R300_ME_POWER_FUNC_FF 5 -# define R300_ME_RECIP_DX 6 -# define R300_ME_RECIP_FF 7 -# define R300_ME_RECIP_SQRT_DX 8 -# define R300_ME_RECIP_SQRT_FF 9 -# define R300_ME_MULTIPLY 10 -# define R300_ME_EXP_BASE2_FULL_DX 11 -# define R300_ME_LOG_BASE2_FULL_DX 12 -# define R300_ME_POWER_FUNC_FF_CLAMP_B 13 -# define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 -# define R300_ME_POWER_FUNC_FF_CLAMP_01 15 -# define R300_ME_SIN 16 -# define R300_ME_COS 17 -/* R500 additions */ -# define R500_ME_LOG_BASE2_IEEE 18 -# define R500_ME_RECIP_IEEE 19 -# define R500_ME_RECIP_SQRT_IEEE 20 -# define R500_ME_PRED_SET_EQ 21 -# define R500_ME_PRED_SET_GT 22 -# define R500_ME_PRED_SET_GTE 23 -# define R500_ME_PRED_SET_NEQ 24 -# define R500_ME_PRED_SET_CLR 25 -# define R500_ME_PRED_SET_INV 26 -# define R500_ME_PRED_SET_POP 27 -# define R500_ME_PRED_SET_RESTORE 28 -/* macro */ -# define R300_PVS_MACRO_OP_2CLK_MADD 0 -# define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 -#define R300_PVS_DST_MATH_INST (1 << 6) -#define R300_PVS_DST_MACRO_INST (1 << 7) -#define R300_PVS_DST_REG_TYPE(x) (x << 8) -# define R300_PVS_DST_REG_TEMPORARY 0 -# define R300_PVS_DST_REG_A0 1 -# define R300_PVS_DST_REG_OUT 2 -# define R500_PVS_DST_REG_OUT_REPL_X 3 -# define R300_PVS_DST_REG_ALT_TEMPORARY 4 -# define R300_PVS_DST_REG_INPUT 5 -#define R300_PVS_DST_ADDR_MODE_1 (1 << 12) -#define R300_PVS_DST_OFFSET(x) (x << 13) -#define R300_PVS_DST_WE_X (1 << 20) -#define R300_PVS_DST_WE_Y (1 << 21) -#define R300_PVS_DST_WE_Z (1 << 22) -#define R300_PVS_DST_WE_W (1 << 23) -#define R300_PVS_DST_VE_SAT (1 << 24) -#define R300_PVS_DST_ME_SAT (1 << 25) -#define R300_PVS_DST_PRED_ENABLE (1 << 26) -#define R300_PVS_DST_PRED_SENSE (1 << 27) -#define R300_PVS_DST_DUAL_MATH_OP (1 << 28) -#define R300_PVS_DST_ADDR_SEL(x) (x << 29) -#define R300_PVS_DST_ADDR_MODE_0 (1 << 31) -/* src operand instruction */ -#define R300_PVS_SRC_REG_TYPE(x) (x << 0) -# define R300_PVS_SRC_REG_TEMPORARY 0 -# define R300_PVS_SRC_REG_INPUT 1 -# define R300_PVS_SRC_REG_CONSTANT 2 -# define R300_PVS_SRC_REG_ALT_TEMPORARY 3 -#define R300_SPARE_0 (1 << 2) -#define R300_PVS_SRC_ABS_XYZW (1 << 3) -#define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) -#define R300_PVS_SRC_OFFSET(x) (x << 5) -#define R300_PVS_SRC_SWIZZLE_X(x) (x << 13) -#define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16) -#define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19) -#define R300_PVS_SRC_SWIZZLE_W(x) (x << 22) -# define R300_PVS_SRC_SELECT_X 0 -# define R300_PVS_SRC_SELECT_Y 1 -# define R300_PVS_SRC_SELECT_Z 2 -# define R300_PVS_SRC_SELECT_W 3 -# define R300_PVS_SRC_SELECT_FORCE_0 4 -# define R300_PVS_SRC_SELECT_FORCE_1 5 -#define R300_PVS_SRC_NEG_X (1 << 25) -#define R300_PVS_SRC_NEG_Y (1 << 26) -#define R300_PVS_SRC_NEG_Z (1 << 27) -#define R300_PVS_SRC_NEG_W (1 << 28) -#define R300_PVS_SRC_ADDR_SEL(x) (x << 29) -#define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) - -#define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc -#define R300_VAP_OUT_VTX_FMT_0 0x2090 -# define R300_VTX_POS_PRESENT (1 << 0) -# define R300_VTX_COLOR_0_PRESENT (1 << 1) -# define R300_VTX_COLOR_1_PRESENT (1 << 2) -# define R300_VTX_COLOR_2_PRESENT (1 << 3) -# define R300_VTX_COLOR_3_PRESENT (1 << 4) -# define R300_VTX_PT_SIZE_PRESENT (1 << 16) -#define R300_VAP_OUT_VTX_FMT_1 0x2094 -# define R300_TEX_0_COMP_CNT_SHIFT 0 -# define R300_TEX_1_COMP_CNT_SHIFT 3 -# define R300_TEX_2_COMP_CNT_SHIFT 6 -# define R300_TEX_3_COMP_CNT_SHIFT 9 -# define R300_TEX_4_COMP_CNT_SHIFT 12 -# define R300_TEX_5_COMP_CNT_SHIFT 15 -# define R300_TEX_6_COMP_CNT_SHIFT 18 -# define R300_TEX_7_COMP_CNT_SHIFT 21 -#define R300_VAP_VTX_SIZE 0x20b4 -#define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 -#define R300_VAP_GB_VERT_DISC_ADJ 0x2224 -#define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 -#define R300_VAP_GB_HORZ_DISC_ADJ 0x222c -#define R300_VAP_CLIP_CNTL 0x221c -# define R300_UCP_ENA_0 (1 << 0) -# define R300_UCP_ENA_1 (1 << 1) -# define R300_UCP_ENA_2 (1 << 2) -# define R300_UCP_ENA_3 (1 << 3) -# define R300_UCP_ENA_4 (1 << 4) -# define R300_UCP_ENA_5 (1 << 5) -# define R300_PS_UCP_MODE_SHIFT 14 -# define R300_CLIP_DISABLE (1 << 16) -# define R300_UCP_CULL_ONLY_ENA (1 << 17) -# define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) -#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 - -#define R500_VAP_INDEX_OFFSET 0x208c - -#define R300_SU_TEX_WRAP 0x42a0 -#define R300_SU_POLY_OFFSET_ENABLE 0x42b4 -#define R300_SU_CULL_MODE 0x42b8 -# define R300_CULL_FRONT (1 << 0) -# define R300_CULL_BACK (1 << 1) -# define R300_FACE_POS (0 << 2) -# define R300_FACE_NEG (1 << 2) -#define R300_SU_DEPTH_SCALE 0x42c0 -#define R300_SU_DEPTH_OFFSET 0x42c4 - -#define R300_RS_COUNT 0x4300 -# define R300_RS_COUNT_IT_COUNT_SHIFT 0 -# define R300_RS_COUNT_IC_COUNT_SHIFT 7 -# define R300_RS_COUNT_HIRES_EN (1 << 18) - -#define R300_RS_IP_0 0x4310 -#define R300_RS_IP_1 0x4314 -# define R300_RS_TEX_PTR(x) (x << 0) -# define R300_RS_COL_PTR(x) (x << 6) -# define R300_RS_COL_FMT(x) (x << 9) -# define R300_RS_COL_FMT_RGBA 0 -# define R300_RS_COL_FMT_RGB0 2 -# define R300_RS_COL_FMT_RGB1 3 -# define R300_RS_COL_FMT_000A 4 -# define R300_RS_COL_FMT_0000 5 -# define R300_RS_COL_FMT_0001 6 -# define R300_RS_COL_FMT_111A 8 -# define R300_RS_COL_FMT_1110 9 -# define R300_RS_COL_FMT_1111 10 -# define R300_RS_SEL_S(x) (x << 13) -# define R300_RS_SEL_T(x) (x << 16) -# define R300_RS_SEL_R(x) (x << 19) -# define R300_RS_SEL_Q(x) (x << 22) -# define R300_RS_SEL_C0 0 -# define R300_RS_SEL_C1 1 -# define R300_RS_SEL_C2 2 -# define R300_RS_SEL_C3 3 -# define R300_RS_SEL_K0 4 -# define R300_RS_SEL_K1 5 -#define R300_RS_INST_COUNT 0x4304 -# define R300_INST_COUNT_RS(x) (x << 0) -# define R300_RS_W_EN (1 << 4) -# define R300_TX_OFFSET_RS(x) (x << 5) -#define R300_RS_INST_0 0x4330 -#define R300_RS_INST_1 0x4334 -# define R300_INST_TEX_ID(x) (x << 0) -# define R300_RS_INST_TEX_CN_WRITE (1 << 3) -# define R300_INST_TEX_ADDR(x) (x << 6) - -#define R300_TX_INVALTAGS 0x4100 -#define R300_TX_FILTER0_0 0x4400 -#define R300_TX_FILTER0_1 0x4404 -# define R300_TX_CLAMP_S(x) (x << 0) -# define R300_TX_CLAMP_T(x) (x << 3) -# define R300_TX_CLAMP_R(x) (x << 6) -# define R300_TX_CLAMP_WRAP 0 -# define R300_TX_CLAMP_MIRROR 1 -# define R300_TX_CLAMP_CLAMP_LAST 2 -# define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 -# define R300_TX_CLAMP_CLAMP_BORDER 4 -# define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 -# define R300_TX_CLAMP_CLAMP_GL 6 -# define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 -# define R300_TX_MAG_FILTER_NEAREST (1 << 9) -# define R300_TX_MIN_FILTER_NEAREST (1 << 11) -# define R300_TX_MAG_FILTER_LINEAR (2 << 9) -# define R300_TX_MIN_FILTER_LINEAR (2 << 11) -# define R300_TX_ID_SHIFT 28 -#define R300_TX_FILTER1_0 0x4440 -#define R300_TX_FILTER1_1 0x4444 -#define R300_TX_FORMAT0_0 0x4480 -#define R300_TX_FORMAT0_1 0x4484 -# define R300_TXWIDTH_SHIFT 0 -# define R300_TXHEIGHT_SHIFT 11 -# define R300_NUM_LEVELS_SHIFT 26 -# define R300_NUM_LEVELS_MASK 0x -# define R300_TXPROJECTED (1 << 30) -# define R300_TXPITCH_EN (1 << 31) -#define R300_TX_FORMAT1_0 0x44c0 -#define R300_TX_FORMAT1_1 0x44c4 -# define R300_TX_FORMAT_X8 0x0 -# define R300_TX_FORMAT_X16 0x1 -# define R300_TX_FORMAT_Y4X4 0x2 -# define R300_TX_FORMAT_Y8X8 0x3 -# define R300_TX_FORMAT_Y16X16 0x4 -# define R300_TX_FORMAT_Z3Y3X2 0x5 -# define R300_TX_FORMAT_Z5Y6X5 0x6 -# define R300_TX_FORMAT_Z6Y5X5 0x7 -# define R300_TX_FORMAT_Z11Y11X10 0x8 -# define R300_TX_FORMAT_Z10Y11X11 0x9 -# define R300_TX_FORMAT_W4Z4Y4X4 0xA -# define R300_TX_FORMAT_W1Z5Y5X5 0xB -# define R300_TX_FORMAT_W8Z8Y8X8 0xC -# define R300_TX_FORMAT_W2Z10Y10X10 0xD -# define R300_TX_FORMAT_W16Z16Y16X16 0xE -# define R300_TX_FORMAT_DXT1 0xF -# define R300_TX_FORMAT_DXT3 0x10 -# define R300_TX_FORMAT_DXT5 0x11 -# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ -# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ -# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ -# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ -# define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ -# define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ -# define R300_TX_FORMAT_X24_Y8 0x1e -# define R300_TX_FORMAT_X32 0x1e - /* Floating point formats */ - /* Note - hardware supports both 16 and 32 bit floating point */ -# define R300_TX_FORMAT_FL_I16 0x18 -# define R300_TX_FORMAT_FL_I16A16 0x19 -# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A -# define R300_TX_FORMAT_FL_I32 0x1B -# define R300_TX_FORMAT_FL_I32A32 0x1C -# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D - /* alpha modes, convenience mostly */ - /* if you have alpha, pick constant appropriate to the - number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ -# define R300_TX_FORMAT_ALPHA_1CH 0x000 -# define R300_TX_FORMAT_ALPHA_2CH 0x200 -# define R300_TX_FORMAT_ALPHA_4CH 0x600 -# define R300_TX_FORMAT_ALPHA_NONE 0xA00 - /* Swizzling */ - /* constants */ -# define R300_TX_FORMAT_X 0 -# define R300_TX_FORMAT_Y 1 -# define R300_TX_FORMAT_Z 2 -# define R300_TX_FORMAT_W 3 -# define R300_TX_FORMAT_ZERO 4 -# define R300_TX_FORMAT_ONE 5 - /* 2.0*Z, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_Z 6 - /* 2.0*W, everything above 1.0 is set to 0.0 */ -# define R300_TX_FORMAT_CUT_W 7 - -# define R300_TX_FORMAT_B_SHIFT 18 -# define R300_TX_FORMAT_G_SHIFT 15 -# define R300_TX_FORMAT_R_SHIFT 12 -# define R300_TX_FORMAT_A_SHIFT 9 - - /* Convenience macro to take care of layout and swizzling */ -# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ - ((R300_TX_FORMAT_##B)< Date: Sat, 24 Jan 2009 03:34:17 -0800 Subject: r300: Add some useful debugging information; remove a couple compile warnings. Deck chairs on the Titanic. --- src/gallium/drivers/r300/r300_chipset.h | 27 ------------- src/gallium/drivers/r300/r300_cs.h | 16 ++++++-- src/gallium/drivers/r300/r300_screen.c | 72 +++++++++++++++++++++++++++++---- 3 files changed, 77 insertions(+), 38 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h index f1502ff76c..c4104a65cb 100644 --- a/src/gallium/drivers/r300/r300_chipset.h +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -73,33 +73,6 @@ enum { CHIP_FAMILY_RV570 }; -static const char* chip_families[] = { - "R300", - "R350", - "R360", - "RV350", - "RV370", - "RV380", - "R420", - "R423", - "R430", - "R480", - "R481", - "RV410", - "RS400", - "RC410", - "RS480", - "RS482", - "RS690", - "RS740", - "RV515", - "R520", - "RV530", - "R580", - "RV560", - "RV570" -}; - void r300_parse_chipset(struct r300_capabilities* caps); #endif /* R300_CHIPSET_H */ diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 67cb5ee7d1..2dcb92d9af 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -67,6 +67,8 @@ static uint32_t pack_float_32(float f) #define BEGIN_CS(size) do { \ CHECK_CS(size); \ + debug_printf("r300: BEGIN_CS in %s (%s:%d)", __FUNCTION__, __FILE__, \ + __LINE__); \ cs_winsys->begin_cs(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ } while (0) @@ -91,10 +93,16 @@ static uint32_t pack_float_32(float f) cs_winsys->write_cs_reloc(cs, bo, rd, wd, flags); \ } while (0) -#define END_CS \ - cs_winsys->end_cs(cs, __FILE__, __FUNCTION__, __LINE__) +#define END_CS do { \ + debug_printf("r300: END_CS in %s (%s:%d)", __FUNCTION__, __FILE__, \ + __LINE__); \ + cs_winsys->end_cs(cs, __FILE__, __FUNCTION__, __LINE__); \ +} while (0) -#define FLUSH_CS \ - cs_winsys->flush_cs(cs) +#define FLUSH_CS do { \ + debug_printf("r300: FLUSH_CS in %s (%s:%d)", __FUNCTION__, __FILE__, \ + __LINE__); \ + cs_winsys->flush_cs(cs); \ +} while (0) #endif /* R300_CS_H */ diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index bd5aa4f466..dc1e41749f 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -22,11 +22,44 @@ #include "r300_screen.h" +/* Return the identifier behind whom the brave coders responsible for this + * amalgamation of code, sweat, and duct tape, routinely obscure their names. + * + * ...I should have just put "Corbin Simpson", but I'm not that cool. + * + * (Or egotistical. Yet.) */ static const char* r300_get_vendor(struct pipe_screen* pscreen) { return "X.Org R300 Project"; } +static const char* chip_families[] = { + "R300", + "R350", + "R360", + "RV350", + "RV370", + "RV380", + "R420", + "R423", + "R430", + "R480", + "R481", + "RV410", + "RS400", + "RC410", + "RS480", + "RS482", + "RS690", + "RS740", + "RV515", + "R520", + "RV530", + "R580", + "RV560", + "RV570" +}; + static const char* r300_get_name(struct pipe_screen* pscreen) { struct r300_screen* r300screen = r300_screen(pscreen); @@ -74,18 +107,39 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) /* IN THEORY */ return 0; case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: - /* 12 == 2048x2048 */ - return 12; + if (r300screen->caps->is_r500) { + /* 13 == 4096x4096 */ + return 13; + } else { + /* 12 == 2048x2048 */ + return 12; + } case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: - /* XXX educated guess */ - return 8; + /* So, technically, the limit is the same as above, but some math + * shows why this is silly. Assuming RGBA, 4cpp, we can see that + * 4096*4096*4096 = 64.0 GiB exactly, so it's not exactly + * practical. However, if at some point a game really wants this, + * then we can remove this limit. */ + if (r300screen->caps->is_r500) { + /* 9 == 256x256x256 */ + return 9; + } else { + /* 8 == 128*128*128 */ + return 8; + } case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: - /* XXX educated guess */ - return 11; + if (r300screen->caps->is_r500) { + /* 13 == 4096x4096 */ + return 13; + } else { + /* 12 == 2048x2048 */ + return 12; + } case PIPE_CAP_MAX_RENDER_TARGETS: /* XXX 4 eventually */ return 1; default: + debug_printf("r300: Implementation error: Bad param %d", param); return 0; } } @@ -108,7 +162,7 @@ static float r300_get_paramf(struct pipe_screen* pscreen, int param) case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: return 16.0f; default: - /* XXX implementation error? */ + debug_printf("r300: Implementation error: Bad paramf %d", param); return 0.0f; } } @@ -121,6 +175,8 @@ static boolean check_tex_2d_format(enum pipe_format format) case PIPE_FORMAT_I8_UNORM: return TRUE; default: + debug_printf("r300: Warning: Got unknown format: %d, in %s", + format, __FUNCTION__); break; } @@ -138,6 +194,8 @@ static boolean r300_is_format_supported(struct pipe_screen* pscreen, case PIPE_TEXTURE_2D: return check_tex_2d_format(format); default: + debug_printf("r300: Warning: Got unknown format target: %d", + format); break; } -- cgit v1.2.3 From 161f4068aa5f8b556d0c00c3e31192b3736aada5 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 04:03:11 -0800 Subject: r300: More state setters. --- src/gallium/drivers/r300/r300_state.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index e52d8ec9c2..1f6abc2385 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -704,13 +704,33 @@ static void r300_set_scissor_state(struct pipe_context* pipe, } static void r300_set_viewport_state(struct pipe_context* pipe, - const struct pipe_viewport_state* state) + const struct pipe_viewport_state* state) { struct r300_context* r300 = r300_context(pipe); /* XXX handing this off to Draw for now */ draw_set_viewport_state(r300->draw, state); } +static void r300_set_vertex_buffers(struct pipe_context* pipe, + unsigned count, + const struct pipe_vertex_buffer* buffers) +{ + struct r300_context* r300 = r300_context(pipe); + /* XXX Draw */ + draw_flush(r300->draw); + draw_set_vertex_buffers(r300->draw, count, buffers); +} + +static void r300_set_vertex_elements(struct pipe_context* pipe, + unsigned count, + const struct pipe_vertex_element* elements) +{ + struct r300_context* r300 = r300_context(pipe); + /* XXX Draw */ + draw_flush(r300->draw); + draw_set_vertex_elements(r300->draw, count, elements); +} + static void* r300_create_vs_state(struct pipe_context* pipe, const struct pipe_shader_state* state) { @@ -772,8 +792,8 @@ void r300_init_state_functions(struct r300_context* r300) r300->context.set_viewport_state = r300_set_viewport_state; - /* XXX r300->context.set_vertex_buffers = r300_set_vertex_buffers; - * XXX r300->context.set_vertex_elements = r300_set_vertex_elements; */ + r300->context.set_vertex_buffers = r300_set_vertex_buffers; + r300->context.set_vertex_elements = r300_set_vertex_elements; r300->context.create_vs_state = r300_create_vs_state; r300->context.bind_vs_state = r300_bind_vs_state; -- cgit v1.2.3 From f2a7d4f2e8e890e69e1dfa9067db4e90df63989f Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 04:03:27 -0800 Subject: r300: Newlines, dammit! --- src/gallium/drivers/r300/r300_cs.h | 6 +++--- src/gallium/drivers/r300/r300_screen.c | 10 ++++++---- 2 files changed, 9 insertions(+), 7 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 2dcb92d9af..e6860cbaf7 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -67,7 +67,7 @@ static uint32_t pack_float_32(float f) #define BEGIN_CS(size) do { \ CHECK_CS(size); \ - debug_printf("r300: BEGIN_CS in %s (%s:%d)", __FUNCTION__, __FILE__, \ + debug_printf("r300: BEGIN_CS in %s (%s:%d)\n", __FUNCTION__, __FILE__, \ __LINE__); \ cs_winsys->begin_cs(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ } while (0) @@ -94,13 +94,13 @@ static uint32_t pack_float_32(float f) } while (0) #define END_CS do { \ - debug_printf("r300: END_CS in %s (%s:%d)", __FUNCTION__, __FILE__, \ + debug_printf("r300: END_CS in %s (%s:%d)\n", __FUNCTION__, __FILE__, \ __LINE__); \ cs_winsys->end_cs(cs, __FILE__, __FUNCTION__, __LINE__); \ } while (0) #define FLUSH_CS do { \ - debug_printf("r300: FLUSH_CS in %s (%s:%d)", __FUNCTION__, __FILE__, \ + debug_printf("r300: FLUSH_CS in %s (%s:%d)\n", __FUNCTION__, __FILE__, \ __LINE__); \ cs_winsys->flush_cs(cs); \ } while (0) diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index dc1e41749f..25ddb0e8c6 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -139,7 +139,8 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) /* XXX 4 eventually */ return 1; default: - debug_printf("r300: Implementation error: Bad param %d", param); + debug_printf("r300: Implementation error: Bad param %d\n", + param); return 0; } } @@ -162,7 +163,8 @@ static float r300_get_paramf(struct pipe_screen* pscreen, int param) case PIPE_CAP_MAX_TEXTURE_LOD_BIAS: return 16.0f; default: - debug_printf("r300: Implementation error: Bad paramf %d", param); + debug_printf("r300: Implementation error: Bad paramf %d\n", + param); return 0.0f; } } @@ -175,7 +177,7 @@ static boolean check_tex_2d_format(enum pipe_format format) case PIPE_FORMAT_I8_UNORM: return TRUE; default: - debug_printf("r300: Warning: Got unknown format: %d, in %s", + debug_printf("r300: Warning: Got unknown format: %d, in %s\n", format, __FUNCTION__); break; } @@ -194,7 +196,7 @@ static boolean r300_is_format_supported(struct pipe_screen* pscreen, case PIPE_TEXTURE_2D: return check_tex_2d_format(format); default: - debug_printf("r300: Warning: Got unknown format target: %d", + debug_printf("r300: Warning: Got unknown format target: %d\n", format); break; } -- cgit v1.2.3 From f045988ee101fbef77f280f37f56967e6a95c5f2 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 04:08:33 -0800 Subject: r300: Add more capabilities. --- src/gallium/drivers/r300/r300_screen.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 25ddb0e8c6..6de97a79e1 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -80,9 +80,6 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) case PIPE_CAP_NPOT_TEXTURES: /* IN THEORY */ return 0; - case PIPE_CAP_S3TC: - /* IN THEORY */ - return 0; case PIPE_CAP_TWO_SIDED_STENCIL: /* IN THEORY */ /* if (r300screen->is_r500) { @@ -91,21 +88,27 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) * return 0; * } */ return 0; + case PIPE_CAP_GLSL: + /* IN THEORY */ + return 0; + case PIPE_CAP_S3TC: + /* IN THEORY */ + return 0; case PIPE_CAP_ANISOTROPIC_FILTER: /* IN THEORY */ return 0; case PIPE_CAP_POINT_SPRITE: /* IN THEORY */ return 0; + case PIPE_CAP_MAX_RENDER_TARGETS: + /* XXX 4 eventually */ + return 1; case PIPE_CAP_OCCLUSION_QUERY: /* IN THEORY */ return 0; case PIPE_CAP_TEXTURE_SHADOW_MAP: /* IN THEORY */ return 0; - case PIPE_CAP_GLSL: - /* IN THEORY */ - return 0; case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: if (r300screen->caps->is_r500) { /* 13 == 4096x4096 */ @@ -135,9 +138,13 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) /* 12 == 2048x2048 */ return 12; } - case PIPE_CAP_MAX_RENDER_TARGETS: - /* XXX 4 eventually */ + case PIPE_CAP_TEXTURE_MIRROR_CLAMP: + return 1; + case PIPE_CAP_TEXTURE_MIRROR_REPEAT: return 1; + case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS: + /* XXX guessing */ + return 2; default: debug_printf("r300: Implementation error: Bad param %d\n", param); -- cgit v1.2.3 From 57b062f77551f0111fd210a2d8dd44be6acfc818 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 04:11:03 -0800 Subject: r300: Make format names legible. --- src/gallium/drivers/r300/r300_screen.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 6de97a79e1..607dfe911c 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -184,8 +184,8 @@ static boolean check_tex_2d_format(enum pipe_format format) case PIPE_FORMAT_I8_UNORM: return TRUE; default: - debug_printf("r300: Warning: Got unknown format: %d, in %s\n", - format, __FUNCTION__); + debug_printf("r300: Warning: Got unknown format: %s, in %s\n", + pf_name(format), __FUNCTION__); break; } -- cgit v1.2.3 From 188f61d43ae82c63d557d25282e349926321e3d0 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 05:44:01 -0800 Subject: r300: Hook up clear, set it to fallback. --- src/gallium/drivers/r300/r300_context.c | 2 ++ src/gallium/drivers/r300/r300_context.h | 1 + src/gallium/drivers/r300/r300_state.c | 18 ++++++++++++++++-- src/gallium/drivers/r300/r300_surface.c | 8 +++++++- 4 files changed, 26 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index 314b2f0a11..e63e1278bf 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -47,6 +47,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->context.destroy = r300_destroy_context; + r300->context.clear = r300_clear; + r300->draw = draw_create(); r300->blend_color_state = CALLOC_STRUCT(r300_blend_color_state); diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 52ddfa1df9..f246c57f48 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -27,6 +27,7 @@ #include "pipe/p_context.h" #include "util/u_memory.h" +#include "r300_clear.h" #include "r300_screen.h" #include "r300_winsys.h" diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 1f6abc2385..907ebe5c75 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -204,6 +204,14 @@ static void r300_set_clip_state(struct pipe_context* pipe, draw_set_clip_state(r300->draw, state); } +static void + r300_set_constant_buffer(struct pipe_context* pipe, + uint shader, uint index, + const struct pipe_constant_buffer* buffer) +{ + /* XXX */ +} + static uint32_t translate_depth_stencil_function(int zs_func) { switch (zs_func) { case PIPE_FUNC_NEVER: @@ -367,6 +375,12 @@ static void r300_delete_dsa_state(struct pipe_context* pipe, FREE(state); } +static void r300_set_edgeflags(struct pipe_context* pipe, + const unsigned* bitfield) +{ + /* XXX you know it's bad when i915 has this blank too */ +} + static void r300_set_framebuffer_state(struct pipe_context* pipe, const struct pipe_framebuffer_state* state) @@ -762,13 +776,13 @@ void r300_init_state_functions(struct r300_context* r300) r300->context.set_clip_state = r300_set_clip_state; - /* XXX r300->context.set_constant_buffer = r300_set_constant_buffer; */ + r300->context.set_constant_buffer = r300_set_constant_buffer; r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; - /* XXX r300->context.set_edgeflags = r300_set_edgeflags; */ + r300->context.set_edgeflags = r300_set_edgeflags; r300->context.set_framebuffer_state = r300_set_framebuffer_state; diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index dd1c8862a7..c9957a0af2 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -30,6 +30,12 @@ static void r300_surface_fill(struct pipe_context* pipe, unsigned w, unsigned h, unsigned color) { + +void *dst_map = pipe->screen->surface_map( pipe->screen, dest, +PIPE_BUFFER_USAGE_CPU_WRITE ); +pipe_fill_rect(dst_map, &dest->block, dest->stride, x, y, w, h, color); +pipe->screen->surface_unmap(pipe->screen, dest); +return; struct r300_context* r300 = r300_context(pipe); CS_LOCALS(r300); struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps; @@ -278,7 +284,7 @@ static void r300_surface_fill(struct pipe_context* pipe, /* XXX might have to switch to 2D */ OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_CS_RELOC(0, dest->buffer, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); /* XXX this needs more TLC (or TCL, as it were) */ OUT_CS_REG(R300_RB3D_COLORPITCH0, R300_COLOR_FORMAT_ARGB8888); #if 0 -- cgit v1.2.3 From f40e6988bdbdc89a7753d5a28323757e58f3e01f Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sat, 24 Jan 2009 06:21:00 -0800 Subject: Rebased to gallium-0.2, Jan 24 2009. --- src/gallium/drivers/r300/r300_texture.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 4adfe478c3..eb7c9d06f5 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -120,7 +120,6 @@ static struct pipe_surface* r300_get_tex_surface(struct pipe_screen* screen, if (surface) { surface->refcount = 1; - surface->winsys = screen->winsys; pipe_texture_reference(&surface->texture, texture); pipe_buffer_reference(screen, &surface->buffer, tex->buffer); surface->format = texture->format; -- cgit v1.2.3 From 412cf4d38be628200982208b7f93bb17530bb6db Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sun, 25 Jan 2009 16:29:02 -0800 Subject: BROKEN This commit is only to protect against data loss, so please skip it when bisecting. Thanks. --- src/gallium/drivers/r300/r300_cs.h | 15 +- src/gallium/drivers/r300/r300_surface.c | 320 ++++++++++++++++++++++++++++++- src/gallium/winsys/drm/amd/amd_context.c | 2 +- 3 files changed, 322 insertions(+), 15 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index e6860cbaf7..edcfb9628f 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -72,19 +72,24 @@ static uint32_t pack_float_32(float f) cs_winsys->begin_cs(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ } while (0) -#define OUT_CS(value) \ - cs_winsys->write_cs_dword(cs, value) +#define OUT_CS(value) do { \ + cs_winsys->write_cs_dword(cs, value); \ +} while (0) -#define OUT_CS_32F(value) \ - cs_winsys->write_cs_dword(cs, pack_float_32(value)) +#define OUT_CS_32F(value) do { \ + cs_winsys->write_cs_dword(cs, pack_float_32(value)); \ +} while (0) #define OUT_CS_REG(register, value) do { \ + debug_printf("writing 0x%x to register 0x%x\n", value, register); \ OUT_CS(CP_PACKET0(register, 0)); \ - OUT_CS(value); } while (0) + OUT_CS(value); \ +} while (0) /* Note: This expects count to be the number of registers, * not the actual packet0 count! */ #define OUT_CS_REG_SEQ(register, count) do { \ + debug_printf("writing register sequence 0x%x\n", register); \ OUT_CS(CP_PACKET0(register, ((count) - 1))); \ } while (0) diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index c9957a0af2..8afa06dec8 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -30,14 +30,9 @@ static void r300_surface_fill(struct pipe_context* pipe, unsigned w, unsigned h, unsigned color) { - -void *dst_map = pipe->screen->surface_map( pipe->screen, dest, -PIPE_BUFFER_USAGE_CPU_WRITE ); -pipe_fill_rect(dst_map, &dest->block, dest->stride, x, y, w, h, color); -pipe->screen->surface_unmap(pipe->screen, dest); -return; struct r300_context* r300 = r300_context(pipe); CS_LOCALS(r300); +#if 0 struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps; boolean has_tcl = caps->has_tcl; boolean is_r500 = caps->is_r500; @@ -47,6 +42,13 @@ return; * XXX it goes without saying that this needs to be cleaned up and * shifted around to work with the rest of the driver's state handling. */ + BEGIN_CS(450); + /* XXX */ + OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); + OUT_CS_REG(R300_TX_INVALTAGS, 0x0); + OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); + OUT_CS_REG(R300_TX_INVALTAGS, 0x0); + /* Sequence starting at R300_VAP_PROG_STREAM_CNTL_0 */ OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 1); if (has_tcl) { @@ -93,8 +95,23 @@ return; R300_VPORT_Z_OFFSET_ENA); OUT_CS(0x8); + /* XXX */ + OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2); + OUT_CS(0xFFFFFF); + OUT_CS(0x0); + + OUT_CS_REG(R300_VAP_CNTL_STATUS, 0x0); + + OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4); + OUT_CS(0x3f800000); + OUT_CS(0x3f800000); + OUT_CS(0x3f800000); + OUT_CS(0x3f800000); + OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); + OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff); + OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); OUT_CS(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT); @@ -135,7 +152,7 @@ return; OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); } else { - OUT_CS_REG(R300_RS_IP_0, 8); + OUT_CS_REG_SEQ(R300_RS_IP_0, 8); for (i = 0; i < 8; ++i) { OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); } @@ -287,7 +304,6 @@ return; OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); /* XXX this needs more TLC (or TCL, as it were) */ OUT_CS_REG(R300_RB3D_COLORPITCH0, R300_COLOR_FORMAT_ARGB8888); -#if 0 if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) { assert(rrbd != 0); cbpitch = (rrbd->pitch / rrbd->cpp); @@ -337,7 +353,11 @@ return; (ctx->Stencil.Clear & R300_STENCILREF_MASK)); END_BATCH(); } -#endif + + OUT_CS_REG_SEQ(R300_ZB_CNTL, 3); + OUT_CS(0x0); + OUT_CS(0x0); + OUT_CS(0x0); OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | @@ -355,7 +375,289 @@ return; /* XXX this should be split off, also figure out WTF with the numbers */ OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); + END_CS; FLUSH_CS; +#endif +BEGIN_CS(276); +OUT_CS_REG(0x1720, 0x00068000); +OUT_CS_REG(0x4100, 0x00000000); +OUT_CS_REG(0x1720, 0x00068000); +OUT_CS_REG(0x1D98, 0x43000000); +OUT_CS_REG(0x1D9C, 0x43002000); +OUT_CS_REG(0x1DA0, 0xC3000000); +OUT_CS_REG(0x1DA4, 0x43002000); +OUT_CS_REG(0x1DA8, 0x3F000000); +OUT_CS_REG(0x1DAC, 0x3F000000); +OUT_CS_REG(0x2284, 0x00000000); +OUT_CS_REG(0x2080, 0x0030046A); +OUT_CS_REG(0x20B0, 0x0000043F); +OUT_CS_REG(0x20B4, 0x00000008); +OUT_CS_REG(0x2134, 0x00FFFFFF); +OUT_CS_REG(0x2138, 0x00000000); +OUT_CS_REG(0x2140, 0x00000000); +OUT_CS_REG(0x2150, 0x00000000); +OUT_CS_REG(0x21E0, 0x00000000); +OUT_CS_REG(0x2180, 0x00000000); +OUT_CS_REG(0x2184, 0x00000000); +OUT_CS_REG(0x21DC, 0xAAAAAAAA); +OUT_CS_REG(0x221C, 0x00000000); +OUT_CS_REG(0x2220, 0x3F800000); +OUT_CS_REG(0x2224, 0x3F800000); +OUT_CS_REG(0x2228, 0x3F800000); +OUT_CS_REG(0x222C, 0x3F800000); +OUT_CS_REG(0x2288, 0x0000FFFF); +OUT_CS_REG(0x2090, 0x00000000); +OUT_CS_REG(0x2094, 0x00000000); +OUT_CS_REG(0x22D0, 0x00000000); +OUT_CS_REG(0x22D4, 0x00000000); +OUT_CS_REG(0x22D8, 0x00000000); +OUT_CS_REG(0x4008, 0x00000007); +OUT_CS_REG(0x4010, 0x66666666); +OUT_CS_REG(0x4014, 0x06666666); +OUT_CS_REG(0x4018, 0x00000011); +OUT_CS_REG(0x401C, 0x00000004); +OUT_CS_REG(0x4020, 0x00000000); +OUT_CS_REG(0x4104, 0x00000000); +OUT_CS_REG(0x4200, 0x00000000); +OUT_CS_REG(0x4204, 0x00000000); +OUT_CS_REG(0x4208, 0x3F800000); +OUT_CS_REG(0x420C, 0x3F800000); +OUT_CS_REG(0x4214, 0x00050005); +OUT_CS_REG(0x421C, 0x00060006); +OUT_CS_REG(0x4230, 0x18000006); +OUT_CS_REG(0x4234, 0x00020006); +OUT_CS_REG(0x4238, 0x3BAAAAAB); +OUT_CS_REG(0x4234, 0x00030006); +OUT_CS_REG(0x4260, 0x00000000); +OUT_CS_REG(0x4264, 0x00000000); +OUT_CS_REG(0x4268, 0x3F800000); +OUT_CS_REG(0x4274, 0x00000002); +OUT_CS_REG(0x4278, 0x0003AAAA); +OUT_CS_REG(0x427C, 0x00000000); +OUT_CS_REG(0x4280, 0x00000000); +OUT_CS_REG(0x4288, 0x00000000); +OUT_CS_REG(0x428C, 0x00000001); +OUT_CS_REG(0x4290, 0x00000000); +OUT_CS_REG(0x4294, 0x3DBF1412); +OUT_CS_REG(0x4298, 0x00000000); +OUT_CS_REG(0x42A0, 0x00000000); +OUT_CS_REG(0x42A4, 0x00000000); +OUT_CS_REG(0x42A8, 0x00000000); +OUT_CS_REG(0x42AC, 0x00000000); +OUT_CS_REG(0x42B0, 0x00000000); +OUT_CS_REG(0x42B4, 0x00000000); +OUT_CS_REG(0x42B8, 0x00000000); +OUT_CS_REG(0x42C0, 0x4B7FFFFF); +OUT_CS_REG(0x42C4, 0x00000000); +OUT_CS_REG(0x4300, 0x00000000); +OUT_CS_REG(0x4304, 0x00000000); +OUT_CS_REG(0x4310, 0x00000000); +OUT_CS_REG(0x4314, 0x00000000); +OUT_CS_REG(0x4318, 0x00000000); +OUT_CS_REG(0x431C, 0x00000000); +OUT_CS_REG(0x4320, 0x00000000); +OUT_CS_REG(0x4324, 0x00000000); +OUT_CS_REG(0x4328, 0x00000000); +OUT_CS_REG(0x432C, 0x00000000); +OUT_CS_REG(0x4330, 0x00000000); +OUT_CS_REG(0x43A4, 0x0000001C); +OUT_CS_REG(0x43A8, 0x2DA49525); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x46A4, 0x00001B00); +OUT_CS_REG(0x46A8, 0x00001B0F); +OUT_CS_REG(0x46AC, 0x00001B0F); +OUT_CS_REG(0x46B0, 0x00001B0F); +OUT_CS_REG(0x46B4, 0x00000001); +OUT_CS_REG(0x4600, 0x00000000); +OUT_CS_REG(0x4604, 0x00000000); +OUT_CS_REG(0x4608, 0x00000000); +OUT_CS_REG(0x4610, 0x00000000); +OUT_CS_REG(0x4614, 0x00000000); +OUT_CS_REG(0x4618, 0x00000000); +OUT_CS_REG(0x461C, 0x00000000); +OUT_CS_REG(0x48C0, 0x00000000); +OUT_CS_REG(0x46C0, 0x00000000); +OUT_CS_REG(0x49C0, 0x00000000); +OUT_CS_REG(0x47C0, 0x00000000); +OUT_CS_REG(0x4BC0, 0x00000002); +OUT_CS_REG(0x4BC8, 0x00000000); +OUT_CS_REG(0x4BCC, 0x00000000); +OUT_CS_REG(0x4BD0, 0x00000000); +OUT_CS_REG(0x4BD4, 0x00000000); +OUT_CS_REG(0x4BD8, 0x00000000); +OUT_CS_REG(0x4BD8, 0x00000000); +OUT_CS_REG(0x4E00, 0x00000000); +OUT_CS_REG(0x4E04, 0x20210000); +OUT_CS_REG(0x4E08, 0x20210000); +OUT_CS_REG(0x4E0C, 0x0000000F); +OUT_CS_REG(0x4E10, 0x00000000); +OUT_CS_REG(0x4E18, 0x00000000); +OUT_CS_REG(0x4E28, 0x00000000); +OUT_CS_REG(0x4E38, 0x00C00100); +OUT_CS_REG(0x4E50, 0x00000000); +OUT_CS_REG(0x4E54, 0x00000000); +OUT_CS_REG(0x4E58, 0x00000000); +OUT_CS_REG(0x4E5C, 0x00000000); +OUT_CS_REG(0x4E60, 0x00000000); +OUT_CS_REG(0x4E64, 0x00000000); +OUT_CS_REG(0x4E68, 0x00000000); +OUT_CS_REG(0x4E6C, 0x00000000); +OUT_CS_REG(0x4E70, 0x00000000); +OUT_CS_REG(0x4E88, 0x00000000); +OUT_CS_REG(0x4EA0, 0x00000000); +OUT_CS_REG(0x4EA4, 0xFFFFFFFF); +OUT_CS_REG(0x4F00, 0x00000010); +OUT_CS_REG(0x4F04, 0x00038038); +OUT_CS_REG(0x4F08, 0x00FFFF00); +OUT_CS_REG(0x4F10, 0x00000002); +OUT_CS_REG(0x4F14, 0x00000001); +OUT_CS_REG(0x4F18, 0x00000003); +OUT_CS_REG(0x4F1C, 0x00000000); +OUT_CS_REG(0x4F20, 0x00000000); +OUT_CS_REG(0x4F24, 0x00000100); +OUT_CS_REG(0x4F28, 0x00000000); +OUT_CS_REG(0x4F30, 0x00000000); +OUT_CS_REG(0x4F34, 0x00000000); +OUT_CS_REG(0x4F44, 0x00000000); +OUT_CS_REG(0x4F54, 0x00000000); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000406); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x3F800000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000400); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000401); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000402); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000403); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000404); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000405); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2150, 0x21030003); +OUT_CS_REG(0x4BC0, 0x00000000); +OUT_CS_REG(0x21E0, 0xF688F688); +OUT_CS_REG(0x2180, 0x00000001); +OUT_CS_REG(0x2184, 0x00000405); +OUT_CS_REG(0x20B0, 0x0000043F); +OUT_CS_REG(0x20B4, 0x00000008); +OUT_CS_REG(0x21DC, 0xAAAAAAAA); +OUT_CS_REG(0x2090, 0x00000003); +OUT_CS_REG(0x2094, 0x00000000); +OUT_CS_REG(0x4104, 0x00000000); +OUT_CS_REG(0x1D98, 0x3F800000); +OUT_CS_REG(0x1D9C, 0x00000000); +OUT_CS_REG(0x1DA0, 0x3F800000); +OUT_CS_REG(0x1DA4, 0x00000000); +OUT_CS_REG(0x1DA8, 0x3F800000); +OUT_CS_REG(0x1DAC, 0x00000000); +OUT_CS_REG(0x4BD4, 0x00000000); +OUT_CS_REG(0x4E04, 0x00000000); +OUT_CS_REG(0x4E08, 0x00000000); +OUT_CS_REG(0x221C, 0x0001C000); +OUT_CS_REG(0x421C, 0x06000600); +OUT_CS_REG(0x4310, 0x00D10000); +OUT_CS_REG(0x4314, 0x00D10000); +OUT_CS_REG(0x4318, 0x00D10000); +OUT_CS_REG(0x431C, 0x00D10000); +OUT_CS_REG(0x4320, 0x00D10000); +OUT_CS_REG(0x4324, 0x00D10000); +OUT_CS_REG(0x4328, 0x00D10000); +OUT_CS_REG(0x432C, 0x00D10000); +OUT_CS_REG(0x4300, 0x00040080); +OUT_CS_REG(0x4304, 0x00000000); +OUT_CS_REG(0x4330, 0x00004000); +OUT_CS_REG(0x4600, 0x00000000); +OUT_CS_REG(0x4604, 0x00000000); +OUT_CS_REG(0x4608, 0x00000000); +OUT_CS_REG(0x4610, 0x00000000); +OUT_CS_REG(0x4614, 0x00000000); +OUT_CS_REG(0x4618, 0x00000000); +OUT_CS_REG(0x461C, 0x00400000); +OUT_CS_REG(0x48C0, 0x00050A80); +OUT_CS_REG(0x46C0, 0x1C000000); +OUT_CS_REG(0x49C0, 0x00040889); +OUT_CS_REG(0x47C0, 0x01000000); +OUT_CS_REG(0x2284, 0x00000000); +OUT_CS_REG(0x2080, 0x0030045A); +OUT_CS_REG(0x22D0, 0x00100000); +OUT_CS_REG(0x22D4, 0x00000000); +OUT_CS_REG(0x22D8, 0x00000001); +OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(0x1720, 0x10008000); +OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(0x2284, 0x00000001); +OUT_CS_REG(0x2200, 0x00000000); +OUT_CS_REG(0x2208, 0x00F00203); +OUT_CS_REG(0x2208, 0x00D10001); +OUT_CS_REG(0x2208, 0x01248001); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x2208, 0x00F02203); +OUT_CS_REG(0x2208, 0x00D10021); +OUT_CS_REG(0x2208, 0x01248021); +OUT_CS_REG(0x2208, 0x00000000); +OUT_CS_REG(0x1720, 0x00068000); +OUT_CS_REG(0x4E28, 0x00000000); +OUT_CS_REG(0x4E38, 0x00C00100); +OUT_CS_REG(0x4E0C, 0x0000000F); +OUT_CS_REG(0x4F00, 0x00000000); +OUT_CS_REG(0x4F04, 0x00000000); +OUT_CS_REG(0x4F08, 0x00FF0000); +OUT_CS_REG(0x4E4C, 0x0000000A); +OUT_CS_REG(0x4F18, 0x00000003); +OUT_CS_REG(0x1720, 0x00068000); + +END_CS; +FLUSH_CS; r300->dirty_state = R300_NEW_KITCHEN_SINK; } diff --git a/src/gallium/winsys/drm/amd/amd_context.c b/src/gallium/winsys/drm/amd/amd_context.c index df8eb850c8..9b3c9c2ab2 100644 --- a/src/gallium/winsys/drm/amd/amd_context.c +++ b/src/gallium/winsys/drm/amd/amd_context.c @@ -242,7 +242,7 @@ GLboolean amd_context_create(const __GLcontextModes *visual, return GL_FALSE; } - if (GL_TRUE) { + if (1) { fprintf(stderr, "Creating r300 context...\n"); pipe = r300_create_context(NULL, -- cgit v1.2.3 From 29a4f5493529042d1068a7d35da1e7f542474503 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sun, 25 Jan 2009 21:35:26 -0800 Subject: r300: Working trivial/clear for RV410. This might work for other people too. --- src/gallium/drivers/r300/r300_cs.h | 8 +- src/gallium/drivers/r300/r300_cs_inlines.h | 35 +++ src/gallium/drivers/r300/r300_surface.c | 404 +++-------------------------- 3 files changed, 80 insertions(+), 367 deletions(-) create mode 100644 src/gallium/drivers/r300/r300_cs_inlines.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index edcfb9628f..d515c2f025 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -81,7 +81,7 @@ static uint32_t pack_float_32(float f) } while (0) #define OUT_CS_REG(register, value) do { \ - debug_printf("writing 0x%x to register 0x%x\n", value, register); \ + debug_printf("r300: writing 0x%x to register 0x%x\n", value, register); \ OUT_CS(CP_PACKET0(register, 0)); \ OUT_CS(value); \ } while (0) @@ -89,11 +89,13 @@ static uint32_t pack_float_32(float f) /* Note: This expects count to be the number of registers, * not the actual packet0 count! */ #define OUT_CS_REG_SEQ(register, count) do { \ - debug_printf("writing register sequence 0x%x\n", register); \ + debug_printf("r300: writing register sequence 0x%x\n", register); \ OUT_CS(CP_PACKET0(register, ((count) - 1))); \ } while (0) #define OUT_CS_RELOC(bo, offset, rd, wd, flags) do { \ + debug_printf("r300: writing relocation for buffer %p, offset %d\n", \ + bo, offset); \ OUT_CS(offset); \ cs_winsys->write_cs_reloc(cs, bo, rd, wd, flags); \ } while (0) @@ -110,4 +112,6 @@ static uint32_t pack_float_32(float f) cs_winsys->flush_cs(cs); \ } while (0) +#include "r300_cs_inlines.h" + #endif /* R300_CS_H */ diff --git a/src/gallium/drivers/r300/r300_cs_inlines.h b/src/gallium/drivers/r300/r300_cs_inlines.h new file mode 100644 index 0000000000..aa0e647008 --- /dev/null +++ b/src/gallium/drivers/r300/r300_cs_inlines.h @@ -0,0 +1,35 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +/* r300_cs_inlines: This is just a handful of useful inlines for sending + * (very) common instructions to the CS buffer. Should only be included from + * r300_cs.h, probably. */ + +#ifdef R300_CS_H + +#define R300_PACIFY do { \ + OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | \ + (1 << 18) | (1 << 31)); \ +} while (0) + + +#endif /* R300_CS_H */ diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 8afa06dec8..226cc7fc6c 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -32,356 +32,18 @@ static void r300_surface_fill(struct pipe_context* pipe, { struct r300_context* r300 = r300_context(pipe); CS_LOCALS(r300); -#if 0 - struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps; - boolean has_tcl = caps->has_tcl; - boolean is_r500 = caps->is_r500; - /* For the for loops. */ - int i; - /* Emit a shitload of state, and then draw a point to clear the buffer. - * XXX it goes without saying that this needs to be cleaned up and - * shifted around to work with the rest of the driver's state handling. - */ - BEGIN_CS(450); - /* XXX */ - OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); - OUT_CS_REG(R300_TX_INVALTAGS, 0x0); - OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); - OUT_CS_REG(R300_TX_INVALTAGS, 0x0); + float r, g, b, a; + r = (float)((color >> 16) & 0xff) / 255.0f; + g = (float)((color >> 8) & 0xff) / 255.0f; + b = (float)((color >> 0) & 0xff) / 255.0f; + debug_printf("r300: Filling surface %p at (%d,%d)," + " dimensions %dx%d, color 0x%x\n", + dest, x, y, w, h, color); - /* Sequence starting at R300_VAP_PROG_STREAM_CNTL_0 */ - OUT_CS_REG_SEQ(R300_VAP_PROG_STREAM_CNTL_0, 1); - if (has_tcl) { - OUT_CS(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << - R300_DATA_TYPE_0_SHIFT) | ((R300_LAST_VEC | (1 << - R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << - R300_DATA_TYPE_1_SHIFT))); - } else { - OUT_CS(((((0 << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << - R300_DATA_TYPE_0_SHIFT) | ((R300_LAST_VEC | (2 << - R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_4) << - R300_DATA_TYPE_1_SHIFT))); - } - - /* Disable fog */ - OUT_CS_REG(R300_FG_FOG_BLEND, 0); - OUT_CS_REG(R300_FG_ALPHA_FUNC, 0); - - OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, - ((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | - (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | - (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | - R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << - R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE0_SHIFT) | - (((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) | - (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) | - (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_SHIFT) | - (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_SHIFT) | - ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | - R300_WRITE_ENA_Z | R300_WRITE_ENA_W) << - R300_WRITE_ENA_SHIFT)) << R300_SWIZZLE1_SHIFT))); - /* R300_VAP_INPUT_CNTL_0, R300_VAP_INPUT_CNTL_1 */ - OUT_CS_REG_SEQ(R300_VAP_VTX_STATE_CNTL, 2); - OUT_CS((R300_SEL_USER_COLOR_0 << R300_COLOR_0_ASSEMBLY_SHIFT)); - OUT_CS(R300_INPUT_CNTL_POS | R300_INPUT_CNTL_COLOR | R300_INPUT_CNTL_TC0); - - /* comes from fglrx startup of clear */ - OUT_CS_REG_SEQ(R300_SE_VTE_CNTL, 2); - OUT_CS(R300_VTX_W0_FMT | R300_VPORT_X_SCALE_ENA | - R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | - R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | - R300_VPORT_Z_OFFSET_ENA); - OUT_CS(0x8); - - /* XXX */ - OUT_CS_REG_SEQ(R300_VAP_VF_MAX_VTX_INDX, 2); - OUT_CS(0xFFFFFF); - OUT_CS(0x0); - - OUT_CS_REG(R300_VAP_CNTL_STATUS, 0x0); - - OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4); - OUT_CS(0x3f800000); - OUT_CS(0x3f800000); - OUT_CS(0x3f800000); - OUT_CS(0x3f800000); - - OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); - - OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff); - - OUT_CS_REG_SEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2); - OUT_CS(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT | - R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT); - OUT_CS(0); /* no textures */ - - OUT_CS_REG(R300_TX_ENABLE, 0); - - OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6); - OUT_CS_32F(1.0); - OUT_CS_32F(x); - OUT_CS_32F(1.0); - OUT_CS_32F(y); - OUT_CS_32F(1.0); - OUT_CS_32F(0.0); - - OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2); - OUT_CS(0x0); - OUT_CS(0x0); - - OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_PS_UCP_MODE_CLIP_AS_TRIFAN | R300_CLIP_DISABLE); - - OUT_CS_REG(R300_GA_POINT_SIZE, ((w * 6) << R300_POINTSIZE_X_SHIFT) | - ((h * 6) << R300_POINTSIZE_Y_SHIFT)); - - if (is_r500) { - OUT_CS_REG_SEQ(R500_RS_IP_0, 8); - for (i = 0; i < 8; ++i) { - OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | - (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | - (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); - } - - OUT_CS_REG_SEQ(R300_RS_COUNT, 2); - /* XXX could hires be disabled for a speed boost? */ - OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); - OUT_CS(0x0); - - OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); - } else { - OUT_CS_REG_SEQ(R300_RS_IP_0, 8); - for (i = 0; i < 8; ++i) { - OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); - } - - OUT_CS_REG_SEQ(R300_RS_COUNT, 2); - /* XXX could hires be disabled for a speed boost? */ - OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); - OUT_CS(0x0); - - OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE); - } - - if (is_r500) { - OUT_CS_REG_SEQ(R500_US_CONFIG, 2); - OUT_CS(R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); - OUT_CS(0x0); - OUT_CS_REG_SEQ(R500_US_CODE_ADDR, 3); - OUT_CS(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); - OUT_CS(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); - OUT_CS(R500_US_CODE_OFFSET_ADDR(0)); - - OUT_CS_REG(R500_GA_US_VECTOR_INDEX, 0x0); - - OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_INST_TYPE_OUT | - R500_INST_TEX_SEM_WAIT | - R500_INST_LAST | - R500_INST_RGB_OMASK_R | - R500_INST_RGB_OMASK_G | - R500_INST_RGB_OMASK_B | - R500_INST_ALPHA_OMASK | - R500_INST_RGB_CLAMP | - R500_INST_ALPHA_CLAMP); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_RGB_ADDR0(0) | - R500_RGB_ADDR1(0) | - R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | - R500_RGB_ADDR2_CONST); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_ADDR0(0) | - R500_ALPHA_ADDR1(0) | - R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | - R500_ALPHA_ADDR2_CONST); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | - R500_ALU_RGB_G_SWIZ_A_G | - R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_R | - R500_ALU_RGB_B_SWIZ_B_G | - R500_ALU_RGB_G_SWIZ_B_B); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALPHA_OP_CMP | - R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_A); - OUT_CS_REG(R500_GA_US_VECTOR_DATA, R500_ALU_RGBA_OP_CMP | - R500_ALU_RGBA_R_SWIZ_0 | - R500_ALU_RGBA_G_SWIZ_0 | - R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0); - - } else { - OUT_CS_REG_SEQ(R300_US_CONFIG, 3); - OUT_CS(0x0); - OUT_CS(0x0); - OUT_CS(0x0); - OUT_CS_REG_SEQ(R300_US_CODE_ADDR_0, 4); - OUT_CS(0x0); - OUT_CS(0x0); - OUT_CS(0x0); - OUT_CS(R300_RGBA_OUT); - - OUT_CS_REG(R300_US_ALU_RGB_INST_0, - FP_INSTRC(MAD, FP_ARGC(SRC0C_XYZ), FP_ARGC(ONE), FP_ARGC(ZERO))); - OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, - FP_SELC(0, NO, XYZ, FP_TMP(0), 0, 0)); - OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, - FP_INSTRA(MAD, FP_ARGA(SRC0A), FP_ARGA(ONE), FP_ARGA(ZERO))); - OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, - FP_SELA(0, NO, W, FP_TMP(0), 0, 0)); - } - - /* XXX */ - uint32_t vap_cntl; - OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); - if (has_tcl) { - vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (12 << R300_VF_MAX_VTX_NUM_SHIFT)); - if (CHIP_FAMILY_RV515) - vap_cntl |= R500_TCL_STATE_OPTIMIZATION; - } else { - vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | - (5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (5 << R300_VF_MAX_VTX_NUM_SHIFT)); - } - - vap_cntl |= (caps->num_vert_pipes << - R300_PVS_NUM_FPUS_SHIFT); - - OUT_CS_REG(R300_VAP_CNTL, vap_cntl); - - /* XXX unbreak this - if (has_tcl) { - OUT_CS_REG_SEQ(R300_VAP_PVS_CODE_CNTL_0, 3); - OUT_CS((0 << R300_PVS_FIRST_INST_SHIFT) | - (0 << R300_PVS_XYZW_VALID_INST_SHIFT) | - (1 << R300_PVS_LAST_INST_SHIFT)); - OUT_CS((0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | - (0 << R300_PVS_MAX_CONST_ADDR_SHIFT)); - OUT_CS(1 << R300_PVS_LAST_VTX_SRC_INST_SHIFT); - - OUT_CS_REG(R300_SC_SCREENDOOR, 0x0); - OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 28)); - OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); - OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); - OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_CODE_START); - - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, - 0, 0xf, PVS_DST_REG_OUT)); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(0, PVS_SRC_SELECT_X, PVS_SRC_SELECT_Y, - PVS_SRC_SELECT_Z, PVS_SRC_SELECT_W, - PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(0, PVS_SRC_SELECT_FORCE_0, - PVS_SRC_SELECT_FORCE_0, - PVS_SRC_SELECT_FORCE_0, - PVS_SRC_SELECT_FORCE_0, - PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); - - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_OP_DST_OPERAND(VE_ADD, GL_FALSE, GL_FALSE, 1, 0xf, - PVS_DST_REG_OUT)); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(1, PVS_SRC_SELECT_X, - PVS_SRC_SELECT_Y, PVS_SRC_SELECT_Z, - PVS_SRC_SELECT_W, PVS_SRC_REG_INPUT, - VSF_FLAG_NONE)); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, PVS_SRC_OPERAND(1, PVS_SRC_SELECT_FORCE_0, - PVS_SRC_SELECT_FORCE_0, - PVS_SRC_SELECT_FORCE_0, - PVS_SRC_SELECT_FORCE_0, - PVS_SRC_REG_INPUT, VSF_FLAG_NONE)); - OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); - } */ - - /* TODO in bufmgr */ - /* XXX this should be split off, also figure out WTF with the numbers */ - OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); - /* XXX might have to switch to 2D */ - - OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); - OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - /* XXX this needs more TLC (or TCL, as it were) */ - OUT_CS_REG(R300_RB3D_COLORPITCH0, R300_COLOR_FORMAT_ARGB8888); - if (flags & (CLEARBUFFER_DEPTH | CLEARBUFFER_STENCIL)) { - assert(rrbd != 0); - cbpitch = (rrbd->pitch / rrbd->cpp); - if (rrbd->bo->flags & RADEON_BO_FLAGS_MACRO_TILE){ - cbpitch |= R300_DEPTHMACROTILE_ENABLE; - } - if (rrbd->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){ - cbpitch |= R300_DEPTHMICROTILE_TILED; - } - BEGIN_BATCH_NO_AUTOSTATE(4); - OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1); - OUT_BATCH_RELOC(0, rrbd->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGVAL(R300_ZB_DEPTHPITCH, cbpitch); - END_BATCH(); - } - - { - uint32_t t1, t2; - - t1 = 0x0; - t2 = 0x0; - - if (flags & CLEARBUFFER_DEPTH) { - t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE; - t2 |= - (R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT); - } - - if (flags & CLEARBUFFER_STENCIL) { - t1 |= R300_STENCIL_ENABLE; - t2 |= - (R300_ZS_ALWAYS << - R300_S_FRONT_FUNC_SHIFT) | - (R300_ZS_REPLACE << - R300_S_FRONT_SFAIL_OP_SHIFT) | - (R300_ZS_REPLACE << - R300_S_FRONT_ZPASS_OP_SHIFT) | - (R300_ZS_REPLACE << - R300_S_FRONT_ZFAIL_OP_SHIFT); - } - - OUT_BATCH_REGSEQ(R300_ZB_CNTL, 3); - OUT_BATCH(t1); - OUT_BATCH(t2); - OUT_BATCH(((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) << - R300_STENCILWRITEMASK_SHIFT) | - (ctx->Stencil.Clear & R300_STENCILREF_MASK)); - END_BATCH(); - } - - OUT_CS_REG_SEQ(R300_ZB_CNTL, 3); - OUT_CS(0x0); - OUT_CS(0x0); - OUT_CS(0x0); - - OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); - OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | - (1 << R300_PRIM_NUM_VERTICES_SHIFT)); - OUT_CS_32F(w / 2.0); - OUT_CS_32F(h / 2.0); - /* XXX this should be the depth value to clear to */ - OUT_CS_32F(1.0); - OUT_CS_32F(1.0); - OUT_CS_32F(color); - OUT_CS_32F(color); - OUT_CS_32F(color); - OUT_CS_32F(color); - - /* XXX this should be split off, also figure out WTF with the numbers */ - OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | (1 << 18)); - - END_CS; - FLUSH_CS; -#endif BEGIN_CS(276); -OUT_CS_REG(0x1720, 0x00068000); +R300_PACIFY; OUT_CS_REG(0x4100, 0x00000000); -OUT_CS_REG(0x1720, 0x00068000); +R300_PACIFY; OUT_CS_REG(0x1D98, 0x43000000); OUT_CS_REG(0x1D9C, 0x43002000); OUT_CS_REG(0x1DA0, 0xC3000000); @@ -423,7 +85,6 @@ OUT_CS_REG(0x4204, 0x00000000); OUT_CS_REG(0x4208, 0x3F800000); OUT_CS_REG(0x420C, 0x3F800000); OUT_CS_REG(0x4214, 0x00050005); -OUT_CS_REG(0x421C, 0x00060006); OUT_CS_REG(0x4230, 0x18000006); OUT_CS_REG(0x4234, 0x00020006); OUT_CS_REG(0x4238, 0x3BAAAAAB); @@ -492,8 +153,6 @@ OUT_CS_REG(0x4E08, 0x20210000); OUT_CS_REG(0x4E0C, 0x0000000F); OUT_CS_REG(0x4E10, 0x00000000); OUT_CS_REG(0x4E18, 0x00000000); -OUT_CS_REG(0x4E28, 0x00000000); -OUT_CS_REG(0x4E38, 0x00C00100); OUT_CS_REG(0x4E50, 0x00000000); OUT_CS_REG(0x4E54, 0x00000000); OUT_CS_REG(0x4E58, 0x00000000); @@ -513,15 +172,13 @@ OUT_CS_REG(0x4F10, 0x00000002); OUT_CS_REG(0x4F14, 0x00000001); OUT_CS_REG(0x4F18, 0x00000003); OUT_CS_REG(0x4F1C, 0x00000000); -OUT_CS_REG(0x4F20, 0x00000000); -OUT_CS_REG(0x4F24, 0x00000100); OUT_CS_REG(0x4F28, 0x00000000); OUT_CS_REG(0x4F30, 0x00000000); OUT_CS_REG(0x4F34, 0x00000000); OUT_CS_REG(0x4F44, 0x00000000); OUT_CS_REG(0x4F54, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000406); @@ -530,7 +187,7 @@ OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x3F800000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000400); @@ -539,7 +196,7 @@ OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000401); @@ -548,7 +205,7 @@ OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000402); @@ -557,7 +214,7 @@ OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000403); @@ -566,7 +223,7 @@ OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000404); @@ -575,7 +232,7 @@ OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000405); @@ -604,7 +261,8 @@ OUT_CS_REG(0x4BD4, 0x00000000); OUT_CS_REG(0x4E04, 0x00000000); OUT_CS_REG(0x4E08, 0x00000000); OUT_CS_REG(0x221C, 0x0001C000); -OUT_CS_REG(0x421C, 0x06000600); +OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | + ((w * 6) << R300_POINTSIZE_X_SHIFT)); OUT_CS_REG(0x4310, 0x00D10000); OUT_CS_REG(0x4314, 0x00D10000); OUT_CS_REG(0x4318, 0x00D10000); @@ -633,7 +291,7 @@ OUT_CS_REG(0x22D0, 0x00100000); OUT_CS_REG(0x22D4, 0x00000000); OUT_CS_REG(0x22D8, 0x00000001); OUT_CS_REG(0x43E8, 0x00000000); -OUT_CS_REG(0x1720, 0x10008000); +R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); OUT_CS_REG(0x2284, 0x00000001); OUT_CS_REG(0x2200, 0x00000000); @@ -645,16 +303,32 @@ OUT_CS_REG(0x2208, 0x00F02203); OUT_CS_REG(0x2208, 0x00D10021); OUT_CS_REG(0x2208, 0x01248021); OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x1720, 0x00068000); -OUT_CS_REG(0x4E28, 0x00000000); -OUT_CS_REG(0x4E38, 0x00C00100); +R300_PACIFY; +OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); +OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); +//OUT_CS_REG(0x4E38, 0x00C00100); OUT_CS_REG(0x4E0C, 0x0000000F); OUT_CS_REG(0x4F00, 0x00000000); OUT_CS_REG(0x4F04, 0x00000000); OUT_CS_REG(0x4F08, 0x00FF0000); + +/* XXX Packet3 */ +OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); +OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | +(1 << R300_PRIM_NUM_VERTICES_SHIFT)); +OUT_CS_32F(w / 2.0); +OUT_CS_32F(h / 2.0); +/* XXX this should be the depth value to clear to */ +OUT_CS_32F(1.0); +OUT_CS_32F(1.0); +OUT_CS_32F(r); +OUT_CS_32F(g); +OUT_CS_32F(b); +OUT_CS_32F(1.0); + OUT_CS_REG(0x4E4C, 0x0000000A); OUT_CS_REG(0x4F18, 0x00000003); -OUT_CS_REG(0x1720, 0x00068000); +R300_PACIFY; END_CS; FLUSH_CS; -- cgit v1.2.3 From 3e3122467f1e9f6dde77762d1a35a56f89fb25ce Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 26 Jan 2009 02:18:56 -0800 Subject: r300: Deobfuscate a few registers, fix inaccurate variable names. It's not "pipes", it's floating-point vertex processors. Completely different. --- src/gallium/drivers/r300/r300_chipset.c | 26 +++++++++++++------------- src/gallium/drivers/r300/r300_chipset.h | 9 +++++---- src/gallium/drivers/r300/r300_surface.c | 10 +++++++--- 3 files changed, 25 insertions(+), 20 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index 494c9e54c0..4c84be26ef 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -31,7 +31,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) /* Reasonable defaults */ caps->has_tcl = TRUE; caps->is_r500 = FALSE; - caps->num_vert_pipes = 4; + caps->num_vert_fpus = 4; /* Note: These are not ordered by PCI ID. I leave that task to GCC, @@ -112,7 +112,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x4A50: case 0x4A54: caps->family = CHIP_FAMILY_R420; - caps->num_vert_pipes = 6; + caps->num_vert_fpus = 6; break; case 0x5548: @@ -125,7 +125,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x5554: case 0x5D57: caps->family = CHIP_FAMILY_R423; - caps->num_vert_pipes = 6; + caps->num_vert_fpus = 6; break; case 0x554C: @@ -136,7 +136,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x5D49: case 0x5D4A: caps->family = CHIP_FAMILY_R430; - caps->num_vert_pipes = 6; + caps->num_vert_fpus = 6; break; case 0x5D4C: @@ -146,7 +146,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x5D50: case 0x5D52: caps->family = CHIP_FAMILY_R480; - caps->num_vert_pipes = 6; + caps->num_vert_fpus = 6; break; case 0x4B49: @@ -154,7 +154,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x4B4B: case 0x4B4C: caps->family = CHIP_FAMILY_R481; - caps->num_vert_pipes = 6; + caps->num_vert_fpus = 6; break; case 0x5E4C: @@ -170,7 +170,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x5E4B: case 0x5E4D: caps->family = CHIP_FAMILY_RV410; - caps->num_vert_pipes = 6; + caps->num_vert_fpus = 6; break; case 0x5954: @@ -226,7 +226,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x710E: case 0x710F: caps->family = CHIP_FAMILY_R520; - caps->num_vert_pipes = 8; + caps->num_vert_fpus = 8; caps->is_r500 = TRUE; break; @@ -269,7 +269,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x7210: case 0x7211: caps->family = CHIP_FAMILY_RV515; - caps->num_vert_pipes = 2; + caps->num_vert_fpus = 2; caps->is_r500 = TRUE; break; @@ -290,7 +290,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x71DA: case 0x71DE: caps->family = CHIP_FAMILY_RV530; - caps->num_vert_pipes = 5; + caps->num_vert_fpus = 5; caps->is_r500 = TRUE; break; @@ -310,13 +310,13 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x724F: case 0x7284: caps->family = CHIP_FAMILY_R580; - caps->num_vert_pipes = 8; + caps->num_vert_fpus = 8; caps->is_r500 = TRUE; break; case 0x7280: caps->family = CHIP_FAMILY_RV570; - caps->num_vert_pipes = 5; + caps->num_vert_fpus = 5; caps->is_r500 = TRUE; break; @@ -332,7 +332,7 @@ void r300_parse_chipset(struct r300_capabilities* caps) case 0x7293: case 0x7297: caps->family = CHIP_FAMILY_RV560; - caps->num_vert_pipes = 5; + caps->num_vert_fpus = 5; caps->is_r500 = TRUE; break; diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h index c4104a65cb..a9cd372ec5 100644 --- a/src/gallium/drivers/r300/r300_chipset.h +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -32,14 +32,15 @@ struct r300_capabilities { uint32_t pci_id; /* Chipset family */ int family; - /* The number of vertex pipes */ - int num_vert_pipes; + /* The number of vertex floating-point units */ + int num_vert_fpus; /* The number of fragment pipes */ int num_frag_pipes; /* Whether or not TCL is physically present */ boolean has_tcl; - /* Whether or not this is an RV515 or newer; R500s have many features: - * - Extra bit on texture sizes + /* Whether or not this is an RV515 or newer; R500s have many differences + * that require extra consideration, compared to their R3xx cousins: + * - Extra bit of width and height on texture sizes * - Blend color is split across two registers * - Universal Shader (US) block used for fragment shaders */ boolean is_r500; diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 226cc7fc6c..9a4b3455d1 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -32,6 +32,7 @@ static void r300_surface_fill(struct pipe_context* pipe, { struct r300_context* r300 = r300_context(pipe); CS_LOCALS(r300); + struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps; float r, g, b, a; r = (float)((color >> 16) & 0xff) / 255.0f; g = (float)((color >> 8) & 0xff) / 255.0f; @@ -51,7 +52,6 @@ OUT_CS_REG(0x1DA4, 0x43002000); OUT_CS_REG(0x1DA8, 0x3F000000); OUT_CS_REG(0x1DAC, 0x3F000000); OUT_CS_REG(0x2284, 0x00000000); -OUT_CS_REG(0x2080, 0x0030046A); OUT_CS_REG(0x20B0, 0x0000043F); OUT_CS_REG(0x20B4, 0x00000008); OUT_CS_REG(0x2134, 0x00FFFFFF); @@ -76,7 +76,8 @@ OUT_CS_REG(0x22D8, 0x00000000); OUT_CS_REG(0x4008, 0x00000007); OUT_CS_REG(0x4010, 0x66666666); OUT_CS_REG(0x4014, 0x06666666); -OUT_CS_REG(0x4018, 0x00000011); +/* XXX why doesn't classic Mesa write the number of pipes, too? */ +OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16); OUT_CS_REG(0x401C, 0x00000004); OUT_CS_REG(0x4020, 0x00000000); OUT_CS_REG(0x4104, 0x00000000); @@ -286,7 +287,10 @@ OUT_CS_REG(0x46C0, 0x1C000000); OUT_CS_REG(0x49C0, 0x00040889); OUT_CS_REG(0x47C0, 0x01000000); OUT_CS_REG(0x2284, 0x00000000); -OUT_CS_REG(0x2080, 0x0030045A); +/* XXX these magic numbers should be explained when + * this becomes a cached state object */ +OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT)); OUT_CS_REG(0x22D0, 0x00100000); OUT_CS_REG(0x22D4, 0x00000000); OUT_CS_REG(0x22D8, 0x00000001); -- cgit v1.2.3 From 2c2f819a1de0fc29866fdf90cce4550b0d2a0bad Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 26 Jan 2009 10:26:41 -0800 Subject: r300: Add r300_flush. Haha, I always do this. --- src/gallium/drivers/r300/r300_flush.c | 42 +++++++++++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_flush.h | 33 +++++++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 src/gallium/drivers/r300/r300_flush.c create mode 100644 src/gallium/drivers/r300/r300_flush.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c new file mode 100644 index 0000000000..3766f0a0a7 --- /dev/null +++ b/src/gallium/drivers/r300/r300_flush.c @@ -0,0 +1,42 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "r300_flush.h" + +static void r300_flush(struct pipe_context* pipe, + unsigned flags, + struct pipe_fence_handle** fence) +{ + struct r300_context* r300 = r300_context(pipe); + CS_LOCALS(r300); + + if (r300->dirty_hw) { + FLUSH_CS; + r300->dirty_state = R300_NEW_KITCHEN_SINK; + r300->dirty_hw = 0; + } +} + +void r300_init_flush_functions(struct r300_context* r300) +{ + r300->context.flush = r300_flush; +} diff --git a/src/gallium/drivers/r300/r300_flush.h b/src/gallium/drivers/r300/r300_flush.h new file mode 100644 index 0000000000..a1b224b39c --- /dev/null +++ b/src/gallium/drivers/r300/r300_flush.h @@ -0,0 +1,33 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_FLUSH_H +#define R300_FLUSH_H + +#include "pipe/p_context.h" + +#include "r300_context.h" +#include "r300_cs.h" + +void r300_init_flush_functions(struct r300_context* r300); + +#endif /* R300_FLUSH_H */ -- cgit v1.2.3 From f1ba451bcc7764fd2b92fc8408f6b52c1d670b1f Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 27 Jan 2009 03:40:46 -0800 Subject: r300: Set up blend state emit, clean up blend registers. Also add at least one missing register to r300_reg. --- src/gallium/drivers/r300/r300_emit.c | 18 +++++++++----- src/gallium/drivers/r300/r300_reg.h | 2 ++ src/gallium/drivers/r300/r300_surface.c | 42 +++++++++++++++++---------------- src/gallium/drivers/r300/r300_surface.h | 9 +++++-- 4 files changed, 43 insertions(+), 28 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 19bfcbdd5b..de606cfab7 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -26,6 +26,17 @@ #include "r300_cs.h" #include "r300_screen.h" +void r300_emit_blend_state(struct r300_context* r300, + struct r300_blend_state* blend) +{ + CS_LOCALS(r300); + OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2); + OUT_CS(blend->blend_control); + OUT_CS(blend->alpha_blend_control); + OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop); + OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither); +} + static void r300_emit_dirty_state(struct r300_context* r300) { struct r300_screen* r300screen = (struct r300_screen*)r300->context.screen; @@ -38,12 +49,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) /* XXX check size */ if (r300->dirty_state & R300_NEW_BLEND) { - struct r300_blend_state* blend = r300->blend_state; - /* XXX next two are contiguous regs */ - OUT_CS_REG(R300_RB3D_CBLEND, blend->blend_control); - OUT_CS_REG(R300_RB3D_ABLEND, blend->alpha_blend_control); - OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop); - OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither); + r300_emit_blend_state(r300, r300->blend_state); } if (r300->dirty_state & R300_NEW_BLEND_COLOR) { diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index 7f4a508b1b..c1796ad7a8 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -151,6 +151,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_VTX_W0_FMT (1 << 10) # define R300_SERIAL_PROC_ENA (1 << 11) +#define R300_VAP_VTX_SIZE 0x20b4 + /* BEGIN: Vertex data assembly - lots of uncertainties */ /* gap */ diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 9a4b3455d1..6c7784dd4d 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -43,24 +43,30 @@ static void r300_surface_fill(struct pipe_context* pipe, BEGIN_CS(276); R300_PACIFY; -OUT_CS_REG(0x4100, 0x00000000); +OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; +/* Viewport setup */ OUT_CS_REG(0x1D98, 0x43000000); OUT_CS_REG(0x1D9C, 0x43002000); OUT_CS_REG(0x1DA0, 0xC3000000); OUT_CS_REG(0x1DA4, 0x43002000); OUT_CS_REG(0x1DA8, 0x3F000000); OUT_CS_REG(0x1DAC, 0x3F000000); -OUT_CS_REG(0x2284, 0x00000000); -OUT_CS_REG(0x20B0, 0x0000043F); -OUT_CS_REG(0x20B4, 0x00000008); -OUT_CS_REG(0x2134, 0x00FFFFFF); -OUT_CS_REG(0x2138, 0x00000000); -OUT_CS_REG(0x2140, 0x00000000); -OUT_CS_REG(0x2150, 0x00000000); -OUT_CS_REG(0x21E0, 0x00000000); -OUT_CS_REG(0x2180, 0x00000000); -OUT_CS_REG(0x2184, 0x00000000); +/* Flush PVS. */ +OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); + +OUT_CS_REG(R300_SE_VTE_CNTL, R300_VPORT_X_SCALE_ENA | + R300_VPORT_X_OFFSET_ENA | R300_VPORT_Y_SCALE_ENA | + R300_VPORT_Y_OFFSET_ENA | R300_VPORT_Z_SCALE_ENA | + R300_VPORT_Z_OFFSET_ENA | R300_VTX_W0_FMT); +/* Vertex size. */ +OUT_CS_REG(R300_VAP_VTX_SIZE, 0x8); +/* Max and min vertex index clamp. */ +OUT_CS_REG(R300_VAP_VF_MAX_VTX_INDX, 0xFFFFFF); +OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0); +/* XXX endian */ +OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP); +OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0); OUT_CS_REG(0x21DC, 0xAAAAAAAA); OUT_CS_REG(0x221C, 0x00000000); OUT_CS_REG(0x2220, 0x3F800000); @@ -149,12 +155,8 @@ OUT_CS_REG(0x4BD4, 0x00000000); OUT_CS_REG(0x4BD8, 0x00000000); OUT_CS_REG(0x4BD8, 0x00000000); OUT_CS_REG(0x4E00, 0x00000000); -OUT_CS_REG(0x4E04, 0x20210000); -OUT_CS_REG(0x4E08, 0x20210000); OUT_CS_REG(0x4E0C, 0x0000000F); OUT_CS_REG(0x4E10, 0x00000000); -OUT_CS_REG(0x4E18, 0x00000000); -OUT_CS_REG(0x4E50, 0x00000000); OUT_CS_REG(0x4E54, 0x00000000); OUT_CS_REG(0x4E58, 0x00000000); OUT_CS_REG(0x4E5C, 0x00000000); @@ -243,9 +245,9 @@ OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2150, 0x21030003); OUT_CS_REG(0x4BC0, 0x00000000); -OUT_CS_REG(0x21E0, 0xF688F688); -OUT_CS_REG(0x2180, 0x00000001); -OUT_CS_REG(0x2184, 0x00000405); +OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688); +OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1); +OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405); OUT_CS_REG(0x20B0, 0x0000043F); OUT_CS_REG(0x20B4, 0x00000008); OUT_CS_REG(0x21DC, 0xAAAAAAAA); @@ -259,8 +261,8 @@ OUT_CS_REG(0x1DA4, 0x00000000); OUT_CS_REG(0x1DA8, 0x3F800000); OUT_CS_REG(0x1DAC, 0x00000000); OUT_CS_REG(0x4BD4, 0x00000000); -OUT_CS_REG(0x4E04, 0x00000000); -OUT_CS_REG(0x4E08, 0x00000000); +r300_emit_blend_state(r300, &blend_clear_state); +/* XXX emit blend state */ OUT_CS_REG(0x221C, 0x0001C000); OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | ((w * 6) << R300_POINTSIZE_X_SHIFT)); diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index 2d64a95412..6d71601b98 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -30,8 +30,13 @@ #include "r300_context.h" #include "r300_cs.h" +#include "r300_emit.h" -/* XXX integrate this into r300_reg */ -#include "r300_fragprog.h" +const struct r300_blend_state blend_clear_state = { + .blend_control = 0x0, + .alpha_blend_control = 0x0, + .rop = 0x0, + .dither = 0x0, +}; #endif /* R300_SURFACE_H */ -- cgit v1.2.3 From 2cb90c8e805d010ba4594264dd9edbbb7f95513a Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 27 Jan 2009 04:03:38 -0800 Subject: r300: Count BEGIN_CS, END_CS, warn if count is off. --- src/gallium/drivers/r300/r300_cs.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index d515c2f025..653e2fdafa 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -60,7 +60,8 @@ static uint32_t pack_float_32(float f) #define CS_LOCALS(context) \ struct r300_winsys* cs_winsys = context->winsys; \ - struct radeon_cs* cs = cs_winsys->cs + struct radeon_cs* cs = cs_winsys->cs; \ + int cs_count; #define CHECK_CS(size) \ cs_winsys->check_cs(cs, (size)) @@ -70,6 +71,7 @@ static uint32_t pack_float_32(float f) debug_printf("r300: BEGIN_CS in %s (%s:%d)\n", __FUNCTION__, __FILE__, \ __LINE__); \ cs_winsys->begin_cs(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ + int cs_count = size; \ } while (0) #define OUT_CS(value) do { \ @@ -103,6 +105,8 @@ static uint32_t pack_float_32(float f) #define END_CS do { \ debug_printf("r300: END_CS in %s (%s:%d)\n", __FUNCTION__, __FILE__, \ __LINE__); \ + if (cs_count != 0) \ + debug_printf("r300: Warning: cs_count off by %d\n", cs_count); \ cs_winsys->end_cs(cs, __FILE__, __FUNCTION__, __LINE__); \ } while (0) -- cgit v1.2.3 From bea0c5812bd2795b514725d2a3788add3dc209af Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 27 Jan 2009 04:04:57 -0800 Subject: r300: Add blend color state emit. Slow and steady wins the race. Or something like that. --- src/gallium/drivers/r300/r300_emit.c | 40 ++++++++++++++++++++------------- src/gallium/drivers/r300/r300_emit.h | 31 +++++++++++++++++++++++++ src/gallium/drivers/r300/r300_surface.c | 6 ++++- src/gallium/drivers/r300/r300_surface.h | 6 +++++ 4 files changed, 67 insertions(+), 16 deletions(-) create mode 100644 src/gallium/drivers/r300/r300_emit.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index de606cfab7..e091352c3b 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -22,24 +22,44 @@ /* r300_emit: Functions for emitting state. */ -#include "r300_context.h" -#include "r300_cs.h" -#include "r300_screen.h" +#include "r300_emit.h" void r300_emit_blend_state(struct r300_context* r300, struct r300_blend_state* blend) { CS_LOCALS(r300); + BEGIN_CS(7); OUT_CS_REG_SEQ(R300_RB3D_CBLEND, 2); OUT_CS(blend->blend_control); OUT_CS(blend->alpha_blend_control); OUT_CS_REG(R300_RB3D_ROPCNTL, blend->rop); OUT_CS_REG(R300_RB3D_DITHER_CTL, blend->dither); + END_CS; +} + +void r300_emit_blend_color_state(struct r300_context* r300, + struct r300_blend_color_state* bc) +{ + struct r300_screen* r300screen = + (struct r300_screen*)r300->context.screen; + CS_LOCALS(r300); + if (r300screen->caps->is_r500) { + BEGIN_CS(3); + OUT_CS_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); + OUT_CS(bc->blend_color_red_alpha); + OUT_CS(bc->blend_color_green_blue); + END_CS; + } else { + BEGIN_CS(2); + OUT_CS_REG(R300_RB3D_BLEND_COLOR, bc->blend_color); + END_CS; + } } static void r300_emit_dirty_state(struct r300_context* r300) { - struct r300_screen* r300screen = (struct r300_screen*)r300->context.screen; + struct r300_screen* r300screen = + (struct r300_screen*)r300->context.screen; CS_LOCALS(r300); if (!(r300->dirty_state) && !(r300->dirty_hw)) { @@ -53,17 +73,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) } if (r300->dirty_state & R300_NEW_BLEND_COLOR) { - struct r300_blend_color_state* blend_color = r300->blend_color_state; - if (r300screen->caps->is_r500) { - /* XXX next two are contiguous regs */ - OUT_CS_REG(R500_RB3D_CONSTANT_COLOR_AR, - blend_color->blend_color_red_alpha); - OUT_CS_REG(R500_RB3D_CONSTANT_COLOR_GB, - blend_color->blend_color_green_blue); - } else { - OUT_CS_REG(R300_RB3D_BLEND_COLOR, - blend_color->blend_color); - } + r300_emit_blend_color_state(r300, r300->blend_color_state); } if (r300->dirty_state & R300_NEW_DSA) { diff --git a/src/gallium/drivers/r300/r300_emit.h b/src/gallium/drivers/r300/r300_emit.h new file mode 100644 index 0000000000..5756b6acf4 --- /dev/null +++ b/src/gallium/drivers/r300/r300_emit.h @@ -0,0 +1,31 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "r300_context.h" +#include "r300_cs.h" +#include "r300_screen.h" + +void r300_emit_blend_state(struct r300_context* r300, + struct r300_blend_state* blend); + +void r300_emit_blend_color_state(struct r300_context* r300, + struct r300_blend_color_state* bc); diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 6c7784dd4d..2e5a572f47 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -156,6 +156,9 @@ OUT_CS_REG(0x4BD8, 0x00000000); OUT_CS_REG(0x4BD8, 0x00000000); OUT_CS_REG(0x4E00, 0x00000000); OUT_CS_REG(0x4E0C, 0x0000000F); + +r300_emit_blend_color_state(r300, &blend_color_clear_state); + OUT_CS_REG(0x4E10, 0x00000000); OUT_CS_REG(0x4E54, 0x00000000); OUT_CS_REG(0x4E58, 0x00000000); @@ -261,8 +264,9 @@ OUT_CS_REG(0x1DA4, 0x00000000); OUT_CS_REG(0x1DA8, 0x3F800000); OUT_CS_REG(0x1DAC, 0x00000000); OUT_CS_REG(0x4BD4, 0x00000000); + r300_emit_blend_state(r300, &blend_clear_state); -/* XXX emit blend state */ + OUT_CS_REG(0x221C, 0x0001C000); OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | ((w * 6) << R300_POINTSIZE_X_SHIFT)); diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index 6d71601b98..8ec7151f4d 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -39,4 +39,10 @@ const struct r300_blend_state blend_clear_state = { .dither = 0x0, }; +const struct r300_blend_color_state blend_color_clear_state = { + .blend_color = 0x0, + .blend_color_red_alpha = 0x0, + .blend_color_green_blue = 0x0, +}; + #endif /* R300_SURFACE_H */ -- cgit v1.2.3 From 2e635ef563e2bff50e7a2af4f505bbd066865723 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 27 Jan 2009 04:48:19 -0800 Subject: r300: Add dsa state emit. Seeing a pattern yet? --- src/gallium/drivers/r300/r300_emit.c | 31 ++++++++++++++++++++----------- src/gallium/drivers/r300/r300_emit.h | 3 +++ src/gallium/drivers/r300/r300_surface.c | 9 +++------ src/gallium/drivers/r300/r300_surface.h | 10 ++++++++++ 4 files changed, 36 insertions(+), 17 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index e091352c3b..d8de766c31 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -56,6 +56,25 @@ void r300_emit_blend_color_state(struct r300_context* r300, } } +void r300_emit_dsa_state(struct r300_context* r300, + struct r300_dsa_state* dsa) +{ + struct r300_screen* r300screen = + (struct r300_screen*)r300->context.screen; + CS_LOCALS(r300); + BEGIN_CS(r300screen->caps->is_r500 ? 12 : 10); + OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); + OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); + OUT_CS_REG_SEQ(R300_ZB_CNTL, 3); + OUT_CS(dsa->z_buffer_control); + OUT_CS(dsa->z_stencil_control); + OUT_CS(dsa->stencil_ref_mask); + OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top); + if (r300screen->caps->is_r500) { + OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); + } +} + static void r300_emit_dirty_state(struct r300_context* r300) { struct r300_screen* r300screen = @@ -77,17 +96,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) } if (r300->dirty_state & R300_NEW_DSA) { - struct r300_dsa_state* dsa = r300->dsa_state; - OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); - OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); - /* XXX next three are contiguous regs */ - OUT_CS_REG(R300_ZB_CNTL, dsa->z_buffer_control); - OUT_CS_REG(R300_ZB_ZSTENCILCNTL, dsa->z_stencil_control); - OUT_CS_REG(R300_ZB_STENCILREFMASK, dsa->stencil_ref_mask); - OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top); - if (r300screen->caps->is_r500) { - OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); - } + r300_emit_dsa_state(r300, r300->dsa_state); } if (r300->dirty_state & R300_NEW_RASTERIZER) { diff --git a/src/gallium/drivers/r300/r300_emit.h b/src/gallium/drivers/r300/r300_emit.h index 5756b6acf4..98287bc1f3 100644 --- a/src/gallium/drivers/r300/r300_emit.h +++ b/src/gallium/drivers/r300/r300_emit.h @@ -29,3 +29,6 @@ void r300_emit_blend_state(struct r300_context* r300, void r300_emit_blend_color_state(struct r300_context* r300, struct r300_blend_color_state* bc); + +void r300_emit_dsa_state(struct r300_context* r300, + struct r300_dsa_state* dsa); diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 2e5a572f47..aab1850144 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -151,7 +151,6 @@ OUT_CS_REG(0x4BC0, 0x00000002); OUT_CS_REG(0x4BC8, 0x00000000); OUT_CS_REG(0x4BCC, 0x00000000); OUT_CS_REG(0x4BD0, 0x00000000); -OUT_CS_REG(0x4BD4, 0x00000000); OUT_CS_REG(0x4BD8, 0x00000000); OUT_CS_REG(0x4BD8, 0x00000000); OUT_CS_REG(0x4E00, 0x00000000); @@ -175,7 +174,6 @@ OUT_CS_REG(0x4F00, 0x00000010); OUT_CS_REG(0x4F04, 0x00038038); OUT_CS_REG(0x4F08, 0x00FFFF00); OUT_CS_REG(0x4F10, 0x00000002); -OUT_CS_REG(0x4F14, 0x00000001); OUT_CS_REG(0x4F18, 0x00000003); OUT_CS_REG(0x4F1C, 0x00000000); OUT_CS_REG(0x4F28, 0x00000000); @@ -313,15 +311,14 @@ OUT_CS_REG(0x2208, 0x00F02203); OUT_CS_REG(0x2208, 0x00D10021); OUT_CS_REG(0x2208, 0x01248021); OUT_CS_REG(0x2208, 0x00000000); + +r300_emit_dsa_state(r300, &dsa_clear_state); + R300_PACIFY; OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); //OUT_CS_REG(0x4E38, 0x00C00100); OUT_CS_REG(0x4E0C, 0x0000000F); -OUT_CS_REG(0x4F00, 0x00000000); -OUT_CS_REG(0x4F04, 0x00000000); -OUT_CS_REG(0x4F08, 0x00FF0000); - /* XXX Packet3 */ OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index 8ec7151f4d..2b89698ca5 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -45,4 +45,14 @@ const struct r300_blend_color_state blend_color_clear_state = { .blend_color_green_blue = 0x0, }; +const struct r300_dsa_state dsa_clear_state = { + .alpha_function = 0x0, + .alpha_reference = 0x0, + .z_buffer_control = 0x0, + .z_stencil_control = 0x0, + .stencil_ref_mask = 0x0, + .z_buffer_top = R300_ZTOP_ENABLE, + .stencil_ref_bf = 0x0, +}; + #endif /* R300_SURFACE_H */ -- cgit v1.2.3 From 962d2e678f4da6ffef4f21f2fa9b062747bfbb85 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 27 Jan 2009 15:12:01 -0800 Subject: r300: Clean up PVS upload emits. --- src/gallium/drivers/r300/r300_surface.c | 82 +++++---------------------------- 1 file changed, 11 insertions(+), 71 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index aab1850144..c0b020f81d 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -184,66 +184,6 @@ OUT_CS_REG(0x4F54, 0x00000000); OUT_CS_REG(0x43E8, 0x00000000); R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000406); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x3F800000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x43E8, 0x00000000); -R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000400); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x43E8, 0x00000000); -R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000401); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x43E8, 0x00000000); -R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000402); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x43E8, 0x00000000); -R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000403); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x43E8, 0x00000000); -R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000404); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x43E8, 0x00000000); -R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000405); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00000000); OUT_CS_REG(0x2150, 0x21030003); OUT_CS_REG(0x4BC0, 0x00000000); OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688); @@ -290,7 +230,6 @@ OUT_CS_REG(0x48C0, 0x00050A80); OUT_CS_REG(0x46C0, 0x1C000000); OUT_CS_REG(0x49C0, 0x00040889); OUT_CS_REG(0x47C0, 0x01000000); -OUT_CS_REG(0x2284, 0x00000000); /* XXX these magic numbers should be explained when * this becomes a cached state object */ OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | @@ -301,16 +240,17 @@ OUT_CS_REG(0x22D8, 0x00000001); OUT_CS_REG(0x43E8, 0x00000000); R300_PACIFY; OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2284, 0x00000001); -OUT_CS_REG(0x2200, 0x00000000); -OUT_CS_REG(0x2208, 0x00F00203); -OUT_CS_REG(0x2208, 0x00D10001); -OUT_CS_REG(0x2208, 0x01248001); -OUT_CS_REG(0x2208, 0x00000000); -OUT_CS_REG(0x2208, 0x00F02203); -OUT_CS_REG(0x2208, 0x00D10021); -OUT_CS_REG(0x2208, 0x01248021); -OUT_CS_REG(0x2208, 0x00000000); +/* XXX translate these back into normal instructions */ +OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); +OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF00203); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10001); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248001); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021); +OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); r300_emit_dsa_state(r300, &dsa_clear_state); -- cgit v1.2.3 From 9814fca71897a11f635945224105eb40c021d787 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 27 Jan 2009 17:56:44 -0800 Subject: r300: Cleanup first part of RS block. Working towards r500-ability. --- src/gallium/drivers/r300/r300_surface.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index c0b020f81d..728a0076b7 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -33,6 +33,7 @@ static void r300_surface_fill(struct pipe_context* pipe, struct r300_context* r300 = r300_context(pipe); CS_LOCALS(r300); struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps; + int i; float r, g, b, a; r = (float)((color >> 16) & 0xff) / 255.0f; g = (float)((color >> 8) & 0xff) / 255.0f; @@ -117,8 +118,6 @@ OUT_CS_REG(0x42B4, 0x00000000); OUT_CS_REG(0x42B8, 0x00000000); OUT_CS_REG(0x42C0, 0x4B7FFFFF); OUT_CS_REG(0x42C4, 0x00000000); -OUT_CS_REG(0x4300, 0x00000000); -OUT_CS_REG(0x4304, 0x00000000); OUT_CS_REG(0x4310, 0x00000000); OUT_CS_REG(0x4314, 0x00000000); OUT_CS_REG(0x4318, 0x00000000); @@ -208,16 +207,26 @@ r300_emit_blend_state(r300, &blend_clear_state); OUT_CS_REG(0x221C, 0x0001C000); OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | ((w * 6) << R300_POINTSIZE_X_SHIFT)); -OUT_CS_REG(0x4310, 0x00D10000); -OUT_CS_REG(0x4314, 0x00D10000); -OUT_CS_REG(0x4318, 0x00D10000); -OUT_CS_REG(0x431C, 0x00D10000); -OUT_CS_REG(0x4320, 0x00D10000); -OUT_CS_REG(0x4324, 0x00D10000); -OUT_CS_REG(0x4328, 0x00D10000); -OUT_CS_REG(0x432C, 0x00D10000); -OUT_CS_REG(0x4300, 0x00040080); -OUT_CS_REG(0x4304, 0x00000000); + +/* XXX RS block setup */ +if (caps->is_r500) { + OUT_CS_REG_SEQ(R500_RS_IP_0, 8); + for (i = 0; i < 8; i++) { + /* I like the operator macros more than the shift macros... */ + OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | + (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | + (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); + } +} else { + OUT_CS_REG_SEQ(R300_RS_IP_0, 8); + for (i = 0; i < 8; i++) { + OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); + } +} +OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); +OUT_CS_REG(R300_RS_INST_COUNT, 0x0); + OUT_CS_REG(0x4330, 0x00004000); OUT_CS_REG(0x4600, 0x00000000); OUT_CS_REG(0x4604, 0x00000000); -- cgit v1.2.3 From 3f1bc7ed3285de255d0a76f1ed3e439f3b668d9b Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 27 Jan 2009 18:09:14 -0800 Subject: r300: Moar RS cleanup. How could I possibly miss these? --- src/gallium/drivers/r300/r300_surface.c | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 728a0076b7..47a3aac77d 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -118,15 +118,6 @@ OUT_CS_REG(0x42B4, 0x00000000); OUT_CS_REG(0x42B8, 0x00000000); OUT_CS_REG(0x42C0, 0x4B7FFFFF); OUT_CS_REG(0x42C4, 0x00000000); -OUT_CS_REG(0x4310, 0x00000000); -OUT_CS_REG(0x4314, 0x00000000); -OUT_CS_REG(0x4318, 0x00000000); -OUT_CS_REG(0x431C, 0x00000000); -OUT_CS_REG(0x4320, 0x00000000); -OUT_CS_REG(0x4324, 0x00000000); -OUT_CS_REG(0x4328, 0x00000000); -OUT_CS_REG(0x432C, 0x00000000); -OUT_CS_REG(0x4330, 0x00000000); OUT_CS_REG(0x43A4, 0x0000001C); OUT_CS_REG(0x43A8, 0x2DA49525); OUT_CS_REG(0x43E8, 0x00FFFFFF); -- cgit v1.2.3 From f6add70ef889b609a114baf8f6bcb43413caa702 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 28 Jan 2009 02:40:18 -0800 Subject: r300: Fix small r300_reg typo. --- src/gallium/drivers/r300/r300_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index c1796ad7a8..37f168ed4c 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -658,7 +658,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_GB_FOG_SELECT_C3A (3 << 0) # define R300_GB_FOG_SELECT_1_1_W (4 << 0) # define R300_GB_FOG_SELECT_Z (5 << 0) -# define R300_GB_DEPTH_SELECT_Z (0 << 3 +# define R300_GB_DEPTH_SELECT_Z (0 << 3) # define R300_GB_DEPTH_SELECT_1_1_W (1 << 3) # define R300_GB_W_SELECT_1_W (0 << 4) # define R300_GB_W_SELECT_1 (1 << 4) -- cgit v1.2.3 From 80dc1801409f9913cc37b8fc8e68c692bc8a22ca Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 28 Jan 2009 02:51:51 -0800 Subject: r300: A handful of thingys. --- src/gallium/drivers/r300/r300_cs.h | 6 ++-- src/gallium/drivers/r300/r300_emit.c | 1 + src/gallium/drivers/r300/r300_reg.h | 2 +- src/gallium/drivers/r300/r300_surface.c | 54 ++++++++++++++++++--------------- 4 files changed, 35 insertions(+), 28 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 653e2fdafa..42ec9fb094 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -61,7 +61,7 @@ static uint32_t pack_float_32(float f) #define CS_LOCALS(context) \ struct r300_winsys* cs_winsys = context->winsys; \ struct radeon_cs* cs = cs_winsys->cs; \ - int cs_count; + int cs_count = 0; #define CHECK_CS(size) \ cs_winsys->check_cs(cs, (size)) @@ -75,11 +75,13 @@ static uint32_t pack_float_32(float f) } while (0) #define OUT_CS(value) do { \ - cs_winsys->write_cs_dword(cs, value); \ + cs_winsys->write_cs_dword(cs, (value)); \ + cs_count--; \ } while (0) #define OUT_CS_32F(value) do { \ cs_winsys->write_cs_dword(cs, pack_float_32(value)); \ + cs_count--; \ } while (0) #define OUT_CS_REG(register, value) do { \ diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index d8de766c31..4ae8a46637 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -73,6 +73,7 @@ void r300_emit_dsa_state(struct r300_context* r300, if (r300screen->caps->is_r500) { OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); } + END_CS; } static void r300_emit_dirty_state(struct r300_context* r300) diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index 37f168ed4c..c1d5009b86 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -670,7 +670,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_GB_FOG_STUFF_COMP_MASK 0x00000c00 /* Specifies the graphics pipeline configuration for antialiasing. */ -#define GB_AA_CONFIG 0x4020 +#define R300_GB_AA_CONFIG 0x4020 # define GB_AA_CONFIG_AA_DISABLE (0 << 0) # define GB_AA_CONFIG_AA_ENABLE (1 << 0) # define GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2 (0 << 1) diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 47a3aac77d..fc756133b4 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -68,30 +68,31 @@ OUT_CS_REG(R300_VAP_VF_MIN_VTX_INDX, 0x0); /* XXX endian */ OUT_CS_REG(R300_VAP_CNTL_STATUS, R300_VC_NO_SWAP); OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0); -OUT_CS_REG(0x21DC, 0xAAAAAAAA); -OUT_CS_REG(0x221C, 0x00000000); -OUT_CS_REG(0x2220, 0x3F800000); -OUT_CS_REG(0x2224, 0x3F800000); -OUT_CS_REG(0x2228, 0x3F800000); -OUT_CS_REG(0x222C, 0x3F800000); -OUT_CS_REG(0x2288, 0x0000FFFF); -OUT_CS_REG(0x2090, 0x00000000); -OUT_CS_REG(0x2094, 0x00000000); -OUT_CS_REG(0x22D0, 0x00000000); -OUT_CS_REG(0x22D4, 0x00000000); -OUT_CS_REG(0x22D8, 0x00000000); -OUT_CS_REG(0x4008, 0x00000007); -OUT_CS_REG(0x4010, 0x66666666); -OUT_CS_REG(0x4014, 0x06666666); +/* XXX magic number not in r300_reg */ +OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA); +OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0); +OUT_CS_REG(R300_VAP_GB_VERT_CLIP_ADJ, 4); +OUT_CS_32F(1.0); +OUT_CS_32F(1.0); +OUT_CS_32F(1.0); +OUT_CS_32F(1.0); +/* XXX is this too long? */ +OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xFFFF); +OUT_CS_REG(R300_GB_ENABLE, R300_GB_POINT_STUFF_ENABLE | + R300_GB_LINE_STUFF_ENABLE | R300_GB_TRIANGLE_STUFF_ENABLE); +/* XXX more magic numbers */ +OUT_CS_REG(R300_GB_MSPOS0, 0x66666666); +OUT_CS_REG(R300_GB_MSPOS1, 0x66666666); /* XXX why doesn't classic Mesa write the number of pipes, too? */ OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16); -OUT_CS_REG(0x401C, 0x00000004); -OUT_CS_REG(0x4020, 0x00000000); -OUT_CS_REG(0x4104, 0x00000000); -OUT_CS_REG(0x4200, 0x00000000); -OUT_CS_REG(0x4204, 0x00000000); -OUT_CS_REG(0x4208, 0x3F800000); -OUT_CS_REG(0x420C, 0x3F800000); +OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W); +OUT_CS_REG(R300_GB_AA_CONFIG, 0x0); +/* XXX point tex stuffing */ +OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4); +OUT_CS_32F(0.0); +OUT_CS_32F(0.0); +OUT_CS_32F(1.0); +OUT_CS_32F(1.0); OUT_CS_REG(0x4214, 0x00050005); OUT_CS_REG(0x4230, 0x18000006); OUT_CS_REG(0x4234, 0x00020006); @@ -184,7 +185,7 @@ OUT_CS_REG(0x20B4, 0x00000008); OUT_CS_REG(0x21DC, 0xAAAAAAAA); OUT_CS_REG(0x2090, 0x00000003); OUT_CS_REG(0x2094, 0x00000000); -OUT_CS_REG(0x4104, 0x00000000); +OUT_CS_REG(R300_TX_ENABLE, 0x0); OUT_CS_REG(0x1D98, 0x3F800000); OUT_CS_REG(0x1D9C, 0x00000000); OUT_CS_REG(0x1DA0, 0x3F800000); @@ -273,8 +274,11 @@ OUT_CS_32F(g); OUT_CS_32F(b); OUT_CS_32F(1.0); -OUT_CS_REG(0x4E4C, 0x0000000A); -OUT_CS_REG(0x4F18, 0x00000003); +/* XXX figure out why this is 0xA and not 0x2 */ +/* XXX OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); +OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, + R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | + R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */ R300_PACIFY; END_CS; -- cgit v1.2.3 From 84ec4d6bedf33bf03ff7a778632eef7b209944cb Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 28 Jan 2009 02:57:08 -0800 Subject: Ack, forgot to update the index again. --- src/gallium/drivers/r300/r300_cs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 42ec9fb094..5686e5a6e9 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -68,10 +68,10 @@ static uint32_t pack_float_32(float f) #define BEGIN_CS(size) do { \ CHECK_CS(size); \ - debug_printf("r300: BEGIN_CS in %s (%s:%d)\n", __FUNCTION__, __FILE__, \ - __LINE__); \ + debug_printf("r300: BEGIN_CS, count %d, in %s (%s:%d)\n", \ + size, __FUNCTION__, __FILE__, __LINE__); \ cs_winsys->begin_cs(cs, (size), __FILE__, __FUNCTION__, __LINE__); \ - int cs_count = size; \ + cs_count = size; \ } while (0) #define OUT_CS(value) do { \ -- cgit v1.2.3 From 588d8f3befa007e03ffb124033e6879330ad9614 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 28 Jan 2009 03:06:08 -0800 Subject: r300: Fix a few more registers. --- src/gallium/drivers/r300/r300_surface.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index fc756133b4..0ef26d4305 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -93,11 +93,13 @@ OUT_CS_32F(0.0); OUT_CS_32F(0.0); OUT_CS_32F(1.0); OUT_CS_32F(1.0); -OUT_CS_REG(0x4214, 0x00050005); -OUT_CS_REG(0x4230, 0x18000006); -OUT_CS_REG(0x4234, 0x00020006); -OUT_CS_REG(0x4238, 0x3BAAAAAB); +OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 | + (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT)); +/* XXX should this be related to the actual point size? */ +OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 | + (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT)); OUT_CS_REG(0x4234, 0x00030006); +OUT_CS_REG(0x4238, 0x3BAAAAAB); OUT_CS_REG(0x4260, 0x00000000); OUT_CS_REG(0x4264, 0x00000000); OUT_CS_REG(0x4268, 0x3F800000); -- cgit v1.2.3 From 00f96d054d782fd0fa7b103b857fb19d3e4a1472 Mon Sep 17 00:00:00 2001 From: Joakim Sindholt Date: Wed, 28 Jan 2009 14:53:39 +0100 Subject: r300: name registers for human readability Signed-off-by: Corbin Simpson --- src/gallium/drivers/r300/r300_surface.c | 206 ++++++++++++++++---------------- 1 file changed, 103 insertions(+), 103 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 0ef26d4305..48e0f54db9 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -47,12 +47,12 @@ R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; /* Viewport setup */ -OUT_CS_REG(0x1D98, 0x43000000); -OUT_CS_REG(0x1D9C, 0x43002000); -OUT_CS_REG(0x1DA0, 0xC3000000); -OUT_CS_REG(0x1DA4, 0x43002000); -OUT_CS_REG(0x1DA8, 0x3F000000); -OUT_CS_REG(0x1DAC, 0x3F000000); +OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x43000000); +OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x43002000); +OUT_CS_REG(R300_SE_VPORT_YSCALE, 0xC3000000); +OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x43002000); +OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F000000); +OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x3F000000); /* Flush PVS. */ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); @@ -98,61 +98,61 @@ OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 | /* XXX should this be related to the actual point size? */ OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 | (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT)); -OUT_CS_REG(0x4234, 0x00030006); -OUT_CS_REG(0x4238, 0x3BAAAAAB); -OUT_CS_REG(0x4260, 0x00000000); -OUT_CS_REG(0x4264, 0x00000000); -OUT_CS_REG(0x4268, 0x3F800000); -OUT_CS_REG(0x4274, 0x00000002); -OUT_CS_REG(0x4278, 0x0003AAAA); -OUT_CS_REG(0x427C, 0x00000000); -OUT_CS_REG(0x4280, 0x00000000); -OUT_CS_REG(0x4288, 0x00000000); -OUT_CS_REG(0x428C, 0x00000001); -OUT_CS_REG(0x4290, 0x00000000); -OUT_CS_REG(0x4294, 0x3DBF1412); -OUT_CS_REG(0x4298, 0x00000000); -OUT_CS_REG(0x42A0, 0x00000000); -OUT_CS_REG(0x42A4, 0x00000000); -OUT_CS_REG(0x42A8, 0x00000000); -OUT_CS_REG(0x42AC, 0x00000000); -OUT_CS_REG(0x42B0, 0x00000000); -OUT_CS_REG(0x42B4, 0x00000000); -OUT_CS_REG(0x42B8, 0x00000000); -OUT_CS_REG(0x42C0, 0x4B7FFFFF); -OUT_CS_REG(0x42C4, 0x00000000); -OUT_CS_REG(0x43A4, 0x0000001C); -OUT_CS_REG(0x43A8, 0x2DA49525); -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x46A4, 0x00001B00); +OUT_CS_REG(R300_GA_LINE_CNTL, 0x00030006); +OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, 0x3BAAAAAB); +OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, 0x00000000); +OUT_CS_REG(R300_GA_LINE_S0, 0x00000000); +OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000); +OUT_CS_REG(R300_GA_ENHANCE, 0x00000002); +OUT_CS_REG(R300_GA_COLOR_CONTROL, 0x0003AAAA); +OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000); +OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000); +OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000); +OUT_CS_REG(R300_GA_ROUND_MODE, 0x00000001); +OUT_CS_REG(R300_GA_OFFSET, 0x00000000); +OUT_CS_REG(R300_GA_FOG_SCALE, 0x3DBF1412); +OUT_CS_REG(R300_GA_FOG_OFFSET, 0x00000000); +OUT_CS_REG(R300_SU_TEX_WRAP, 0x00000000); +OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, 0x00000000); +OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, 0x00000000); +OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, 0x00000000); +OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, 0x00000000); +OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, 0x00000000); +OUT_CS_REG(R300_SU_CULL_MODE, 0x00000000); +OUT_CS_REG(R300_SU_DEPTH_SCALE, 0x4B7FFFFF); +OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000); +OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C); +OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525); +OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); +OUT_CS_REG(R300_US_OUT_FMT, 0x00001B00); OUT_CS_REG(0x46A8, 0x00001B0F); OUT_CS_REG(0x46AC, 0x00001B0F); OUT_CS_REG(0x46B0, 0x00001B0F); -OUT_CS_REG(0x46B4, 0x00000001); -OUT_CS_REG(0x4600, 0x00000000); -OUT_CS_REG(0x4604, 0x00000000); -OUT_CS_REG(0x4608, 0x00000000); -OUT_CS_REG(0x4610, 0x00000000); -OUT_CS_REG(0x4614, 0x00000000); -OUT_CS_REG(0x4618, 0x00000000); -OUT_CS_REG(0x461C, 0x00000000); -OUT_CS_REG(0x48C0, 0x00000000); -OUT_CS_REG(0x46C0, 0x00000000); -OUT_CS_REG(0x49C0, 0x00000000); -OUT_CS_REG(0x47C0, 0x00000000); -OUT_CS_REG(0x4BC0, 0x00000002); -OUT_CS_REG(0x4BC8, 0x00000000); -OUT_CS_REG(0x4BCC, 0x00000000); -OUT_CS_REG(0x4BD0, 0x00000000); -OUT_CS_REG(0x4BD8, 0x00000000); -OUT_CS_REG(0x4BD8, 0x00000000); -OUT_CS_REG(0x4E00, 0x00000000); -OUT_CS_REG(0x4E0C, 0x0000000F); +OUT_CS_REG(R300_US_W_FMT, 0x00000001); +OUT_CS_REG(R300_US_CONFIG, 0x00000000); +OUT_CS_REG(R300_US_PIXSIZE, 0x00000000); +OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00000000); +OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00000000); +OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x00000000); +OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00000000); +OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x00000000); +OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002); +OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000); +OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000); +OUT_CS_REG(R300_FG_FOG_COLOR_B, 0x00000000); +OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000); +OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000); +OUT_CS_REG(R300_RB3D_CCTL, 0x00000000); +OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); r300_emit_blend_color_state(r300, &blend_color_clear_state); -OUT_CS_REG(0x4E10, 0x00000000); -OUT_CS_REG(0x4E54, 0x00000000); +OUT_CS_REG(R300_RB3D_BLEND_COLOR, 0x00000000); +OUT_CS_REG(0x4E54, 0x00000000); OUT_CS_REG(0x4E58, 0x00000000); OUT_CS_REG(0x4E5C, 0x00000000); OUT_CS_REG(0x4E60, 0x00000000); @@ -160,45 +160,45 @@ OUT_CS_REG(0x4E64, 0x00000000); OUT_CS_REG(0x4E68, 0x00000000); OUT_CS_REG(0x4E6C, 0x00000000); OUT_CS_REG(0x4E70, 0x00000000); -OUT_CS_REG(0x4E88, 0x00000000); -OUT_CS_REG(0x4EA0, 0x00000000); -OUT_CS_REG(0x4EA4, 0xFFFFFFFF); -OUT_CS_REG(0x4F00, 0x00000010); -OUT_CS_REG(0x4F04, 0x00038038); -OUT_CS_REG(0x4F08, 0x00FFFF00); -OUT_CS_REG(0x4F10, 0x00000002); -OUT_CS_REG(0x4F18, 0x00000003); -OUT_CS_REG(0x4F1C, 0x00000000); -OUT_CS_REG(0x4F28, 0x00000000); +OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000); +OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000); +OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF); +OUT_CS_REG(R300_ZB_CNTL, 0x00000010); +OUT_CS_REG(R300_ZB_ZSTENCILCNTL, 0x00038038); +OUT_CS_REG(R300_ZB_STENCILREFMASK, 0x00FFFF00); +OUT_CS_REG(R300_ZB_FORMAT, 0x00000002); +OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003); +OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000); +OUT_CS_REG(R300_ZB_DEPTHCLEARVALUE, 0x00000000); OUT_CS_REG(0x4F30, 0x00000000); OUT_CS_REG(0x4F34, 0x00000000); -OUT_CS_REG(0x4F44, 0x00000000); -OUT_CS_REG(0x4F54, 0x00000000); -OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000); +OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000); +OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000); R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); -OUT_CS_REG(0x2150, 0x21030003); -OUT_CS_REG(0x4BC0, 0x00000000); +OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); +OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x21030003); +OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000); OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688); OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1); OUT_CS_REG(R300_VAP_VSM_VTX_ASSM, 0x405); -OUT_CS_REG(0x20B0, 0x0000043F); -OUT_CS_REG(0x20B4, 0x00000008); -OUT_CS_REG(0x21DC, 0xAAAAAAAA); -OUT_CS_REG(0x2090, 0x00000003); -OUT_CS_REG(0x2094, 0x00000000); +OUT_CS_REG(R300_SE_VTE_CNTL, 0x0000043F); +OUT_CS_REG(R300_VAP_VTX_SIZE, 0x00000008); +OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA); +OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003); +OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000); OUT_CS_REG(R300_TX_ENABLE, 0x0); -OUT_CS_REG(0x1D98, 0x3F800000); -OUT_CS_REG(0x1D9C, 0x00000000); -OUT_CS_REG(0x1DA0, 0x3F800000); -OUT_CS_REG(0x1DA4, 0x00000000); -OUT_CS_REG(0x1DA8, 0x3F800000); -OUT_CS_REG(0x1DAC, 0x00000000); -OUT_CS_REG(0x4BD4, 0x00000000); +OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x3F800000); +OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x00000000); +OUT_CS_REG(R300_SE_VPORT_YSCALE, 0x3F800000); +OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x00000000); +OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F800000); +OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x00000000); +OUT_CS_REG(R300_FG_ALPHA_FUNC, 0x00000000); r300_emit_blend_state(r300, &blend_clear_state); -OUT_CS_REG(0x221C, 0x0001C000); +OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000); OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | ((w * 6) << R300_POINTSIZE_X_SHIFT)); @@ -221,28 +221,28 @@ if (caps->is_r500) { OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); OUT_CS_REG(R300_RS_INST_COUNT, 0x0); -OUT_CS_REG(0x4330, 0x00004000); -OUT_CS_REG(0x4600, 0x00000000); -OUT_CS_REG(0x4604, 0x00000000); -OUT_CS_REG(0x4608, 0x00000000); -OUT_CS_REG(0x4610, 0x00000000); -OUT_CS_REG(0x4614, 0x00000000); -OUT_CS_REG(0x4618, 0x00000000); -OUT_CS_REG(0x461C, 0x00400000); -OUT_CS_REG(0x48C0, 0x00050A80); -OUT_CS_REG(0x46C0, 0x1C000000); -OUT_CS_REG(0x49C0, 0x00040889); -OUT_CS_REG(0x47C0, 0x01000000); +OUT_CS_REG(R300_RS_INST_0, 0x00004000); +OUT_CS_REG(R300_US_CONFIG, 0x00000000); +OUT_CS_REG(R300_US_PIXSIZE, 0x00000000); +OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000); +OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00400000); +OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00050A80); +OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000); +OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); +OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x01000000); /* XXX these magic numbers should be explained when * this becomes a cached state object */ OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT)); -OUT_CS_REG(0x22D0, 0x00100000); -OUT_CS_REG(0x22D4, 0x00000000); -OUT_CS_REG(0x22D8, 0x00000001); -OUT_CS_REG(0x43E8, 0x00000000); +OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000); +OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000); +OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001); +OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000); R300_PACIFY; -OUT_CS_REG(0x43E8, 0x00FFFFFF); +OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); /* XXX translate these back into normal instructions */ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0); @@ -260,8 +260,8 @@ r300_emit_dsa_state(r300, &dsa_clear_state); R300_PACIFY; OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); -//OUT_CS_REG(0x4E38, 0x00C00100); -OUT_CS_REG(0x4E0C, 0x0000000F); +//OUT_CS_REG(R300_RB3D_COLORPITCH0, 0x00C00100); +OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); /* XXX Packet3 */ OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); OUT_CS(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING | -- cgit v1.2.3 From f0fce46a48a1f0547a1e50ad54696c4b660c8dce Mon Sep 17 00:00:00 2001 From: Joakim Sindholt Date: Thu, 29 Jan 2009 00:12:32 +0100 Subject: r300: attempt at trivial/clear on r5xx --- src/gallium/drivers/r300/r300_cs.h | 4 +- src/gallium/drivers/r300/r300_reg.h | 25 ++++++++-- src/gallium/drivers/r300/r300_surface.c | 83 +++++++++++++++++++++++++-------- 3 files changed, 87 insertions(+), 25 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 5686e5a6e9..d15887fb1c 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -85,7 +85,7 @@ static uint32_t pack_float_32(float f) } while (0) #define OUT_CS_REG(register, value) do { \ - debug_printf("r300: writing 0x%x to register 0x%x\n", value, register); \ + debug_printf("r300: writing 0x%08X to register 0x%04X\n", value, register); \ OUT_CS(CP_PACKET0(register, 0)); \ OUT_CS(value); \ } while (0) @@ -93,7 +93,7 @@ static uint32_t pack_float_32(float f) /* Note: This expects count to be the number of registers, * not the actual packet0 count! */ #define OUT_CS_REG_SEQ(register, count) do { \ - debug_printf("r300: writing register sequence 0x%x\n", register); \ + debug_printf("r300: writing register sequence of %d to 0x%04X\n", count, register); \ OUT_CS(CP_PACKET0(register, ((count) - 1))); \ } while (0) diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index c1d5009b86..9281e6656f 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -1669,7 +1669,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_TEX_INST_MASK (7 << 15) /* Output format from the unfied shader */ -#define R300_US_OUT_FMT 0x46A4 +#define R300_US_OUT_FMT_0 0x46A4 # define R300_US_OUT_FMT_C4_8 (0 << 0) # define R300_US_OUT_FMT_C4_10 (1 << 0) # define R300_US_OUT_FMT_C4_10_GAMMA (2 << 0) @@ -1691,7 +1691,24 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_US_OUT_FMT_C4_16_FP (18 << 0) # define R300_US_OUT_FMT_C_32_FP (19 << 0) # define R300_US_OUT_FMT_C2_32_FP (20 << 0) -# define R300_US_OUT_FMT_C4_32_FP (20 << 0) +# define R300_US_OUT_FMT_C4_32_FP (21 << 0) +# define R300_C0_SEL_A (0 << 8) +# define R300_C0_SEL_R (1 << 8) +# define R300_C0_SEL_G (2 << 8) +# define R300_C0_SEL_B (3 << 8) +# define R300_C1_SEL_A (0 << 10) +# define R300_C1_SEL_R (1 << 10) +# define R300_C1_SEL_G (2 << 10) +# define R300_C1_SEL_B (3 << 10) +# define R300_C2_SEL_A (0 << 12) +# define R300_C2_SEL_R (1 << 12) +# define R300_C2_SEL_G (2 << 12) +# define R300_C2_SEL_B (3 << 12) +# define R300_C3_SEL_A (0 << 14) +# define R300_C3_SEL_R (1 << 14) +# define R300_C3_SEL_G (2 << 14) +# define R300_C3_SEL_B (3 << 14) +# define R300_OUT_SIGN(x) (x << 16) /* ALU * The ALU instructions register blocks are enumerated according to the order @@ -2987,7 +3004,7 @@ enum { # define R500_US_CODE_RANGE_ADDR(x) (x << 0) # define R500_US_CODE_RANGE_SIZE(x) (x << 16) #define R500_US_CONFIG 0x4600 -# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) +# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 0) #define R500_US_FC_ADDR_0 0xa000 # define R500_FC_BOOL_ADDR(x) (x << 0) # define R500_FC_INT_ADDR(x) (x << 8) @@ -3031,7 +3048,7 @@ enum { # define R500_FORMAT_TXHEIGHT(x) (x << 11) # define R500_FORMAT_TXDEPTH(x) (x << 22) /* _0 through _3 */ -#define R500_US_OUT_FMT_0 0x46a4 +#define R500_US_OUT_FMT_0 0x46A4 # define R500_OUT_FMT_C4_8 (0 << 0) # define R500_OUT_FMT_C4_10 (1 << 0) # define R500_OUT_FMT_C4_10_GAMMA (2 << 0) diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 48e0f54db9..f2d0183c98 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -42,7 +42,7 @@ static void r300_surface_fill(struct pipe_context* pipe, " dimensions %dx%d, color 0x%x\n", dest, x, y, w, h, color); -BEGIN_CS(276); +BEGIN_CS((caps->is_r500) ? 367 : 276); R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; @@ -88,10 +88,9 @@ OUT_CS_REG(R300_GB_TILE_CONFIG, R300_GB_TILE_ENABLE | R300_GB_TILE_SIZE_16); OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W); OUT_CS_REG(R300_GB_AA_CONFIG, 0x0); /* XXX point tex stuffing */ -OUT_CS_REG_SEQ(R300_GA_POINT_S0, 4); +OUT_CS_REG_SEQ(R300_GA_POINT_S0, 1); OUT_CS_32F(0.0); -OUT_CS_32F(0.0); -OUT_CS_32F(1.0); +OUT_CS_REG_SEQ(R300_GA_POINT_S1, 1); OUT_CS_32F(1.0); OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 | (0x5 << R300_GA_TRIANGLE_STIPPLE_Y_SHIFT_SHIFT)); @@ -124,10 +123,11 @@ OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000); OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C); OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525); OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); -OUT_CS_REG(R300_US_OUT_FMT, 0x00001B00); -OUT_CS_REG(0x46A8, 0x00001B0F); -OUT_CS_REG(0x46AC, 0x00001B0F); -OUT_CS_REG(0x46B0, 0x00001B0F); +OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4); +OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R); +OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); +OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); +OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); OUT_CS_REG(R300_US_W_FMT, 0x00000001); OUT_CS_REG(R300_US_CONFIG, 0x00000000); OUT_CS_REG(R300_US_PIXSIZE, 0x00000000); @@ -152,14 +152,10 @@ OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); r300_emit_blend_color_state(r300, &blend_color_clear_state); OUT_CS_REG(R300_RB3D_BLEND_COLOR, 0x00000000); -OUT_CS_REG(0x4E54, 0x00000000); -OUT_CS_REG(0x4E58, 0x00000000); -OUT_CS_REG(0x4E5C, 0x00000000); -OUT_CS_REG(0x4E60, 0x00000000); -OUT_CS_REG(0x4E64, 0x00000000); -OUT_CS_REG(0x4E68, 0x00000000); -OUT_CS_REG(0x4E6C, 0x00000000); -OUT_CS_REG(0x4E70, 0x00000000); +/* XXX: Oh the wonderful unknown */ +OUT_CS_REG_SEQ(0x4E54, 8); +for (i = 0; i < 8; i++) + OUT_CS(0x00000000); OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000); OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000); OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF); @@ -202,16 +198,65 @@ OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000); OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | ((w * 6) << R300_POINTSIZE_X_SHIFT)); -/* XXX RS block setup */ +/* XXX RS block and fp setup */ if (caps->is_r500) { - OUT_CS_REG_SEQ(R500_RS_IP_0, 8); - for (i = 0; i < 8; i++) { + OUT_CS_REG_SEQ(R500_RS_IP_0, 16); + for (i = 0; i < 16; i++) { /* I like the operator macros more than the shift macros... */ OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); } + R300_PACIFY; + OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); + OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | + R500_US_CODE_END_ADDR(1)); + OUT_CS_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | + R500_US_CODE_RANGE_SIZE(1)); + OUT_CS_REG(R500_US_CODE_OFFSET, R500_US_CODE_OFFSET_ADDR(0)); + R300_PACIFY; + OUT_CS_REG(R500_US_CMN_INST_0, + R500_INST_TYPE_OUT | + R500_INST_TEX_SEM_WAIT | + R500_INST_LAST | + R500_INST_RGB_OMASK_R | + R500_INST_RGB_OMASK_G | + R500_INST_RGB_OMASK_B | + R500_INST_ALPHA_OMASK | + R500_INST_RGB_CLAMP | + R500_INST_ALPHA_CLAMP); + OUT_CS_REG(R500_US_ALU_RGB_ADDR_0, + R500_RGB_ADDR0(0) | + R500_RGB_ADDR1(0) | + R500_RGB_ADDR1_CONST | + R500_RGB_ADDR2(0) | + R500_RGB_ADDR2_CONST); + OUT_CS_REG(R500_US_ALU_ALPHA_ADDR_0, + R500_ALPHA_ADDR0(0) | + R500_ALPHA_ADDR1(0) | + R500_ALPHA_ADDR1_CONST | + R500_ALPHA_ADDR2(0) | + R500_ALPHA_ADDR2_CONST); + OUT_CS_REG(R500_US_ALU_RGB_INST_0, + R500_ALU_RGB_SEL_A_SRC0 | + R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | + R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC0 | + R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_G | + R500_ALU_RGB_G_SWIZ_B_B); + OUT_CS_REG(R500_US_ALU_ALPHA_INST_0, + R500_ALPHA_OP_CMP | + R500_ALPHA_SWIZ_A_A | + R500_ALPHA_SWIZ_B_A); + OUT_CS_REG(R500_US_ALU_RGBA_INST_0, + R500_ALU_RGBA_OP_CMP | + R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | + R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0); } else { OUT_CS_REG_SEQ(R300_RS_IP_0, 8); for (i = 0; i < 8; i++) { -- cgit v1.2.3 From c199f330322921e01c8c30e3ea69a2a5291ae8ee Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 28 Jan 2009 21:33:35 -0800 Subject: r300: Unbreak emit, fix up a bunch of little things. --- src/gallium/drivers/r300/r300_cs.h | 9 +++- src/gallium/drivers/r300/r300_emit.c | 7 +++- src/gallium/drivers/r300/r300_surface.c | 73 +++++++++++++++++---------------- src/gallium/drivers/r300/r300_surface.h | 2 +- 4 files changed, 50 insertions(+), 41 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index d15887fb1c..734ccb13d9 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -85,7 +85,9 @@ static uint32_t pack_float_32(float f) } while (0) #define OUT_CS_REG(register, value) do { \ - debug_printf("r300: writing 0x%08X to register 0x%04X\n", value, register); \ + debug_printf("r300: writing 0x%08X to register 0x%04X\n", \ + value, register); \ + assert(register); \ OUT_CS(CP_PACKET0(register, 0)); \ OUT_CS(value); \ } while (0) @@ -93,13 +95,16 @@ static uint32_t pack_float_32(float f) /* Note: This expects count to be the number of registers, * not the actual packet0 count! */ #define OUT_CS_REG_SEQ(register, count) do { \ - debug_printf("r300: writing register sequence of %d to 0x%04X\n", count, register); \ + debug_printf("r300: writing register sequence of %d to 0x%04X\n", \ + count, register); \ + assert(register); \ OUT_CS(CP_PACKET0(register, ((count) - 1))); \ } while (0) #define OUT_CS_RELOC(bo, offset, rd, wd, flags) do { \ debug_printf("r300: writing relocation for buffer %p, offset %d\n", \ bo, offset); \ + assert(bo); \ OUT_CS(offset); \ cs_winsys->write_cs_reloc(cs, bo, rd, wd, flags); \ } while (0) diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 4ae8a46637..c5f08a2404 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -62,9 +62,12 @@ void r300_emit_dsa_state(struct r300_context* r300, struct r300_screen* r300screen = (struct r300_screen*)r300->context.screen; CS_LOCALS(r300); - BEGIN_CS(r300screen->caps->is_r500 ? 12 : 10); + BEGIN_CS(r300screen->caps->is_r500 ? 12 : 8); OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); - OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); + /* XXX figure out the r300 counterpart for this */ + if (r300screen->caps->is_r500) { + OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); + } OUT_CS_REG_SEQ(R300_ZB_CNTL, 3); OUT_CS(dsa->z_buffer_control); OUT_CS(dsa->z_stencil_control); diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index f2d0183c98..185b56ff88 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -42,17 +42,10 @@ static void r300_surface_fill(struct pipe_context* pipe, " dimensions %dx%d, color 0x%x\n", dest, x, y, w, h, color); -BEGIN_CS((caps->is_r500) ? 367 : 276); +BEGIN_CS((caps->is_r500) ? 367 : 322); R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; -/* Viewport setup */ -OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x43000000); -OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x43002000); -OUT_CS_REG(R300_SE_VPORT_YSCALE, 0xC3000000); -OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x43002000); -OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F000000); -OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x3F000000); /* Flush PVS. */ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0); @@ -71,7 +64,7 @@ OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x0); /* XXX magic number not in r300_reg */ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA); OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0); -OUT_CS_REG(R300_VAP_GB_VERT_CLIP_ADJ, 4); +OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4); OUT_CS_32F(1.0); OUT_CS_32F(1.0); OUT_CS_32F(1.0); @@ -149,9 +142,6 @@ OUT_CS_REG(R300_FG_DEPTH_SRC, 0x00000000); OUT_CS_REG(R300_RB3D_CCTL, 0x00000000); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); -r300_emit_blend_color_state(r300, &blend_color_clear_state); - -OUT_CS_REG(R300_RB3D_BLEND_COLOR, 0x00000000); /* XXX: Oh the wonderful unknown */ OUT_CS_REG_SEQ(0x4E54, 8); for (i = 0; i < 8; i++) @@ -184,16 +174,16 @@ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0xAAAAAAAA); OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_0, 0x00000003); OUT_CS_REG(R300_VAP_OUTPUT_VTX_FMT_1, 0x00000000); OUT_CS_REG(R300_TX_ENABLE, 0x0); -OUT_CS_REG(R300_SE_VPORT_XSCALE, 0x3F800000); -OUT_CS_REG(R300_SE_VPORT_XOFFSET, 0x00000000); -OUT_CS_REG(R300_SE_VPORT_YSCALE, 0x3F800000); -OUT_CS_REG(R300_SE_VPORT_YOFFSET, 0x00000000); -OUT_CS_REG(R300_SE_VPORT_ZSCALE, 0x3F800000); -OUT_CS_REG(R300_SE_VPORT_ZOFFSET, 0x00000000); +/* XXX viewport setup */ +OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6); +OUT_CS_32F(1.0); +OUT_CS_32F(0.0); +OUT_CS_32F(1.0); +OUT_CS_32F(0.0); +OUT_CS_32F(1.0); +OUT_CS_32F(0.0); OUT_CS_REG(R300_FG_ALPHA_FUNC, 0x00000000); -r300_emit_blend_state(r300, &blend_clear_state); - OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000); OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | ((w * 6) << R300_POINTSIZE_X_SHIFT)); @@ -262,22 +252,22 @@ if (caps->is_r500) { for (i = 0; i < 8; i++) { OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); } -} -OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); -OUT_CS_REG(R300_RS_INST_COUNT, 0x0); + OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_CS_REG(R300_RS_INST_COUNT, 0x0); -OUT_CS_REG(R300_RS_INST_0, 0x00004000); -OUT_CS_REG(R300_US_CONFIG, 0x00000000); -OUT_CS_REG(R300_US_PIXSIZE, 0x00000000); -OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00400000); -OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00050A80); -OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000); -OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); -OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x01000000); + OUT_CS_REG(R300_RS_INST_0, 0x00004000); + OUT_CS_REG(R300_US_CONFIG, 0x00000000); + OUT_CS_REG(R300_US_PIXSIZE, 0x00000000); + OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000); + OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000); + OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000); + OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000); + OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00400000); + OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00050A80); + OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000); + OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); + OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x01000000); +} /* XXX these magic numbers should be explained when * this becomes a cached state object */ OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | @@ -300,12 +290,23 @@ OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021); OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021); OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); +r300_emit_blend_state(r300, &blend_clear_state); +r300_emit_blend_color_state(r300, &blend_color_clear_state); r300_emit_dsa_state(r300, &dsa_clear_state); R300_PACIFY; +/* Flush colorbuffer and blend caches. */ +OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, + R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D | + R300_RB3D_DSTCACHE_CTLSTAT_DC_FINISH_SIGNAL); +OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, + R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | + R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); + OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); -//OUT_CS_REG(R300_RB3D_COLORPITCH0, 0x00C00100); +OUT_CS_REG(R300_RB3D_COLORPITCH0, (w >> 1) | R300_COLOR_TILE_ENABLE | + R300_COLOR_FORMAT_ARGB8888); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); /* XXX Packet3 */ OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); diff --git a/src/gallium/drivers/r300/r300_surface.h b/src/gallium/drivers/r300/r300_surface.h index 2b89698ca5..e1d53116a1 100644 --- a/src/gallium/drivers/r300/r300_surface.h +++ b/src/gallium/drivers/r300/r300_surface.h @@ -50,7 +50,7 @@ const struct r300_dsa_state dsa_clear_state = { .alpha_reference = 0x0, .z_buffer_control = 0x0, .z_stencil_control = 0x0, - .stencil_ref_mask = 0x0, + .stencil_ref_mask = R300_STENCILWRITEMASK_MASK, .z_buffer_top = R300_ZTOP_ENABLE, .stencil_ref_bf = 0x0, }; -- cgit v1.2.3 From 0c9d2bbb1296e7b5c812ce04f79aff2d8308907c Mon Sep 17 00:00:00 2001 From: Joakim Sindholt Date: Thu, 29 Jan 2009 20:24:34 +0100 Subject: r300: set up r5xx fragment shader; clear still broken --- src/gallium/drivers/r300/r300_emit.c | 6 +-- src/gallium/drivers/r300/r300_reg.h | 2 +- src/gallium/drivers/r300/r300_surface.c | 82 ++++++++++----------------------- 3 files changed, 29 insertions(+), 61 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index c5f08a2404..001aa02f41 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -62,11 +62,11 @@ void r300_emit_dsa_state(struct r300_context* r300, struct r300_screen* r300screen = (struct r300_screen*)r300->context.screen; CS_LOCALS(r300); - BEGIN_CS(r300screen->caps->is_r500 ? 12 : 8); + BEGIN_CS(r300screen->caps->is_r500 ? 8 : 8); OUT_CS_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); /* XXX figure out the r300 counterpart for this */ if (r300screen->caps->is_r500) { - OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); + /* OUT_CS_REG(R500_FG_ALPHA_VALUE, dsa->alpha_reference); */ } OUT_CS_REG_SEQ(R300_ZB_CNTL, 3); OUT_CS(dsa->z_buffer_control); @@ -74,7 +74,7 @@ void r300_emit_dsa_state(struct r300_context* r300, OUT_CS(dsa->stencil_ref_mask); OUT_CS_REG(R300_ZB_ZTOP, dsa->z_buffer_top); if (r300screen->caps->is_r500) { - OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); + /* OUT_CS_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); */ } END_CS; } diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index 9281e6656f..f01e15b8dd 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -3004,7 +3004,7 @@ enum { # define R500_US_CODE_RANGE_ADDR(x) (x << 0) # define R500_US_CODE_RANGE_SIZE(x) (x << 16) #define R500_US_CONFIG 0x4600 -# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 0) +# define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) #define R500_US_FC_ADDR_0 0xa000 # define R500_FC_BOOL_ADDR(x) (x << 0) # define R500_FC_INT_ADDR(x) (x << 8) diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 185b56ff88..0503d8faed 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -42,7 +42,7 @@ static void r300_surface_fill(struct pipe_context* pipe, " dimensions %dx%d, color 0x%x\n", dest, x, y, w, h, color); -BEGIN_CS((caps->is_r500) ? 367 : 322); +BEGIN_CS((caps->is_r500) ? 300 : 322); R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; @@ -122,17 +122,6 @@ OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); OUT_CS_REG(R300_US_W_FMT, 0x00000001); -OUT_CS_REG(R300_US_CONFIG, 0x00000000); -OUT_CS_REG(R300_US_PIXSIZE, 0x00000000); -OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000); -OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00000000); -OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00000000); -OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x00000000); -OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00000000); -OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x00000000); OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002); OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000); OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000); @@ -149,9 +138,6 @@ for (i = 0; i < 8; i++) OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000); OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x00000000); OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFFFFFFFF); -OUT_CS_REG(R300_ZB_CNTL, 0x00000010); -OUT_CS_REG(R300_ZB_ZSTENCILCNTL, 0x00038038); -OUT_CS_REG(R300_ZB_STENCILREFMASK, 0x00FFFF00); OUT_CS_REG(R300_ZB_FORMAT, 0x00000002); OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, 0x00000003); OUT_CS_REG(R300_ZB_BW_CNTL, 0x00000000); @@ -182,7 +168,6 @@ OUT_CS_32F(1.0); OUT_CS_32F(0.0); OUT_CS_32F(1.0); OUT_CS_32F(0.0); -OUT_CS_REG(R300_FG_ALPHA_FUNC, 0x00000000); OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000); OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | @@ -200,53 +185,36 @@ if (caps->is_r500) { } R300_PACIFY; OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); + OUT_CS_REG(R500_US_PIXSIZE, 0x00000000); OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(1)); OUT_CS_REG(R500_US_CODE_RANGE, R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(1)); OUT_CS_REG(R500_US_CODE_OFFSET, R500_US_CODE_OFFSET_ADDR(0)); R300_PACIFY; - OUT_CS_REG(R500_US_CMN_INST_0, - R500_INST_TYPE_OUT | - R500_INST_TEX_SEM_WAIT | - R500_INST_LAST | - R500_INST_RGB_OMASK_R | - R500_INST_RGB_OMASK_G | - R500_INST_RGB_OMASK_B | - R500_INST_ALPHA_OMASK | - R500_INST_RGB_CLAMP | - R500_INST_ALPHA_CLAMP); - OUT_CS_REG(R500_US_ALU_RGB_ADDR_0, - R500_RGB_ADDR0(0) | - R500_RGB_ADDR1(0) | - R500_RGB_ADDR1_CONST | - R500_RGB_ADDR2(0) | - R500_RGB_ADDR2_CONST); - OUT_CS_REG(R500_US_ALU_ALPHA_ADDR_0, - R500_ALPHA_ADDR0(0) | - R500_ALPHA_ADDR1(0) | - R500_ALPHA_ADDR1_CONST | - R500_ALPHA_ADDR2(0) | - R500_ALPHA_ADDR2_CONST); - OUT_CS_REG(R500_US_ALU_RGB_INST_0, - R500_ALU_RGB_SEL_A_SRC0 | - R500_ALU_RGB_R_SWIZ_A_R | - R500_ALU_RGB_G_SWIZ_A_G | - R500_ALU_RGB_B_SWIZ_A_B | - R500_ALU_RGB_SEL_B_SRC0 | - R500_ALU_RGB_R_SWIZ_B_R | - R500_ALU_RGB_B_SWIZ_B_G | - R500_ALU_RGB_G_SWIZ_B_B); - OUT_CS_REG(R500_US_ALU_ALPHA_INST_0, - R500_ALPHA_OP_CMP | - R500_ALPHA_SWIZ_A_A | - R500_ALPHA_SWIZ_B_A); - OUT_CS_REG(R500_US_ALU_RGBA_INST_0, - R500_ALU_RGBA_OP_CMP | - R500_ALU_RGBA_R_SWIZ_0 | - R500_ALU_RGBA_G_SWIZ_0 | - R500_ALU_RGBA_B_SWIZ_0 | - R500_ALU_RGBA_A_SWIZ_0); + OUT_CS_REG(R500_GA_US_VECTOR_INDEX, + 0 | R500_GA_US_VECTOR_INDEX_TYPE_INSTR); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, + R500_INST_TYPE_OUT | R500_INST_TEX_SEM_WAIT | R500_INST_LAST | + R500_INST_RGB_OMASK_R | R500_INST_RGB_OMASK_G | R500_INST_RGB_OMASK_B | + R500_INST_ALPHA_OMASK | R500_INST_RGB_CLAMP | R500_INST_ALPHA_CLAMP); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, + R500_RGB_ADDR0(0) | R500_RGB_ADDR1(0) | R500_RGB_ADDR1_CONST | + R500_RGB_ADDR2(0) | R500_RGB_ADDR2_CONST); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, + R500_ALPHA_ADDR0(0) | R500_ALPHA_ADDR1(0) | R500_ALPHA_ADDR1_CONST | + R500_ALPHA_ADDR2(0) | R500_ALPHA_ADDR2_CONST); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, + R500_ALU_RGB_SEL_A_SRC0 | R500_ALU_RGB_R_SWIZ_A_R | + R500_ALU_RGB_G_SWIZ_A_G | R500_ALU_RGB_B_SWIZ_A_B | + R500_ALU_RGB_SEL_B_SRC0 | R500_ALU_RGB_R_SWIZ_B_R | + R500_ALU_RGB_B_SWIZ_B_G | R500_ALU_RGB_G_SWIZ_B_B); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, + R500_ALPHA_OP_CMP | R500_ALPHA_SWIZ_A_A | R500_ALPHA_SWIZ_B_A); + OUT_CS_REG(R500_GA_US_VECTOR_DATA, + R500_ALU_RGBA_OP_CMP | R500_ALU_RGBA_R_SWIZ_0 | + R500_ALU_RGBA_G_SWIZ_0 | R500_ALU_RGBA_B_SWIZ_0 | + R500_ALU_RGBA_A_SWIZ_0); } else { OUT_CS_REG_SEQ(R300_RS_IP_0, 8); for (i = 0; i < 8; i++) { -- cgit v1.2.3 From 09b107058d11ac2362ea296556b68331ff04f193 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 29 Jan 2009 12:27:00 -0800 Subject: r300: Try to fix up RS a bit more. --- src/gallium/drivers/r300/r300_surface.c | 41 ++++++++++++++++++++------------- 1 file changed, 25 insertions(+), 16 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 0503d8faed..cc6b4f3d79 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -90,6 +90,7 @@ OUT_CS_REG(R300_GA_TRIANGLE_STIPPLE, 0x5 | /* XXX should this be related to the actual point size? */ OUT_CS_REG(R300_GA_POINT_MINMAX, 0x6 | (0x1800 << R300_GA_POINT_MINMAX_MAX_SHIFT)); +/* XXX this big chunk should be refactored into rs_state */ OUT_CS_REG(R300_GA_LINE_CNTL, 0x00030006); OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, 0x3BAAAAAB); OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, 0x00000000); @@ -175,15 +176,20 @@ OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | /* XXX RS block and fp setup */ if (caps->is_r500) { - OUT_CS_REG_SEQ(R500_RS_IP_0, 16); - for (i = 0; i < 16; i++) { + OUT_CS_REG_SEQ(R500_RS_IP_0, 8); + for (i = 0; i < 8; i++) { /* I like the operator macros more than the shift macros... */ OUT_CS((R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_S_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_T_SHIFT) | (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT)); } - R300_PACIFY; + /* XXX */ + OUT_CS_REG_SEQ(R300_RS_COUNT, 2); + OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_CS(0x0); + OUT_CS_REG(R500_RS_INST_0, R500_RS_INST_COL_CN_WRITE); + OUT_CS_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); OUT_CS_REG(R500_US_PIXSIZE, 0x00000000); OUT_CS_REG(R500_US_CODE_ADDR, R500_US_CODE_START_ADDR(0) | @@ -220,21 +226,24 @@ if (caps->is_r500) { for (i = 0; i < 8; i++) { OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); } - OUT_CS_REG(R300_RS_COUNT, (1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); - OUT_CS_REG(R300_RS_INST_COUNT, 0x0); + /* XXX */ + OUT_CS_REG_SEQ(R300_RS_COUNT, 2); + OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); + OUT_CS(0x0); + OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE); - OUT_CS_REG(R300_RS_INST_0, 0x00004000); - OUT_CS_REG(R300_US_CONFIG, 0x00000000); - OUT_CS_REG(R300_US_PIXSIZE, 0x00000000); - OUT_CS_REG(R300_US_CODE_OFFSET, 0x00000000); - OUT_CS_REG(R300_US_CODE_ADDR_0, 0x00000000); - OUT_CS_REG(R300_US_CODE_ADDR_1, 0x00000000); - OUT_CS_REG(R300_US_CODE_ADDR_2, 0x00000000); - OUT_CS_REG(R300_US_CODE_ADDR_3, 0x00400000); - OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x00050A80); + /* XXX magic numbers */ + OUT_CS_REG(R300_US_CONFIG, 0x0); + OUT_CS_REG(R300_US_PIXSIZE, 0x0); + OUT_CS_REG(R300_US_CODE_OFFSET, 0x0); + OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0); + OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0); + OUT_CS_REG(R300_US_CODE_ADDR_2, 0x0); + OUT_CS_REG(R300_US_CODE_ADDR_3, 0x400000); + OUT_CS_REG(R300_US_ALU_RGB_INST_0, 0x50A80); OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000); - OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x00040889); - OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x01000000); + OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x40889); + OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1000000); } /* XXX these magic numbers should be explained when * this becomes a cached state object */ -- cgit v1.2.3 From e14a10691e1a0ca6b453faf705f94494113962de Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 29 Jan 2009 13:23:11 -0800 Subject: r300: Add cleaned-up clear fallback, sort more regs. --- src/gallium/drivers/r300/r300_reg.h | 10 +++++----- src/gallium/drivers/r300/r300_surface.c | 35 ++++++++++++++++++++++----------- 2 files changed, 28 insertions(+), 17 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index f01e15b8dd..dbd0cc28e2 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -1233,11 +1233,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_RS_INST_0 0x4330 #define R300_RS_INST_1 0x4334 #define R300_RS_INST_2 0x4338 -#define R300_RS_INST_3 0x433C /* GUESS */ -#define R300_RS_INST_4 0x4340 /* GUESS */ -#define R300_RS_INST_5 0x4344 /* GUESS */ -#define R300_RS_INST_6 0x4348 /* GUESS */ -#define R300_RS_INST_7 0x434C /* GUESS */ +#define R300_RS_INST_3 0x433C +#define R300_RS_INST_4 0x4340 +#define R300_RS_INST_5 0x4344 +#define R300_RS_INST_6 0x4348 +#define R300_RS_INST_7 0x434C # define R300_RS_INST_TEX_ID(x) ((x) << 0) # define R300_RS_INST_TEX_CN_WRITE (1 << 3) # define R300_RS_INST_TEX_ADDR_SHIFT 6 diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index cc6b4f3d79..3ffaee54b6 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -42,6 +42,16 @@ static void r300_surface_fill(struct pipe_context* pipe, " dimensions %dx%d, color 0x%x\n", dest, x, y, w, h, color); + /* Fallback? */ + if (0) { + debug_printf("r300: Falling back on surface clear..."); + void* map = pipe->screen->surface_map(pipe->screen, dest, + PIPE_BUFFER_USAGE_CPU_WRITE); + pipe_fill_rect(map, &dest->block, &dest->stride, x, y, w, h, color); + pipe->screen->surface_unmap(pipe->screen, dest); + return; + } + BEGIN_CS((caps->is_r500) ? 300 : 322); R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); @@ -117,12 +127,6 @@ OUT_CS_REG(R300_SU_DEPTH_OFFSET, 0x00000000); OUT_CS_REG(R300_SC_HYPERZ, 0x0000001C); OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525); OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); -OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4); -OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R); -OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); -OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); -OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_US_OUT_FMT_UNUSED); -OUT_CS_REG(R300_US_W_FMT, 0x00000001); OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000002); OUT_CS_REG(R300_FG_FOG_COLOR_R, 0x00000000); OUT_CS_REG(R300_FG_FOG_COLOR_G, 0x00000000); @@ -164,9 +168,9 @@ OUT_CS_REG(R300_TX_ENABLE, 0x0); /* XXX viewport setup */ OUT_CS_REG_SEQ(R300_SE_VPORT_XSCALE, 6); OUT_CS_32F(1.0); -OUT_CS_32F(0.0); +OUT_CS_32F((float)x); OUT_CS_32F(1.0); -OUT_CS_32F(0.0); +OUT_CS_32F((float)y); OUT_CS_32F(1.0); OUT_CS_32F(0.0); @@ -224,17 +228,18 @@ if (caps->is_r500) { } else { OUT_CS_REG_SEQ(R300_RS_IP_0, 8); for (i = 0; i < 8; i++) { - OUT_CS(R300_RS_SEL_T(1) | R300_RS_SEL_R(2) | R300_RS_SEL_Q(3)); + OUT_CS(R300_RS_SEL_T(R300_RS_SEL_K0) | + R300_RS_SEL_R(R300_RS_SEL_K0) | R300_RS_SEL_Q(R300_RS_SEL_K1)); } /* XXX */ OUT_CS_REG_SEQ(R300_RS_COUNT, 2); OUT_CS((1 << R300_IC_COUNT_SHIFT) | R300_HIRES_EN); - OUT_CS(0x0); + OUT_CS(1); OUT_CS_REG(R300_RS_INST_0, R300_RS_INST_COL_CN_WRITE); /* XXX magic numbers */ - OUT_CS_REG(R300_US_CONFIG, 0x0); - OUT_CS_REG(R300_US_PIXSIZE, 0x0); + OUT_CS_REG(R300_US_CONFIG, 0); + OUT_CS_REG(R300_US_PIXSIZE, 2); OUT_CS_REG(R300_US_CODE_OFFSET, 0x0); OUT_CS_REG(R300_US_CODE_ADDR_0, 0x0); OUT_CS_REG(R300_US_CODE_ADDR_1, 0x0); @@ -244,6 +249,12 @@ if (caps->is_r500) { OUT_CS_REG(R300_US_ALU_RGB_ADDR_0, 0x1C000000); OUT_CS_REG(R300_US_ALU_ALPHA_INST_0, 0x40889); OUT_CS_REG(R300_US_ALU_ALPHA_ADDR_0, 0x1000000); + OUT_CS_REG_SEQ(R300_US_OUT_FMT_0, 4); + OUT_CS(R300_C0_SEL_B | R300_C1_SEL_G | R300_C2_SEL_R | R300_C3_SEL_A); + OUT_CS(R300_US_OUT_FMT_UNUSED); + OUT_CS(R300_US_OUT_FMT_UNUSED); + OUT_CS(R300_US_OUT_FMT_UNUSED); + OUT_CS_REG(R300_US_W_FMT, R300_W_FMT_W0); } /* XXX these magic numbers should be explained when * this becomes a cached state object */ -- cgit v1.2.3 From 8c8bdcde6d9eb1cda7bf268cd75ca7676e220075 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 29 Jan 2009 15:50:46 -0800 Subject: r300: Add line stipple state to rs_state. --- src/gallium/drivers/r300/r300_context.h | 10 ++++++---- src/gallium/drivers/r300/r300_state.c | 12 +++++++++--- 2 files changed, 15 insertions(+), 7 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index f246c57f48..13982784ff 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -61,12 +61,14 @@ struct r300_fs_state { struct r300_rs_state { uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ - uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */ - uint32_t depth_offset_front; /* R300_SU_POLY_OFFSET_FRONT_OFFSET: 0x42a8 */ - uint32_t depth_scale_back; /* R300_SU_POLY_OFFSET_BACK_SCALE: 0x42ac */ - uint32_t depth_offset_back; /* R300_SU_POLY_OFFSET_BACK_OFFSET: 0x42b0 */ + uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */ + uint32_t depth_offset_front;/* R300_SU_POLY_OFFSET_FRONT_OFFSET: 0x42a8 */ + uint32_t depth_scale_back; /* R300_SU_POLY_OFFSET_BACK_SCALE: 0x42ac */ + uint32_t depth_offset_back; /* R300_SU_POLY_OFFSET_BACK_OFFSET: 0x42b0 */ uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ + uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ + uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ }; struct r300_sampler_state { diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 907ebe5c75..ee947feb5a 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -440,9 +440,6 @@ struct pipe_rasterizer_state unsigned point_size_per_vertex:1; /**< size computed in vertex shader */ unsigned multisample:1; /* XXX maybe more ms state in future */ unsigned line_smooth:1; - unsigned line_stipple_enable:1; - unsigned line_stipple_factor:8; /**< [1..256] actually */ - unsigned line_stipple_pattern:16; unsigned line_last_pixel:1; unsigned bypass_clipping:1; unsigned bypass_vs:1; /**< Skip the vertex shader. Note that the shader is @@ -504,6 +501,15 @@ static void* r300_create_rs_state(struct pipe_context* pipe, pack_float_32(state->offset_scale); } + if (state->line_stipple_enable) { + rs->line_stipple_config = + R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | + (pack_float_32((float)state->line_stipple_factor) & + R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); + /* XXX this might need to be scaled up */ + rs->line_stipple_value = state->line_stipple_pattern; + } + /* XXX this is part of HW TCL */ /* XXX endian control */ rs->vap_control_status = R300_VAP_TCL_BYPASS; -- cgit v1.2.3 From 70b508bffba723b58817e375447c1695d9d5602b Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 30 Jan 2009 01:24:03 -0800 Subject: r300: Split rs_state emit into its own function. --- src/gallium/drivers/r300/r300_emit.c | 29 ++++++++++++++++++++--------- src/gallium/drivers/r300/r300_emit.h | 4 +++- 2 files changed, 23 insertions(+), 10 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index 001aa02f41..de5719db8d 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -79,6 +79,25 @@ void r300_emit_dsa_state(struct r300_context* r300, END_CS; } +void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs) +{ + struct r300_screen* r300screen = + (struct r300_screen*)r300->context.screen; + CS_LOCALS(r300); + BEGIN_CS(14); + OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status); + OUT_CS_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 6); + OUT_CS(rs->depth_scale_front); + OUT_CS(rs->depth_offset_front); + OUT_CS(rs->depth_scale_back); + OUT_CS(rs->depth_offset_back); + OUT_CS(rs->polygon_offset_enable); + OUT_CS(rs->cull_mode); + OUT_CS_REG(R300_GA_LINE_STIPPLE_CONFIG, rs->line_stipple_config); + OUT_CS_REG(R300_GA_LINE_STIPPLE_VALUE, rs->line_stipple_value); + END_CS; +} + static void r300_emit_dirty_state(struct r300_context* r300) { struct r300_screen* r300screen = @@ -104,15 +123,7 @@ static void r300_emit_dirty_state(struct r300_context* r300) } if (r300->dirty_state & R300_NEW_RASTERIZER) { - struct r300_rs_state* rs = r300->rs_state; - OUT_CS_REG(R300_VAP_CNTL_STATUS, rs->vap_control_status); - /* XXX next six are contiguous regs */ - OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_SCALE, rs->depth_scale_front); - OUT_CS_REG(R300_SU_POLY_OFFSET_FRONT_OFFSET, rs->depth_offset_front); - OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_SCALE, rs->depth_scale_back); - OUT_CS_REG(R300_SU_POLY_OFFSET_BACK_OFFSET, rs->depth_offset_back); - OUT_CS_REG(R300_SU_POLY_OFFSET_ENABLE, rs->polygon_offset_enable); - OUT_CS_REG(R300_SU_CULL_MODE, rs->cull_mode); + r300_emit_rs_state(r300, r300->rs_state); } if (r300->dirty_state & R300_NEW_SCISSOR) { diff --git a/src/gallium/drivers/r300/r300_emit.h b/src/gallium/drivers/r300/r300_emit.h index 98287bc1f3..b6e69386f9 100644 --- a/src/gallium/drivers/r300/r300_emit.h +++ b/src/gallium/drivers/r300/r300_emit.h @@ -31,4 +31,6 @@ void r300_emit_blend_color_state(struct r300_context* r300, struct r300_blend_color_state* bc); void r300_emit_dsa_state(struct r300_context* r300, - struct r300_dsa_state* dsa); + struct r300_dsa_state* dsa); + +void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs); -- cgit v1.2.3 From e6e6b493b6123df675d5222b0e78087a370aea01 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 30 Jan 2009 02:17:48 -0800 Subject: r300: Add more rs_state, fix indents on dsa_state. --- src/gallium/drivers/r300/r300_context.h | 2 ++ src/gallium/drivers/r300/r300_state.c | 51 ++++++++++++++++++--------------- 2 files changed, 30 insertions(+), 23 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 13982784ff..0cb0ec20d5 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -61,6 +61,8 @@ struct r300_fs_state { struct r300_rs_state { uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ + uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ + uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ uint32_t depth_scale_front; /* R300_SU_POLY_OFFSET_FRONT_SCALE: 0x42a4 */ uint32_t depth_offset_front;/* R300_SU_POLY_OFFSET_FRONT_OFFSET: 0x42a8 */ uint32_t depth_scale_back; /* R300_SU_POLY_OFFSET_BACK_SCALE: 0x42ac */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index ee947feb5a..d81aee94e3 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -307,8 +307,8 @@ static void* } dsa->z_stencil_control |= - (translate_depth_stencil_function(state->depth.func) << - R300_Z_FUNC_SHIFT); + (translate_depth_stencil_function(state->depth.func) << + R300_Z_FUNC_SHIFT); } /* Stencil buffer setup. */ @@ -331,25 +331,25 @@ static void* if (state->stencil[1].enabled) { dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; dsa->z_stencil_control |= - (translate_depth_stencil_function(state->stencil[1].func) << - R300_S_BACK_FUNC_SHIFT) | - (translate_stencil_op(state->stencil[1].fail_op) << - R300_S_BACK_SFAIL_OP_SHIFT) | - (translate_stencil_op(state->stencil[1].zpass_op) << - R300_S_BACK_ZPASS_OP_SHIFT) | - (translate_stencil_op(state->stencil[1].zfail_op) << - R300_S_BACK_ZFAIL_OP_SHIFT); + (translate_depth_stencil_function(state->stencil[1].func) << + R300_S_BACK_FUNC_SHIFT) | + (translate_stencil_op(state->stencil[1].fail_op) << + R300_S_BACK_SFAIL_OP_SHIFT) | + (translate_stencil_op(state->stencil[1].zpass_op) << + R300_S_BACK_ZPASS_OP_SHIFT) | + (translate_stencil_op(state->stencil[1].zfail_op) << + R300_S_BACK_ZFAIL_OP_SHIFT); dsa->stencil_ref_bf = (state->stencil[1].ref_value) | - (state->stencil[1].value_mask << R300_STENCILMASK_SHIFT) | - (state->stencil[1].write_mask << R300_STENCILWRITEMASK_SHIFT); + (state->stencil[1].value_mask << R300_STENCILMASK_SHIFT) | + (state->stencil[1].write_mask << R300_STENCILWRITEMASK_SHIFT); } } /* Alpha test setup. */ if (state->alpha.enabled) { dsa->alpha_function = translate_alpha_function(state->alpha.func) | - R300_FG_ALPHA_FUNC_ENABLE; + R300_FG_ALPHA_FUNC_ENABLE; dsa->alpha_reference = CLAMP(state->alpha.ref * 1023.0f, 0, 1023); } else { dsa->z_buffer_top = R300_ZTOP_ENABLE; @@ -437,7 +437,6 @@ struct pipe_rasterizer_state unsigned poly_stipple_enable:1; unsigned point_smooth:1; unsigned point_sprite:1; - unsigned point_size_per_vertex:1; /**< size computed in vertex shader */ unsigned multisample:1; /* XXX maybe more ms state in future */ unsigned line_smooth:1; unsigned line_last_pixel:1; @@ -447,14 +446,14 @@ struct pipe_rasterizer_state unsigned origin_lower_left:1; /**< Is (0,0) the lower-left corner? */ unsigned flatshade_first:1; /**< take color attribute from the first vertex of a primitive */ unsigned gl_rasterization_rules:1; /**< enable tweaks for GL rasterization? */ - - float line_width; - float point_size; /**< used when no per-vertex size */ - float point_size_min; /* XXX - temporary, will go away */ - float point_size_max; /* XXX - temporary, will go away */ ubyte sprite_coord_mode[PIPE_MAX_SHADER_OUTPUTS]; /**< PIPE_SPRITE_COORD_ */ }; #endif + +static INLINE int pack_float_16_6x(float f) { + return ((int)(f * 6.0) & 0xffff); +} + /* Create a new rasterizer state based on the CSO rasterizer state. * * This is a very large chunk of state, and covers most of the graphics @@ -467,6 +466,16 @@ static void* r300_create_rs_state(struct pipe_context* pipe, { struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); + /* XXX this is part of HW TCL */ + /* XXX endian control */ + rs->vap_control_status = R300_VAP_TCL_BYPASS; + + rs->point_size = pack_float_16_6x(state->point_size) | + (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); + + rs->line_control = pack_float_16_6x(state->line_width) | + R300_GA_LINE_CNTL_END_TYPE_COMP; + /* Radeons don't think in "CW/CCW", they think in "front/back". */ if (state->front_winding == PIPE_WINDING_CW) { rs->cull_mode = R300_FRONT_FACE_CW; @@ -510,10 +519,6 @@ static void* r300_create_rs_state(struct pipe_context* pipe, rs->line_stipple_value = state->line_stipple_pattern; } - /* XXX this is part of HW TCL */ - /* XXX endian control */ - rs->vap_control_status = R300_VAP_TCL_BYPASS; - return (void*)rs; } -- cgit v1.2.3 From 38f610e5360a2beb46f92e75942745cfbfbac22a Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sun, 1 Feb 2009 23:43:30 -0800 Subject: r300: Add u_simple_screen support. --- src/gallium/drivers/r300/r300_screen.c | 1 + src/gallium/drivers/r300/r300_screen.h | 1 + 2 files changed, 2 insertions(+) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 607dfe911c..99dcf38f43 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -264,6 +264,7 @@ struct pipe_screen* r300_create_screen(struct pipe_winsys* winsys, r300screen->screen.surface_unmap = r300_surface_unmap; r300_init_screen_texture_functions(&r300screen->screen); + u_simple_screen_init(&r300screen->screen); return &r300screen->screen; } diff --git a/src/gallium/drivers/r300/r300_screen.h b/src/gallium/drivers/r300/r300_screen.h index b45ce5e8c6..2e25f61dbf 100644 --- a/src/gallium/drivers/r300/r300_screen.h +++ b/src/gallium/drivers/r300/r300_screen.h @@ -26,6 +26,7 @@ #include "pipe/p_inlines.h" #include "pipe/p_screen.h" #include "util/u_memory.h" +#include "util/u_simple_screen.h" #include "r300_chipset.h" #include "r300_texture.h" -- cgit v1.2.3 From ce6710e369d3b5c512ba8b315efc863fd41de734 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sun, 1 Feb 2009 23:58:16 -0800 Subject: r300: Clean up after rebase. Fix a couple struct members, clear up a few texture lines. --- src/gallium/drivers/r300/r300_state.c | 11 ++++++----- src/gallium/drivers/r300/r300_texture.c | 8 ++++---- 2 files changed, 10 insertions(+), 9 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index d81aee94e3..96fdce903e 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -325,8 +325,8 @@ static void* R300_S_FRONT_ZFAIL_OP_SHIFT); dsa->stencil_ref_mask = (state->stencil[0].ref_value) | - (state->stencil[0].value_mask << R300_STENCILMASK_SHIFT) | - (state->stencil[0].write_mask << R300_STENCILWRITEMASK_SHIFT); + (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | + (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); if (state->stencil[1].enabled) { dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; @@ -341,8 +341,8 @@ static void* R300_S_BACK_ZFAIL_OP_SHIFT); dsa->stencil_ref_bf = (state->stencil[1].ref_value) | - (state->stencil[1].value_mask << R300_STENCILMASK_SHIFT) | - (state->stencil[1].write_mask << R300_STENCILWRITEMASK_SHIFT); + (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | + (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); } } @@ -350,7 +350,8 @@ static void* if (state->alpha.enabled) { dsa->alpha_function = translate_alpha_function(state->alpha.func) | R300_FG_ALPHA_FUNC_ENABLE; - dsa->alpha_reference = CLAMP(state->alpha.ref * 1023.0f, 0, 1023); + dsa->alpha_reference = CLAMP(state->alpha.ref_value * 1023.0f, + 0, 1023); } else { dsa->z_buffer_top = R300_ZTOP_ENABLE; } diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index eb7c9d06f5..ae2d525d78 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -58,7 +58,7 @@ static struct pipe_texture* r300_texture_create(struct pipe_screen* screen, const struct pipe_texture* template) { - struct r300_screen* r300screen = r300_screen(screen); + /* XXX struct r300_screen* r300screen = r300_screen(screen); */ struct r300_texture* tex = CALLOC_STRUCT(r300_texture); @@ -72,9 +72,9 @@ static struct pipe_texture* r300_setup_miptree(tex); - tex->buffer = screen->winsys->buffer_create(screen->winsys, 32, - PIPE_BUFFER_USAGE_PIXEL, - tex->size); + tex->buffer = screen->buffer_create(screen->winsys, 32, + PIPE_BUFFER_USAGE_PIXEL, + tex->size); if (!tex->buffer) { FREE(tex); -- cgit v1.2.3 From a2416e3d7ecb2fcf18d93a08bc3cc3639ed97b39 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 2 Feb 2009 14:42:04 -0800 Subject: r300, amd: Oops, a couple more API changes. Somehow I forgot to commit these. --- src/gallium/drivers/r300/r300_texture.c | 2 +- src/gallium/winsys/drm/amd/amd_buffer.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index ae2d525d78..537425c1e2 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -72,7 +72,7 @@ static struct pipe_texture* r300_setup_miptree(tex); - tex->buffer = screen->buffer_create(screen->winsys, 32, + tex->buffer = screen->buffer_create(screen, 32, PIPE_BUFFER_USAGE_PIXEL, tex->size); diff --git a/src/gallium/winsys/drm/amd/amd_buffer.c b/src/gallium/winsys/drm/amd/amd_buffer.c index fb7c6f33ed..4b831c7fcc 100644 --- a/src/gallium/winsys/drm/amd/amd_buffer.c +++ b/src/gallium/winsys/drm/amd/amd_buffer.c @@ -231,7 +231,7 @@ struct pipe_surface *amd_surface_from_handle(struct amd_context *amd_context, pt = pipe_screen->texture_blanket(pipe_screen, &tmpl, &pitch, pb); if (pt == NULL) { - winsys_buffer_reference(pipe_winsys, &pb, NULL); + pipe_buffer_reference(pipe_screen, &pb, NULL); } ps = pipe_screen->get_tex_surface(pipe_screen, pt, 0, 0, 0, PIPE_BUFFER_USAGE_GPU_WRITE); -- cgit v1.2.3 From 33d798c4eab57293336082c7d011aa27af693bbb Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 2 Feb 2009 15:39:30 -0800 Subject: r300: Move some registers around. This fixes r500 hangs. --- src/gallium/drivers/r300/r300_cs_inlines.h | 2 ++ src/gallium/drivers/r300/r300_surface.c | 11 ++++------- 2 files changed, 6 insertions(+), 7 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs_inlines.h b/src/gallium/drivers/r300/r300_cs_inlines.h index aa0e647008..71e6623699 100644 --- a/src/gallium/drivers/r300/r300_cs_inlines.h +++ b/src/gallium/drivers/r300/r300_cs_inlines.h @@ -27,8 +27,10 @@ #ifdef R300_CS_H #define R300_PACIFY do { \ + OUT_CS_REG(R300_SC_SCREENDOOR, 0x0); \ OUT_CS_REG(RADEON_WAIT_UNTIL, (1 << 15) | (1 << 17) | \ (1 << 18) | (1 << 31)); \ + OUT_CS_REG(R300_SC_SCREENDOOR, 0xffffff); \ } while (0) diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 3ffaee54b6..4bccdbca29 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -151,9 +151,7 @@ OUT_CS_REG(0x4F30, 0x00000000); OUT_CS_REG(0x4F34, 0x00000000); OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000); OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000); -OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000); R300_PACIFY; -OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x21030003); OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000); OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688); @@ -263,9 +261,7 @@ OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000); OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000); OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001); -OUT_CS_REG(R300_SC_SCREENDOOR, 0x00000000); R300_PACIFY; -OUT_CS_REG(R300_SC_SCREENDOOR, 0x00FFFFFF); /* XXX translate these back into normal instructions */ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0); @@ -293,7 +289,8 @@ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); -OUT_CS_REG(R300_RB3D_COLORPITCH0, (w >> 1) | R300_COLOR_TILE_ENABLE | +/* XXX this should not be so rigid */ +OUT_CS_REG(R300_RB3D_COLORPITCH0, (w / 4) | R300_COLOR_TILE_ENABLE | R300_COLOR_FORMAT_ARGB8888); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); /* XXX Packet3 */ @@ -311,8 +308,8 @@ OUT_CS_32F(b); OUT_CS_32F(1.0); /* XXX figure out why this is 0xA and not 0x2 */ -/* XXX OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); -OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, +OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, 0xA); +/* XXX OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE | R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); */ R300_PACIFY; -- cgit v1.2.3 From fa3c59136e9dd788ee7d3689b6cb89dd27040a9e Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 2 Feb 2009 16:13:41 -0800 Subject: r300: Take care of some XXXes. --- src/gallium/drivers/r300/r300_chipset.c | 3 ++- src/gallium/drivers/r300/r300_screen.c | 11 +++++------ src/gallium/drivers/r300/r300_winsys.h | 1 - 3 files changed, 7 insertions(+), 8 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index 4c84be26ef..b0a7fe7d21 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -337,7 +337,8 @@ void r300_parse_chipset(struct r300_capabilities* caps) break; default: - /* XXX not an r300?! */ + debug_printf("r300: Warning: Unknown chipset 0x%x\n", + caps->pci_id); break; } diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 99dcf38f43..8e77e0ddd9 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -81,12 +81,11 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) /* IN THEORY */ return 0; case PIPE_CAP_TWO_SIDED_STENCIL: - /* IN THEORY */ - /* if (r300screen->is_r500) { - * return 1; - * } else { - * return 0; - * } */ + if (r300screen->is_r500) { + return 1; + } else { + return 0; + } return 0; case PIPE_CAP_GLSL: /* IN THEORY */ diff --git a/src/gallium/drivers/r300/r300_winsys.h b/src/gallium/drivers/r300/r300_winsys.h index 867d65b7de..5a3a212892 100644 --- a/src/gallium/drivers/r300/r300_winsys.h +++ b/src/gallium/drivers/r300/r300_winsys.h @@ -64,7 +64,6 @@ struct r300_winsys { int line); /* Write a dword to the command buffer. */ - /* XXX is this an okay name for this handle? */ void (*write_cs_dword)(struct radeon_cs* cs, uint32_t dword); /* Write a relocated dword to the command buffer. */ -- cgit v1.2.3 From 3aabfa46083daf60859bb26b65568de4cf40915f Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 2 Feb 2009 16:39:43 -0800 Subject: r300: Clear up XXX in r300_state. --- src/gallium/drivers/r300/r300_state.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 96fdce903e..37770cd5c6 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -56,7 +56,7 @@ static uint32_t translate_blend_function(int blend_func) { case PIPE_BLEND_MAX: return R300_COMB_FCN_MAX; default: - /* XXX should be unreachable, handle this */ + debug_printf("r300: Unknown blend function %d\n", blend_func); break; } return 0; @@ -102,7 +102,7 @@ static uint32_t translate_blend_factor(int blend_fact) { case PIPE_BLENDFACTOR_INV_SRC1_COLOR: case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: */ default: - /* XXX the mythical 0x16 blend factor! */ + debug_printf("r300: Unknown blend factor %d\n", blend_fact); break; } return 0; @@ -231,7 +231,8 @@ static uint32_t translate_depth_stencil_function(int zs_func) { case PIPE_FUNC_ALWAYS: return R300_ZS_ALWAYS; default: - /* XXX shouldn't be reachable */ + debug_printf("r300: Unknown depth/stencil function %d\n", + zs_func); break; } return 0; @@ -256,7 +257,7 @@ static uint32_t translate_stencil_op(int s_op) { case PIPE_STENCIL_OP_INVERT: return R300_ZS_INVERT; default: - /* XXX shouldn't be reachable */ + debug_printf("r300: Unknown stencil op %d", s_op); break; } return 0; @@ -281,7 +282,7 @@ static uint32_t translate_alpha_function(int alpha_func) { case PIPE_FUNC_ALWAYS: return R300_FG_ALPHA_FUNC_ALWAYS; default: - /* XXX shouldn't be reachable */ + debug_printf("r300: Unknown alpha function %d", alpha_func); break; } return 0; @@ -557,7 +558,7 @@ static uint32_t translate_wrap(int wrap) { case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED; default: - /* XXX handle this? */ + debug_printf("r300: Unknown texture wrap %d", wrap); return 0; } } @@ -572,7 +573,7 @@ static uint32_t translate_tex_filters(int min, int mag, int mip) { case PIPE_TEX_FILTER_ANISO: retval |= R300_TX_MIN_FILTER_ANISO; default: - /* XXX WTF?! */ + debug_printf("r300: Unknown texture filter %d", min); break; } switch (mag) { @@ -583,7 +584,7 @@ static uint32_t translate_tex_filters(int min, int mag, int mip) { case PIPE_TEX_FILTER_ANISO: retval |= R300_TX_MAG_FILTER_ANISO; default: - /* XXX WTF?! */ + debug_printf("r300: Unknown texture filter %d", mag); break; } switch (mip) { @@ -594,7 +595,7 @@ static uint32_t translate_tex_filters(int min, int mag, int mip) { case PIPE_TEX_MIPFILTER_LINEAR: retval |= R300_TX_MIN_FILTER_MIP_LINEAR; default: - /* XXX WTF?! */ + debug_printf("r300: Unknown texture filter %d", mip); break; } -- cgit v1.2.3 From e1b04da9b35aad1f474f7396f206a7c124c6859b Mon Sep 17 00:00:00 2001 From: Joakim Sindholt Date: Tue, 3 Feb 2009 02:58:51 +0100 Subject: r300: fix compiler/linker errors --- src/gallium/drivers/r300/r300_chipset.c | 1 + src/gallium/drivers/r300/r300_screen.c | 2 +- src/gallium/drivers/r300/r300_state.c | 1 + src/gallium/drivers/r300/r300_surface.c | 4 ++-- 4 files changed, 5 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index b0a7fe7d21..7def62422a 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -21,6 +21,7 @@ * USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "r300_chipset.h" +#include "pipe/p_debug.h" /* r300_chipset: A file all to itself for deducing the various properties of * Radeons. */ diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 8e77e0ddd9..fd916fadbe 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -81,7 +81,7 @@ static int r300_get_param(struct pipe_screen* pscreen, int param) /* IN THEORY */ return 0; case PIPE_CAP_TWO_SIDED_STENCIL: - if (r300screen->is_r500) { + if (r300screen->caps->is_r500) { return 1; } else { return 0; diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 37770cd5c6..6bb8379dd5 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -22,6 +22,7 @@ #include "util/u_math.h" #include "util/u_pack_color.h" +#include "pipe/p_debug.h" #include "r300_context.h" #include "r300_reg.h" diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 4bccdbca29..e03f3de371 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -52,7 +52,7 @@ static void r300_surface_fill(struct pipe_context* pipe, return; } -BEGIN_CS((caps->is_r500) ? 300 : 322); +BEGIN_CS((caps->is_r500) ? 309 : 322); R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; @@ -289,7 +289,7 @@ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); -/* XXX this should not be so rigid */ +/* XXX this should not be so rigid and it still doesn't work right */ OUT_CS_REG(R300_RB3D_COLORPITCH0, (w / 4) | R300_COLOR_TILE_ENABLE | R300_COLOR_FORMAT_ARGB8888); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); -- cgit v1.2.3 From e5018a5675603ec26e833bc0808e4150a6bba16a Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Mon, 2 Feb 2009 20:33:57 -0800 Subject: r300: Add stubs for swtcl immediate emit. --- src/gallium/drivers/r300/Makefile | 1 + src/gallium/drivers/r300/r300_context.c | 1 + src/gallium/drivers/r300/r300_swtcl_emit.c | 106 +++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 src/gallium/drivers/r300/r300_swtcl_emit.c (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index 1d61b31605..8906d1227a 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -12,6 +12,7 @@ C_SOURCES = \ r300_screen.c \ r300_state.c \ r300_surface.c \ + r300_swtcl_emit.c \ r300_texture.c include ../../Makefile.template diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c index e63e1278bf..7b605ae87a 100644 --- a/src/gallium/drivers/r300/r300_context.c +++ b/src/gallium/drivers/r300/r300_context.c @@ -50,6 +50,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen, r300->context.clear = r300_clear; r300->draw = draw_create(); + /*XXX draw_set_rasterize_stage(r300->draw, r300_draw_swtcl_stage(r300));*/ r300->blend_color_state = CALLOC_STRUCT(r300_blend_color_state); r300->scissor_state = CALLOC_STRUCT(r300_scissor_state); diff --git a/src/gallium/drivers/r300/r300_swtcl_emit.c b/src/gallium/drivers/r300/r300_swtcl_emit.c new file mode 100644 index 0000000000..98340a7a7c --- /dev/null +++ b/src/gallium/drivers/r300/r300_swtcl_emit.c @@ -0,0 +1,106 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "draw/draw_pipe.h" +#include "util/u_memory.h" + +#include "r300_context.h" +#include "r300_reg.h" + +/* r300_swtcl_emit: Primitive vertex emission using an immediate + * vertex buffer and no HW TCL. */ + +struct swtcl_stage { + /* Parent class */ + struct draw_stage draw; + + struct r300_context* r300; +}; + +static INLINE struct swtcl_stage* swtcl_stage(struct draw_stage* draw) { + return (struct swtcl_stage*)draw; +} + +static INLINE void r300_emit_prim(struct draw_stage* draw, + struct prim_header* prim, + unsigned hwprim, + unsigned count) +{ + struct r300_context* r300 = swtcl_stage(draw)->r300; +} + +/* Just as an aside... + * + * Radeons can do many more primitives: + * - Line strip + * - Triangle fan + * - Triangle strip + * - Line loop + * - Quads + * - Quad strip + * - Polygons + * + * The following were just the only ones in Draw. */ + +static void r300_emit_point(struct draw_stage* draw, struct prim_header* prim) +{ + r300_emit_prim(draw, prim, R300_VAP_VF_CNTL__PRIM_POINTS, 1); +} + +static void r300_emit_line(struct draw_stage* draw, struct prim_header* prim) +{ + r300_emit_prim(draw, prim, R300_VAP_VF_CNTL__PRIM_LINES, 2); +} + +static void r300_emit_tri(struct draw_stage* draw, struct prim_header* prim) +{ + r300_emit_prim(draw, prim, R300_VAP_VF_CNTL__PRIM_TRIANGLES, 3); +} + +static void r300_swtcl_flush(struct draw_stage* draw, unsigned flags) +{ +} + +static void r300_reset_stipple(struct draw_stage* draw) +{ + /* XXX */ +} + +static void r300_swtcl_destroy(struct draw_stage* draw) +{ + FREE(draw); +} + +struct draw_stage* r300_draw_swtcl_stage(struct r300_context* r300) +{ + struct swtcl_stage* swtcl = CALLOC_STRUCT(swtcl_stage); + + swtcl->r300 = r300; + swtcl->draw.point = r300_emit_point; + swtcl->draw.line = r300_emit_line; + swtcl->draw.tri = r300_emit_tri; + swtcl->draw.flush = r300_swtcl_flush; + swtcl->draw.reset_stipple_counter = r300_reset_stipple; + swtcl->draw.destroy = r300_swtcl_destroy; + + return &swtcl->draw; +} -- cgit v1.2.3 From f097465bb85d3ca212a23c2dcc9cf73988de9160 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Tue, 3 Feb 2009 22:55:30 -0800 Subject: r300: Moar swtcl emit. Still sucks, but getting there. --- src/gallium/drivers/r300/r300_swtcl_emit.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_swtcl_emit.c b/src/gallium/drivers/r300/r300_swtcl_emit.c index 98340a7a7c..f6e98d23e9 100644 --- a/src/gallium/drivers/r300/r300_swtcl_emit.c +++ b/src/gallium/drivers/r300/r300_swtcl_emit.c @@ -23,6 +23,7 @@ #include "draw/draw_pipe.h" #include "util/u_memory.h" +#include "r300_cs.h" #include "r300_context.h" #include "r300_reg.h" @@ -40,12 +41,34 @@ static INLINE struct swtcl_stage* swtcl_stage(struct draw_stage* draw) { return (struct swtcl_stage*)draw; } +static void r300_emit_vertex(struct r300_context* r300, + const struct vertex_header* vertex) +{ + /* XXX */ +} + static INLINE void r300_emit_prim(struct draw_stage* draw, struct prim_header* prim, unsigned hwprim, unsigned count) { struct r300_context* r300 = swtcl_stage(draw)->r300; + CS_LOCALS(r300); + int i; + + r300_emit_dirty_state(r300); + + /* XXX should be count * vtx size */ + BEGIN_CS(2 + count + 6); + OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, count)); + OUT_CS(hwprim | R300_PRIM_WALK_RING | + (count << R300_PRIM_NUM_VERTICES_SHIFT)); + + for (i = 0; i < count; i++) { + r300_emit_vertex(r300, prim->v[i]); + } + R300_PACIFY; + END_CS; } /* Just as an aside... @@ -63,17 +86,17 @@ static INLINE void r300_emit_prim(struct draw_stage* draw, static void r300_emit_point(struct draw_stage* draw, struct prim_header* prim) { - r300_emit_prim(draw, prim, R300_VAP_VF_CNTL__PRIM_POINTS, 1); + r300_emit_prim(draw, prim, R300_PRIM_TYPE_POINT, 1); } static void r300_emit_line(struct draw_stage* draw, struct prim_header* prim) { - r300_emit_prim(draw, prim, R300_VAP_VF_CNTL__PRIM_LINES, 2); + r300_emit_prim(draw, prim, R300_PRIM_TYPE_LINE, 2); } static void r300_emit_tri(struct draw_stage* draw, struct prim_header* prim) { - r300_emit_prim(draw, prim, R300_VAP_VF_CNTL__PRIM_TRIANGLES, 3); + r300_emit_prim(draw, prim, R300_PRIM_TYPE_TRI_LIST, 3); } static void r300_swtcl_flush(struct draw_stage* draw, unsigned flags) -- cgit v1.2.3 From 9f10b16790d7e4e224fc30cf105df944275d6353 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 4 Feb 2009 00:50:38 -0800 Subject: r300: A bit more cleanup and state handling. --- src/gallium/drivers/r300/r300_context.h | 20 +++++++++-------- src/gallium/drivers/r300/r300_state.c | 38 ++++++--------------------------- 2 files changed, 18 insertions(+), 40 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index 0cb0ec20d5..e0aad66018 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -87,15 +87,17 @@ struct r300_scissor_state { struct r300_texture_state { }; -#define R300_NEW_BLEND 0x0001 -#define R300_NEW_BLEND_COLOR 0x0002 -#define R300_NEW_DSA 0x0004 -#define R300_NEW_FRAGMENT_SHADER 0x0008 -#define R300_NEW_RASTERIZER 0x0010 -#define R300_NEW_SAMPLER 0x0020 -#define R300_NEW_SCISSOR 0x2000 -#define R300_NEW_VERTEX_SHADER 0x4000 -#define R300_NEW_KITCHEN_SINK 0x7fff +#define R300_NEW_BLEND 0x000001 +#define R300_NEW_BLEND_COLOR 0x000002 +#define R300_NEW_DSA 0x000004 +#define R300_NEW_FRAMEBUFFERS 0x000008 +#define R300_NEW_FRAGMENT_SHADER 0x000010 +#define R300_NEW_RASTERIZER 0x000020 +#define R300_NEW_SAMPLER 0x000040 +#define R300_NEW_SCISSOR 0x004000 +#define R300_NEW_TEXTURE 0x008000 +#define R300_NEW_VERTEX_SHADER 0x800000 +#define R300_NEW_KITCHEN_SINK 0xffffff struct r300_texture { /* Parent class */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index 6bb8379dd5..b4b50ce1a9 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -394,7 +394,7 @@ static void r300->framebuffer_state = *state; - /* XXX do we need to mark dirty state? */ + r300->dirty_state |= R300_NEW_FRAMEBUFFERS; } /* Create fragment shader state. */ @@ -428,31 +428,6 @@ static void r300_set_polygon_stipple(struct pipe_context* pipe, /* XXX */ } -#if 0 -struct pipe_rasterizer_state -{ - unsigned flatshade:1; - unsigned light_twoside:1; - unsigned fill_cw:2; /**< PIPE_POLYGON_MODE_x */ - unsigned fill_ccw:2; /**< PIPE_POLYGON_MODE_x */ - unsigned scissor:1; - unsigned poly_smooth:1; - unsigned poly_stipple_enable:1; - unsigned point_smooth:1; - unsigned point_sprite:1; - unsigned multisample:1; /* XXX maybe more ms state in future */ - unsigned line_smooth:1; - unsigned line_last_pixel:1; - unsigned bypass_clipping:1; - unsigned bypass_vs:1; /**< Skip the vertex shader. Note that the shader is - still needed though, to indicate inputs/outputs */ - unsigned origin_lower_left:1; /**< Is (0,0) the lower-left corner? */ - unsigned flatshade_first:1; /**< take color attribute from the first vertex of a primitive */ - unsigned gl_rasterization_rules:1; /**< enable tweaks for GL rasterization? */ - ubyte sprite_coord_mode[PIPE_MAX_SHADER_OUTPUTS]; /**< PIPE_SPRITE_COORD_ */ -}; -#endif - static INLINE int pack_float_16_6x(float f) { return ((int)(f * 6.0) & 0xffff); } @@ -693,15 +668,16 @@ static void r300_set_sampler_textures(struct pipe_context* pipe, if (r300->textures[i] != (struct r300_texture*)texture[i]) { pipe_texture_reference((struct pipe_texture**)&r300->textures[i], texture[i]); - /* XXX NEW_TEXTURE instead? */ - r300->dirty_state |= (R300_NEW_SAMPLER << i); + r300->dirty_state |= (R300_NEW_TEXTURE << i); } } for (i = count; i < 8; i++) { - /* XXX also state change? */ - pipe_texture_reference((struct pipe_texture**)&r300->textures[i], - NULL); + if (r300->textures[i]) { + pipe_texture_reference((struct pipe_texture**)&r300->textures[i], + NULL); + r300->dirty_state |= (R300_NEW_TEXTURE << i); + } } r300->texture_count = count; -- cgit v1.2.3 From fb8b794c69330924ad15083237b1a8a35eb62e31 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Wed, 4 Feb 2009 16:07:39 -0800 Subject: r300: Add shader state stubs. --- src/gallium/drivers/r300/Makefile | 1 + src/gallium/drivers/r300/r300_context.h | 30 ++++++++++++++++++++---- src/gallium/drivers/r300/r300_state.c | 35 ++++++++++++++++++++++------ src/gallium/drivers/r300/r300_state_shader.c | 33 ++++++++++++++++++++++++++ src/gallium/drivers/r300/r300_state_shader.h | 35 ++++++++++++++++++++++++++++ 5 files changed, 122 insertions(+), 12 deletions(-) create mode 100644 src/gallium/drivers/r300/r300_state_shader.c create mode 100644 src/gallium/drivers/r300/r300_state_shader.h (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/Makefile b/src/gallium/drivers/r300/Makefile index 8906d1227a..e83d943cd8 100644 --- a/src/gallium/drivers/r300/Makefile +++ b/src/gallium/drivers/r300/Makefile @@ -11,6 +11,7 @@ C_SOURCES = \ r300_flush.c \ r300_screen.c \ r300_state.c \ + r300_state_shader.c \ r300_surface.c \ r300_swtcl_emit.c \ r300_texture.c diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index e0aad66018..fb91c172f4 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -25,6 +25,7 @@ #include "draw/draw_context.h" #include "pipe/p_context.h" +#include "tgsi/tgsi_scan.h" #include "util/u_memory.h" #include "r300_clear.h" @@ -56,9 +57,6 @@ struct r300_dsa_state { uint32_t stencil_ref_bf; /* R500_ZB_STENCILREFMASK_BF: 0x4fd4 */ }; -struct r300_fs_state { -}; - struct r300_rs_state { uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ @@ -99,6 +97,28 @@ struct r300_texture_state { #define R300_NEW_VERTEX_SHADER 0x800000 #define R300_NEW_KITCHEN_SINK 0xffffff +/* The next several objects are not pure Radeon state; they inherit from + * various Gallium classes. */ + +struct r3xx_fragment_shader { + /* Parent class */ + struct pipe_shader_state state; + struct tgsi_shader_info info; + + /* Has this shader been translated yet? */ + boolean translated; +}; + +struct r300_fragment_shader { + /* Parent class */ + struct r3xx_fragment_shader shader; +}; + +struct r500_fragment_shader { + /* Parent class */ + struct r3xx_fragment_shader shader; +}; + struct r300_texture { /* Parent class */ struct pipe_texture tex; @@ -129,8 +149,8 @@ struct r300_context { struct r300_blend_color_state* blend_color_state; /* Depth, stencil, and alpha state. */ struct r300_dsa_state* dsa_state; - /* Fragment shader state. */ - struct r300_fs_state* fs_state; + /* Fragment shader. */ + struct r3xx_fragment_shader* fs; /* Framebuffer state. We currently don't need our own version of this. */ struct pipe_framebuffer_state framebuffer_state; /* Rasterizer state. */ diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c index b4b50ce1a9..9392d72342 100644 --- a/src/gallium/drivers/r300/r300_state.c +++ b/src/gallium/drivers/r300/r300_state.c @@ -399,27 +399,48 @@ static void /* Create fragment shader state. */ static void* r300_create_fs_state(struct pipe_context* pipe, - const struct pipe_shader_state* state) + const struct pipe_shader_state* shader) { - struct r300_fs_state* fs = CALLOC_STRUCT(r300_fs_state); + struct r300_context* r300 = r300_context(pipe); + struct r3xx_fragment_shader* fs = NULL; + + if (r300_screen(r300->context.screen)->caps->is_r500) { + fs = + (struct r3xx_fragment_shader*)CALLOC_STRUCT(r500_fragment_shader); + } else { + fs = + (struct r3xx_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); + } + + /* Copy state directly into shader. */ + fs->state = *shader; return (void*)fs; } /* Bind fragment shader state. */ -static void r300_bind_fs_state(struct pipe_context* pipe, void* state) +static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) { struct r300_context* r300 = r300_context(pipe); + struct r3xx_fragment_shader* fs = (struct r3xx_fragment_shader*)shader; - r300->fs_state = (struct r300_fs_state*)state; + if (!fs->translated) { + if (r300_screen(r300->context.screen)->caps->is_r500) { + r500_translate_shader(r300, fs); + } else { + r300_translate_shader(r300, fs); + } + } + + r300->fs = fs; r300->dirty_state |= R300_NEW_FRAGMENT_SHADER; } -/* Delect fragment shader state. */ -static void r300_delete_fs_state(struct pipe_context* pipe, void* state) +/* Delete fragment shader state. */ +static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) { - FREE(state); + FREE(shader); } static void r300_set_polygon_stipple(struct pipe_context* pipe, diff --git a/src/gallium/drivers/r300/r300_state_shader.c b/src/gallium/drivers/r300/r300_state_shader.c new file mode 100644 index 0000000000..e87172128f --- /dev/null +++ b/src/gallium/drivers/r300/r300_state_shader.c @@ -0,0 +1,33 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#include "r300_state_shader.h" + +void r300_translate_shader(struct r300_context* r300, + struct r300_fragment_shader* fs) +{ +} + +void r500_translate_shader(struct r300_context* r300, + struct r500_fragment_shader* fs) +{ +} diff --git a/src/gallium/drivers/r300/r300_state_shader.h b/src/gallium/drivers/r300/r300_state_shader.h new file mode 100644 index 0000000000..a20bd4276c --- /dev/null +++ b/src/gallium/drivers/r300/r300_state_shader.h @@ -0,0 +1,35 @@ +/* + * Copyright 2008 Corbin Simpson + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef R300_STATE_SHADER_H +#define R300_STATE_SHADER_H + +#include "r300_context.h" +#include "r300_screen.h" + +void r300_translate_shader(struct r300_context* r300, + struct r300_fragment_shader* fs); + +void r500_translate_shader(struct r300_context* r300, + struct r500_fragment_shader* fs); + +#endif /* R300_STATE_SHADER_H */ -- cgit v1.2.3 From be53dfa3b9ca4d1503fdbdf934569442175e30ef Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Thu, 5 Feb 2009 13:27:07 -0800 Subject: r300: Add framebuffer setup stub. --- src/gallium/drivers/r300/r300_emit.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index de5719db8d..c71b8d0b02 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -79,6 +79,22 @@ void r300_emit_dsa_state(struct r300_context* r300, END_CS; } +/* XXX add pitch, stride, z/stencil buf */ +void r300_emit_fb_state(struct r300_context* r300, + struct pipe_framebuffer_state* fb) +{ + CS_LOCALS(r300); + int i; + + BEGIN_CS((3 * fb->nr_cbufs) + 6); + for (i = 0; i < fb->nr_cbufs; i++) { + OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1); + OUT_CS_RELOC(fb->cbufs[i]->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + } + R300_PACIFY; + END_CS; +} + void r300_emit_rs_state(struct r300_context* r300, struct r300_rs_state* rs) { struct r300_screen* r300screen = -- cgit v1.2.3 From 402d45d99b4533140aa706300da3154af2f376f0 Mon Sep 17 00:00:00 2001 From: Joakim Sindholt Date: Thu, 5 Feb 2009 22:23:40 +0100 Subject: r300: working trivial/clear for r5xx --- src/gallium/drivers/r300/r300_surface.c | 4 ++-- src/gallium/drivers/r300/r300_texture.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index e03f3de371..3db013cd7e 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -290,8 +290,8 @@ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); /* XXX this should not be so rigid and it still doesn't work right */ -OUT_CS_REG(R300_RB3D_COLORPITCH0, (w / 4) | R300_COLOR_TILE_ENABLE | - R300_COLOR_FORMAT_ARGB8888); +debug_printf("Buffer width (stride): %d\n", dest->stride); +OUT_CS_REG(R300_RB3D_COLORPITCH0, (dest->stride >> 2) | R300_COLOR_FORMAT_ARGB8888); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); /* XXX Packet3 */ OUT_CS(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8)); diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 537425c1e2..f9ad14f12b 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -44,11 +44,11 @@ static void r300_setup_miptree(struct r300_texture* tex) /* Radeons enjoy things in multiples of 32. */ /* XXX NPOT -> 64, not 32 */ - stride = (base->nblocksx[i] * base->block.size + 31) & ~31; + stride = (base->nblocksx[i] * base->block.size + 63) & ~63; size = stride * base->nblocksy[i] * base->depth[i]; /* XXX 64 for NPOT */ - tex->offset[i] = (tex->size + 31) & ~31; + tex->offset[i] = (tex->size + 63) & ~63; tex->size = tex->offset[i] + size; } } @@ -72,7 +72,7 @@ static struct pipe_texture* r300_setup_miptree(tex); - tex->buffer = screen->buffer_create(screen, 32, + tex->buffer = screen->buffer_create(screen, 63, PIPE_BUFFER_USAGE_PIXEL, tex->size); @@ -130,7 +130,7 @@ static struct pipe_surface* r300_get_tex_surface(struct pipe_screen* screen, surface->nblocksy = texture->nblocksy[level]; /* XXX save the actual stride instead plz kthnxbai */ surface->stride = - (texture->nblocksx[level] * texture->block.size + 31) & ~31; + (texture->nblocksx[level] * texture->block.size + 63) & ~63; surface->offset = offset; surface->usage = flags; surface->status = PIPE_SURFACE_STATUS_DEFINED; -- cgit v1.2.3 From 2e70971e4f1ac5278e9da67341e8c39518308d20 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Fri, 6 Feb 2009 01:59:26 -0800 Subject: r300: Clean up CS counting. --- src/gallium/drivers/r300/r300_cs.h | 1 + src/gallium/drivers/r300/r300_surface.c | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_cs.h b/src/gallium/drivers/r300/r300_cs.h index 734ccb13d9..385b61a096 100644 --- a/src/gallium/drivers/r300/r300_cs.h +++ b/src/gallium/drivers/r300/r300_cs.h @@ -107,6 +107,7 @@ static uint32_t pack_float_32(float f) assert(bo); \ OUT_CS(offset); \ cs_winsys->write_cs_reloc(cs, bo, rd, wd, flags); \ + cs_count -= 2; \ } while (0) #define END_CS do { \ diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 3db013cd7e..1ed4a4e3bc 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -39,8 +39,8 @@ static void r300_surface_fill(struct pipe_context* pipe, g = (float)((color >> 8) & 0xff) / 255.0f; b = (float)((color >> 0) & 0xff) / 255.0f; debug_printf("r300: Filling surface %p at (%d,%d)," - " dimensions %dx%d, color 0x%x\n", - dest, x, y, w, h, color); + " dimensions %dx%d (stride %d), color 0x%x\n", + dest, x, y, w, h, dest->stride, color); /* Fallback? */ if (0) { @@ -52,7 +52,7 @@ static void r300_surface_fill(struct pipe_context* pipe, return; } -BEGIN_CS((caps->is_r500) ? 309 : 322); +BEGIN_CS((caps->is_r500) ? 309 : 280); R300_PACIFY; OUT_CS_REG(R300_TX_INVALTAGS, 0x0); R300_PACIFY; @@ -273,11 +273,14 @@ OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203); OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021); OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021); OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); +R300_PACIFY; +END_CS; r300_emit_blend_state(r300, &blend_clear_state); r300_emit_blend_color_state(r300, &blend_color_clear_state); r300_emit_dsa_state(r300, &dsa_clear_state); +BEGIN_CS(36); R300_PACIFY; /* Flush colorbuffer and blend caches. */ OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT, @@ -290,7 +293,6 @@ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); /* XXX this should not be so rigid and it still doesn't work right */ -debug_printf("Buffer width (stride): %d\n", dest->stride); OUT_CS_REG(R300_RB3D_COLORPITCH0, (dest->stride >> 2) | R300_COLOR_FORMAT_ARGB8888); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); /* XXX Packet3 */ -- cgit v1.2.3 From ea3398cf3395fd36ac6edc717f2680361ac5e239 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sun, 8 Feb 2009 01:01:26 -0800 Subject: r300: Update to match pipe_surface changes. --- src/gallium/drivers/r300/r300_context.h | 4 ++++ src/gallium/drivers/r300/r300_emit.c | 4 +++- src/gallium/drivers/r300/r300_screen.c | 6 ++++-- src/gallium/drivers/r300/r300_surface.c | 3 ++- src/gallium/drivers/r300/r300_texture.c | 4 ---- 5 files changed, 13 insertions(+), 8 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h index fb91c172f4..376c57639d 100644 --- a/src/gallium/drivers/r300/r300_context.h +++ b/src/gallium/drivers/r300/r300_context.h @@ -179,8 +179,12 @@ static struct r300_context* r300_context(struct pipe_context* context) { void r300_init_state_functions(struct r300_context* r300); void r300_init_surface_functions(struct r300_context* r300); +/* Fun with includes: r300_winsys also declares this prototype. + * We'll just step out in that case... */ +#ifndef R300_WINSYS_H struct pipe_context* r300_create_context(struct pipe_screen* screen, struct pipe_winsys* winsys, struct r300_winsys* r300_winsys); +#endif #endif /* R300_CONTEXT_H */ diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c index c71b8d0b02..585a9e729d 100644 --- a/src/gallium/drivers/r300/r300_emit.c +++ b/src/gallium/drivers/r300/r300_emit.c @@ -84,12 +84,14 @@ void r300_emit_fb_state(struct r300_context* r300, struct pipe_framebuffer_state* fb) { CS_LOCALS(r300); + struct r300_texture* tex; int i; BEGIN_CS((3 * fb->nr_cbufs) + 6); for (i = 0; i < fb->nr_cbufs; i++) { + tex = (struct r300_texture*)fb->cbufs[i]->texture; OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0 + (4 * i), 1); - OUT_CS_RELOC(fb->cbufs[i]->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); + OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); } R300_PACIFY; END_CS; diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index fd916fadbe..8ed66a1660 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -214,7 +214,8 @@ static void* r300_surface_map(struct pipe_screen* screen, struct pipe_surface* surface, unsigned flags) { - char* map = pipe_buffer_map(screen, surface->buffer, flags); + struct r300_texture* tex = (struct r300_texture*)surface->texture; + char* map = pipe_buffer_map(screen, tex->buffer, flags); if (!map) { return NULL; @@ -226,7 +227,8 @@ static void* r300_surface_map(struct pipe_screen* screen, static void r300_surface_unmap(struct pipe_screen* screen, struct pipe_surface* surface) { - pipe_buffer_unmap(screen, surface->buffer); + struct r300_texture* tex = (struct r300_texture*)surface->texture; + pipe_buffer_unmap(screen, tex->buffer); } static void r300_destroy_screen(struct pipe_screen* pscreen) diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index 1ed4a4e3bc..bbd2ade64a 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -33,6 +33,7 @@ static void r300_surface_fill(struct pipe_context* pipe, struct r300_context* r300 = r300_context(pipe); CS_LOCALS(r300); struct r300_capabilities* caps = ((struct r300_screen*)pipe->screen)->caps; + struct r300_texture* tex = (struct r300_texture*)dest->texture; int i; float r, g, b, a; r = (float)((color >> 16) & 0xff) / 255.0f; @@ -291,7 +292,7 @@ OUT_CS_REG(R300_ZB_ZCACHE_CTLSTAT, R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); OUT_CS_REG_SEQ(R300_RB3D_COLOROFFSET0, 1); -OUT_CS_RELOC(dest->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); +OUT_CS_RELOC(tex->buffer, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); /* XXX this should not be so rigid and it still doesn't work right */ OUT_CS_REG(R300_RB3D_COLORPITCH0, (dest->stride >> 2) | R300_COLOR_FORMAT_ARGB8888); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0x0000000F); diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index f9ad14f12b..7f57656a78 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -121,7 +121,6 @@ static struct pipe_surface* r300_get_tex_surface(struct pipe_screen* screen, if (surface) { surface->refcount = 1; pipe_texture_reference(&surface->texture, texture); - pipe_buffer_reference(screen, &surface->buffer, tex->buffer); surface->format = texture->format; surface->width = texture->width[level]; surface->height = texture->height[level]; @@ -148,7 +147,6 @@ static void r300_tex_surface_release(struct pipe_screen* screen, if (s->refcount <= 0) { pipe_texture_reference(&s->texture, NULL); - pipe_buffer_reference(screen, &s->buffer, NULL); FREE(s); } @@ -180,8 +178,6 @@ static struct pipe_texture* /* XXX tex->stride = *stride; */ - pipe_buffer_reference(screen, &tex->buffer, buffer); - return (struct pipe_texture*)tex; } -- cgit v1.2.3 From 360e700a43ce3914d7f336593f380562ca190898 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sun, 8 Feb 2009 01:07:03 -0800 Subject: r300: Add SW TCL paths for clear. This should make things work for people on RSxxx chipsets. --- src/gallium/drivers/r300/r300_surface.c | 61 +++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 19 deletions(-) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_surface.c b/src/gallium/drivers/r300/r300_surface.c index bbd2ade64a..1e1f96a7f9 100644 --- a/src/gallium/drivers/r300/r300_surface.c +++ b/src/gallium/drivers/r300/r300_surface.c @@ -153,7 +153,17 @@ OUT_CS_REG(0x4F34, 0x00000000); OUT_CS_REG(R300_ZB_HIZ_OFFSET, 0x00000000); OUT_CS_REG(R300_ZB_HIZ_PITCH, 0x00000000); R300_PACIFY; -OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, 0x21030003); +if (caps->has_tcl) { + OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, + (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) | + ((R300_LAST_VEC | (1 << R300_DST_VEC_LOC_SHIFT) | + R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)); +} else { + OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_0, + (R300_DATA_TYPE_FLOAT_4 << R300_DATA_TYPE_0_SHIFT) | + ((R300_LAST_VEC | (2 << R300_DST_VEC_LOC_SHIFT) | + R300_DATA_TYPE_FLOAT_4) << R300_DATA_TYPE_1_SHIFT)); +} OUT_CS_REG(R300_FG_FOG_BLEND, 0x00000000); OUT_CS_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 0xF688F688); OUT_CS_REG(R300_VAP_VTX_STATE_CNTL, 0x1); @@ -173,7 +183,11 @@ OUT_CS_32F((float)y); OUT_CS_32F(1.0); OUT_CS_32F(0.0); -OUT_CS_REG(R300_VAP_CLIP_CNTL, 0x0001C000); +if (caps->has_tcl) { + OUT_CS_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE | + R300_PS_UCP_MODE_CLIP_AS_TRIFAN); +} + OUT_CS_REG(R300_GA_POINT_SIZE, ((h * 6) & R300_POINTSIZE_Y_MASK) | ((w * 6) << R300_POINTSIZE_X_SHIFT)); @@ -257,23 +271,32 @@ if (caps->is_r500) { } /* XXX these magic numbers should be explained when * this becomes a cached state object */ -OUT_CS_REG(R300_VAP_CNTL, 0xA | (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | - (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT)); -OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000); -OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000); -OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001); -R300_PACIFY; -/* XXX translate these back into normal instructions */ -OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); -OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF00203); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10001); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248001); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021); -OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); +if (caps->has_tcl) { + OUT_CS_REG(R300_VAP_CNTL, 0xA | + (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (0xB << R300_VF_MAX_VTX_NUM_SHIFT) | + (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT)); + OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_0, 0x00100000); + OUT_CS_REG(R300_VAP_PVS_CONST_CNTL, 0x00000000); + OUT_CS_REG(R300_VAP_PVS_CODE_CNTL_1, 0x00000001); + R300_PACIFY; + /* XXX translate these back into normal instructions */ + OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x1); + OUT_CS_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0x0); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF00203); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10001); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248001); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xF02203); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0xD10021); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x1248021); + OUT_CS_REG(R300_VAP_PVS_UPLOAD_DATA, 0x0); +} else { + OUT_CS_REG(R300_VAP_CNTL, 0xA | + (0x5 << R300_PVS_NUM_CNTLRS_SHIFT) | + (0x5 << R300_VF_MAX_VTX_NUM_SHIFT) | + (caps->num_vert_fpus << R300_PVS_NUM_FPUS_SHIFT)); +} R300_PACIFY; END_CS; -- cgit v1.2.3 From 5425c4aa28721072085f128e902f5679ba31a963 Mon Sep 17 00:00:00 2001 From: Corbin Simpson Date: Sun, 8 Feb 2009 02:03:29 -0800 Subject: r300: Accidentally removed a pipe_buffer_reference that should be there. --- src/gallium/drivers/r300/r300_texture.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/gallium/drivers/r300') diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 7f57656a78..ff812c09f8 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -178,6 +178,8 @@ static struct pipe_texture* /* XXX tex->stride = *stride; */ + pipe_buffer_reference(screen, &tex->buffer, buffer); + return (struct pipe_texture*)tex; } -- cgit v1.2.3