From de553d906b4a205d811a9e1651f14212ec284e29 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 23 Jul 2010 17:32:32 -0400
Subject: r600g: drop compiler stuff and switch over dumb tgsi assembler

Writing a compiler is time consuming and error prone in
order to allow r600g to further progress in the meantime
i wrote a simple tgsi assembler, it does stupid thing but
i would rather keep the code simple than having people
trying to optimize code it does.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_state.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 4150f88785..84a13e4ef7 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -151,7 +151,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 static void *r600_create_fs_state(struct pipe_context *ctx,
 					const struct pipe_shader_state *shader)
 {
-	return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_FS, shader->tokens);
+	return r600_pipe_shader_create(ctx, shader->tokens);
 }
 
 static void r600_bind_fs_state(struct pipe_context *ctx, void *state)
@@ -164,7 +164,7 @@ static void r600_bind_fs_state(struct pipe_context *ctx, void *state)
 static void *r600_create_vs_state(struct pipe_context *ctx,
 					const struct pipe_shader_state *shader)
 {
-	return r600_pipe_shader_create(ctx, C_PROGRAM_TYPE_VS, shader->tokens);
+	return r600_pipe_shader_create(ctx, shader->tokens);
 }
 
 static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
-- 
cgit v1.2.3


From 641c9adb09e8707f659d42be600d16902ebf8895 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Tue, 27 Jul 2010 20:15:17 -0400
Subject: r600g: texture support

Add texture mapping support, redbook/texbind works if
you comment out glClear and second checkboard. Need to
fix :
 - texture overwritting
 - lod & mip/map handling
 - unormalized coordinate handling
 - texture view with first leve > 0
 - and many other things

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.c |   2 +-
 src/gallium/drivers/r600/r600_context.h |  12 ++
 src/gallium/drivers/r600/r600_draw.c    |  11 ++
 src/gallium/drivers/r600/r600_shader.c  |  78 ++++++++-
 src/gallium/drivers/r600/r600_state.c   | 277 +++++++++++++++++++++++++++++++-
 src/gallium/drivers/r600/r600_texture.c |   4 +
 src/gallium/drivers/r600/r600d.h        | 235 +++++++++++++++++++++++++++
 7 files changed, 610 insertions(+), 9 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 05575b5767..3c5195f79e 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -55,7 +55,7 @@ static void r600_flush(struct pipe_context *ctx, unsigned flags,
 	 */
 	if (!dc)
 		radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
-#if 0
+#if 1
 	radeon_ctx_submit(rctx->ctx);
 #endif
 	rctx->ctx = radeon_ctx_decref(rctx->ctx);
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 669aaec0b2..30f33f757e 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -23,6 +23,7 @@
 #ifndef R600_CONTEXT_H
 #define R600_CONTEXT_H
 
+#include <stdio.h>
 #include <pipe/p_state.h>
 #include <pipe/p_context.h>
 #include <tgsi/tgsi_scan.h>
@@ -45,6 +46,11 @@ struct r600_pipe_shader {
 	struct radeon_state			*state;
 };
 
+struct r600_texture_resource {
+	struct pipe_sampler_view		view;
+	struct radeon_state			*state;
+};
+
 struct r600_context {
 	struct pipe_context		context;
 	struct r600_screen		*screen;
@@ -55,6 +61,12 @@ struct r600_context {
 	struct radeon_state		*config;
 	struct r600_pipe_shader		*ps_shader;
 	struct r600_pipe_shader		*vs_shader;
+	unsigned			nps_sampler;
+	struct radeon_state		*ps_sampler[PIPE_MAX_ATTRIBS];
+	unsigned			nps_view;
+	unsigned			nvs_view;
+	struct r600_texture_resource	*ps_view[PIPE_MAX_ATTRIBS];
+	struct r600_texture_resource	*vs_view[PIPE_MAX_ATTRIBS];
 	unsigned			flat_shade;
 	unsigned			nvertex_buffer;
 	struct r600_vertex_elements_state *vertex_elements;
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 724fb6c988..e0d624889f 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -125,6 +125,17 @@ static int r600_draw_common(struct r600_draw *draw)
 		if (r)
 			return r;
 	}
+	/* setup texture sampler & resource */
+	for (i = 0 ; i < rctx->nps_sampler; i++) {
+		r = radeon_draw_set_new(rctx->draw, rctx->ps_sampler[i]);
+		if (r)
+			return r;
+	}
+	for (i = 0 ; i < rctx->nps_view; i++) {
+		r = radeon_draw_set_new(rctx->draw, rctx->ps_view[i]->state);
+		if (r)
+			return r;
+	}
 	/* FIXME start need to change winsys */
 	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
 	if (draw->draw == NULL)
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 17e9c14d6b..9796112775 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -838,12 +838,82 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_tex tex;
+	struct r600_bc_alu alu;
+	unsigned src_gpr;
+	int r;
+
+	src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
+
+	/* Add perspective divide */
+	if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_TXP) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
+		alu.src[0].sel = src_gpr;
+		alu.src[0].chan = 3;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 3;
+		alu.last = 1;
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 3;
+		alu.src[1].sel = src_gpr;
+		alu.src[1].chan = 0;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 0;
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 3;
+		alu.src[1].sel = src_gpr;
+		alu.src[1].chan = 1;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 1;
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 3;
+		alu.src[1].sel = src_gpr;
+		alu.src[1].chan = 2;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 2;
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+		alu.src[0].sel = 249;
+		alu.src[0].chan = 0;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 3;
+		alu.last = 1;
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+		src_gpr = ctx->temp_reg;
+	}
 
+	/* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
 	memset(&tex, 0, sizeof(struct r600_bc_tex));
 	tex.inst = ctx->inst_info->r600_opcode;
 	tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
 	tex.sampler_id = tex.resource_id;
-	tex.src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
+	tex.src_gpr = src_gpr;
 	tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Src[0].Register.Index;
 	tex.dst_sel_x = 0;
 	tex.dst_sel_y = 1;
@@ -853,6 +923,10 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	tex.src_sel_y = 1;
 	tex.src_sel_z = 2;
 	tex.src_sel_w = 3;
+	tex.coord_type_x = 1;
+	tex.coord_type_y = 1;
+	tex.coord_type_z = 1;
+	tex.coord_type_w = 1;
 	return r600_bc_add_tex(ctx->bc, &tex);
 }
 
@@ -912,7 +986,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TEX,	0, 0x10, tgsi_tex},
 	{TGSI_OPCODE_TXD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TXP,	0, 0x10, tgsi_tex},
 	{TGSI_OPCODE_UP2H,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 84a13e4ef7..6503c3740e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -187,6 +187,8 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
 	struct radeon_state *rstate;
 
 	rctx->flat_shade = state->flatshade;
+	rctx->flat_shade = 0;
+R600_ERR("flat shade with texture broke tex coord interp\n");
 	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 	if (rstate == NULL)
 		return NULL;
@@ -224,43 +226,306 @@ static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 	radeon_draw_set(rctx->draw, state);
 }
 
+static inline unsigned r600_tex_wrap(unsigned wrap)
+{
+	switch (wrap) {
+	default:
+	case PIPE_TEX_WRAP_REPEAT:
+		return V_03C000_SQ_TEX_WRAP;
+	case PIPE_TEX_WRAP_CLAMP:
+		return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
+	case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
+	case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_CLAMP_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_REPEAT:
+		return V_03C000_SQ_TEX_MIRROR;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
+	case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+		return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
+	}
+}
+
+static inline unsigned r600_tex_filter(unsigned filter)
+{
+	switch (filter) {
+	default:
+	case PIPE_TEX_FILTER_NEAREST:
+		return V_03C000_SQ_TEX_XY_FILTER_POINT;
+	case PIPE_TEX_FILTER_LINEAR:
+		return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
+	}
+}
+
+static inline unsigned r600_tex_mipfilter(unsigned filter)
+{
+	switch (filter) {
+	case PIPE_TEX_MIPFILTER_NEAREST:
+		return V_03C000_SQ_TEX_Z_FILTER_POINT;
+	case PIPE_TEX_MIPFILTER_LINEAR:
+		return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
+	default:
+	case PIPE_TEX_MIPFILTER_NONE:
+		return V_03C000_SQ_TEX_Z_FILTER_NONE;
+	}
+}
+
+static inline unsigned r600_tex_compare(unsigned compare)
+{
+	switch (compare) {
+	default:
+	case PIPE_FUNC_NEVER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
+	case PIPE_FUNC_LESS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
+	case PIPE_FUNC_EQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
+	case PIPE_FUNC_LEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
+	case PIPE_FUNC_GREATER:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
+	case PIPE_FUNC_NOTEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
+	case PIPE_FUNC_GEQUAL:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
+	case PIPE_FUNC_ALWAYS:
+		return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
+	}
+}
+
 static void *r600_create_sampler_state(struct pipe_context *ctx,
 					const struct pipe_sampler_state *state)
 {
-	return NULL;
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, R600_PS_SAMPLER);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
+			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
+			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
+			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
+			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) |
+			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) |
+			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
+			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
+	/* FIXME LOD it depends on texture base level ... */
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
+			S_03C004_MIN_LOD(0) |
+			S_03C004_MAX_LOD(0) |
+			S_03C004_LOD_BIAS(0);
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
 static void r600_bind_sampler_states(struct pipe_context *ctx,
 					unsigned count, void **states)
 {
+	struct r600_context *rctx = r600_context(ctx);
+	unsigned i;
+
+	/* FIXME split VS/PS/GS sampler */
+	for (i = 0; i < count; i++) {
+		rctx->ps_sampler[i] = radeon_state_decref(rctx->ps_sampler[i]);
+	}
+	rctx->nps_sampler = count;
+	for (i = 0; i < count; i++) {
+		rctx->ps_sampler[i] = radeon_state_incref(states[i]);
+		rctx->ps_sampler[i]->id = R600_PS_SAMPLER + i;
+	}
+}
+
+static inline unsigned r600_tex_swizzle(unsigned swizzle)
+{
+	switch (swizzle) {
+	case PIPE_SWIZZLE_RED:
+		return V_038010_SQ_SEL_X;
+	case PIPE_SWIZZLE_GREEN:
+		return V_038010_SQ_SEL_Y;
+	case PIPE_SWIZZLE_BLUE:
+		return V_038010_SQ_SEL_Z;
+	case PIPE_SWIZZLE_ALPHA:
+		return V_038010_SQ_SEL_W;
+	case PIPE_SWIZZLE_ZERO:
+		return V_038010_SQ_SEL_0;
+	default:
+	case PIPE_SWIZZLE_ONE:
+		return V_038010_SQ_SEL_1;
+	}
+}
+
+static inline unsigned r600_format_type(unsigned format_type)
+{
+	switch (format_type) {
+	default:
+	case UTIL_FORMAT_TYPE_UNSIGNED:
+		return V_038010_SQ_FORMAT_COMP_UNSIGNED;
+	case UTIL_FORMAT_TYPE_SIGNED:
+		return V_038010_SQ_FORMAT_COMP_SIGNED;
+	case UTIL_FORMAT_TYPE_FIXED:
+		return V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED;
+	}
+}
+
+static inline unsigned r600_tex_dim(unsigned dim)
+{
+	switch (dim) {
+	default:
+	case PIPE_TEXTURE_1D:
+		return V_038000_SQ_TEX_DIM_1D;
+	case PIPE_TEXTURE_2D:
+		return V_038000_SQ_TEX_DIM_2D;
+	case PIPE_TEXTURE_3D:
+		return V_038000_SQ_TEX_DIM_3D;
+	case PIPE_TEXTURE_CUBE:
+		return V_038000_SQ_TEX_DIM_CUBEMAP;
+	}
 }
 
 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
 							  struct pipe_resource *texture,
-							  const struct pipe_sampler_view *templ)
+							  const struct pipe_sampler_view *view)
 {
-	struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_texture_resource *rtexture;
+	const struct util_format_description *desc;
+	struct r600_texture *tmp;
+	struct r600_buffer *rbuffer;
+	unsigned format;
 
-	*view = *templ;
-	return view;
+	if (r600_conv_pipe_format(texture->format, &format))
+		return NULL;
+	rtexture = CALLOC_STRUCT(r600_texture_resource);
+	if (rtexture == NULL)
+		return NULL;
+	desc = util_format_description(texture->format);
+	assert(desc == NULL);
+	rtexture->state = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, R600_PS_RESOURCE);
+	if (rtexture->state == NULL) {
+		FREE(rtexture);
+		return NULL;
+	}
+	rtexture->view = *view;
+	rtexture->view.reference.count = 1;
+	rtexture->view.texture = NULL;
+	pipe_resource_reference(&rtexture->view.texture, texture);
+	rtexture->view.context = ctx;
+
+	tmp = (struct r600_texture*)texture;
+	rbuffer = (struct r600_buffer*)tmp->buffer;
+	rtexture->state->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rtexture->state->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rtexture->state->nbo = 2;
+	rtexture->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rtexture->state->placement[1] = RADEON_GEM_DOMAIN_GTT;
+	rtexture->state->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	rtexture->state->placement[3] = RADEON_GEM_DOMAIN_GTT;
+
+	/* FIXME properly handle first level != 0 */
+	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
+			S_038000_DIM(r600_tex_dim(texture->target)) |
+			S_038000_PITCH((tmp->pitch[0] / 8) - 1) |
+			S_038000_TEX_WIDTH(texture->width0 - 1);
+	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
+			S_038004_TEX_HEIGHT(texture->height0 - 1) |
+			S_038004_TEX_DEPTH(texture->depth0 - 1) |
+			S_038004_DATA_FORMAT(format);
+	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
+	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
+	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
+			S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+			S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
+			S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
+			S_038010_REQUEST_SIZE(1) |
+			S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_r)) |
+			S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
+			S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_b)) |
+			S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
+			S_038010_BASE_LEVEL(view->first_level);
+	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
+			S_038014_LAST_LEVEL(view->last_level) |
+			S_038014_BASE_ARRAY(0) |
+			S_038014_LAST_ARRAY(0);
+	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
+			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
+	return &rtexture->view;
 }
 
 static void r600_sampler_view_destroy(struct pipe_context *ctx,
 				      struct pipe_sampler_view *view)
 {
-	FREE(view);
+	struct r600_texture_resource *texture;
+
+	if (view == NULL)
+		return;
+	texture  = LIST_ENTRY(struct r600_texture_resource, view, view);
+	radeon_state_decref(texture->state);
+	FREE(texture);
 }
 
 static void r600_set_fragment_sampler_views(struct pipe_context *ctx,
 					    unsigned count,
 					    struct pipe_sampler_view **views)
 {
+	struct r600_texture_resource *rtexture;
+	struct r600_context *rctx = r600_context(ctx);
+	struct pipe_sampler_view *tmp;
+	unsigned i;
+
+	if (views == NULL)
+		return;
+
+	for (i = 0; i < rctx->nps_view; i++) {
+		tmp = &rctx->ps_view[i]->view;
+		pipe_sampler_view_reference(&tmp, NULL);
+		rctx->ps_view[i] = NULL;
+	}
+	rctx->nps_view = count;
+	for (i = 0; i < count; i++) {
+		rtexture = LIST_ENTRY(struct r600_texture_resource, views[i], view);
+		rctx->ps_view[i] = rtexture;
+		tmp = NULL;
+		pipe_sampler_view_reference(&tmp, views[i]);
+		rtexture->state->id = R600_PS_RESOURCE + i;
+	}
 }
 
 static void r600_set_vertex_sampler_views(struct pipe_context *ctx,
 					  unsigned count,
 					  struct pipe_sampler_view **views)
 {
+	struct r600_texture_resource *rtexture;
+	struct r600_context *rctx = r600_context(ctx);
+	struct pipe_sampler_view *tmp;
+	unsigned i;
+
+	if (views == NULL)
+		return;
+
+	for (i = 0; i < rctx->nvs_view; i++) {
+		tmp = &rctx->vs_view[i]->view;
+		pipe_sampler_view_reference(&tmp, NULL);
+		rctx->vs_view[i] = NULL;
+	}
+	rctx->nps_view = count;
+	for (i = 0; i < count; i++) {
+		rtexture = LIST_ENTRY(struct r600_texture_resource, views[i], view);
+		rctx->vs_view[i] = rtexture;
+		tmp = NULL;
+		pipe_sampler_view_reference(&tmp, views[i]);
+		rtexture->state->id = R600_VS_RESOURCE + i;
+	}
 }
 
 static void r600_set_scissor_state(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 903cfad80a..1c219a5579 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -31,7 +31,9 @@
 #include <util/u_memory.h>
 #include "state_tracker/drm_driver.h"
 #include "r600_screen.h"
+#include "r600_context.h"
 #include "r600_texture.h"
+#include "r600d.h"
 
 extern struct u_resource_vtbl r600_texture_vtbl;
 
@@ -69,6 +71,8 @@ static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_texture
 		rtex->offset[i] = offset;
 		rtex->layer_size[i] = layer_size;
 		rtex->pitch[i] = stride / util_format_get_blocksize(ptex->format);
+		rtex->pitch[i] += R600_TEXEL_PITCH_ALIGNMENT_MASK;
+		rtex->pitch[i] &= ~R600_TEXEL_PITCH_ALIGNMENT_MASK;
 		rtex->stride[i] = stride;
 		offset += align(size, 32);
 	}
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 44834984c6..593b95c9c7 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -26,6 +26,8 @@
 #ifndef R600D_H
 #define R600D_H
 
+#define R600_TEXEL_PITCH_ALIGNMENT_MASK        0x7
+
 #define PKT3_NOP                               0x10
 #define PKT3_INDIRECT_BUFFER_END               0x17
 #define PKT3_SET_PREDICATION                   0x20
@@ -574,6 +576,132 @@
 #define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
 #define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
 #define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+#define R_038000_SQ_TEX_RESOURCE_WORD0_0             0x038000
+#define   S_038000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_038000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_038000_DIM                                 0xFFFFFFF8
+#define     V_038000_SQ_TEX_DIM_1D                     0x00000000
+#define     V_038000_SQ_TEX_DIM_2D                     0x00000001
+#define     V_038000_SQ_TEX_DIM_3D                     0x00000002
+#define     V_038000_SQ_TEX_DIM_CUBEMAP                0x00000003
+#define     V_038000_SQ_TEX_DIM_1D_ARRAY               0x00000004
+#define     V_038000_SQ_TEX_DIM_2D_ARRAY               0x00000005
+#define     V_038000_SQ_TEX_DIM_2D_MSAA                0x00000006
+#define     V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA          0x00000007
+#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
+#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
+#define   C_038000_TILE_MODE                           0xFFFFFF87
+#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
+#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
+#define   C_038000_TILE_TYPE                           0xFFFFFF7F
+#define   S_038000_PITCH(x)                            (((x) & 0x7FF) << 8)
+#define   G_038000_PITCH(x)                            (((x) >> 8) & 0x7FF)
+#define   C_038000_PITCH                               0xFFF800FF
+#define   S_038000_TEX_WIDTH(x)                        (((x) & 0x1FFF) << 19)
+#define   G_038000_TEX_WIDTH(x)                        (((x) >> 19) & 0x1FFF)
+#define   C_038000_TEX_WIDTH                           0x0007FFFF
+#define R_038004_SQ_TEX_RESOURCE_WORD1_0             0x038004
+#define   S_038004_TEX_HEIGHT(x)                       (((x) & 0x1FFF) << 0)
+#define   G_038004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_038004_TEX_HEIGHT                          0xFFFFE000
+#define   S_038004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 13)
+#define   G_038004_TEX_DEPTH(x)                        (((x) >> 13) & 0x1FFF)
+#define   C_038004_TEX_DEPTH                           0xFC001FFF
+#define   S_038004_DATA_FORMAT(x)                      (((x) & 0x3F) << 26)
+#define   G_038004_DATA_FORMAT(x)                      (((x) >> 26) & 0x3F)
+#define   C_038004_DATA_FORMAT                         0x03FFFFFF
+#define R_038008_SQ_TEX_RESOURCE_WORD2_0             0x038008
+#define   S_038008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_038008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_038008_BASE_ADDRESS                        0x00000000
+#define R_03800C_SQ_TEX_RESOURCE_WORD3_0             0x03800C
+#define   S_03800C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03800C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03800C_MIP_ADDRESS                         0x00000000
+#define R_038010_SQ_TEX_RESOURCE_WORD4_0             0x038010
+#define   S_038010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_038010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_038010_FORMAT_COMP_X                       0xFFFFFFFC
+#define     V_038010_SQ_FORMAT_COMP_UNSIGNED           0x00000000
+#define     V_038010_SQ_FORMAT_COMP_SIGNED             0x00000001
+#define     V_038010_SQ_FORMAT_COMP_UNSIGNED_BIASED    0x00000002
+#define   S_038010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_038010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_038010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_038010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_038010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_038010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_038010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_038010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_038010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_038010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_038010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_038010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define     V_038010_SQ_NUM_FORMAT_NORM                0x00000000
+#define     V_038010_SQ_NUM_FORMAT_INT                 0x00000001
+#define     V_038010_SQ_NUM_FORMAT_SCALED              0x00000002
+#define   S_038010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_038010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_038010_SRF_MODE_ALL                        0xFFFFFBFF
+#define     V_038010_SFR_MODE_ZERO_CLAMP_MINUS_ONE     0x00000000
+#define     V_038010_SFR_MODE_NO_ZERO                  0x00000001
+#define   S_038010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_038010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_038010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_038010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_038010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_038010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_038010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_038010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_038010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_038010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_038010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_038010_DST_SEL_X                           0xFFF8FFFF
+#define     V_038010_SQ_SEL_X                          0x00000000
+#define     V_038010_SQ_SEL_Y                          0x00000001
+#define     V_038010_SQ_SEL_Z                          0x00000002
+#define     V_038010_SQ_SEL_W                          0x00000003
+#define     V_038010_SQ_SEL_0                          0x00000004
+#define     V_038010_SQ_SEL_1                          0x00000005
+#define   S_038010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_038010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_038010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_038010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_038010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_038010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_038010_DST_SEL_W                           0xF1FFFFFF
+#define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_038010_BASE_LEVEL                          0x0FFFFFFF
+#define R_038014_SQ_TEX_RESOURCE_WORD5_0             0x038014
+#define   S_038014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_038014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_038014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_038014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_038014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_038014_BASE_ARRAY                          0xFFFE000F
+#define   S_038014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_038014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_038014_LAST_ARRAY                          0xC001FFFF
+#define R_038018_SQ_TEX_RESOURCE_WORD6_0             0x038018
+#define   S_038018_MPEG_CLAMP(x)                       (((x) & 0x3) << 0)
+#define   G_038018_MPEG_CLAMP(x)                       (((x) >> 0) & 0x3)
+#define   C_038018_MPEG_CLAMP                          0xFFFFFFFC
+#define   S_038018_PERF_MODULATION(x)                  (((x) & 0x7) << 5)
+#define   G_038018_PERF_MODULATION(x)                  (((x) >> 5) & 0x7)
+#define   C_038018_PERF_MODULATION                     0xFFFFFF1F
+#define   S_038018_INTERLACED(x)                       (((x) & 0x1) << 8)
+#define   G_038018_INTERLACED(x)                       (((x) >> 8) & 0x1)
+#define   C_038018_INTERLACED                          0xFFFFFEFF
+#define   S_038018_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_038018_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_038018_TYPE                                0x3FFFFFFF
+#define     V_038010_SQ_TEX_VTX_INVALID_TEXTURE        0x00000000
+#define     V_038010_SQ_TEX_VTX_INVALID_BUFFER         0x00000001
+#define     V_038010_SQ_TEX_VTX_VALID_TEXTURE          0x00000002
+#define     V_038010_SQ_TEX_VTX_VALID_BUFFER           0x00000003
 #define R_038008_SQ_VTX_CONSTANT_WORD2_0             0x038008
 #define   S_038008_BASE_ADDRESS_HI(x)                  (((x) & 0xFF) << 0)
 #define   G_038008_BASE_ADDRESS_HI(x)                  (((x) >> 0) & 0xFF)
@@ -633,6 +761,113 @@
 #define   S_038008_ENDIAN_SWAP(x)                      (((x) & 0x3) << 30)
 #define   G_038008_ENDIAN_SWAP(x)                      (((x) >> 30) & 0x3)
 #define   C_038008_ENDIAN_SWAP                         0x3FFFFFFF
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define     V_03C000_SQ_TEX_WRAP                       0x00000000
+#define     V_03C000_SQ_TEX_MIRROR                     0x00000001
+#define     V_03C000_SQ_TEX_CLAMP_LAST_TEXEL           0x00000002
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL     0x00000003
+#define     V_03C000_SQ_TEX_CLAMP_HALF_BORDER          0x00000004
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER    0x00000005
+#define     V_03C000_SQ_TEX_CLAMP_BORDER               0x00000006
+#define     V_03C000_SQ_TEX_MIRROR_ONCE_BORDER         0x00000007
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x7) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x7)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF1FF
+#define     V_03C000_SQ_TEX_XY_FILTER_POINT            0x00000000
+#define     V_03C000_SQ_TEX_XY_FILTER_BILINEAR         0x00000001
+#define     V_03C000_SQ_TEX_XY_FILTER_BICUBIC          0x00000002
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x7) << 12)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 12) & 0x7)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFF8FFF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 15)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 15) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFE7FFF
+#define     V_03C000_SQ_TEX_Z_FILTER_NONE              0x00000000
+#define     V_03C000_SQ_TEX_Z_FILTER_POINT             0x00000001
+#define     V_03C000_SQ_TEX_Z_FILTER_LINEAR            0x00000002
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 17)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 17) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFF9FFFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 22)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 22) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFF3FFFFF
+#define     V_03C000_SQ_TEX_BORDER_COLOR_TRANS_BLACK   0x00000000
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK  0x00000001
+#define     V_03C000_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE  0x00000002
+#define     V_03C000_SQ_TEX_BORDER_COLOR_REGISTER      0x00000003
+#define   S_03C000_POINT_SAMPLING_CLAMP(x)             (((x) & 0x1) << 24)
+#define   G_03C000_POINT_SAMPLING_CLAMP(x)             (((x) >> 24) & 0x1)
+#define   C_03C000_POINT_SAMPLING_CLAMP                0xFEFFFFFF
+#define   S_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) & 0x1) << 25)
+#define   G_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) >> 25) & 0x1)
+#define   C_03C000_TEX_ARRAY_OVERRIDE                  0xFDFFFFFF
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 26)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 26) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xE3FFFFFF
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER        0x00000000
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESS         0x00000001
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL        0x00000002
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL    0x00000003
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER      0x00000004
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL     0x00000005
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 0x00000006
+#define     V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS       0x00000007
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 29)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 29) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0x9FFFFFFF
+#define     V_03C000_SQ_TEX_CHROMA_KEY_DISABLE         0x00000000
+#define     V_03C000_SQ_TEX_CHROMA_KEY_KILL            0x00000001
+#define     V_03C000_SQ_TEX_CHROMA_KEY_BLEND           0x00000002
+#define   S_03C000_LOD_USES_MINOR_AXIS(x)              (((x) & 0x1) << 31)
+#define   G_03C000_LOD_USES_MINOR_AXIS(x)              (((x) >> 31) & 0x1)
+#define   C_03C000_LOD_USES_MINOR_AXIS                 0x7FFFFFFF
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0x3FF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0x3FF)
+#define   C_03C004_MIN_LOD                             0xFFFFFC00
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0x3FF) << 10)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 10) & 0x3FF)
+#define   C_03C004_MAX_LOD                             0xFFF003FF
+#define   S_03C004_LOD_BIAS(x)                         (((x) & 0xFFF) << 20)
+#define   G_03C004_LOD_BIAS(x)                         (((x) >> 20) & 0xFFF)
+#define   C_03C004_LOD_BIAS                            0x000FFFFF
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0xFFF) << 0)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 0) & 0xFFF)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFFFF000
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 12)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 12) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFFFEFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 13)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 13) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFFFDFFF
+#define   S_03C008_HIGH_PRECISION_FILTER(x)            (((x) & 0x1) << 14)
+#define   G_03C008_HIGH_PRECISION_FILTER(x)            (((x) >> 14) & 0x1)
+#define   C_03C008_HIGH_PRECISION_FILTER               0xFFFFBFFF
+#define   S_03C008_PERF_MIP(x)                         (((x) & 0x7) << 15)
+#define   G_03C008_PERF_MIP(x)                         (((x) >> 15) & 0x7)
+#define   C_03C008_PERF_MIP                            0xFFFC7FFF
+#define   S_03C008_PERF_Z(x)                           (((x) & 0x3) << 18)
+#define   G_03C008_PERF_Z(x)                           (((x) >> 18) & 0x3)
+#define   C_03C008_PERF_Z                              0xFFF3FFFF
+#define   S_03C008_FETCH_4(x)                          (((x) & 0x1) << 26)
+#define   G_03C008_FETCH_4(x)                          (((x) >> 26) & 0x1)
+#define   C_03C008_FETCH_4                             0xFBFFFFFF
+#define   S_03C008_SAMPLE_IS_PCF(x)                    (((x) & 0x1) << 27)
+#define   G_03C008_SAMPLE_IS_PCF(x)                    (((x) >> 27) & 0x1)
+#define   C_03C008_SAMPLE_IS_PCF                       0xF7FFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
 #define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
 #define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
 #define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
-- 
cgit v1.2.3


From f514ad0a9b9bebde0808eadb1e63ea548260be1e Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 28 Jul 2010 11:51:16 +1000
Subject: r600g: use gallium util for float->ui conversion

---
 src/gallium/drivers/r600/r600_screen.h | 13 -------------
 src/gallium/drivers/r600/r600_state.c  | 12 ++++++------
 2 files changed, 6 insertions(+), 19 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 0a0286d96b..7a373cd0ef 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -88,17 +88,4 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 int r600_conv_pipe_format(unsigned pformat, unsigned *format);
 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
 
-union r600_float_to_u32_u {
-	u32	u;
-	float	f;
-};
-
-static inline u32 r600_float_to_u32(float f)
-{
-	union r600_float_to_u32_u c;
-
-	c.f = f;
-	return c.u;
-}
-
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 6503c3740e..367a1f9991 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -579,12 +579,12 @@ static void r600_set_viewport_state(struct pipe_context *ctx,
 		return;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = r600_float_to_u32(state->scale[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = r600_float_to_u32(state->scale[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = r600_float_to_u32(state->scale[2]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = r600_float_to_u32(state->translate[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = r600_float_to_u32(state->translate[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = r600_float_to_u32(state->translate[2]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
-- 
cgit v1.2.3


From 2ab24a6faedb0f9b93055cbf3d52be1120353ee1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 28 Jul 2010 15:26:14 +1000
Subject: r600g: fix up segfault with variation between views and count.

For some reason gallium hands us something with lots of empty views, and
we are expected to deal with it, just do what r300g does for this bit.
---
 src/gallium/drivers/r600/r600_state.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 367a1f9991..2fdcdea14e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -481,18 +481,26 @@ static void r600_set_fragment_sampler_views(struct pipe_context *ctx,
 	struct r600_texture_resource *rtexture;
 	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_sampler_view *tmp;
-	unsigned i;
+	unsigned i, real_num_views = 0;
 
 	if (views == NULL)
 		return;
 
+	for (i = 0; i < count; i++) {
+		if (views[i])
+			real_num_views++;
+	}
+
 	for (i = 0; i < rctx->nps_view; i++) {
 		tmp = &rctx->ps_view[i]->view;
 		pipe_sampler_view_reference(&tmp, NULL);
 		rctx->ps_view[i] = NULL;
 	}
-	rctx->nps_view = count;
+	rctx->nps_view = real_num_views;
 	for (i = 0; i < count; i++) {
+
+		if (!views[i])
+			continue;
 		rtexture = LIST_ENTRY(struct r600_texture_resource, views[i], view);
 		rctx->ps_view[i] = rtexture;
 		tmp = NULL;
@@ -508,18 +516,24 @@ static void r600_set_vertex_sampler_views(struct pipe_context *ctx,
 	struct r600_texture_resource *rtexture;
 	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_sampler_view *tmp;
-	unsigned i;
+	unsigned i, real_num_views = 0;
 
 	if (views == NULL)
 		return;
 
+	for (i = 0; i < count; i++) {
+		if (views[i])
+			real_num_views++;
+	}
 	for (i = 0; i < rctx->nvs_view; i++) {
 		tmp = &rctx->vs_view[i]->view;
 		pipe_sampler_view_reference(&tmp, NULL);
 		rctx->vs_view[i] = NULL;
 	}
-	rctx->nps_view = count;
+	rctx->nvs_view = real_num_views;
 	for (i = 0; i < count; i++) {
+		if (!views[i])
+			continue;
 		rtexture = LIST_ENTRY(struct r600_texture_resource, views[i], view);
 		rctx->vs_view[i] = rtexture;
 		tmp = NULL;
-- 
cgit v1.2.3


From 742ee7935da60dda974795243d2e0fcf31accb59 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 28 Jul 2010 12:18:19 -0400
Subject: r600g: cleanup resource buffer/texture mess

Use a common function, fix the mess it was before.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_buffer.c   |  59 +++++------
 src/gallium/drivers/r600/r600_context.c  |   2 +-
 src/gallium/drivers/r600/r600_draw.c     |   5 +-
 src/gallium/drivers/r600/r600_resource.c |  54 +++++-----
 src/gallium/drivers/r600/r600_resource.h |  35 ++++++-
 src/gallium/drivers/r600/r600_screen.c   |  69 +------------
 src/gallium/drivers/r600/r600_screen.h   |   8 --
 src/gallium/drivers/r600/r600_state.c    |  28 +++---
 src/gallium/drivers/r600/r600_texture.c  | 163 +++++++++++++++++++------------
 src/gallium/drivers/r600/r600_texture.h  |  53 ----------
 10 files changed, 217 insertions(+), 259 deletions(-)
 delete mode 100644 src/gallium/drivers/r600/r600_texture.h

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c
index bc6e336ba7..167d117520 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -32,10 +32,11 @@
 #include "state_tracker/drm_driver.h"
 #include "r600_screen.h"
 #include "r600_context.h"
+#include "r600_resource.h"
 
 extern struct u_resource_vtbl r600_buffer_vtbl;
 
-static u32 r600_domain_from_usage(unsigned usage)
+u32 r600_domain_from_usage(unsigned usage)
 {
 	u32 domain = RADEON_GEM_DOMAIN_GTT;
 
@@ -63,47 +64,47 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 					 const struct pipe_resource *templ)
 {
 	struct r600_screen *rscreen = r600_screen(screen);
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	struct radeon_bo *bo;
 	struct pb_desc desc;
 	/* XXX We probably want a different alignment for buffers and textures. */
 	unsigned alignment = 4096;
 
-	rbuffer = CALLOC_STRUCT(r600_buffer);
+	rbuffer = CALLOC_STRUCT(r600_resource);
 	if (rbuffer == NULL)
 		return NULL;
 
-	rbuffer->b.b = *templ;
-	pipe_reference_init(&rbuffer->b.b.reference, 1);
-	rbuffer->b.b.screen = screen;
-	rbuffer->b.vtbl = &r600_buffer_vtbl;
+	rbuffer->base.b = *templ;
+	pipe_reference_init(&rbuffer->base.b.reference, 1);
+	rbuffer->base.b.screen = screen;
+	rbuffer->base.vtbl = &r600_buffer_vtbl;
 
-	if (rbuffer->b.b.bind & PIPE_BIND_CONSTANT_BUFFER) {
+	if (rbuffer->base.b.bind & PIPE_BIND_CONSTANT_BUFFER) {
 		desc.alignment = alignment;
-		desc.usage = rbuffer->b.b.bind;
-		rbuffer->pb = pb_malloc_buffer_create(rbuffer->b.b.width0,
+		desc.usage = rbuffer->base.b.bind;
+		rbuffer->pb = pb_malloc_buffer_create(rbuffer->base.b.width0,
 						      &desc);
 		if (rbuffer->pb == NULL) {
 			free(rbuffer);
 			return NULL;
 		}
-		return &rbuffer->b.b;
+		return &rbuffer->base.b;
 	}
-	rbuffer->domain = r600_domain_from_usage(rbuffer->b.b.bind);
-	bo = radeon_bo(rscreen->rw, 0, rbuffer->b.b.width0, alignment, NULL);
+	rbuffer->domain = r600_domain_from_usage(rbuffer->base.b.bind);
+	bo = radeon_bo(rscreen->rw, 0, rbuffer->base.b.width0, alignment, NULL);
 	if (bo == NULL) {
 		FREE(rbuffer);
 		return NULL;
 	}
 	rbuffer->bo = bo;
-	return &rbuffer->b.b;
+	return &rbuffer->base.b;
 }
 
 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 					      void *ptr, unsigned bytes,
 					      unsigned bind)
 {
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	struct r600_screen *rscreen = r600_screen(screen);
 	struct pipe_resource templ;
 
@@ -116,20 +117,20 @@ struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 	templ.height0 = 1;
 	templ.depth0 = 1;
 
-	rbuffer = (struct r600_buffer*)r600_buffer_create(screen, &templ);
+	rbuffer = (struct r600_resource*)r600_buffer_create(screen, &templ);
 	if (rbuffer == NULL) {
 		return NULL;
 	}
 	radeon_bo_map(rscreen->rw, rbuffer->bo);
 	memcpy(rbuffer->bo->data, ptr, bytes);
 	radeon_bo_unmap(rscreen->rw, rbuffer->bo);
-	return &rbuffer->b.b;
+	return &rbuffer->base.b;
 }
 
 static void r600_buffer_destroy(struct pipe_screen *screen,
 				struct pipe_resource *buf)
 {
-	struct r600_buffer *rbuffer = (struct r600_buffer*)buf;
+	struct r600_resource *rbuffer = (struct r600_resource*)buf;
 	struct r600_screen *rscreen = r600_screen(screen);
 
 	if (rbuffer->pb) {
@@ -146,7 +147,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 				      struct pipe_transfer *transfer)
 {
-	struct r600_buffer *rbuffer = (struct r600_buffer*)transfer->resource;
+	struct r600_resource *rbuffer = (struct r600_resource*)transfer->resource;
 	struct r600_screen *rscreen = r600_screen(pipe->screen);
 	int write = 0;
 
@@ -166,9 +167,9 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 }
 
 static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
-				       struct pipe_transfer *transfer)
+					struct pipe_transfer *transfer)
 {
-	struct r600_buffer *rbuffer = (struct r600_buffer*)transfer->resource;
+	struct r600_resource *rbuffer = (struct r600_resource*)transfer->resource;
 	struct r600_screen *rscreen = r600_screen(pipe->screen);
 
 	if (rbuffer->pb) {
@@ -188,7 +189,7 @@ unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
 					 struct pipe_resource *buf,
 					 unsigned face, unsigned level)
 {
-	/* XXX */
+	/* FIXME */
 	return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
 }
 
@@ -196,7 +197,7 @@ struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 					      struct winsys_handle *whandle)
 {
 	struct radeon *rw = (struct radeon*)screen->winsys;
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	struct radeon_bo *bo = NULL;
 
 	bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
@@ -204,18 +205,18 @@ struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 		return NULL;
 	}
 
-	rbuffer = CALLOC_STRUCT(r600_buffer);
+	rbuffer = CALLOC_STRUCT(r600_resource);
 	if (rbuffer == NULL) {
 		radeon_bo_decref(rw, bo);
 		return NULL;
 	}
 
-	pipe_reference_init(&rbuffer->b.b.reference, 1);
-	rbuffer->b.b.target = PIPE_BUFFER;
-	rbuffer->b.b.screen = screen;
-	rbuffer->b.vtbl = &r600_buffer_vtbl;
+	pipe_reference_init(&rbuffer->base.b.reference, 1);
+	rbuffer->base.b.target = PIPE_BUFFER;
+	rbuffer->base.b.screen = screen;
+	rbuffer->base.vtbl = &r600_buffer_vtbl;
 	rbuffer->bo = bo;
-	return &rbuffer->b.b;
+	return &rbuffer->base.b;
 }
 
 struct u_resource_vtbl r600_buffer_vtbl =
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 3c5195f79e..f2875f4380 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -29,9 +29,9 @@
 #include <util/u_format.h>
 #include <util/u_memory.h>
 #include <util/u_blitter.h>
-#include "r600_resource.h"
 #include "r600_screen.h"
 #include "r600_context.h"
+#include "r600_resource.h"
 #include "r600d.h"
 
 static void r600_destroy_context(struct pipe_context *context)
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index e0d624889f..8e9d11b855 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -33,6 +33,7 @@
 #include <util/u_memory.h>
 #include "r600_screen.h"
 #include "r600_context.h"
+#include "r600_resource.h"
 #include "r600d.h"
 
 struct r600_draw {
@@ -51,7 +52,7 @@ static int r600_draw_common(struct r600_draw *draw)
 	struct r600_context *rctx = r600_context(draw->ctx);
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *vs_resource;
-	struct r600_buffer *rbuffer;
+	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
 	u32 vgt_dma_index_type, vgt_draw_initiator;
 	int r;
@@ -101,7 +102,7 @@ static int r600_draw_common(struct r600_draw *draw)
 
 	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
 		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
-		rbuffer = (struct r600_buffer*)rctx->vertex_buffer[j].buffer;
+		rbuffer = (struct r600_resource*)rctx->vertex_buffer[j].buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + rctx->vertex_buffer[j].buffer_offset;
 		r = r600_conv_pipe_format(rctx->vertex_elements->elements[i].src_format, &format);
 		if (r)
diff --git a/src/gallium/drivers/r600/r600_resource.c b/src/gallium/drivers/r600/r600_resource.c
index d9aa1df04f..292c5d294d 100644
--- a/src/gallium/drivers/r600/r600_resource.c
+++ b/src/gallium/drivers/r600/r600_resource.c
@@ -26,43 +26,43 @@
 #include "r600_screen.h"
 #include "r600_texture.h"
 
-static struct pipe_resource *
-r600_resource_create(struct pipe_screen *screen,
-                    const struct pipe_resource *templ)
+static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
+						const struct pipe_resource *templ)
 {
-   if (templ->target == PIPE_BUFFER)
-      return r600_buffer_create(screen, templ);
-   else
-      return r600_texture_create(screen, templ);
+	if (templ->target == PIPE_BUFFER) {
+		return r600_buffer_create(screen, templ);
+	} else {
+		return r600_texture_create(screen, templ);
+	}
 }
 
-static struct pipe_resource *
-r600_resource_from_handle(struct pipe_screen * screen,
-			 const struct pipe_resource *templ,
-			 struct winsys_handle *whandle)
+static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * screen,
+							const struct pipe_resource *templ,
+							struct winsys_handle *whandle)
 {
-   if (templ->target == PIPE_BUFFER)
-      return NULL;
-   else
-      return r600_texture_from_handle(screen, templ, whandle);
+	if (templ->target == PIPE_BUFFER) {
+		return NULL;
+	} else {
+		return r600_texture_from_handle(screen, templ, whandle);
+	}
 }
 
 void r600_init_context_resource_functions(struct r600_context *r600)
 {
-   r600->context.get_transfer = u_get_transfer_vtbl;
-   r600->context.transfer_map = u_transfer_map_vtbl;
-   r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
-   r600->context.transfer_unmap = u_transfer_unmap_vtbl;
-   r600->context.transfer_destroy = u_transfer_destroy_vtbl;
-   r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
-   r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
+	r600->context.get_transfer = u_get_transfer_vtbl;
+	r600->context.transfer_map = u_transfer_map_vtbl;
+	r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
+	r600->context.transfer_unmap = u_transfer_unmap_vtbl;
+	r600->context.transfer_destroy = u_transfer_destroy_vtbl;
+	r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
+	r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
 }
 
 void r600_init_screen_resource_functions(struct r600_screen *r600screen)
 {
-   r600screen->screen.resource_create = r600_resource_create;
-   r600screen->screen.resource_from_handle = r600_resource_from_handle;
-   r600screen->screen.resource_get_handle = u_resource_get_handle_vtbl;
-   r600screen->screen.resource_destroy = u_resource_destroy_vtbl;
-   r600screen->screen.user_buffer_create = r600_user_buffer_create;
+	r600screen->screen.resource_create = r600_resource_create;
+	r600screen->screen.resource_from_handle = r600_resource_from_handle;
+	r600screen->screen.resource_get_handle = u_resource_get_handle_vtbl;
+	r600screen->screen.resource_destroy = u_resource_destroy_vtbl;
+	r600screen->screen.user_buffer_create = r600_user_buffer_create;
 }
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 95084a371b..0139a3b777 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -20,14 +20,47 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-
 #ifndef R600_RESOURCE_H
 #define R600_RESOURCE_H
 
+#include "util/u_transfer.h"
+
 struct r600_context;
 struct r600_screen;
 
+/* This gets further specialized into either buffer or texture
+ * structures. Use the vtbl struct to choose between the two
+ * underlying implementations.
+ */
+struct r600_resource {
+	struct u_resource		base;
+	struct radeon_bo		*bo;
+	u32				domain;
+	u32				flink;
+	struct pb_buffer		*pb;
+};
+
+struct r600_resource_texture {
+	struct r600_resource		resource;
+	unsigned long			offset[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			pitch[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			stride[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			layer_size[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			stride_override;
+	unsigned long			size;
+};
+
 void r600_init_context_resource_functions(struct r600_context *r600);
 void r600_init_screen_resource_functions(struct r600_screen *r600screen);
 
+/* r600_buffer */
+u32 r600_domain_from_usage(unsigned usage);
+
+/* r600_texture */
+struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
+					const struct pipe_resource *templ);
+struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
+						const struct pipe_resource *base,
+						struct winsys_handle *whandle);
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index dec6fa8d27..e0d74ca558 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -24,15 +24,14 @@
  *      Jerome Glisse
  *      Corbin Simpson
  */
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include "r600_resource.h"
+#include <stdio.h>
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "util/u_memory.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
 #include "r600_context.h"
 #include "r600_public.h"
-#include <stdio.h>
+#include "r600_resource.h"
 
 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 {
@@ -180,64 +179,6 @@ static boolean r600_is_format_supported(struct pipe_screen* screen,
 	return FALSE;
 }
 
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
-						struct pipe_resource *texture,
-						struct pipe_subresource sr,
-						unsigned usage,
-						const struct pipe_box *box)
-{
-	struct r600_texture *rtex = (struct r600_texture*)texture;
-	struct r600_transfer *trans;
-
-	trans = CALLOC_STRUCT(r600_transfer);
-	if (trans == NULL)
-		return NULL;
-	pipe_resource_reference(&trans->transfer.resource, texture);
-	trans->transfer.sr = sr;
-	trans->transfer.usage = usage;
-	trans->transfer.box = *box;
-	trans->transfer.stride = rtex->stride[sr.level];
-	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
-	return &trans->transfer;
-}
-
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
-				   struct pipe_transfer *trans)
-{
-	pipe_resource_reference(&trans->resource, NULL);
-	FREE(trans);
-}
-
-void* r600_texture_transfer_map(struct pipe_context *ctx,
-				struct pipe_transfer* transfer)
-{
-	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct r600_texture *rtex = (struct r600_texture*)transfer->resource;
-	char *map;
-	enum pipe_format format = rtex->b.b.format;
-
-	map = pipe_buffer_map(ctx, rtex->buffer,
-			      transfer->usage,
-			      &rtransfer->buffer_transfer);
-
-	if (!map) {
-		return NULL;
-	}
-
-	return map + rtransfer->offset +
-		transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
-		transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
-}
-
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
-				 struct pipe_transfer* transfer)
-{
-	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct r600_texture *rtex = (struct r600_texture*)transfer->resource;
-
-	pipe_buffer_unmap(ctx, rtex->buffer, rtransfer->buffer_transfer);
-}
-
 static void r600_destroy_screen(struct pipe_screen* pscreen)
 {
 	struct r600_screen* rscreen = r600_screen(pscreen);
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 7a373cd0ef..9a452ecfe3 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -40,14 +40,6 @@ struct r600_transfer {
 	unsigned			offset;
 };
 
-struct r600_buffer {
-	struct u_resource		b;
-	struct radeon_bo		*bo;
-	u32				domain;
-	u32				flink;
-	struct pb_buffer		*pb;
-};
-
 struct r600_screen {
 	struct pipe_screen		screen;
 	struct radeon			*rw;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 2fdcdea14e..7d67e28c06 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -24,12 +24,12 @@
  *      Jerome Glisse
  */
 #include <stdio.h>
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "util/u_memory.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
 #include "r600_context.h"
+#include "r600_resource.h"
 #include "r600d.h"
 
 
@@ -90,8 +90,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
-	struct r600_texture *rtex;
-	struct r600_buffer *rbuffer;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
 	struct radeon_state *rstate;
 	unsigned level = state->cbufs[0]->level;
 	unsigned pitch, slice;
@@ -99,8 +99,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
 	if (rstate == NULL)
 		return;
-	rtex = (struct r600_texture*)state->cbufs[0]->texture;
-	rbuffer = (struct r600_buffer*)rtex->buffer;
+	rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
+	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -125,8 +125,8 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	radeon_draw_set_new(rctx->draw, rstate);
 	rctx->db = radeon_state_decref(rctx->db);
 	if(state->zsbuf) {
-		rtex = (struct r600_texture*)state->zsbuf->texture;
-		rbuffer = (struct r600_buffer*)rtex->buffer;
+		rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+		rbuffer = &rtex->resource;
 		rctx->db = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
 		if(rctx->db == NULL)
 		     return;
@@ -397,8 +397,8 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_texture_resource *rtexture;
 	const struct util_format_description *desc;
-	struct r600_texture *tmp;
-	struct r600_buffer *rbuffer;
+	struct r600_resource_texture *tmp;
+	struct r600_resource *rbuffer;
 	unsigned format;
 
 	if (r600_conv_pipe_format(texture->format, &format))
@@ -419,8 +419,8 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	pipe_resource_reference(&rtexture->view.texture, texture);
 	rtexture->view.context = ctx;
 
-	tmp = (struct r600_texture*)texture;
-	rbuffer = (struct r600_buffer*)tmp->buffer;
+	tmp = (struct r600_resource_texture*)texture;
+	rbuffer = &tmp->resource;
 	rtexture->state->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rtexture->state->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rtexture->state->nbo = 2;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 1c219a5579..ab20e97948 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -32,16 +32,18 @@
 #include "state_tracker/drm_driver.h"
 #include "r600_screen.h"
 #include "r600_context.h"
-#include "r600_texture.h"
+#include "r600_resource.h"
 #include "r600d.h"
 
 extern struct u_resource_vtbl r600_texture_vtbl;
 
-unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned zslice, unsigned face)
+static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
+					unsigned level, unsigned zslice,
+					unsigned face)
 {
 	unsigned long offset = rtex->offset[level];
 
-	switch (rtex->b.b.target) {
+	switch (rtex->resource.base.b.target) {
 	case PIPE_TEXTURE_3D:
 		assert(face == 0);
 		return offset + zslice * rtex->layer_size[level];
@@ -54,9 +56,9 @@ unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
 	}
 }
 
-static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_texture *rtex)
+static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource_texture *rtex)
 {
-	struct pipe_resource *ptex = &rtex->b.b;
+	struct pipe_resource *ptex = &rtex->resource.base.b;
 	unsigned long w, h, stride, size, layer_size, i, offset;
 
 	for (i = 0, offset = 0; i <= ptex->last_level; i++) {
@@ -80,43 +82,44 @@ static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_texture
 }
 
 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
-					  const struct pipe_resource *templ)
+						const struct pipe_resource *templ)
 {
-	struct r600_texture *rtex = CALLOC_STRUCT(r600_texture);
+	struct r600_resource_texture *rtex;
+	struct r600_resource *resource;
 	struct r600_screen *rscreen = r600_screen(screen);
-	struct pipe_resource templ_buf;
 
+	rtex = CALLOC_STRUCT(r600_resource_texture);
 	if (!rtex) {
 		return NULL;
 	}
-	rtex->b.b = *templ;
-	rtex->b.vtbl = &r600_texture_vtbl;
-	pipe_reference_init(&rtex->b.b.reference, 1);
-	rtex->b.b.screen = screen;
+	resource = &rtex->resource;
+	resource->base.b = *templ;
+	resource->base.vtbl = &r600_texture_vtbl;
+	pipe_reference_init(&resource->base.b.reference, 1);
+	resource->base.b.screen = screen;
 	r600_setup_miptree(rscreen, rtex);
 
-	memset(&templ_buf, 0, sizeof(struct pipe_resource));
-	templ_buf.target = PIPE_BUFFER;
-	templ_buf.format = PIPE_FORMAT_R8_UNORM;
-	templ_buf.usage = templ->usage;
-	templ_buf.bind = templ->bind;
-	templ_buf.width0 = rtex->size;
-	templ_buf.height0 = 1;
-	templ_buf.depth0 = 1;
-
-	rtex->buffer = screen->resource_create(screen, &templ_buf);
-	if (!rtex->buffer) {
+	/* FIXME alignment 4096 enought ? too much ? */
+	resource->domain = r600_domain_from_usage(resource->base.b.bind);
+	resource->bo = radeon_bo(rscreen->rw, 0, rtex->size, 4096, NULL);
+	if (resource->bo == NULL) {
 		FREE(rtex);
 		return NULL;
 	}
-	return &rtex->b.b;
+
+	return &resource->base.b;
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
-	struct r600_texture *rtex = (struct r600_texture*)ptex;
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
+	struct r600_resource *resource = &rtex->resource;
+	struct r600_screen *rscreen = r600_screen(screen);
 
+	if (resource->bo) {
+		radeon_bo_decref(rscreen->rw, resource->bo);
+	}
 	FREE(rtex);
 }
 
@@ -125,7 +128,7 @@ static struct pipe_surface *r600_get_tex_surface(struct pipe_screen *screen,
 						unsigned face, unsigned level,
 						unsigned zslice, unsigned flags)
 {
-	struct r600_texture *rtex = (struct r600_texture*)texture;
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
 	struct pipe_surface *surface = CALLOC_STRUCT(pipe_surface);
 	unsigned long offset;
 
@@ -153,71 +156,111 @@ static void r600_tex_surface_destroy(struct pipe_surface *surface)
 }
 
 struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
-					       const struct pipe_resource *base,
+					       const struct pipe_resource *templ,
 					       struct winsys_handle *whandle)
 {
-	struct pipe_resource *buffer;
-	struct r600_texture *rtex;
+	struct radeon *rw = (struct radeon*)screen->winsys;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *resource;
+	struct radeon_bo *bo = NULL;
 
-	buffer = r600_buffer_from_handle(screen, whandle);
-	if (buffer == NULL) {
+	bo = radeon_bo(rw, whandle->handle, 0, 0, NULL);
+	if (bo == NULL) {
 		return NULL;
 	}
 
 	/* Support only 2D textures without mipmaps */
-	if (base->target != PIPE_TEXTURE_2D || base->depth0 != 1 || base->last_level != 0)
+	if (templ->target != PIPE_TEXTURE_2D || templ->depth0 != 1 || templ->last_level != 0)
 		return NULL;
 
-	rtex = CALLOC_STRUCT(r600_texture);
+	rtex = CALLOC_STRUCT(r600_resource_texture);
 	if (rtex == NULL)
 		return NULL;
 
-	/* one ref already taken */
-	rtex->buffer = buffer;
-
-	rtex->b.b = *base;
-	rtex->b.vtbl = &r600_texture_vtbl;
-	pipe_reference_init(&rtex->b.b.reference, 1);
-	rtex->b.b.screen = screen;
+	resource = &rtex->resource;
+	resource->base.b = *templ;
+	resource->base.vtbl = &r600_texture_vtbl;
+	pipe_reference_init(&resource->base.b.reference, 1);
+	resource->base.b.screen = screen;
+	resource->bo = bo;
 	rtex->stride_override = whandle->stride;
-	rtex->pitch[0] = whandle->stride / util_format_get_blocksize(base->format);
+	rtex->pitch[0] = whandle->stride / util_format_get_blocksize(templ->format);
 	rtex->stride[0] = whandle->stride;
 	rtex->offset[0] = 0;
-	rtex->size = align(rtex->stride[0] * base->height0, 32);
+	rtex->size = align(rtex->stride[0] * templ->height0, 32);
 
-	return &rtex->b.b;
+	return &resource->base.b;
 }
 
-static boolean r600_texture_get_handle(struct pipe_screen* screen,
-				       struct pipe_resource *texture,
-				       struct winsys_handle *whandle)
+static unsigned int r600_texture_is_referenced(struct pipe_context *context,
+						struct pipe_resource *texture,
+						unsigned face, unsigned level)
 {
-	struct r600_screen *rscreen = r600_screen(screen);
-	struct r600_texture* rtex = (struct r600_texture*)texture;
+	/* FIXME */
+	return PIPE_REFERENCED_FOR_READ | PIPE_REFERENCED_FOR_WRITE;
+}
 
-	if (!rtex) {
-		return FALSE;
-	}
+struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
+						struct pipe_resource *texture,
+						struct pipe_subresource sr,
+						unsigned usage,
+						const struct pipe_box *box)
+{
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+	struct r600_transfer *trans;
 
-	whandle->stride = rtex->stride[0];
+	trans = CALLOC_STRUCT(r600_transfer);
+	if (trans == NULL)
+		return NULL;
+	pipe_resource_reference(&trans->transfer.resource, texture);
+	trans->transfer.sr = sr;
+	trans->transfer.usage = usage;
+	trans->transfer.box = *box;
+	trans->transfer.stride = rtex->stride[sr.level];
+	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
+	return &trans->transfer;
+}
+
+void r600_texture_transfer_destroy(struct pipe_context *ctx,
+				   struct pipe_transfer *trans)
+{
+	pipe_resource_reference(&trans->resource, NULL);
+	FREE(trans);
+}
+
+void* r600_texture_transfer_map(struct pipe_context *ctx,
+				struct pipe_transfer* transfer)
+{
+	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+	struct r600_resource *resource;
+	enum pipe_format format = transfer->resource->format;
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	char *map;
 
-	r600_buffer_get_handle(rscreen->rw, rtex->buffer, whandle);
+	resource = (struct r600_resource *)transfer->resource;
+	if (radeon_bo_map(rscreen->rw, resource->bo)) {
+		return NULL;
+	}
+	map = resource->bo->data;
 
-	return TRUE;
+	return map + rtransfer->offset +
+		transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
+		transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 }
 
-static unsigned int r600_texture_is_referenced(struct pipe_context *context,
-						struct pipe_resource *texture,
-						unsigned face, unsigned level)
+void r600_texture_transfer_unmap(struct pipe_context *ctx,
+				 struct pipe_transfer* transfer)
 {
-	struct r600_texture *rtex = (struct r600_texture*)texture;
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_resource *resource;
 
-	return r600_buffer_is_referenced_by_cs(context, rtex->buffer, face, level);
+	resource = (struct r600_resource *)transfer->resource;
+	radeon_bo_unmap(rscreen->rw, resource->bo);
 }
 
 struct u_resource_vtbl r600_texture_vtbl =
 {
-	r600_texture_get_handle,	/* get_handle */
+	u_default_resource_get_handle,	/* get_handle */
 	r600_texture_destroy,		/* resource_destroy */
 	r600_texture_is_referenced,	/* is_resource_referenced */
 	r600_texture_get_transfer,	/* get_transfer */
diff --git a/src/gallium/drivers/r600/r600_texture.h b/src/gallium/drivers/r600/r600_texture.h
deleted file mode 100644
index 9bc08d6b04..0000000000
--- a/src/gallium/drivers/r600/r600_texture.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef R600_TEXTURE_H
-#define R600_TEXTURE_H
-
-#include <pipe/p_state.h>
-
-struct r600_texture {
-	struct u_resource		b;
-	unsigned long			offset[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			pitch[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			stride[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			layer_size[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			stride_override;
-	unsigned long			size;
-	struct pipe_resource		*buffer;
-};
-
-struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
-					  const struct pipe_resource *templ);
-unsigned long r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned zslice, unsigned face);
-struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
-					       const struct pipe_resource *base,
-					       struct winsys_handle *whandle);
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-
-/* This should be implemented by winsys. */
-boolean r600_buffer_get_handle(struct radeon *rw,
-			       struct pipe_resource *buf,
-			       struct winsys_handle *whandle);
-
-
-#endif
-- 
cgit v1.2.3


From 6f0f6c64596b7bbbfa96e8af6715565e37efa91e Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 28 Jul 2010 19:33:50 -0400
Subject: r600g: split pipe state creating/binding from hw state creation

Split hw vs pipe states creation handling as hw states group doesn't
match pipe state group exactly. Right now be dumb about that and
rebuild all hw states on each draw call. More optimization on that
side coming.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c     |   48 +-
 src/gallium/drivers/r600/r600_buffer.c   |    1 +
 src/gallium/drivers/r600/r600_context.c  |  152 ++--
 src/gallium/drivers/r600/r600_context.h  |  147 +++-
 src/gallium/drivers/r600/r600_draw.c     |   34 +-
 src/gallium/drivers/r600/r600_resource.c |    1 -
 src/gallium/drivers/r600/r600_shader.c   |   47 +-
 src/gallium/drivers/r600/r600_state.c    | 1273 +++++++++++++++++++-----------
 src/gallium/winsys/r600/drm/r600_drm.c   |    4 +-
 9 files changed, 1086 insertions(+), 621 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 1dcb19babc..cc37227ead 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -34,31 +34,37 @@
 
 static void r600_blitter_save_states(struct r600_context *rctx)
 {
-	util_blitter_save_blend(rctx->blitter,
-					rctx->draw->state[R600_BLEND]);
-	util_blitter_save_depth_stencil_alpha(rctx->blitter,
-					rctx->draw->state[R600_DSA]);
-	util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref);
-	util_blitter_save_rasterizer(rctx->blitter,
-					rctx->draw->state[R600_RASTERIZER]);
-	util_blitter_save_fragment_shader(rctx->blitter,
-					rctx->ps_shader);
-	util_blitter_save_vertex_shader(rctx->blitter,
-					rctx->vs_shader);
-	util_blitter_save_vertex_elements(rctx->blitter,
-					rctx->vertex_elements);
-	util_blitter_save_viewport(rctx->blitter,
-					&rctx->viewport);
+	util_blitter_save_blend(rctx->blitter, rctx->blend);
+	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
+	if (rctx->stencil_ref) {
+		util_blitter_save_stencil_ref(rctx->blitter,
+					&rctx->stencil_ref->state.stencil_ref);
+	}
+	util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer);
+	util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
+	util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
+	util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
+	if (rctx->viewport) {
+		util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
+	}
 	/* XXX util_blitter_save_clip(rctx->blitter, &rctx->clip); */
 	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
-					 rctx->vertex_buffer);
+					rctx->vertex_buffer);
+
+	/* remove ptr so they don't get deleted */
+	rctx->blend = NULL;
+	rctx->vs_shader = NULL;
+	rctx->ps_shader = NULL;
+	rctx->rasterizer = NULL;
+	rctx->dsa = NULL;
+	rctx->vertex_elements = NULL;
 }
 
 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 		       const float *rgba, double depth, unsigned stencil)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->fb_state;
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
 	r600_blitter_save_states(rctx);
 	util_blitter_clear(rctx->blitter, fb->width, fb->height,
@@ -73,12 +79,14 @@ static void r600_clear_render_target(struct pipe_context *pipe,
 				     unsigned width, unsigned height)
 {
 	struct r600_context *rctx = r600_context(pipe);
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
 	r600_blitter_save_states(rctx);
-	util_blitter_save_framebuffer(rctx->blitter, &rctx->fb_state);
+	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
 					 dstx, dsty, width, height);
+R600_ERR("vtx elem %p\n", rctx->vertex_elements);
 }
 
 static void r600_clear_depth_stencil(struct pipe_context *pipe,
@@ -90,12 +98,14 @@ static void r600_clear_depth_stencil(struct pipe_context *pipe,
 				     unsigned width, unsigned height)
 {
 	struct r600_context *rctx = r600_context(pipe);
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
 	r600_blitter_save_states(rctx);
-	util_blitter_save_framebuffer(rctx->blitter, &rctx->fb_state);
+	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
 					 dstx, dsty, width, height);
+R600_ERR("vtx elem %p\n", rctx->vertex_elements);
 }
 
 static void r600_resource_copy_region(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/r600/r600_buffer.c b/src/gallium/drivers/r600/r600_buffer.c
index 167d117520..7829a479c2 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -141,6 +141,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 	if (rbuffer->bo) {
 		radeon_bo_decref(rscreen->rw, rbuffer->bo);
 	}
+	memset(rbuffer, 0, sizeof(struct r600_resource));
 	FREE(rbuffer);
 }
 
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index f2875f4380..4c7b67ea52 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -220,9 +220,9 @@ static void r600_init_config(struct r600_context *rctx)
 	printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
 	printf("num_es_stack_entries : %d\n", num_es_stack_entries);
 
-	rctx->config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
+	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
 
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
 	case CHIP_RV610:
 	case CHIP_RV620:
@@ -231,75 +231,75 @@ static void r600_init_config(struct r600_context *rctx)
 	case CHIP_RV710:
 		break;
 	default:
-		rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 		break;
 	}
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	rctx->config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 
-	rctx->config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-	rctx->config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-	rctx->config->states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-	rctx->config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	rctx->config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(rctx->config);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+	rctx->hw_states.config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+	rctx->hw_states.config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+	rctx->hw_states.config->states[R600_CONFIG__SX_MISC] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+	rctx->hw_states.config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
+	radeon_state_pm4(rctx->hw_states.config);
 }
 
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
@@ -333,19 +333,19 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 		return NULL;
 	}
 
-	rctx->cb_cntl = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0000;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
-	rctx->cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
-	rctx->cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	radeon_state_pm4(rctx->cb_cntl);
+	rctx->hw_states.cb_cntl = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0000;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
+	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
+	radeon_state_pm4(rctx->hw_states.cb_cntl);
 
 	r600_init_config(rctx);
 
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 30f33f757e..1f03b202ee 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -34,21 +34,74 @@
 #include "r600_shader.h"
 
 /* XXX move this to a more appropriate place */
-struct r600_vertex_elements_state
-{
-	unsigned count;
-	struct pipe_vertex_element elements[32];
+union pipe_states {
+	struct pipe_rasterizer_state		rasterizer;
+	struct pipe_poly_stipple		poly_stipple;
+	struct pipe_scissor_state		scissor;
+	struct pipe_clip_state			clip;
+	struct pipe_shader_state		shader;
+	struct pipe_depth_state			depth;
+	struct pipe_stencil_state		stencil;
+	struct pipe_alpha_state			alpha;
+	struct pipe_depth_stencil_alpha_state	dsa;
+	struct pipe_blend_state			blend;
+	struct pipe_blend_color			blend_color;
+	struct pipe_stencil_ref			stencil_ref;
+	struct pipe_framebuffer_state		framebuffer;
+	struct pipe_sampler_state		sampler;
+	struct pipe_sampler_view		sampler_view;
+	struct pipe_viewport_state		viewport;
 };
 
-struct r600_pipe_shader {
-	struct r600_shader			shader;
-	struct radeon_bo			*bo;
-	struct radeon_state			*state;
+enum pipe_state_type {
+	pipe_rasterizer_type = 1,
+	pipe_poly_stipple_type,
+	pipe_scissor_type,
+	pipe_clip_type,
+	pipe_shader_type,
+	pipe_depth_type,
+	pipe_stencil_type,
+	pipe_alpha_type,
+	pipe_dsa_type,
+	pipe_blend_type,
+	pipe_stencil_ref_type,
+	pipe_framebuffer_type,
+	pipe_sampler_type,
+	pipe_sampler_view_type,
+	pipe_viewport_type,
+	pipe_type_count
 };
 
-struct r600_texture_resource {
-	struct pipe_sampler_view		view;
-	struct radeon_state			*state;
+struct r600_context_state {
+	union pipe_states		state;
+	unsigned			refcount;
+	unsigned			type;
+	struct radeon_state		*rstate;
+	struct r600_shader		shader;
+	struct radeon_bo		*bo;
+};
+
+struct r600_vertex_element
+{
+	unsigned			refcount;
+	unsigned			count;
+	struct pipe_vertex_element	elements[32];
+};
+
+struct r600_context_hw_states {
+	struct radeon_state	*rasterizer;
+	struct radeon_state	*scissor;
+	struct radeon_state	*dsa;
+	struct radeon_state	*blend;
+	struct radeon_state	*viewport;
+	struct radeon_state	*cb0;
+	struct radeon_state	*config;
+	struct radeon_state	*cb_cntl;
+	struct radeon_state	*db;
+	unsigned		ps_nresource;
+	unsigned		ps_nsampler;
+	struct radeon_state	*ps_resource[160];
+	struct radeon_state	*ps_sampler[16];
 };
 
 struct r600_context {
@@ -56,9 +109,11 @@ struct r600_context {
 	struct r600_screen		*screen;
 	struct radeon			*rw;
 	struct radeon_ctx		*ctx;
-	struct radeon_state		*cb_cntl;
-	struct radeon_state		*db;
-	struct radeon_state		*config;
+	struct blitter_context		*blitter;
+	struct radeon_draw		*draw;
+	/* hw states */
+	struct r600_context_hw_states	hw_states;
+#if 0
 	struct r600_pipe_shader		*ps_shader;
 	struct r600_pipe_shader		*vs_shader;
 	unsigned			nps_sampler;
@@ -71,12 +126,57 @@ struct r600_context {
 	unsigned			nvertex_buffer;
 	struct r600_vertex_elements_state *vertex_elements;
 	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
-	struct blitter_context		*blitter;
 	struct pipe_stencil_ref		stencil_ref;
 	struct pipe_framebuffer_state	fb_state;
-	struct radeon_draw		*draw;
 	struct pipe_viewport_state	viewport;
+#endif
+	/* pipe states */
+	unsigned			flat_shade;
+	unsigned			ps_nsampler;
+	unsigned			vs_nsampler;
+	unsigned			ps_nsampler_view;
+	unsigned			vs_nsampler_view;
+	unsigned			nvertex_buffer;
+	struct r600_context_state	*rasterizer;
+	struct r600_context_state	*poly_stipple;
+	struct r600_context_state	*scissor;
+	struct r600_context_state	*clip;
+	struct r600_context_state	*ps_shader;
+	struct r600_context_state	*vs_shader;
+	struct r600_context_state	*depth;
+	struct r600_context_state	*stencil;
+	struct r600_context_state	*alpha;
+	struct r600_context_state	*dsa;
+	struct r600_context_state	*blend;
+	struct r600_context_state	*stencil_ref;
+	struct r600_context_state	*viewport;
+	struct r600_context_state	*framebuffer;
+	struct r600_context_state	*ps_sampler[PIPE_MAX_ATTRIBS];
+	struct r600_context_state	*vs_sampler[PIPE_MAX_ATTRIBS];
+	struct r600_context_state	*ps_sampler_view[PIPE_MAX_ATTRIBS];
+	struct r600_context_state	*vs_sampler_view[PIPE_MAX_ATTRIBS];
+	struct r600_vertex_element	*vertex_elements;
+	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
+};
+
+#if 0
+struct r600_vertex_elements_state
+{
+	unsigned count;
+	struct pipe_vertex_element	elements[32];
+};
+
+struct r600_pipe_shader {
+	struct r600_shader		shader;
+	struct radeon_bo		*bo;
+	struct radeon_state		*state;
+};
+
+struct r600_texture_resource {
+	struct pipe_sampler_view	view;
+	struct radeon_state		*state;
 };
+#endif
 
 /* Convenience cast wrapper. */
 static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
@@ -84,6 +184,12 @@ static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
     return (struct r600_context*)pipe;
 }
 
+struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state);
+struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate);
+struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate);
+
+int r600_context_hw_states(struct r600_context *rctx);
+
 void r600_draw_arrays(struct pipe_context *ctx, unsigned mode,
 			unsigned start, unsigned count);
 void r600_draw_elements(struct pipe_context *ctx,
@@ -101,10 +207,11 @@ void r600_init_state_functions(struct r600_context *rctx);
 void r600_init_query_functions(struct r600_context* rctx);
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv);
 
-void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *rpshader);
-struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx,
-						const struct tgsi_token *tokens);
-int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader);
+int r600_pipe_shader_create(struct pipe_context *ctx,
+			struct r600_context_state *rstate,
+			const struct tgsi_token *tokens);
+int r600_pipe_shader_update(struct pipe_context *ctx,
+				struct r600_context_state *rstate);
 
 #define R600_ERR(fmt, args...) \
 	fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 8e9d11b855..b248beaf8c 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -55,8 +55,12 @@ static int r600_draw_common(struct r600_draw *draw)
 	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
 	u32 vgt_dma_index_type, vgt_draw_initiator;
+	struct pipe_vertex_buffer *vertex_buffer;
 	int r;
 
+	r = r600_context_hw_states(rctx);
+	if (r)
+		return r;
 	switch (draw->index_size) {
 	case 2:
 		vgt_draw_initiator = 0;
@@ -84,26 +88,18 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->vs_shader->state);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->ps_shader->state);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->cb_cntl);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->db);
+	r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->config);
+	r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
 	if (r)
 		return r;
 
 	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
 		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
-		rbuffer = (struct r600_resource*)rctx->vertex_buffer[j].buffer;
-		offset = rctx->vertex_elements->elements[i].src_offset + rctx->vertex_buffer[j].buffer_offset;
+		vertex_buffer = &rctx->vertex_buffer[j];
+		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
+		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		r = r600_conv_pipe_format(rctx->vertex_elements->elements[i].src_format, &format);
 		if (r)
 			return r;
@@ -114,7 +110,7 @@ static int r600_draw_common(struct r600_draw *draw)
 		vs_resource->nbo = 1;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(rctx->vertex_buffer[j].stride) |
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 								S_038008_DATA_FORMAT(format);
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
@@ -126,17 +122,19 @@ static int r600_draw_common(struct r600_draw *draw)
 		if (r)
 			return r;
 	}
+#if 0
 	/* setup texture sampler & resource */
-	for (i = 0 ; i < rctx->nps_sampler; i++) {
-		r = radeon_draw_set_new(rctx->draw, rctx->ps_sampler[i]);
+	for (i = 0 ; i < rctx->ps_nsampler; i++) {
+		r = radeon_draw_set_new(rctx->draw, rctx->ps_sampler[i]->rstate);
 		if (r)
 			return r;
 	}
-	for (i = 0 ; i < rctx->nps_view; i++) {
-		r = radeon_draw_set_new(rctx->draw, rctx->ps_view[i]->state);
+	for (i = 0 ; i < rctx->ps_nsampler_view; i++) {
+		r = radeon_draw_set_new(rctx->draw, rctx->ps_sampler_view[i]->rstate);
 		if (r)
 			return r;
 	}
+#endif
 	/* FIXME start need to change winsys */
 	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
 	if (draw->draw == NULL)
diff --git a/src/gallium/drivers/r600/r600_resource.c b/src/gallium/drivers/r600/r600_resource.c
index 292c5d294d..8dc411ef40 100644
--- a/src/gallium/drivers/r600/r600_resource.c
+++ b/src/gallium/drivers/r600/r600_resource.c
@@ -24,7 +24,6 @@
 #include "r600_context.h"
 #include "r600_resource.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
 
 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 						const struct pipe_resource *templ)
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 3909c704e7..8837a7272b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -98,43 +98,40 @@ static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shad
 	return r600_bc_build(&shader->bc);
 }
 
-struct r600_pipe_shader *r600_pipe_shader_create(struct pipe_context *ctx,
-						const struct tgsi_token *tokens)
+int r600_pipe_shader_create(struct pipe_context *ctx,
+			struct r600_context_state *rpshader,
+			const struct tgsi_token *tokens)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_pipe_shader *rpshader = CALLOC_STRUCT(r600_pipe_shader);
 	int r;
 
 fprintf(stderr, "--------------------------------------------------------------\n");
 tgsi_dump(tokens, 0);
 	if (rpshader == NULL)
-		return NULL;
+		return -ENOMEM;
 	rpshader->shader.family = radeon_get_family(rscreen->rw);
 	r = r600_shader_from_tgsi(tokens, &rpshader->shader);
 	if (r) {
 		R600_ERR("translation from TGSI failed !\n");
-		goto out_err;
+		return r;
 	}
 	r = r600_bc_build(&rpshader->shader.bc);
 	if (r) {
 		R600_ERR("building bytecode failed !\n");
-		goto out_err;
+		return r;
 	}
 fprintf(stderr, "______________________________________________________________\n");
-	return rpshader;
-out_err:
-	free(rpshader);
-	return NULL;
+	return 0;
 }
 
-static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
 	unsigned i, j, tmp;
 
-	rpshader->state = radeon_state_decref(rpshader->state);
+	rpshader->rstate = radeon_state_decref(rpshader->rstate);
 	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
@@ -150,22 +147,22 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
 	}
 	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
 	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
-	rpshader->state = state;
-	rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->state->nbo = 2;
-	rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate = state;
+	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->nbo = 2;
+	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
-static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
 	unsigned i, tmp;
 
-	rpshader->state = radeon_state_decref(rpshader->state);
+	rpshader->rstate = radeon_state_decref(rpshader->rstate);
 	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
@@ -180,14 +177,14 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
 	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
-	rpshader->state = state;
-	rpshader->state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->state->nbo = 1;
-	rpshader->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate = state;
+	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->nbo = 1;
+	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
-static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
@@ -221,7 +218,7 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *r
 	return r;
 }
 
-int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_pipe_shader *rpshader)
+int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	int r;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 7d67e28c06..0f1e1cd761 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -32,18 +32,557 @@
 #include "r600_resource.h"
 #include "r600d.h"
 
+static void *r600_create_blend_state(struct pipe_context *ctx,
+					const struct pipe_blend_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_blend_type, state);
+}
+
+static void *r600_create_dsa_state(struct pipe_context *ctx,
+					const struct pipe_depth_stencil_alpha_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_dsa_type, state);
+}
+
+static void *r600_create_rs_state(struct pipe_context *ctx,
+					const struct pipe_rasterizer_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_rasterizer_type, state);
+}
+
+static void *r600_create_sampler_state(struct pipe_context *ctx,
+					const struct pipe_sampler_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_sampler_type, state);
+}
+
+static void r600_sampler_view_destroy(struct pipe_context *ctx,
+				      struct pipe_sampler_view *state)
+{
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	r600_context_state_decref(rstate);
+}
+
+static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
+							struct pipe_resource *texture,
+							const struct pipe_sampler_view *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_sampler_type, state);
+	pipe_reference(NULL, &texture->reference);
+	rstate->state.sampler_view.texture = texture;
+	rstate->state.sampler_view.reference.count = 1;
+	return &rstate->state.sampler_view;
+}
+
+static void *r600_create_shader_state(struct pipe_context *ctx,
+					const struct pipe_shader_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	return r600_context_state(rctx, pipe_shader_type, state);
+}
+
+static void *r600_create_vertex_elements(struct pipe_context *ctx,
+				unsigned count,
+				const struct pipe_vertex_element *elements)
+{
+	struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
+
+	assert(count < 32);
+	v->count = count;
+	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
+	v->refcount = 1;
+	return v;
+}
+
+static void r600_bind_state(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	if (state == NULL)
+		return;
+	switch (rstate->type) {
+	case pipe_rasterizer_type:
+		rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
+		rctx->rasterizer = r600_context_state_incref(rstate);
+		break;
+	case pipe_poly_stipple_type:
+		rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
+		rctx->poly_stipple = r600_context_state_incref(rstate);
+		break;
+	case pipe_scissor_type:
+		rctx->scissor = r600_context_state_decref(rctx->scissor);
+		rctx->scissor = r600_context_state_incref(rstate);
+		break;
+	case pipe_clip_type:
+		rctx->clip = r600_context_state_decref(rctx->clip);
+		rctx->clip = r600_context_state_incref(rstate);
+		break;
+	case pipe_depth_type:
+		rctx->depth = r600_context_state_decref(rctx->depth);
+		rctx->depth = r600_context_state_incref(rstate);
+		break;
+	case pipe_stencil_type:
+		rctx->stencil = r600_context_state_decref(rctx->stencil);
+		rctx->stencil = r600_context_state_incref(rstate);
+		break;
+	case pipe_alpha_type:
+		rctx->alpha = r600_context_state_decref(rctx->alpha);
+		rctx->alpha = r600_context_state_incref(rstate);
+		break;
+	case pipe_dsa_type:
+		rctx->dsa = r600_context_state_decref(rctx->dsa);
+		rctx->dsa = r600_context_state_incref(rstate);
+		break;
+	case pipe_blend_type:
+		rctx->blend = r600_context_state_decref(rctx->blend);
+		rctx->blend = r600_context_state_incref(rstate);
+		break;
+	case pipe_framebuffer_type:
+		rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
+		rctx->framebuffer = r600_context_state_incref(rstate);
+		break;
+	case pipe_stencil_ref_type:
+		rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
+		rctx->stencil_ref = r600_context_state_incref(rstate);
+		break;
+	case pipe_viewport_type:
+		rctx->viewport = r600_context_state_decref(rctx->viewport);
+		rctx->viewport = r600_context_state_incref(rstate);
+		break;
+	case pipe_shader_type:
+	case pipe_sampler_type:
+	case pipe_sampler_view_type:
+	default:
+		R600_ERR("invalid type %d\n", rstate->type);
+		return;
+	}
+}
+
+static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
+	rctx->ps_shader = r600_context_state_incref(rstate);
+}
+
+static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
+
+	rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
+	rctx->vs_shader = r600_context_state_incref(rstate);
+}
+
+static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
+{
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	if (v == NULL)
+		return;
+	if (--v->refcount)
+		return;
+	free(v);
+}
+
+static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+
+	r600_delete_vertex_element(ctx, rctx->vertex_elements);
+	rctx->vertex_elements = v;
+	if (v) {
+		v->refcount++;
+	}
+}
+
+static void r600_bind_ps_sampler(struct pipe_context *ctx,
+					unsigned count, void **states)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->ps_nsampler; i++) {
+		rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)states[i];
+		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
+	}
+	rctx->ps_nsampler = count;
+}
+
+static void r600_bind_vs_sampler(struct pipe_context *ctx,
+					unsigned count, void **states)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->vs_nsampler; i++) {
+		rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)states[i];
+		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
+	}
+	rctx->vs_nsampler = count;
+}
 
 static void r600_delete_state(struct pipe_context *ctx, void *state)
 {
-	struct radeon_state *rstate = state;
+	struct r600_context_state *rstate = (struct r600_context_state *)state;
 
-	radeon_state_decref(rstate);
+	r600_context_state_decref(rstate);
 }
 
-static void *r600_create_blend_state(struct pipe_context *ctx,
-					const struct pipe_blend_state *state)
+static void r600_set_blend_color(struct pipe_context *ctx,
+					const struct pipe_blend_color *color)
+{
+}
+
+static void r600_set_clip_state(struct pipe_context *ctx,
+				const struct pipe_clip_state *state)
+{
+}
+
+static void r600_set_constant_buffer(struct pipe_context *ctx,
+					uint shader, uint index,
+					struct pipe_resource *buffer)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	unsigned nconstant = 0, i, type, id;
+	struct radeon_state *rstate;
+	struct pipe_transfer *transfer;
+	u32 *ptr;
+
+	switch (shader) {
+	case PIPE_SHADER_VERTEX:
+		id = R600_VS_CONSTANT;
+		type = R600_VS_CONSTANT_TYPE;
+		break;
+	case PIPE_SHADER_FRAGMENT:
+		id = R600_PS_CONSTANT;
+		type = R600_PS_CONSTANT_TYPE;
+		break;
+	default:
+		fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
+		return;
+	}
+	if (buffer && buffer->width0 > 0) {
+		nconstant = buffer->width0 / 16;
+		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
+		if (ptr == NULL)
+			return;
+		for (i = 0; i < nconstant; i++) {
+			rstate = radeon_state(rscreen->rw, type, id + i);
+			if (rstate == NULL)
+				return;
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
+			if (radeon_state_pm4(rstate))
+				return;
+			if (radeon_draw_set_new(rctx->draw, rstate))
+				return;
+		}
+		pipe_buffer_unmap(ctx, buffer, transfer);
+	}
+}
+
+static void r600_set_ps_sampler_view(struct pipe_context *ctx,
+					unsigned count,
+					struct pipe_sampler_view **views)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->ps_nsampler_view; i++) {
+		rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)views[i];
+		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
+	}
+	rctx->ps_nsampler_view = count;
+}
+
+static void r600_set_vs_sampler_view(struct pipe_context *ctx,
+					unsigned count,
+					struct pipe_sampler_view **views)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+	unsigned i;
+
+	for (i = 0; i < rctx->vs_nsampler_view; i++) {
+		rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
+	}
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)views[i];
+		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
+	}
+	rctx->vs_nsampler_view = count;
+}
+
+static void r600_set_framebuffer_state(struct pipe_context *ctx,
+					const struct pipe_framebuffer_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+static void r600_set_polygon_stipple(struct pipe_context *ctx,
+					 const struct pipe_poly_stipple *state)
+{
+}
+
+static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
+{
+}
+
+static void r600_set_scissor_state(struct pipe_context *ctx,
+					const struct pipe_scissor_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_scissor_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+static void r600_set_stencil_ref(struct pipe_context *ctx,
+				const struct pipe_stencil_ref *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+static void r600_set_vertex_buffers(struct pipe_context *ctx,
+					unsigned count,
+					const struct pipe_vertex_buffer *buffers)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	unsigned i;
+
+	for (i = 0; i < rctx->nvertex_buffer; i++) {
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
+	}
+	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
+	for (i = 0; i < count; i++) {
+		rctx->vertex_buffer[i].buffer = NULL;
+		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
+	}
+	rctx->nvertex_buffer = count;
+}
+
+static void r600_set_viewport_state(struct pipe_context *ctx,
+					const struct pipe_viewport_state *state)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_viewport_type, state);
+	r600_bind_state(ctx, rstate);
+}
+
+void r600_init_state_functions(struct r600_context *rctx)
+{
+	rctx->context.create_blend_state = r600_create_blend_state;
+	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
+	rctx->context.create_fs_state = r600_create_shader_state;
+	rctx->context.create_rasterizer_state = r600_create_rs_state;
+	rctx->context.create_sampler_state = r600_create_sampler_state;
+	rctx->context.create_sampler_view = r600_create_sampler_view;
+	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
+	rctx->context.create_vs_state = r600_create_shader_state;
+	rctx->context.bind_blend_state = r600_bind_state;
+	rctx->context.bind_depth_stencil_alpha_state = r600_bind_state;
+	rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
+	rctx->context.bind_fs_state = r600_bind_ps_shader;
+	rctx->context.bind_rasterizer_state = r600_bind_state;
+	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
+	rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
+	rctx->context.bind_vs_state = r600_bind_vs_shader;
+	rctx->context.delete_blend_state = r600_delete_state;
+	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
+	rctx->context.delete_fs_state = r600_delete_state;
+	rctx->context.delete_rasterizer_state = r600_delete_state;
+	rctx->context.delete_sampler_state = r600_delete_state;
+	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
+	rctx->context.delete_vs_state = r600_delete_state;
+	rctx->context.set_blend_color = r600_set_blend_color;
+	rctx->context.set_clip_state = r600_set_clip_state;
+	rctx->context.set_constant_buffer = r600_set_constant_buffer;
+	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
+	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
+	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
+	rctx->context.set_sample_mask = r600_set_sample_mask;
+	rctx->context.set_scissor_state = r600_set_scissor_state;
+	rctx->context.set_stencil_ref = r600_set_stencil_ref;
+	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
+	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
+	rctx->context.set_viewport_state = r600_set_viewport_state;
+	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
+}
+
+struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
+{
+	if (rstate == NULL)
+		return NULL;
+	rstate->refcount++;
+	return rstate;
+}
+
+struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
+{
+	unsigned i;
+
+	if (rstate == NULL)
+		return NULL;
+	if (--rstate->refcount)
+		return NULL;
+	switch (rstate->type) {
+	case pipe_sampler_view_type:
+		pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
+		break;
+	case pipe_framebuffer_type:
+		for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
+			pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
+		}
+		pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
+		break;
+	case pipe_viewport_type:
+	case pipe_depth_type:
+	case pipe_rasterizer_type:
+	case pipe_poly_stipple_type:
+	case pipe_scissor_type:
+	case pipe_clip_type:
+	case pipe_stencil_type:
+	case pipe_alpha_type:
+	case pipe_dsa_type:
+	case pipe_blend_type:
+	case pipe_stencil_ref_type:
+	case pipe_shader_type:
+	case pipe_sampler_type:
+		break;
+	default:
+		R600_ERR("invalid type %d\n", rstate->type);
+		return NULL;
+	}
+	radeon_state_decref(rstate->rstate);
+	FREE(rstate);
+	return NULL;
+}
+
+struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state)
+{
+	struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
+	const union pipe_states *states = state;
+	unsigned i;
+	int r;
+
+	if (rstate == NULL)
+		return NULL;
+	rstate->type = type;
+	rstate->refcount = 1;
+
+	switch (rstate->type) {
+	case pipe_sampler_view_type:
+		rstate->state.sampler_view = (*states).sampler_view;
+		rstate->state.sampler_view.texture = NULL;
+		break;
+	case pipe_framebuffer_type:
+		rstate->state.framebuffer = (*states).framebuffer;
+		for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
+			pipe_surface_reference(&rstate->state.framebuffer.cbufs[i],
+						(*states).framebuffer.cbufs[i]);
+		}
+		pipe_surface_reference(&rstate->state.framebuffer.zsbuf,
+					(*states).framebuffer.zsbuf);
+		break;
+	case pipe_viewport_type:
+		rstate->state.viewport = (*states).viewport;
+		break;
+	case pipe_depth_type:
+		rstate->state.depth = (*states).depth;
+		break;
+	case pipe_rasterizer_type:
+		rstate->state.rasterizer = (*states).rasterizer;
+		break;
+	case pipe_poly_stipple_type:
+		rstate->state.poly_stipple = (*states).poly_stipple;
+		break;
+	case pipe_scissor_type:
+		rstate->state.scissor = (*states).scissor;
+		break;
+	case pipe_clip_type:
+		rstate->state.clip = (*states).clip;
+		break;
+	case pipe_stencil_type:
+		rstate->state.stencil = (*states).stencil;
+		break;
+	case pipe_alpha_type:
+		rstate->state.alpha = (*states).alpha;
+		break;
+	case pipe_dsa_type:
+		rstate->state.dsa = (*states).dsa;
+		break;
+	case pipe_blend_type:
+		rstate->state.blend = (*states).blend;
+		break;
+	case pipe_stencil_ref_type:
+		rstate->state.stencil_ref = (*states).stencil_ref;
+		break;
+	case pipe_shader_type:
+		rstate->state.shader = (*states).shader;
+		r =  r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
+		if (r) {
+			r600_context_state_decref(rstate);
+			return NULL;
+		}
+		break;
+	case pipe_sampler_type:
+		rstate->state.sampler = (*states).sampler;
+		break;
+	default:
+		R600_ERR("invalid type %d\n", rstate->type);
+		FREE(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blend(struct r600_context *rctx)
+{
+	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
 	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
@@ -69,36 +608,19 @@ static void *r600_create_blend_state(struct pipe_context *ctx,
 	return rstate;
 }
 
-static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
+static struct radeon_state *r600_cb0(struct r600_context *rctx)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	radeon_draw_set(rctx->draw, state);
-}
-
-static void r600_set_blend_color(struct pipe_context *ctx,
-					const struct pipe_blend_color *color)
-{
-}
-
-static void r600_set_clip_state(struct pipe_context *ctx,
-				const struct pipe_clip_state *state)
-{
-}
-
-static void r600_set_framebuffer_state(struct pipe_context *ctx,
-					const struct pipe_framebuffer_state *state)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
+	struct r600_screen *rscreen = rctx->screen;
 	struct r600_resource_texture *rtex;
 	struct r600_resource *rbuffer;
 	struct radeon_state *rstate;
+	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 	unsigned level = state->cbufs[0]->level;
 	unsigned pitch, slice;
 
 	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
 	if (rstate == NULL)
-		return;
+		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
 	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -120,70 +642,53 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
-		return;
+		return NULL;
 	}
-	radeon_draw_set_new(rctx->draw, rstate);
-	rctx->db = radeon_state_decref(rctx->db);
-	if(state->zsbuf) {
-		rtex = (struct r600_resource_texture*)state->zsbuf->texture;
-		rbuffer = &rtex->resource;
-		rctx->db = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
-		if(rctx->db == NULL)
-		     return;
-		rctx->db->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		rctx->db->nbo = 1;
-		rctx->db->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-		level = state->zsbuf->level;
-		pitch = rtex->pitch[level] / 8 - 1;
-		slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1;
-
-		rctx->db->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
-		rctx->db->states[R600_DB__DB_DEPTH_INFO] = 0x00010006;
-		rctx->db->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-		rctx->db->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
-		rctx->db->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	} else 
-		rctx->db = NULL;
-	rctx->fb_state = *state;
-}
-
-static void *r600_create_fs_state(struct pipe_context *ctx,
-					const struct pipe_shader_state *shader)
-{
-	return r600_pipe_shader_create(ctx, shader->tokens);
-}
-
-static void r600_bind_fs_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	rctx->ps_shader = state;
+	return rstate;
 }
 
-static void *r600_create_vs_state(struct pipe_context *ctx,
-					const struct pipe_shader_state *shader)
+static struct radeon_state *r600_db(struct r600_context *rctx)
 {
-	return r600_pipe_shader_create(ctx, shader->tokens);
-}
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
+	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
+	unsigned level = state->cbufs[0]->level;
+	unsigned pitch, slice;
 
-static void r600_bind_vs_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
+	if (state->zsbuf == NULL)
+		return NULL;
 
-	rctx->vs_shader = state;
-}
+	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	if (rstate == NULL)
+		return NULL;
 
-static void r600_set_polygon_stipple(struct pipe_context *ctx,
-					 const struct pipe_poly_stipple *state)
-{
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rbuffer = &rtex->resource;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	level = state->zsbuf->level;
+	pitch = rtex->pitch[level] / 8 - 1;
+	slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1;
+	rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
+	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010006;
+	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
+	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
+	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
+						S_028000_SLICE_TILE_MAX(slice);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static void *r600_create_rs_state(struct pipe_context *ctx,
-					const struct pipe_rasterizer_state *state)
+static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
+	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
+	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
 	rctx->flat_shade = state->flatshade;
@@ -220,10 +725,102 @@ R600_ERR("flat shade with texture broke tex coord interp\n");
 	return rstate;
 }
 
-static void r600_bind_rs_state(struct pipe_context *ctx, void *state)
+static struct radeon_state *r600_scissor(struct r600_context *rctx)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	radeon_draw_set(rctx->draw, state);
+	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+	u32 tl, br;
+
+	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
+	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
+	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
+	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
+	rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
+	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
+	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
+	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_viewport(struct r600_context *rctx)
+{
+	const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
+	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
+	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_dsa(struct r600_context *rctx)
+{
+	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+	unsigned db_depth_control;
+
+	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	if (rstate == NULL)
+		return NULL;
+	db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
+	
+	rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
+	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
+	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
+	rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
+	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
+	rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
+	rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
+	rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
+	rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
+	rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
+	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
+	rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
+	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
+	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
+	rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
+	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
 static inline unsigned r600_tex_wrap(unsigned wrap)
@@ -296,13 +893,14 @@ static inline unsigned r600_tex_compare(unsigned compare)
 	}
 }
 
-static void *r600_create_sampler_state(struct pipe_context *ctx,
-					const struct pipe_sampler_state *state)
+static struct radeon_state *r600_sampler(struct r600_context *rctx,
+				const struct pipe_sampler_state *state,
+				unsigned id)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, R600_PS_SAMPLER);
+	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
@@ -314,33 +912,16 @@ static void *r600_create_sampler_state(struct pipe_context *ctx,
 			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
 	/* FIXME LOD it depends on texture base level ... */
-	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
-			S_03C004_MIN_LOD(0) |
-			S_03C004_MAX_LOD(0) |
-			S_03C004_LOD_BIAS(0);
-	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
-}
-
-static void r600_bind_sampler_states(struct pipe_context *ctx,
-					unsigned count, void **states)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned i;
-
-	/* FIXME split VS/PS/GS sampler */
-	for (i = 0; i < count; i++) {
-		rctx->ps_sampler[i] = radeon_state_decref(rctx->ps_sampler[i]);
-	}
-	rctx->nps_sampler = count;
-	for (i = 0; i < count; i++) {
-		rctx->ps_sampler[i] = radeon_state_incref(states[i]);
-		rctx->ps_sampler[i]->id = R600_PS_SAMPLER + i;
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
+			S_03C004_MIN_LOD(0) |
+			S_03C004_MAX_LOD(0) |
+			S_03C004_LOD_BIAS(0);
+	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
 	}
+	return rstate;
 }
 
 static inline unsigned r600_tex_swizzle(unsigned swizzle)
@@ -390,57 +971,47 @@ static inline unsigned r600_tex_dim(unsigned dim)
 	}
 }
 
-static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
-							  struct pipe_resource *texture,
-							  const struct pipe_sampler_view *view)
+static struct radeon_state *r600_resource(struct r600_context *rctx,
+					const struct pipe_sampler_view *view,
+					unsigned id)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_texture_resource *rtexture;
+	struct r600_screen *rscreen = rctx->screen;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
 	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
 	unsigned format;
 
-	if (r600_conv_pipe_format(texture->format, &format))
+	if (r600_conv_pipe_format(view->texture->format, &format))
 		return NULL;
-	rtexture = CALLOC_STRUCT(r600_texture_resource);
-	if (rtexture == NULL)
-		return NULL;
-	desc = util_format_description(texture->format);
+	desc = util_format_description(view->texture->format);
 	assert(desc == NULL);
-	rtexture->state = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, R600_PS_RESOURCE);
-	if (rtexture->state == NULL) {
-		FREE(rtexture);
+	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
+	if (rstate == NULL) {
 		return NULL;
 	}
-	rtexture->view = *view;
-	rtexture->view.reference.count = 1;
-	rtexture->view.texture = NULL;
-	pipe_resource_reference(&rtexture->view.texture, texture);
-	rtexture->view.context = ctx;
-
-	tmp = (struct r600_resource_texture*)texture;
+	tmp = (struct r600_resource_texture*)view->texture;
 	rbuffer = &tmp->resource;
-	rtexture->state->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rtexture->state->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rtexture->state->nbo = 2;
-	rtexture->state->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rtexture->state->placement[1] = RADEON_GEM_DOMAIN_GTT;
-	rtexture->state->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	rtexture->state->placement[3] = RADEON_GEM_DOMAIN_GTT;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 2;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
 
 	/* FIXME properly handle first level != 0 */
-	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
-			S_038000_DIM(r600_tex_dim(texture->target)) |
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
+			S_038000_DIM(r600_tex_dim(view->texture->target)) |
 			S_038000_PITCH((tmp->pitch[0] / 8) - 1) |
-			S_038000_TEX_WIDTH(texture->width0 - 1);
-	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
-			S_038004_TEX_HEIGHT(texture->height0 - 1) |
-			S_038004_TEX_DEPTH(texture->depth0 - 1) |
+			S_038000_TEX_WIDTH(view->texture->width0 - 1);
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
+			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
+			S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
 			S_038004_DATA_FORMAT(format);
-	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
-	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
-	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
 			S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
 			S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
 			S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
@@ -453,225 +1024,12 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 			S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_b)) |
 			S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
 			S_038010_BASE_LEVEL(view->first_level);
-	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
 			S_038014_LAST_LEVEL(view->last_level) |
 			S_038014_BASE_ARRAY(0) |
 			S_038014_LAST_ARRAY(0);
-	rtexture->state->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
 			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
-	return &rtexture->view;
-}
-
-static void r600_sampler_view_destroy(struct pipe_context *ctx,
-				      struct pipe_sampler_view *view)
-{
-	struct r600_texture_resource *texture;
-
-	if (view == NULL)
-		return;
-	texture  = LIST_ENTRY(struct r600_texture_resource, view, view);
-	radeon_state_decref(texture->state);
-	FREE(texture);
-}
-
-static void r600_set_fragment_sampler_views(struct pipe_context *ctx,
-					    unsigned count,
-					    struct pipe_sampler_view **views)
-{
-	struct r600_texture_resource *rtexture;
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_sampler_view *tmp;
-	unsigned i, real_num_views = 0;
-
-	if (views == NULL)
-		return;
-
-	for (i = 0; i < count; i++) {
-		if (views[i])
-			real_num_views++;
-	}
-
-	for (i = 0; i < rctx->nps_view; i++) {
-		tmp = &rctx->ps_view[i]->view;
-		pipe_sampler_view_reference(&tmp, NULL);
-		rctx->ps_view[i] = NULL;
-	}
-	rctx->nps_view = real_num_views;
-	for (i = 0; i < count; i++) {
-
-		if (!views[i])
-			continue;
-		rtexture = LIST_ENTRY(struct r600_texture_resource, views[i], view);
-		rctx->ps_view[i] = rtexture;
-		tmp = NULL;
-		pipe_sampler_view_reference(&tmp, views[i]);
-		rtexture->state->id = R600_PS_RESOURCE + i;
-	}
-}
-
-static void r600_set_vertex_sampler_views(struct pipe_context *ctx,
-					  unsigned count,
-					  struct pipe_sampler_view **views)
-{
-	struct r600_texture_resource *rtexture;
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_sampler_view *tmp;
-	unsigned i, real_num_views = 0;
-
-	if (views == NULL)
-		return;
-
-	for (i = 0; i < count; i++) {
-		if (views[i])
-			real_num_views++;
-	}
-	for (i = 0; i < rctx->nvs_view; i++) {
-		tmp = &rctx->vs_view[i]->view;
-		pipe_sampler_view_reference(&tmp, NULL);
-		rctx->vs_view[i] = NULL;
-	}
-	rctx->nvs_view = real_num_views;
-	for (i = 0; i < count; i++) {
-		if (!views[i])
-			continue;
-		rtexture = LIST_ENTRY(struct r600_texture_resource, views[i], view);
-		rctx->vs_view[i] = rtexture;
-		tmp = NULL;
-		pipe_sampler_view_reference(&tmp, views[i]);
-		rtexture->state->id = R600_VS_RESOURCE + i;
-	}
-}
-
-static void r600_set_scissor_state(struct pipe_context *ctx,
-					const struct pipe_scissor_state *state)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_state *rstate;
-	u32 tl, br;
-
-	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
-	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
-	if (rstate == NULL)
-		return;
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
-	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return;
-	}
-	radeon_draw_set_new(rctx->draw, rstate);
-}
-
-static void r600_set_viewport_state(struct pipe_context *ctx,
-					const struct pipe_viewport_state *state)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
-	if (rstate == NULL)
-		return;
-	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
-	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui(state->scale[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = fui(state->scale[2]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui(state->translate[0]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
-	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return;
-	}
-	radeon_draw_set_new(rctx->draw, rstate);
-	rctx->viewport = *state;
-}
-
-static void r600_set_vertex_buffers(struct pipe_context *ctx,
-					unsigned count,
-					const struct pipe_vertex_buffer *buffers)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
-	rctx->nvertex_buffer = count;
-}
-
-
-static void *r600_create_vertex_elements_state(struct pipe_context *ctx,
-					       unsigned count,
-					       const struct pipe_vertex_element *elements)
-{
-	struct r600_vertex_elements_state *v = CALLOC_STRUCT(r600_vertex_elements_state);
-
-	assert(count < 32);
-	v->count = count;
-	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
-	return v;
-}
-
-static void r600_bind_vertex_elements_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_vertex_elements_state *v = (struct r600_vertex_elements_state*)state;
-
-	rctx->vertex_elements = v;
-}
-
-static void r600_delete_vertex_elements_state(struct pipe_context *ctx, void *state)
-{
-	FREE(state);
-}
-
-static void *r600_create_dsa_state(struct pipe_context *ctx,
-					const struct pipe_depth_stencil_alpha_state *state)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct radeon_state *rstate;
-	unsigned db_depth_control;
-
-	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
-	if (rstate == NULL)
-		return NULL;
-	db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
-	
-	rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
-	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
-	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
-	rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
-	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
-	rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
-	rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
-	rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
-	rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
-	rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
-	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
-	rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
-	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
-	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
-	rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
-	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
@@ -679,105 +1037,100 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
 	return rstate;
 }
 
-static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	radeon_draw_set(rctx->draw, state);
-}
-
-static void r600_set_constant_buffer(struct pipe_context *ctx,
-				     uint shader, uint index,
-				     struct pipe_resource *buffer)
+int r600_context_hw_states(struct r600_context *rctx)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, i, type, id;
-	struct radeon_state *rstate;
-	struct pipe_transfer *transfer;
-	u32 *ptr;
-
-	switch (shader) {
-	case PIPE_SHADER_VERTEX:
-		id = R600_VS_CONSTANT;
-		type = R600_VS_CONSTANT_TYPE;
-		break;
-	case PIPE_SHADER_FRAGMENT:
-		id = R600_PS_CONSTANT;
-		type = R600_PS_CONSTANT_TYPE;
-		break;
-	default:
-		fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
-		return;
+	unsigned i;
+	int r;
+
+	/* free previous TODO determine what need to be updated, what
+	 * doesn't
+	 */
+	//radeon_state_decref(rctx->hw_states.config);
+	//radeon_state_decref(rctx->hw_states.cb_cntl);
+	radeon_state_decref(rctx->hw_states.db);
+	radeon_state_decref(rctx->hw_states.rasterizer);
+	radeon_state_decref(rctx->hw_states.scissor);
+	radeon_state_decref(rctx->hw_states.dsa);
+	radeon_state_decref(rctx->hw_states.blend);
+	radeon_state_decref(rctx->hw_states.viewport);
+	radeon_state_decref(rctx->hw_states.cb0);
+	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
+		radeon_state_decref(rctx->hw_states.ps_resource[i]);
+		rctx->hw_states.ps_resource[i] = NULL;
 	}
-	if (buffer && buffer->width0 > 0) {
-		nconstant = buffer->width0 / 16;
-		ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ, &transfer);
-		if (ptr == NULL)
-			return;
-		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state(rscreen->rw, type, id + i);
-			if (rstate == NULL)
-				return;
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
-			if (radeon_state_pm4(rstate))
-				return;
-			if (radeon_draw_set_new(rctx->draw, rstate))
-				return;
+	rctx->hw_states.ps_nresource = 0;
+	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
+		radeon_state_decref(rctx->hw_states.ps_sampler[i]);
+		rctx->hw_states.ps_sampler[i] = NULL;
+	}
+	rctx->hw_states.ps_nsampler = 0;
+
+	/* build new states */
+	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
+	rctx->hw_states.scissor = r600_scissor(rctx);
+	rctx->hw_states.dsa = r600_dsa(rctx);
+	rctx->hw_states.blend = r600_blend(rctx);
+	rctx->hw_states.viewport = r600_viewport(rctx);
+	rctx->hw_states.cb0 = r600_cb0(rctx);
+	rctx->hw_states.db = r600_db(rctx);
+	for (i = 0; i < rctx->ps_nsampler; i++) {
+		if (rctx->ps_sampler[i]) {
+			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
+							&rctx->ps_sampler[i]->state.sampler,
+							R600_PS_SAMPLER + i);
 		}
-		pipe_buffer_unmap(ctx, buffer, transfer);
 	}
-}
-
-static void r600_set_stencil_ref(struct pipe_context *ctx,
-				const struct pipe_stencil_ref *sr)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	rctx->stencil_ref = *sr;
-}
-
-static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
-{
-}
-
-void r600_init_state_functions(struct r600_context *rctx)
-{
-	rctx->context.set_sample_mask = r600_set_sample_mask;
-	rctx->context.create_blend_state = r600_create_blend_state;
-	rctx->context.bind_blend_state = r600_bind_blend_state;
-	rctx->context.delete_blend_state = r600_delete_state;
-	rctx->context.set_blend_color = r600_set_blend_color;
-	rctx->context.set_clip_state = r600_set_clip_state;
-	rctx->context.set_constant_buffer = r600_set_constant_buffer;
-	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
-	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
-	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
-	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
-	rctx->context.create_fs_state = r600_create_fs_state;
-	rctx->context.bind_fs_state = r600_bind_fs_state;
-	rctx->context.delete_fs_state = r600_delete_state;
-	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
-	rctx->context.create_rasterizer_state = r600_create_rs_state;
-	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
-	rctx->context.delete_rasterizer_state = r600_delete_state;
-	rctx->context.create_sampler_state = r600_create_sampler_state;
-	rctx->context.bind_fragment_sampler_states = r600_bind_sampler_states;
-	rctx->context.bind_vertex_sampler_states = r600_bind_sampler_states;
-	rctx->context.delete_sampler_state = r600_delete_state;
-	rctx->context.create_sampler_view = r600_create_sampler_view;
-	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
-	rctx->context.set_fragment_sampler_views = r600_set_fragment_sampler_views;
-	rctx->context.set_vertex_sampler_views = r600_set_vertex_sampler_views;
-	rctx->context.set_scissor_state = r600_set_scissor_state;
-	rctx->context.set_viewport_state = r600_set_viewport_state;
-	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
-	rctx->context.create_vertex_elements_state = r600_create_vertex_elements_state;
-	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements_state;
-	rctx->context.delete_vertex_elements_state = r600_delete_vertex_elements_state;
-	rctx->context.create_vs_state = r600_create_vs_state;
-	rctx->context.bind_vs_state = r600_bind_vs_state;
-	rctx->context.delete_vs_state = r600_delete_state;
-	rctx->context.set_stencil_ref = r600_set_stencil_ref;
+	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
+	for (i = 0; i < rctx->ps_nsampler_view; i++) {
+		if (rctx->ps_sampler_view[i]) {
+			rctx->hw_states.ps_resource[i] = r600_resource(rctx,
+							&rctx->ps_sampler_view[i]->state.sampler_view,
+							R600_PS_RESOURCE + i);
+		}
+	}
+	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
+
+	/* bind states */
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
+	if (r)
+		return r;
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
+	if (r)
+		return r;
+	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
+		if (rctx->hw_states.ps_resource[i]) {
+			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
+			if (r)
+				return r;
+		}
+	}
+	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
+		if (rctx->hw_states.ps_sampler[i]) {
+			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
+			if (r)
+				return r;
+		}
+	}
+	return 0;
 }
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 3d87a994c1..9520792f54 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -30,7 +30,7 @@
 #include "util/u_debug.h"
 #include "radeon_priv.h"
 #include "r600_screen.h"
-#include "r600_texture.h"
+#include "r600_resource.h"
 #include "r600_public.h"
 #include "r600_drm_public.h"
 #include "state_tracker/drm_driver.h"
@@ -45,7 +45,7 @@ boolean r600_buffer_get_handle(struct radeon *rw,
 			       struct winsys_handle *whandle)
 {
 	struct drm_gem_flink flink;
-	struct r600_buffer* rbuffer = (struct r600_buffer*)buf;
+	struct r600_resource* rbuffer = (struct r600_buffer*)buf;
 
 	if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
 		if (!rbuffer->flink) {
-- 
cgit v1.2.3


From 35e044ab562b65aa53f9d9d7b5885e6a887774bb Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 28 Jul 2010 19:59:38 -0400
Subject: r600g: switch btw flat/linear interpolation

I am not sure how to properly handle flat shading regarding
non color parameter to fragment shader. It seems we should
still interpolate non color using linear interpolation and
flat shade only apply to color.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 7 ++++++-
 src/gallium/drivers/r600/r600_shader.h | 1 +
 src/gallium/drivers/r600/r600_state.c  | 2 --
 3 files changed, 7 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 8837a7272b..3f1979b9cc 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -169,7 +169,10 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	for (i = 0; i < rshader->ninput; i++) {
 		tmp = S_028644_SEMANTIC(rshader->input[i].sid);
 		tmp |= S_028644_SEL_CENTROID(1);
-		tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
+			rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
+			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
+		}
 		state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
 	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
@@ -287,6 +290,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 		i = ctx->shader->ninput++;
 		ctx->shader->input[i].name = d->Semantic.Name;
 		ctx->shader->input[i].sid = d->Semantic.Index;
+		ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
 		ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
 		if (ctx->type == TGSI_PROCESSOR_VERTEX) {
 			/* turn input into fetch */
@@ -313,6 +317,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 		ctx->shader->output[i].name = d->Semantic.Name;
 		ctx->shader->output[i].sid = d->Semantic.Index;
 		ctx->shader->output[i].gpr = ctx->file_offset[TGSI_FILE_OUTPUT] + i;
+		ctx->shader->output[i].interpolate = d->Declaration.Interpolate;
 		break;
 	case TGSI_FILE_CONSTANT:
 	case TGSI_FILE_TEMPORARY:
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index 23b6a83b9a..ee0381e8bd 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -29,6 +29,7 @@ struct r600_shader_io {
 	unsigned		name;
 	unsigned		gpr;
 	int			sid;
+	unsigned		interpolate;
 };
 
 struct r600_shader {
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 0f1e1cd761..5b98dbe236 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -692,8 +692,6 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	struct radeon_state *rstate;
 
 	rctx->flat_shade = state->flatshade;
-	rctx->flat_shade = 0;
-R600_ERR("flat shade with texture broke tex coord interp\n");
 	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 	if (rstate == NULL)
 		return NULL;
-- 
cgit v1.2.3


From 42c1f27149828e5b5143f5e53ca3bd7c04a4e762 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 28 Jul 2010 20:09:15 -0400
Subject: r600g: state context ptr in sampler_view & add I8/L8 buffer format

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_helper.c | 2 ++
 src/gallium/drivers/r600/r600_state.c  | 1 +
 2 files changed, 3 insertions(+)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_helper.c b/src/gallium/drivers/r600/r600_helper.c
index 7241ab1c17..132abf90a3 100644
--- a/src/gallium/drivers/r600/r600_helper.c
+++ b/src/gallium/drivers/r600/r600_helper.c
@@ -59,6 +59,8 @@ int r600_conv_pipe_format(unsigned pformat, unsigned *format)
 	case PIPE_FORMAT_L8_UNORM:
 	case PIPE_FORMAT_A8_UNORM:
 	case PIPE_FORMAT_I8_UNORM:
+		*format = V_0280A0_COLOR_8;
+		return 0;
 	case PIPE_FORMAT_L16_UNORM:
 	case PIPE_FORMAT_Z16_UNORM:
 	case PIPE_FORMAT_Z32_UNORM:
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 5b98dbe236..ff5df855c6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -83,6 +83,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	pipe_reference(NULL, &texture->reference);
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
+	rstate->state.sampler_view.context = ctx;
 	return &rstate->state.sampler_view;
 }
 
-- 
cgit v1.2.3


From 6d28bf917fb1d741d90fd3f05c22769376021fca Mon Sep 17 00:00:00 2001
From: Chia-I Wu <olv@lunarg.com>
Date: Fri, 16 Jul 2010 04:35:58 +0800
Subject: gallium: Implement draw_vbo and set_index_buffer for all drivers.

Some drivers define a generic function that is called by all drawing
functions.  To implement draw_vbo for such drivers, either draw_vbo
calls the generic function or the prototype of the generic function is
changed to match draw_vbo.

Other drivers have no such generic function.  draw_vbo is implemented by
calling either draw_arrays and draw_elements.

For most drivers, set_index_buffer does not mark the state dirty for
tracking.  Instead, the index buffer state is emitted whenever draw_vbo
is called, just like the case with draw_elements.  It surely can be
improved.
---
 src/gallium/auxiliary/util/u_draw_quad.h          |  30 +++++
 src/gallium/drivers/cell/ppu/cell_context.h       |   1 +
 src/gallium/drivers/cell/ppu/cell_draw_arrays.c   |  69 ++++++++---
 src/gallium/drivers/cell/ppu/cell_state_vertex.c  |  16 +++
 src/gallium/drivers/failover/fo_context.c         |  61 ++++++----
 src/gallium/drivers/failover/fo_context.h         |   2 +
 src/gallium/drivers/failover/fo_state.c           |  18 +++
 src/gallium/drivers/failover/fo_state_emit.c      |   5 +
 src/gallium/drivers/galahad/glhd_context.c        |  47 +++++++
 src/gallium/drivers/i915/i915_context.c           |  70 ++++++++---
 src/gallium/drivers/i915/i915_context.h           |   1 +
 src/gallium/drivers/i915/i915_state.c             |  14 +++
 src/gallium/drivers/i965/brw_context.h            |   1 +
 src/gallium/drivers/i965/brw_draw.c               |  87 ++++++++-----
 src/gallium/drivers/i965/brw_draw_upload.c        |   7 +-
 src/gallium/drivers/i965/brw_pipe_vertex.c        |  31 +++++
 src/gallium/drivers/identity/id_context.c         |  30 +++++
 src/gallium/drivers/llvmpipe/lp_context.h         |   1 +
 src/gallium/drivers/llvmpipe/lp_draw_arrays.c     |  90 ++++++++++----
 src/gallium/drivers/llvmpipe/lp_state_vertex.c    |  14 +++
 src/gallium/drivers/nv50/nv50_context.c           |   1 +
 src/gallium/drivers/nv50/nv50_context.h           |   3 +
 src/gallium/drivers/nv50/nv50_state.c             |  15 +++
 src/gallium/drivers/nv50/nv50_vbo.c               |  31 +++++
 src/gallium/drivers/nvfx/nvfx_context.c           |   1 +
 src/gallium/drivers/nvfx/nvfx_context.h           |   5 +-
 src/gallium/drivers/nvfx/nvfx_state.c             |  15 +++
 src/gallium/drivers/nvfx/nvfx_vbo.c               |  39 +++++-
 src/gallium/drivers/r300/r300_context.h           |   2 +
 src/gallium/drivers/r300/r300_render.c            | 142 ++++++++++++++--------
 src/gallium/drivers/r300/r300_render_stencilref.c |  22 ++++
 src/gallium/drivers/r300/r300_state.c             |  18 +++
 src/gallium/drivers/r600/r600_context.c           |   1 +
 src/gallium/drivers/r600/r600_context.h           |   3 +
 src/gallium/drivers/r600/r600_draw.c              |  27 ++++
 src/gallium/drivers/r600/r600_state.c             |  18 +++
 src/gallium/drivers/rbug/rbug_context.c           |  34 ++++++
 src/gallium/drivers/softpipe/sp_context.c         |   2 +
 src/gallium/drivers/softpipe/sp_context.h         |   1 +
 src/gallium/drivers/softpipe/sp_draw_arrays.c     |  92 +++++++++-----
 src/gallium/drivers/softpipe/sp_state.h           |   7 ++
 src/gallium/drivers/softpipe/sp_state_vertex.c    |  14 +++
 src/gallium/drivers/svga/svga_context.h           |   1 +
 src/gallium/drivers/svga/svga_pipe_draw.c         |  24 ++++
 src/gallium/drivers/svga/svga_pipe_vertex.c       |  19 +++
 src/gallium/drivers/trace/tr_context.c            |  52 ++++++++
 src/gallium/drivers/trace/tr_dump_state.c         |  20 +++
 src/gallium/drivers/trace/tr_dump_state.h         |   2 +
 48 files changed, 1004 insertions(+), 202 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/auxiliary/util/u_draw_quad.h b/src/gallium/auxiliary/util/u_draw_quad.h
index 42eb184428..1c9f752611 100644
--- a/src/gallium/auxiliary/util/u_draw_quad.h
+++ b/src/gallium/auxiliary/util/u_draw_quad.h
@@ -29,12 +29,42 @@
 #define U_DRAWQUAD_H
 
 
+#include "pipe/p_compiler.h"
+#include "pipe/p_context.h"
+
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 struct pipe_resource;
 
+
+static INLINE void
+util_draw_init_info(struct pipe_draw_info *info)
+{
+   memset(info, 0, sizeof(*info));
+   info->instance_count = 1;
+   info->max_index = 0xffffffff;
+}
+
+
+static INLINE void
+util_draw_arrays(struct pipe_context *pipe, uint mode, uint start, uint count)
+{
+   struct pipe_draw_info info;
+
+   util_draw_init_info(&info);
+   info.mode = mode;
+   info.start = start;
+   info.count = count;
+   info.min_index = start;
+   info.max_index = start + count - 1;
+
+   pipe->draw_vbo(pipe, &info);
+}
+
+
 extern void 
 util_draw_vertex_buffer(struct pipe_context *pipe,
                         struct pipe_resource *vbuf, uint offset,
diff --git a/src/gallium/drivers/cell/ppu/cell_context.h b/src/gallium/drivers/cell/ppu/cell_context.h
index dc46e59a2d..d1aee62ba1 100644
--- a/src/gallium/drivers/cell/ppu/cell_context.h
+++ b/src/gallium/drivers/cell/ppu/cell_context.h
@@ -132,6 +132,7 @@ struct cell_context
    struct pipe_viewport_state viewport;
    struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
    uint num_vertex_buffers;
+   struct pipe_index_buffer index_buffer;
 
    ubyte *cbuf_map[PIPE_MAX_COLOR_BUFS];
    ubyte *zsbuf_map;
diff --git a/src/gallium/drivers/cell/ppu/cell_draw_arrays.c b/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
index 6a1e4d8a64..e06226fbfe 100644
--- a/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
+++ b/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
@@ -34,6 +34,7 @@
 #include "pipe/p_defines.h"
 #include "pipe/p_context.h"
 #include "util/u_inlines.h"
+#include "util/u_draw_quad.h"
 
 #include "cell_context.h"
 #include "cell_draw_arrays.h"
@@ -56,16 +57,11 @@
  * XXX should the element buffer be specified/bound with a separate function?
  */
 static void
-cell_draw_range_elements(struct pipe_context *pipe,
-                         struct pipe_resource *indexBuffer,
-                         unsigned indexSize,
-                         int indexBias,
-                         unsigned min_index,
-                         unsigned max_index,
-                         unsigned mode, unsigned start, unsigned count)
+cell_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
    struct cell_context *cell = cell_context(pipe);
    struct draw_context *draw = cell->draw;
+   void *mapped_indices = NULL;
    unsigned i;
 
    if (cell->dirty)
@@ -83,18 +79,20 @@ cell_draw_range_elements(struct pipe_context *pipe,
       draw_set_mapped_vertex_buffer(draw, i, buf);
    }
    /* Map index buffer, if present */
-   if (indexBuffer) {
-      void *mapped_indexes = cell_resource(indexBuffer)->data;
-      draw_set_mapped_element_buffer(draw, indexSize, indexBias, mapped_indexes);
-   }
-   else {
-      /* no index/element buffer */
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
+   if (info->indexed && cell->index_buffer.buffer) {
+      mapped_indices = cell_resource(cell->index_buffer.buffer)->data;
+      mapped_indices += cell->index_buffer.offset;
    }
 
+   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
+                                        lp->index_buffer.index_size : 0,
+                                        info->index_bias,
+                                        info->min_index,
+                                        info->max_index,
+                                        mapped_indices);
 
    /* draw! */
-   draw_arrays(draw, mode, start, count);
+   draw_arrays(draw, info->mode, info->start, info->count);
 
    /*
     * unmap vertex/index buffers - will cause draw module to flush
@@ -102,7 +100,7 @@ cell_draw_range_elements(struct pipe_context *pipe,
    for (i = 0; i < cell->num_vertex_buffers; i++) {
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
-   if (indexBuffer) {
+   if (mapped_indices) {
       draw_set_mapped_element_buffer(draw, 0, 0, NULL);
    }
 
@@ -115,6 +113,44 @@ cell_draw_range_elements(struct pipe_context *pipe,
 }
 
 
+static void
+cell_draw_range_elements(struct pipe_context *pipe,
+                         struct pipe_resource *indexBuffer,
+                         unsigned indexSize,
+                         int indexBias,
+                         unsigned min_index,
+                         unsigned max_index,
+                         unsigned mode, unsigned start, unsigned count)
+{
+   struct cell_context *cell = cell_context(pipe);
+   struct pipe_draw_info info;
+   struct pipe_index_buffer saved_ib, ib;
+
+   util_draw_init_info(&info);
+   info.mode = mode;
+   info.start = start;
+   info.count = count;
+   info.index_bias = indexBias;
+   info.min_index = min_index;
+   info.max_index = max_index;
+
+   if (indexBuffer) {
+      info.indexed = TRUE;
+      saved_ib = cell->index_buffer;
+
+      ib.buffer = indexBuffer;
+      ib.offset = 0;
+      ib.index_size = indexSize;
+      pipe->set_index_buffer(pipe, &ib);
+   }
+
+   cell_draw_vbo(pipe, &info);
+
+   if (indexBuffer)
+      pipe->set_index_buffer(pipe, &saved_ib);
+}
+
+
 static void
 cell_draw_elements(struct pipe_context *pipe,
                    struct pipe_resource *indexBuffer,
@@ -142,5 +178,6 @@ cell_init_draw_functions(struct cell_context *cell)
    cell->pipe.draw_arrays = cell_draw_arrays;
    cell->pipe.draw_elements = cell_draw_elements;
    cell->pipe.draw_range_elements = cell_draw_range_elements;
+   cell->pipe.draw_vbo = cell_draw_vbo;
 }
 
diff --git a/src/gallium/drivers/cell/ppu/cell_state_vertex.c b/src/gallium/drivers/cell/ppu/cell_state_vertex.c
index 69152b6cbf..4e3701cd0a 100644
--- a/src/gallium/drivers/cell/ppu/cell_state_vertex.c
+++ b/src/gallium/drivers/cell/ppu/cell_state_vertex.c
@@ -91,10 +91,26 @@ cell_set_vertex_buffers(struct pipe_context *pipe,
 }
 
 
+static void
+cell_set_index_buffer(struct pipe_context *pipe,
+                      const struct pipe_index_buffer *ib)
+{
+   struct cell_context *cell = cell_context(pipe);
+
+   if (ib)
+      memcpy(&cell->index_buffer, ib, sizeof(cell->index_buffer));
+   else
+      memset(&cell->index_buffer, 0, sizeof(cell->index_buffer));
+
+   /* TODO make this more like a state */
+}
+
+
 void
 cell_init_vertex_functions(struct cell_context *cell)
 {
    cell->pipe.set_vertex_buffers = cell_set_vertex_buffers;
+   cell->pipe.set_index_buffer = cell_set_index_buffer;
    cell->pipe.create_vertex_elements_state = cell_create_vertex_elements_state;
    cell->pipe.bind_vertex_elements_state = cell_bind_vertex_elements_state;
    cell->pipe.delete_vertex_elements_state = cell_delete_vertex_elements_state;
diff --git a/src/gallium/drivers/failover/fo_context.c b/src/gallium/drivers/failover/fo_context.c
index 9c9c1bdc45..1048d58313 100644
--- a/src/gallium/drivers/failover/fo_context.c
+++ b/src/gallium/drivers/failover/fo_context.c
@@ -28,6 +28,7 @@
 
 #include "pipe/p_defines.h"
 #include "util/u_memory.h"
+#include "util/u_draw_quad.h"
 #include "pipe/p_context.h"
 
 #include "fo_context.h"
@@ -50,13 +51,8 @@ void failover_fail_over( struct failover_context *failover )
 }
 
 
-static void failover_draw_elements( struct pipe_context *pipe,
-                                    struct pipe_resource *indexResource,
-                                    unsigned indexSize,
-                                    int indexBias,
-                                    unsigned prim, 
-                                    unsigned start, 
-                                    unsigned count)
+static void failover_draw_vbo( struct pipe_context *pipe,
+                               const struct pipe_draw_info *info)
 {
    struct failover_context *failover = failover_context( pipe );
 
@@ -70,13 +66,7 @@ static void failover_draw_elements( struct pipe_context *pipe,
    /* Try hardware:
     */
    if (failover->mode == FO_HW) {
-      failover->hw->draw_elements( failover->hw, 
-                                   indexResource, 
-                                   indexSize, 
-                                   indexBias,
-                                   prim, 
-                                   start, 
-                                   count );
+      failover->hw->draw_vbo( failover->hw, info );
    }
 
    /* Possibly try software:
@@ -88,13 +78,7 @@ static void failover_draw_elements( struct pipe_context *pipe,
 	 failover_state_emit( failover );
       }
 
-      failover->sw->draw_elements( failover->sw, 
-				   indexResource, 
-				   indexSize, 
-				   indexBias,
-				   prim, 
-				   start, 
-				   count );
+      failover->sw->draw_vbo( failover->sw, info );
 
       /* Be ready to switch back to hardware rendering without an
        * intervening flush.  Unlikely to be much performance impact to
@@ -105,6 +89,40 @@ static void failover_draw_elements( struct pipe_context *pipe,
 }
 
 
+static void failover_draw_elements( struct pipe_context *pipe,
+                                    struct pipe_resource *indexResource,
+                                    unsigned indexSize,
+                                    int indexBias,
+                                    unsigned prim, 
+                                    unsigned start, 
+                                    unsigned count)
+{
+   struct failover_context *failover = failover_context( pipe );
+   struct pipe_draw_info info;
+   struct pipe_index_buffer saved_ib, ib;
+
+   util_draw_init_info(&info);
+   info.mode = prim;
+   info.start = start;
+   info.count = count;
+
+   if (indexResource) {
+      info.indexed = TRUE;
+      saved_ib = failover->index_buffer;
+
+      ib.buffer = indexResource;
+      ib.offset = 0;
+      ib.index_size = indexSize;
+      pipe->set_index_buffer(pipe, &ib);
+   }
+
+   failover_draw_vbo(pipe, &info);
+
+   if (indexResource)
+      pipe->set_index_buffer(pipe, &saved_ib);
+}
+
+
 static void failover_draw_arrays( struct pipe_context *pipe,
 				     unsigned prim, unsigned start, unsigned count)
 {
@@ -145,6 +163,7 @@ struct pipe_context *failover_create( struct pipe_context *hw,
 
    failover->pipe.draw_arrays = failover_draw_arrays;
    failover->pipe.draw_elements = failover_draw_elements;
+   failover->pipe.draw_vbo = failover_draw_vbo;
    failover->pipe.clear = hw->clear;
    failover->pipe.clear_render_target = hw->clear_render_target;
    failover->pipe.clear_depth_stencil = hw->clear_depth_stencil;
diff --git a/src/gallium/drivers/failover/fo_context.h b/src/gallium/drivers/failover/fo_context.h
index 9d3e0d0dba..1afa6c9cee 100644
--- a/src/gallium/drivers/failover/fo_context.h
+++ b/src/gallium/drivers/failover/fo_context.h
@@ -56,6 +56,7 @@
 #define FO_NEW_VERTEX_BUFFER   0x40000
 #define FO_NEW_VERTEX_ELEMENT  0x80000
 #define FO_NEW_SAMPLE_MASK     0x100000
+#define FO_NEW_INDEX_BUFFER    0x200000
 
 
 
@@ -97,6 +98,7 @@ struct failover_context {
    struct pipe_scissor_state scissor;
    struct pipe_viewport_state viewport;
    struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];
+   struct pipe_index_buffer index_buffer;
 
    uint num_vertex_buffers;
 
diff --git a/src/gallium/drivers/failover/fo_state.c b/src/gallium/drivers/failover/fo_state.c
index 12e42379f9..c265f381b6 100644
--- a/src/gallium/drivers/failover/fo_state.c
+++ b/src/gallium/drivers/failover/fo_state.c
@@ -583,6 +583,23 @@ failover_set_vertex_buffers(struct pipe_context *pipe,
 }
 
 
+static void
+failover_set_index_buffer(struct pipe_context *pipe,
+                          const struct pipe_index_buffer *ib)
+{
+   struct failover_context *failover = failover_context(pipe);
+
+   if (ib)
+      memcpy(&failover->index_buffer, ib, sizeof(failover->index_buffer));
+   else
+      memset(&failover->index_buffer, 0, sizeof(failover->index_buffer));
+
+   failover->dirty |= FO_NEW_INDEX_BUFFER;
+   failover->sw->set_index_buffer( failover->sw, ib );
+   failover->hw->set_index_buffer( failover->hw, ib );
+}
+
+
 void
 failover_set_constant_buffer(struct pipe_context *pipe,
                              uint shader, uint index,
@@ -635,6 +652,7 @@ failover_init_state_functions( struct failover_context *failover )
    failover->pipe.set_vertex_sampler_views = failover_set_vertex_sampler_views;
    failover->pipe.set_viewport_state = failover_set_viewport_state;
    failover->pipe.set_vertex_buffers = failover_set_vertex_buffers;
+   failover->pipe.set_index_buffer = failover_set_index_buffer;
    failover->pipe.set_constant_buffer = failover_set_constant_buffer;
    failover->pipe.create_sampler_view = failover_create_sampler_view;
    failover->pipe.sampler_view_destroy = failover_sampler_view_destroy;
diff --git a/src/gallium/drivers/failover/fo_state_emit.c b/src/gallium/drivers/failover/fo_state_emit.c
index 147f23269c..7f434ff9d6 100644
--- a/src/gallium/drivers/failover/fo_state_emit.c
+++ b/src/gallium/drivers/failover/fo_state_emit.c
@@ -135,5 +135,10 @@ failover_state_emit( struct failover_context *failover )
                                         failover->vertex_buffers );
    }
 
+   if (failover->dirty & FO_NEW_INDEX_BUFFER) {
+      failover->sw->set_index_buffer( failover->sw,
+                                      &failover->index_buffer );
+   }
+
    failover->dirty = 0;
 }
diff --git a/src/gallium/drivers/galahad/glhd_context.c b/src/gallium/drivers/galahad/glhd_context.c
index ab6f17b3ab..6473f2d499 100644
--- a/src/gallium/drivers/galahad/glhd_context.c
+++ b/src/gallium/drivers/galahad/glhd_context.c
@@ -112,6 +112,16 @@ galahad_draw_range_elements(struct pipe_context *_pipe,
                              count);
 }
 
+static void
+galahad_draw_vbo(struct pipe_context *_pipe,
+                 const struct pipe_draw_info *info)
+{
+   struct galahad_context *glhd_pipe = galahad_context(_pipe);
+   struct pipe_context *pipe = glhd_pipe->pipe;
+
+   pipe->draw_vbo(pipe, info);
+}
+
 static struct pipe_query *
 galahad_create_query(struct pipe_context *_pipe,
                       unsigned query_type)
@@ -650,6 +660,41 @@ galahad_set_vertex_buffers(struct pipe_context *_pipe,
                             num_buffers,
                             buffers);
 }
+
+static void
+galahad_set_index_buffer(struct pipe_context *_pipe,
+                         const struct pipe_index_buffer *_ib)
+{
+   struct galahad_context *glhd_pipe = galahad_context(_pipe);
+   struct pipe_context *pipe = glhd_pipe->pipe;
+   struct pipe_index_buffer unwrapped_ib, *ib = NULL;
+
+   if (_ib->buffer) {
+      switch (_ib->index_size) {
+      case 1:
+      case 2:
+      case 4:
+         break;
+      default:
+         glhd_warn("index buffer %p has unrecognized index size %d",
+               _ib->buffer, _ib->index_size);
+         break;
+      }
+   }
+   else if (_ib->offset || _ib->index_size) {
+      glhd_warn("non-indexed state with index offset %d and index size %d",
+            _ib->offset, _ib->index_size);
+   }
+
+   if (_ib) {
+      unwrapped_ib = *_ib;
+      unwrapped_ib.buffer = galahad_resource_unwrap(_ib->buffer);
+      ib = &unwrapped_ib;
+   }
+
+   pipe->set_index_buffer(pipe, ib);
+}
+
 static void
 galahad_resource_copy_region(struct pipe_context *_pipe,
                               struct pipe_resource *_dst,
@@ -937,6 +982,7 @@ galahad_context_create(struct pipe_screen *_screen, struct pipe_context *pipe)
    glhd_pipe->base.draw_arrays = galahad_draw_arrays;
    glhd_pipe->base.draw_elements = galahad_draw_elements;
    glhd_pipe->base.draw_range_elements = galahad_draw_range_elements;
+   glhd_pipe->base.draw_vbo = galahad_draw_vbo;
    glhd_pipe->base.create_query = galahad_create_query;
    glhd_pipe->base.destroy_query = galahad_destroy_query;
    glhd_pipe->base.begin_query = galahad_begin_query;
@@ -976,6 +1022,7 @@ galahad_context_create(struct pipe_screen *_screen, struct pipe_context *pipe)
    glhd_pipe->base.set_fragment_sampler_views = galahad_set_fragment_sampler_views;
    glhd_pipe->base.set_vertex_sampler_views = galahad_set_vertex_sampler_views;
    glhd_pipe->base.set_vertex_buffers = galahad_set_vertex_buffers;
+   glhd_pipe->base.set_index_buffer = galahad_set_index_buffer;
    glhd_pipe->base.resource_copy_region = galahad_resource_copy_region;
    glhd_pipe->base.clear = galahad_clear;
    glhd_pipe->base.clear_render_target = galahad_clear_render_target;
diff --git a/src/gallium/drivers/i915/i915_context.c b/src/gallium/drivers/i915/i915_context.c
index 2af9bdac95..ca07b3e235 100644
--- a/src/gallium/drivers/i915/i915_context.c
+++ b/src/gallium/drivers/i915/i915_context.c
@@ -36,6 +36,7 @@
 #include "pipe/p_defines.h"
 #include "util/u_inlines.h"
 #include "util/u_memory.h"
+#include "util/u_draw_quad.h"
 #include "pipe/p_screen.h"
 
 
@@ -45,16 +46,11 @@
 
 
 static void
-i915_draw_range_elements(struct pipe_context *pipe,
-                         struct pipe_resource *indexBuffer,
-                         unsigned indexSize,
-                         int indexBias,
-                         unsigned min_index,
-                         unsigned max_index,
-                         unsigned prim, unsigned start, unsigned count)
+i915_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
    struct i915_context *i915 = i915_context(pipe);
    struct draw_context *draw = i915->draw;
+   void *mapped_indices = NULL;
    unsigned i;
 
    if (i915->dirty)
@@ -71,16 +67,18 @@ i915_draw_range_elements(struct pipe_context *pipe,
    /*
     * Map index buffer, if present
     */
-   if (indexBuffer) {
-      void *mapped_indexes = i915_buffer(indexBuffer)->data;
-      draw_set_mapped_element_buffer_range(draw, indexSize, indexBias,
-                                           min_index,
-                                           max_index,
-                                           mapped_indexes);
-   } else {
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
+   if (info->indexed && i915->index_buffer.buffer) {
+      mapped_indices = i915_buffer(i915->index_buffer.buffer)->data;
+      mapped_indices += i915->index_buffer.offset;
    }
 
+   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
+                                        i915->index_buffer.index_size : 0,
+                                        info->index_bias,
+                                        info->min_index,
+                                        info->max_index,
+                                        mapped_indices);
+
 
    draw_set_mapped_constant_buffer(draw, PIPE_SHADER_VERTEX, 0,
                                    i915->current.constants[PIPE_SHADER_VERTEX],
@@ -90,7 +88,7 @@ i915_draw_range_elements(struct pipe_context *pipe,
    /*
     * Do the drawing
     */
-   draw_arrays(i915->draw, prim, start, count);
+   draw_arrays(i915->draw, info->mode, info->start, info->count);
 
    /*
     * unmap vertex/index buffers
@@ -99,11 +97,48 @@ i915_draw_range_elements(struct pipe_context *pipe,
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
 
-   if (indexBuffer) {
+   if (mapped_indices) {
       draw_set_mapped_element_buffer(draw, 0, 0, NULL);
    }
 }
 
+static void
+i915_draw_range_elements(struct pipe_context *pipe,
+                         struct pipe_resource *indexBuffer,
+                         unsigned indexSize,
+                         int indexBias,
+                         unsigned min_index,
+                         unsigned max_index,
+                         unsigned prim, unsigned start, unsigned count)
+{
+   struct i915_context *i915 = i915_context(pipe);
+   struct pipe_draw_info info;
+   struct pipe_index_buffer saved_ib, ib;
+
+   util_draw_init_info(&info);
+   info.mode = prim;
+   info.start = start;
+   info.count = count;
+   info.index_bias = indexBias;
+   info.min_index = min_index;
+   info.max_index = max_index;
+
+   if (indexBuffer) {
+      info.indexed = TRUE;
+      saved_ib = i915->index_buffer;
+
+      ib.buffer = indexBuffer;
+      ib.offset = 0;
+      ib.index_size = indexSize;
+      pipe->set_index_buffer(pipe, &ib);
+   }
+
+   i915_draw_vbo(pipe, &info);
+
+   if (indexBuffer)
+      pipe->set_index_buffer(pipe, &saved_ib);
+}
+
 static void
 i915_draw_elements(struct pipe_context *pipe,
                    struct pipe_resource *indexBuffer,
@@ -171,6 +206,7 @@ i915_create_context(struct pipe_screen *screen, void *priv)
    i915->base.draw_arrays = i915_draw_arrays;
    i915->base.draw_elements = i915_draw_elements;
    i915->base.draw_range_elements = i915_draw_range_elements;
+   i915->base.draw_vbo = i915_draw_vbo;
 
    /*
     * Create drawing context and plug our rendering stage into it.
diff --git a/src/gallium/drivers/i915/i915_context.h b/src/gallium/drivers/i915/i915_context.h
index b210cb130d..3ae61d0ea7 100644
--- a/src/gallium/drivers/i915/i915_context.h
+++ b/src/gallium/drivers/i915/i915_context.h
@@ -221,6 +221,7 @@ struct i915_context
    struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS];
    struct pipe_viewport_state viewport;
    struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+   struct pipe_index_buffer index_buffer;
 
    unsigned dirty;
 
diff --git a/src/gallium/drivers/i915/i915_state.c b/src/gallium/drivers/i915/i915_state.c
index e767aa9f8f..385c3b2d2d 100644
--- a/src/gallium/drivers/i915/i915_state.c
+++ b/src/gallium/drivers/i915/i915_state.c
@@ -812,6 +812,19 @@ i915_delete_vertex_elements_state(struct pipe_context *pipe, void *velems)
    FREE( velems );
 }
 
+static void i915_set_index_buffer(struct pipe_context *pipe,
+                                  const struct pipe_index_buffer *ib)
+{
+   struct i915_context *i915 = i915_context(pipe);
+
+   if (ib)
+      memcpy(&i915->index_buffer, ib, sizeof(i915->index_buffer));
+   else
+      memset(&i915->index_buffer, 0, sizeof(i915->index_buffer));
+
+   /* TODO make this more like a state */
+}
+
 static void
 i915_set_sample_mask(struct pipe_context *pipe,
                      unsigned sample_mask)
@@ -860,4 +873,5 @@ i915_init_state_functions( struct i915_context *i915 )
    i915->base.sampler_view_destroy = i915_sampler_view_destroy;
    i915->base.set_viewport_state = i915_set_viewport_state;
    i915->base.set_vertex_buffers = i915_set_vertex_buffers;
+   i915->base.set_index_buffer = i915_set_index_buffer;
 }
diff --git a/src/gallium/drivers/i965/brw_context.h b/src/gallium/drivers/i965/brw_context.h
index 94c9c443f0..56d351f97d 100644
--- a/src/gallium/drivers/i965/brw_context.h
+++ b/src/gallium/drivers/i965/brw_context.h
@@ -576,6 +576,7 @@ struct brw_context
        */
       struct pipe_resource *index_buffer;
       unsigned index_size;
+      unsigned index_offset;
 
       /* Updates are signalled by PIPE_NEW_INDEX_RANGE:
        */
diff --git a/src/gallium/drivers/i965/brw_draw.c b/src/gallium/drivers/i965/brw_draw.c
index 4625c2048f..fa7d047e0b 100644
--- a/src/gallium/drivers/i965/brw_draw.c
+++ b/src/gallium/drivers/i965/brw_draw.c
@@ -29,6 +29,7 @@
 #include "util/u_inlines.h"
 #include "util/u_prim.h"
 #include "util/u_upload_mgr.h"
+#include "util/u_draw_quad.h"
 
 #include "brw_draw.h"
 #include "brw_defines.h"
@@ -142,7 +143,7 @@ static int brw_emit_prim(struct brw_context *brw,
  */
 static int
 try_draw_range_elements(struct brw_context *brw,
-			struct pipe_resource *index_buffer,
+			boolean indexed,
 			unsigned hw_prim, 
 			unsigned start, unsigned count)
 {
@@ -165,7 +166,7 @@ try_draw_range_elements(struct brw_context *brw,
    if (ret)
       return ret;
    
-   ret = brw_emit_prim(brw, start, count, index_buffer != NULL, hw_prim);
+   ret = brw_emit_prim(brw, start, count, indexed, hw_prim);
    if (ret)
       return ret;
 
@@ -177,61 +178,86 @@ try_draw_range_elements(struct brw_context *brw,
 
 
 static void
-brw_draw_range_elements(struct pipe_context *pipe,
-			struct pipe_resource *index_buffer,
-			unsigned index_size, int index_bias,
-			unsigned min_index,
-			unsigned max_index,
-			unsigned mode, unsigned start, unsigned count)
+brw_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
    struct brw_context *brw = brw_context(pipe);
    int ret;
    uint32_t hw_prim;
 
-   hw_prim = brw_set_prim(brw, mode);
+   hw_prim = brw_set_prim(brw, info->mode);
 
    if (BRW_DEBUG & DEBUG_PRIMS)
       debug_printf("PRIM: %s start %d count %d index_buffer %p\n",
-                   u_prim_name(mode), start, count, (void *)index_buffer);
-
-   assert(index_bias == 0);
+                   u_prim_name(info->mode), info->start, info->count,
+                   (void *) brw->curr.index_buffer);
 
-   /* Potentially trigger upload of new index buffer.
-    *
-    * XXX: do we need to go through state validation to achieve this?
-    * Could just call upload code directly.
-    */
-   if (brw->curr.index_buffer != index_buffer ||
-       brw->curr.index_size != index_size) {
-      pipe_resource_reference( &brw->curr.index_buffer, index_buffer );
-      brw->curr.index_size = index_size;
-      brw->state.dirty.mesa |= PIPE_NEW_INDEX_BUFFER;
-   }
+   assert(info->index_bias == 0);
 
-   /* XXX: do we really care?
+   /* Potentially trigger upload of new index buffer range.
+    * XXX: do we really care?
     */
-   if (brw->curr.min_index != min_index ||
-       brw->curr.max_index != max_index) 
+   if (brw->curr.min_index != info->min_index ||
+       brw->curr.max_index != info->max_index) 
    { 
-      brw->curr.min_index = min_index;
-      brw->curr.max_index = max_index;
+      brw->curr.min_index = info->min_index;
+      brw->curr.max_index = info->max_index;
       brw->state.dirty.mesa |= PIPE_NEW_INDEX_RANGE;
    }
 
 
    /* Make a first attempt at drawing:
     */
-   ret = try_draw_range_elements(brw, index_buffer, hw_prim, start, count );
+   ret = try_draw_range_elements(brw, info->indexed,
+         hw_prim, info->start, info->count);
 
    /* Otherwise, flush and retry:
     */
    if (ret != 0) {
       brw_context_flush( brw );
-      ret = try_draw_range_elements(brw, index_buffer, hw_prim, start, count );
+      ret = try_draw_range_elements(brw, info->indexed,
+            hw_prim, info->start, info->count);
       assert(ret == 0);
    }
 }
 
+static void
+brw_draw_range_elements(struct pipe_context *pipe,
+			struct pipe_resource *index_buffer,
+			unsigned index_size, int index_bias,
+			unsigned min_index,
+			unsigned max_index,
+			unsigned mode, unsigned start, unsigned count)
+{
+   struct brw_context *brw = brw_context(pipe);
+   struct pipe_draw_info info;
+   struct pipe_index_buffer saved_ib, ib;
+
+   util_draw_init_info(&info);
+   info.mode = mode;
+   info.start = start;
+   info.count = count;
+   info.index_bias = index_bias;
+   info.min_index = min_index;
+   info.max_index = max_index;
+
+   if (index_buffer) {
+      info.indexed = TRUE;
+      saved_ib.buffer = brw->curr.index_buffer;
+      saved_ib.offset = brw->curr.index_offset;
+      saved_ib.index_size = brw->curr.index_size;
+
+      ib.buffer = index_buffer;
+      ib.offset = 0;
+      ib.index_size = index_size;
+      pipe->set_index_buffer(pipe, &ib);
+   }
+
+   brw_draw_vbo(pipe, &info);
+
+   if (index_buffer)
+      pipe->set_index_buffer(pipe, &saved_ib);
+}
+
 static void
 brw_draw_elements(struct pipe_context *pipe,
 		  struct pipe_resource *index_buffer,
@@ -262,6 +288,7 @@ boolean brw_draw_init( struct brw_context *brw )
    brw->base.draw_arrays = brw_draw_arrays;
    brw->base.draw_elements = brw_draw_elements;
    brw->base.draw_range_elements = brw_draw_range_elements;
+   brw->base.draw_vbo = brw_draw_vbo;
 
    /* Create helpers for uploading data in user buffers:
     */
diff --git a/src/gallium/drivers/i965/brw_draw_upload.c b/src/gallium/drivers/i965/brw_draw_upload.c
index 337eee8cd9..ebeb1e146a 100644
--- a/src/gallium/drivers/i965/brw_draw_upload.c
+++ b/src/gallium/drivers/i965/brw_draw_upload.c
@@ -231,7 +231,7 @@ static int brw_prepare_indices(struct brw_context *brw)
    struct pipe_resource *upload_buf = NULL;
    struct brw_winsys_buffer *bo = NULL;
    GLuint offset;
-   GLuint index_size;
+   GLuint index_size, index_offset;
    GLuint ib_size;
    int ret;
 
@@ -246,13 +246,14 @@ static int brw_prepare_indices(struct brw_context *brw)
 
    ib_size = index_buffer->width0;
    index_size = brw->curr.index_size;
+   index_offset = brw->curr.index_offset;
 
    /* Turn userbuffer into a proper hardware buffer?
     */
    if (brw_buffer_is_user_buffer(index_buffer)) {
 
       ret = u_upload_buffer( brw->vb.upload_index,
-			     0,
+			     index_offset,
 			     ib_size,
 			     index_buffer,
 			     &offset,
@@ -269,7 +270,7 @@ static int brw_prepare_indices(struct brw_context *brw)
    else {
       bo = brw_buffer(index_buffer)->bo;
       ib_size = bo->size;
-      offset = 0;
+      offset = index_offset;
    }
 
    /* Use CMD_3D_PRIM's start_vertex_offset to avoid re-uploading the
diff --git a/src/gallium/drivers/i965/brw_pipe_vertex.c b/src/gallium/drivers/i965/brw_pipe_vertex.c
index 4a120a51da..007239efc4 100644
--- a/src/gallium/drivers/i965/brw_pipe_vertex.c
+++ b/src/gallium/drivers/i965/brw_pipe_vertex.c
@@ -274,10 +274,41 @@ static void brw_set_vertex_buffers(struct pipe_context *pipe,
 }
 
 
+static void brw_set_index_buffer(struct pipe_context *pipe,
+                                 const struct pipe_index_buffer *ib)
+{
+   struct brw_context *brw = brw_context(pipe);
+
+   if (ib) {
+      if (brw->curr.index_buffer == ib->buffer &&
+          brw->curr.index_offset == ib->offset &&
+          brw->curr.index_size == ib->index_size)
+         return;
+
+      pipe_resource_reference(&brw->curr.index_buffer, ib->buffer);
+      brw->curr.index_offset = ib->offset;
+      brw->curr.index_size = ib->index_size;
+   }
+   else {
+      if (!brw->curr.index_buffer &&
+          !brw->curr.index_offset &&
+          !brw->curr.index_size)
+         return;
+
+      pipe_resource_reference(&brw->curr.index_buffer, NULL);
+      brw->curr.index_offset = 0;
+      brw->curr.index_size = 0;
+   }
+
+   brw->state.dirty.mesa |= PIPE_NEW_INDEX_BUFFER;
+}
+
+
 void 
 brw_pipe_vertex_init( struct brw_context *brw )
 {
    brw->base.set_vertex_buffers = brw_set_vertex_buffers;
+   brw->base.set_index_buffer = brw_set_index_buffer;
    brw->base.create_vertex_elements_state = brw_create_vertex_elements_state;
    brw->base.bind_vertex_elements_state = brw_bind_vertex_elements_state;
    brw->base.delete_vertex_elements_state = brw_delete_vertex_elements_state;
diff --git a/src/gallium/drivers/identity/id_context.c b/src/gallium/drivers/identity/id_context.c
index 67be895b38..e10d3a1413 100644
--- a/src/gallium/drivers/identity/id_context.c
+++ b/src/gallium/drivers/identity/id_context.c
@@ -110,6 +110,16 @@ identity_draw_range_elements(struct pipe_context *_pipe,
                              count);
 }
 
+static void
+identity_draw_vbo(struct pipe_context *_pipe,
+                  const struct pipe_draw_info *info)
+{
+   struct identity_context *id_pipe = identity_context(_pipe);
+   struct pipe_context *pipe = id_pipe->pipe;
+
+   pipe->draw_vbo(pipe, info);
+}
+
 static struct pipe_query *
 identity_create_query(struct pipe_context *_pipe,
                       unsigned query_type)
@@ -611,6 +621,24 @@ identity_set_vertex_buffers(struct pipe_context *_pipe,
                             num_buffers,
                             buffers);
 }
+
+static void
+identity_set_index_buffer(struct pipe_context *_pipe,
+                          const struct pipe_index_buffer *_ib)
+{
+   struct identity_context *id_pipe = identity_context(_pipe);
+   struct pipe_context *pipe = id_pipe->pipe;
+   struct pipe_index_buffer unwrapped_ib, *ib = NULL;
+
+   if (_ib) {
+      unwrapped_ib = *_ib;
+      unwrapped_ib.buffer = identity_resource_unwrap(_ib->buffer);
+      ib = &unwrapped_ib;
+   }
+
+   pipe->set_index_buffer(pipe, ib);
+}
+
 static void
 identity_resource_copy_region(struct pipe_context *_pipe,
                               struct pipe_resource *_dst,
@@ -892,6 +920,7 @@ identity_context_create(struct pipe_screen *_screen, struct pipe_context *pipe)
    id_pipe->base.draw_arrays = identity_draw_arrays;
    id_pipe->base.draw_elements = identity_draw_elements;
    id_pipe->base.draw_range_elements = identity_draw_range_elements;
+   id_pipe->base.draw_vbo = identity_draw_vbo;
    id_pipe->base.create_query = identity_create_query;
    id_pipe->base.destroy_query = identity_destroy_query;
    id_pipe->base.begin_query = identity_begin_query;
@@ -931,6 +960,7 @@ identity_context_create(struct pipe_screen *_screen, struct pipe_context *pipe)
    id_pipe->base.set_fragment_sampler_views = identity_set_fragment_sampler_views;
    id_pipe->base.set_vertex_sampler_views = identity_set_vertex_sampler_views;
    id_pipe->base.set_vertex_buffers = identity_set_vertex_buffers;
+   id_pipe->base.set_index_buffer = identity_set_index_buffer;
    id_pipe->base.resource_copy_region = identity_resource_copy_region;
    id_pipe->base.clear = identity_clear;
    id_pipe->base.clear_render_target = identity_clear_render_target;
diff --git a/src/gallium/drivers/llvmpipe/lp_context.h b/src/gallium/drivers/llvmpipe/lp_context.h
index b2643ab33c..50f9091c3c 100644
--- a/src/gallium/drivers/llvmpipe/lp_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_context.h
@@ -77,6 +77,7 @@ struct llvmpipe_context {
    struct pipe_sampler_view *vertex_sampler_views[PIPE_MAX_VERTEX_SAMPLERS];
    struct pipe_viewport_state viewport;
    struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+   struct pipe_index_buffer index_buffer;
    struct {
       struct llvmpipe_resource *buffer[PIPE_MAX_SO_BUFFERS];
       int offset[PIPE_MAX_SO_BUFFERS];
diff --git a/src/gallium/drivers/llvmpipe/lp_draw_arrays.c b/src/gallium/drivers/llvmpipe/lp_draw_arrays.c
index 625d0c8a8c..b6dbb9d288 100644
--- a/src/gallium/drivers/llvmpipe/lp_draw_arrays.c
+++ b/src/gallium/drivers/llvmpipe/lp_draw_arrays.c
@@ -34,6 +34,7 @@
 #include "pipe/p_defines.h"
 #include "pipe/p_context.h"
 #include "util/u_prim.h"
+#include "util/u_draw_quad.h"
 
 #include "lp_context.h"
 #include "lp_state.h"
@@ -49,20 +50,11 @@
  * the drawing to the 'draw' module.
  */
 static void
-llvmpipe_draw_range_elements_instanced(struct pipe_context *pipe,
-                                       struct pipe_resource *indexBuffer,
-                                       unsigned indexSize,
-                                       int indexBias,
-                                       unsigned minIndex,
-                                       unsigned maxIndex,
-                                       unsigned mode,
-                                       unsigned start,
-                                       unsigned count,
-                                       unsigned startInstance,
-                                       unsigned instanceCount)
+llvmpipe_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
    struct llvmpipe_context *lp = llvmpipe_context(pipe);
    struct draw_context *draw = lp->draw;
+   void *mapped_indices = NULL;
    unsigned i;
 
    if (lp->dirty)
@@ -77,27 +69,25 @@ llvmpipe_draw_range_elements_instanced(struct pipe_context *pipe,
    }
 
    /* Map index buffer, if present */
-   if (indexBuffer) {
-      void *mapped_indexes = llvmpipe_resource_data(indexBuffer);
-      draw_set_mapped_element_buffer_range(draw,
-                                           indexSize,
-                                           indexBias,
-                                           minIndex,
-                                           maxIndex,
-                                           mapped_indexes);
-   }
-   else {
-      /* no index/element buffer */
-      draw_set_mapped_element_buffer_range(draw, 0, 0, start,
-                                           start + count - 1, NULL);
+   if (info->indexed && lp->index_buffer.buffer) {
+      mapped_indices = llvmpipe_resource_data(lp->index_buffer.buffer);
+      mapped_indices += lp->index_buffer.offset;
    }
+
+   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
+                                        lp->index_buffer.index_size : 0,
+                                        info->index_bias,
+                                        info->min_index,
+                                        info->max_index,
+                                        mapped_indices);
+
    llvmpipe_prepare_vertex_sampling(lp,
                                     lp->num_vertex_sampler_views,
                                     lp->vertex_sampler_views);
 
    /* draw! */
-   draw_arrays_instanced(draw, mode, start, count,
-                         startInstance, instanceCount);
+   draw_arrays_instanced(draw, info->mode, info->start, info->count,
+         info->start_instance, info->instance_count);
 
    /*
     * unmap vertex/index buffers
@@ -105,7 +95,7 @@ llvmpipe_draw_range_elements_instanced(struct pipe_context *pipe,
    for (i = 0; i < lp->num_vertex_buffers; i++) {
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
-   if (indexBuffer) {
+   if (mapped_indices) {
       draw_set_mapped_element_buffer(draw, 0, 0, NULL);
    }
    llvmpipe_cleanup_vertex_sampling(lp);
@@ -119,6 +109,50 @@ llvmpipe_draw_range_elements_instanced(struct pipe_context *pipe,
 }
 
 
+static void
+llvmpipe_draw_range_elements_instanced(struct pipe_context *pipe,
+                                       struct pipe_resource *indexBuffer,
+                                       unsigned indexSize,
+                                       int indexBias,
+                                       unsigned minIndex,
+                                       unsigned maxIndex,
+                                       unsigned mode,
+                                       unsigned start,
+                                       unsigned count,
+                                       unsigned startInstance,
+                                       unsigned instanceCount)
+{
+   struct llvmpipe_context *lp = llvmpipe_context(pipe);
+   struct pipe_draw_info info;
+   struct pipe_index_buffer saved_ib, ib;
+
+   util_draw_init_info(&info);
+   info.mode = mode;
+   info.start = start;
+   info.count = count;
+   info.start_instance = startInstance;
+   info.instance_count = instanceCount;
+
+   info.index_bias = indexBias;
+   info.min_index = minIndex;
+   info.max_index = maxIndex;
+
+   if (indexBuffer) {
+      info.indexed = TRUE;
+      saved_ib = lp->index_buffer;
+
+      ib.buffer = indexBuffer;
+      ib.offset = 0;
+      ib.index_size = indexSize;
+      pipe->set_index_buffer(pipe, &ib);
+   }
+
+   llvmpipe_draw_vbo(pipe, &info);
+
+   if (indexBuffer)
+      pipe->set_index_buffer(pipe, &saved_ib);
+}
+
 static void
 llvmpipe_draw_arrays_instanced(struct pipe_context *pipe,
                                unsigned mode,
@@ -227,4 +261,6 @@ llvmpipe_init_draw_funcs(struct llvmpipe_context *llvmpipe)
    llvmpipe->pipe.draw_range_elements = llvmpipe_draw_range_elements;
    llvmpipe->pipe.draw_arrays_instanced = llvmpipe_draw_arrays_instanced;
    llvmpipe->pipe.draw_elements_instanced = llvmpipe_draw_elements_instanced;
+
+   llvmpipe->pipe.draw_vbo = llvmpipe_draw_vbo;
 }
diff --git a/src/gallium/drivers/llvmpipe/lp_state_vertex.c b/src/gallium/drivers/llvmpipe/lp_state_vertex.c
index 113f13db01..d86e66b4fb 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_vertex.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_vertex.c
@@ -89,6 +89,19 @@ llvmpipe_set_vertex_buffers(struct pipe_context *pipe,
 }
 
 
+static void
+llvmpipe_set_index_buffer(struct pipe_context *pipe,
+                          const struct pipe_index_buffer *ib)
+{
+   struct llvmpipe_context *llvmpipe = llvmpipe_context(pipe);
+
+   if (ib)
+      memcpy(&llvmpipe->index_buffer, ib, sizeof(llvmpipe->index_buffer));
+   else
+      memset(&llvmpipe->index_buffer, 0, sizeof(llvmpipe->index_buffer));
+
+   /* TODO make this more like a state */
+}
 
 void
 llvmpipe_init_vertex_funcs(struct llvmpipe_context *llvmpipe)
@@ -98,4 +111,5 @@ llvmpipe_init_vertex_funcs(struct llvmpipe_context *llvmpipe)
    llvmpipe->pipe.delete_vertex_elements_state = llvmpipe_delete_vertex_elements_state;
 
    llvmpipe->pipe.set_vertex_buffers = llvmpipe_set_vertex_buffers;
+   llvmpipe->pipe.set_index_buffer = llvmpipe_set_index_buffer;
 }
diff --git a/src/gallium/drivers/nv50/nv50_context.c b/src/gallium/drivers/nv50/nv50_context.c
index 915a925402..3fc39c1137 100644
--- a/src/gallium/drivers/nv50/nv50_context.c
+++ b/src/gallium/drivers/nv50/nv50_context.c
@@ -86,6 +86,7 @@ nv50_create(struct pipe_screen *pscreen, void *priv)
 	nv50->pipe.draw_arrays_instanced = nv50_draw_arrays_instanced;
 	nv50->pipe.draw_elements = nv50_draw_elements;
 	nv50->pipe.draw_elements_instanced = nv50_draw_elements_instanced;
+	nv50->pipe.draw_vbo = nv50_draw_vbo;
 	nv50->pipe.clear = nv50_clear;
 
 	nv50->pipe.flush = nv50_flush;
diff --git a/src/gallium/drivers/nv50/nv50_context.h b/src/gallium/drivers/nv50/nv50_context.h
index 12c4a93a9b..a7c2b5d487 100644
--- a/src/gallium/drivers/nv50/nv50_context.h
+++ b/src/gallium/drivers/nv50/nv50_context.h
@@ -148,6 +148,7 @@ struct nv50_context {
 	struct pipe_resource *constbuf[PIPE_SHADER_TYPES];
 	struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
 	unsigned vtxbuf_nr;
+	struct pipe_index_buffer idxbuf;
 	struct nv50_vtxelt_stateobj *vtxelt;
 	struct nv50_sampler_stateobj *sampler[3][PIPE_MAX_SAMPLERS];
 	unsigned sampler_nr[3];
@@ -197,6 +198,8 @@ extern void nv50_draw_elements_instanced(struct pipe_context *pipe,
 					 unsigned count,
 					 unsigned startInstance,
 					 unsigned instanceCount);
+extern void nv50_draw_vbo(struct pipe_context *pipe,
+                          const struct pipe_draw_info *info);
 extern void nv50_vtxelt_construct(struct nv50_vtxelt_stateobj *cso);
 extern struct nouveau_stateobj *nv50_vbo_validate(struct nv50_context *nv50);
 
diff --git a/src/gallium/drivers/nv50/nv50_state.c b/src/gallium/drivers/nv50/nv50_state.c
index 42c5a58318..ec0c0ff283 100644
--- a/src/gallium/drivers/nv50/nv50_state.c
+++ b/src/gallium/drivers/nv50/nv50_state.c
@@ -742,6 +742,20 @@ nv50_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
 	nv50->dirty |= NV50_NEW_ARRAYS;
 }
 
+static void
+nv50_set_index_buffer(struct pipe_context *pipe,
+		      const struct pipe_index_buffer *ib)
+{
+	struct nv50_context *nv50 = nv50_context(pipe);
+
+	if (ib)
+		memcpy(&nv50->idxbuf, ib, sizeof(nv50->idxbuf));
+	else
+		memset(&nv50->idxbuf, 0, sizeof(nv50->idxbuf));
+
+	/* TODO make this more like a state */
+}
+
 static void *
 nv50_vtxelts_state_create(struct pipe_context *pipe,
 			  unsigned num_elements,
@@ -827,5 +841,6 @@ nv50_init_state_functions(struct nv50_context *nv50)
 	nv50->pipe.bind_vertex_elements_state = nv50_vtxelts_state_bind;
 
 	nv50->pipe.set_vertex_buffers = nv50_set_vertex_buffers;
+	nv50->pipe.set_index_buffer = nv50_set_index_buffer;
 }
 
diff --git a/src/gallium/drivers/nv50/nv50_vbo.c b/src/gallium/drivers/nv50/nv50_vbo.c
index 864cb09352..11ffc182c2 100644
--- a/src/gallium/drivers/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nv50/nv50_vbo.c
@@ -473,6 +473,37 @@ nv50_draw_elements(struct pipe_context *pipe,
 				     mode, start, count, 0, 1);
 }
 
+void
+nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
+{
+	struct nv50_context *nv50 = nv50_context(pipe);
+
+	if (info->indexed && nv50->idxbuf.buffer) {
+		unsigned offset;
+
+		assert(nv50->idxbuf.offset % nv50->idxbuf.index_size == 0);
+		offset = nv50->idxbuf.offset / nv50->idxbuf.index_size;
+
+		nv50_draw_elements_instanced(pipe,
+					     nv50->idxbuf.buffer,
+					     nv50->idxbuf.index_size,
+					     info->index_bias,
+					     info->mode,
+					     info->start + offset,
+					     info->count,
+					     info->start_instance,
+					     info->instance_count);
+	}
+	else {
+		nv50_draw_arrays_instanced(pipe,
+					   info->mode,
+					   info->start,
+					   info->count,
+					   info->start_instance,
+					   info->instance_count);
+	}
+}
+
 static INLINE boolean
 nv50_vbo_static_attrib(struct nv50_context *nv50, unsigned attrib,
 		       struct nouveau_stateobj **pso,
diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 6d2dc4d5bf..f30795f69a 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -57,6 +57,7 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	nvfx->pipe.destroy = nvfx_destroy;
 	nvfx->pipe.draw_arrays = nvfx_draw_arrays;
 	nvfx->pipe.draw_elements = nvfx_draw_elements;
+	nvfx->pipe.draw_vbo = nvfx_draw_vbo;
 	nvfx->pipe.clear = nvfx_clear;
 	nvfx->pipe.flush = nvfx_flush;
 
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index e48f9f3aa8..d6cd272eed 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -121,7 +121,8 @@ struct nvfx_context {
 	struct pipe_stencil_ref stencil_ref;
 	struct pipe_viewport_state viewport;
 	struct pipe_framebuffer_state framebuffer;
-	struct pipe_resource *idxbuf;
+	struct pipe_index_buffer idxbuf;
+	struct pipe_resource *idxbuf_buffer;
 	unsigned idxbuf_format;
 	struct nvfx_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
 	struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS];
@@ -242,6 +243,8 @@ extern void nvfx_draw_elements(struct pipe_context *pipe,
                                unsigned indexSize, int indexBias,
                                unsigned mode, unsigned start,
                                unsigned count);
+extern void nvfx_draw_vbo(struct pipe_context *pipe,
+                          const struct pipe_draw_info *info);
 
 /* nvfx_vertprog.c */
 extern boolean nvfx_vertprog_validate(struct nvfx_context *nvfx);
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index 30322d46d9..cd58e439d7 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -555,6 +555,20 @@ nvfx_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
 	nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
 }
 
+static void
+nvfx_set_index_buffer(struct pipe_context *pipe,
+		      const struct pipe_index_buffer *ib)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+
+	if (ib)
+		memcpy(&nvfx->idxbuf, ib, sizeof(nvfx->idxbuf));
+	else
+		memset(&nvfx->idxbuf, 0, sizeof(nvfx->idxbuf));
+
+	/* TODO make this more like a state */
+}
+
 static void *
 nvfx_vtxelts_state_create(struct pipe_context *pipe,
 			  unsigned num_elements,
@@ -635,4 +649,5 @@ nvfx_init_state_functions(struct nvfx_context *nvfx)
 	nvfx->pipe.bind_vertex_elements_state = nvfx_vtxelts_state_bind;
 
 	nvfx->pipe.set_vertex_buffers = nvfx_set_vertex_buffers;
+	nvfx->pipe.set_index_buffer = nvfx_set_index_buffer;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index 520bae5aed..23a59b589b 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -85,7 +85,7 @@ nvfx_vbo_set_idxbuf(struct nvfx_context *nvfx, struct pipe_resource *ib,
 	unsigned type;
 
 	if (!ib) {
-		nvfx->idxbuf = NULL;
+		nvfx->idxbuf_buffer = NULL;
 		nvfx->idxbuf_format = 0xdeadbeef;
 		return FALSE;
 	}
@@ -104,10 +104,10 @@ nvfx_vbo_set_idxbuf(struct nvfx_context *nvfx, struct pipe_resource *ib,
 		return FALSE;
 	}
 
-	if (ib != nvfx->idxbuf ||
+	if (ib != nvfx->idxbuf_buffer ||
 	    type != nvfx->idxbuf_format) {
 		nvfx->dirty |= NVFX_NEW_ARRAYS;
-		nvfx->idxbuf = ib;
+		nvfx->idxbuf_buffer = ib;
 		nvfx->idxbuf_format = type;
 	}
 
@@ -491,11 +491,38 @@ nvfx_draw_elements(struct pipe_context *pipe,
 	pipe->flush(pipe, 0, NULL);
 }
 
+void
+nvfx_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+
+	if (info->indexed && nvfx->idxbuf.buffer) {
+		unsigned offset;
+
+		assert(nvfx->idxbuf.offset % nvfx->idxbuf.index_size == 0);
+		offset = nvfx->idxbuf.offset / nvfx->idxbuf.index_size;
+
+		nvfx_draw_elements(pipe,
+				   nvfx->idxbuf.buffer,
+				   nvfx->idxbuf.index_size,
+				   info->index_bias,
+				   info->mode,
+				   info->start + offset,
+				   info->count);
+	}
+	else {
+		nvfx_draw_arrays(pipe,
+				info->mode,
+				info->start,
+				info->count);
+	}
+}
+
 boolean
 nvfx_vbo_validate(struct nvfx_context *nvfx)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	struct pipe_resource *ib = nvfx->idxbuf;
+	struct pipe_resource *ib = nvfx->idxbuf_buffer;
 	unsigned ib_format = nvfx->idxbuf_format;
 	int i;
 	int elements = MAX2(nvfx->vtxelt->num_elements, nvfx->hw_vtxelt_nr);
@@ -610,10 +637,10 @@ nvfx_vbo_relocate(struct nvfx_context *nvfx)
 		}
 	}
 
-	if(nvfx->idxbuf)
+	if(nvfx->idxbuf_buffer)
 	{
 		unsigned ib_flags = nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
-		struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf)->bo;
+		struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf_buffer)->bo;
 
 		assert(nvfx->screen->index_buffer_reloc_flags);
 
diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
index b4256c6278..7c77a46016 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -524,6 +524,8 @@ struct r300_context {
     struct r300_vertex_element_state *velems;
     bool any_user_vbs;
 
+    struct pipe_index_buffer index_buffer;
+
     /* Vertex info for Draw. */
     struct vertex_info vertex_info;
 
diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c
index bae02135da..da96098cc4 100644
--- a/src/gallium/drivers/r300/r300_render.c
+++ b/src/gallium/drivers/r300/r300_render.c
@@ -33,6 +33,7 @@
 #include "util/u_memory.h"
 #include "util/u_upload_mgr.h"
 #include "util/u_prim.h"
+#include "util/u_draw_quad.h"
 
 #include "r300_cs.h"
 #include "r300_context.h"
@@ -638,26 +639,56 @@ static void r300_draw_arrays(struct pipe_context* pipe, unsigned mode,
     }
 }
 
+static void r300_draw_vbo(struct pipe_context* pipe,
+                          const struct pipe_draw_info *info)
+{
+    struct r300_context* r300 = r300_context(pipe);
+
+    if (info->indexed && r300->index_buffer.buffer) {
+        unsigned offset;
+
+        assert(r300->index_buffer.offset % r300->index_buffer.index_size == 0);
+        offset = r300->index_buffer.offset / r300->index_buffer.index_size;
+
+        r300_draw_range_elements(pipe,
+                                 r300->index_buffer.buffer,
+                                 r300->index_buffer.index_size,
+                                 info->index_bias,
+                                 info->min_index,
+                                 info->max_index,
+                                 info->mode,
+                                 info->start + offset,
+                                 info->count);
+    }
+    else {
+        r300_draw_arrays(pipe,
+                         info->mode,
+                         info->start,
+                         info->count);
+    }
+}
+
 /****************************************************************************
  * The rest of this file is for SW TCL rendering only. Please be polite and *
  * keep these functions separated so that they are easier to locate. ~C.    *
  ***************************************************************************/
 
-/* SW TCL arrays, using Draw. */
-static void r300_swtcl_draw_arrays(struct pipe_context* pipe,
-                                   unsigned mode,
-                                   unsigned start,
-                                   unsigned count)
+/* SW TCL elements, using Draw. */
+static void r300_swtcl_draw_vbo(struct pipe_context* pipe,
+                                const struct pipe_draw_info *info)
 {
     struct r300_context* r300 = r300_context(pipe);
     struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
+    struct pipe_transfer *ib_transfer;
+    unsigned count = info->count;
     int i;
+    void* indices = NULL;
 
     if (r300->skip_rendering) {
         return;
     }
 
-    if (!u_trim_pipe_prim(mode, &count)) {
+    if (!u_trim_pipe_prim(info->mode, &count)) {
         return;
     }
 
@@ -667,13 +698,25 @@ static void r300_swtcl_draw_arrays(struct pipe_context* pipe,
         void* buf = pipe_buffer_map(pipe,
                                     r300->vertex_buffer[i].buffer,
                                     PIPE_TRANSFER_READ,
-				    &vb_transfer[i]);
+                                    &vb_transfer[i]);
         draw_set_mapped_vertex_buffer(r300->draw, i, buf);
     }
 
-    draw_set_mapped_element_buffer(r300->draw, 0, 0, NULL);
+    if (info->indexed && r300->index_buffer.buffer) {
+        indices = pipe_buffer_map(pipe, r300->index_buffer.buffer,
+                                  PIPE_TRANSFER_READ, &ib_transfer);
+        if (indices)
+            indices += r300->index_buffer.offset;
+    }
+
+    draw_set_mapped_element_buffer_range(r300->draw, (indices) ?
+                                         r300->index_buffer.index_size : 0,
+                                         info->index_bias,
+                                         info->min_index,
+                                         info->max_index,
+                                         indices);
 
-    draw_arrays(r300->draw, mode, start, count);
+    draw_arrays(r300->draw, info->mode, info->start, count);
 
     /* XXX Not sure whether this is the best fix.
      * It prevents CS from being rejected and weird assertion failures. */
@@ -681,9 +724,15 @@ static void r300_swtcl_draw_arrays(struct pipe_context* pipe,
 
     for (i = 0; i < r300->vertex_buffer_count; i++) {
         pipe_buffer_unmap(pipe, r300->vertex_buffer[i].buffer,
-			  vb_transfer[i]);
+                          vb_transfer[i]);
         draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
     }
+
+    if (ib_transfer) {
+        pipe_buffer_unmap(pipe, r300->index_buffer.buffer, ib_transfer);
+        draw_set_mapped_element_buffer_range(r300->draw, 0, 0, info->start,
+                info->start + count - 1, NULL);
+    }
 }
 
 /* SW TCL elements, using Draw. */
@@ -698,51 +747,40 @@ static void r300_swtcl_draw_range_elements(struct pipe_context* pipe,
                                            unsigned count)
 {
     struct r300_context* r300 = r300_context(pipe);
-    struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
-    struct pipe_transfer *ib_transfer;
-    int i;
-    void* indices;
-
-    if (r300->skip_rendering) {
-        return;
-    }
-
-    if (!u_trim_pipe_prim(mode, &count)) {
-        return;
+    struct pipe_draw_info info;
+    struct pipe_index_buffer saved_ib, ib;
+
+    util_draw_init_info(&info);
+    info.mode = mode;
+    info.start = start;
+    info.count = count;
+    info.index_bias = indexBias;
+    info.min_index = minIndex;
+    info.max_index = maxIndex;
+
+    if (indexBuffer) {
+       info.indexed = TRUE;
+
+       saved_ib = r300->index_buffer;
+       ib.buffer = indexBuffer;
+       ib.offset = 0;
+       ib.index_size = indexSize;
+       pipe->set_index_buffer(pipe, &ib);
     }
 
-    r300_update_derived_state(r300);
-
-    for (i = 0; i < r300->vertex_buffer_count; i++) {
-        void* buf = pipe_buffer_map(pipe,
-                                    r300->vertex_buffer[i].buffer,
-                                    PIPE_TRANSFER_READ,
-				    &vb_transfer[i]);
-        draw_set_mapped_vertex_buffer(r300->draw, i, buf);
-    }
-
-    indices = pipe_buffer_map(pipe, indexBuffer,
-                              PIPE_TRANSFER_READ, &ib_transfer);
-    draw_set_mapped_element_buffer_range(r300->draw, indexSize, indexBias,
-                                         minIndex, maxIndex, indices);
-
-    draw_arrays(r300->draw, mode, start, count);
-
-    /* XXX Not sure whether this is the best fix.
-     * It prevents CS from being rejected and weird assertion failures. */
-    draw_flush(r300->draw);
+    r300_swtcl_draw_vbo(pipe, &info);
 
-    for (i = 0; i < r300->vertex_buffer_count; i++) {
-        pipe_buffer_unmap(pipe, r300->vertex_buffer[i].buffer,
-			  vb_transfer[i]);
-        draw_set_mapped_vertex_buffer(r300->draw, i, NULL);
-    }
+    if (indexBuffer)
+       pipe->set_index_buffer(pipe, &saved_ib);
+}
 
-    pipe_buffer_unmap(pipe, indexBuffer,
-		      ib_transfer);
-    draw_set_mapped_element_buffer_range(r300->draw, 0, 0,
-                                         start, start + count - 1,
-                                         NULL);
+static void r300_swtcl_draw_arrays(struct pipe_context* pipe,
+                                   unsigned mode,
+                                   unsigned start,
+                                   unsigned count)
+{
+   r300_swtcl_draw_range_elements(pipe, NULL, 0, 0,
+           start, start + count -1, mode, start, count);
 }
 
 /* Object for rendering using Draw. */
@@ -1148,9 +1186,11 @@ void r300_init_render_functions(struct r300_context *r300)
     if (r300->screen->caps.has_tcl) {
         r300->context.draw_arrays = r300_draw_arrays;
         r300->context.draw_range_elements = r300_draw_range_elements;
+        r300->context.draw_vbo = r300_draw_vbo;
     } else {
         r300->context.draw_arrays = r300_swtcl_draw_arrays;
         r300->context.draw_range_elements = r300_swtcl_draw_range_elements;
+        r300->context.draw_vbo = r300_swtcl_draw_vbo;
     }
 
     r300->context.resource_resolve = r300_resource_resolve;
diff --git a/src/gallium/drivers/r300/r300_render_stencilref.c b/src/gallium/drivers/r300/r300_render_stencilref.c
index 9a6b4e12ff..6d801cf159 100644
--- a/src/gallium/drivers/r300/r300_render_stencilref.c
+++ b/src/gallium/drivers/r300/r300_render_stencilref.c
@@ -42,6 +42,9 @@ struct r300_stencilref_context {
         unsigned indexSize, int indexBias, unsigned minIndex, unsigned maxIndex,
         unsigned mode, unsigned start, unsigned count);
 
+    void (*draw_vbo)(struct pipe_context *pipe,
+                     const struct pipe_draw_info *info);
+
     uint32_t rs_cull_mode;
     uint32_t zb_stencilrefmask;
     ubyte ref_value_front;
@@ -144,6 +147,23 @@ static void r300_stencilref_draw_range_elements(
     }
 }
 
+static void r300_stencilref_draw_vbo(struct pipe_context *pipe,
+                                     const struct pipe_draw_info *info)
+{
+    struct r300_context *r300 = r300_context(pipe);
+    struct r300_stencilref_context *sr = r300->stencilref_fallback;
+
+    if (!r300_stencilref_needed(r300)) {
+        sr->draw_vbo(pipe, info);
+    } else {
+        r300_stencilref_begin(r300);
+        sr->draw_vbo(pipe, info);
+        r300_stencilref_switch_side(r300);
+        sr->draw_vbo(pipe, info);
+        r300_stencilref_end(r300);
+    }
+}
+
 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300)
 {
     r300->stencilref_fallback = CALLOC_STRUCT(r300_stencilref_context);
@@ -151,8 +171,10 @@ void r300_plug_in_stencil_ref_fallback(struct r300_context *r300)
     /* Save original draw functions. */
     r300->stencilref_fallback->draw_arrays = r300->context.draw_arrays;
     r300->stencilref_fallback->draw_range_elements = r300->context.draw_range_elements;
+    r300->stencilref_fallback->draw_vbo = r300->context.draw_vbo;
 
     /* Override the draw functions. */
     r300->context.draw_arrays = r300_stencilref_draw_arrays;
     r300->context.draw_range_elements = r300_stencilref_draw_range_elements;
+    r300->context.draw_vbo = r300_stencilref_draw_vbo;
 }
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 3e221f2e02..bccd7d7859 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -1505,6 +1505,23 @@ static void r300_set_vertex_buffers(struct pipe_context* pipe,
     r300->vertex_buffer_count = count;
 }
 
+static void r300_set_index_buffer(struct pipe_context* pipe,
+                                  const struct pipe_index_buffer *ib)
+{
+    struct r300_context* r300 = r300_context(pipe);
+
+    if (ib) {
+        pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer);
+        memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer));
+    }
+    else {
+        pipe_resource_reference(&r300->index_buffer.buffer, NULL);
+        memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
+    }
+
+    /* TODO make this more like a state */
+}
+
 /* Initialize the PSC tables. */
 static void r300_vertex_psc(struct r300_vertex_element_state *velems)
 {
@@ -1852,6 +1869,7 @@ void r300_init_state_functions(struct r300_context* r300)
     r300->context.set_viewport_state = r300_set_viewport_state;
 
     r300->context.set_vertex_buffers = r300_set_vertex_buffers;
+    r300->context.set_index_buffer = r300_set_index_buffer;
 
     r300->context.create_vertex_elements_state = r300_create_vertex_elements_state;
     r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state;
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 4c7b67ea52..2c2bd4672b 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -316,6 +316,7 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 	rctx->context.draw_arrays = r600_draw_arrays;
 	rctx->context.draw_elements = r600_draw_elements;
 	rctx->context.draw_range_elements = r600_draw_range_elements;
+	rctx->context.draw_vbo = r600_draw_vbo;
 	rctx->context.flush = r600_flush;
 
 	/* Easy accessing of screen/winsys. */
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 1f03b202ee..9427c19d05 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -157,6 +157,7 @@ struct r600_context {
 	struct r600_context_state	*vs_sampler_view[PIPE_MAX_ATTRIBS];
 	struct r600_vertex_element	*vertex_elements;
 	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
+	struct pipe_index_buffer	index_buffer;
 };
 
 #if 0
@@ -201,6 +202,8 @@ void r600_draw_range_elements(struct pipe_context *ctx,
 		unsigned index_size, int index_bias, unsigned min_index,
 		unsigned max_index, unsigned mode,
 		unsigned start, unsigned count);
+void r600_draw_vbo(struct pipe_context *ctx,
+                   const struct pipe_draw_info *info);
 
 void r600_init_blit_functions(struct r600_context *rctx);
 void r600_init_state_functions(struct r600_context *rctx);
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index b248beaf8c..eeaa677edb 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -225,3 +225,30 @@ void r600_draw_arrays(struct pipe_context *ctx, unsigned mode,
 	draw.index_buffer = NULL;
 	r600_draw_common(&draw);
 }
+
+void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_draw draw;
+
+	assert(info->index_bias == 0);
+
+	draw.ctx = ctx;
+	draw.mode = info->mode;
+	draw.start = info->start;
+	draw.count = info->count;
+	if (info->indexed && rctx->index_buffer.buffer) {
+		draw.index_size = rctx->index_buffer.index_size;
+		draw.index_buffer = rctx->index_buffer.buffer;
+
+		assert(rctx->index_buffer.offset %
+				rctx->index_buffer.index_size == 0);
+		draw.start += rctx->index_buffer.offset /
+			rctx->index_buffer.index_size;
+	}
+	else {
+		draw.index_size = 0;
+		draw.index_buffer = NULL;
+	}
+	r600_draw_common(&draw);
+}
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index ff5df855c6..57879e8d8b 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -404,6 +404,23 @@ static void r600_set_vertex_buffers(struct pipe_context *ctx,
 	rctx->nvertex_buffer = count;
 }
 
+static void r600_set_index_buffer(struct pipe_context *ctx,
+				  const struct pipe_index_buffer *ib)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	if (ib) {
+		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
+		memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
+	}
+	else {
+		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
+		memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
+	}
+
+	/* TODO make this more like a state */
+}
+
 static void r600_set_viewport_state(struct pipe_context *ctx,
 					const struct pipe_viewport_state *state)
 {
@@ -449,6 +466,7 @@ void r600_init_state_functions(struct r600_context *rctx)
 	rctx->context.set_scissor_state = r600_set_scissor_state;
 	rctx->context.set_stencil_ref = r600_set_stencil_ref;
 	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
+	rctx->context.set_index_buffer = r600_set_index_buffer;
 	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
 	rctx->context.set_viewport_state = r600_set_viewport_state;
 	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
diff --git a/src/gallium/drivers/rbug/rbug_context.c b/src/gallium/drivers/rbug/rbug_context.c
index e0dd5cf8c2..c748073b2a 100644
--- a/src/gallium/drivers/rbug/rbug_context.c
+++ b/src/gallium/drivers/rbug/rbug_context.c
@@ -185,6 +185,21 @@ rbug_draw_range_elements(struct pipe_context *_pipe,
    pipe_mutex_unlock(rb_pipe->draw_mutex);
 }
 
+static void
+rbug_draw_vbo(struct pipe_context *_pipe, const struct pipe_draw_info *info)
+{
+   struct rbug_context *rb_pipe = rbug_context(_pipe);
+   struct pipe_context *pipe = rb_pipe->pipe;
+
+   pipe_mutex_lock(rb_pipe->draw_mutex);
+   rbug_draw_block_locked(rb_pipe, RBUG_BLOCK_BEFORE);
+
+   pipe->draw_vbo(pipe, info);
+
+   rbug_draw_block_locked(rb_pipe, RBUG_BLOCK_AFTER);
+   pipe_mutex_unlock(rb_pipe->draw_mutex);
+}
+
 static struct pipe_query *
 rbug_create_query(struct pipe_context *_pipe,
                   unsigned query_type)
@@ -744,6 +759,23 @@ rbug_set_vertex_buffers(struct pipe_context *_pipe,
                             buffers);
 }
 
+static void
+rbug_set_index_buffer(struct pipe_context *_pipe,
+                      const struct pipe_index_buffer *_ib)
+{
+   struct rbug_context *rb_pipe = rbug_context(_pipe);
+   struct pipe_context *pipe = rb_pipe->pipe;
+   struct pipe_index_buffer unwrapped_ib, *ib = NULL;
+
+   if (_ib) {
+      unwrapped_ib = *_ib;
+      unwrapped_ib.buffer = rbug_resource_unwrap(_ib->buffer);
+      ib = &unwrapped_ib;
+   }
+
+   pipe->set_index_buffer(pipe, ib);
+}
+
 static void
 rbug_set_sample_mask(struct pipe_context *_pipe,
                      unsigned sample_mask)
@@ -1043,6 +1075,7 @@ rbug_context_create(struct pipe_screen *_screen, struct pipe_context *pipe)
    rb_pipe->base.draw_arrays = rbug_draw_arrays;
    rb_pipe->base.draw_elements = rbug_draw_elements;
    rb_pipe->base.draw_range_elements = rbug_draw_range_elements;
+   rb_pipe->base.draw_vbo = rbug_draw_vbo;
    rb_pipe->base.create_query = rbug_create_query;
    rb_pipe->base.destroy_query = rbug_destroy_query;
    rb_pipe->base.begin_query = rbug_begin_query;
@@ -1084,6 +1117,7 @@ rbug_context_create(struct pipe_screen *_screen, struct pipe_context *pipe)
    rb_pipe->base.set_fragment_sampler_views = rbug_set_fragment_sampler_views;
    rb_pipe->base.set_vertex_sampler_views = rbug_set_vertex_sampler_views;
    rb_pipe->base.set_vertex_buffers = rbug_set_vertex_buffers;
+   rb_pipe->base.set_index_buffer = rbug_set_index_buffer;
    rb_pipe->base.set_sample_mask = rbug_set_sample_mask;
    rb_pipe->base.resource_copy_region = rbug_resource_copy_region;
    rb_pipe->base.clear = rbug_clear;
diff --git a/src/gallium/drivers/softpipe/sp_context.c b/src/gallium/drivers/softpipe/sp_context.c
index 12ef98aac7..fa1fae6f00 100644
--- a/src/gallium/drivers/softpipe/sp_context.c
+++ b/src/gallium/drivers/softpipe/sp_context.c
@@ -282,12 +282,14 @@ softpipe_create_context( struct pipe_screen *screen,
    softpipe->pipe.set_viewport_state = softpipe_set_viewport_state;
    softpipe->pipe.set_stream_output_buffers = softpipe_set_stream_output_buffers;
    softpipe->pipe.set_vertex_buffers = softpipe_set_vertex_buffers;
+   softpipe->pipe.set_index_buffer = softpipe_set_index_buffer;
 
    softpipe->pipe.draw_arrays = softpipe_draw_arrays;
    softpipe->pipe.draw_elements = softpipe_draw_elements;
    softpipe->pipe.draw_range_elements = softpipe_draw_range_elements;
    softpipe->pipe.draw_arrays_instanced = softpipe_draw_arrays_instanced;
    softpipe->pipe.draw_elements_instanced = softpipe_draw_elements_instanced;
+   softpipe->pipe.draw_vbo = softpipe_draw_vbo;
    softpipe->pipe.draw_stream_output = softpipe_draw_stream_output;
 
    softpipe->pipe.clear = softpipe_clear;
diff --git a/src/gallium/drivers/softpipe/sp_context.h b/src/gallium/drivers/softpipe/sp_context.h
index 53115a827d..c5f53cfa61 100644
--- a/src/gallium/drivers/softpipe/sp_context.h
+++ b/src/gallium/drivers/softpipe/sp_context.h
@@ -82,6 +82,7 @@ struct softpipe_context {
    struct pipe_sampler_view *geometry_sampler_views[PIPE_MAX_GEOMETRY_SAMPLERS];
    struct pipe_viewport_state viewport;
    struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
+   struct pipe_index_buffer index_buffer;
    struct {
       struct softpipe_resource *buffer[PIPE_MAX_SO_BUFFERS];
       int offset[PIPE_MAX_SO_BUFFERS];
diff --git a/src/gallium/drivers/softpipe/sp_draw_arrays.c b/src/gallium/drivers/softpipe/sp_draw_arrays.c
index 9e727c9381..2855f55a0e 100644
--- a/src/gallium/drivers/softpipe/sp_draw_arrays.c
+++ b/src/gallium/drivers/softpipe/sp_draw_arrays.c
@@ -35,6 +35,7 @@
 #include "pipe/p_context.h"
 #include "util/u_inlines.h"
 #include "util/u_prim.h"
+#include "util/u_draw_quad.h"
 
 #include "sp_context.h"
 #include "sp_query.h"
@@ -111,27 +112,19 @@ softpipe_draw_stream_output(struct pipe_context *pipe, unsigned mode)
  * When the min/max element indexes aren't known, minIndex should be 0
  * and maxIndex should be ~0.
  */
-static void
-softpipe_draw_range_elements_instanced(struct pipe_context *pipe,
-                                       struct pipe_resource *indexBuffer,
-                                       unsigned indexSize,
-                                       int indexBias,
-                                       unsigned minIndex,
-                                       unsigned maxIndex,
-                                       unsigned mode,
-                                       unsigned start,
-                                       unsigned count,
-                                       unsigned startInstance,
-                                       unsigned instanceCount)
+void
+softpipe_draw_vbo(struct pipe_context *pipe,
+                  const struct pipe_draw_info *info)
 {
    struct softpipe_context *sp = softpipe_context(pipe);
    struct draw_context *draw = sp->draw;
+   void *mapped_indices = NULL;
    unsigned i;
 
    if (!softpipe_check_render_cond(sp))
       return;
 
-   sp->reduced_api_prim = u_reduced_prim(mode);
+   sp->reduced_api_prim = u_reduced_prim(info->mode);
 
    if (sp->dirty) {
       softpipe_update_derived(sp);
@@ -146,31 +139,27 @@ softpipe_draw_range_elements_instanced(struct pipe_context *pipe,
    }
 
    /* Map index buffer, if present */
-   if (indexBuffer) {
-      void *mapped_indexes = softpipe_resource(indexBuffer)->data;
-      draw_set_mapped_element_buffer_range(draw,
-                                           indexSize,
-                                           indexBias,
-                                           minIndex,
-                                           maxIndex,
-                                           mapped_indexes);
-   } else {
-      /* no index/element buffer */
-      draw_set_mapped_element_buffer_range(draw,
-                                           0, 0,
-                                           start,
-                                           start + count - 1,
-                                           NULL);
+   if (info->indexed && sp->index_buffer.buffer) {
+      mapped_indices = softpipe_resource(sp->index_buffer.buffer)->data;
+      mapped_indices += sp->index_buffer.offset;
    }
 
+   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
+                                        sp->index_buffer.index_size : 0,
+                                        info->index_bias,
+                                        info->min_index,
+                                        info->max_index,
+                                        mapped_indices);
+
    /* draw! */
-   draw_arrays_instanced(draw, mode, start, count, startInstance, instanceCount);
+   draw_arrays_instanced(draw, info->mode, info->start, info->count,
+         info->start_instance, info->instance_count);
 
    /* unmap vertex/index buffers - will cause draw module to flush */
    for (i = 0; i < sp->num_vertex_buffers; i++) {
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
-   if (indexBuffer) {
+   if (mapped_indices) {
       draw_set_mapped_element_buffer(draw, 0, 0, NULL);
    }
 
@@ -185,6 +174,49 @@ softpipe_draw_range_elements_instanced(struct pipe_context *pipe,
    sp->dirty_render_cache = TRUE;
 }
 
+static void
+softpipe_draw_range_elements_instanced(struct pipe_context *pipe,
+                                       struct pipe_resource *indexBuffer,
+                                       unsigned indexSize,
+                                       int indexBias,
+                                       unsigned minIndex,
+                                       unsigned maxIndex,
+                                       unsigned mode,
+                                       unsigned start,
+                                       unsigned count,
+                                       unsigned startInstance,
+                                       unsigned instanceCount)
+{
+   struct softpipe_context *sp = softpipe_context(pipe);
+   struct pipe_draw_info info;
+   struct pipe_index_buffer saved_ib, ib;
+
+   util_draw_init_info(&info);
+   info.mode = mode;
+   info.start = start;
+   info.count = count;
+   info.start_instance = startInstance;
+   info.instance_count = instanceCount;
+   info.index_bias = indexBias;
+   info.min_index = minIndex;
+   info.max_index = maxIndex;
+
+   if (indexBuffer) {
+      info.indexed = TRUE;
+
+      saved_ib = sp->index_buffer;
+      ib.buffer = indexBuffer;
+      ib.offset = 0;
+      ib.index_size = indexSize;
+      pipe->set_index_buffer(pipe, &ib);
+   }
+
+   softpipe_draw_vbo(pipe, &info);
+
+   if (indexBuffer)
+      pipe->set_index_buffer(pipe, &saved_ib);
+}
+
 
 void
 softpipe_draw_range_elements(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/softpipe/sp_state.h b/src/gallium/drivers/softpipe/sp_state.h
index 7d6b86dce0..f04b0a5d31 100644
--- a/src/gallium/drivers/softpipe/sp_state.h
+++ b/src/gallium/drivers/softpipe/sp_state.h
@@ -221,6 +221,9 @@ void softpipe_set_vertex_buffers(struct pipe_context *,
                                  unsigned count,
                                  const struct pipe_vertex_buffer *);
 
+void softpipe_set_index_buffer(struct pipe_context *,
+                               const struct pipe_index_buffer *);
+
 
 void softpipe_update_derived( struct softpipe_context *softpipe );
 
@@ -260,6 +263,10 @@ softpipe_draw_elements_instanced(struct pipe_context *pipe,
                                  unsigned startInstance,
                                  unsigned instanceCount);
 
+void
+softpipe_draw_vbo(struct pipe_context *pipe,
+                  const struct pipe_draw_info *info);
+
 void softpipe_draw_stream_output(struct pipe_context *pipe, unsigned mode);
 
 void
diff --git a/src/gallium/drivers/softpipe/sp_state_vertex.c b/src/gallium/drivers/softpipe/sp_state_vertex.c
index 462f4d2655..880a7c7cd2 100644
--- a/src/gallium/drivers/softpipe/sp_state_vertex.c
+++ b/src/gallium/drivers/softpipe/sp_state_vertex.c
@@ -88,3 +88,17 @@ softpipe_set_vertex_buffers(struct pipe_context *pipe,
 
    draw_set_vertex_buffers(softpipe->draw, count, buffers);
 }
+
+void
+softpipe_set_index_buffer(struct pipe_context *pipe,
+                          const struct pipe_index_buffer *ib)
+{
+   struct softpipe_context *softpipe = softpipe_context(pipe);
+
+   if (ib)
+      memcpy(&softpipe->index_buffer, ib, sizeof(softpipe->index_buffer));
+   else
+      memset(&softpipe->index_buffer, 0, sizeof(softpipe->index_buffer));
+
+   /* TODO make this more like a state */
+}
diff --git a/src/gallium/drivers/svga/svga_context.h b/src/gallium/drivers/svga/svga_context.h
index 9a46de643f..67a7614c8a 100644
--- a/src/gallium/drivers/svga/svga_context.h
+++ b/src/gallium/drivers/svga/svga_context.h
@@ -190,6 +190,7 @@ struct svga_state
    struct svga_vertex_shader *vs;
 
    struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
+   struct pipe_index_buffer ib;
    struct pipe_resource *cb[PIPE_SHADER_TYPES];
 
    struct pipe_framebuffer_state framebuffer;
diff --git a/src/gallium/drivers/svga/svga_pipe_draw.c b/src/gallium/drivers/svga/svga_pipe_draw.c
index 58e930d983..fceaa83d70 100644
--- a/src/gallium/drivers/svga/svga_pipe_draw.c
+++ b/src/gallium/drivers/svga/svga_pipe_draw.c
@@ -248,10 +248,34 @@ svga_draw_arrays( struct pipe_context *pipe,
                             start, count);
 }
 
+static void
+svga_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
+{
+   struct svga_context *svga = svga_context(pipe);
+
+   if (info->indexed && svga->curr.ib.buffer) {
+      unsigned offset;
+
+      assert(svga->curr.ib.offset % svga->curr.ib.index_size == 0);
+      offset = svga->curr.ib.offset / svga->curr.ib.index_size;
+
+      svga_draw_range_elements(pipe, svga->curr.ib.buffer,
+                               svga->curr.ib.index_size, info->index_bias,
+                               info->min_index, info->max_index,
+                               info->mode, info->start + offset, info->count);
+   }
+   else {
+      svga_draw_range_elements(pipe, NULL, 0, 0,
+                               info->min_index, info->max_index,
+                               info->mode, info->start, info->count);
+   }
+}
+
 
 void svga_init_draw_functions( struct svga_context *svga )
 {
    svga->pipe.draw_arrays = svga_draw_arrays;
    svga->pipe.draw_elements = svga_draw_elements;
    svga->pipe.draw_range_elements = svga_draw_range_elements;
+   svga->pipe.draw_vbo = svga_draw_vbo;
 }
diff --git a/src/gallium/drivers/svga/svga_pipe_vertex.c b/src/gallium/drivers/svga/svga_pipe_vertex.c
index 23808ad08e..86c79459f3 100644
--- a/src/gallium/drivers/svga/svga_pipe_vertex.c
+++ b/src/gallium/drivers/svga/svga_pipe_vertex.c
@@ -66,6 +66,24 @@ static void svga_set_vertex_buffers(struct pipe_context *pipe,
 }
 
 
+static void svga_set_index_buffer(struct pipe_context *pipe,
+                                  const struct pipe_index_buffer *ib)
+{
+   struct svga_context *svga = svga_context(pipe);
+
+   if (ib) {
+      pipe_resource_reference(&svga->curr.ib.buffer, ib->buffer);
+      memcpy(&svga->curr.ib, ib, sizeof(svga->curr.ib));
+   }
+   else {
+      pipe_resource_reference(&svga->curr.ib.buffer, NULL);
+      memset(&svga->curr.ib, 0, sizeof(svga->curr.ib));
+   }
+
+   /* TODO make this more like a state */
+}
+
+
 static void *
 svga_create_vertex_elements_state(struct pipe_context *pipe,
                                   unsigned count,
@@ -109,6 +127,7 @@ void svga_cleanup_vertex_state( struct svga_context *svga )
 void svga_init_vertex_functions( struct svga_context *svga )
 {
    svga->pipe.set_vertex_buffers = svga_set_vertex_buffers;
+   svga->pipe.set_index_buffer = svga_set_index_buffer;
    svga->pipe.create_vertex_elements_state = svga_create_vertex_elements_state;
    svga->pipe.bind_vertex_elements_state = svga_bind_vertex_elements_state;
    svga->pipe.delete_vertex_elements_state = svga_delete_vertex_elements_state;
diff --git a/src/gallium/drivers/trace/tr_context.c b/src/gallium/drivers/trace/tr_context.c
index 55dd6cf883..91c9bf0999 100644
--- a/src/gallium/drivers/trace/tr_context.c
+++ b/src/gallium/drivers/trace/tr_context.c
@@ -167,6 +167,32 @@ trace_context_draw_range_elements(struct pipe_context *_pipe,
 }
 
 
+static INLINE void
+trace_context_draw_vbo(struct pipe_context *_pipe,
+                       const struct pipe_draw_info *info)
+{
+   struct trace_context *tr_ctx = trace_context(_pipe);
+   struct pipe_context *pipe = tr_ctx->pipe;
+
+   trace_dump_call_begin("pipe_context", "draw_vbo");
+
+   trace_dump_arg(ptr,  pipe);
+   trace_dump_arg(bool, info->indexed);
+   trace_dump_arg(uint, info->mode);
+   trace_dump_arg(uint, info->start);
+   trace_dump_arg(uint, info->count);
+   trace_dump_arg(uint, info->start_instance);
+   trace_dump_arg(uint, info->instance_count);
+   trace_dump_arg(int,  info->index_bias);
+   trace_dump_arg(uint, info->min_index);
+   trace_dump_arg(uint, info->max_index);
+
+   pipe->draw_vbo(pipe, info);
+
+   trace_dump_call_end();
+}
+
+
 static INLINE struct pipe_query *
 trace_context_create_query(struct pipe_context *_pipe,
                            unsigned query_type)
@@ -1044,6 +1070,30 @@ trace_context_set_vertex_buffers(struct pipe_context *_pipe,
 }
 
 
+static INLINE void
+trace_context_set_index_buffer(struct pipe_context *_pipe,
+                               const struct pipe_index_buffer *_ib)
+{
+   struct trace_context *tr_ctx = trace_context(_pipe);
+   struct pipe_context *pipe = tr_ctx->pipe;
+   struct pipe_index_buffer unwrapped_ib, *ib = NULL;
+
+   if (_ib) {
+      unwrapped_ib = *_ib;
+      unwrapped_ib.buffer = trace_resource_unwrap(tr_ctx, _ib->buffer);
+      ib = &unwrapped_ib;
+   }
+
+   trace_dump_call_begin("pipe_context", "set_index_buffer");
+
+   trace_dump_arg(ptr, pipe);
+   trace_dump_arg(index_buffer, ib);
+
+   pipe->set_index_buffer(pipe, ib);
+
+   trace_dump_call_end();
+}
+
 static INLINE void
 trace_context_resource_copy_region(struct pipe_context *_pipe,
                                    struct pipe_resource *dst,
@@ -1436,6 +1486,7 @@ trace_context_create(struct trace_screen *tr_scr,
    tr_ctx->base.draw_arrays = trace_context_draw_arrays;
    tr_ctx->base.draw_elements = trace_context_draw_elements;
    tr_ctx->base.draw_range_elements = trace_context_draw_range_elements;
+   tr_ctx->base.draw_vbo = trace_context_draw_vbo;
    tr_ctx->base.create_query = trace_context_create_query;
    tr_ctx->base.destroy_query = trace_context_destroy_query;
    tr_ctx->base.begin_query = trace_context_begin_query;
@@ -1477,6 +1528,7 @@ trace_context_create(struct trace_screen *tr_scr,
    tr_ctx->base.create_sampler_view = trace_create_sampler_view;
    tr_ctx->base.sampler_view_destroy = trace_sampler_view_destroy;
    tr_ctx->base.set_vertex_buffers = trace_context_set_vertex_buffers;
+   tr_ctx->base.set_index_buffer = trace_context_set_index_buffer;
    tr_ctx->base.resource_copy_region = trace_context_resource_copy_region;
    tr_ctx->base.clear = trace_context_clear;
    tr_ctx->base.clear_render_target = trace_context_clear_render_target;
diff --git a/src/gallium/drivers/trace/tr_dump_state.c b/src/gallium/drivers/trace/tr_dump_state.c
index 1727c2a020..bd9a9bfaf1 100644
--- a/src/gallium/drivers/trace/tr_dump_state.c
+++ b/src/gallium/drivers/trace/tr_dump_state.c
@@ -533,6 +533,26 @@ void trace_dump_vertex_buffer(const struct pipe_vertex_buffer *state)
 }
 
 
+void trace_dump_index_buffer(const struct pipe_index_buffer *state)
+{
+   if (!trace_dumping_enabled_locked())
+      return;
+
+   if(!state) {
+      trace_dump_null();
+      return;
+   }
+
+   trace_dump_struct_begin("pipe_index_buffer");
+
+   trace_dump_member(uint, state, index_size);
+   trace_dump_member(uint, state, offset);
+   trace_dump_member(resource_ptr, state, buffer);
+
+   trace_dump_struct_end();
+}
+
+
 void trace_dump_vertex_element(const struct pipe_vertex_element *state)
 {
    if (!trace_dumping_enabled_locked())
diff --git a/src/gallium/drivers/trace/tr_dump_state.h b/src/gallium/drivers/trace/tr_dump_state.h
index e614e8355e..2e70f4e1c7 100644
--- a/src/gallium/drivers/trace/tr_dump_state.h
+++ b/src/gallium/drivers/trace/tr_dump_state.h
@@ -75,6 +75,8 @@ void trace_dump_transfer(const struct pipe_transfer *state);
 
 void trace_dump_vertex_buffer(const struct pipe_vertex_buffer *state);
 
+void trace_dump_index_buffer(const struct pipe_index_buffer *state);
+
 void trace_dump_vertex_element(const struct pipe_vertex_element *state);
 
 
-- 
cgit v1.2.3


From 7a73390f9126fd270d9891cd9d2bf38ef56d9b80 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Thu, 29 Jul 2010 14:51:06 -0400
Subject: r600g: mipmap early support + EX2/ABS instruction + culling

Add mipmap support (demos/src/redbook/mipmap is working)
Add EX2/ABS shader instruction support.
Add face culling support.

Misc fixes.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_asm.c      |  2 ++
 src/gallium/drivers/r600/r600_resource.h |  4 +--
 src/gallium/drivers/r600/r600_shader.c   | 16 +++++----
 src/gallium/drivers/r600/r600_state.c    | 56 ++++++++++++++++++++++++--------
 src/gallium/drivers/r600/r600_texture.c  | 24 +++++++-------
 src/gallium/drivers/r600/r600d.h         | 40 +++++++++++++++++++++++
 6 files changed, 108 insertions(+), 34 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index e678a2fdf2..e560f65dcd 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -294,6 +294,7 @@ int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 					S_SQ_ALU_WORD0_LAST(alu->last);
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
 					S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
 					S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
 					S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
@@ -309,6 +310,7 @@ int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
 					S_SQ_ALU_WORD0_LAST(alu->last);
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
 					S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
 					S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
 					S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 0139a3b777..bb90e76fb7 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -44,9 +44,9 @@ struct r600_resource_texture {
 	struct r600_resource		resource;
 	unsigned long			offset[PIPE_MAX_TEXTURE_LEVELS];
 	unsigned long			pitch[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			stride[PIPE_MAX_TEXTURE_LEVELS];
 	unsigned long			layer_size[PIPE_MAX_TEXTURE_LEVELS];
-	unsigned long			stride_override;
+	unsigned long			pitch_override;
+	unsigned long			bpt;
 	unsigned long			size;
 };
 
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 3f1979b9cc..c61cc11e88 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -249,10 +249,6 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 		R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs);
 		return -EINVAL;
 	}
-	if (i->Instruction.Saturate) {
-		R600_ERR("staturate unsupported\n");
-		return -EINVAL;
-	}
 	if (i->Instruction.Predicate) {
 		R600_ERR("predicate unsupported\n");
 		return -EINVAL;
@@ -507,10 +503,15 @@ static int tgsi_dst(struct r600_shader_ctx *ctx,
 			unsigned swizzle,
 			struct r600_bc_alu_dst *r600_dst)
 {
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+
 	r600_dst->sel = tgsi_dst->Register.Index;
 	r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
 	r600_dst->chan = swizzle;
 	r600_dst->write = 1;
+	if (inst->Instruction.Saturate) {
+		r600_dst->clamp = 1;
+	}
 	return 0;
 }
 
@@ -540,6 +541,9 @@ static int tgsi_op2(struct r600_shader_ctx *ctx)
 		case TGSI_OPCODE_SUB:
 			alu.src[1].neg = 1;
 			break;
+		case TGSI_OPCODE_ABS:
+			alu.src[0].abs = 1;
+			break;
 		default:
 			break;
 		}
@@ -1040,13 +1044,13 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_CLAMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_FLR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans},
 	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_XPD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	/* gap */
 	{32,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_RCC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DPH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 57879e8d8b..0191070daa 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -24,6 +24,7 @@
  *      Jerome Glisse
  */
 #include <stdio.h>
+#include <errno.h>
 #include "util/u_inlines.h"
 #include "util/u_format.h"
 #include "util/u_memory.h"
@@ -649,8 +650,8 @@ static struct radeon_state *r600_cb0(struct r600_context *rctx)
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 3;
-	pitch = rtex->pitch[level] / 8 - 1;
-	slice = rtex->pitch[level] * state->cbufs[0]->height / 64 - 1;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
 	rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
 	rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
@@ -666,6 +667,22 @@ static struct radeon_state *r600_cb0(struct r600_context *rctx)
 	return rstate;
 }
 
+int r600_db_format(unsigned pformat, unsigned *format)
+{
+	switch (pformat) {
+	case PIPE_FORMAT_Z24X8_UNORM:
+		*format = V_028010_DEPTH_X8_24;
+		return 0;
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		*format = V_028010_DEPTH_8_24;
+		return 0;
+	default:
+		*format = V_028010_DEPTH_INVALID;
+		R600_ERR("unsupported %d\n", pformat);
+		return -EINVAL;
+	}
+}
+
 static struct radeon_state *r600_db(struct r600_context *rctx)
 {
 	struct r600_screen *rscreen = rctx->screen;
@@ -674,7 +691,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	struct radeon_state *rstate;
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 	unsigned level = state->cbufs[0]->level;
-	unsigned pitch, slice;
+	unsigned pitch, slice, format;
 
 	if (state->zsbuf == NULL)
 		return NULL;
@@ -689,10 +706,15 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
 	level = state->zsbuf->level;
-	pitch = rtex->pitch[level] / 8 - 1;
-	slice = rtex->pitch[level] * state->zsbuf->height / 64 - 1;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+	if (r600_db_format(state->zsbuf->texture->format, &format)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
 	rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010006;
+	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
+					S_028010_FORMAT(format);
 	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
 	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
 	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
@@ -716,7 +738,10 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000;
+	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
+			S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+			S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+			S_028814_FACE(!state->front_ccw);
 	rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
@@ -910,6 +935,11 @@ static inline unsigned r600_tex_compare(unsigned compare)
 	}
 }
 
+static INLINE u32 S_FIXED(float value, u32 frac_bits)
+{
+	return value * (1 << frac_bits);
+}
+
 static struct radeon_state *r600_sampler(struct r600_context *rctx,
 				const struct pipe_sampler_state *state,
 				unsigned id)
@@ -930,9 +960,9 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
 			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func));
 	/* FIXME LOD it depends on texture base level ... */
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0] =
-			S_03C004_MIN_LOD(0) |
-			S_03C004_MAX_LOD(0) |
-			S_03C004_LOD_BIAS(0);
+			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
+			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
+			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -1020,7 +1050,7 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	/* FIXME properly handle first level != 0 */
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
-			S_038000_PITCH((tmp->pitch[0] / 8) - 1) |
+			S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
 			S_038000_TEX_WIDTH(view->texture->width0 - 1);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
 			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
@@ -1036,9 +1066,9 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 			S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
 			S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
 			S_038010_REQUEST_SIZE(1) |
-			S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_r)) |
+			S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) |
 			S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
-			S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_b)) |
+			S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
 			S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
 			S_038010_BASE_LEVEL(view->first_level);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index ab20e97948..96173b0ed6 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -59,24 +59,22 @@ static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
 static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource_texture *rtex)
 {
 	struct pipe_resource *ptex = &rtex->resource.base.b;
-	unsigned long w, h, stride, size, layer_size, i, offset;
+	unsigned long w, h, pitch, size, layer_size, i, offset;
 
+	rtex->bpt = util_format_get_blocksize(ptex->format);
 	for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 		w = u_minify(ptex->width0, i);
 		h = u_minify(ptex->height0, i);
-		stride = align(util_format_get_stride(ptex->format, w), 32);
-		layer_size = stride * h;
+		pitch = util_format_get_stride(ptex->format, align(w, 64));
+		layer_size = pitch * h;
 		if (ptex->target == PIPE_TEXTURE_CUBE)
 			size = layer_size * 6;
 		else
 			size = layer_size * u_minify(ptex->depth0, i);
 		rtex->offset[i] = offset;
 		rtex->layer_size[i] = layer_size;
-		rtex->pitch[i] = stride / util_format_get_blocksize(ptex->format);
-		rtex->pitch[i] += R600_TEXEL_PITCH_ALIGNMENT_MASK;
-		rtex->pitch[i] &= ~R600_TEXEL_PITCH_ALIGNMENT_MASK;
-		rtex->stride[i] = stride;
-		offset += align(size, 32);
+		rtex->pitch[i] = pitch;
+		offset += size;
 	}
 	rtex->size = offset;
 }
@@ -183,11 +181,11 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	pipe_reference_init(&resource->base.b.reference, 1);
 	resource->base.b.screen = screen;
 	resource->bo = bo;
-	rtex->stride_override = whandle->stride;
-	rtex->pitch[0] = whandle->stride / util_format_get_blocksize(templ->format);
-	rtex->stride[0] = whandle->stride;
+	rtex->pitch_override = whandle->stride;
+	rtex->bpt = util_format_get_blocksize(templ->format);
+	rtex->pitch[0] = whandle->stride;
 	rtex->offset[0] = 0;
-	rtex->size = align(rtex->stride[0] * templ->height0, 32);
+	rtex->size = align(rtex->pitch[0] * templ->height0, 64);
 
 	return &resource->base.b;
 }
@@ -216,7 +214,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	trans->transfer.sr = sr;
 	trans->transfer.usage = usage;
 	trans->transfer.box = *box;
-	trans->transfer.stride = rtex->stride[sr.level];
+	trans->transfer.stride = rtex->pitch[sr.level];
 	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
 	return &trans->transfer;
 }
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 593b95c9c7..c1acfcd29e 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -316,6 +316,46 @@
 #define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
 #define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
 #define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define   S_028814_CULL_FRONT(x)                       (((x) & 0x1) << 0)
+#define   G_028814_CULL_FRONT(x)                       (((x) >> 0) & 0x1)
+#define   C_028814_CULL_FRONT                          0xFFFFFFFE
+#define   S_028814_CULL_BACK(x)                        (((x) & 0x1) << 1)
+#define   G_028814_CULL_BACK(x)                        (((x) >> 1) & 0x1)
+#define   C_028814_CULL_BACK                           0xFFFFFFFD
+#define   S_028814_FACE(x)                             (((x) & 0x1) << 2)
+#define   G_028814_FACE(x)                             (((x) >> 2) & 0x1)
+#define   C_028814_FACE                                0xFFFFFFFB
+#define   S_028814_POLY_MODE(x)                        (((x) & 0x3) << 3)
+#define   G_028814_POLY_MODE(x)                        (((x) >> 3) & 0x3)
+#define   C_028814_POLY_MODE                           0xFFFFFFE7
+#define   S_028814_POLYMODE_FRONT_PTYPE(x)             (((x) & 0x7) << 5)
+#define   G_028814_POLYMODE_FRONT_PTYPE(x)             (((x) >> 5) & 0x7)
+#define   C_028814_POLYMODE_FRONT_PTYPE                0xFFFFFF1F
+#define   S_028814_POLYMODE_BACK_PTYPE(x)              (((x) & 0x7) << 8)
+#define   G_028814_POLYMODE_BACK_PTYPE(x)              (((x) >> 8) & 0x7)
+#define   C_028814_POLYMODE_BACK_PTYPE                 0xFFFFF8FF
+#define   S_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) & 0x1) << 11)
+#define   G_028814_POLY_OFFSET_FRONT_ENABLE(x)         (((x) >> 11) & 0x1)
+#define   C_028814_POLY_OFFSET_FRONT_ENABLE            0xFFFFF7FF
+#define   S_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) & 0x1) << 12)
+#define   G_028814_POLY_OFFSET_BACK_ENABLE(x)          (((x) >> 12) & 0x1)
+#define   C_028814_POLY_OFFSET_BACK_ENABLE             0xFFFFEFFF
+#define   S_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) & 0x1) << 13)
+#define   G_028814_POLY_OFFSET_PARA_ENABLE(x)          (((x) >> 13) & 0x1)
+#define   C_028814_POLY_OFFSET_PARA_ENABLE             0xFFFFDFFF
+#define   S_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) & 0x1) << 16)
+#define   G_028814_VTX_WINDOW_OFFSET_ENABLE(x)         (((x) >> 16) & 0x1)
+#define   C_028814_VTX_WINDOW_OFFSET_ENABLE            0xFFFEFFFF
+#define   S_028814_PROVOKING_VTX_LAST(x)               (((x) & 0x1) << 19)
+#define   G_028814_PROVOKING_VTX_LAST(x)               (((x) >> 19) & 0x1)
+#define   C_028814_PROVOKING_VTX_LAST                  0xFFF7FFFF
+#define   S_028814_PERSP_CORR_DIS(x)                   (((x) & 0x1) << 20)
+#define   G_028814_PERSP_CORR_DIS(x)                   (((x) >> 20) & 0x1)
+#define   C_028814_PERSP_CORR_DIS                      0xFFEFFFFF
+#define   S_028814_MULTI_PRIM_IB_ENA(x)                (((x) & 0x1) << 21)
+#define   G_028814_MULTI_PRIM_IB_ENA(x)                (((x) >> 21) & 0x1)
+#define   C_028814_MULTI_PRIM_IB_ENA                   0xFFDFFFFF
 #define R_028000_DB_DEPTH_SIZE                       0x028000
 #define   S_028000_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
 #define   G_028000_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
-- 
cgit v1.2.3


From 919750a55771cfd731e2f90d1385cbb4265e4cf4 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 2 Aug 2010 14:31:49 +1000
Subject: r600g: make r600_db_format static.

this isn't used anywhere else yet.
---
 src/gallium/drivers/r600/r600_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 0191070daa..b27d9d5557 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -667,7 +667,7 @@ static struct radeon_state *r600_cb0(struct r600_context *rctx)
 	return rstate;
 }
 
-int r600_db_format(unsigned pformat, unsigned *format)
+static int r600_db_format(unsigned pformat, unsigned *format)
 {
 	switch (pformat) {
 	case PIPE_FORMAT_Z24X8_UNORM:
-- 
cgit v1.2.3


From 7bcd39ce50b7b710bb8561c430f345ebe91ab9a3 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 2 Aug 2010 14:42:29 +1000
Subject: r600g: add initial blend state.

migrates cb_cntl to be regenerated
---
 src/gallium/drivers/r600/r600_context.c       |  14 ----
 src/gallium/drivers/r600/r600_context.h       |   1 +
 src/gallium/drivers/r600/r600_reg.h           |  72 +++++++++++++++++++
 src/gallium/drivers/r600/r600_state.c         |  95 ++++++++++++++++++++++--
 src/gallium/drivers/r600/r600_state_inlines.h | 100 ++++++++++++++++++++++++++
 5 files changed, 262 insertions(+), 20 deletions(-)
 create mode 100644 src/gallium/drivers/r600/r600_reg.h
 create mode 100644 src/gallium/drivers/r600/r600_state_inlines.h

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index fc8aa1b866..8b191914f5 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -331,20 +331,6 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 		return NULL;
 	}
 
-	rctx->hw_states.cb_cntl = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0000;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
-	rctx->hw_states.cb_cntl->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	radeon_state_pm4(rctx->hw_states.cb_cntl);
-
 	r600_init_config(rctx);
 
 	rctx->ctx = radeon_ctx(rscreen->rw);
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 97c8a46bb0..a1ee9577ba 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -158,6 +158,7 @@ struct r600_context {
 	struct r600_vertex_element	*vertex_elements;
 	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
 	struct pipe_index_buffer	index_buffer;
+	struct pipe_blend_color         blend_color;
 };
 
 #if 0
diff --git a/src/gallium/drivers/r600/r600_reg.h b/src/gallium/drivers/r600/r600_reg.h
new file mode 100644
index 0000000000..2600875d5c
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_reg.h
@@ -0,0 +1,72 @@
+#ifndef R600_REG_H
+#define R600_REG_H
+
+/* for regs which haven't been generated yet */
+
+#define R600_BLEND_ZERO 0
+#define R600_BLEND_ONE 1
+#define R600_BLEND_SRC_COLOR 2
+#define R600_BLEND_ONE_MINUS_SRC_COLOR 3
+#define R600_BLEND_SRC_ALPHA 4
+#define R600_BLEND_ONE_MINUS_SRC_ALPHA 5
+#define R600_BLEND_DST_ALPHA 6
+#define R600_BLEND_ONE_MINUS_DST_ALPHA 7
+#define R600_BLEND_DST_COLOR 8
+#define R600_BLEND_ONE_MINUS_DST_COLOR 9
+#define R600_BLEND_SRC_ALPHA_SATURATE 10
+#define R600_BLEND_BOTH_SRC_ALPHA 11
+#define R600_BLEND_BOTH_INV_SRC_ALPHA 12
+#define R600_BLEND_CONST_COLOR 13
+#define R600_BLEND_ONE_MINUS_CONST_COLOR 14
+#define R600_BLEND_SRC1_COLOR 15
+#define R600_BLEND_INV_SRC1_COLOR 16
+#define R600_BLEND_SRC1_ALPHA 17
+#define R600_BLEND_INV_SRC1_ALPHA 18
+#define R600_BLEND_CONST_ALPHA 19
+#define R600_BLEND_ONE_MINUS_CONST_ALPHA 20
+
+#define R600_BLEND_FCN_ADD 0
+#define R600_BLEND_FCN_SUBTRACT 1
+#define R600_BLEND_FCN_MIN 2
+#define R600_BLEND_FCN_MAX 3
+#define R600_BLEND_FCN_RSUB 4
+
+#define CB_BLEND_COLOR_SRCBLEND_SHIFT 0
+#define CB_BLEND_COLOR_COMB_FCN_SHIFT 5
+#define CB_BLEND_COLOR_DESTBLEND_SHIFT 8
+#define CB_BLEND_ALPHA_SRCBLEND_SHIFT 16
+#define CB_BLEND_ALPHA_COMB_FCN_SHIFT 21
+#define CB_BLEND_ALPHA_DESTBLEND_SHIFT 24
+#define CB_BLEND_SEPARATE_ALPHA_BLEND (1 << 29)
+
+#define SX_ALPHA_TEST_FUNC_SHIFT (0)
+#define SX_ALPHA_TEST_ENABLE (1 << 3)
+
+#define R600_ZS_KEEP			0
+#define R600_ZS_ZERO			1
+#define R600_ZS_REPLACE			2
+#define R600_ZS_INCR			3
+#define R600_ZS_DECR			4
+#define R600_ZS_INVERT			5
+#define R600_ZS_INCR_WRAP		6
+#define R600_ZS_DECR_WRAP		7
+
+#define R600_STENCILREF_SHIFT 0
+#define R600_STENCILMASK_SHIFT 8
+#define R600_STENCILWRITEMASK_SHIFT 16
+
+#define PA_SU_PS_WIDTH_SHIFT 16
+
+#define PA_SU_CULL_FRONT (1 << 0)
+#define PA_SU_CULL_BACK (1 << 1)
+#define PA_SU_FACE_CCW (0 << 2)
+#define PA_SU_FACE_CW (1 << 2)
+
+#define PA_SU_POLYMODE_FRONT_SHIFT 5
+#define PA_SU_POLYMODE_BACK_SHIFT 5
+#define POLYGON_MODE_POINT 0
+#define POLYGON_MODE_LINE 1
+#define POLYGON_MODE_TRI 2
+
+
+#endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b27d9d5557..56304cc69f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -32,6 +32,8 @@
 #include "r600_context.h"
 #include "r600_resource.h"
 #include "r600d.h"
+#include "r600_reg.h"
+#include "r600_state_inlines.h"
 
 static void *r600_create_blend_state(struct pipe_context *ctx,
 					const struct pipe_blend_state *state)
@@ -259,6 +261,9 @@ static void r600_delete_state(struct pipe_context *ctx, void *state)
 static void r600_set_blend_color(struct pipe_context *ctx,
 					const struct pipe_blend_color *color)
 {
+	struct r600_context *rctx = r600_context(ctx);
+
+	rctx->blend_color = *color;
 }
 
 static void r600_set_clip_state(struct pipe_context *ctx,
@@ -604,15 +609,17 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
+	const struct pipe_blend_state *state = &rctx->blend->state.blend;
+	int i;
 
 	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
 	if (rstate == NULL)
 		return NULL;
-	rstate->states[R600_BLEND__CB_BLEND_RED] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND_GREEN] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND_BLUE] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND_ALPHA] = 0x00000000;
-	rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00010001;
+	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
+	rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
+	rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
+	rstate->states[R600_BLEND__CB_BLEND_ALPHA] = fui(rctx->blend_color.color[3]);
+	rstate->states[R600_BLEND__CB_BLEND0_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND1_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND2_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND3_CONTROL] = 0x00000000;
@@ -621,6 +628,37 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	rstate->states[R600_BLEND__CB_BLEND6_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND7_CONTROL] = 0x00000000;
 	rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
+
+	for (i = 0; i < 8; i++) {
+
+		unsigned eqRGB = state->rt[i].rgb_func;
+		unsigned srcRGB = state->rt[i].rgb_src_factor;
+		unsigned dstRGB = state->rt[i].rgb_dst_factor;
+		
+		unsigned eqA = state->rt[i].alpha_func;
+		unsigned srcA = state->rt[i].alpha_src_factor;
+		unsigned dstA = state->rt[i].alpha_dst_factor;
+		uint32_t bc = 0;
+
+		if (!state->rt[i].blend_enable)
+			continue;
+
+		bc |= r600_translate_blend_function(eqRGB) << CB_BLEND_COLOR_COMB_FCN_SHIFT;
+		bc |= r600_translate_blend_factor(srcRGB) << CB_BLEND_COLOR_SRCBLEND_SHIFT;
+		bc |= r600_translate_blend_factor(dstRGB) << CB_BLEND_COLOR_DESTBLEND_SHIFT;
+
+		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
+			bc |= CB_BLEND_SEPARATE_ALPHA_BLEND;
+			bc |= r600_translate_blend_function(eqA) << CB_BLEND_ALPHA_COMB_FCN_SHIFT;
+			bc |= r600_translate_blend_factor(srcA) << CB_BLEND_ALPHA_SRCBLEND_SHIFT;
+			bc |= r600_translate_blend_factor(dstA) << CB_BLEND_ALPHA_DESTBLEND_SHIFT;
+		}
+
+		rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
+		if (i == 0)
+			rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
+	}
+
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
@@ -1084,6 +1122,49 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	return rstate;
 }
 
+static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
+	uint32_t color_control, target_mask;
+	int i;
+
+	target_mask = 0;
+	color_control = 0;
+
+	if (pbs->logicop_enable) {
+		color_control |= (pbs->logicop_func) << 16;
+	} else
+		color_control |= (0xcc << 16);
+
+	target_mask |= (pbs->rt[0].colormask);
+	for (i = 0; i < 8; i++) {
+		if (pbs->rt[i].blend_enable) {
+			color_control |= (1 << (8 + i));
+			target_mask |= (pbs->rt[0].colormask << (4 * i));
+		} else if (i == 0)
+			target_mask |= 0xf;
+	}
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
+	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
+	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX] = 0x00000000;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX] = 0x00000000;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_SRC] = 0x00000000;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
 int r600_context_hw_states(struct r600_context *rctx)
 {
 	unsigned i;
@@ -1093,7 +1174,7 @@ int r600_context_hw_states(struct r600_context *rctx)
 	 * doesn't
 	 */
 	//radeon_state_decref(rctx->hw_states.config);
-	//radeon_state_decref(rctx->hw_states.cb_cntl);
+	radeon_state_decref(rctx->hw_states.cb_cntl);
 	radeon_state_decref(rctx->hw_states.db);
 	radeon_state_decref(rctx->hw_states.rasterizer);
 	radeon_state_decref(rctx->hw_states.scissor);
@@ -1120,6 +1201,8 @@ int r600_context_hw_states(struct r600_context *rctx)
 	rctx->hw_states.viewport = r600_viewport(rctx);
 	rctx->hw_states.cb0 = r600_cb0(rctx);
 	rctx->hw_states.db = r600_db(rctx);
+	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
+
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
 			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
new file mode 100644
index 0000000000..42bab52b3f
--- /dev/null
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef R600_STATE_INLINES_H
+#define R600_STATE_INLINES_H
+
+#include "r600_reg.h"
+
+static INLINE uint32_t r600_translate_blend_function(int blend_func)
+{
+	switch (blend_func) {
+        case PIPE_BLEND_ADD:
+		return R600_BLEND_FCN_ADD;
+        case PIPE_BLEND_SUBTRACT:
+		return R600_BLEND_FCN_SUBTRACT;
+        case PIPE_BLEND_REVERSE_SUBTRACT:
+		return R600_BLEND_FCN_RSUB;
+        case PIPE_BLEND_MIN:
+		return R600_BLEND_FCN_MIN;
+        case PIPE_BLEND_MAX:
+		return R600_BLEND_FCN_MAX;
+        default:
+            fprintf(stderr, "r600: Unknown blend function %d\n", blend_func);
+            assert(0);
+            break;
+    }
+    return 0;
+}
+
+static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
+{
+	switch (blend_fact) {
+        case PIPE_BLENDFACTOR_ONE:
+		return R600_BLEND_ZERO;
+        case PIPE_BLENDFACTOR_SRC_COLOR:
+		return R600_BLEND_SRC_COLOR;
+        case PIPE_BLENDFACTOR_SRC_ALPHA:
+		return R600_BLEND_SRC_ALPHA;
+        case PIPE_BLENDFACTOR_DST_ALPHA:
+		return R600_BLEND_DST_ALPHA;
+        case PIPE_BLENDFACTOR_DST_COLOR:
+		return R600_BLEND_DST_COLOR;
+        case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+		return R600_BLEND_SRC_ALPHA_SATURATE;
+        case PIPE_BLENDFACTOR_CONST_COLOR:
+		return R600_BLEND_CONST_COLOR;
+        case PIPE_BLENDFACTOR_CONST_ALPHA:
+		return R600_BLEND_CONST_ALPHA;
+        case PIPE_BLENDFACTOR_ZERO:
+		return R600_BLEND_ZERO;
+        case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+		return R600_BLEND_ONE_MINUS_SRC_COLOR;
+        case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+		return R600_BLEND_ONE_MINUS_SRC_ALPHA;
+        case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+		return R600_BLEND_ONE_MINUS_DST_ALPHA;
+        case PIPE_BLENDFACTOR_INV_DST_COLOR:
+		return R600_BLEND_ONE_MINUS_DST_COLOR;
+        case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+		return R600_BLEND_ONE_MINUS_CONST_COLOR;
+        case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+		return R600_BLEND_ONE_MINUS_CONST_ALPHA;
+
+        case PIPE_BLENDFACTOR_SRC1_COLOR:
+		return R600_BLEND_SRC1_COLOR;
+        case PIPE_BLENDFACTOR_SRC1_ALPHA:
+		return R600_BLEND_SRC1_ALPHA;
+        case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+		return R600_BLEND_INV_SRC1_COLOR;
+        case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+		return R600_BLEND_INV_SRC1_ALPHA;
+	default:
+		fprintf(stderr, "r600: Implementation error: "
+			"Bad blend factor %d not supported!\n", blend_fact);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+#endif
-- 
cgit v1.2.3


From 3f4ec394b027c6d947ccc88309a7d37bc3859e9d Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 2 Aug 2010 14:46:17 +1000
Subject: r600g: initial alpha test state

---
 src/gallium/drivers/r600/r600_state.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 56304cc69f..9af39f7218 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -873,19 +873,27 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
-	unsigned db_depth_control;
-
+	unsigned db_depth_control, alpha_test_control, alpha_ref;
+	
 	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 	if (rstate == NULL)
 		return NULL;
+
 	db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
-	
+	alpha_test_control = 0;
+	alpha_ref = 0;
+	if (state->alpha.enabled) {
+		alpha_test_control = (state->alpha.func) << 0;
+		alpha_test_control |= SX_ALPHA_TEST_ENABLE;
+		alpha_ref = fui(state->alpha.ref_value);
+	}
+
 	rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
 	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
-	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = 0x00000000;
+	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
 	rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
 	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
-	rstate->states[R600_DSA__SX_ALPHA_REF] = 0x00000000;
+	rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
 	rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
 	rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
 	rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
-- 
cgit v1.2.3


From 4af5f11c3232015006f61c1a6befdff3411b8d6c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 2 Aug 2010 14:48:59 +1000
Subject: r600g: add stencil op/func translation

---
 src/gallium/drivers/r600/r600_state.c         | 36 ++++++++++++++++++++++++---
 src/gallium/drivers/r600/r600_state_inlines.h | 33 ++++++++++++++++++++++++
 2 files changed, 66 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 9af39f7218..bbfe4da840 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -874,12 +874,42 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 	unsigned db_depth_control, alpha_test_control, alpha_ref;
+	unsigned stencil_ref_mask, stencil_ref_mask_bf;
 	
 	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 	if (rstate == NULL)
 		return NULL;
 
-	db_depth_control = 0x00700700 | S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func);
+	stencil_ref_mask = 0;
+	stencil_ref_mask_bf = 0;
+	db_depth_control = 0x00700700 |
+		S_028800_Z_ENABLE(state->depth.enabled) |
+		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
+		S_028800_ZFUNC(state->depth.func);
+	/* set stencil enable */
+	db_depth_control |= S_028800_STENCIL_ENABLE(state->stencil[0].enabled);
+	
+	if (state->stencil[0].enabled) {
+
+		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
+		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
+		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
+		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
+		
+		db_depth_control |= S_028800_BACKFACE_ENABLE(state->stencil[1].enabled);
+
+		stencil_ref_mask = (state->stencil[0].valuemask << R600_STENCILMASK_SHIFT) |
+			(state->stencil[0].writemask << R600_STENCILWRITEMASK_SHIFT);
+		if (state->stencil[1].enabled) {
+			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
+			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
+			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
+			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
+			stencil_ref_mask_bf = (state->stencil[1].valuemask << R600_STENCILMASK_SHIFT) |
+				(state->stencil[1].writemask << R600_STENCILWRITEMASK_SHIFT);
+		}
+	}
+
 	alpha_test_control = 0;
 	alpha_ref = 0;
 	if (state->alpha.enabled) {
@@ -891,8 +921,8 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	rstate->states[R600_DSA__DB_STENCIL_CLEAR] = 0x00000000;
 	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
 	rstate->states[R600_DSA__SX_ALPHA_TEST_CONTROL] = alpha_test_control;
-	rstate->states[R600_DSA__DB_STENCILREFMASK] = 0xFFFFFF00;
-	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = 0xFFFFFF00;
+	rstate->states[R600_DSA__DB_STENCILREFMASK] = stencil_ref_mask;
+	rstate->states[R600_DSA__DB_STENCILREFMASK_BF] = stencil_ref_mask_bf;
 	rstate->states[R600_DSA__SX_ALPHA_REF] = alpha_ref;
 	rstate->states[R600_DSA__SPI_FOG_FUNC_SCALE] = 0x00000000;
 	rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 42bab52b3f..369263dc8f 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -97,4 +97,37 @@ static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
 	return 0;
 }
 
+static INLINE uint32_t r600_translate_stencil_op(int s_op)
+{
+	switch (s_op) {
+	case PIPE_STENCIL_OP_KEEP:
+		return R600_ZS_KEEP;
+        case PIPE_STENCIL_OP_ZERO:
+		return R600_ZS_ZERO;
+        case PIPE_STENCIL_OP_REPLACE:
+		return R600_ZS_REPLACE;
+        case PIPE_STENCIL_OP_INCR:
+		return R600_ZS_INCR;
+        case PIPE_STENCIL_OP_DECR:
+		return R600_ZS_DECR;
+        case PIPE_STENCIL_OP_INCR_WRAP:
+		return R600_ZS_INCR_WRAP;
+        case PIPE_STENCIL_OP_DECR_WRAP:
+		return R600_ZS_DECR_WRAP;
+        case PIPE_STENCIL_OP_INVERT:
+		return R600_ZS_INVERT;
+        default:
+		fprintf(stderr, "r600: Unknown stencil op %d", s_op);
+		assert(0);
+		break;
+	}
+	return 0;
+}
+
+/* translates straight */
+static INLINE uint32_t r600_translate_ds_func(int func)
+{
+	return func;
+}
+
 #endif
-- 
cgit v1.2.3


From 313df4156279f84ebc5b98a7540820b994762650 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Mon, 2 Aug 2010 14:21:33 -0400
Subject: r600g: add autogenerated reg definition + debug print cleanup

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_reg.h           |  72 ------------
 src/gallium/drivers/r600/r600_screen.c        |   6 +-
 src/gallium/drivers/r600/r600_shader.c        |   2 +-
 src/gallium/drivers/r600/r600_state.c         |  38 +++----
 src/gallium/drivers/r600/r600_state_inlines.h | 152 +++++++++++++-------------
 src/gallium/drivers/r600/r600d.h              |  97 ++++++++++++++++
 6 files changed, 194 insertions(+), 173 deletions(-)
 delete mode 100644 src/gallium/drivers/r600/r600_reg.h

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_reg.h b/src/gallium/drivers/r600/r600_reg.h
deleted file mode 100644
index 2600875d5c..0000000000
--- a/src/gallium/drivers/r600/r600_reg.h
+++ /dev/null
@@ -1,72 +0,0 @@
-#ifndef R600_REG_H
-#define R600_REG_H
-
-/* for regs which haven't been generated yet */
-
-#define R600_BLEND_ZERO 0
-#define R600_BLEND_ONE 1
-#define R600_BLEND_SRC_COLOR 2
-#define R600_BLEND_ONE_MINUS_SRC_COLOR 3
-#define R600_BLEND_SRC_ALPHA 4
-#define R600_BLEND_ONE_MINUS_SRC_ALPHA 5
-#define R600_BLEND_DST_ALPHA 6
-#define R600_BLEND_ONE_MINUS_DST_ALPHA 7
-#define R600_BLEND_DST_COLOR 8
-#define R600_BLEND_ONE_MINUS_DST_COLOR 9
-#define R600_BLEND_SRC_ALPHA_SATURATE 10
-#define R600_BLEND_BOTH_SRC_ALPHA 11
-#define R600_BLEND_BOTH_INV_SRC_ALPHA 12
-#define R600_BLEND_CONST_COLOR 13
-#define R600_BLEND_ONE_MINUS_CONST_COLOR 14
-#define R600_BLEND_SRC1_COLOR 15
-#define R600_BLEND_INV_SRC1_COLOR 16
-#define R600_BLEND_SRC1_ALPHA 17
-#define R600_BLEND_INV_SRC1_ALPHA 18
-#define R600_BLEND_CONST_ALPHA 19
-#define R600_BLEND_ONE_MINUS_CONST_ALPHA 20
-
-#define R600_BLEND_FCN_ADD 0
-#define R600_BLEND_FCN_SUBTRACT 1
-#define R600_BLEND_FCN_MIN 2
-#define R600_BLEND_FCN_MAX 3
-#define R600_BLEND_FCN_RSUB 4
-
-#define CB_BLEND_COLOR_SRCBLEND_SHIFT 0
-#define CB_BLEND_COLOR_COMB_FCN_SHIFT 5
-#define CB_BLEND_COLOR_DESTBLEND_SHIFT 8
-#define CB_BLEND_ALPHA_SRCBLEND_SHIFT 16
-#define CB_BLEND_ALPHA_COMB_FCN_SHIFT 21
-#define CB_BLEND_ALPHA_DESTBLEND_SHIFT 24
-#define CB_BLEND_SEPARATE_ALPHA_BLEND (1 << 29)
-
-#define SX_ALPHA_TEST_FUNC_SHIFT (0)
-#define SX_ALPHA_TEST_ENABLE (1 << 3)
-
-#define R600_ZS_KEEP			0
-#define R600_ZS_ZERO			1
-#define R600_ZS_REPLACE			2
-#define R600_ZS_INCR			3
-#define R600_ZS_DECR			4
-#define R600_ZS_INVERT			5
-#define R600_ZS_INCR_WRAP		6
-#define R600_ZS_DECR_WRAP		7
-
-#define R600_STENCILREF_SHIFT 0
-#define R600_STENCILMASK_SHIFT 8
-#define R600_STENCILWRITEMASK_SHIFT 16
-
-#define PA_SU_PS_WIDTH_SHIFT 16
-
-#define PA_SU_CULL_FRONT (1 << 0)
-#define PA_SU_CULL_BACK (1 << 1)
-#define PA_SU_FACE_CCW (0 << 2)
-#define PA_SU_FACE_CW (1 << 2)
-
-#define PA_SU_POLYMODE_FRONT_SHIFT 5
-#define PA_SU_POLYMODE_BACK_SHIFT 5
-#define POLYGON_MODE_POINT 0
-#define POLYGON_MODE_LINE 1
-#define POLYGON_MODE_TRI 2
-
-
-#endif
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index e0d74ca558..68615ca162 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -106,7 +106,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 		return 0;
 	default:
-		debug_printf("r600: unknown param %d\n", param);
+		R600_ERR("r600: unknown param %d\n", param);
 		return 0;
 	}
 }
@@ -124,7 +124,7 @@ static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 		return 16.0f;
 	default:
-		debug_printf("r600: unsupported paramf %d\n", param);
+		R600_ERR("r600: unsupported paramf %d\n", param);
 		return 0.0f;
 	}
 }
@@ -137,7 +137,7 @@ static boolean r600_is_format_supported(struct pipe_screen* screen,
 					unsigned geom_flags)
 {
 	if (target >= PIPE_MAX_TEXTURE_TYPES) {
-		debug_printf("r600: unsupported texture type %d\n", target);
+		R600_ERR("r600: unsupported texture type %d\n", target);
 		return FALSE;
 	}
 	switch (format) {
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 0582839905..34c6a444a3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -129,7 +129,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
-	unsigned i, j, tmp;
+	unsigned i, tmp;
 
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
 	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index bbfe4da840..60270e18a6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -32,7 +32,6 @@
 #include "r600_context.h"
 #include "r600_resource.h"
 #include "r600d.h"
-#include "r600_reg.h"
 #include "r600_state_inlines.h"
 
 static void *r600_create_blend_state(struct pipe_context *ctx,
@@ -292,7 +291,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		type = R600_PS_CONSTANT_TYPE;
 		break;
 	default:
-		fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, shader);
+		R600_ERR("unsupported %d\n", shader);
 		return;
 	}
 	if (buffer && buffer->width0 > 0) {
@@ -418,8 +417,7 @@ static void r600_set_index_buffer(struct pipe_context *ctx,
 	if (ib) {
 		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 		memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
-	}
-	else {
+	} else {
 		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 		memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
 	}
@@ -643,15 +641,15 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 		if (!state->rt[i].blend_enable)
 			continue;
 
-		bc |= r600_translate_blend_function(eqRGB) << CB_BLEND_COLOR_COMB_FCN_SHIFT;
-		bc |= r600_translate_blend_factor(srcRGB) << CB_BLEND_COLOR_SRCBLEND_SHIFT;
-		bc |= r600_translate_blend_factor(dstRGB) << CB_BLEND_COLOR_DESTBLEND_SHIFT;
+		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
+		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
+		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 
 		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
-			bc |= CB_BLEND_SEPARATE_ALPHA_BLEND;
-			bc |= r600_translate_blend_function(eqA) << CB_BLEND_ALPHA_COMB_FCN_SHIFT;
-			bc |= r600_translate_blend_factor(srcA) << CB_BLEND_ALPHA_SRCBLEND_SHIFT;
-			bc |= r600_translate_blend_factor(dstA) << CB_BLEND_ALPHA_DESTBLEND_SHIFT;
+			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
+			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
+			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
+			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 		}
 
 		rstate->states[R600_BLEND__CB_BLEND0_CONTROL + i] = bc;
@@ -895,26 +893,25 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
-		
 		db_depth_control |= S_028800_BACKFACE_ENABLE(state->stencil[1].enabled);
 
-		stencil_ref_mask = (state->stencil[0].valuemask << R600_STENCILMASK_SHIFT) |
-			(state->stencil[0].writemask << R600_STENCILWRITEMASK_SHIFT);
+		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
+			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 		if (state->stencil[1].enabled) {
 			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
-			stencil_ref_mask_bf = (state->stencil[1].valuemask << R600_STENCILMASK_SHIFT) |
-				(state->stencil[1].writemask << R600_STENCILWRITEMASK_SHIFT);
+			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
+				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 		}
 	}
 
 	alpha_test_control = 0;
 	alpha_ref = 0;
 	if (state->alpha.enabled) {
-		alpha_test_control = (state->alpha.func) << 0;
-		alpha_test_control |= SX_ALPHA_TEST_ENABLE;
+		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
+		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 		alpha_ref = fui(state->alpha.ref_value);
 	}
 
@@ -1108,7 +1105,10 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	if (r600_conv_pipe_format(view->texture->format, &format))
 		return NULL;
 	desc = util_format_description(view->texture->format);
-	assert(desc == NULL);
+	if (desc == NULL) {
+		R600_ERR("unknow format %d\n", view->texture->format);
+		return NULL;
+	}
 	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
 	if (rstate == NULL) {
 		return NULL;
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 369263dc8f..26a5dd0432 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -18,79 +18,75 @@
  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE. */
-
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
 #ifndef R600_STATE_INLINES_H
 #define R600_STATE_INLINES_H
 
-#include "r600_reg.h"
-
 static INLINE uint32_t r600_translate_blend_function(int blend_func)
 {
 	switch (blend_func) {
-        case PIPE_BLEND_ADD:
-		return R600_BLEND_FCN_ADD;
-        case PIPE_BLEND_SUBTRACT:
-		return R600_BLEND_FCN_SUBTRACT;
-        case PIPE_BLEND_REVERSE_SUBTRACT:
-		return R600_BLEND_FCN_RSUB;
-        case PIPE_BLEND_MIN:
-		return R600_BLEND_FCN_MIN;
-        case PIPE_BLEND_MAX:
-		return R600_BLEND_FCN_MAX;
-        default:
-            fprintf(stderr, "r600: Unknown blend function %d\n", blend_func);
-            assert(0);
-            break;
-    }
-    return 0;
+	case PIPE_BLEND_ADD:
+		return V_028804_COMB_DST_PLUS_SRC;
+	case PIPE_BLEND_SUBTRACT:
+		return V_028804_COMB_SRC_MINUS_DST;
+	case PIPE_BLEND_REVERSE_SUBTRACT:
+		return V_028804_COMB_DST_MINUS_SRC;
+	case PIPE_BLEND_MIN:
+		return V_028804_COMB_MIN_DST_SRC;
+	case PIPE_BLEND_MAX:
+		return V_028804_COMB_MAX_DST_SRC;
+	default:
+		R600_ERR("Unknown blend function %d\n", blend_func);
+		assert(0);
+		break;
+	}
+	return 0;
 }
 
 static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
 {
 	switch (blend_fact) {
-        case PIPE_BLENDFACTOR_ONE:
-		return R600_BLEND_ZERO;
-        case PIPE_BLENDFACTOR_SRC_COLOR:
-		return R600_BLEND_SRC_COLOR;
-        case PIPE_BLENDFACTOR_SRC_ALPHA:
-		return R600_BLEND_SRC_ALPHA;
-        case PIPE_BLENDFACTOR_DST_ALPHA:
-		return R600_BLEND_DST_ALPHA;
-        case PIPE_BLENDFACTOR_DST_COLOR:
-		return R600_BLEND_DST_COLOR;
-        case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
-		return R600_BLEND_SRC_ALPHA_SATURATE;
-        case PIPE_BLENDFACTOR_CONST_COLOR:
-		return R600_BLEND_CONST_COLOR;
-        case PIPE_BLENDFACTOR_CONST_ALPHA:
-		return R600_BLEND_CONST_ALPHA;
-        case PIPE_BLENDFACTOR_ZERO:
-		return R600_BLEND_ZERO;
-        case PIPE_BLENDFACTOR_INV_SRC_COLOR:
-		return R600_BLEND_ONE_MINUS_SRC_COLOR;
-        case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
-		return R600_BLEND_ONE_MINUS_SRC_ALPHA;
-        case PIPE_BLENDFACTOR_INV_DST_ALPHA:
-		return R600_BLEND_ONE_MINUS_DST_ALPHA;
-        case PIPE_BLENDFACTOR_INV_DST_COLOR:
-		return R600_BLEND_ONE_MINUS_DST_COLOR;
-        case PIPE_BLENDFACTOR_INV_CONST_COLOR:
-		return R600_BLEND_ONE_MINUS_CONST_COLOR;
-        case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
-		return R600_BLEND_ONE_MINUS_CONST_ALPHA;
-
-        case PIPE_BLENDFACTOR_SRC1_COLOR:
-		return R600_BLEND_SRC1_COLOR;
-        case PIPE_BLENDFACTOR_SRC1_ALPHA:
-		return R600_BLEND_SRC1_ALPHA;
-        case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
-		return R600_BLEND_INV_SRC1_COLOR;
-        case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
-		return R600_BLEND_INV_SRC1_ALPHA;
+	case PIPE_BLENDFACTOR_ONE:
+		return V_028804_BLEND_ZERO;
+	case PIPE_BLENDFACTOR_SRC_COLOR:
+		return V_028804_BLEND_SRC_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA:
+		return V_028804_BLEND_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_DST_ALPHA:
+		return V_028804_BLEND_DST_ALPHA;
+	case PIPE_BLENDFACTOR_DST_COLOR:
+		return V_028804_BLEND_DST_COLOR;
+	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
+		return V_028804_BLEND_SRC_ALPHA_SATURATE;
+	case PIPE_BLENDFACTOR_CONST_COLOR:
+		return V_028804_BLEND_CONST_COLOR;
+	case PIPE_BLENDFACTOR_CONST_ALPHA:
+		return V_028804_BLEND_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_ZERO:
+		return V_028804_BLEND_ZERO;
+	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
+		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
+	case PIPE_BLENDFACTOR_INV_DST_COLOR:
+		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
+		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
+	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
+		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
+	case PIPE_BLENDFACTOR_SRC1_COLOR:
+		return V_028804_BLEND_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_SRC1_ALPHA:
+		return V_028804_BLEND_SRC1_ALPHA;
+	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
+		return V_028804_BLEND_INV_SRC1_COLOR;
+	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
+		return V_028804_BLEND_INV_SRC1_ALPHA;
 	default:
-		fprintf(stderr, "r600: Implementation error: "
-			"Bad blend factor %d not supported!\n", blend_fact);
+		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 		assert(0);
 		break;
 	}
@@ -101,23 +97,23 @@ static INLINE uint32_t r600_translate_stencil_op(int s_op)
 {
 	switch (s_op) {
 	case PIPE_STENCIL_OP_KEEP:
-		return R600_ZS_KEEP;
-        case PIPE_STENCIL_OP_ZERO:
-		return R600_ZS_ZERO;
-        case PIPE_STENCIL_OP_REPLACE:
-		return R600_ZS_REPLACE;
-        case PIPE_STENCIL_OP_INCR:
-		return R600_ZS_INCR;
-        case PIPE_STENCIL_OP_DECR:
-		return R600_ZS_DECR;
-        case PIPE_STENCIL_OP_INCR_WRAP:
-		return R600_ZS_INCR_WRAP;
-        case PIPE_STENCIL_OP_DECR_WRAP:
-		return R600_ZS_DECR_WRAP;
-        case PIPE_STENCIL_OP_INVERT:
-		return R600_ZS_INVERT;
-        default:
-		fprintf(stderr, "r600: Unknown stencil op %d", s_op);
+		return V_028800_STENCIL_KEEP;
+	case PIPE_STENCIL_OP_ZERO:
+		return V_028800_STENCIL_ZERO;
+	case PIPE_STENCIL_OP_REPLACE:
+		return V_028800_STENCIL_REPLACE;
+	case PIPE_STENCIL_OP_INCR:
+		return V_028800_STENCIL_INCR;
+	case PIPE_STENCIL_OP_DECR:
+		return V_028800_STENCIL_DECR;
+	case PIPE_STENCIL_OP_INCR_WRAP:
+		return V_028800_STENCIL_INVERT;
+	case PIPE_STENCIL_OP_DECR_WRAP:
+		return V_028800_STENCIL_DECR_WRAP;
+	case PIPE_STENCIL_OP_INVERT:
+		return V_028800_STENCIL_INVERT;
+	default:
+		R600_ERR("Unknown stencil op %d", s_op);
 		assert(0);
 		break;
 	}
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index c1acfcd29e..6085596ea8 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -249,6 +249,16 @@
 #define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
 #define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
 #define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
 #define R_028800_DB_DEPTH_CONTROL                    0x028800
 #define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
 #define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
@@ -268,9 +278,25 @@
 #define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
 #define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
 #define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define     V_028800_STENCILFUNC_NEVER                 0x00000000
+#define     V_028800_STENCILFUNC_LESS                  0x00000001
+#define     V_028800_STENCILFUNC_EQUAL                 0x00000002
+#define     V_028800_STENCILFUNC_LEQUAL                0x00000003
+#define     V_028800_STENCILFUNC_GREATER               0x00000004
+#define     V_028800_STENCILFUNC_NOTEQUAL              0x00000005
+#define     V_028800_STENCILFUNC_GEQUAL                0x00000006
+#define     V_028800_STENCILFUNC_ALWAYS                0x00000007
 #define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
 #define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
 #define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define     V_028800_STENCIL_KEEP                      0x00000000
+#define     V_028800_STENCIL_ZERO                      0x00000001
+#define     V_028800_STENCIL_REPLACE                   0x00000002
+#define     V_028800_STENCIL_INCR                      0x00000003
+#define     V_028800_STENCIL_DECR                      0x00000004
+#define     V_028800_STENCIL_INVERT                    0x00000005
+#define     V_028800_STENCIL_INCR_WRAP                 0x00000006
+#define     V_028800_STENCIL_DECR_WRAP                 0x00000007
 #define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
 #define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
 #define   C_028800_STENCILZPASS                        0xFFFE3FFF
@@ -316,6 +342,77 @@
 #define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
 #define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
 #define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define   S_028430_STENCILREF(x)                       (((x) & 0xFF) << 0)
+#define   G_028430_STENCILREF(x)                       (((x) >> 0) & 0xFF)
+#define   C_028430_STENCILREF                          0xFFFFFF00
+#define   S_028430_STENCILMASK(x)                      (((x) & 0xFF) << 8)
+#define   G_028430_STENCILMASK(x)                      (((x) >> 8) & 0xFF)
+#define   C_028430_STENCILMASK                         0xFFFF00FF
+#define   S_028430_STENCILWRITEMASK(x)                 (((x) & 0xFF) << 16)
+#define   G_028430_STENCILWRITEMASK(x)                 (((x) >> 16) & 0xFF)
+#define   C_028430_STENCILWRITEMASK                    0xFF00FFFF
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define   S_028434_STENCILREF_BF(x)                    (((x) & 0xFF) << 0)
+#define   G_028434_STENCILREF_BF(x)                    (((x) >> 0) & 0xFF)
+#define   C_028434_STENCILREF_BF                       0xFFFFFF00
+#define   S_028434_STENCILMASK_BF(x)                   (((x) & 0xFF) << 8)
+#define   G_028434_STENCILMASK_BF(x)                   (((x) >> 8) & 0xFF)
+#define   C_028434_STENCILMASK_BF                      0xFFFF00FF
+#define   S_028434_STENCILWRITEMASK_BF(x)              (((x) & 0xFF) << 16)
+#define   G_028434_STENCILWRITEMASK_BF(x)              (((x) >> 16) & 0xFF)
+#define   C_028434_STENCILWRITEMASK_BF                 0xFF00FFFF
+#define R_028804_CB_BLEND_CONTROL                    0x028804
+#define   S_028804_COLOR_SRCBLEND(x)                   (((x) & 0x1F) << 0)
+#define   G_028804_COLOR_SRCBLEND(x)                   (((x) >> 0) & 0x1F)
+#define   C_028804_COLOR_SRCBLEND                      0xFFFFFFE0
+#define     V_028804_BLEND_ZERO                        0x00000000
+#define     V_028804_BLEND_ONE                         0x00000001
+#define     V_028804_BLEND_SRC_COLOR                   0x00000002
+#define     V_028804_BLEND_ONE_MINUS_SRC_COLOR         0x00000003
+#define     V_028804_BLEND_SRC_ALPHA                   0x00000004
+#define     V_028804_BLEND_ONE_MINUS_SRC_ALPHA         0x00000005
+#define     V_028804_BLEND_DST_ALPHA                   0x00000006
+#define     V_028804_BLEND_ONE_MINUS_DST_ALPHA         0x00000007
+#define     V_028804_BLEND_DST_COLOR                   0x00000008
+#define     V_028804_BLEND_ONE_MINUS_DST_COLOR         0x00000009
+#define     V_028804_BLEND_SRC_ALPHA_SATURATE          0x0000000A
+#define     V_028804_BLEND_BOTH_SRC_ALPHA              0x0000000B
+#define     V_028804_BLEND_BOTH_INV_SRC_ALPHA          0x0000000C
+#define     V_028804_BLEND_CONST_COLOR                 0x0000000D
+#define     V_028804_BLEND_ONE_MINUS_CONST_COLOR       0x0000000E
+#define     V_028804_BLEND_SRC1_COLOR                  0x0000000F
+#define     V_028804_BLEND_INV_SRC1_COLOR              0x00000010
+#define     V_028804_BLEND_SRC1_ALPHA                  0x00000011
+#define     V_028804_BLEND_INV_SRC1_ALPHA              0x00000012
+#define     V_028804_BLEND_CONST_ALPHA                 0x00000013
+#define     V_028804_BLEND_ONE_MINUS_CONST_ALPHA       0x00000014
+#define   S_028804_COLOR_COMB_FCN(x)                   (((x) & 0x7) << 5)
+#define   G_028804_COLOR_COMB_FCN(x)                   (((x) >> 5) & 0x7)
+#define   C_028804_COLOR_COMB_FCN                      0xFFFFFF1F
+#define     V_028804_COMB_DST_PLUS_SRC                 0x00000000
+#define     V_028804_COMB_SRC_MINUS_DST                0x00000001
+#define     V_028804_COMB_MIN_DST_SRC                  0x00000002
+#define     V_028804_COMB_MAX_DST_SRC                  0x00000003
+#define     V_028804_COMB_DST_MINUS_SRC                0x00000004
+#define   S_028804_COLOR_DESTBLEND(x)                  (((x) & 0x1F) << 8)
+#define   G_028804_COLOR_DESTBLEND(x)                  (((x) >> 8) & 0x1F)
+#define   C_028804_COLOR_DESTBLEND                     0xFFFFE0FF
+#define   S_028804_OPACITY_WEIGHT(x)                   (((x) & 0x1) << 13)
+#define   G_028804_OPACITY_WEIGHT(x)                   (((x) >> 13) & 0x1)
+#define   C_028804_OPACITY_WEIGHT                      0xFFFFDFFF
+#define   S_028804_ALPHA_SRCBLEND(x)                   (((x) & 0x1F) << 16)
+#define   G_028804_ALPHA_SRCBLEND(x)                   (((x) >> 16) & 0x1F)
+#define   C_028804_ALPHA_SRCBLEND                      0xFFE0FFFF
+#define   S_028804_ALPHA_COMB_FCN(x)                   (((x) & 0x7) << 21)
+#define   G_028804_ALPHA_COMB_FCN(x)                   (((x) >> 21) & 0x7)
+#define   C_028804_ALPHA_COMB_FCN                      0xFF1FFFFF
+#define   S_028804_ALPHA_DESTBLEND(x)                  (((x) & 0x1F) << 24)
+#define   G_028804_ALPHA_DESTBLEND(x)                  (((x) >> 24) & 0x1F)
+#define   C_028804_ALPHA_DESTBLEND                     0xE0FFFFFF
+#define   S_028804_SEPARATE_ALPHA_BLEND(x)             (((x) & 0x1) << 29)
+#define   G_028804_SEPARATE_ALPHA_BLEND(x)             (((x) >> 29) & 0x1)
+#define   C_028804_SEPARATE_ALPHA_BLEND                0xDFFFFFFF
 #define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
 #define   S_028814_CULL_FRONT(x)                       (((x) & 0x1) << 0)
 #define   G_028814_CULL_FRONT(x)                       (((x) >> 0) & 0x1)
-- 
cgit v1.2.3


From 8f6341d42131e6f60f269610d62b7f5b7b683052 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Tue, 3 Aug 2010 15:49:21 -0400
Subject: r600g: fix stencil

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c  |  2 --
 src/gallium/drivers/r600/r600_state.c | 13 +++++++------
 2 files changed, 7 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index cc37227ead..f4eedfe4cb 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -86,7 +86,6 @@ static void r600_clear_render_target(struct pipe_context *pipe,
 
 	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
 					 dstx, dsty, width, height);
-R600_ERR("vtx elem %p\n", rctx->vertex_elements);
 }
 
 static void r600_clear_depth_stencil(struct pipe_context *pipe,
@@ -105,7 +104,6 @@ static void r600_clear_depth_stencil(struct pipe_context *pipe,
 
 	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
 					 dstx, dsty, width, height);
-R600_ERR("vtx elem %p\n", rctx->vertex_elements);
 }
 
 static void r600_resource_copy_region(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 60270e18a6..f687d31e4b 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -869,6 +869,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
 static struct radeon_state *r600_dsa(struct r600_context *rctx)
 {
 	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
+	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 	unsigned db_depth_control, alpha_test_control, alpha_ref;
@@ -880,30 +881,30 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 
 	stencil_ref_mask = 0;
 	stencil_ref_mask_bf = 0;
-	db_depth_control = 0x00700700 |
-		S_028800_Z_ENABLE(state->depth.enabled) |
+	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 		S_028800_ZFUNC(state->depth.func);
 	/* set stencil enable */
-	db_depth_control |= S_028800_STENCIL_ENABLE(state->stencil[0].enabled);
-	
-	if (state->stencil[0].enabled) {
 
+	if (state->stencil[0].enabled) {
+		db_depth_control |= S_028800_STENCIL_ENABLE(1);
 		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
-		db_depth_control |= S_028800_BACKFACE_ENABLE(state->stencil[1].enabled);
 
 		stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 			S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
+		stencil_ref_mask |= S_028430_STENCILREF(stencil_ref->ref_value[0]);
 		if (state->stencil[1].enabled) {
+			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 			db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 			stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 				S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
+			stencil_ref_mask_bf |= S_028430_STENCILREF(stencil_ref->ref_value[1]);
 		}
 	}
 
-- 
cgit v1.2.3


From 3a8d4a89795d180b910b2c0dfa98c57cf9bb45a6 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Tue, 3 Aug 2010 16:15:17 -0400
Subject: r600g: fix color target mask

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_state.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index f687d31e4b..f0abafd6c2 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1182,8 +1182,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 		if (pbs->rt[i].blend_enable) {
 			color_control |= (1 << (8 + i));
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
-		} else if (i == 0)
-			target_mask |= 0xf;
+		}
 	}
 	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
-- 
cgit v1.2.3


From dd863bf5e7c6680075cf7c355a026b1da69ee9e3 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Tue, 3 Aug 2010 17:45:51 -0400
Subject: r600g: add polygon offset support

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c |  2 +-
 src/gallium/drivers/r600/r600_state.c  | 44 +++++++++++++++++++++++++++++-----
 src/gallium/drivers/r600/r600d.h       | 23 ++++++++++++++++++
 3 files changed, 62 insertions(+), 7 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 7d304f5ae8..43b3e40fad 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1142,7 +1142,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_DP3,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_DP4,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_DST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
 	{TGSI_OPCODE_MAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
 	{TGSI_OPCODE_SLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
 	{TGSI_OPCODE_SGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index f0abafd6c2..72c0ac5dd1 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -765,8 +765,37 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 {
 	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
+	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
+	float offset_units = 0, offset_scale = 0;
+	char depth = 0;
+	unsigned offset_db_fmt_cntl = 0;
+
+	if (fb->zsbuf) {
+		offset_units = state->offset_units;
+		offset_scale = state->offset_scale * 12.0f;
+		switch (fb->zsbuf->texture->format) {
+		case PIPE_FORMAT_Z24X8_UNORM:
+		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+			depth = -24;
+			offset_units *= 2.0f;
+			break;
+		case PIPE_FORMAT_Z32_FLOAT:
+			depth = -23;
+			offset_units *= 1.0f;
+			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+			break;
+		case PIPE_FORMAT_Z16_UNORM:
+			depth = -16;
+			offset_units *= 4.0f;
+			break;
+		default:
+			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
+			return NULL;
+		}
+	}
+	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 
 	rctx->flat_shade = state->flatshade;
 	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
@@ -777,7 +806,10 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
 			S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 			S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
-			S_028814_FACE(!state->front_ccw);
+			S_028814_FACE(!state->front_ccw) |
+			S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+			S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+			S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
 	rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
@@ -790,12 +822,12 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
 	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
 	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = 0x00000000;
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL] = offset_db_fmt_cntl;
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = 0x00000000;
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE] = fui(offset_scale);
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
+	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 6085596ea8..24cb8593f7 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -539,6 +539,29 @@
 #define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
 #define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
 #define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) & 0xFF) << 0)
+#define   G_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(x)      (((x) >> 0) & 0xFF)
+#define   C_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS         0xFFFFFF00
+#define   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) & 0x1) << 8)
+#define   G_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(x)      (((x) >> 8) & 0x1)
+#define   C_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT         0xFFFFFEFF
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define   S_028E00_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E00_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E00_SCALE                               0x00000000
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define   S_028E04_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E04_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E04_OFFSET                              0x00000000
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define   S_028E08_SCALE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E08_SCALE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E08_SCALE                               0x00000000
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
+#define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028E0C_OFFSET                              0x00000000
 #define R_028A40_VGT_GS_MODE                         0x028A40
 #define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
 #define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
-- 
cgit v1.2.3


From 9a78e790dc4c40362b971ad5eff2505c02b73ed7 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 4 Aug 2010 16:10:11 -0400
Subject: r600g: always perform texture perspective divide + fix blending

quake3 engine seems to run fine at this point (ioquake)

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c        | 121 +++++++++++++-------------
 src/gallium/drivers/r600/r600_state.c         |   5 +-
 src/gallium/drivers/r600/r600_state_inlines.h |   2 +-
 src/gallium/drivers/r600/r600d.h              |  25 ++++++
 4 files changed, 88 insertions(+), 65 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 43b3e40fad..8da102cde0 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -963,68 +963,66 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
 
 	/* Add perspective divide */
-	if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_TXP) {
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
-		alu.src[0].sel = src_gpr;
-		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 3;
-		alu.last = 1;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
+	alu.src[0].sel = src_gpr;
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 3;
+	alu.last = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
 
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-		alu.src[0].sel = ctx->temp_reg;
-		alu.src[0].chan = 3;
-		alu.src[1].sel = src_gpr;
-		alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 0;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-		alu.src[0].sel = ctx->temp_reg;
-		alu.src[0].chan = 3;
-		alu.src[1].sel = src_gpr;
-		alu.src[1].chan = tgsi_chan(&inst->Src[0], 1);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 1;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-		alu.src[0].sel = ctx->temp_reg;
-		alu.src[0].chan = 3;
-		alu.src[1].sel = src_gpr;
-		alu.src[1].chan = tgsi_chan(&inst->Src[0], 2);
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 2;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-		alu.src[0].sel = 249;
-		alu.src[0].chan = 0;
-		alu.dst.sel = ctx->temp_reg;
-		alu.dst.chan = 3;
-		alu.last = 1;
-		alu.dst.write = 1;
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-		src_gpr = ctx->temp_reg;
-	}
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 0;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 1);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 3;
+	alu.src[1].sel = src_gpr;
+	alu.src[1].chan = tgsi_chan(&inst->Src[0], 2);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 2;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+	alu.src[0].sel = 249;
+	alu.src[0].chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.chan = 3;
+	alu.last = 1;
+	alu.dst.write = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	src_gpr = ctx->temp_reg;
 
 	/* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
 	memset(&tex, 0, sizeof(struct r600_bc_tex));
@@ -1041,6 +1039,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	tex.src_sel_y = 1;
 	tex.src_sel_z = 2;
 	tex.src_sel_w = 3;
+
 	if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
 		tex.coord_type_x = 1;
 		tex.coord_type_y = 1;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 72c0ac5dd1..e8a591f73e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -628,7 +628,6 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	rstate->states[R600_BLEND__CB_BLEND_CONTROL] = 0x00000000;
 
 	for (i = 0; i < 8; i++) {
-
 		unsigned eqRGB = state->rt[i].rgb_func;
 		unsigned srcRGB = state->rt[i].rgb_src_factor;
 		unsigned dstRGB = state->rt[i].rgb_dst_factor;
@@ -1202,7 +1201,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	int i;
 
 	target_mask = 0;
-	color_control = 0;
+	color_control = S_028808_PER_MRT_BLEND(1);
 
 	if (pbs->logicop_enable) {
 		color_control |= (pbs->logicop_func) << 16;
@@ -1212,7 +1211,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	target_mask |= (pbs->rt[0].colormask);
 	for (i = 0; i < 8; i++) {
 		if (pbs->rt[i].blend_enable) {
-			color_control |= (1 << (8 + i));
+			color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 26a5dd0432..321e75d7a1 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -48,7 +48,7 @@ static INLINE uint32_t r600_translate_blend_factor(int blend_fact)
 {
 	switch (blend_fact) {
 	case PIPE_BLENDFACTOR_ONE:
-		return V_028804_BLEND_ZERO;
+		return V_028804_BLEND_ONE;
 	case PIPE_BLENDFACTOR_SRC_COLOR:
 		return V_028804_BLEND_SRC_COLOR;
 	case PIPE_BLENDFACTOR_SRC_ALPHA:
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 24cb8593f7..8205bdeadc 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -315,6 +315,31 @@
 #define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
 #define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
 #define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define   S_028808_PER_MRT_BLEND(x)                    (((x) & 0x1) << 7)
+#define   G_028808_PER_MRT_BLEND(x)                    (((x) >> 7) & 0x1)
+#define   C_028808_PER_MRT_BLEND                       0xFFFFFF7F
+#define   S_028808_TARGET_BLEND_ENABLE(x)              (((x) & 0xFF) << 8)
+#define   G_028808_TARGET_BLEND_ENABLE(x)              (((x) >> 8) & 0xFF)
+#define   C_028808_TARGET_BLEND_ENABLE                 0xFFFF00FF
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
 #define R_028010_DB_DEPTH_INFO                       0x028010
 #define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
 #define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)
-- 
cgit v1.2.3


From 9c949d4a4dd43b7889e13bdf683bcf211f049ced Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 4 Aug 2010 17:37:59 -0400
Subject: r600g: don't use dynamic state allocation for states

Simplify state handly by avoiding state allocation.
Next step is to allocate once for all context packet
buffer and then avoid rebuilding pm4 packet each time
(through use of combined crc) this would also avoid
number of memcpy.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.c    | 141 +++++++--------
 src/gallium/drivers/r600/r600_context.h    |  29 +--
 src/gallium/drivers/r600/r600_draw.c       | 115 ++++++------
 src/gallium/drivers/r600/r600_shader.c     |  34 ++--
 src/gallium/drivers/r600/r600_state.c      | 281 ++++++++++++-----------------
 src/gallium/drivers/r600/radeon.h          |  52 ++++--
 src/gallium/targets/dri-r600/Makefile      |   4 +-
 src/gallium/winsys/r600/drm/radeon.c       |  11 --
 src/gallium/winsys/r600/drm/radeon_ctx.c   | 160 +++++-----------
 src/gallium/winsys/r600/drm/radeon_draw.c  |  92 +---------
 src/gallium/winsys/r600/drm/radeon_priv.h  |  29 ---
 src/gallium/winsys/r600/drm/radeon_state.c |  70 +------
 12 files changed, 361 insertions(+), 657 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index ae1780a1d4..f7732d8952 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -48,18 +48,14 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	struct r600_screen *rscreen = rctx->screen;
 	static int dc = 0;
 
-	if (radeon_ctx_pm4(rctx->ctx))
+	if (radeon_ctx_pm4(&rctx->ctx))
 		return;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
 	if (!dc)
-		radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
-#if 1
-	radeon_ctx_submit(rctx->ctx);
-#endif
-	rctx->ctx = radeon_ctx_decref(rctx->ctx);
-	rctx->ctx = radeon_ctx(rscreen->rw);
+		radeon_ctx_dump_bof(&rctx->ctx, "gallium.bof");
+	radeon_ctx_submit(&rctx->ctx);
 	dc++;
 }
 
@@ -220,9 +216,8 @@ static void r600_init_config(struct r600_context *rctx)
 	printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
 	printf("num_es_stack_entries : %d\n", num_es_stack_entries);
 
-	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
-
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
+	radeon_state_init(&rctx->config, rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
 	case CHIP_RV610:
 	case CHIP_RV620:
@@ -231,75 +226,75 @@ static void r600_init_config(struct r600_context *rctx)
 	case CHIP_RV710:
 		break;
 	default:
-		rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 		break;
 	}
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->hw_states.config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-	rctx->hw_states.config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-	rctx->hw_states.config->states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-	rctx->hw_states.config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(rctx->hw_states.config);
+	rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+	rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+	rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+	rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+	rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+	rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
+	rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
+	radeon_state_pm4(&rctx->config);
 }
 
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
@@ -333,7 +328,7 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 
 	r600_init_config(rctx);
 
-	rctx->ctx = radeon_ctx(rscreen->rw);
-	rctx->draw = radeon_draw(rscreen->rw);
+	radeon_ctx_init(&rctx->ctx, rscreen->rw);
+	radeon_draw_init(&rctx->draw, rscreen->rw);
 	return &rctx->context;
 }
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 8d102b6850..78da88fef5 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -76,7 +76,7 @@ struct r600_context_state {
 	union pipe_states		state;
 	unsigned			refcount;
 	unsigned			type;
-	struct radeon_state		*rstate;
+	struct radeon_state		rstate;
 	struct r600_shader		shader;
 	struct radeon_bo		*bo;
 };
@@ -89,28 +89,28 @@ struct r600_vertex_element
 };
 
 struct r600_context_hw_states {
-	struct radeon_state	*rasterizer;
-	struct radeon_state	*scissor;
-	struct radeon_state	*dsa;
-	struct radeon_state	*blend;
-	struct radeon_state	*viewport;
-	struct radeon_state	*cb0;
-	struct radeon_state	*config;
-	struct radeon_state	*cb_cntl;
-	struct radeon_state	*db;
+	struct radeon_state	rasterizer;
+	struct radeon_state	scissor;
+	struct radeon_state	dsa;
+	struct radeon_state	blend;
+	struct radeon_state	viewport;
+	struct radeon_state	cb0;
+	struct radeon_state	config;
+	struct radeon_state	cb_cntl;
+	struct radeon_state	db;
 	unsigned		ps_nresource;
 	unsigned		ps_nsampler;
-	struct radeon_state	*ps_resource[160];
-	struct radeon_state	*ps_sampler[16];
+	struct radeon_state	ps_resource[160];
+	struct radeon_state	ps_sampler[16];
 };
 
 struct r600_context {
 	struct pipe_context		context;
 	struct r600_screen		*screen;
 	struct radeon			*rw;
-	struct radeon_ctx		*ctx;
+	struct radeon_ctx		ctx;
 	struct blitter_context		*blitter;
-	struct radeon_draw		*draw;
+	struct radeon_draw		draw;
 	/* hw states */
 	struct r600_context_hw_states	hw_states;
 	/* pipe states */
@@ -120,6 +120,7 @@ struct r600_context {
 	unsigned			ps_nsampler_view;
 	unsigned			vs_nsampler_view;
 	unsigned			nvertex_buffer;
+	struct radeon_state		config;
 	struct r600_context_state	*rasterizer;
 	struct r600_context_state	*poly_stipple;
 	struct r600_context_state	*scissor;
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 43c805b982..7130bf2fa8 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -38,8 +38,8 @@
 
 struct r600_draw {
 	struct pipe_context	*ctx;
-	struct radeon_state	*draw;
-	struct radeon_state	*vgt;
+	struct radeon_state	draw;
+	struct radeon_state	vgt;
 	unsigned		mode;
 	unsigned		start;
 	unsigned		count;
@@ -51,7 +51,7 @@ static int r600_draw_common(struct r600_draw *draw)
 {
 	struct r600_context *rctx = r600_context(draw->ctx);
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *vs_resource;
+	struct radeon_state vs_resource;
 	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
 	u32 vgt_dma_index_type, vgt_draw_initiator;
@@ -88,10 +88,10 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
+	r = radeon_draw_set(&rctx->draw, &rctx->vs_shader->rstate);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
+	r = radeon_draw_set(&rctx->draw, &rctx->ps_shader->rstate);
 	if (r)
 		return r;
 
@@ -103,81 +103,68 @@ static int r600_draw_common(struct r600_draw *draw)
 		r = r600_conv_pipe_format(rctx->vertex_elements->elements[i].src_format, &format);
 		if (r)
 			return r;
-		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
-		if (vs_resource == NULL)
-			return -ENOMEM;
-		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		vs_resource->nbo = 1;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
-								S_038008_DATA_FORMAT(format);
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
-		vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
-		r = radeon_draw_set_new(rctx->draw, vs_resource);
-		if (r)
-			return r;
-	}
-#if 0
-	/* setup texture sampler & resource */
-	for (i = 0 ; i < rctx->ps_nsampler; i++) {
-		r = radeon_draw_set_new(rctx->draw, rctx->ps_sampler[i]->rstate);
+		r = radeon_state_init(&vs_resource, rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
 		if (r)
 			return r;
-	}
-	for (i = 0 ; i < rctx->ps_nsampler_view; i++) {
-		r = radeon_draw_set_new(rctx->draw, rctx->ps_sampler_view[i]->rstate);
+		vs_resource.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		vs_resource.nbo = 1;
+		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
+		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
+		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
+								S_038008_DATA_FORMAT(format);
+		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
+		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
+		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
+		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
+		vs_resource.placement[0] = RADEON_GEM_DOMAIN_GTT;
+		vs_resource.placement[1] = RADEON_GEM_DOMAIN_GTT;
+		radeon_state_pm4(&vs_resource);
+		r = radeon_draw_set(&rctx->draw, &vs_resource);
 		if (r)
 			return r;
 	}
-#endif
 	/* FIXME start need to change winsys */
-	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
-	if (draw->draw == NULL)
-		return -ENOMEM;
-	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
+	r = radeon_state_init(&draw->draw, rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	if (r)
+		return r;
+	draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+	draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	if (draw->index_buffer) {
-		rbuffer = (struct r600_buffer*)draw->index_buffer;
-		draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw->nbo = 1;
+		rbuffer = (struct r600_resource*)draw->index_buffer;
+		draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw.nbo = 1;
 	}
-	r = radeon_draw_set_new(rctx->draw, draw->draw);
+	radeon_state_pm4(&draw->draw);
+	r = radeon_draw_set(&rctx->draw, &draw->draw);
+	if (r)
+		return r;
+	r = radeon_state_init(&draw->vgt, rscreen->rw, R600_VGT_TYPE, R600_VGT);
 	if (r)
 		return r;
-	draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
-	if (draw->vgt == NULL)
-		return -ENOMEM;
-	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
-	draw->vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
-	draw->vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
-	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
-	r = radeon_draw_set_new(rctx->draw, draw->vgt);
+	draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
+	draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+	draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
+	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+	draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
+	radeon_state_pm4(&draw->vgt);
+	r = radeon_draw_set(&rctx->draw, &draw->vgt);
 	if (r)
 		return r;
 	/* FIXME */
-	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+	r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 	if (r == -EBUSY) {
 		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+		r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 	}
-	if (r)
-		return r;
-	rctx->draw = radeon_draw_duplicate(rctx->draw);
-	return 0;
+	return r;
 }
 
 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 8da102cde0..f38aa7b463 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -130,11 +130,12 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
 	unsigned i, tmp;
+	int r;
 
-	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
-	if (state == NULL)
-		return -ENOMEM;
+	r = radeon_state_init(&rpshader->rstate, rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
+	if (r)
+		return r;
+	state = &rpshader->rstate;
 	for (i = 0; i < 10; i++) {
 		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
 	}
@@ -145,11 +146,10 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	}
 	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
 	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
-	rpshader->rstate = state;
-	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->nbo = 2;
-	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate.bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate.bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate.nbo = 2;
+	rpshader->rstate.placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
@@ -159,11 +159,12 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
 	unsigned i, tmp;
+	int r;
 
-	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
-	if (state == NULL)
-		return -ENOMEM;
+	r = radeon_state_init(&rpshader->rstate, rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
+	if (r)
+		return r;
+	state = &rpshader->rstate;
 	for (i = 0; i < rshader->ninput; i++) {
 		tmp = S_028644_SEMANTIC(i);
 		tmp |= S_028644_SEL_CENTROID(1);
@@ -178,10 +179,9 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
 	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
-	rpshader->rstate = state;
-	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->nbo = 1;
-	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate.bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate.nbo = 1;
+	rpshader->rstate.placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e8a591f73e..926a19cc6f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -277,9 +277,10 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
 	unsigned nconstant = 0, i, type, id;
-	struct radeon_state *rstate;
+	struct radeon_state rstate;
 	struct pipe_transfer *transfer;
 	u32 *ptr;
+	int r;
 
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
@@ -300,16 +301,16 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		if (ptr == NULL)
 			return;
 		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state(rscreen->rw, type, id + i);
-			if (rstate == NULL)
+			r = radeon_state_init(&rstate, rscreen->rw, type, id + i);
+			if (r)
 				return;
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
-			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
-			if (radeon_state_pm4(rstate))
+			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
+			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
+			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
+			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
+			if (radeon_state_pm4(&rstate))
 				return;
-			if (radeon_draw_set_new(rctx->draw, rstate))
+			if (radeon_draw_set(&rctx->draw, &rstate))
 				return;
 		}
 		pipe_buffer_unmap(ctx, buffer, transfer);
@@ -520,7 +521,6 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state *
 		R600_ERR("invalid type %d\n", rstate->type);
 		return NULL;
 	}
-	radeon_state_decref(rstate->rstate);
 	FREE(rstate);
 	return NULL;
 }
@@ -603,16 +603,17 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 	return rstate;
 }
 
-static struct radeon_state *r600_blend(struct r600_context *rctx)
+static int r600_blend(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
+	int r;
+
+	r = radeon_state_init(rstate, rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
+	if (r)
+		return r;
 
-	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
-	if (rstate == NULL)
-		return NULL;
 	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
 	rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
 	rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
@@ -656,26 +657,23 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 			rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
 	}
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_cb0(struct r600_context *rctx)
+static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct r600_resource_texture *rtex;
 	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 	unsigned level = state->cbufs[0]->level;
 	unsigned pitch, slice;
+	int r;
+
+	r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, R600_CB0);
+	if (r)
+		return r;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
-	if (rstate == NULL)
-		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
 	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -695,11 +693,7 @@ static struct radeon_state *r600_cb0(struct r600_context *rctx)
 	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
 	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
 	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
 static int r600_db_format(unsigned pformat, unsigned *format)
@@ -718,23 +712,22 @@ static int r600_db_format(unsigned pformat, unsigned *format)
 	}
 }
 
-static struct radeon_state *r600_db(struct r600_context *rctx)
+static int r600_db(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct r600_resource_texture *rtex;
 	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 	unsigned level = state->cbufs[0]->level;
 	unsigned pitch, slice, format;
+	int r;
 
-	if (state->zsbuf == NULL)
-		return NULL;
-
-	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
-	if (rstate == NULL)
-		return NULL;
+	r = radeon_state_init(rstate, rscreen->rw, R600_DB_TYPE, R600_DB);
+	if (r)
+		return r;
 
+	if (state->zsbuf == NULL)
+		return 0;
 	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -744,8 +737,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
 	if (r600_db_format(state->zsbuf->texture->format, &format)) {
-		radeon_state_decref(rstate);
-		return NULL;
+		return -EINVAL;
 	}
 	rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
 	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
@@ -754,23 +746,22 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
 	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
 						S_028000_SLICE_TILE_MAX(slice);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
+static int r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
 	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	float offset_units = 0, offset_scale = 0;
 	char depth = 0;
 	unsigned offset_db_fmt_cntl = 0;
+	int r;
 
+	r = radeon_state_init(rstate, rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
+	if (r)
+		return r;
 	if (fb->zsbuf) {
 		offset_units = state->offset_units;
 		offset_scale = state->offset_scale * 12.0f;
@@ -791,15 +782,12 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 			break;
 		default:
 			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
-			return NULL;
+			return -EINVAL;
 		}
 	}
 	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 
 	rctx->flat_shade = state->flatshade;
-	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
-	if (rstate == NULL)
-		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
@@ -827,25 +815,21 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_scissor(struct r600_context *rctx)
+static int r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	u32 tl, br;
+	int r;
 
+	r = radeon_state_init(rstate, rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	if (r)
+		return r;
 	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
-	if (rstate == NULL)
-		return NULL;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
@@ -865,22 +849,18 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_viewport(struct r600_context *rctx)
+static int r600_viewport(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
+	int r;
 
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
-	if (rstate == NULL)
-		return NULL;
+	r = radeon_state_init(rstate, rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	if (r)
+		return r;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
@@ -890,33 +870,29 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_dsa(struct r600_context *rctx)
+static int r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	unsigned db_depth_control, alpha_test_control, alpha_ref;
 	unsigned stencil_ref_mask, stencil_ref_mask_bf;
-	
-	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
-	if (rstate == NULL)
-		return NULL;
+	int r;
+
+	r = radeon_state_init(rstate, rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	if (r)
+		return r;
 
 	stencil_ref_mask = 0;
 	stencil_ref_mask_bf = 0;
 	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 		S_028800_ZFUNC(state->depth.func);
-	/* set stencil enable */
 
+	/* set stencil enable */
 	if (state->stencil[0].enabled) {
 		db_depth_control |= S_028800_STENCIL_ENABLE(1);
 		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
@@ -963,11 +939,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
 	rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
 	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
 static inline unsigned r600_tex_wrap(unsigned wrap)
@@ -1045,16 +1017,15 @@ static INLINE u32 S_FIXED(float value, u32 frac_bits)
 	return value * (1 << frac_bits);
 }
 
-static struct radeon_state *r600_sampler(struct r600_context *rctx,
-				const struct pipe_sampler_state *state,
-				unsigned id)
+static int r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_sampler_state *state, unsigned id)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
+	int r;
 
-	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
-	if (rstate == NULL)
-		return NULL;
+	r = radeon_state_init(rstate, rscreen->rw, R600_PS_SAMPLER_TYPE, id);
+	if (r)
+		return r;
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
 			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
@@ -1069,11 +1040,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
 			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
 static inline unsigned r600_tex_swizzle(unsigned swizzle)
@@ -1123,27 +1090,25 @@ static inline unsigned r600_tex_dim(unsigned dim)
 	}
 }
 
-static struct radeon_state *r600_resource(struct r600_context *rctx,
-					const struct pipe_sampler_view *view,
-					unsigned id)
+static int r600_resource(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_sampler_view *view, unsigned id)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
 	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
 	unsigned format;
+	int r;
 
+	r = radeon_state_init(rstate, rscreen->rw, R600_PS_RESOURCE_TYPE, id);
+	if (r)
+		return r;
 	if (r600_conv_pipe_format(view->texture->format, &format))
-		return NULL;
+		return -EINVAL;
 	desc = util_format_description(view->texture->format);
 	if (desc == NULL) {
 		R600_ERR("unknow format %d\n", view->texture->format);
-		return NULL;
-	}
-	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
-	if (rstate == NULL) {
-		return NULL;
+		return -EINVAL;
 	}
 	tmp = (struct r600_resource_texture*)view->texture;
 	rbuffer = &tmp->resource;
@@ -1185,20 +1150,15 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 			S_038014_LAST_ARRAY(0);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
 			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
+static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
 	uint32_t color_control, target_mask;
-	int i;
+	int i, r;
 
 	target_mask = 0;
 	color_control = S_028808_PER_MRT_BLEND(1);
@@ -1215,7 +1175,9 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
-	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	r = radeon_state_init(rstate, rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	if (r)
+		return r;
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1227,11 +1189,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
 	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	return radeon_state_pm4(rstate);
 }
 
 int r600_context_hw_states(struct r600_context *rctx)
@@ -1242,91 +1200,74 @@ int r600_context_hw_states(struct r600_context *rctx)
 	/* free previous TODO determine what need to be updated, what
 	 * doesn't
 	 */
-	//radeon_state_decref(rctx->hw_states.config);
-	radeon_state_decref(rctx->hw_states.cb_cntl);
-	radeon_state_decref(rctx->hw_states.db);
-	radeon_state_decref(rctx->hw_states.rasterizer);
-	radeon_state_decref(rctx->hw_states.scissor);
-	radeon_state_decref(rctx->hw_states.dsa);
-	radeon_state_decref(rctx->hw_states.blend);
-	radeon_state_decref(rctx->hw_states.viewport);
-	radeon_state_decref(rctx->hw_states.cb0);
-	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
-		radeon_state_decref(rctx->hw_states.ps_resource[i]);
-		rctx->hw_states.ps_resource[i] = NULL;
-	}
-	rctx->hw_states.ps_nresource = 0;
-	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
-		radeon_state_decref(rctx->hw_states.ps_sampler[i]);
-		rctx->hw_states.ps_sampler[i] = NULL;
-	}
-	rctx->hw_states.ps_nsampler = 0;
+	memset(&rctx->hw_states, 0, sizeof(struct r600_context_hw_states));
 
 	/* build new states */
-	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
-	rctx->hw_states.scissor = r600_scissor(rctx);
-	rctx->hw_states.dsa = r600_dsa(rctx);
-	rctx->hw_states.blend = r600_blend(rctx);
-	rctx->hw_states.viewport = r600_viewport(rctx);
-	rctx->hw_states.cb0 = r600_cb0(rctx);
-	rctx->hw_states.db = r600_db(rctx);
-	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
+	rctx->hw_states.config = rctx->config;
+	r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
+	r600_scissor(rctx, &rctx->hw_states.scissor);
+	r600_dsa(rctx, &rctx->hw_states.dsa);
+	r600_blend(rctx, &rctx->hw_states.blend);
+	r600_viewport(rctx, &rctx->hw_states.viewport);
+	r600_cb0(rctx, &rctx->hw_states.cb0);
+	r600_db(rctx, &rctx->hw_states.db);
+	r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
 
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
-							&rctx->ps_sampler[i]->state.sampler,
-							R600_PS_SAMPLER + i);
+			r600_sampler(rctx, &rctx->hw_states.ps_sampler[i],
+					&rctx->ps_sampler[i]->state.sampler,
+					R600_PS_SAMPLER + i);
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			rctx->hw_states.ps_resource[i] = r600_resource(rctx,
-							&rctx->ps_sampler_view[i]->state.sampler_view,
-							R600_PS_RESOURCE + i);
+			r600_resource(rctx, &rctx->hw_states.ps_resource[i],
+					&rctx->ps_sampler_view[i]->state.sampler_view,
+					R600_PS_RESOURCE + i);
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
 
 	/* bind states */
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.db);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.rasterizer);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.scissor);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.dsa);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.blend);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.viewport);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb0);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb0);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.config);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
+	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb_cntl);
 	if (r)
 		return r;
 	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
-		if (rctx->hw_states.ps_resource[i]) {
-			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
+		if (rctx->hw_states.ps_resource[i].valid) {
+			r = radeon_draw_set(&rctx->draw, &rctx->hw_states.ps_resource[i]);
 			if (r)
 				return r;
 		}
 	}
 	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
-		if (rctx->hw_states.ps_sampler[i]) {
-			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
+		if (rctx->hw_states.ps_sampler[i].valid) {
+			r = radeon_draw_set(&rctx->draw, &rctx->hw_states.ps_sampler[i]);
 			if (r)
 				return r;
 		}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 3a8405f9b4..709ef8a85a 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -103,17 +103,17 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
  */
 struct radeon_state {
 	struct radeon			*radeon;
-	unsigned			refcount;
+	unsigned			valid;
 	unsigned			type;
 	unsigned			id;
 	unsigned			nstates;
-	u32				*states;
+	u32				states[64];
 	unsigned			npm4;
 	unsigned			cpm4;
 	u32				pm4_crc;
-	u32				*pm4;
+	u32				pm4[128];
 	u32				nimmd;
-	u32				*immd;
+	u32				immd[64];
 	unsigned			nbo;
 	struct radeon_bo		*bo[4];
 	unsigned			nreloc;
@@ -123,35 +123,51 @@ struct radeon_state {
 	unsigned			bo_dirty[4];
 };
 
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
-struct radeon_state *radeon_state_incref(struct radeon_state *state);
-struct radeon_state *radeon_state_decref(struct radeon_state *state);
+int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 type, u32 id);
 int radeon_state_pm4(struct radeon_state *state);
 
 /*
  * draw functions
  */
 struct radeon_draw {
-	unsigned			refcount;
 	struct radeon			*radeon;
 	unsigned			nstate;
-	struct radeon_state		**state;
+	struct radeon_state		state[1273];
 	unsigned			cpm4;
 };
 
-struct radeon_draw *radeon_draw(struct radeon *radeon);
-struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw);
-struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw);
-struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw);
+int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
 int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
-int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
 int radeon_draw_check(struct radeon_draw *draw);
 
-struct radeon_ctx *radeon_ctx(struct radeon *radeon);
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
+/*
+ * Context
+ */
+#pragma pack(1)
+struct radeon_cs_reloc {
+	uint32_t	handle;
+	uint32_t	read_domain;
+	uint32_t	write_domain;
+	uint32_t	flags;
+};
+#pragma pack()
+
+struct radeon_ctx {
+	struct radeon			*radeon;
+	u32				*pm4;
+	u32				cpm4;
+	u32				draw_cpm4;
+	unsigned			id;
+	unsigned			nreloc;
+	struct radeon_cs_reloc		reloc[2048];
+	unsigned			nbo;
+	struct radeon_bo		*bo[2048];
+	unsigned			ndraw;
+	struct radeon_draw		draw[128];
+};
+
+int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon);
 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
 int radeon_ctx_pm4(struct radeon_ctx *ctx);
 int radeon_ctx_submit(struct radeon_ctx *ctx);
 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
diff --git a/src/gallium/targets/dri-r600/Makefile b/src/gallium/targets/dri-r600/Makefile
index 932303d194..9c8b4ab252 100644
--- a/src/gallium/targets/dri-r600/Makefile
+++ b/src/gallium/targets/dri-r600/Makefile
@@ -4,12 +4,12 @@ include $(TOP)/configs/current
 LIBNAME = r600_dri.so
 
 PIPE_DRIVERS = \
+	$(TOP)/src/gallium/drivers/r600/libr600.a \
 	$(TOP)/src/gallium/state_trackers/dri/drm/libdridrm.a \
 	$(TOP)/src/gallium/winsys/r600/drm/libr600winsys.a \
 	$(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \
 	$(TOP)/src/gallium/drivers/trace/libtrace.a \
-	$(TOP)/src/gallium/drivers/rbug/librbug.a \
-	$(TOP)/src/gallium/drivers/r600/libr600.a
+	$(TOP)/src/gallium/drivers/rbug/librbug.a
 
 C_SOURCES = \
 	target.c \
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 7e65669806..24d821d5cf 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -43,16 +43,6 @@ static int radeon_get_device(struct radeon *radeon)
 	return r;
 }
 
-/* symbol missing drove me crazy hack to get symbol exported */
-static void fake(void)
-{
-	struct radeon_ctx *ctx;
-	struct radeon_draw *draw;
-
-	ctx = radeon_ctx(NULL);
-	draw = radeon_draw(NULL);
-}
-
 struct radeon *radeon_new(int fd, unsigned device)
 {
 	struct radeon *radeon;
@@ -60,7 +50,6 @@ struct radeon *radeon_new(int fd, unsigned device)
 
 	radeon = calloc(1, sizeof(*radeon));
 	if (radeon == NULL) {
-		fake();
 		return NULL;
 	}
 	radeon->fd = fd;
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index 6b0eba0b28..af270d5d20 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -32,13 +32,8 @@
 
 int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo)
 {
-	void *ptr;
-
-	ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1));
-	if (ptr == NULL) {
-		return -ENOMEM;
-	}
-	ctx->bo = ptr;
+	if (ctx->nbo >= 2048)
+		return -EBUSY;
 	ctx->bo[ctx->nbo] = bo;
 	ctx->nbo++;
 	return 0;
@@ -76,49 +71,26 @@ void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *place
 	}
 }
 
-struct radeon_ctx *radeon_ctx(struct radeon *radeon)
-{
-	struct radeon_ctx *ctx;
-
-	if (radeon == NULL)
-		return NULL;
-	ctx = calloc(1, sizeof(*ctx));
-	if (ctx == NULL)
-		return NULL;
-	ctx->radeon = radeon_incref(radeon);
-	return ctx;
-}
-
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx)
+static void radeon_ctx_clear(struct radeon_ctx *ctx)
 {
-	ctx->refcount++;
-	return ctx;
+	ctx->draw_cpm4 = 0;
+	ctx->cpm4 = 0;
+	ctx->ndraw = 0;
+	ctx->nbo = 0;
+	ctx->nreloc = 0;
 }
 
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
+int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon)
 {
-	unsigned i;
-
-	if (ctx == NULL)
-		return NULL;
-	if (--ctx->refcount > 0) {
-		return NULL;
-	}
-
-	for (i = 0; i < ctx->ndraw; i++) {
-		ctx->draw[i] = radeon_draw_decref(ctx->draw[i]);
-	}
-	for (i = 0; i < ctx->nbo; i++) {
-		ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
-	}
-	ctx->radeon = radeon_decref(ctx->radeon);
-	free(ctx->draw);
-	free(ctx->bo);
+	memset(ctx, 0, sizeof(struct radeon_ctx));
+	ctx->radeon = radeon_incref(radeon);
+	radeon_ctx_clear(ctx);
 	free(ctx->pm4);
-	free(ctx->reloc);
-	memset(ctx, 0, sizeof(*ctx));
-	free(ctx);
-	return NULL;
+	ctx->cpm4 = 0;
+	ctx->pm4 = malloc(64 * 1024);
+	if (ctx->pm4 == NULL)
+		return -ENOMEM;
+	return 0;
 }
 
 static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
@@ -143,7 +115,6 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
 	return 0;
 }
 
-
 int radeon_ctx_submit(struct radeon_ctx *ctx)
 {
 	struct drm_radeon_cs drmib;
@@ -170,6 +141,7 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
 	r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
 				sizeof(struct drm_radeon_cs));
 #endif
+	radeon_ctx_clear(ctx);
 	return r;
 }
 
@@ -177,7 +149,6 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			unsigned id, unsigned *placement)
 {
 	unsigned i;
-	struct radeon_cs_reloc *ptr;
 
 	for (i = 0; i < ctx->nreloc; i++) {
 		if (ctx->reloc[i].handle == bo->handle) {
@@ -185,14 +156,12 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			return 0;
 		}
 	}
-	ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1));
-	if (ptr == NULL)
-		return -ENOMEM;
-	ctx->reloc = ptr;
-	ptr[ctx->nreloc].handle = bo->handle;
-	ptr[ctx->nreloc].read_domain = placement[0] | placement [1];
-	ptr[ctx->nreloc].write_domain = placement[0] | placement [1];
-	ptr[ctx->nreloc].flags = 0;
+	if (ctx->nreloc >= 2048)
+		return -EINVAL;
+	ctx->reloc[ctx->nreloc].handle = bo->handle;
+	ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1];
+	ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1];
+	ctx->reloc[ctx->nreloc].flags = 0;
 	ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
 	ctx->nreloc++;
 	return 0;
@@ -221,21 +190,13 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
 	return 0;
 }
 
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
 {
-	struct radeon_draw *pdraw = NULL;
-	struct radeon_draw **ndraw;
-	struct radeon_state *nstate, *ostate;
-	unsigned cpm4, i, cstate;
-	void *tmp;
+	unsigned cpm4, i;
 	int r = 0;
 
-	ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1));
-	if (ndraw == NULL)
-		return -ENOMEM;
-	ctx->draw = ndraw;
 	for (i = 0; i < draw->nstate; i++) {
-		r = radeon_ctx_state_bo(ctx, draw->state[i]);
+		r = radeon_ctx_state_bo(ctx, &draw->state[i]);
 		if (r)
 			return r;
 	}
@@ -247,69 +208,48 @@ int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
 			__func__, draw->cpm4, RADEON_CTX_MAX_PM4);
 		return -EINVAL;
 	}
-	tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*));
-	if (tmp == NULL)
-		return -ENOMEM;
-	ctx->state = tmp;
-	pdraw = ctx->cdraw;
-	for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) {
-		nstate = draw->state[i];
-		if (nstate) {
-			if (pdraw && pdraw->state[i]) {
-				ostate = pdraw->state[i];
-				if (ostate->pm4_crc != nstate->pm4_crc) {
-					ctx->state[cstate++] = nstate;
-					cpm4 += nstate->cpm4;
-				}
-			} else {
-				ctx->state[cstate++] = nstate;
-				cpm4 += nstate->cpm4;
+	ctx->draw[ctx->ndraw] = *draw;
+	for (i = 0, cpm4 = 0; i < draw->nstate - 1; i++) {
+		ctx->draw[ctx->ndraw].state[i].valid &= ~2;
+		if (ctx->draw[ctx->ndraw].state[i].valid) {
+			if (ctx->ndraw > 1 && ctx->draw[ctx->ndraw - 1].state[i].valid) {
+				if (ctx->draw[ctx->ndraw - 1].state[i].pm4_crc == draw->state[i].pm4_crc)
+					continue;
 			}
+			ctx->draw[ctx->ndraw].state[i].valid |= 2;
+			cpm4 += ctx->draw[ctx->ndraw].state[i].cpm4;
 		}
 	}
 	/* The last state is the draw state always add it */
-	if (draw->state[i] == NULL) {
+	if (!draw->state[i].valid) {
 		fprintf(stderr, "%s no draw command\n", __func__);
 		return -EINVAL;
 	}
-	ctx->state[cstate++] = draw->state[i];
-	cpm4 += draw->state[i]->cpm4;
+	ctx->draw[ctx->ndraw].state[i].valid |= 2;
+	cpm4 += ctx->draw[ctx->ndraw].state[i].cpm4;
 	if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) {
 		/* need to flush */
 		return -EBUSY;
 	}
 	ctx->draw_cpm4 += cpm4;
-	ctx->nstate = cstate;
-	ctx->draw[ctx->ndraw++] = draw;
-	ctx->cdraw = draw;
+	ctx->ndraw++;
 	return 0;
 }
 
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
-{
-	int r;
-
-	radeon_draw_incref(draw);
-	r = radeon_ctx_set_draw_new(ctx, draw);
-	if (r)
-		radeon_draw_decref(draw);
-	return r;
-}
-
 int radeon_ctx_pm4(struct radeon_ctx *ctx)
 {
-	unsigned i;
+	unsigned i, j, c;
 	int r;
 
-	free(ctx->pm4);
-	ctx->cpm4 = 0;
-	ctx->pm4 = malloc(ctx->draw_cpm4 * 4);
-	if (ctx->pm4 == NULL)
-		return -EINVAL;
-	for (i = 0, ctx->id = 0; i < ctx->nstate; i++) {
-		r = radeon_ctx_state_schedule(ctx, ctx->state[i]);
-		if (r)
-			return r;
+	for (i = 0, c = 0, ctx->id = 0; i < ctx->ndraw; i++) {
+		for (j = 0; j < ctx->draw[i].nstate; j++) {
+			if (ctx->draw[i].state[j].valid & 2) {
+				r = radeon_ctx_state_schedule(ctx, &ctx->draw[i].state[j]);
+				if (r)
+					return r;
+				c += ctx->draw[i].state[j].cpm4;
+			}
+		}
 	}
 	if (ctx->id != ctx->draw_cpm4) {
 		fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c
index 4413ed79fb..53699eb0b1 100644
--- a/src/gallium/winsys/r600/drm/radeon_draw.c
+++ b/src/gallium/winsys/r600/drm/radeon_draw.c
@@ -31,111 +31,33 @@
 /*
  * draw functions
  */
-struct radeon_draw *radeon_draw(struct radeon *radeon)
+int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon)
 {
-	struct radeon_draw *draw;
-
-	draw = calloc(1, sizeof(*draw));
-	if (draw == NULL)
-		return NULL;
+	memset(draw, 0, sizeof(struct radeon_draw));
 	draw->nstate = radeon->nstate;
 	draw->radeon = radeon;
-	draw->refcount = 1;
-	draw->state = calloc(1, sizeof(void*) * draw->nstate);
-	if (draw->state == NULL) {
-		free(draw);
-		return NULL;
-	}
-	return draw;
-}
-
-struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw)
-{
-	draw->refcount++;
-	return draw;
-}
-
-struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw)
-{
-	unsigned i;
-
-	if (draw == NULL)
-		return NULL;
-	if (--draw->refcount > 0)
-		return NULL;
-	for (i = 0; i < draw->nstate; i++) {
-		draw->state[i] = radeon_state_decref(draw->state[i]);
-	}
-	free(draw->state);
-	memset(draw, 0, sizeof(*draw));
-	free(draw);
-	return NULL;
+	return 0;
 }
 
-int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
+int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state)
 {
 	if (state == NULL)
 		return 0;
 	if (state->type >= draw->radeon->ntype)
 		return -EINVAL;
-	draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
-	draw->state[state->id] = state;
+	draw->state[state->id] = *state;
 	return 0;
 }
 
-int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state)
-{
-	if (state == NULL)
-		return 0;
-	radeon_state_incref(state);
-	return radeon_draw_set_new(draw, state);
-}
-
 int radeon_draw_check(struct radeon_draw *draw)
 {
 	unsigned i;
 	int r;
 
-	r = radeon_draw_pm4(draw);
-	if (r)
-		return r;
 	for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
-		if (draw->state[i]) {
-			draw->cpm4 += draw->state[i]->cpm4;
+		if (draw->state[i].valid) {
+			draw->cpm4 += draw->state[i].cpm4;
 		}
 	}
 	return 0;
 }
-
-struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw)
-{
-	struct radeon_draw *ndraw;
-	unsigned i;
-
-	if (draw == NULL)
-		return NULL;
-	ndraw = radeon_draw(draw->radeon);
-	if (ndraw == NULL) {
-		return NULL;
-	}
-	for (i = 0; i < draw->nstate; i++) {
-		if (radeon_draw_set(ndraw, draw->state[i])) {
-			radeon_draw_decref(ndraw);
-			return NULL;
-		}
-	}
-	return ndraw;
-}
-
-int radeon_draw_pm4(struct radeon_draw *draw)
-{
-	unsigned i;
-	int r;
-
-	for (i = 0; i < draw->nstate; i++) {
-		r = radeon_state_pm4(draw->state[i]);
-		if (r)
-			return r;
-	}
-	return 0;
-}
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index b91421f438..80392cda96 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -24,7 +24,6 @@
 #include "radeon.h"
 
 struct radeon;
-struct radeon_ctx;
 
 /*
  * radeon functions
@@ -71,34 +70,6 @@ extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
 /*
  * radeon context functions
  */
-#pragma pack(1)
-struct radeon_cs_reloc {
-	uint32_t	handle;
-	uint32_t	read_domain;
-	uint32_t	write_domain;
-	uint32_t	flags;
-};
-#pragma pack()
-
-struct radeon_ctx {
-	int				refcount;
-	struct radeon			*radeon;
-	u32				*pm4;
-	u32				cpm4;
-	u32				draw_cpm4;
-	unsigned			id;
-	unsigned			next_id;
-	unsigned			nreloc;
-	struct radeon_cs_reloc		*reloc;
-	unsigned			nbo;
-	struct radeon_bo		**bo;
-	unsigned			ndraw;
-	struct radeon_draw		*cdraw;
-	struct radeon_draw		**draw;
-	unsigned			nstate;
-	struct radeon_state		**state;
-};
-
 int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
 struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
 void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index 308288557a..d7cd1d7a94 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -32,82 +32,23 @@
 /*
  * state core functions
  */
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
+int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 type, u32 id)
 {
-	struct radeon_state *state;
-
 	if (type > radeon->ntype) {
 		fprintf(stderr, "%s invalid type %d\n", __func__, type);
-		return NULL;
+		return -EINVAL;
 	}
 	if (id > radeon->nstate) {
 		fprintf(stderr, "%s invalid state id %d\n", __func__, id);
-		return NULL;
+		return -EINVAL;
 	}
-	state = calloc(1, sizeof(*state));
-	if (state == NULL)
-		return NULL;
+	memset(state, 0, sizeof(struct radeon_state));
 	state->radeon = radeon;
 	state->type = type;
 	state->id = id;
-	state->refcount = 1;
 	state->npm4 = radeon->type[type].npm4;
 	state->nstates = radeon->type[type].nstates;
-	state->states = calloc(1, state->nstates * 4);
-	state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
-	if (state->states == NULL || state->pm4 == NULL) {
-		radeon_state_decref(state);
-		return NULL;
-	}
-	return state;
-}
-
-struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
-{
-	struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
-	unsigned i;
-
-	if (state == NULL)
-		return NULL;
-	nstate->cpm4 = state->cpm4;
-	nstate->nbo = state->nbo;
-	nstate->nreloc = state->nreloc;
-	memcpy(nstate->states, state->states, state->nstates * 4);
-	memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
-	memcpy(nstate->placement, state->placement, 8 * 4);
-	memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
-	memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
-	memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
-	for (i = 0; i < state->nbo; i++) {
-		nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]);
-	}
-	return nstate;
-}
-
-struct radeon_state *radeon_state_incref(struct radeon_state *state)
-{
-	state->refcount++;
-	return state;
-}
-
-struct radeon_state *radeon_state_decref(struct radeon_state *state)
-{
-	unsigned i;
-
-	if (state == NULL)
-		return NULL;
-	if (--state->refcount > 0) {
-		return NULL;
-	}
-	for (i = 0; i < state->nbo; i++) {
-		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
-	}
-	free(state->immd);
-	free(state->states);
-	free(state->pm4);
-	memset(state, 0, sizeof(*state));
-	free(state);
-	return NULL;
+	return 0;
 }
 
 int radeon_state_replace_always(struct radeon_state *ostate,
@@ -156,6 +97,7 @@ int radeon_state_pm4(struct radeon_state *state)
 		return r;
 	}
 	state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
+	state->valid = 1;
 	return 0;
 }
 
-- 
cgit v1.2.3


From 2b9036476511edd549d1c2cea6044eef4652a19c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 6 Aug 2010 14:53:38 +1000
Subject: r600g: improve supported format selection.

This fixes fbo-readpixels piglit test, and adds support for swapping
the formats. Not all formats are correct yet I don't think.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r600/r600_draw.c          |   6 +-
 src/gallium/drivers/r600/r600_helper.c        |  99 -----------------
 src/gallium/drivers/r600/r600_screen.c        |  76 ++++++-------
 src/gallium/drivers/r600/r600_state.c         |  15 ++-
 src/gallium/drivers/r600/r600_state_inlines.h | 153 ++++++++++++++++++++++++++
 src/gallium/drivers/r600/r600d.h              |   5 +
 6 files changed, 212 insertions(+), 142 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 7130bf2fa8..3a54cee2d9 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -34,7 +34,7 @@
 #include "r600_screen.h"
 #include "r600_context.h"
 #include "r600_resource.h"
-#include "r600d.h"
+#include "r600_state_inlines.h"
 
 struct r600_draw {
 	struct pipe_context	*ctx;
@@ -100,9 +100,7 @@ static int r600_draw_common(struct r600_draw *draw)
 		vertex_buffer = &rctx->vertex_buffer[j];
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
-		r = r600_conv_pipe_format(rctx->vertex_elements->elements[i].src_format, &format);
-		if (r)
-			return r;
+		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
 		r = radeon_state_init(&vs_resource, rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
 		if (r)
 			return r;
diff --git a/src/gallium/drivers/r600/r600_helper.c b/src/gallium/drivers/r600/r600_helper.c
index c672fe7386..5e0e0aab57 100644
--- a/src/gallium/drivers/r600/r600_helper.c
+++ b/src/gallium/drivers/r600/r600_helper.c
@@ -30,105 +30,6 @@
 #include "r600_context.h"
 #include "r600d.h"
 
-int r600_conv_pipe_format(unsigned pformat, unsigned *format)
-{
-	switch (pformat) {
-	case PIPE_FORMAT_R32G32B32_FLOAT:
-		*format = 0x30;
-		return 0;
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-		*format = V_0280A0_COLOR_32_32_32_32_FLOAT;
-		return 0;
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_USCALED:
-	case PIPE_FORMAT_R8G8B8A8_SNORM:
-	case PIPE_FORMAT_R8G8B8A8_SSCALED:
-		*format = V_0280A0_COLOR_8_8_8_8;
-		return 0;
-	case PIPE_FORMAT_R32_FLOAT:
-		*format = V_0280A0_COLOR_32_FLOAT;
-		return 0;
-	case PIPE_FORMAT_R32G32_FLOAT:
-		*format = V_0280A0_COLOR_32_32_FLOAT;
-		return 0;
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-		*format = V_0280A0_COLOR_8;
-		return 0;
-	case PIPE_FORMAT_B4G4R4A4_UNORM:
-		*format = V_0280A0_COLOR_4_4_4_4;
-		return 0;
-	case PIPE_FORMAT_B5G6R5_UNORM:
-		*format = V_0280A0_COLOR_5_6_5;
-		return 0;
-	case PIPE_FORMAT_L16_UNORM:
-	case PIPE_FORMAT_Z16_UNORM:
-	case PIPE_FORMAT_Z32_UNORM:
-	case PIPE_FORMAT_Z32_FLOAT:
-	case PIPE_FORMAT_R64_FLOAT:
-	case PIPE_FORMAT_R64G64_FLOAT:
-	case PIPE_FORMAT_R64G64B64_FLOAT:
-	case PIPE_FORMAT_R64G64B64A64_FLOAT:
-	case PIPE_FORMAT_R32_UNORM:
-	case PIPE_FORMAT_R32G32_UNORM:
-	case PIPE_FORMAT_R32G32B32_UNORM:
-	case PIPE_FORMAT_R32G32B32A32_UNORM:
-	case PIPE_FORMAT_R32_USCALED:
-	case PIPE_FORMAT_R32G32_USCALED:
-	case PIPE_FORMAT_R32G32B32_USCALED:
-	case PIPE_FORMAT_R32G32B32A32_USCALED:
-	case PIPE_FORMAT_R32_SNORM:
-	case PIPE_FORMAT_R32G32_SNORM:
-	case PIPE_FORMAT_R32G32B32_SNORM:
-	case PIPE_FORMAT_R32G32B32A32_SNORM:
-	case PIPE_FORMAT_R32_SSCALED:
-	case PIPE_FORMAT_R32G32_SSCALED:
-	case PIPE_FORMAT_R32G32B32_SSCALED:
-	case PIPE_FORMAT_R32G32B32A32_SSCALED:
-	case PIPE_FORMAT_R16_UNORM:
-	case PIPE_FORMAT_R16G16_UNORM:
-	case PIPE_FORMAT_R16G16B16_UNORM:
-	case PIPE_FORMAT_R16G16B16A16_UNORM:
-	case PIPE_FORMAT_R16_USCALED:
-	case PIPE_FORMAT_R16G16_USCALED:
-	case PIPE_FORMAT_R16G16B16_USCALED:
-	case PIPE_FORMAT_R16G16B16A16_USCALED:
-	case PIPE_FORMAT_R16_SNORM:
-	case PIPE_FORMAT_R16G16_SNORM:
-	case PIPE_FORMAT_R16G16B16_SNORM:
-	case PIPE_FORMAT_R16G16B16A16_SNORM:
-	case PIPE_FORMAT_R16_SSCALED:
-	case PIPE_FORMAT_R16G16_SSCALED:
-	case PIPE_FORMAT_R16G16B16_SSCALED:
-	case PIPE_FORMAT_R16G16B16A16_SSCALED:
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R8G8_UNORM:
-	case PIPE_FORMAT_R8G8B8_UNORM:
-	case PIPE_FORMAT_R8_USCALED:
-	case PIPE_FORMAT_R8G8_USCALED:
-	case PIPE_FORMAT_R8G8B8_USCALED:
-	case PIPE_FORMAT_R8_SNORM:
-	case PIPE_FORMAT_R8G8_SNORM:
-	case PIPE_FORMAT_R8G8B8_SNORM:
-	case PIPE_FORMAT_R8_SSCALED:
-	case PIPE_FORMAT_R8G8_SSCALED:
-	case PIPE_FORMAT_R8G8B8_SSCALED:
-	case PIPE_FORMAT_R32_FIXED:
-	case PIPE_FORMAT_R32G32_FIXED:
-	case PIPE_FORMAT_R32G32B32_FIXED:
-	case PIPE_FORMAT_R32G32B32A32_FIXED:
-	default:
-		R600_ERR("unsupported %d\n", pformat);
-		return -EINVAL;
-	}
-}
-
 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 {
 	switch (pprim) {
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index 68615ca162..4b87327a7c 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -32,6 +32,7 @@
 #include "r600_context.h"
 #include "r600_public.h"
 #include "r600_resource.h"
+#include "r600_state_inlines.h"
 
 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 {
@@ -133,50 +134,51 @@ static boolean r600_is_format_supported(struct pipe_screen* screen,
 					enum pipe_format format,
 					enum pipe_texture_target target,
 					unsigned sample_count,
-					unsigned bindings,
+					unsigned usage,
 					unsigned geom_flags)
 {
+	unsigned retval = 0;
 	if (target >= PIPE_MAX_TEXTURE_TYPES) {
 		R600_ERR("r600: unsupported texture type %d\n", target);
 		return FALSE;
 	}
-	switch (format) {
-	case PIPE_FORMAT_B4G4R4A4_UNORM:
-	case PIPE_FORMAT_B5G6R5_UNORM:
-	case PIPE_FORMAT_B5G5R5A1_UNORM:
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_A8R8G8B8_SRGB:
-	case PIPE_FORMAT_R8G8B8A8_SRGB:
-	case PIPE_FORMAT_DXT1_RGB:
-	case PIPE_FORMAT_DXT1_RGBA:
-	case PIPE_FORMAT_DXT3_RGBA:
-	case PIPE_FORMAT_DXT5_RGBA:
-	case PIPE_FORMAT_UYVY:
-	case PIPE_FORMAT_L8_SRGB:
-	case PIPE_FORMAT_L8A8_SRGB:
-	case PIPE_FORMAT_L8A8_UNORM:
-	case PIPE_FORMAT_A8R8G8B8_UNORM:
-	case PIPE_FORMAT_X8R8G8B8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R8G8B8X8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_A8B8G8R8_SRGB:
-	case PIPE_FORMAT_B8G8R8A8_SRGB:
-	case PIPE_FORMAT_I8_UNORM:
-	case PIPE_FORMAT_Z16_UNORM:
-	case PIPE_FORMAT_X8Z24_UNORM:
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-	case PIPE_FORMAT_Z32_UNORM:
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-	case PIPE_FORMAT_Z24X8_UNORM:
-		return TRUE;
-	default:
-		/* Unknown format... */
-		break;
+
+	/* Multisample */
+	if (sample_count > 1)
+		return FALSE;
+
+	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
+	    r600_is_sampler_format_supported(format)) {
+		retval |= PIPE_BIND_SAMPLER_VIEW;
+	}
+
+	if ((usage & (PIPE_BIND_RENDER_TARGET |
+                  PIPE_BIND_DISPLAY_TARGET |
+                  PIPE_BIND_SCANOUT |
+                  PIPE_BIND_SHARED)) &&
+	    r600_is_colorbuffer_format_supported(format)) {
+		retval |= usage &
+			(PIPE_BIND_RENDER_TARGET |
+			 PIPE_BIND_DISPLAY_TARGET |
+			 PIPE_BIND_SCANOUT |
+			 PIPE_BIND_SHARED);
 	}
-	return FALSE;
+
+	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
+	    r600_is_zs_format_supported(format)) {
+		retval |= PIPE_BIND_DEPTH_STENCIL;
+	}
+
+	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
+	    r600_is_vertex_format_supported(format))
+		retval |= PIPE_BIND_VERTEX_BUFFER;
+
+	if (usage & PIPE_BIND_TRANSFER_READ)
+		retval |= PIPE_BIND_TRANSFER_READ;
+	if (usage & PIPE_BIND_TRANSFER_WRITE)
+		retval |= PIPE_BIND_TRANSFER_WRITE;
+
+	return retval == usage;
 }
 
 static void r600_destroy_screen(struct pipe_screen* pscreen)
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 926a19cc6f..b8d50452e6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -668,6 +668,8 @@ static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 	unsigned level = state->cbufs[0]->level;
 	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap;
 	int r;
 
 	r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, R600_CB0);
@@ -685,8 +687,16 @@ static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->nbo = 3;
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+	color_info = S_0280A0_FORMAT(format) |
+	  S_0280A0_COMP_SWAP(swap) |
+	  S_0280A0_BLEND_CLAMP(1) |
+	  S_0280A0_SOURCE_FORMAT(1);
+
 	rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = 0x08110068;
+	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
 	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
@@ -1103,7 +1113,8 @@ static int r600_resource(struct r600_context *rctx, struct radeon_state *rstate,
 	r = radeon_state_init(rstate, rscreen->rw, R600_PS_RESOURCE_TYPE, id);
 	if (r)
 		return r;
-	if (r600_conv_pipe_format(view->texture->format, &format))
+	format = r600_translate_colorformat(view->texture->format);
+	if (format == ~0)
 		return -EINVAL;
 	desc = util_format_description(view->texture->format);
 	if (desc == NULL) {
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 321e75d7a1..b45089dcc1 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -23,6 +23,9 @@
 #ifndef R600_STATE_INLINES_H
 #define R600_STATE_INLINES_H
 
+#include "util/u_format.h"
+#include "r600d.h"
+
 static INLINE uint32_t r600_translate_blend_function(int blend_func)
 {
 	switch (blend_func) {
@@ -126,4 +129,154 @@ static INLINE uint32_t r600_translate_ds_func(int func)
 	return func;
 }
 
+static uint32_t r600_translate_colorswap(enum pipe_format format)
+{
+	switch (format) {
+		/* 8-bit buffers. */
+        case PIPE_FORMAT_A8_UNORM:
+        case PIPE_FORMAT_I8_UNORM:
+        case PIPE_FORMAT_L8_UNORM:
+        case PIPE_FORMAT_R8_UNORM:
+        case PIPE_FORMAT_R8_SNORM:
+		return SWAP_STD;
+
+		/* 16-bit buffers. */
+        case PIPE_FORMAT_B5G6R5_UNORM:
+		return SWAP_STD_REV;
+
+        case PIPE_FORMAT_B5G5R5A1_UNORM:
+        case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return SWAP_ALT;
+
+        case PIPE_FORMAT_B4G4R4A4_UNORM:
+        case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return SWAP_ALT;
+		/* 32-bit buffers. */
+        case PIPE_FORMAT_B8G8R8A8_UNORM:
+        case PIPE_FORMAT_B8G8R8X8_UNORM:
+		return SWAP_ALT;
+
+        case PIPE_FORMAT_A8R8G8B8_UNORM:
+        case PIPE_FORMAT_X8R8G8B8_UNORM:
+		return SWAP_ALT_REV;
+        case PIPE_FORMAT_R8G8B8A8_SNORM:
+        case PIPE_FORMAT_R8G8B8X8_UNORM:
+		return SWAP_STD;
+
+        case PIPE_FORMAT_A8B8G8R8_UNORM:
+        case PIPE_FORMAT_X8B8G8R8_UNORM:
+//        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+		return SWAP_STD_REV;
+
+        case PIPE_FORMAT_R10G10B10A2_UNORM:
+        case PIPE_FORMAT_R10G10B10X2_SNORM:
+        case PIPE_FORMAT_B10G10R10A2_UNORM:
+        case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return SWAP_STD_REV;
+
+		/* 64-bit buffers. */
+        case PIPE_FORMAT_R16G16B16A16_UNORM:
+        case PIPE_FORMAT_R16G16B16A16_SNORM:
+//		return V_0280A0_COLOR_16_16_16_16;
+        case PIPE_FORMAT_R16G16B16A16_FLOAT:
+//		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+
+		/* 128-bit buffers. */
+        case PIPE_FORMAT_R32G32B32A32_FLOAT:
+//		return V_0280A0_COLOR_32_32_32_32_FLOAT;
+		return 0;
+	default:
+		R600_ERR("unsupported colorswap format %d\n", format);
+		return ~0;
+	}
+	return ~0;
+
+}
+
+static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
+{
+	switch (format) {
+		/* 8-bit buffers. */
+        case PIPE_FORMAT_A8_UNORM:
+        case PIPE_FORMAT_I8_UNORM:
+        case PIPE_FORMAT_L8_UNORM:
+        case PIPE_FORMAT_R8_UNORM:
+        case PIPE_FORMAT_R8_SNORM:
+		return V_0280A0_COLOR_8;
+
+		/* 16-bit buffers. */
+        case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_0280A0_COLOR_5_6_5;
+
+        case PIPE_FORMAT_B5G5R5A1_UNORM:
+        case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_0280A0_COLOR_1_5_5_5;
+
+        case PIPE_FORMAT_B4G4R4A4_UNORM:
+        case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_0280A0_COLOR_4_4_4_4;
+
+		/* 32-bit buffers. */
+        case PIPE_FORMAT_B8G8R8A8_UNORM:
+        case PIPE_FORMAT_B8G8R8X8_UNORM:
+        case PIPE_FORMAT_A8R8G8B8_UNORM:
+        case PIPE_FORMAT_X8R8G8B8_UNORM:
+        case PIPE_FORMAT_A8B8G8R8_UNORM:
+        case PIPE_FORMAT_R8G8B8A8_SNORM:
+        case PIPE_FORMAT_X8B8G8R8_UNORM:
+        case PIPE_FORMAT_R8G8B8X8_UNORM:
+        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+		return V_0280A0_COLOR_8_8_8_8;
+
+        case PIPE_FORMAT_R10G10B10A2_UNORM:
+        case PIPE_FORMAT_R10G10B10X2_SNORM:
+        case PIPE_FORMAT_B10G10R10A2_UNORM:
+        case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_0280A0_COLOR_10_10_10_2;
+
+		/* 64-bit buffers. */
+        case PIPE_FORMAT_R16G16B16A16_UNORM:
+        case PIPE_FORMAT_R16G16B16A16_SNORM:
+		return V_0280A0_COLOR_16_16_16_16;
+        case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+        case PIPE_FORMAT_R32G32_FLOAT:
+		return V_0280A0_COLOR_32_32_FLOAT;
+
+		/* 128-bit buffers. */
+        case PIPE_FORMAT_R32G32B32_FLOAT:
+        case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		return V_0280A0_COLOR_32_32_32_32_FLOAT;
+
+		/* YUV buffers. */
+        case PIPE_FORMAT_UYVY:
+//		return R300_COLOR_FORMAT_YVYU;
+        case PIPE_FORMAT_YUYV:
+//		return R300_COLOR_FORMAT_VYUY;
+        default:
+		return ~0; /* Unsupported. */
+	}
+}
+
+static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0;
+}
+
+static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0 &&
+		r600_translate_colorswap(format) != ~0;
+}
+
+static INLINE boolean r600_is_zs_format_supported(enum pipe_format format)
+{
+	return TRUE;
+}
+
+static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format)
+{
+	return r600_translate_colorformat(format) != ~0;
+}
+
 #endif
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 8205bdeadc..2d0ede20fa 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -1169,4 +1169,9 @@
 #define   G_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) >> 14) & 0x1)
 #define   C_0286D4_PNT_SPRITE_TOP_1                    0xFFFFBFFF
 
+/* temporary swap */
+#define SWAP_STD 0
+#define SWAP_ALT 1
+#define SWAP_STD_REV 2
+#define SWAP_ALT_REV 3
 #endif
-- 
cgit v1.2.3


From b8de7788a4b20c702b06402e2e6eed60467e2522 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 6 Aug 2010 14:54:24 +1000
Subject: r600g: fix targetmask to work correctly.

At least this seems to fix the glean maskedClear test.
---
 src/gallium/drivers/r600/r600_state.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b8d50452e6..e43e4afe55 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1179,12 +1179,11 @@ static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 	} else
 		color_control |= (0xcc << 16);
 
-	target_mask |= (pbs->rt[0].colormask);
 	for (i = 0; i < 8; i++) {
 		if (pbs->rt[i].blend_enable) {
 			color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
-			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
+		target_mask |= (pbs->rt[i].colormask << (4 * i));
 	}
 	r = radeon_state_init(rstate, rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 	if (r)
-- 
cgit v1.2.3


From fc47cb9d710c046d34e8238337e009d7b76a3207 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 6 Aug 2010 15:06:25 +1000
Subject: r600g: fixup z format translations.

this enables GL_EXT_packed_depth_stencil. fbo-d24s8 passes
---
 src/gallium/drivers/r600/r600_state.c         | 20 +-------------------
 src/gallium/drivers/r600/r600_state_inlines.h | 24 +++++++++++++++++++++++-
 2 files changed, 24 insertions(+), 20 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e43e4afe55..82145617ca 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -706,22 +706,6 @@ static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
 	return radeon_state_pm4(rstate);
 }
 
-static int r600_db_format(unsigned pformat, unsigned *format)
-{
-	switch (pformat) {
-	case PIPE_FORMAT_Z24X8_UNORM:
-		*format = V_028010_DEPTH_X8_24;
-		return 0;
-	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		*format = V_028010_DEPTH_8_24;
-		return 0;
-	default:
-		*format = V_028010_DEPTH_INVALID;
-		R600_ERR("unsupported %d\n", pformat);
-		return -EINVAL;
-	}
-}
-
 static int r600_db(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
@@ -746,9 +730,7 @@ static int r600_db(struct r600_context *rctx, struct radeon_state *rstate)
 	level = state->zsbuf->level;
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
-	if (r600_db_format(state->zsbuf->texture->format, &format)) {
-		return -EINVAL;
-	}
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
 	rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
 	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
 					S_028010_FORMAT(format);
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index b45089dcc1..4a955da1c0 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -129,6 +129,20 @@ static INLINE uint32_t r600_translate_ds_func(int func)
 	return func;
 }
 
+static uint32_t r600_translate_dbformat(enum pipe_format format)
+{
+	switch (format) {
+	case PIPE_FORMAT_Z16_UNORM:
+		return V_028010_DEPTH_16;
+	case PIPE_FORMAT_Z24X8_UNORM:
+		return V_028010_DEPTH_X8_24;
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_028010_DEPTH_8_24;
+	default:
+		return ~0;
+	}
+}
+
 static uint32_t r600_translate_colorswap(enum pipe_format format)
 {
 	switch (format) {
@@ -168,6 +182,10 @@ static uint32_t r600_translate_colorswap(enum pipe_format format)
 //        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 		return SWAP_STD_REV;
 
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return SWAP_STD;
+
         case PIPE_FORMAT_R10G10B10A2_UNORM:
         case PIPE_FORMAT_R10G10B10X2_SNORM:
         case PIPE_FORMAT_B10G10R10A2_UNORM:
@@ -234,6 +252,10 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 		return V_0280A0_COLOR_10_10_10_2;
 
+	case PIPE_FORMAT_Z24X8_UNORM:
+	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+		return V_0280A0_COLOR_24_8;
+
 		/* 64-bit buffers. */
         case PIPE_FORMAT_R16G16B16A16_UNORM:
         case PIPE_FORMAT_R16G16B16A16_SNORM:
@@ -271,7 +293,7 @@ static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format form
 
 static INLINE boolean r600_is_zs_format_supported(enum pipe_format format)
 {
-	return TRUE;
+	return r600_translate_dbformat(format) != ~0;
 }
 
 static INLINE boolean r600_is_vertex_format_supported(enum pipe_format format)
-- 
cgit v1.2.3


From 0a2a6c75bffc56d8dfde9b8a46c40222825630ea Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 6 Aug 2010 15:21:44 +1000
Subject: r600g: add SRGB support.

This enables GL2.1 and passes glean's texture_srgb test.
---
 src/gallium/drivers/r600/r600_state.c         | 17 +++++++++++++----
 src/gallium/drivers/r600/r600_state_inlines.h |  8 ++++++++
 src/gallium/drivers/r600/r600d.h              |  2 ++
 3 files changed, 23 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 82145617ca..1a8ec48936 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -669,8 +669,9 @@ static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
 	unsigned level = state->cbufs[0]->level;
 	unsigned pitch, slice;
 	unsigned color_info;
-	unsigned format, swap;
+	unsigned format, swap, ntype;
 	int r;
+	const struct util_format_description *desc;
 
 	r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, R600_CB0);
 	if (r)
@@ -688,12 +689,19 @@ static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
 
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = NUM_FORMAT_SRGB;
+
 	format = r600_translate_colorformat(rtex->resource.base.b.format);
 	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+
 	color_info = S_0280A0_FORMAT(format) |
-	  S_0280A0_COMP_SWAP(swap) |
-	  S_0280A0_BLEND_CLAMP(1) |
-	  S_0280A0_SOURCE_FORMAT(1);
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_SOURCE_FORMAT(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
 
 	rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
 	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
@@ -1136,6 +1144,7 @@ static int r600_resource(struct r600_context *rctx, struct radeon_state *rstate,
 			S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
 			S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
 			S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
+		        S_038010_FORCE_DEGAMMA(desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB ? 1 : 0) |
 			S_038010_BASE_LEVEL(view->first_level);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
 			S_038014_LAST_LEVEL(view->last_level) |
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 4a955da1c0..fdc29386ae 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -166,6 +166,12 @@ static uint32_t r600_translate_colorswap(enum pipe_format format)
         case PIPE_FORMAT_B4G4R4X4_UNORM:
 		return SWAP_ALT;
 		/* 32-bit buffers. */
+
+        case PIPE_FORMAT_A8B8G8R8_SRGB:
+		return SWAP_STD_REV;
+        case PIPE_FORMAT_B8G8R8A8_SRGB:
+		return SWAP_ALT;
+
         case PIPE_FORMAT_B8G8R8A8_UNORM:
         case PIPE_FORMAT_B8G8R8X8_UNORM:
 		return SWAP_ALT;
@@ -244,6 +250,8 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
         case PIPE_FORMAT_X8B8G8R8_UNORM:
         case PIPE_FORMAT_R8G8B8X8_UNORM:
         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+        case PIPE_FORMAT_A8B8G8R8_SRGB:
+        case PIPE_FORMAT_B8G8R8A8_SRGB:
 		return V_0280A0_COLOR_8_8_8_8;
 
         case PIPE_FORMAT_R10G10B10A2_UNORM:
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 2d0ede20fa..f9cad93185 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -1174,4 +1174,6 @@
 #define SWAP_ALT 1
 #define SWAP_STD_REV 2
 #define SWAP_ALT_REV 3
+
+#define NUM_FORMAT_SRGB 6
 #endif
-- 
cgit v1.2.3


From 5f6ab5e259de826bb3795d90fdb0235c8997acb9 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 6 Aug 2010 15:29:50 +1000
Subject: r600g: start to fix up multiple targets.

fixup exports from pixel shader for multi-cbs + depth buffer writing.

Still crashes GPU running any of the multi-buffer or depth writing
---
 src/gallium/drivers/r600/r600_context.h |  2 +-
 src/gallium/drivers/r600/r600_shader.c  | 18 +++++++++++--
 src/gallium/drivers/r600/r600_state.c   | 47 +++++++++++++++++++++++----------
 3 files changed, 50 insertions(+), 17 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 78da88fef5..c83949de42 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -94,7 +94,7 @@ struct r600_context_hw_states {
 	struct radeon_state	dsa;
 	struct radeon_state	blend;
 	struct radeon_state	viewport;
-	struct radeon_state	cb0;
+	struct radeon_state	cb[7];
 	struct radeon_state	config;
 	struct radeon_state	cb_cntl;
 	struct radeon_state	db;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index f38aa7b463..d925dcbe4b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -158,7 +158,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
-	unsigned i, tmp;
+	unsigned i, tmp, exports_ps, num_cout;
 	int r;
 
 	r = radeon_state_init(&rpshader->rstate, rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
@@ -174,11 +174,22 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 		}
 		state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
 	}
+
+	exports_ps = 0;
+	num_cout = 0;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			exports_ps |= 1;
+		else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
+			exports_ps |= (1 << (num_cout+1));
+			num_cout++;
+		}
+	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
 							S_0286CC_PERSP_GRADIENT_ENA(1);
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
-	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
+	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
 	rpshader->rstate.bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
 	rpshader->rstate.nbo = 1;
 	rpshader->rstate.placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -431,6 +442,9 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
 				output.array_base = 0;
 				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
+			} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
+				output.array_base = 61;
+				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else {
 				R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
 				r = -EINVAL;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 1a8ec48936..c5e74d1efc 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -660,24 +660,25 @@ static int r600_blend(struct r600_context *rctx, struct radeon_state *rstate)
 	return radeon_state_pm4(rstate);
 }
 
-static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
+static int r600_cb(struct r600_context *rctx, struct radeon_state *rstate, int cb)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct r600_resource_texture *rtex;
 	struct r600_resource *rbuffer;
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level = state->cbufs[0]->level;
+	unsigned level = state->cbufs[cb]->level;
 	unsigned pitch, slice;
 	unsigned color_info;
 	unsigned format, swap, ntype;
 	int r;
 	const struct util_format_description *desc;
+	int id = R600_CB0 + cb;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, R600_CB0);
+	r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, id);
 	if (r)
 		return r;
 
-	rtex = (struct r600_resource_texture*)state->cbufs[0]->texture;
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
 	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -687,7 +688,7 @@ static int r600_cb0(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 3;
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[0]->height / 64 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
 
 	ntype = 0;
 	desc = util_format_description(rtex->resource.base.b.format);
@@ -878,14 +879,20 @@ static int r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
 	struct r600_screen *rscreen = rctx->screen;
-	unsigned db_depth_control, alpha_test_control, alpha_ref;
+	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 	unsigned stencil_ref_mask, stencil_ref_mask_bf;
-	int r;
+	int r, i;
+	struct r600_shader *rshader = &rctx->ps_shader->shader;
 
 	r = radeon_state_init(rstate, rscreen->rw, R600_DSA_TYPE, R600_DSA);
 	if (r)
 		return r;
 
+	db_shader_control = 0x210;
+	for (i = 0; i < rshader->noutput; i++) {
+		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
+			db_shader_control |= 1;
+	}
 	stencil_ref_mask = 0;
 	stencil_ref_mask_bf = 0;
 	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
@@ -933,7 +940,7 @@ static int r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->states[R600_DSA__SPI_FOG_FUNC_BIAS] = 0x00000000;
 	rstate->states[R600_DSA__SPI_FOG_CNTL] = 0x00000000;
 	rstate->states[R600_DSA__DB_DEPTH_CONTROL] = db_depth_control;
-	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
+	rstate->states[R600_DSA__DB_SHADER_CONTROL] = db_shader_control;
 	rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
 	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
@@ -1159,12 +1166,18 @@ static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
-	uint32_t color_control, target_mask;
+	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;	
+	uint32_t color_control, target_mask, shader_mask;
 	int i, r;
 
 	target_mask = 0;
+	shader_mask = 0;
 	color_control = S_028808_PER_MRT_BLEND(1);
 
+	for (i = 0; i < nr_cbufs; i++) {
+		shader_mask |= 0xf << i;
+	}
+
 	if (pbs->logicop_enable) {
 		color_control |= (pbs->logicop_func) << 16;
 	} else
@@ -1175,11 +1188,13 @@ static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 			color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 		}
 		target_mask |= (pbs->rt[i].colormask << (4 * i));
+		
 	}
 	r = radeon_state_init(rstate, rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 	if (r)
 		return r;
-	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
+
+	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
 	rstate->states[R600_CB_CNTL__PA_SC_AA_CONFIG] = 0x00000000;
@@ -1197,6 +1212,7 @@ int r600_context_hw_states(struct r600_context *rctx)
 {
 	unsigned i;
 	int r;
+	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
 
 	/* free previous TODO determine what need to be updated, what
 	 * doesn't
@@ -1210,7 +1226,8 @@ int r600_context_hw_states(struct r600_context *rctx)
 	r600_dsa(rctx, &rctx->hw_states.dsa);
 	r600_blend(rctx, &rctx->hw_states.blend);
 	r600_viewport(rctx, &rctx->hw_states.viewport);
-	r600_cb0(rctx, &rctx->hw_states.cb0);
+	for (i = 0; i < nr_cbufs; i++)
+		r600_cb(rctx, &rctx->hw_states.cb[i], i);
 	r600_db(rctx, &rctx->hw_states.db);
 	r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
 
@@ -1250,9 +1267,11 @@ int r600_context_hw_states(struct r600_context *rctx)
 	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.viewport);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb0);
-	if (r)
-		return r;
+	for (i = 0; i < nr_cbufs; i++) {
+		r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb[i]);
+		if (r)
+			return r;
+	}
 	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.config);
 	if (r)
 		return r;
-- 
cgit v1.2.3


From 6e6103004c9c737297b842a4aff298da920e7c33 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 6 Aug 2010 10:59:27 -0400
Subject: Revert "r600g: don't use dynamic state allocation for states"

This reverts commit 9c949d4a4dd43b7889e13bdf683bcf211f049ced.

Conflicts:

	src/gallium/drivers/r600/r600_context.h
	src/gallium/drivers/r600/r600_draw.c
	src/gallium/drivers/r600/r600_shader.c
	src/gallium/drivers/r600/r600_state.c
---
 src/gallium/drivers/r600/r600_context.c    | 141 +++++++-------
 src/gallium/drivers/r600/r600_context.h    |  29 ++-
 src/gallium/drivers/r600/r600_draw.c       | 104 +++++------
 src/gallium/drivers/r600/r600_shader.c     |  34 ++--
 src/gallium/drivers/r600/r600_state.c      | 283 ++++++++++++++++++-----------
 src/gallium/drivers/r600/radeon.h          |  52 ++----
 src/gallium/targets/dri-r600/Makefile      |   4 +-
 src/gallium/winsys/r600/drm/radeon.c       |  11 ++
 src/gallium/winsys/r600/drm/radeon_ctx.c   | 160 +++++++++++-----
 src/gallium/winsys/r600/drm/radeon_draw.c  |  92 +++++++++-
 src/gallium/winsys/r600/drm/radeon_priv.h  |  29 +++
 src/gallium/winsys/r600/drm/radeon_state.c |  70 ++++++-
 12 files changed, 647 insertions(+), 362 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index f7732d8952..ae1780a1d4 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -48,14 +48,18 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	struct r600_screen *rscreen = rctx->screen;
 	static int dc = 0;
 
-	if (radeon_ctx_pm4(&rctx->ctx))
+	if (radeon_ctx_pm4(rctx->ctx))
 		return;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
 	if (!dc)
-		radeon_ctx_dump_bof(&rctx->ctx, "gallium.bof");
-	radeon_ctx_submit(&rctx->ctx);
+		radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
+#if 1
+	radeon_ctx_submit(rctx->ctx);
+#endif
+	rctx->ctx = radeon_ctx_decref(rctx->ctx);
+	rctx->ctx = radeon_ctx(rscreen->rw);
 	dc++;
 }
 
@@ -216,8 +220,9 @@ static void r600_init_config(struct r600_context *rctx)
 	printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
 	printf("num_es_stack_entries : %d\n", num_es_stack_entries);
 
-	radeon_state_init(&rctx->config, rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
+	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
+
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
 	case CHIP_RV610:
 	case CHIP_RV620:
@@ -226,75 +231,75 @@ static void r600_init_config(struct r600_context *rctx)
 	case CHIP_RV710:
 		break;
 	default:
-		rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 		break;
 	}
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 
-	rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-	rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-	rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-	rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(&rctx->config);
+	rctx->hw_states.config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+	rctx->hw_states.config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+	rctx->hw_states.config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+	rctx->hw_states.config->states[R600_CONFIG__SX_MISC] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+	rctx->hw_states.config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
+	radeon_state_pm4(rctx->hw_states.config);
 }
 
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
@@ -328,7 +333,7 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 
 	r600_init_config(rctx);
 
-	radeon_ctx_init(&rctx->ctx, rscreen->rw);
-	radeon_draw_init(&rctx->draw, rscreen->rw);
+	rctx->ctx = radeon_ctx(rscreen->rw);
+	rctx->draw = radeon_draw(rscreen->rw);
 	return &rctx->context;
 }
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index c83949de42..431f8951b2 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -76,7 +76,7 @@ struct r600_context_state {
 	union pipe_states		state;
 	unsigned			refcount;
 	unsigned			type;
-	struct radeon_state		rstate;
+	struct radeon_state		*rstate;
 	struct r600_shader		shader;
 	struct radeon_bo		*bo;
 };
@@ -89,28 +89,28 @@ struct r600_vertex_element
 };
 
 struct r600_context_hw_states {
-	struct radeon_state	rasterizer;
-	struct radeon_state	scissor;
-	struct radeon_state	dsa;
-	struct radeon_state	blend;
-	struct radeon_state	viewport;
-	struct radeon_state	cb[7];
-	struct radeon_state	config;
-	struct radeon_state	cb_cntl;
-	struct radeon_state	db;
+	struct radeon_state	*rasterizer;
+	struct radeon_state	*scissor;
+	struct radeon_state	*dsa;
+	struct radeon_state	*blend;
+	struct radeon_state	*viewport;
+	struct radeon_state	*cb[7];
+	struct radeon_state	*config;
+	struct radeon_state	*cb_cntl;
+	struct radeon_state	*db;
 	unsigned		ps_nresource;
 	unsigned		ps_nsampler;
-	struct radeon_state	ps_resource[160];
-	struct radeon_state	ps_sampler[16];
+	struct radeon_state	*ps_resource[160];
+	struct radeon_state	*ps_sampler[16];
 };
 
 struct r600_context {
 	struct pipe_context		context;
 	struct r600_screen		*screen;
 	struct radeon			*rw;
-	struct radeon_ctx		ctx;
+	struct radeon_ctx		*ctx;
 	struct blitter_context		*blitter;
-	struct radeon_draw		draw;
+	struct radeon_draw		*draw;
 	/* hw states */
 	struct r600_context_hw_states	hw_states;
 	/* pipe states */
@@ -120,7 +120,6 @@ struct r600_context {
 	unsigned			ps_nsampler_view;
 	unsigned			vs_nsampler_view;
 	unsigned			nvertex_buffer;
-	struct radeon_state		config;
 	struct r600_context_state	*rasterizer;
 	struct r600_context_state	*poly_stipple;
 	struct r600_context_state	*scissor;
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 3a54cee2d9..2420b76318 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -38,8 +38,8 @@
 
 struct r600_draw {
 	struct pipe_context	*ctx;
-	struct radeon_state	draw;
-	struct radeon_state	vgt;
+	struct radeon_state	*draw;
+	struct radeon_state	*vgt;
 	unsigned		mode;
 	unsigned		start;
 	unsigned		count;
@@ -51,7 +51,7 @@ static int r600_draw_common(struct r600_draw *draw)
 {
 	struct r600_context *rctx = r600_context(draw->ctx);
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state vs_resource;
+	struct radeon_state *vs_resource;
 	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
 	u32 vgt_dma_index_type, vgt_draw_initiator;
@@ -88,10 +88,10 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->vs_shader->rstate);
+	r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->ps_shader->rstate);
+	r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
 	if (r)
 		return r;
 
@@ -101,68 +101,68 @@ static int r600_draw_common(struct r600_draw *draw)
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		r = radeon_state_init(&vs_resource, rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
-		if (r)
-			return r;
-		vs_resource.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		vs_resource.nbo = 1;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
+		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
+		if (vs_resource == NULL)
+			return -ENOMEM;
+		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		vs_resource->nbo = 1;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 								S_038008_DATA_FORMAT(format);
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
-		vs_resource.states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
-		vs_resource.placement[0] = RADEON_GEM_DOMAIN_GTT;
-		vs_resource.placement[1] = RADEON_GEM_DOMAIN_GTT;
-		radeon_state_pm4(&vs_resource);
-		r = radeon_draw_set(&rctx->draw, &vs_resource);
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
+		vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
+		vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
+		r = radeon_draw_set_new(rctx->draw, vs_resource);
 		if (r)
 			return r;
 	}
 	/* FIXME start need to change winsys */
-	r = radeon_state_init(&draw->draw, rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
-	if (r)
-		return r;
-	draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
+	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	if (draw->draw == NULL)
+		return -ENOMEM;
+	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+	draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	if (draw->index_buffer) {
-		rbuffer = (struct r600_resource*)draw->index_buffer;
-		draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw.nbo = 1;
+		rbuffer = (struct r600_buffer*)draw->index_buffer;
+		draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw->nbo = 1;
 	}
-	radeon_state_pm4(&draw->draw);
-	r = radeon_draw_set(&rctx->draw, &draw->draw);
+	r = radeon_draw_set_new(rctx->draw, draw->draw);
 	if (r)
 		return r;
-	r = radeon_state_init(&draw->vgt, rscreen->rw, R600_VGT_TYPE, R600_VGT);
-	if (r)
-		return r;
-	draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
-	draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
-	draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
-	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
-	radeon_state_pm4(&draw->vgt);
-	r = radeon_draw_set(&rctx->draw, &draw->vgt);
+	draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
+	if (draw->vgt == NULL)
+		return -ENOMEM;
+	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
+	draw->vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+	draw->vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
+	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+	draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
+	r = radeon_draw_set_new(rctx->draw, draw->vgt);
 	if (r)
 		return r;
 	/* FIXME */
-	r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
+	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
 	if (r == -EBUSY) {
 		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
+		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
 	}
-	return r;
+	if (r)
+		return r;
+	rctx->draw = radeon_draw_duplicate(rctx->draw);
+	return 0;
 }
 
 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index d925dcbe4b..dc8d4cb315 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -130,12 +130,11 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
 	unsigned i, tmp;
-	int r;
 
-	r = radeon_state_init(&rpshader->rstate, rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
-	if (r)
-		return r;
-	state = &rpshader->rstate;
+	rpshader->rstate = radeon_state_decref(rpshader->rstate);
+	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
+	if (state == NULL)
+		return -ENOMEM;
 	for (i = 0; i < 10; i++) {
 		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
 	}
@@ -146,10 +145,11 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	}
 	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
 	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
-	rpshader->rstate.bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate.bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate.nbo = 2;
-	rpshader->rstate.placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate = state;
+	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->nbo = 2;
+	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
@@ -159,12 +159,11 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	struct r600_shader *rshader = &rpshader->shader;
 	struct radeon_state *state;
 	unsigned i, tmp, exports_ps, num_cout;
-	int r;
 
-	r = radeon_state_init(&rpshader->rstate, rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
-	if (r)
-		return r;
-	state = &rpshader->rstate;
+	rpshader->rstate = radeon_state_decref(rpshader->rstate);
+	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
+	if (state == NULL)
+		return -ENOMEM;
 	for (i = 0; i < rshader->ninput; i++) {
 		tmp = S_028644_SEMANTIC(i);
 		tmp |= S_028644_SEL_CENTROID(1);
@@ -190,9 +189,10 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
 	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
-	rpshader->rstate.bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate.nbo = 1;
-	rpshader->rstate.placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate = state;
+	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	rpshader->rstate->nbo = 1;
+	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index c5e74d1efc..e8871cd748 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -277,10 +277,9 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
 	unsigned nconstant = 0, i, type, id;
-	struct radeon_state rstate;
+	struct radeon_state *rstate;
 	struct pipe_transfer *transfer;
 	u32 *ptr;
-	int r;
 
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
@@ -301,16 +300,16 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		if (ptr == NULL)
 			return;
 		for (i = 0; i < nconstant; i++) {
-			r = radeon_state_init(&rstate, rscreen->rw, type, id + i);
-			if (r)
+			rstate = radeon_state(rscreen->rw, type, id + i);
+			if (rstate == NULL)
 				return;
-			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
-			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
-			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
-			rstate.states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
-			if (radeon_state_pm4(&rstate))
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
+			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
+			if (radeon_state_pm4(rstate))
 				return;
-			if (radeon_draw_set(&rctx->draw, &rstate))
+			if (radeon_draw_set_new(rctx->draw, rstate))
 				return;
 		}
 		pipe_buffer_unmap(ctx, buffer, transfer);
@@ -521,6 +520,7 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state *
 		R600_ERR("invalid type %d\n", rstate->type);
 		return NULL;
 	}
+	radeon_state_decref(rstate->rstate);
 	FREE(rstate);
 	return NULL;
 }
@@ -603,17 +603,16 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 	return rstate;
 }
 
-static int r600_blend(struct r600_context *rctx, struct radeon_state *rstate)
+static struct radeon_state *r600_blend(struct r600_context *rctx)
 {
 	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
 	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
-	int r;
-
-	r = radeon_state_init(rstate, rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
-	if (r)
-		return r;
 
+	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
+	if (rstate == NULL)
+		return NULL;
 	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
 	rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
 	rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
@@ -657,27 +656,30 @@ static int r600_blend(struct r600_context *rctx, struct radeon_state *rstate)
 			rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
 	}
 
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static int r600_cb(struct r600_context *rctx, struct radeon_state *rstate, int cb)
+static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct r600_resource_texture *rtex;
 	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 	unsigned level = state->cbufs[cb]->level;
 	unsigned pitch, slice;
 	unsigned color_info;
 	unsigned format, swap, ntype;
-	int r;
 	const struct util_format_description *desc;
 	int id = R600_CB0 + cb;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_CB0_TYPE, id);
-	if (r)
-		return r;
-
+	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, id);
+	if (rstate == NULL)
+		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
 	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -712,25 +714,30 @@ static int r600_cb(struct r600_context *rctx, struct radeon_state *rstate, int c
 	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
 	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
 	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static int r600_db(struct r600_context *rctx, struct radeon_state *rstate)
+static struct radeon_state *r600_db(struct r600_context *rctx)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct r600_resource_texture *rtex;
 	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
 	unsigned level = state->cbufs[0]->level;
 	unsigned pitch, slice, format;
-	int r;
-
-	r = radeon_state_init(rstate, rscreen->rw, R600_DB_TYPE, R600_DB);
-	if (r)
-		return r;
 
 	if (state->zsbuf == NULL)
-		return 0;
+		return NULL;
+
+	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	if (rstate == NULL)
+		return NULL;
+
 	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -747,22 +754,23 @@ static int r600_db(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
 	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
 						S_028000_SLICE_TILE_MAX(slice);
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static int r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
+static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 {
 	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
 	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
 	float offset_units = 0, offset_scale = 0;
 	char depth = 0;
 	unsigned offset_db_fmt_cntl = 0;
-	int r;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
-	if (r)
-		return r;
 	if (fb->zsbuf) {
 		offset_units = state->offset_units;
 		offset_scale = state->offset_scale * 12.0f;
@@ -783,12 +791,15 @@ static int r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstat
 			break;
 		default:
 			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
-			return -EINVAL;
+			return NULL;
 		}
 	}
 	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 
 	rctx->flat_shade = state->flatshade;
+	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
+	if (rstate == NULL)
+		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
@@ -816,21 +827,25 @@ static int r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstat
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static int r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
+static struct radeon_state *r600_scissor(struct r600_context *rctx)
 {
 	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
 	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
 	u32 tl, br;
-	int r;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
-	if (r)
-		return r;
 	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	if (rstate == NULL)
+		return NULL;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
@@ -850,18 +865,22 @@ static int r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static int r600_viewport(struct r600_context *rctx, struct radeon_state *rstate)
+static struct radeon_state *r600_viewport(struct r600_context *rctx)
 {
 	const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
 	struct r600_screen *rscreen = rctx->screen;
-	int r;
+	struct radeon_state *rstate;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
-	if (r)
-		return r;
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	if (rstate == NULL)
+		return NULL;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
@@ -871,22 +890,27 @@ static int r600_viewport(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static int r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
+static struct radeon_state *r600_dsa(struct r600_context *rctx)
 {
 	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
 	struct r600_screen *rscreen = rctx->screen;
 	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 	unsigned stencil_ref_mask, stencil_ref_mask_bf;
-	int r, i;
 	struct r600_shader *rshader = &rctx->ps_shader->shader;
+	struct radeon_state *rstate;
+	int i;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_DSA_TYPE, R600_DSA);
-	if (r)
-		return r;
+	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	if (rstate == NULL)
+		return NULL;
 
 	db_shader_control = 0x210;
 	for (i = 0; i < rshader->noutput; i++) {
@@ -898,8 +922,8 @@ static int r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 		S_028800_ZFUNC(state->depth.func);
-
 	/* set stencil enable */
+
 	if (state->stencil[0].enabled) {
 		db_depth_control |= S_028800_STENCIL_ENABLE(1);
 		db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
@@ -946,7 +970,11 @@ static int r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
 	rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
 	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
 static inline unsigned r600_tex_wrap(unsigned wrap)
@@ -1024,15 +1052,16 @@ static INLINE u32 S_FIXED(float value, u32 frac_bits)
 	return value * (1 << frac_bits);
 }
 
-static int r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_sampler_state *state, unsigned id)
+static struct radeon_state *r600_sampler(struct r600_context *rctx,
+				const struct pipe_sampler_state *state,
+				unsigned id)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	int r;
+	struct radeon_state *rstate;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_PS_SAMPLER_TYPE, id);
-	if (r)
-		return r;
+	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
+	if (rstate == NULL)
+		return NULL;
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
 			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
@@ -1047,7 +1076,11 @@ static int r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
 			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
 static inline unsigned r600_tex_swizzle(unsigned swizzle)
@@ -1097,26 +1130,28 @@ static inline unsigned r600_tex_dim(unsigned dim)
 	}
 }
 
-static int r600_resource(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_sampler_view *view, unsigned id)
+static struct radeon_state *r600_resource(struct r600_context *rctx,
+					const struct pipe_sampler_view *view,
+					unsigned id)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
 	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
 	unsigned format;
-	int r;
 
-	r = radeon_state_init(rstate, rscreen->rw, R600_PS_RESOURCE_TYPE, id);
-	if (r)
-		return r;
 	format = r600_translate_colorformat(view->texture->format);
 	if (format == ~0)
-		return -EINVAL;
+		return NULL;
 	desc = util_format_description(view->texture->format);
 	if (desc == NULL) {
 		R600_ERR("unknow format %d\n", view->texture->format);
-		return -EINVAL;
+		return NULL;
+	}
+	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
+	if (rstate == NULL) {
+		return NULL;
 	}
 	tmp = (struct r600_resource_texture*)view->texture;
 	rbuffer = &tmp->resource;
@@ -1159,16 +1194,21 @@ static int r600_resource(struct r600_context *rctx, struct radeon_state *rstate,
 			S_038014_LAST_ARRAY(0);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
 			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
+static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 {
 	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
 	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;	
 	uint32_t color_control, target_mask, shader_mask;
-	int i, r;
+	int i;
 
 	target_mask = 0;
 	shader_mask = 0;
@@ -1190,10 +1230,7 @@ static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 		target_mask |= (pbs->rt[i].colormask << (4 * i));
 		
 	}
-	r = radeon_state_init(rstate, rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
-	if (r)
-		return r;
-
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1205,7 +1242,11 @@ static int r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
 	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	return radeon_state_pm4(rstate);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
 int r600_context_hw_states(struct r600_context *rctx)
@@ -1217,77 +1258,97 @@ int r600_context_hw_states(struct r600_context *rctx)
 	/* free previous TODO determine what need to be updated, what
 	 * doesn't
 	 */
-	memset(&rctx->hw_states, 0, sizeof(struct r600_context_hw_states));
+	//radeon_state_decref(rctx->hw_states.config);
+	rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
+	rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
+	rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
+	rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
+	rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
+	rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
+	rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
+	for (i = 0; i < 8; i++) {
+		rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
+	}
+	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
+		radeon_state_decref(rctx->hw_states.ps_resource[i]);
+		rctx->hw_states.ps_resource[i] = NULL;
+	}
+	rctx->hw_states.ps_nresource = 0;
+	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
+		radeon_state_decref(rctx->hw_states.ps_sampler[i]);
+		rctx->hw_states.ps_sampler[i] = NULL;
+	}
+	rctx->hw_states.ps_nsampler = 0;
 
 	/* build new states */
-	rctx->hw_states.config = rctx->config;
-	r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
-	r600_scissor(rctx, &rctx->hw_states.scissor);
-	r600_dsa(rctx, &rctx->hw_states.dsa);
-	r600_blend(rctx, &rctx->hw_states.blend);
-	r600_viewport(rctx, &rctx->hw_states.viewport);
-	for (i = 0; i < nr_cbufs; i++)
-		r600_cb(rctx, &rctx->hw_states.cb[i], i);
-	r600_db(rctx, &rctx->hw_states.db);
-	r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
+	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
+	rctx->hw_states.scissor = r600_scissor(rctx);
+	rctx->hw_states.dsa = r600_dsa(rctx);
+	rctx->hw_states.blend = r600_blend(rctx);
+	rctx->hw_states.viewport = r600_viewport(rctx);
+	for (i = 0; i < nr_cbufs; i++) {
+		rctx->hw_states.cb[i] = r600_cb(rctx, i);
+	}
+	rctx->hw_states.db = r600_db(rctx);
+	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
 
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			r600_sampler(rctx, &rctx->hw_states.ps_sampler[i],
-					&rctx->ps_sampler[i]->state.sampler,
-					R600_PS_SAMPLER + i);
+			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
+							&rctx->ps_sampler[i]->state.sampler,
+							R600_PS_SAMPLER + i);
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			r600_resource(rctx, &rctx->hw_states.ps_resource[i],
-					&rctx->ps_sampler_view[i]->state.sampler_view,
-					R600_PS_RESOURCE + i);
+			rctx->hw_states.ps_resource[i] = r600_resource(rctx,
+							&rctx->ps_sampler_view[i]->state.sampler_view,
+							R600_PS_RESOURCE + i);
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
 
 	/* bind states */
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.db);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.rasterizer);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.scissor);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.dsa);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.blend);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.viewport);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
 	if (r)
 		return r;
 	for (i = 0; i < nr_cbufs; i++) {
-		r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb[i]);
+		r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
 		if (r)
 			return r;
 	}
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.config);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
 	if (r)
 		return r;
-	r = radeon_draw_set(&rctx->draw, &rctx->hw_states.cb_cntl);
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
 	if (r)
 		return r;
 	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
-		if (rctx->hw_states.ps_resource[i].valid) {
-			r = radeon_draw_set(&rctx->draw, &rctx->hw_states.ps_resource[i]);
+		if (rctx->hw_states.ps_resource[i]) {
+			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
 			if (r)
 				return r;
 		}
 	}
 	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
-		if (rctx->hw_states.ps_sampler[i].valid) {
-			r = radeon_draw_set(&rctx->draw, &rctx->hw_states.ps_sampler[i]);
+		if (rctx->hw_states.ps_sampler[i]) {
+			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
 			if (r)
 				return r;
 		}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 709ef8a85a..3a8405f9b4 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -103,17 +103,17 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
  */
 struct radeon_state {
 	struct radeon			*radeon;
-	unsigned			valid;
+	unsigned			refcount;
 	unsigned			type;
 	unsigned			id;
 	unsigned			nstates;
-	u32				states[64];
+	u32				*states;
 	unsigned			npm4;
 	unsigned			cpm4;
 	u32				pm4_crc;
-	u32				pm4[128];
+	u32				*pm4;
 	u32				nimmd;
-	u32				immd[64];
+	u32				*immd;
 	unsigned			nbo;
 	struct radeon_bo		*bo[4];
 	unsigned			nreloc;
@@ -123,51 +123,35 @@ struct radeon_state {
 	unsigned			bo_dirty[4];
 };
 
-int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 type, u32 id);
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
+struct radeon_state *radeon_state_incref(struct radeon_state *state);
+struct radeon_state *radeon_state_decref(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
 
 /*
  * draw functions
  */
 struct radeon_draw {
+	unsigned			refcount;
 	struct radeon			*radeon;
 	unsigned			nstate;
-	struct radeon_state		state[1273];
+	struct radeon_state		**state;
 	unsigned			cpm4;
 };
 
-int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
+struct radeon_draw *radeon_draw(struct radeon *radeon);
+struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw);
+struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw);
+struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw);
 int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
+int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
 int radeon_draw_check(struct radeon_draw *draw);
 
-/*
- * Context
- */
-#pragma pack(1)
-struct radeon_cs_reloc {
-	uint32_t	handle;
-	uint32_t	read_domain;
-	uint32_t	write_domain;
-	uint32_t	flags;
-};
-#pragma pack()
-
-struct radeon_ctx {
-	struct radeon			*radeon;
-	u32				*pm4;
-	u32				cpm4;
-	u32				draw_cpm4;
-	unsigned			id;
-	unsigned			nreloc;
-	struct radeon_cs_reloc		reloc[2048];
-	unsigned			nbo;
-	struct radeon_bo		*bo[2048];
-	unsigned			ndraw;
-	struct radeon_draw		draw[128];
-};
-
-int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon);
+struct radeon_ctx *radeon_ctx(struct radeon *radeon);
+struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
+struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
 int radeon_ctx_pm4(struct radeon_ctx *ctx);
 int radeon_ctx_submit(struct radeon_ctx *ctx);
 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
diff --git a/src/gallium/targets/dri-r600/Makefile b/src/gallium/targets/dri-r600/Makefile
index 9c8b4ab252..932303d194 100644
--- a/src/gallium/targets/dri-r600/Makefile
+++ b/src/gallium/targets/dri-r600/Makefile
@@ -4,12 +4,12 @@ include $(TOP)/configs/current
 LIBNAME = r600_dri.so
 
 PIPE_DRIVERS = \
-	$(TOP)/src/gallium/drivers/r600/libr600.a \
 	$(TOP)/src/gallium/state_trackers/dri/drm/libdridrm.a \
 	$(TOP)/src/gallium/winsys/r600/drm/libr600winsys.a \
 	$(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \
 	$(TOP)/src/gallium/drivers/trace/libtrace.a \
-	$(TOP)/src/gallium/drivers/rbug/librbug.a
+	$(TOP)/src/gallium/drivers/rbug/librbug.a \
+	$(TOP)/src/gallium/drivers/r600/libr600.a
 
 C_SOURCES = \
 	target.c \
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 24d821d5cf..7e65669806 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -43,6 +43,16 @@ static int radeon_get_device(struct radeon *radeon)
 	return r;
 }
 
+/* symbol missing drove me crazy hack to get symbol exported */
+static void fake(void)
+{
+	struct radeon_ctx *ctx;
+	struct radeon_draw *draw;
+
+	ctx = radeon_ctx(NULL);
+	draw = radeon_draw(NULL);
+}
+
 struct radeon *radeon_new(int fd, unsigned device)
 {
 	struct radeon *radeon;
@@ -50,6 +60,7 @@ struct radeon *radeon_new(int fd, unsigned device)
 
 	radeon = calloc(1, sizeof(*radeon));
 	if (radeon == NULL) {
+		fake();
 		return NULL;
 	}
 	radeon->fd = fd;
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index af270d5d20..6b0eba0b28 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -32,8 +32,13 @@
 
 int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo)
 {
-	if (ctx->nbo >= 2048)
-		return -EBUSY;
+	void *ptr;
+
+	ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1));
+	if (ptr == NULL) {
+		return -ENOMEM;
+	}
+	ctx->bo = ptr;
 	ctx->bo[ctx->nbo] = bo;
 	ctx->nbo++;
 	return 0;
@@ -71,26 +76,49 @@ void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *place
 	}
 }
 
-static void radeon_ctx_clear(struct radeon_ctx *ctx)
+struct radeon_ctx *radeon_ctx(struct radeon *radeon)
 {
-	ctx->draw_cpm4 = 0;
-	ctx->cpm4 = 0;
-	ctx->ndraw = 0;
-	ctx->nbo = 0;
-	ctx->nreloc = 0;
+	struct radeon_ctx *ctx;
+
+	if (radeon == NULL)
+		return NULL;
+	ctx = calloc(1, sizeof(*ctx));
+	if (ctx == NULL)
+		return NULL;
+	ctx->radeon = radeon_incref(radeon);
+	return ctx;
 }
 
-int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon)
+struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx)
 {
-	memset(ctx, 0, sizeof(struct radeon_ctx));
-	ctx->radeon = radeon_incref(radeon);
-	radeon_ctx_clear(ctx);
+	ctx->refcount++;
+	return ctx;
+}
+
+struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
+{
+	unsigned i;
+
+	if (ctx == NULL)
+		return NULL;
+	if (--ctx->refcount > 0) {
+		return NULL;
+	}
+
+	for (i = 0; i < ctx->ndraw; i++) {
+		ctx->draw[i] = radeon_draw_decref(ctx->draw[i]);
+	}
+	for (i = 0; i < ctx->nbo; i++) {
+		ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
+	}
+	ctx->radeon = radeon_decref(ctx->radeon);
+	free(ctx->draw);
+	free(ctx->bo);
 	free(ctx->pm4);
-	ctx->cpm4 = 0;
-	ctx->pm4 = malloc(64 * 1024);
-	if (ctx->pm4 == NULL)
-		return -ENOMEM;
-	return 0;
+	free(ctx->reloc);
+	memset(ctx, 0, sizeof(*ctx));
+	free(ctx);
+	return NULL;
 }
 
 static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
@@ -115,6 +143,7 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
 	return 0;
 }
 
+
 int radeon_ctx_submit(struct radeon_ctx *ctx)
 {
 	struct drm_radeon_cs drmib;
@@ -141,7 +170,6 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
 	r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
 				sizeof(struct drm_radeon_cs));
 #endif
-	radeon_ctx_clear(ctx);
 	return r;
 }
 
@@ -149,6 +177,7 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			unsigned id, unsigned *placement)
 {
 	unsigned i;
+	struct radeon_cs_reloc *ptr;
 
 	for (i = 0; i < ctx->nreloc; i++) {
 		if (ctx->reloc[i].handle == bo->handle) {
@@ -156,12 +185,14 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			return 0;
 		}
 	}
-	if (ctx->nreloc >= 2048)
-		return -EINVAL;
-	ctx->reloc[ctx->nreloc].handle = bo->handle;
-	ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1];
-	ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1];
-	ctx->reloc[ctx->nreloc].flags = 0;
+	ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1));
+	if (ptr == NULL)
+		return -ENOMEM;
+	ctx->reloc = ptr;
+	ptr[ctx->nreloc].handle = bo->handle;
+	ptr[ctx->nreloc].read_domain = placement[0] | placement [1];
+	ptr[ctx->nreloc].write_domain = placement[0] | placement [1];
+	ptr[ctx->nreloc].flags = 0;
 	ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
 	ctx->nreloc++;
 	return 0;
@@ -190,13 +221,21 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
 	return 0;
 }
 
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
+int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
 {
-	unsigned cpm4, i;
+	struct radeon_draw *pdraw = NULL;
+	struct radeon_draw **ndraw;
+	struct radeon_state *nstate, *ostate;
+	unsigned cpm4, i, cstate;
+	void *tmp;
 	int r = 0;
 
+	ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1));
+	if (ndraw == NULL)
+		return -ENOMEM;
+	ctx->draw = ndraw;
 	for (i = 0; i < draw->nstate; i++) {
-		r = radeon_ctx_state_bo(ctx, &draw->state[i]);
+		r = radeon_ctx_state_bo(ctx, draw->state[i]);
 		if (r)
 			return r;
 	}
@@ -208,48 +247,69 @@ int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
 			__func__, draw->cpm4, RADEON_CTX_MAX_PM4);
 		return -EINVAL;
 	}
-	ctx->draw[ctx->ndraw] = *draw;
-	for (i = 0, cpm4 = 0; i < draw->nstate - 1; i++) {
-		ctx->draw[ctx->ndraw].state[i].valid &= ~2;
-		if (ctx->draw[ctx->ndraw].state[i].valid) {
-			if (ctx->ndraw > 1 && ctx->draw[ctx->ndraw - 1].state[i].valid) {
-				if (ctx->draw[ctx->ndraw - 1].state[i].pm4_crc == draw->state[i].pm4_crc)
-					continue;
+	tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*));
+	if (tmp == NULL)
+		return -ENOMEM;
+	ctx->state = tmp;
+	pdraw = ctx->cdraw;
+	for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) {
+		nstate = draw->state[i];
+		if (nstate) {
+			if (pdraw && pdraw->state[i]) {
+				ostate = pdraw->state[i];
+				if (ostate->pm4_crc != nstate->pm4_crc) {
+					ctx->state[cstate++] = nstate;
+					cpm4 += nstate->cpm4;
+				}
+			} else {
+				ctx->state[cstate++] = nstate;
+				cpm4 += nstate->cpm4;
 			}
-			ctx->draw[ctx->ndraw].state[i].valid |= 2;
-			cpm4 += ctx->draw[ctx->ndraw].state[i].cpm4;
 		}
 	}
 	/* The last state is the draw state always add it */
-	if (!draw->state[i].valid) {
+	if (draw->state[i] == NULL) {
 		fprintf(stderr, "%s no draw command\n", __func__);
 		return -EINVAL;
 	}
-	ctx->draw[ctx->ndraw].state[i].valid |= 2;
-	cpm4 += ctx->draw[ctx->ndraw].state[i].cpm4;
+	ctx->state[cstate++] = draw->state[i];
+	cpm4 += draw->state[i]->cpm4;
 	if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) {
 		/* need to flush */
 		return -EBUSY;
 	}
 	ctx->draw_cpm4 += cpm4;
-	ctx->ndraw++;
+	ctx->nstate = cstate;
+	ctx->draw[ctx->ndraw++] = draw;
+	ctx->cdraw = draw;
 	return 0;
 }
 
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
+{
+	int r;
+
+	radeon_draw_incref(draw);
+	r = radeon_ctx_set_draw_new(ctx, draw);
+	if (r)
+		radeon_draw_decref(draw);
+	return r;
+}
+
 int radeon_ctx_pm4(struct radeon_ctx *ctx)
 {
-	unsigned i, j, c;
+	unsigned i;
 	int r;
 
-	for (i = 0, c = 0, ctx->id = 0; i < ctx->ndraw; i++) {
-		for (j = 0; j < ctx->draw[i].nstate; j++) {
-			if (ctx->draw[i].state[j].valid & 2) {
-				r = radeon_ctx_state_schedule(ctx, &ctx->draw[i].state[j]);
-				if (r)
-					return r;
-				c += ctx->draw[i].state[j].cpm4;
-			}
-		}
+	free(ctx->pm4);
+	ctx->cpm4 = 0;
+	ctx->pm4 = malloc(ctx->draw_cpm4 * 4);
+	if (ctx->pm4 == NULL)
+		return -EINVAL;
+	for (i = 0, ctx->id = 0; i < ctx->nstate; i++) {
+		r = radeon_ctx_state_schedule(ctx, ctx->state[i]);
+		if (r)
+			return r;
 	}
 	if (ctx->id != ctx->draw_cpm4) {
 		fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c
index 53699eb0b1..4413ed79fb 100644
--- a/src/gallium/winsys/r600/drm/radeon_draw.c
+++ b/src/gallium/winsys/r600/drm/radeon_draw.c
@@ -31,33 +31,111 @@
 /*
  * draw functions
  */
-int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon)
+struct radeon_draw *radeon_draw(struct radeon *radeon)
 {
-	memset(draw, 0, sizeof(struct radeon_draw));
+	struct radeon_draw *draw;
+
+	draw = calloc(1, sizeof(*draw));
+	if (draw == NULL)
+		return NULL;
 	draw->nstate = radeon->nstate;
 	draw->radeon = radeon;
-	return 0;
+	draw->refcount = 1;
+	draw->state = calloc(1, sizeof(void*) * draw->nstate);
+	if (draw->state == NULL) {
+		free(draw);
+		return NULL;
+	}
+	return draw;
 }
 
-int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state)
+struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw)
+{
+	draw->refcount++;
+	return draw;
+}
+
+struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw)
+{
+	unsigned i;
+
+	if (draw == NULL)
+		return NULL;
+	if (--draw->refcount > 0)
+		return NULL;
+	for (i = 0; i < draw->nstate; i++) {
+		draw->state[i] = radeon_state_decref(draw->state[i]);
+	}
+	free(draw->state);
+	memset(draw, 0, sizeof(*draw));
+	free(draw);
+	return NULL;
+}
+
+int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
 {
 	if (state == NULL)
 		return 0;
 	if (state->type >= draw->radeon->ntype)
 		return -EINVAL;
-	draw->state[state->id] = *state;
+	draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
+	draw->state[state->id] = state;
 	return 0;
 }
 
+int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state)
+{
+	if (state == NULL)
+		return 0;
+	radeon_state_incref(state);
+	return radeon_draw_set_new(draw, state);
+}
+
 int radeon_draw_check(struct radeon_draw *draw)
 {
 	unsigned i;
 	int r;
 
+	r = radeon_draw_pm4(draw);
+	if (r)
+		return r;
 	for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
-		if (draw->state[i].valid) {
-			draw->cpm4 += draw->state[i].cpm4;
+		if (draw->state[i]) {
+			draw->cpm4 += draw->state[i]->cpm4;
 		}
 	}
 	return 0;
 }
+
+struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw)
+{
+	struct radeon_draw *ndraw;
+	unsigned i;
+
+	if (draw == NULL)
+		return NULL;
+	ndraw = radeon_draw(draw->radeon);
+	if (ndraw == NULL) {
+		return NULL;
+	}
+	for (i = 0; i < draw->nstate; i++) {
+		if (radeon_draw_set(ndraw, draw->state[i])) {
+			radeon_draw_decref(ndraw);
+			return NULL;
+		}
+	}
+	return ndraw;
+}
+
+int radeon_draw_pm4(struct radeon_draw *draw)
+{
+	unsigned i;
+	int r;
+
+	for (i = 0; i < draw->nstate; i++) {
+		r = radeon_state_pm4(draw->state[i]);
+		if (r)
+			return r;
+	}
+	return 0;
+}
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 80392cda96..b91421f438 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -24,6 +24,7 @@
 #include "radeon.h"
 
 struct radeon;
+struct radeon_ctx;
 
 /*
  * radeon functions
@@ -70,6 +71,34 @@ extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
 /*
  * radeon context functions
  */
+#pragma pack(1)
+struct radeon_cs_reloc {
+	uint32_t	handle;
+	uint32_t	read_domain;
+	uint32_t	write_domain;
+	uint32_t	flags;
+};
+#pragma pack()
+
+struct radeon_ctx {
+	int				refcount;
+	struct radeon			*radeon;
+	u32				*pm4;
+	u32				cpm4;
+	u32				draw_cpm4;
+	unsigned			id;
+	unsigned			next_id;
+	unsigned			nreloc;
+	struct radeon_cs_reloc		*reloc;
+	unsigned			nbo;
+	struct radeon_bo		**bo;
+	unsigned			ndraw;
+	struct radeon_draw		*cdraw;
+	struct radeon_draw		**draw;
+	unsigned			nstate;
+	struct radeon_state		**state;
+};
+
 int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
 struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
 void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index d7cd1d7a94..308288557a 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -32,23 +32,82 @@
 /*
  * state core functions
  */
-int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 type, u32 id)
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
 {
+	struct radeon_state *state;
+
 	if (type > radeon->ntype) {
 		fprintf(stderr, "%s invalid type %d\n", __func__, type);
-		return -EINVAL;
+		return NULL;
 	}
 	if (id > radeon->nstate) {
 		fprintf(stderr, "%s invalid state id %d\n", __func__, id);
-		return -EINVAL;
+		return NULL;
 	}
-	memset(state, 0, sizeof(struct radeon_state));
+	state = calloc(1, sizeof(*state));
+	if (state == NULL)
+		return NULL;
 	state->radeon = radeon;
 	state->type = type;
 	state->id = id;
+	state->refcount = 1;
 	state->npm4 = radeon->type[type].npm4;
 	state->nstates = radeon->type[type].nstates;
-	return 0;
+	state->states = calloc(1, state->nstates * 4);
+	state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
+	if (state->states == NULL || state->pm4 == NULL) {
+		radeon_state_decref(state);
+		return NULL;
+	}
+	return state;
+}
+
+struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
+{
+	struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
+	unsigned i;
+
+	if (state == NULL)
+		return NULL;
+	nstate->cpm4 = state->cpm4;
+	nstate->nbo = state->nbo;
+	nstate->nreloc = state->nreloc;
+	memcpy(nstate->states, state->states, state->nstates * 4);
+	memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
+	memcpy(nstate->placement, state->placement, 8 * 4);
+	memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
+	memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
+	memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
+	for (i = 0; i < state->nbo; i++) {
+		nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]);
+	}
+	return nstate;
+}
+
+struct radeon_state *radeon_state_incref(struct radeon_state *state)
+{
+	state->refcount++;
+	return state;
+}
+
+struct radeon_state *radeon_state_decref(struct radeon_state *state)
+{
+	unsigned i;
+
+	if (state == NULL)
+		return NULL;
+	if (--state->refcount > 0) {
+		return NULL;
+	}
+	for (i = 0; i < state->nbo; i++) {
+		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
+	}
+	free(state->immd);
+	free(state->states);
+	free(state->pm4);
+	memset(state, 0, sizeof(*state));
+	free(state);
+	return NULL;
 }
 
 int radeon_state_replace_always(struct radeon_state *ostate,
@@ -97,7 +156,6 @@ int radeon_state_pm4(struct radeon_state *state)
 		return r;
 	}
 	state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
-	state->valid = 1;
 	return 0;
 }
 
-- 
cgit v1.2.3


From 27041d7cb3faeaed483538a228573466363ec1c7 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 6 Aug 2010 11:28:33 -0400
Subject: r600g: fix color format, indentation, defines

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_state.c         |   2 +-
 src/gallium/drivers/r600/r600_state_inlines.h | 161 +++++++++++++-------------
 src/gallium/drivers/r600/r600d.h              |  19 +--
 3 files changed, 93 insertions(+), 89 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e8871cd748..deb9bf3395 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -695,7 +695,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	ntype = 0;
 	desc = util_format_description(rtex->resource.base.b.format);
 	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = NUM_FORMAT_SRGB;
+		ntype = V_0280A0_NUMBER_SRGB;
 
 	format = r600_translate_colorformat(rtex->resource.base.b.format);
 	swap = r600_translate_colorswap(rtex->resource.base.b.format);
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index fdc29386ae..8271ad19fb 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -147,117 +147,117 @@ static uint32_t r600_translate_colorswap(enum pipe_format format)
 {
 	switch (format) {
 		/* 8-bit buffers. */
-        case PIPE_FORMAT_A8_UNORM:
-        case PIPE_FORMAT_I8_UNORM:
-        case PIPE_FORMAT_L8_UNORM:
-        case PIPE_FORMAT_R8_UNORM:
-        case PIPE_FORMAT_R8_SNORM:
-		return SWAP_STD;
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
+		return V_0280A0_SWAP_STD;
 
 		/* 16-bit buffers. */
-        case PIPE_FORMAT_B5G6R5_UNORM:
-		return SWAP_STD_REV;
+	case PIPE_FORMAT_B5G6R5_UNORM:
+		return V_0280A0_SWAP_STD_REV;
 
-        case PIPE_FORMAT_B5G5R5A1_UNORM:
-        case PIPE_FORMAT_B5G5R5X1_UNORM:
-		return SWAP_ALT;
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
+		return V_0280A0_SWAP_ALT;
 
-        case PIPE_FORMAT_B4G4R4A4_UNORM:
-        case PIPE_FORMAT_B4G4R4X4_UNORM:
-		return SWAP_ALT;
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
+		return V_0280A0_SWAP_ALT;
 		/* 32-bit buffers. */
 
-        case PIPE_FORMAT_A8B8G8R8_SRGB:
-		return SWAP_STD_REV;
-        case PIPE_FORMAT_B8G8R8A8_SRGB:
-		return SWAP_ALT;
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+		return V_0280A0_SWAP_STD_REV;
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+		return V_0280A0_SWAP_ALT;
 
-        case PIPE_FORMAT_B8G8R8A8_UNORM:
-        case PIPE_FORMAT_B8G8R8X8_UNORM:
-		return SWAP_ALT;
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+		return V_0280A0_SWAP_ALT;
 
-        case PIPE_FORMAT_A8R8G8B8_UNORM:
-        case PIPE_FORMAT_X8R8G8B8_UNORM:
-		return SWAP_ALT_REV;
-        case PIPE_FORMAT_R8G8B8A8_SNORM:
-        case PIPE_FORMAT_R8G8B8X8_UNORM:
-		return SWAP_STD;
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
+		return V_0280A0_SWAP_ALT_REV;
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+		return V_0280A0_SWAP_STD;
 
-        case PIPE_FORMAT_A8B8G8R8_UNORM:
-        case PIPE_FORMAT_X8B8G8R8_UNORM:
-//        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
-		return SWAP_STD_REV;
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+		//        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+		return V_0280A0_SWAP_STD_REV;
 
 	case PIPE_FORMAT_Z24X8_UNORM:
 	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return SWAP_STD;
+		return V_0280A0_SWAP_STD;
 
-        case PIPE_FORMAT_R10G10B10A2_UNORM:
-        case PIPE_FORMAT_R10G10B10X2_SNORM:
-        case PIPE_FORMAT_B10G10R10A2_UNORM:
-        case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
-		return SWAP_STD_REV;
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+		return V_0280A0_SWAP_STD_REV;
 
 		/* 64-bit buffers. */
-        case PIPE_FORMAT_R16G16B16A16_UNORM:
-        case PIPE_FORMAT_R16G16B16A16_SNORM:
-//		return V_0280A0_COLOR_16_16_16_16;
-        case PIPE_FORMAT_R16G16B16A16_FLOAT:
-//		return V_0280A0_COLOR_16_16_16_16_FLOAT;
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
+		//		return V_0280A0_COLOR_16_16_16_16;
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
+		//		return V_0280A0_COLOR_16_16_16_16_FLOAT;
 
 		/* 128-bit buffers. */
-        case PIPE_FORMAT_R32G32B32A32_FLOAT:
-//		return V_0280A0_COLOR_32_32_32_32_FLOAT;
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
+		//		return V_0280A0_COLOR_32_32_32_32_FLOAT;
 		return 0;
 	default:
 		R600_ERR("unsupported colorswap format %d\n", format);
 		return ~0;
 	}
 	return ~0;
-
 }
 
 static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 {
 	switch (format) {
 		/* 8-bit buffers. */
-        case PIPE_FORMAT_A8_UNORM:
-        case PIPE_FORMAT_I8_UNORM:
-        case PIPE_FORMAT_L8_UNORM:
-        case PIPE_FORMAT_R8_UNORM:
-        case PIPE_FORMAT_R8_SNORM:
+	case PIPE_FORMAT_A8_UNORM:
+	case PIPE_FORMAT_I8_UNORM:
+	case PIPE_FORMAT_L8_UNORM:
+	case PIPE_FORMAT_R8_UNORM:
+	case PIPE_FORMAT_R8_SNORM:
 		return V_0280A0_COLOR_8;
 
 		/* 16-bit buffers. */
-        case PIPE_FORMAT_B5G6R5_UNORM:
+	case PIPE_FORMAT_B5G6R5_UNORM:
 		return V_0280A0_COLOR_5_6_5;
 
-        case PIPE_FORMAT_B5G5R5A1_UNORM:
-        case PIPE_FORMAT_B5G5R5X1_UNORM:
+	case PIPE_FORMAT_B5G5R5A1_UNORM:
+	case PIPE_FORMAT_B5G5R5X1_UNORM:
 		return V_0280A0_COLOR_1_5_5_5;
 
-        case PIPE_FORMAT_B4G4R4A4_UNORM:
-        case PIPE_FORMAT_B4G4R4X4_UNORM:
+	case PIPE_FORMAT_B4G4R4A4_UNORM:
+	case PIPE_FORMAT_B4G4R4X4_UNORM:
 		return V_0280A0_COLOR_4_4_4_4;
 
 		/* 32-bit buffers. */
-        case PIPE_FORMAT_B8G8R8A8_UNORM:
-        case PIPE_FORMAT_B8G8R8X8_UNORM:
-        case PIPE_FORMAT_A8R8G8B8_UNORM:
-        case PIPE_FORMAT_X8R8G8B8_UNORM:
-        case PIPE_FORMAT_A8B8G8R8_UNORM:
-        case PIPE_FORMAT_R8G8B8A8_SNORM:
-        case PIPE_FORMAT_X8B8G8R8_UNORM:
-        case PIPE_FORMAT_R8G8B8X8_UNORM:
-        case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
-        case PIPE_FORMAT_A8B8G8R8_SRGB:
-        case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_A8B8G8R8_SRGB:
+	case PIPE_FORMAT_A8B8G8R8_UNORM:
+	case PIPE_FORMAT_A8R8G8B8_UNORM:
+	case PIPE_FORMAT_B8G8R8A8_SRGB:
+	case PIPE_FORMAT_B8G8R8A8_UNORM:
+	case PIPE_FORMAT_B8G8R8X8_UNORM:
+	case PIPE_FORMAT_R8G8B8A8_SNORM:
+	case PIPE_FORMAT_R8G8B8A8_UNORM:
+	case PIPE_FORMAT_R8G8B8X8_UNORM:
+	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
+	case PIPE_FORMAT_X8B8G8R8_UNORM:
+	case PIPE_FORMAT_X8R8G8B8_UNORM:
 		return V_0280A0_COLOR_8_8_8_8;
 
-        case PIPE_FORMAT_R10G10B10A2_UNORM:
-        case PIPE_FORMAT_R10G10B10X2_SNORM:
-        case PIPE_FORMAT_B10G10R10A2_UNORM:
-        case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
+	case PIPE_FORMAT_R10G10B10A2_UNORM:
+	case PIPE_FORMAT_R10G10B10X2_SNORM:
+	case PIPE_FORMAT_B10G10R10A2_UNORM:
+	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 		return V_0280A0_COLOR_10_10_10_2;
 
 	case PIPE_FORMAT_Z24X8_UNORM:
@@ -265,25 +265,24 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 		return V_0280A0_COLOR_24_8;
 
 		/* 64-bit buffers. */
-        case PIPE_FORMAT_R16G16B16A16_UNORM:
-        case PIPE_FORMAT_R16G16B16A16_SNORM:
+	case PIPE_FORMAT_R16G16B16A16_UNORM:
+	case PIPE_FORMAT_R16G16B16A16_SNORM:
 		return V_0280A0_COLOR_16_16_16_16;
-        case PIPE_FORMAT_R16G16B16A16_FLOAT:
+	case PIPE_FORMAT_R16G16B16A16_FLOAT:
 		return V_0280A0_COLOR_16_16_16_16_FLOAT;
-        case PIPE_FORMAT_R32G32_FLOAT:
+	case PIPE_FORMAT_R32G32_FLOAT:
 		return V_0280A0_COLOR_32_32_FLOAT;
 
 		/* 128-bit buffers. */
-        case PIPE_FORMAT_R32G32B32_FLOAT:
-        case PIPE_FORMAT_R32G32B32A32_FLOAT:
+	case PIPE_FORMAT_R32G32B32_FLOAT:
+	case PIPE_FORMAT_R32G32B32A32_FLOAT:
 		return V_0280A0_COLOR_32_32_32_32_FLOAT;
 
 		/* YUV buffers. */
-        case PIPE_FORMAT_UYVY:
-//		return R300_COLOR_FORMAT_YVYU;
-        case PIPE_FORMAT_YUYV:
-//		return R300_COLOR_FORMAT_VYUY;
-        default:
+	case PIPE_FORMAT_UYVY:
+	case PIPE_FORMAT_YUYV:
+	default:
+		R600_ERR("unsupported color format %d\n", format);
 		return ~0; /* Unsupported. */
 	}
 }
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index f9cad93185..fb71b1e5d1 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -209,12 +209,24 @@
 #define   S_0280A0_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
 #define   G_0280A0_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
 #define   C_0280A0_NUMBER_TYPE                         0xFFFF8FFF
+#define     V_0280A0_NUMBER_UNORM                      0x00000000
+#define     V_0280A0_NUMBER_SNORM                      0x00000001
+#define     V_0280A0_NUMBER_USCALED                    0x00000002
+#define     V_0280A0_NUMBER_SSCALED                    0x00000003
+#define     V_0280A0_NUMBER_UINT                       0x00000004
+#define     V_0280A0_NUMBER_SINT                       0x00000005
+#define     V_0280A0_NUMBER_SRGB                       0x00000006
+#define     V_0280A0_NUMBER_FLOAT                      0x00000007
 #define   S_0280A0_READ_SIZE(x)                        (((x) & 0x1) << 15)
 #define   G_0280A0_READ_SIZE(x)                        (((x) >> 15) & 0x1)
 #define   C_0280A0_READ_SIZE                           0xFFFF7FFF
 #define   S_0280A0_COMP_SWAP(x)                        (((x) & 0x3) << 16)
 #define   G_0280A0_COMP_SWAP(x)                        (((x) >> 16) & 0x3)
 #define   C_0280A0_COMP_SWAP                           0xFFFCFFFF
+#define     V_0280A0_SWAP_STD                          0x00000000
+#define     V_0280A0_SWAP_ALT                          0x00000001
+#define     V_0280A0_SWAP_STD_REV                      0x00000002
+#define     V_0280A0_SWAP_ALT_REV                      0x00000003
 #define   S_0280A0_TILE_MODE(x)                        (((x) & 0x3) << 18)
 #define   G_0280A0_TILE_MODE(x)                        (((x) >> 18) & 0x3)
 #define   C_0280A0_TILE_MODE                           0xFFF3FFFF
@@ -1169,11 +1181,4 @@
 #define   G_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) >> 14) & 0x1)
 #define   C_0286D4_PNT_SPRITE_TOP_1                    0xFFFFBFFF
 
-/* temporary swap */
-#define SWAP_STD 0
-#define SWAP_ALT 1
-#define SWAP_STD_REV 2
-#define SWAP_ALT_REV 3
-
-#define NUM_FORMAT_SRGB 6
 #endif
-- 
cgit v1.2.3


From c3ad060488ffd98f1c6dc9127b46324c5201f434 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 6 Aug 2010 16:10:25 -0400
Subject: r600g: finish multi target rendering support

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.c   |  6 +-
 src/gallium/drivers/r600/r600_shader.c    | 52 ++++++++++-------
 src/gallium/drivers/r600/r600_shader.h    |  9 +++
 src/gallium/drivers/r600/r600_state.c     |  3 +-
 src/gallium/drivers/r600/radeon.h         | 30 +++++++---
 src/gallium/winsys/r600/drm/r600_states.h | 96 +++++++++++++++++++++++++++++--
 6 files changed, 158 insertions(+), 38 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index ae1780a1d4..29dc93bae6 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -47,14 +47,16 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_screen *rscreen = rctx->screen;
 	static int dc = 0;
+	char dname[256];
 
 	if (radeon_ctx_pm4(rctx->ctx))
 		return;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
-	if (!dc)
-		radeon_ctx_dump_bof(rctx->ctx, "gallium.bof");
+	sprintf(dname, "gallium-%08d.bof", dc);
+	if (dc < 10)
+		radeon_ctx_dump_bof(rctx->ctx, dname);
 #if 1
 	radeon_ctx_submit(rctx->ctx);
 #endif
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index dc8d4cb315..33dff97d22 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -339,7 +339,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 {
 	struct tgsi_full_immediate *immediate;
 	struct r600_shader_ctx ctx;
-	struct r600_bc_output output;
+	struct r600_bc_output output[32];
 	unsigned opcode;
 	int i, r = 0, pos0;
 
@@ -418,33 +418,37 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	}
 	/* export output */
 	for (i = 0, pos0 = 0; i < shader->noutput; i++) {
-		memset(&output, 0, sizeof(struct r600_bc_output));
-		output.gpr = shader->output[i].gpr;
-		output.elem_size = 3;
-		output.swizzle_x = 0;
-		output.swizzle_y = 1;
-		output.swizzle_z = 2;
-		output.swizzle_w = 3;
-		output.barrier = 1;
-		output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
-		output.array_base = i - pos0;
-		output.inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
+		memset(&output[i], 0, sizeof(struct r600_bc_output));
+		output[i].gpr = shader->output[i].gpr;
+		output[i].elem_size = 3;
+		output[i].swizzle_x = 0;
+		output[i].swizzle_y = 1;
+		output[i].swizzle_z = 2;
+		output[i].swizzle_w = 3;
+		output[i].barrier = 1;
+		output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
+		output[i].array_base = i - pos0;
+		output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
 		switch (ctx.type == TGSI_PROCESSOR_VERTEX) {
 		case TGSI_PROCESSOR_VERTEX:
+			shader->output[i].type = r600_export_parameter;
 			if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-				output.array_base = 60;
-				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
+				shader->output[i].type = r600_export_position;
+				output[i].array_base = 60;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
 				/* position doesn't count in array_base */
 				pos0 = 1;
 			}
 			break;
 		case TGSI_PROCESSOR_FRAGMENT:
+			shader->output[i].type = r600_export_framebuffer;
 			if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
-				output.array_base = 0;
-				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
+				output[i].array_base = 0;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-				output.array_base = 61;
-				output.type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
+				shader->output[i].type = r600_export_position;
+				output[i].array_base = 61;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else {
 				R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
 				r = -EINVAL;
@@ -457,9 +461,17 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			goto out_err;
 		}
 		if (i == (shader->noutput - 1)) {
-			output.end_of_program = 1;
+			output[i].end_of_program = 1;
 		}
-		r = r600_bc_add_output(ctx.bc, &output);
+	}
+	for (i = shader->noutput - 1, shader->output_done = 0; i >= 0; i--) {
+		if (!(shader->output_done & (1 << output[i].type))) {
+			shader->output_done |= (1 << output[i].type);
+			output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
+		}
+	}
+	for (i = 0; i < shader->noutput; i++) {
+		r = r600_bc_add_output(ctx.bc, &output[i]);
 		if (r)
 			goto out_err;
 	}
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index ee0381e8bd..15562c19a5 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -25,9 +25,17 @@
 
 #include "r600_asm.h"
 
+enum r600_export_type {
+	r600_export_position = 0,
+	r600_export_parameter,
+	r600_export_framebuffer,
+};
+
 struct r600_shader_io {
 	unsigned		name;
 	unsigned		gpr;
+	unsigned		done;
+	unsigned		type;
 	int			sid;
 	unsigned		interpolate;
 };
@@ -41,6 +49,7 @@ struct r600_shader {
 	struct r600_shader_io	input[32];
 	struct r600_shader_io	output[32];
 	enum radeon_family	family;
+	unsigned		output_done;
 };
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index deb9bf3395..ef6c1bedeb 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -675,9 +675,8 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	unsigned color_info;
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
-	int id = R600_CB0 + cb;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, id);
+	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
 	if (rstate == NULL)
 		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 3a8405f9b4..00cff41b4f 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -160,8 +160,8 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
  * R600/R700
  */
 
-#define R600_NSTATE				1273
-#define R600_NTYPE				25
+#define R600_NSTATE				1280
+#define R600_NTYPE				32
 
 #define R600_CONFIG				0
 #define R600_CONFIG_TYPE				0
@@ -207,12 +207,26 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
 #define R600_GS_SAMPLER_BORDER_TYPE				20
 #define R600_CB0				1269
 #define R600_CB0_TYPE				21
-#define R600_DB				1270
-#define R600_DB_TYPE				22
-#define R600_VGT				1271
-#define R600_VGT_TYPE				23
-#define R600_DRAW				1272
-#define R600_DRAW_TYPE				24
+#define R600_CB1				1270
+#define R600_CB1_TYPE				22
+#define R600_CB2				1271
+#define R600_CB2_TYPE				23
+#define R600_CB3				1272
+#define R600_CB3_TYPE				24
+#define R600_CB4				1273
+#define R600_CB4_TYPE				25
+#define R600_CB5				1274
+#define R600_CB5_TYPE				26
+#define R600_CB6				1275
+#define R600_CB6_TYPE				27
+#define R600_CB7				1276
+#define R600_CB7_TYPE				28
+#define R600_DB				1277
+#define R600_DB_TYPE				29
+#define R600_VGT				1278
+#define R600_VGT_TYPE				30
+#define R600_DRAW				1279
+#define R600_DRAW_TYPE				31
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			1
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 5896df21b2..e40c77d8f6 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -372,6 +372,76 @@ static const struct radeon_register R600_CB0_names[] = {
 	{0x00028100, 0, 0, "CB_COLOR0_MASK"},
 };
 
+static const struct radeon_register R600_CB1_names[] = {
+	{0x00028044, 1, 0, "CB_COLOR1_BASE"},
+	{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
+	{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
+	{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
+	{0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
+	{0x000280C4, 1, 2, "CB_COLOR1_TILE"},
+	{0x00028104, 0, 0, "CB_COLOR1_MASK"},
+};
+
+static const struct radeon_register R600_CB2_names[] = {
+	{0x00028048, 1, 0, "CB_COLOR2_BASE"},
+	{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
+	{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
+	{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
+	{0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
+	{0x000280C8, 1, 2, "CB_COLOR2_TILE"},
+	{0x00028108, 0, 0, "CB_COLOR2_MASK"},
+};
+
+static const struct radeon_register R600_CB3_names[] = {
+	{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
+	{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
+	{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
+	{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
+	{0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
+	{0x000280CC, 1, 2, "CB_COLOR3_TILE"},
+	{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
+};
+
+static const struct radeon_register R600_CB4_names[] = {
+	{0x00028050, 1, 0, "CB_COLOR4_BASE"},
+	{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
+	{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
+	{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
+	{0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
+	{0x000280D0, 1, 2, "CB_COLOR4_TILE"},
+	{0x00028110, 0, 0, "CB_COLOR4_MASK"},
+};
+
+static const struct radeon_register R600_CB5_names[] = {
+	{0x00028054, 1, 0, "CB_COLOR5_BASE"},
+	{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
+	{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
+	{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
+	{0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
+	{0x000280D4, 1, 2, "CB_COLOR5_TILE"},
+	{0x00028114, 0, 0, "CB_COLOR5_MASK"},
+};
+
+static const struct radeon_register R600_CB6_names[] = {
+	{0x00028058, 1, 0, "CB_COLOR6_BASE"},
+	{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
+	{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
+	{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
+	{0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
+	{0x000280D8, 1, 2, "CB_COLOR6_TILE"},
+	{0x00028118, 0, 0, "CB_COLOR6_MASK"},
+};
+
+static const struct radeon_register R600_CB7_names[] = {
+	{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
+	{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
+	{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
+	{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
+	{0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
+	{0x000280DC, 1, 2, "CB_COLOR7_TILE"},
+	{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
+};
+
 static const struct radeon_register R600_DB_names[] = {
 	{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
 	{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
@@ -425,9 +495,16 @@ static struct radeon_type R600_types[] = {
 	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
 	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
 	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 static struct radeon_type R700_types[] = {
@@ -453,9 +530,16 @@ static struct radeon_type R700_types[] = {
 	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
 	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
 	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 #endif
-- 
cgit v1.2.3


From b474478f206c6d81af78696d3d5ce156d4d413d7 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 6 Aug 2010 17:12:37 -0400
Subject: r600g: really fix multi target support

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.c | 20 +-------------------
 src/gallium/drivers/r600/r600_shader.c  | 19 ++++++++-----------
 src/gallium/drivers/r600/r600_shader.h  |  8 --------
 src/gallium/drivers/r600/r600_state.c   | 25 +++++++++++++++++--------
 4 files changed, 26 insertions(+), 46 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 29dc93bae6..052eb1cd6d 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -55,7 +55,7 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	 * without throwing bad code
 	 */
 	sprintf(dname, "gallium-%08d.bof", dc);
-	if (dc < 10)
+	if (dc < 1)
 		radeon_ctx_dump_bof(rctx->ctx, dname);
 #if 1
 	radeon_ctx_submit(rctx->ctx);
@@ -204,24 +204,6 @@ static void r600_init_config(struct r600_context *rctx)
 		num_es_stack_entries = 0;
 		break;
 	}
-	printf("ps_prio : %d\n", ps_prio);
-	printf("vs_prio : %d\n", vs_prio);
-	printf("gs_prio : %d\n", gs_prio);
-	printf("es_prio : %d\n", es_prio);
-	printf("num_ps_gprs : %d\n", num_ps_gprs);
-	printf("num_vs_gprs : %d\n", num_vs_gprs);
-	printf("num_gs_gprs : %d\n", num_gs_gprs);
-	printf("num_es_gprs : %d\n", num_es_gprs);
-	printf("num_temp_gprs : %d\n", num_temp_gprs);
-	printf("num_ps_threads : %d\n", num_ps_threads);
-	printf("num_vs_threads : %d\n", num_vs_threads);
-	printf("num_gs_threads : %d\n", num_gs_threads);
-	printf("num_es_threads : %d\n", num_es_threads);
-	printf("num_ps_stack_entries : %d\n", num_ps_stack_entries);
-	printf("num_vs_stack_entries : %d\n", num_vs_stack_entries);
-	printf("num_gs_stack_entries : %d\n", num_gs_stack_entries);
-	printf("num_es_stack_entries : %d\n", num_es_stack_entries);
-
 	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
 
 	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 33dff97d22..8a778f5fd6 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -105,8 +105,8 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	int r;
 
-fprintf(stderr, "--------------------------------------------------------------\n");
-tgsi_dump(tokens, 0);
+//fprintf(stderr, "--------------------------------------------------------------\n");
+//tgsi_dump(tokens, 0);
 	if (rpshader == NULL)
 		return -ENOMEM;
 	rpshader->shader.family = radeon_get_family(rscreen->rw);
@@ -120,7 +120,7 @@ tgsi_dump(tokens, 0);
 		R600_ERR("building bytecode failed !\n");
 		return r;
 	}
-fprintf(stderr, "______________________________________________________________\n");
+//fprintf(stderr, "______________________________________________________________\n");
 	return 0;
 }
 
@@ -340,6 +340,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	struct tgsi_full_immediate *immediate;
 	struct r600_shader_ctx ctx;
 	struct r600_bc_output output[32];
+	unsigned output_done;
 	unsigned opcode;
 	int i, r = 0, pos0;
 
@@ -431,9 +432,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 		output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
 		switch (ctx.type == TGSI_PROCESSOR_VERTEX) {
 		case TGSI_PROCESSOR_VERTEX:
-			shader->output[i].type = r600_export_parameter;
 			if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-				shader->output[i].type = r600_export_position;
 				output[i].array_base = 60;
 				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
 				/* position doesn't count in array_base */
@@ -441,12 +440,10 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			}
 			break;
 		case TGSI_PROCESSOR_FRAGMENT:
-			shader->output[i].type = r600_export_framebuffer;
 			if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
-				output[i].array_base = 0;
+				output[i].array_base = shader->output[i].sid;
 				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
-				shader->output[i].type = r600_export_position;
 				output[i].array_base = 61;
 				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else {
@@ -464,9 +461,9 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			output[i].end_of_program = 1;
 		}
 	}
-	for (i = shader->noutput - 1, shader->output_done = 0; i >= 0; i--) {
-		if (!(shader->output_done & (1 << output[i].type))) {
-			shader->output_done |= (1 << output[i].type);
+	for (i = shader->noutput - 1, output_done = 0; i >= 0; i--) {
+		if (!(output_done & (1 << output[i].type))) {
+			output_done |= (1 << output[i].type);
 			output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
 		}
 	}
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index 15562c19a5..2ee7780ead 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -25,17 +25,10 @@
 
 #include "r600_asm.h"
 
-enum r600_export_type {
-	r600_export_position = 0,
-	r600_export_parameter,
-	r600_export_framebuffer,
-};
-
 struct r600_shader_io {
 	unsigned		name;
 	unsigned		gpr;
 	unsigned		done;
-	unsigned		type;
 	int			sid;
 	unsigned		interpolate;
 };
@@ -49,7 +42,6 @@ struct r600_shader {
 	struct r600_shader_io	input[32];
 	struct r600_shader_io	output[32];
 	enum radeon_family	family;
-	unsigned		output_done;
 };
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index ef6c1bedeb..223f2f3900 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1205,7 +1205,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
-	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;	
+	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
 	uint32_t color_control, target_mask, shader_mask;
 	int i;
 
@@ -1214,20 +1214,29 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	color_control = S_028808_PER_MRT_BLEND(1);
 
 	for (i = 0; i < nr_cbufs; i++) {
-		shader_mask |= 0xf << i;
+		shader_mask |= 0xf << (i * 4);
 	}
 
 	if (pbs->logicop_enable) {
 		color_control |= (pbs->logicop_func) << 16;
-	} else
+	} else {
 		color_control |= (0xcc << 16);
+	}
 
-	for (i = 0; i < 8; i++) {
-		if (pbs->rt[i].blend_enable) {
-			color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+	if (pbs->independent_blend_enable) {
+		for (i = 0; i < 8; i++) {
+			if (pbs->rt[i].blend_enable) {
+				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+			}
+			target_mask |= (pbs->rt[i].colormask << (4 * i));
+		}
+	} else {
+		for (i = 0; i < 8; i++) {
+			if (pbs->rt[0].blend_enable) {
+				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
+			}
+			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
-		target_mask |= (pbs->rt[i].colormask << (4 * i));
-		
 	}
 	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
-- 
cgit v1.2.3


From 32251c34f06ef91759fa75271ce724a06483cc42 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 6 Aug 2010 17:22:45 -0400
Subject: r600g: fix rendering, only enable target we write too

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_state.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 223f2f3900..ff621084d4 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1224,14 +1224,14 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	}
 
 	if (pbs->independent_blend_enable) {
-		for (i = 0; i < 8; i++) {
+		for (i = 0; i < nr_cbufs; i++) {
 			if (pbs->rt[i].blend_enable) {
 				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 			}
 			target_mask |= (pbs->rt[i].colormask << (4 * i));
 		}
 	} else {
-		for (i = 0; i < 8; i++) {
+		for (i = 0; i < nr_cbufs; i++) {
 			if (pbs->rt[0].blend_enable) {
 				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 			}
-- 
cgit v1.2.3


From 95fb0bf58dde0b81ce601d3f0477fd1b2a5a28d4 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Mon, 9 Aug 2010 11:32:45 -0400
Subject: r600g: fix r600 context structure, avoid segfault when no scissor

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.h |  2 +-
 src/gallium/drivers/r600/r600_state.c   | 17 +++++++++++++++--
 2 files changed, 16 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 431f8951b2..c606dbbda3 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -94,7 +94,7 @@ struct r600_context_hw_states {
 	struct radeon_state	*dsa;
 	struct radeon_state	*blend;
 	struct radeon_state	*viewport;
-	struct radeon_state	*cb[7];
+	struct radeon_state	*cb[8];
 	struct radeon_state	*config;
 	struct radeon_state	*cb_cntl;
 	struct radeon_state	*db;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index ff621084d4..cad5185e32 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -836,12 +836,25 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 static struct radeon_state *r600_scissor(struct r600_context *rctx)
 {
 	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
+	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
+	unsigned minx, maxx, miny, maxy;
 	u32 tl, br;
 
-	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
-	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
+	if (state == NULL) {
+		minx = 0;
+		miny = 0;
+		maxx = fb->cbufs[0]->width;
+		maxy = fb->cbufs[0]->height;
+	} else {
+		minx = state->minx;
+		miny = state->miny;
+		maxx = state->maxx;
+		maxy = state->maxy;
+	}
+	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
+	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
 	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
 	if (rstate == NULL)
 		return NULL;
-- 
cgit v1.2.3


From 457378e031ffb89a2011604c7798a6f5f2142207 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 11 Aug 2010 12:19:33 -0400
Subject: r600g: add point/sprite rendering support

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 60 ++++++++++++++++++++-----
 src/gallium/drivers/r600/r600_state.c  | 23 ++++++++--
 src/gallium/drivers/r600/r600d.h       | 80 ++++++++++++++++++++++++++++++++++
 3 files changed, 149 insertions(+), 14 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 8a778f5fd6..ca65bff24c 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -105,8 +105,8 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	int r;
 
-//fprintf(stderr, "--------------------------------------------------------------\n");
-//tgsi_dump(tokens, 0);
+fprintf(stderr, "--------------------------------------------------------------\n");
+tgsi_dump(tokens, 0);
 	if (rpshader == NULL)
 		return -ENOMEM;
 	rpshader->shader.family = radeon_get_family(rscreen->rw);
@@ -120,7 +120,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 		R600_ERR("building bytecode failed !\n");
 		return r;
 	}
-//fprintf(stderr, "______________________________________________________________\n");
+fprintf(stderr, "______________________________________________________________\n");
 	return 0;
 }
 
@@ -155,11 +155,14 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 
 static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
 {
+	const struct pipe_rasterizer_state *rasterizer;
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_shader *rshader = &rpshader->shader;
+	struct r600_context *rctx = r600_context(ctx);
 	struct radeon_state *state;
 	unsigned i, tmp, exports_ps, num_cout;
 
+	rasterizer = &rctx->rasterizer->state.rasterizer;
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
 	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
 	if (state == NULL)
@@ -171,6 +174,9 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 			rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
 			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
 		}
+		if (rasterizer->sprite_coord_enable & (1 << i)) {
+			tmp |= S_028644_PT_SPRITE_TEX(1);
+		}
 		state->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0 + i] = tmp;
 	}
 
@@ -340,7 +346,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	struct tgsi_full_immediate *immediate;
 	struct r600_shader_ctx ctx;
 	struct r600_bc_output output[32];
-	unsigned output_done;
+	unsigned output_done, noutput;
 	unsigned opcode;
 	int i, r = 0, pos0;
 
@@ -418,7 +424,8 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 		}
 	}
 	/* export output */
-	for (i = 0, pos0 = 0; i < shader->noutput; i++) {
+	noutput = shader->noutput;
+	for (i = 0, pos0 = 0; i < noutput; i++) {
 		memset(&output[i], 0, sizeof(struct r600_bc_output));
 		output[i].gpr = shader->output[i].gpr;
 		output[i].elem_size = 3;
@@ -430,13 +437,19 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 		output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
 		output[i].array_base = i - pos0;
 		output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
-		switch (ctx.type == TGSI_PROCESSOR_VERTEX) {
+		switch (ctx.type) {
 		case TGSI_PROCESSOR_VERTEX:
 			if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
 				output[i].array_base = 60;
 				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
 				/* position doesn't count in array_base */
-				pos0 = 1;
+				pos0++;
+			}
+			if (shader->output[i].name == TGSI_SEMANTIC_PSIZE) {
+				output[i].array_base = 61;
+				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_POS;
+				/* position doesn't count in array_base */
+				pos0++;
 			}
 			break;
 		case TGSI_PROCESSOR_FRAGMENT:
@@ -457,17 +470,42 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			r = -EINVAL;
 			goto out_err;
 		}
-		if (i == (shader->noutput - 1)) {
-			output[i].end_of_program = 1;
+	}
+	/* add fake param output for vertex shader if no param is exported */
+	if (ctx.type == TGSI_PROCESSOR_VERTEX) {
+		for (i = 0, pos0 = 0; i < noutput; i++) {
+			if (output[i].type == V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM) {
+				pos0 = 1;
+				break;
+			}
+		}
+		if (!pos0) {
+			memset(&output[i], 0, sizeof(struct r600_bc_output));
+			output[i].gpr = 0;
+			output[i].elem_size = 3;
+			output[i].swizzle_x = 0;
+			output[i].swizzle_y = 1;
+			output[i].swizzle_z = 2;
+			output[i].swizzle_w = 3;
+			output[i].barrier = 1;
+			output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
+			output[i].array_base = 0;
+			output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
+			noutput++;
 		}
 	}
-	for (i = shader->noutput - 1, output_done = 0; i >= 0; i--) {
+	/* set export done on last export of each type */
+	for (i = noutput - 1, output_done = 0; i >= 0; i--) {
+		if (i == (noutput - 1)) {
+			output[i].end_of_program = 1;
+		}
 		if (!(output_done & (1 << output[i].type))) {
 			output_done |= (1 << output[i].type);
 			output[i].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE;
 		}
 	}
-	for (i = 0; i < shader->noutput; i++) {
+	/* add output to bytecode */
+	for (i = 0; i < noutput; i++) {
 		r = r600_bc_add_output(ctx.bc, &output[i]);
 		if (r)
 			goto out_err;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index cad5185e32..a50b75cc79 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -769,6 +769,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	float offset_units = 0, offset_scale = 0;
 	char depth = 0;
 	unsigned offset_db_fmt_cntl = 0;
+	unsigned tmp;
 
 	if (fb->zsbuf) {
 		offset_units = state->offset_units;
@@ -800,6 +801,18 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
+	if (state->sprite_coord_enable) {
+		rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
+				S_0286D4_PNT_SPRITE_ENA(1) |
+				S_0286D4_PNT_SPRITE_OVRD_X(2) |
+				S_0286D4_PNT_SPRITE_OVRD_Y(3) |
+				S_0286D4_PNT_SPRITE_OVRD_Z(0) |
+				S_0286D4_PNT_SPRITE_OVRD_W(1);
+		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
+			rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
+					S_0286D4_PNT_SPRITE_TOP_1(1);
+		}
+	}
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
 			S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
@@ -808,10 +821,14 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 			S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 			S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 			S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
-	rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] = 0x00000000;
+	rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
+			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
+			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
 	rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = 0x00080008;
-	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x00000000;
+	/* point size 12.4 fixed point */
+	tmp = (unsigned)(state->point_size * 8.0 / 2.0);
+	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
+	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
 	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
 	rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
 	rstate->states[R600_RASTERIZER__PA_SC_MPASS_PS_CNTL] = 0x00000000;
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index af93731550..53388f822e 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -654,6 +654,13 @@
 #define   S_028E0C_OFFSET(x)                           (((x) & 0xFFFFFFFF) << 0)
 #define   G_028E0C_OFFSET(x)                           (((x) >> 0) & 0xFFFFFFFF)
 #define   C_028E0C_OFFSET                              0x00000000
+#define R_028A00_PA_SU_POINT_SIZE                    0x028A00
+#define   S_028A00_HEIGHT(x)                           (((x) & 0xFFFF) << 0)
+#define   G_028A00_HEIGHT(x)                           (((x) >> 0) & 0xFFFF)
+#define   C_028A00_HEIGHT                              0xFFFF0000
+#define   S_028A00_WIDTH(x)                            (((x) & 0xFFFF) << 16)
+#define   G_028A00_WIDTH(x)                            (((x) >> 16) & 0xFFFF)
+#define   C_028A00_WIDTH                               0x0000FFFF
 #define R_028A40_VGT_GS_MODE                         0x028A40
 #define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
 #define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
@@ -1153,6 +1160,79 @@
 #define     V_008958_DI_PT_2D_FILL_RECT_LIST           0x0000001A
 #define     V_008958_DI_PT_2D_LINE_STRIP               0x0000001B
 #define     V_008958_DI_PT_2D_TRI_STRIP                0x0000001C
+#define R_02881C_PA_CL_VS_OUT_CNTL                   0x02881C
+#define   S_02881C_CLIP_DIST_ENA_0(x)                  (((x) & 0x1) << 0)
+#define   G_02881C_CLIP_DIST_ENA_0(x)                  (((x) >> 0) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_0                     0xFFFFFFFE
+#define   S_02881C_CLIP_DIST_ENA_1(x)                  (((x) & 0x1) << 1)
+#define   G_02881C_CLIP_DIST_ENA_1(x)                  (((x) >> 1) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_1                     0xFFFFFFFD
+#define   S_02881C_CLIP_DIST_ENA_2(x)                  (((x) & 0x1) << 2)
+#define   G_02881C_CLIP_DIST_ENA_2(x)                  (((x) >> 2) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_2                     0xFFFFFFFB
+#define   S_02881C_CLIP_DIST_ENA_3(x)                  (((x) & 0x1) << 3)
+#define   G_02881C_CLIP_DIST_ENA_3(x)                  (((x) >> 3) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_3                     0xFFFFFFF7
+#define   S_02881C_CLIP_DIST_ENA_4(x)                  (((x) & 0x1) << 4)
+#define   G_02881C_CLIP_DIST_ENA_4(x)                  (((x) >> 4) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_4                     0xFFFFFFEF
+#define   S_02881C_CLIP_DIST_ENA_5(x)                  (((x) & 0x1) << 5)
+#define   G_02881C_CLIP_DIST_ENA_5(x)                  (((x) >> 5) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_5                     0xFFFFFFDF
+#define   S_02881C_CLIP_DIST_ENA_6(x)                  (((x) & 0x1) << 6)
+#define   G_02881C_CLIP_DIST_ENA_6(x)                  (((x) >> 6) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_6                     0xFFFFFFBF
+#define   S_02881C_CLIP_DIST_ENA_7(x)                  (((x) & 0x1) << 7)
+#define   G_02881C_CLIP_DIST_ENA_7(x)                  (((x) >> 7) & 0x1)
+#define   C_02881C_CLIP_DIST_ENA_7                     0xFFFFFF7F
+#define   S_02881C_CULL_DIST_ENA_0(x)                  (((x) & 0x1) << 8)
+#define   G_02881C_CULL_DIST_ENA_0(x)                  (((x) >> 8) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_0                     0xFFFFFEFF
+#define   S_02881C_CULL_DIST_ENA_1(x)                  (((x) & 0x1) << 9)
+#define   G_02881C_CULL_DIST_ENA_1(x)                  (((x) >> 9) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_1                     0xFFFFFDFF
+#define   S_02881C_CULL_DIST_ENA_2(x)                  (((x) & 0x1) << 10)
+#define   G_02881C_CULL_DIST_ENA_2(x)                  (((x) >> 10) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_2                     0xFFFFFBFF
+#define   S_02881C_CULL_DIST_ENA_3(x)                  (((x) & 0x1) << 11)
+#define   G_02881C_CULL_DIST_ENA_3(x)                  (((x) >> 11) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_3                     0xFFFFF7FF
+#define   S_02881C_CULL_DIST_ENA_4(x)                  (((x) & 0x1) << 12)
+#define   G_02881C_CULL_DIST_ENA_4(x)                  (((x) >> 12) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_4                     0xFFFFEFFF
+#define   S_02881C_CULL_DIST_ENA_5(x)                  (((x) & 0x1) << 13)
+#define   G_02881C_CULL_DIST_ENA_5(x)                  (((x) >> 13) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_5                     0xFFFFDFFF
+#define   S_02881C_CULL_DIST_ENA_6(x)                  (((x) & 0x1) << 14)
+#define   G_02881C_CULL_DIST_ENA_6(x)                  (((x) >> 14) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_6                     0xFFFFBFFF
+#define   S_02881C_CULL_DIST_ENA_7(x)                  (((x) & 0x1) << 15)
+#define   G_02881C_CULL_DIST_ENA_7(x)                  (((x) >> 15) & 0x1)
+#define   C_02881C_CULL_DIST_ENA_7                     0xFFFF7FFF
+#define   S_02881C_USE_VTX_POINT_SIZE(x)               (((x) & 0x1) << 16)
+#define   G_02881C_USE_VTX_POINT_SIZE(x)               (((x) >> 16) & 0x1)
+#define   C_02881C_USE_VTX_POINT_SIZE                  0xFFFEFFFF
+#define   S_02881C_USE_VTX_EDGE_FLAG(x)                (((x) & 0x1) << 17)
+#define   G_02881C_USE_VTX_EDGE_FLAG(x)                (((x) >> 17) & 0x1)
+#define   C_02881C_USE_VTX_EDGE_FLAG                   0xFFFDFFFF
+#define   S_02881C_USE_VTX_RENDER_TARGET_INDX(x)       (((x) & 0x1) << 18)
+#define   G_02881C_USE_VTX_RENDER_TARGET_INDX(x)       (((x) >> 18) & 0x1)
+#define   C_02881C_USE_VTX_RENDER_TARGET_INDX          0xFFFBFFFF
+#define   S_02881C_USE_VTX_VIEWPORT_INDX(x)            (((x) & 0x1) << 19)
+#define   G_02881C_USE_VTX_VIEWPORT_INDX(x)            (((x) >> 19) & 0x1)
+#define   C_02881C_USE_VTX_VIEWPORT_INDX               0xFFF7FFFF
+#define   S_02881C_USE_VTX_KILL_FLAG(x)                (((x) & 0x1) << 20)
+#define   G_02881C_USE_VTX_KILL_FLAG(x)                (((x) >> 20) & 0x1)
+#define   C_02881C_USE_VTX_KILL_FLAG                   0xFFEFFFFF
+#define   S_02881C_VS_OUT_MISC_VEC_ENA(x)              (((x) & 0x1) << 21)
+#define   G_02881C_VS_OUT_MISC_VEC_ENA(x)              (((x) >> 21) & 0x1)
+#define   C_02881C_VS_OUT_MISC_VEC_ENA                 0xFFDFFFFF
+#define   S_02881C_VS_OUT_CCDIST0_VEC_ENA(x)           (((x) & 0x1) << 22)
+#define   G_02881C_VS_OUT_CCDIST0_VEC_ENA(x)           (((x) >> 22) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST0_VEC_ENA              0xFFBFFFFF
+#define   S_02881C_VS_OUT_CCDIST1_VEC_ENA(x)           (((x) & 0x1) << 23)
+#define   G_02881C_VS_OUT_CCDIST1_VEC_ENA(x)           (((x) >> 23) & 0x1)
+#define   C_02881C_VS_OUT_CCDIST1_VEC_ENA              0xFF7FFFFF
 #define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
 #define   S_028868_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
 #define   G_028868_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
-- 
cgit v1.2.3


From 481b65abaedb271d0da24c75b8c60f7bcf6d8ce9 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 11 Aug 2010 14:26:07 -0400
Subject: r600g: accept empty frag prog shader

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_asm.c    |  3 +--
 src/gallium/drivers/r600/r600_shader.c | 15 +++++++++++++++
 src/gallium/drivers/r600/r600_state.c  |  2 +-
 3 files changed, 17 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index ae818bf19b..9ea9d4354d 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -167,8 +167,7 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
 	struct r600_bc_alu *alu;
 
 	if (bc->cf_last == NULL) {
-		R600_ERR("no last CF\n");
-		return -EINVAL;
+		return 0;
 	}
 	if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
 		return 0;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index cbeb69221c..956c7e7930 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -494,6 +494,21 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			noutput++;
 		}
 	}
+	/* add fake pixel export */
+	if (ctx.type == TGSI_PROCESSOR_FRAGMENT && !noutput) {
+		memset(&output[0], 0, sizeof(struct r600_bc_output));
+		output[0].gpr = 0;
+		output[0].elem_size = 3;
+		output[0].swizzle_x = 7;
+		output[0].swizzle_y = 7;
+		output[0].swizzle_z = 7;
+		output[0].swizzle_w = 7;
+		output[0].barrier = 1;
+		output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
+		output[0].array_base = 0;
+		output[0].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
+		noutput++;
+	}
 	/* set export done on last export of each type */
 	for (i = noutput - 1, output_done = 0; i >= 0; i--) {
 		if (i == (noutput - 1)) {
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index a50b75cc79..ed2d9f9984 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -727,7 +727,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	struct r600_resource *rbuffer;
 	struct radeon_state *rstate;
 	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level = state->cbufs[0]->level;
+	unsigned level;
 	unsigned pitch, slice, format;
 
 	if (state->zsbuf == NULL)
-- 
cgit v1.2.3


From e2df0a8b234efde140b340c2c9b67b06b789b758 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 12 Aug 2010 16:06:40 +1000
Subject: r600g: improve texture format checker.

This takes the r300g texture format checker and fixes it up for r600g,
it passes glean texSwizzle, pixelformats, and texture_srgb tests,

however I think it L8S8_SRGB is broken as is L8_SRGB, need to investigate.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r600/r600_context.h       |   3 +
 src/gallium/drivers/r600/r600_state.c         |  22 +--
 src/gallium/drivers/r600/r600_state_inlines.h |   2 +-
 src/gallium/drivers/r600/r600_texture.c       | 248 ++++++++++++++++++++++++++
 4 files changed, 263 insertions(+), 12 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index c606dbbda3..76d5de8653 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -175,4 +175,7 @@ extern int r600_pipe_shader_update(struct pipe_context *ctx,
 #define R600_ERR(fmt, args...) \
 	fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
 
+uint32_t r600_translate_texformat(enum pipe_format format,
+				  const unsigned char *swizzle_view, 
+				  uint32_t *word4_p, uint32_t *yuv_format_p);
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index ed2d9f9984..46e8f2ae1f 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1169,8 +1169,16 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	struct r600_resource *rbuffer;
 	struct radeon_state *rstate;
 	unsigned format;
-
-	format = r600_translate_colorformat(view->texture->format);
+	uint32_t word4 = 0, yuv_format = 0;
+	unsigned char swizzle[4];
+
+	swizzle[0] = view->swizzle_r;
+	swizzle[1] = view->swizzle_g;
+	swizzle[2] = view->swizzle_b;
+	swizzle[3] = view->swizzle_a;
+	format = r600_translate_texformat(view->texture->format,
+					  swizzle,
+					  &word4, &yuv_format);
 	if (format == ~0)
 		return NULL;
 	desc = util_format_description(view->texture->format);
@@ -1204,18 +1212,10 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
-			S_038010_FORMAT_COMP_X(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
-			S_038010_FORMAT_COMP_Y(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
-			S_038010_FORMAT_COMP_Z(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
-			S_038010_FORMAT_COMP_W(r600_format_type(UTIL_FORMAT_TYPE_UNSIGNED)) |
+		        word4 | 
 			S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
 			S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
 			S_038010_REQUEST_SIZE(1) |
-			S_038010_DST_SEL_X(r600_tex_swizzle(view->swizzle_b)) |
-			S_038010_DST_SEL_Y(r600_tex_swizzle(view->swizzle_g)) |
-			S_038010_DST_SEL_Z(r600_tex_swizzle(view->swizzle_r)) |
-			S_038010_DST_SEL_W(r600_tex_swizzle(view->swizzle_a)) |
-		        S_038010_FORCE_DEGAMMA(desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB ? 1 : 0) |
 			S_038010_BASE_LEVEL(view->first_level);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
 			S_038014_LAST_LEVEL(view->last_level) |
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 8271ad19fb..060a27cd6f 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -289,7 +289,7 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 
 static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
 {
-	return r600_translate_colorformat(format) != ~0;
+	return r600_translate_texformat(format, NULL, NULL, NULL) != ~0;
 }
 
 static INLINE boolean r600_is_colorbuffer_format_supported(enum pipe_format format)
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 1bce911306..30d79ebdd6 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -33,6 +33,7 @@
 #include "r600_screen.h"
 #include "r600_context.h"
 #include "r600_resource.h"
+#include "r600d.h"
 
 extern struct u_resource_vtbl r600_texture_vtbl;
 
@@ -277,3 +278,250 @@ void r600_init_screen_texture_functions(struct pipe_screen *screen)
 	screen->get_tex_surface = r600_get_tex_surface;
 	screen->tex_surface_destroy = r600_tex_surface_destroy;
 }
+
+static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
+					  const unsigned char *swizzle_view)
+{
+    unsigned i;
+    unsigned char swizzle[4];
+    unsigned result = 0;
+    const uint32_t swizzle_shift[4] = {
+	    16, 19, 22, 25,
+    };
+    const uint32_t swizzle_bit[4] = {
+	    0, 1, 2, 3,
+    };
+
+    if (swizzle_view) {
+        /* Combine two sets of swizzles. */
+        for (i = 0; i < 4; i++) {
+            swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
+                         swizzle_format[swizzle_view[i]] : swizzle_view[i];
+        }
+    } else {
+        memcpy(swizzle, swizzle_format, 4);
+    }
+
+    /* Get swizzle. */
+    for (i = 0; i < 4; i++) {
+        switch (swizzle[i]) {
+            case UTIL_FORMAT_SWIZZLE_Y:
+                result |= swizzle_bit[1] << swizzle_shift[i];
+                break;
+            case UTIL_FORMAT_SWIZZLE_Z:
+                result |= swizzle_bit[2] << swizzle_shift[i];
+                break;
+            case UTIL_FORMAT_SWIZZLE_W:
+                result |= swizzle_bit[3] << swizzle_shift[i];
+                break;
+            case UTIL_FORMAT_SWIZZLE_0:
+                result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
+                break;
+            case UTIL_FORMAT_SWIZZLE_1:
+                result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
+                break;
+            default: /* UTIL_FORMAT_SWIZZLE_X */
+                result |= swizzle_bit[0] << swizzle_shift[i];
+        }
+    }
+    return result;
+}
+
+/* texture format translate */
+uint32_t r600_translate_texformat(enum pipe_format format,
+				  const unsigned char *swizzle_view, 
+				  uint32_t *word4_p, uint32_t *yuv_format_p)
+{
+	uint32_t result = 0, word4 = 0, yuv_format = 0;
+	const struct util_format_description *desc;
+	boolean uniform = TRUE;
+	int i;
+	const uint32_t sign_bit[4] = {
+		S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED),
+		S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED),
+		S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED),
+		S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED)
+	};
+	desc = util_format_description(format);
+
+	/* Colorspace (return non-RGB formats directly). */
+	switch (desc->colorspace) {
+		/* Depth stencil formats */
+	case UTIL_FORMAT_COLORSPACE_ZS:
+		switch (format) {
+		case PIPE_FORMAT_Z16_UNORM:
+			result = V_028010_DEPTH_16;
+			goto out_word4;
+		case PIPE_FORMAT_Z24X8_UNORM:
+			result = V_028010_DEPTH_X8_24;
+			goto out_word4;
+		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+			result = V_028010_DEPTH_8_24;
+			goto out_word4;
+		default:
+			goto out_unknown;
+		}
+
+	case UTIL_FORMAT_COLORSPACE_YUV:
+		yuv_format |= (1 << 30);
+		switch (format) {
+                case PIPE_FORMAT_UYVY:
+                case PIPE_FORMAT_YUYV:
+		default:
+			break;
+		}
+		goto out_unknown; /* TODO */
+		
+	case UTIL_FORMAT_COLORSPACE_SRGB:
+		word4 |= S_038010_FORCE_DEGAMMA(1);
+		if (format == PIPE_FORMAT_L8A8_SRGB || format == PIPE_FORMAT_L8_SRGB)
+			goto out_unknown; /* fails for some reason - TODO */
+		break;
+
+	default:
+		break;
+	}
+	
+	word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
+
+	/* S3TC formats. TODO */
+	if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
+		goto out_unknown;
+	}
+
+
+	for (i = 0; i < desc->nr_channels; i++) {	
+		if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
+			word4 |= sign_bit[i];
+		}
+	}
+
+	/* R8G8Bx_SNORM - TODO CxV8U8 */
+
+	/* RGTC - TODO */
+
+	/* See whether the components are of the same size. */
+	for (i = 1; i < desc->nr_channels; i++) {
+		uniform = uniform && desc->channel[0].size == desc->channel[i].size;
+	}
+	
+	/* Non-uniform formats. */
+	if (!uniform) {
+		switch(desc->nr_channels) {
+		case 3:
+			if (desc->channel[0].size == 5 &&
+			    desc->channel[1].size == 6 &&
+			    desc->channel[2].size == 5) {
+				result |= V_0280A0_COLOR_5_6_5;
+				goto out_word4;
+			}
+			goto out_unknown;
+		case 4:
+			if (desc->channel[0].size == 5 &&
+			    desc->channel[1].size == 5 &&
+			    desc->channel[2].size == 5 &&
+			    desc->channel[3].size == 1) {
+				result |= V_0280A0_COLOR_1_5_5_5;
+				goto out_word4;
+			}
+			if (desc->channel[0].size == 10 &&
+			    desc->channel[1].size == 10 &&
+			    desc->channel[2].size == 10 &&
+			    desc->channel[3].size == 2) {
+				result |= V_0280A0_COLOR_10_10_10_2;
+				goto out_word4;
+			}
+			goto out_unknown;
+		}
+		goto out_unknown;
+	}
+
+	/* uniform formats */
+	switch (desc->channel[0].type) {
+	case UTIL_FORMAT_TYPE_UNSIGNED:
+	case UTIL_FORMAT_TYPE_SIGNED:
+		if (!desc->channel[0].normalized &&
+		    desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) {
+			goto out_unknown;
+		}
+
+		switch (desc->channel[0].size) {
+		case 4:
+			switch (desc->nr_channels) {
+			case 2:
+				result |= V_0280A0_COLOR_4_4;
+				goto out_word4;
+			case 4:
+				result |= V_0280A0_COLOR_4_4_4_4;
+				goto out_word4;
+			}
+			goto out_unknown;
+		case 8:
+			switch (desc->nr_channels) {
+			case 1:
+				result |= V_0280A0_COLOR_8;
+				goto out_word4;
+			case 2:
+				result |= V_0280A0_COLOR_8_8;
+				goto out_word4;
+			case 4:
+				result |= V_0280A0_COLOR_8_8_8_8;
+				goto out_word4;
+			}
+			goto out_unknown;
+		case 16:
+			switch (desc->nr_channels) {
+			case 1:
+				result |= V_0280A0_COLOR_16;
+				goto out_word4;
+			case 2:
+				result |= V_0280A0_COLOR_16_16;
+				goto out_word4;
+			case 4:
+				result |= V_0280A0_COLOR_16_16_16_16;
+				goto out_word4;
+			}
+		}
+		goto out_unknown;
+
+	case UTIL_FORMAT_TYPE_FLOAT:
+		switch (desc->channel[0].size) {
+		case 16:
+			switch (desc->nr_channels) {
+			case 1:
+				result |= V_0280A0_COLOR_16_FLOAT;
+				goto out_word4;
+			case 2:
+				result |= V_0280A0_COLOR_16_16_FLOAT;
+				goto out_word4;
+			case 4:
+				result |= V_0280A0_COLOR_16_16_16_16_FLOAT;
+				goto out_word4;
+			}
+			goto out_unknown;
+		case 32:
+			switch (desc->nr_channels) {
+			case 1:
+				result |= V_0280A0_COLOR_32_FLOAT;
+				goto out_word4;
+			case 2:
+				result |= V_0280A0_COLOR_32_32_FLOAT;
+				goto out_word4;
+			case 4:
+				result |= V_0280A0_COLOR_32_32_32_32_FLOAT;
+				goto out_word4;
+			}
+		}
+		
+	}
+out_word4:
+	if (word4_p)
+		*word4_p = word4;
+	if (yuv_format_p)
+		*yuv_format_p = yuv_format;
+//	fprintf(stderr,"returning %08x %08x %08x\n", result, word4, yuv_format);
+	return result;
+out_unknown:
+//	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
+	return ~0;
+}
-- 
cgit v1.2.3


From 13bc2098ca21be3d11176e558ca71e29e41a239f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 12 Aug 2010 16:29:04 +1000
Subject: r600g: fix provoking-vertex piglit test.

---
 src/gallium/drivers/r600/r600_state.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 46e8f2ae1f..b9b46d64e3 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -770,7 +770,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	char depth = 0;
 	unsigned offset_db_fmt_cntl = 0;
 	unsigned tmp;
-
+	unsigned prov_vtx = 1;
 	if (fb->zsbuf) {
 		offset_units = state->offset_units;
 		offset_scale = state->offset_scale * 12.0f;
@@ -796,6 +796,9 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	}
 	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 
+	if (state->flatshade_first)
+		prov_vtx = 0;
+
 	rctx->flat_shade = state->flatshade;
 	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 	if (rstate == NULL)
@@ -814,13 +817,14 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		}
 	}
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
-	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080000 |
-			S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
-			S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
-			S_028814_FACE(!state->front_ccw) |
-			S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
-			S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
-			S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
+	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
+		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
+		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
+		S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
+		S_028814_FACE(!state->front_ccw) |
+		S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
+		S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri);
 	rstate->states[R600_RASTERIZER__PA_CL_VS_OUT_CNTL] =
 			S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
-- 
cgit v1.2.3


From f2804e70623c4c71e5758a24d695f8d6b74bf6d7 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 13 Aug 2010 10:16:29 +1000
Subject: r600g: fix memory leaks running gears.

I noticed gears memory usage was heading skywards, some r600 "states"
aren't properly refcounted, and the ctx->state is never freed.
---
 src/gallium/drivers/r600/r600_state.c    | 5 +++++
 src/gallium/winsys/r600/drm/radeon_ctx.c | 1 +
 2 files changed, 6 insertions(+)

(limited to 'src/gallium/drivers/r600/r600_state.c')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b9b46d64e3..3efd409ae0 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -379,6 +379,8 @@ static void r600_set_scissor_state(struct pipe_context *ctx,
 
 	rstate = r600_context_state(rctx, pipe_scissor_type, state);
 	r600_bind_state(ctx, rstate);
+	/* refcount is taken care of this */
+	r600_delete_state(ctx, rstate);
 }
 
 static void r600_set_stencil_ref(struct pipe_context *ctx,
@@ -389,6 +391,8 @@ static void r600_set_stencil_ref(struct pipe_context *ctx,
 
 	rstate = r600_context_state(rctx, pipe_stencil_ref_type, state);
 	r600_bind_state(ctx, rstate);
+	/* refcount is taken care of this */
+	r600_delete_state(ctx, rstate);
 }
 
 static void r600_set_vertex_buffers(struct pipe_context *ctx,
@@ -433,6 +437,7 @@ static void r600_set_viewport_state(struct pipe_context *ctx,
 
 	rstate = r600_context_state(rctx, pipe_viewport_type, state);
 	r600_bind_state(ctx, rstate);
+	r600_delete_state(ctx, rstate);
 }
 
 void r600_init_state_functions(struct r600_context *rctx)
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index ff70ce6de7..45b706bb0f 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -112,6 +112,7 @@ struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
 		ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
 	}
 	ctx->radeon = radeon_decref(ctx->radeon);
+	free(ctx->state);
 	free(ctx->draw);
 	free(ctx->bo);
 	free(ctx->pm4);
-- 
cgit v1.2.3