From c3974dc837b4a11a30603bb00fa1d346e721af59 Mon Sep 17 00:00:00 2001 From: Keith Whitwell Date: Sun, 17 Oct 2010 11:45:49 -0700 Subject: r600g: set hardware pixel centers according to gl_rasterization_rules These were previously being left in the default (D3D) mode. This mean that triangles were drawn slightly incorrectly, but also because this state is relied on by the u_blitter code, all blits were half a pixel off. --- src/gallium/drivers/r600/r600_state.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/gallium/drivers/r600/r600_state.c') diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index ccd74210b7..17e64b18e9 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -475,6 +475,11 @@ static void *r600_create_rs_state(struct pipe_context *ctx, r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL); + + r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, + S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), + 0xFFFFFFFF, NULL); + r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); -- cgit v1.2.3