From c9b7bece0569d9e193591ebff329acd1d9bd9e3c Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Sun, 15 Aug 2010 22:58:26 +0100
Subject: llvmpipe: special case triangles which fall in a single 16x16 block

Check for these and route them to a dedicated handler with one fewer
levels of recursive rasterization.
---
 src/gallium/drivers/llvmpipe/lp_rast.h      |  4 ++
 src/gallium/drivers/llvmpipe/lp_rast_tri.c  | 82 +++++++++++++++++++++++++++++
 src/gallium/drivers/llvmpipe/lp_setup_tri.c | 20 +++++++
 3 files changed, 106 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_rast.h b/src/gallium/drivers/llvmpipe/lp_rast.h
index 44319a0ad6..102e902d02 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast.h
+++ b/src/gallium/drivers/llvmpipe/lp_rast.h
@@ -256,5 +256,9 @@ void lp_rast_begin_query(struct lp_rasterizer_task *,
 void lp_rast_end_query(struct lp_rasterizer_task *,
                        const union lp_rast_cmd_arg );
 
+void
+lp_rast_triangle_3_16(struct lp_rasterizer_task *task,
+                      const union lp_rast_cmd_arg arg);
+
 
 #endif
diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri.c b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
index 980c18c024..673f67386b 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
@@ -157,3 +157,85 @@ build_mask_linear(int c, int dcdx, int dcdy)
 #define NR_PLANES 7
 #include "lp_rast_tri_tmp.h"
 
+
+/* Special case for 3 plane triangle which is contained entirely
+ * within a 16x16 block.
+ */
+void
+lp_rast_triangle_3_16(struct lp_rasterizer_task *task,
+                      const union lp_rast_cmd_arg arg)
+{
+   const struct lp_rast_triangle *tri = arg.triangle.tri;
+   const struct lp_rast_plane *plane = tri->plane;
+   unsigned mask = arg.triangle.plane_mask;
+   const int x = task->x + (mask & 0xf) * 16;
+   const int y = task->y + (mask >> 4) * 16;
+   unsigned outmask, inmask, partmask, partial_mask;
+   unsigned j;
+   int c[3];
+
+   outmask = 0;                 /* outside one or more trivial reject planes */
+   partmask = 0;                /* outside one or more trivial accept planes */
+
+   for (j = 0; j < 3; j++) {
+      c[j] = plane[j].c + plane[j].dcdy * y - plane[j].dcdx * x;
+
+      {
+	 const int dcdx = -plane[j].dcdx * 4;
+	 const int dcdy = plane[j].dcdy * 4;
+	 const int cox = c[j] + plane[j].eo * 4;
+	 const int cio = c[j] + plane[j].ei * 4 - 1;
+
+	 outmask |= build_mask_linear(cox, dcdx, dcdy);
+	 partmask |= build_mask_linear(cio, dcdx, dcdy);
+      }
+   }
+
+   if (outmask == 0xffff)
+      return;
+
+   /* Mask of sub-blocks which are inside all trivial accept planes:
+    */
+   inmask = ~partmask & 0xffff;
+
+   /* Mask of sub-blocks which are inside all trivial reject planes,
+    * but outside at least one trivial accept plane:
+    */
+   partial_mask = partmask & ~outmask;
+
+   assert((partial_mask & inmask) == 0);
+
+   /* Iterate over partials:
+    */
+   while (partial_mask) {
+      int i = ffs(partial_mask) - 1;
+      int ix = (i & 3) * 4;
+      int iy = (i >> 2) * 4;
+      int px = x + ix;
+      int py = y + iy; 
+      int cx[3];
+
+      partial_mask &= ~(1 << i);
+
+      for (j = 0; j < 3; j++)
+         cx[j] = (c[j] 
+		  - plane[j].dcdx * ix
+		  + plane[j].dcdy * iy);
+
+      do_block_4_3(task, tri, plane, px, py, cx);
+   }
+
+   /* Iterate over fulls: 
+    */
+   while (inmask) {
+      int i = ffs(inmask) - 1;
+      int ix = (i & 3) * 4;
+      int iy = (i >> 2) * 4;
+      int px = x + ix;
+      int py = y + iy; 
+
+      inmask &= ~(1 << i);
+
+      block_full_4(task, tri, px, py);
+   }
+}
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index 393533ebee..614a6372b4 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -643,6 +643,26 @@ do_triangle_ccw(struct lp_setup_context *setup,
 
    /* Convert to tile coordinates, and inclusive ranges:
     */
+   if (nr_planes == 3) {
+      int ix0 = minx / 16;
+      int iy0 = miny / 16;
+      int ix1 = (maxx-1) / 16;
+      int iy1 = (maxy-1) / 16;
+      
+      if (iy0 == iy1 && ix0 == ix1)
+      {
+
+	 /* Triangle is contained in a single 16x16 block:
+	  */
+	 int mask = (ix0 & 3) | ((iy0 & 3) << 4);
+
+	 lp_scene_bin_command( scene, ix0/4, iy0/4,
+			       lp_rast_triangle_3_16,
+			       lp_rast_arg_triangle(tri, mask) );
+	 return;
+      }
+   }
+
    ix0 = minx / TILE_SIZE;
    iy0 = miny / TILE_SIZE;
    ix1 = (maxx-1) / TILE_SIZE;
-- 
cgit v1.2.3


From b217167056970a9b7d09b7ffe863f013c2083395 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Sun, 15 Aug 2010 22:53:17 +0200
Subject: r300/compiler: implement SSG opcode

---
 src/gallium/drivers/r300/r300_tgsi_to_rc.c         |  2 +-
 .../drivers/dri/r300/compiler/radeon_opcodes.c     |  7 ++
 .../drivers/dri/r300/compiler/radeon_opcodes.h     |  3 +
 .../drivers/dri/r300/compiler/radeon_program_alu.c | 74 ++++++++++++++++++++++
 4 files changed, 85 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
index dd697b9c37..53f07c1f02 100644
--- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
+++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
@@ -97,7 +97,7 @@ static unsigned translate_opcode(unsigned opcode)
      /* case TGSI_OPCODE_BRA: return RC_OPCODE_BRA; */
      /* case TGSI_OPCODE_CAL: return RC_OPCODE_CAL; */
      /* case TGSI_OPCODE_RET: return RC_OPCODE_RET; */
-     /* case TGSI_OPCODE_SSG: return RC_OPCODE_SSG; */
+        case TGSI_OPCODE_SSG: return RC_OPCODE_SSG;
         case TGSI_OPCODE_CMP: return RC_OPCODE_CMP;
         case TGSI_OPCODE_SCS: return RC_OPCODE_SCS;
         case TGSI_OPCODE_TXB: return RC_OPCODE_TXB;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index 2ea830be7f..0602e02a98 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -294,6 +294,13 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
 		.HasDstReg = 1,
 		.IsComponentwise = 1
 	},
+	{
+		.Opcode = RC_OPCODE_SSG,
+		.Name = "SSG",
+		.NumSrcRegs = 1,
+		.HasDstReg = 1,
+		.IsComponentwise = 1
+	},
 	{
 		.Opcode = RC_OPCODE_SUB,
 		.Name = "SUB",
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
index 6e18d6eb3f..0a9fceef38 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
@@ -154,6 +154,9 @@ typedef enum {
 	/** vec4 instruction: dst.c = (src0.c != src1.c) ? 1.0 : 0.0 */
 	RC_OPCODE_SNE,
 
+	/** vec4 instruction: dst.c = (src0.c < 0 ?) -1 : ((src0.c > 0) : 1 : 0) */
+	RC_OPCODE_SSG,
+
 	/** vec4 instruction: dst.c = src0.c - src1.c */
 	RC_OPCODE_SUB,
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
index 857aae5514..c988e0c67e 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
@@ -464,6 +464,43 @@ static void transform_SNE(struct radeon_compiler* c,
 	rc_remove_instruction(inst);
 }
 
+static void transform_SSG(struct radeon_compiler* c,
+	struct rc_instruction* inst)
+{
+	/* result = sign(x)
+	 *
+	 *   CMP tmp0, -x, 1, 0
+	 *   CMP tmp1, x, 1, 0
+	 *   ADD result, tmp0, -tmp1;
+	 */
+	unsigned tmp0, tmp1;
+
+	/* 0 < x */
+	tmp0 = rc_find_free_temporary(c);
+	emit3(c, inst->Prev, RC_OPCODE_CMP, 0,
+	      dstregtmpmask(tmp0, inst->U.I.DstReg.WriteMask),
+	      negate(inst->U.I.SrcReg[0]),
+	      builtin_one,
+	      builtin_zero);
+
+	/* x < 0 */
+	tmp1 = rc_find_free_temporary(c);
+	emit3(c, inst->Prev, RC_OPCODE_CMP, 0,
+	      dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask),
+	      inst->U.I.SrcReg[0],
+	      builtin_one,
+	      builtin_zero);
+
+	/* Either both are zero, or one of them is one and the other is zero. */
+	/* result = tmp0 - tmp1 */
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
+	      inst->U.I.DstReg,
+	      srcreg(RC_FILE_TEMPORARY, tmp0),
+	      negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
+
+	rc_remove_instruction(inst);
+}
+
 static void transform_SUB(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
@@ -530,6 +567,7 @@ int radeonTransformALU(
 	case RC_OPCODE_SLE: transform_SLE(c, inst); return 1;
 	case RC_OPCODE_SLT: transform_SLT(c, inst); return 1;
 	case RC_OPCODE_SNE: transform_SNE(c, inst); return 1;
+	case RC_OPCODE_SSG: transform_SSG(c, inst); return 1;
 	case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 	case RC_OPCODE_SWZ: transform_SWZ(c, inst); return 1;
 	case RC_OPCODE_XPD: transform_XPD(c, inst); return 1;
@@ -672,6 +710,41 @@ static void transform_r300_vertex_SLE(struct radeon_compiler* c,
 	inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
 }
 
+static void transform_r300_vertex_SSG(struct radeon_compiler* c,
+	struct rc_instruction* inst)
+{
+	/* result = sign(x)
+	 *
+	 *   SLT tmp0, 0, x;
+	 *   SLT tmp1, x, 0;
+	 *   ADD result, tmp0, -tmp1;
+	 */
+	unsigned tmp0, tmp1;
+
+	/* 0 < x */
+	tmp0 = rc_find_free_temporary(c);
+	emit2(c, inst->Prev, RC_OPCODE_SLT, 0,
+	      dstregtmpmask(tmp0, inst->U.I.DstReg.WriteMask),
+	      builtin_zero,
+	      inst->U.I.SrcReg[0]);
+
+	/* x < 0 */
+	tmp1 = rc_find_free_temporary(c);
+	emit2(c, inst->Prev, RC_OPCODE_SLT, 0,
+	      dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask),
+	      inst->U.I.SrcReg[0],
+	      builtin_zero);
+
+	/* Either both are zero, or one of them is one and the other is zero. */
+	/* result = tmp0 - tmp1 */
+	emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
+	      inst->U.I.DstReg,
+	      srcreg(RC_FILE_TEMPORARY, tmp0),
+	      negate(srcreg(RC_FILE_TEMPORARY, tmp1)));
+
+	rc_remove_instruction(inst);
+}
+
 /**
  * For use with radeonLocalTransform, this transforms non-native ALU
  * instructions of the r300 up to r500 vertex engine.
@@ -705,6 +778,7 @@ int r300_transform_vertex_alu(
 			return 1;
 		}
 		return 0;
+	case RC_OPCODE_SSG: transform_r300_vertex_SSG(c, inst); return 1;
 	case RC_OPCODE_SUB: transform_SUB(c, inst); return 1;
 	case RC_OPCODE_SWZ: transform_SWZ(c, inst); return 1;
 	case RC_OPCODE_XPD: transform_XPD(c, inst); return 1;
-- 
cgit v1.2.3


From 27eb2e275544d78a229eaded9bafc0db60172675 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Sun, 15 Aug 2010 23:44:16 +0200
Subject: r300/compiler: implement DP2 opcode

---
 src/gallium/drivers/r300/r300_tgsi_to_rc.c         |  2 +-
 .../drivers/dri/r300/compiler/radeon_opcodes.c     | 10 +++++
 .../drivers/dri/r300/compiler/radeon_opcodes.h     |  3 ++
 .../drivers/dri/r300/compiler/radeon_program_alu.c | 43 +++++++++++++++++-----
 4 files changed, 48 insertions(+), 10 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_tgsi_to_rc.c b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
index 53f07c1f02..a4911b9a2a 100644
--- a/src/gallium/drivers/r300/r300_tgsi_to_rc.c
+++ b/src/gallium/drivers/r300/r300_tgsi_to_rc.c
@@ -103,7 +103,7 @@ static unsigned translate_opcode(unsigned opcode)
         case TGSI_OPCODE_TXB: return RC_OPCODE_TXB;
      /* case TGSI_OPCODE_NRM: return RC_OPCODE_NRM; */
      /* case TGSI_OPCODE_DIV: return RC_OPCODE_DIV; */
-     /* case TGSI_OPCODE_DP2: return RC_OPCODE_DP2; */
+        case TGSI_OPCODE_DP2: return RC_OPCODE_DP2;
         case TGSI_OPCODE_TXL: return RC_OPCODE_TXL;
         case TGSI_OPCODE_BRK: return RC_OPCODE_BRK;
         case TGSI_OPCODE_IF: return RC_OPCODE_IF;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
index 0602e02a98..da495a3afa 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.c
@@ -94,6 +94,12 @@ struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE] = {
 		.HasDstReg = 1,
 		.IsComponentwise = 1
 	},
+	{
+		.Opcode = RC_OPCODE_DP2,
+		.Name = "DP2",
+		.NumSrcRegs = 2,
+		.HasDstReg = 1
+	},
 	{
 		.Opcode = RC_OPCODE_DP3,
 		.Name = "DP3",
@@ -442,6 +448,10 @@ void rc_compute_sources_for_writemask(
 		case RC_OPCODE_ARL:
 			srcmasks[0] |= RC_MASK_X;
 			break;
+		case RC_OPCODE_DP2:
+			srcmasks[0] |= RC_MASK_XY;
+			srcmasks[1] |= RC_MASK_XY;
+			break;
 		case RC_OPCODE_DP3:
 			srcmasks[0] |= RC_MASK_XYZ;
 			srcmasks[1] |= RC_MASK_XYZ;
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
index 0a9fceef38..d3f639c870 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_opcodes.h
@@ -64,6 +64,9 @@ typedef enum {
 	 * dst.c = d src0.c / dy */
 	RC_OPCODE_DDY,
 
+	/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y */
+	RC_OPCODE_DP2,
+
 	/** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z */
 	RC_OPCODE_DP3,
 
diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
index c988e0c67e..704a7bb2d2 100644
--- a/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
+++ b/src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
@@ -216,18 +216,18 @@ static void transform_CEIL(struct radeon_compiler* c,
 	rc_remove_instruction(inst);
 }
 
-static void transform_DP3(struct radeon_compiler* c,
+static void transform_DP2(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
 	struct rc_src_register src0 = inst->U.I.SrcReg[0];
 	struct rc_src_register src1 = inst->U.I.SrcReg[1];
-	src0.Negate &= ~RC_MASK_W;
-	src0.Swizzle &= ~(7 << (3 * 3));
-	src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
-	src1.Negate &= ~RC_MASK_W;
-	src1.Swizzle &= ~(7 << (3 * 3));
-	src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
-	emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
+	src0.Negate &= ~(RC_MASK_Z | RC_MASK_W);
+	src0.Swizzle &= ~(63 << (3 * 2));
+	src0.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
+	src1.Negate &= ~(RC_MASK_Z | RC_MASK_W);
+	src1.Swizzle &= ~(63 << (3 * 2));
+	src1.Swizzle |= (RC_SWIZZLE_ZERO << (3 * 2)) | (RC_SWIZZLE_ZERO << (3 * 3));
+	emit2(c, inst->Prev, RC_OPCODE_DP3, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
 	rc_remove_instruction(inst);
 }
 
@@ -553,6 +553,7 @@ int radeonTransformALU(
 	switch(inst->U.I.Opcode) {
 	case RC_OPCODE_ABS: transform_ABS(c, inst); return 1;
 	case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
+	case RC_OPCODE_DP2: transform_DP2(c, inst); return 1;
 	case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
 	case RC_OPCODE_DST: transform_DST(c, inst); return 1;
 	case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
@@ -615,6 +616,29 @@ static void transform_r300_vertex_CMP(struct radeon_compiler* c,
 	rc_remove_instruction(inst);
 }
 
+static void transform_r300_vertex_DP2(struct radeon_compiler* c,
+	struct rc_instruction* inst)
+{
+	struct rc_instruction *next_inst = inst->Next;
+	transform_DP2(c, inst);
+	next_inst->Prev->U.I.Opcode = RC_OPCODE_DP4;
+}
+
+static void transform_r300_vertex_DP3(struct radeon_compiler* c,
+	struct rc_instruction* inst)
+{
+	struct rc_src_register src0 = inst->U.I.SrcReg[0];
+	struct rc_src_register src1 = inst->U.I.SrcReg[1];
+	src0.Negate &= ~RC_MASK_W;
+	src0.Swizzle &= ~(7 << (3 * 3));
+	src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
+	src1.Negate &= ~RC_MASK_W;
+	src1.Swizzle &= ~(7 << (3 * 3));
+	src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
+	emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
+	rc_remove_instruction(inst);
+}
+
 static void transform_r300_vertex_fix_LIT(struct radeon_compiler* c,
 	struct rc_instruction* inst)
 {
@@ -758,7 +782,8 @@ int r300_transform_vertex_alu(
 	case RC_OPCODE_ABS: transform_r300_vertex_ABS(c, inst); return 1;
 	case RC_OPCODE_CEIL: transform_CEIL(c, inst); return 1;
 	case RC_OPCODE_CMP: transform_r300_vertex_CMP(c, inst); return 1;
-	case RC_OPCODE_DP3: transform_DP3(c, inst); return 1;
+	case RC_OPCODE_DP2: transform_r300_vertex_DP2(c, inst); return 1;
+	case RC_OPCODE_DP3: transform_r300_vertex_DP3(c, inst); return 1;
 	case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
 	case RC_OPCODE_FLR: transform_FLR(c, inst); return 1;
 	case RC_OPCODE_LIT: transform_r300_vertex_fix_LIT(c, inst); return 1;
-- 
cgit v1.2.3


From b0e1565b5f24c3f624745890170cce0700e620ff Mon Sep 17 00:00:00 2001
From: nobled <nobled@dreamwidth.org>
Date: Sun, 15 Aug 2010 02:50:04 +0000
Subject: r300g: Fix macro
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This fixes a potential bug if (has_hyperz) is false
(it would still init the atom as if has_hyperz were true).

Signed-off-by: Marek Olšák <maraeo@gmail.com>
---
 src/gallium/drivers/r300/r300_context.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index e8b6c4f7af..23b654e0c8 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -158,12 +158,14 @@ void r300_flush_cb(void *data)
 }
 
 #define R300_INIT_ATOM(atomname, atomsize) \
+ do { \
     r300->atomname.name = #atomname; \
     r300->atomname.state = NULL; \
     r300->atomname.size = atomsize; \
     r300->atomname.emit = r300_emit_##atomname; \
     r300->atomname.dirty = FALSE; \
-    insert_at_tail(&r300->atom_list, &r300->atomname);
+    insert_at_tail(&r300->atom_list, &r300->atomname); \
+ } while (0)
 
 static void r300_setup_atoms(struct r300_context* r300)
 {
-- 
cgit v1.2.3


From 1e2cd02eae9d27e48273f4a548dc51f4f838eb96 Mon Sep 17 00:00:00 2001
From: nobled <nobled@dreamwidth.org>
Date: Sun, 15 Aug 2010 03:59:15 +0000
Subject: r300g: Fix leaks in failed context creation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This changes r300_destroy_context() so it can be called
on a partially-initialized context, and uses it when
r300_create_context() hits a fatal error.

This makes sure r300_create_context() doesn't leak memory
or neglect to call r300_update_num_contexts() when it fails.

Signed-off-by: Marek Olšák <maraeo@gmail.com>
---
 src/gallium/drivers/r300/r300_context.c | 82 +++++++++++++++++++--------------
 1 file changed, 48 insertions(+), 34 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index 23b654e0c8..25b39c566c 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -99,8 +99,10 @@ static void r300_destroy_context(struct pipe_context* context)
     struct r300_context* r300 = r300_context(context);
     struct r300_atom *atom;
 
-    util_blitter_destroy(r300->blitter);
-    draw_destroy(r300->draw);
+    if (r300->blitter)
+        util_blitter_destroy(r300->blitter);
+    if (r300->draw)
+        draw_destroy(r300->draw);
 
     /* Print stats, if enabled. */
     if (SCREEN_DBG_ON(r300->screen, DBG_STATS)) {
@@ -112,40 +114,48 @@ static void r300_destroy_context(struct pipe_context* context)
         }
     }
 
-    u_upload_destroy(r300->upload_vb);
-    u_upload_destroy(r300->upload_ib);
+    if (r300->upload_vb)
+        u_upload_destroy(r300->upload_vb);
+    if (r300->upload_ib)
+        u_upload_destroy(r300->upload_ib);
 
-    /* setup hyper-z mm */
-    if (r300->rws->get_value(r300->rws, R300_CAN_HYPERZ))
+    if (r300->zmask_mm)
         r300_hyperz_destroy_mm(r300);
 
-    translate_cache_destroy(r300->tran.translate_cache);
+    if (r300->tran.translate_cache)
+        translate_cache_destroy(r300->tran.translate_cache);
 
+    /* XXX: This function assumes r300->query_list was initialized */
     r300_release_referenced_objects(r300);
 
-    r300->rws->cs_destroy(r300->cs);
+    if (r300->cs)
+        r300->rws->cs_destroy(r300->cs);
 
+    /* XXX: No way to tell if this was initialized or not? */
     util_mempool_destroy(&r300->pool_transfers);
 
     r300_update_num_contexts(r300->screen, -1);
 
-    FREE(r300->aa_state.state);
-    FREE(r300->blend_color_state.state);
-    FREE(r300->clip_state.state);
-    FREE(r300->fb_state.state);
-    FREE(r300->gpu_flush.state);
-    FREE(r300->hyperz_state.state);
-    FREE(r300->invariant_state.state);
-    FREE(r300->rs_block_state.state);
-    FREE(r300->scissor_state.state);
-    FREE(r300->textures_state.state);
-    FREE(r300->vap_invariant_state.state);
-    FREE(r300->viewport_state.state);
-    FREE(r300->ztop_state.state);
-    FREE(r300->fs_constants.state);
-    FREE(r300->vs_constants.state);
-    if (!r300->screen->caps.has_tcl) {
-        FREE(r300->vertex_stream_state.state);
+    /* Free the structs allocated in r300_setup_atoms() */
+    if (r300->aa_state.state) {
+        FREE(r300->aa_state.state);
+        FREE(r300->blend_color_state.state);
+        FREE(r300->clip_state.state);
+        FREE(r300->fb_state.state);
+        FREE(r300->gpu_flush.state);
+        FREE(r300->hyperz_state.state);
+        FREE(r300->invariant_state.state);
+        FREE(r300->rs_block_state.state);
+        FREE(r300->scissor_state.state);
+        FREE(r300->textures_state.state);
+        FREE(r300->vap_invariant_state.state);
+        FREE(r300->viewport_state.state);
+        FREE(r300->ztop_state.state);
+        FREE(r300->fs_constants.state);
+        FREE(r300->vs_constants.state);
+        if (r300->vertex_stream_state.state) {
+            FREE(r300->vertex_stream_state.state);
+        }
     }
     FREE(r300);
 }
@@ -406,12 +416,16 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
 
     r300->context.destroy = r300_destroy_context;
 
-    r300->cs = rws->cs_create(rws);
+    make_empty_list(&r300->query_list);
 
     util_mempool_create(&r300->pool_transfers,
                         sizeof(struct pipe_transfer), 64,
                         UTIL_MEMPOOL_SINGLETHREADED);
 
+    r300->cs = rws->cs_create(rws);
+    if (r300->cs == NULL)
+        goto fail;
+
     if (!r300screen->caps.has_tcl) {
         /* Create a Draw. This is used for SW TCL. */
         r300->draw = draw_create(&r300->context);
@@ -426,8 +440,6 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
 
     r300_setup_atoms(r300);
 
-    make_empty_list(&r300->query_list);
-
     r300_init_blit_functions(r300);
     r300_init_flush_functions(r300);
     r300_init_query_functions(r300);
@@ -435,6 +447,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
     r300_init_resource_functions(r300);
 
     r300->blitter = util_blitter_create(&r300->context);
+    if (r300->blitter == NULL)
+        goto fail;
 
     /* Render functions must be initialized after blitter. */
     r300_init_render_functions(r300);
@@ -450,15 +464,17 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
 				      PIPE_BIND_INDEX_BUFFER);
 
     if (r300->upload_ib == NULL)
-        goto no_upload_ib;
+        goto fail;
 
     r300->upload_vb = u_upload_create(&r300->context,
 				      128 * 1024, 16,
 				      PIPE_BIND_VERTEX_BUFFER);
     if (r300->upload_vb == NULL)
-        goto no_upload_vb;
+        goto fail;
 
     r300->tran.translate_cache = translate_cache_create();
+    if (r300->tran.translate_cache == NULL)
+        goto fail;
 
     r300_init_states(&r300->context);
 
@@ -488,10 +504,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
 
     return &r300->context;
 
- no_upload_ib:
-    u_upload_destroy(r300->upload_ib);
- no_upload_vb:
-    FREE(r300);
+ fail:
+    r300_destroy_context(&r300->context);
     return NULL;
 }
 
-- 
cgit v1.2.3


From e897bf524beae417252a1bf1b6bbd354902a57d7 Mon Sep 17 00:00:00 2001
From: nobled <nobled@dreamwidth.org>
Date: Sun, 15 Aug 2010 03:53:18 +0000
Subject: r300g: Let hyperz init fail
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Marek Olšák <maraeo@gmail.com>
---
 src/gallium/drivers/r300/r300_context.c |  3 ++-
 src/gallium/drivers/r300/r300_hyperz.c  | 21 +++++++++++++++++----
 src/gallium/drivers/r300/r300_hyperz.h  |  2 +-
 3 files changed, 20 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index 25b39c566c..d783f21f5f 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -457,7 +457,8 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
 
     /* setup hyper-z mm */
     if (r300->rws->get_value(r300->rws, R300_CAN_HYPERZ))
-        r300_hyperz_init_mm(r300);
+        if (!r300_hyperz_init_mm(r300))
+            goto fail;
 
     r300->upload_ib = u_upload_create(&r300->context,
 				      32 * 1024, 16,
diff --git a/src/gallium/drivers/r300/r300_hyperz.c b/src/gallium/drivers/r300/r300_hyperz.c
index 811b5646e1..a471b7353b 100644
--- a/src/gallium/drivers/r300/r300_hyperz.c
+++ b/src/gallium/drivers/r300/r300_hyperz.c
@@ -373,23 +373,36 @@ void r300_zmask_alloc_block(struct r300_context *r300, struct r300_surface *surf
     return;
 }
 
-void r300_hyperz_init_mm(struct r300_context *r300)
+boolean r300_hyperz_init_mm(struct r300_context *r300)
 {
     struct r300_screen* r300screen = r300->screen;
     int frag_pipes = r300screen->caps.num_frag_pipes;
 
-    if (r300screen->caps.hiz_ram)
+    r300->zmask_mm = u_mmInit(0, r300screen->caps.zmask_ram * frag_pipes);
+    if (!r300->zmask_mm)
+      return FALSE;
+
+    if (r300screen->caps.hiz_ram) {
       r300->hiz_mm = u_mmInit(0, r300screen->caps.hiz_ram * frag_pipes);
+      if (!r300->hiz_mm) {
+        u_mmDestroy(r300->zmask_mm);
+        r300->zmask_mm = NULL;
+        return FALSE;
+      }
+    }
 
-    r300->zmask_mm = u_mmInit(0, r300screen->caps.zmask_ram * frag_pipes);
+    return TRUE;
 }
 
 void r300_hyperz_destroy_mm(struct r300_context *r300)
 {
     struct r300_screen* r300screen = r300->screen;
 
-    if (r300screen->caps.hiz_ram)
+    if (r300screen->caps.hiz_ram) {
       u_mmDestroy(r300->hiz_mm);
+      r300->hiz_mm = NULL;
+    }
 
     u_mmDestroy(r300->zmask_mm);
+    r300->zmask_mm = NULL;
 }
diff --git a/src/gallium/drivers/r300/r300_hyperz.h b/src/gallium/drivers/r300/r300_hyperz.h
index 09e1ff6625..30a23ec649 100644
--- a/src/gallium/drivers/r300/r300_hyperz.h
+++ b/src/gallium/drivers/r300/r300_hyperz.h
@@ -30,6 +30,6 @@ void r300_update_hyperz_state(struct r300_context* r300);
 void r300_hiz_alloc_block(struct r300_context *r300, struct r300_surface *surf);
 void r300_zmask_alloc_block(struct r300_context *r300, struct r300_surface *surf, int compress);
 
-void r300_hyperz_init_mm(struct r300_context *r300);
+boolean r300_hyperz_init_mm(struct r300_context *r300);
 void r300_hyperz_destroy_mm(struct r300_context *r300);
 #endif
-- 
cgit v1.2.3


From ecae1fca6f93eafb1916aa8621be04edd9228041 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Mon, 16 Aug 2010 05:05:43 +0200
Subject: r300g: fix an invalid pointer in free

---
 src/gallium/drivers/r300/r300_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index d783f21f5f..a83ad892ea 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -153,7 +153,7 @@ static void r300_destroy_context(struct pipe_context* context)
         FREE(r300->ztop_state.state);
         FREE(r300->fs_constants.state);
         FREE(r300->vs_constants.state);
-        if (r300->vertex_stream_state.state) {
+        if (!r300->screen->caps.has_tcl) {
             FREE(r300->vertex_stream_state.state);
         }
     }
-- 
cgit v1.2.3


From ecec6df9cfe74dbd16f072bc4bbcd90374f8d2c8 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Mon, 16 Aug 2010 19:17:02 +0200
Subject: r300g: fix assert in the rasterizer block for r3xx-r4xx

Reported-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
---
 src/gallium/drivers/r300/r300_state_derived.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_state_derived.c b/src/gallium/drivers/r300/r300_state_derived.c
index 4a63ed7fc1..c8de3e1c52 100644
--- a/src/gallium/drivers/r300/r300_state_derived.c
+++ b/src/gallium/drivers/r300/r300_state_derived.c
@@ -211,7 +211,7 @@ static void r300_rs_col(struct r300_rs_block* rs, int id, int ptr,
 static void r300_rs_col_write(struct r300_rs_block* rs, int id, int fp_offset,
                               enum r300_rs_col_write_type type)
 {
-    assert(type != WRITE_COLOR);
+    assert(type == WRITE_COLOR);
     rs->inst[id] |= R300_RS_INST_COL_CN_WRITE |
                     R300_RS_INST_COL_ADDR(fp_offset);
 }
-- 
cgit v1.2.3


From 3e58007892cb2e89cb979ab172b7160adc84a44d Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 17 Aug 2010 13:40:15 +1000
Subject: r600g: add user clip plane support.

Apart from the fact that the radeon.h/r600_states.h editing is a nightmare, this
wasn't so bad.

passes piglit user-clip test now also trivial tests.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c      |  4 ++-
 src/gallium/drivers/r600/r600_context.h   |  1 +
 src/gallium/drivers/r600/r600_state.c     | 56 ++++++++++++++++++++++++++++++-
 src/gallium/drivers/r600/radeon.h         | 23 +++++++++----
 src/gallium/winsys/r600/drm/r600_states.h | 18 +++++++---
 5 files changed, 89 insertions(+), 13 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index f4eedfe4cb..db7aef7ebd 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -47,12 +47,14 @@ static void r600_blitter_save_states(struct r600_context *rctx)
 	if (rctx->viewport) {
 		util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
 	}
-	/* XXX util_blitter_save_clip(rctx->blitter, &rctx->clip); */
+	if (rctx->clip)
+ 	    util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
 	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
 					rctx->vertex_buffer);
 
 	/* remove ptr so they don't get deleted */
 	rctx->blend = NULL;
+	rctx->clip = NULL;
 	rctx->vs_shader = NULL;
 	rctx->ps_shader = NULL;
 	rctx->rasterizer = NULL;
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 76d5de8653..2ce29720d9 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -98,6 +98,7 @@ struct r600_context_hw_states {
 	struct radeon_state	*config;
 	struct radeon_state	*cb_cntl;
 	struct radeon_state	*db;
+	struct radeon_state	*ucp[6];
 	unsigned		ps_nresource;
 	unsigned		ps_nsampler;
 	struct radeon_state	*ps_resource[160];
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 3efd409ae0..cbbc93c04a 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -268,6 +268,14 @@ static void r600_set_blend_color(struct pipe_context *ctx,
 static void r600_set_clip_state(struct pipe_context *ctx,
 				const struct pipe_clip_state *state)
 {
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_context_state *rstate;
+
+	rstate = r600_context_state(rctx, pipe_clip_type, state);
+	r600_bind_state(ctx, rstate);
+	/* refcount is taken care of this */
+	r600_delete_state(ctx, rstate);
 }
 
 static void r600_set_constant_buffer(struct pipe_context *ctx,
@@ -668,6 +676,29 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	return rstate;
 }
 
+static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+	const struct pipe_clip_state *state = &rctx->clip->state.clip;
+
+	rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
+	if (rstate == NULL)
+		return NULL;
+
+	rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
+	rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
+	rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
+	rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+
+}
+
 static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 {
 	struct r600_screen *rscreen = rctx->screen;
@@ -769,6 +800,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 {
 	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
 	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+	const struct pipe_clip_state *clip = NULL;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 	float offset_units = 0, offset_scale = 0;
@@ -776,6 +808,9 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	unsigned offset_db_fmt_cntl = 0;
 	unsigned tmp;
 	unsigned prov_vtx = 1;
+
+	if (rctx->clip)
+		clip = &rctx->clip->state.clip;
 	if (fb->zsbuf) {
 		offset_units = state->offset_units;
 		offset_scale = state->offset_scale * 12.0f;
@@ -821,7 +856,11 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 					S_0286D4_PNT_SPRITE_TOP_1(1);
 		}
 	}
-	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0x00000000;
+	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
+	if (clip && clip->nr) {
+		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
+		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_CLIP_DISABLE(clip->depth_clamp);
+	}
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
 		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 		S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
@@ -1301,6 +1340,10 @@ int r600_context_hw_states(struct r600_context *rctx)
 	unsigned i;
 	int r;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
+	int ucp_nclip = 0;
+
+	if (rctx->clip) 
+		ucp_nclip = rctx->clip->state.clip.nr;
 
 	/* free previous TODO determine what need to be updated, what
 	 * doesn't
@@ -1316,6 +1359,9 @@ int r600_context_hw_states(struct r600_context *rctx)
 	for (i = 0; i < 8; i++) {
 		rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
 	}
+	for (i = 0; i < 6; i++) {
+		rctx->hw_states.ucp[i] = radeon_state_decref(rctx->hw_states.ucp[i]);
+	}
 	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
 		radeon_state_decref(rctx->hw_states.ps_resource[i]);
 		rctx->hw_states.ps_resource[i] = NULL;
@@ -1336,6 +1382,9 @@ int r600_context_hw_states(struct r600_context *rctx)
 	for (i = 0; i < nr_cbufs; i++) {
 		rctx->hw_states.cb[i] = r600_cb(rctx, i);
 	}
+	for (i = 0; i < ucp_nclip; i++) {
+		rctx->hw_states.ucp[i] = r600_ucp(rctx, i);
+	}
 	rctx->hw_states.db = r600_db(rctx);
 	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
 
@@ -1357,6 +1406,11 @@ int r600_context_hw_states(struct r600_context *rctx)
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
 
 	/* bind states */
+	for (i = 0; i < ucp_nclip; i++) {
+		r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp[i]);
+		if (r)
+			return r;
+	}
 	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
 	if (r)
 		return r;
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 8f00a4895a..d36c89d6a7 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -191,8 +191,8 @@ struct radeon_ctx {
  * R600/R700
  */
 
-#define R600_NSTATE				1280
-#define R600_NTYPE				32
+#define R600_NSTATE				1286
+#define R600_NTYPE				33
 
 #define R600_CONFIG				0
 #define R600_CONFIG_TYPE				0
@@ -254,10 +254,13 @@ struct radeon_ctx {
 #define R600_CB7_TYPE				28
 #define R600_DB				1277
 #define R600_DB_TYPE				29
-#define R600_VGT				1278
-#define R600_VGT_TYPE				30
-#define R600_DRAW				1279
-#define R600_DRAW_TYPE				31
+#define R600_CLIP				1278
+#define R600_CLIP_TYPE				30
+#define R600_VGT				1284
+#define R600_VGT_TYPE				31
+#define R600_DRAW				1285
+#define R600_DRAW_TYPE				32
+
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			1
@@ -643,5 +646,11 @@ struct radeon_ctx {
 #define R600_DRAW__VGT_DRAW_INITIATOR			3
 #define R600_DRAW_SIZE				4
 #define R600_DRAW_PM4				128
-
+/* R600_CLIP */
+#define R600_CLIP__PA_CL_UCP_X_0  0
+#define R600_CLIP__PA_CL_UCP_Y_0  1
+#define R600_CLIP__PA_CL_UCP_Z_0  2
+#define R600_CLIP__PA_CL_UCP_W_0  3
+#define R600_CLIP_SIZE  4
+#define R600_CLIP_PM4 128
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index e40c77d8f6..2d7a1d31c8 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -283,6 +283,13 @@ static const struct radeon_register R600_VS_CONSTANT_names[] = {
 	{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
 };
 
+static const struct radeon_register R600_UCP_names[] = {
+	{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
+	{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
+	{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
+	{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
+};
+
 static const struct radeon_register R600_PS_RESOURCE_names[] = {
 	{0x00038000, 0, 0, "RESOURCE0_WORD0"},
 	{0x00038004, 0, 0, "RESOURCE0_WORD1"},
@@ -503,8 +510,10 @@ static struct radeon_type R600_types[] = {
 	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
 	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
 	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
-	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+
 };
 
 static struct radeon_type R700_types[] = {
@@ -538,8 +547,9 @@ static struct radeon_type R700_types[] = {
 	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
 	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
 	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
-	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 #endif
-- 
cgit v1.2.3


From 1c2a44e445fa4d3bd6f95d9c63041c222268724a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 17 Aug 2010 19:01:18 +1000
Subject: r300g: fix context destroy under hyperz

we were destroying the mm before unrefing all the objects, so segfault.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r300/r300_context.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index a83ad892ea..852d88af54 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -119,15 +119,15 @@ static void r300_destroy_context(struct pipe_context* context)
     if (r300->upload_ib)
         u_upload_destroy(r300->upload_ib);
 
-    if (r300->zmask_mm)
-        r300_hyperz_destroy_mm(r300);
-
     if (r300->tran.translate_cache)
         translate_cache_destroy(r300->tran.translate_cache);
 
     /* XXX: This function assumes r300->query_list was initialized */
     r300_release_referenced_objects(r300);
 
+    if (r300->zmask_mm)
+        r300_hyperz_destroy_mm(r300);
+
     if (r300->cs)
         r300->rws->cs_destroy(r300->cs);
 
-- 
cgit v1.2.3


From 608f749ec3fc655d3e67e572fa2e256a42c16878 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Tue, 17 Aug 2010 17:23:20 -0400
Subject: r600g: fix fake pixel output

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 956c7e7930..55247f159d 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -504,7 +504,7 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 		output[0].swizzle_z = 7;
 		output[0].swizzle_w = 7;
 		output[0].barrier = 1;
-		output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PARAM;
+		output[0].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 		output[0].array_base = 0;
 		output[0].inst = V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT;
 		noutput++;
-- 
cgit v1.2.3


From 1d18739290fa667dc81d6780d695a09f8c1cde99 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 09:56:21 +1000
Subject: r600g: emit texture level offset in CB/DB setup.

8 more piglit tests pass,
fbo-clearmipmap, fbo-copyteximage, fbo-generatemipmap,
fbo-generatemipmap-nonsquare, fbo-generatemipmap-scissor,
fbo-generatemipmap-viewport, gen-teximage, gen-texsubimage
---
 src/gallium/drivers/r600/r600_state.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index cbbc93c04a..0059952cef 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -741,7 +741,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 		S_0280A0_SOURCE_FORMAT(1) |
 		S_0280A0_NUMBER_TYPE(ntype);
 
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
 	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
@@ -782,7 +782,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
 	format = r600_translate_dbformat(state->zsbuf->texture->format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = 0x00000000;
+	rstate->states[R600_DB__DB_DEPTH_BASE] = rtex->offset[level] >> 8;
 	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
 					S_028010_FORMAT(format);
 	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-- 
cgit v1.2.3


From edb465e9bb1b45a6db5aca85a002c0f4958deff0 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 10:50:19 +1000
Subject: r600g: fix height calcs for miptree

h needs to be rounded up, this probably needs revisiting when we get
to tiling etc.

fixes fbo-generatemipmap-npot
---
 src/gallium/drivers/r600/r600_texture.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 30d79ebdd6..55cceb6935 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -65,6 +65,7 @@ static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource
 	for (i = 0, offset = 0; i <= ptex->last_level; i++) {
 		w = u_minify(ptex->width0, i);
 		h = u_minify(ptex->height0, i);
+		h = util_next_power_of_two(h);
 		pitch = util_format_get_stride(ptex->format, align(w, 64));
 		layer_size = pitch * h;
 		if (ptex->target == PIPE_TEXTURE_CUBE)
-- 
cgit v1.2.3


From 03c59e4ab16b0ee362f189b549bd13491dba71e4 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 11:49:51 +1000
Subject: r600g: fixup pitch alignment like r600c.

This still needs work, passes tex3d, fbo-scissor-bitmap, scissor-bitmap
---
 src/gallium/drivers/r600/r600_state.c   | 9 ++++++---
 src/gallium/drivers/r600/r600_texture.c | 1 +
 2 files changed, 7 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 0059952cef..260688a9a8 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1217,7 +1217,7 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	struct r600_resource *rbuffer;
 	struct radeon_state *rstate;
 	unsigned format;
-	uint32_t word4 = 0, yuv_format = 0;
+	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 	unsigned char swizzle[4];
 
 	swizzle[0] = view->swizzle_r;
@@ -1248,16 +1248,19 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
 
+	pitch = (tmp->pitch[0] / tmp->bpt);
+	pitch = (pitch + 0x7) & ~0x7;
+	
 	/* FIXME properly handle first level != 0 */
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
-			S_038000_PITCH(((tmp->pitch[0] / tmp->bpt) / 8) - 1) |
+	                S_038000_PITCH((pitch / 8) - 1) |
 			S_038000_TEX_WIDTH(view->texture->width0 - 1);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
 			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
 			S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
 			S_038004_DATA_FORMAT(format);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = 0;
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
 		        word4 | 
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 55cceb6935..eabd7f7705 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -67,6 +67,7 @@ static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource
 		h = u_minify(ptex->height0, i);
 		h = util_next_power_of_two(h);
 		pitch = util_format_get_stride(ptex->format, align(w, 64));
+		pitch = align(pitch, 256);
 		layer_size = pitch * h;
 		if (ptex->target == PIPE_TEXTURE_CUBE)
 			size = layer_size * 6;
-- 
cgit v1.2.3


From 1147814365c78ed20ba71e3f4e0bfe22f9960234 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 13:29:41 +1000
Subject: r600g: fix point size

fixes piglit pointAtten and point-sprite tests
---
 src/gallium/drivers/r600/r600_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 260688a9a8..f78d1671ba 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -874,7 +874,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 			S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
 	rstate->states[R600_RASTERIZER__PA_CL_NANINF_CNTL] = 0x00000000;
 	/* point size 12.4 fixed point */
-	tmp = (unsigned)(state->point_size * 8.0 / 2.0);
+	tmp = (unsigned)(state->point_size * 8.0);
 	rstate->states[R600_RASTERIZER__PA_SU_POINT_SIZE] = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
 	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
 	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
-- 
cgit v1.2.3


From 4558b634556f42867449a6e60d4badc72099f10d Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 13:48:04 +1000
Subject: r600g: add two simple tgsi opcodes.

makes glsl-fs-log2 and glsl1-integer division with uniform var pass
---
 src/gallium/drivers/r600/r600_shader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 55247f159d..a45d63b34b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1237,7 +1237,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_FLR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_XPD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	/* gap */
@@ -1297,7 +1297,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_CEIL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_I2F,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_NOT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TRUNC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TRUNC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_SHL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	/* gap */
 	{88,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-- 
cgit v1.2.3


From b777db32541b360516203865a0fa41f4b8cebf7c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 15:05:34 +1000
Subject: r600g: fix TXP vs TEX in shader.

Don't do perspective for TEX, and also copy input to a temporary for TEX

also add tex opcode names
---
 src/gallium/drivers/r600/r600_shader.c | 125 ++++++++++++++++-----------------
 src/gallium/drivers/r600/r600d.h       |   7 ++
 2 files changed, 67 insertions(+), 65 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index a45d63b34b..c45aa7772a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1035,73 +1035,68 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	struct r600_bc_tex tex;
 	struct r600_bc_alu alu;
 	unsigned src_gpr;
-	int r;
+	int r, i;
 
 	src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
 
-	/* Add perspective divide */
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
-	alu.src[0].sel = src_gpr;
-	alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
-	alu.dst.sel = ctx->temp_reg;
-	alu.dst.chan = 3;
-	alu.last = 1;
-	alu.dst.write = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
-
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-	alu.src[0].sel = ctx->temp_reg;
-	alu.src[0].chan = 3;
-	alu.src[1].sel = src_gpr;
-	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
-	alu.dst.sel = ctx->temp_reg;
-	alu.dst.chan = 0;
-	alu.dst.write = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-	alu.src[0].sel = ctx->temp_reg;
-	alu.src[0].chan = 3;
-	alu.src[1].sel = src_gpr;
-	alu.src[1].chan = tgsi_chan(&inst->Src[0], 1);
-	alu.dst.sel = ctx->temp_reg;
-	alu.dst.chan = 1;
-	alu.dst.write = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
-	alu.src[0].sel = ctx->temp_reg;
-	alu.src[0].chan = 3;
-	alu.src[1].sel = src_gpr;
-	alu.src[1].chan = tgsi_chan(&inst->Src[0], 2);
-	alu.dst.sel = ctx->temp_reg;
-	alu.dst.chan = 2;
-	alu.dst.write = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-	alu.src[0].sel = 249;
-	alu.src[0].chan = 0;
-	alu.dst.sel = ctx->temp_reg;
-	alu.dst.chan = 3;
-	alu.last = 1;
-	alu.dst.write = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
-	src_gpr = ctx->temp_reg;
+	if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
+		/* Add perspective divide */
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
+		alu.src[0].sel = src_gpr;
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 3;
+		alu.last = 1;
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+		
+		for (i = 0; i < 3; i++) {
+			memset(&alu, 0, sizeof(struct r600_bc_alu));
+			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+			alu.src[0].sel = ctx->temp_reg;
+			alu.src[0].chan = 3;
+			alu.src[1].sel = src_gpr;
+			alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
+			alu.dst.sel = ctx->temp_reg;
+			alu.dst.chan = i;
+			alu.dst.write = 1;
+			r = r600_bc_add_alu(ctx->bc, &alu);
+			if (r)
+				return r;
+		}
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+		alu.src[0].sel = 249;
+		alu.src[0].chan = 0;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 3;
+		alu.last = 1;
+		alu.dst.write = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+		src_gpr = ctx->temp_reg;
+	} else if (inst->Src[0].Register.File != TGSI_FILE_TEMPORARY) {
+		for (i = 0; i < 4; i++) {
+			memset(&alu, 0, sizeof(struct r600_bc_alu));
+			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+			alu.src[0].sel = src_gpr;
+			alu.src[0].chan = i;
+			alu.dst.sel = ctx->temp_reg;
+			alu.dst.chan = i;
+			if (i == 3)
+				alu.last = 1;
+			alu.dst.write = 1;
+			r = r600_bc_add_alu(ctx->bc, &alu);
+			if (r)
+				return r;
+		}
+		src_gpr = ctx->temp_reg;
+	}
 
-	/* TODO use temp if src_gpr is not a temporary reg (File != TEMPORARY) */
 	memset(&tex, 0, sizeof(struct r600_bc_tex));
 	tex.inst = ctx->inst_info->r600_opcode;
 	tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
@@ -1261,9 +1256,9 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TEX,	0, 0x10, tgsi_tex},
+	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
 	{TGSI_OPCODE_TXD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXP,	0, 0x10, tgsi_tex},
+	{TGSI_OPCODE_TXP,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
 	{TGSI_OPCODE_UP2H,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_UP2US,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_UP4B,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 53388f822e..9bdfe4f966 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -1316,4 +1316,11 @@
 #define   G_0286D4_PNT_SPRITE_TOP_1(x)                 (((x) >> 14) & 0x1)
 #define   C_0286D4_PNT_SPRITE_TOP_1                    0xFFFFBFFF
 
+#define SQ_TEX_INST_LD 0x03
+#define SQ_TEX_INST_GET_GRADIENTS_H 0x7
+#define SQ_TEX_INST_GET_GRADIENTS_V 0x8
+
+#define SQ_TEX_INST_SAMPLE 0x10
+#define SQ_TEX_INST_SAMPLE_L 0x11
+#define SQ_TEX_INST_SAMPLE_C 0x18
 #endif
-- 
cgit v1.2.3


From d01c0025e81e713d99f4de9ed7f4cdd12a1d08b5 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 15:26:28 +1000
Subject: r600g: add TXB support

fixes biased texturing tests
---
 src/gallium/drivers/r600/r600_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index c45aa7772a..ea1dd1ebe2 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1272,7 +1272,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SSG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* SGN */
 	{TGSI_OPCODE_CMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SCS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_TXB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
 	{TGSI_OPCODE_NRM,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DIV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DP2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-- 
cgit v1.2.3


From be288c3505429811adc2743c1be2c1971f4483a2 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 15:53:29 +1000
Subject: r600g: add SGE and SLE opcodes

fixes fp-set-01 and glsl-fs-step
---
 src/gallium/drivers/r600/r600_shader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index ea1dd1ebe2..1487c4e8b7 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1216,7 +1216,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
 	{TGSI_OPCODE_MAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
 	{TGSI_OPCODE_SLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
-	{TGSI_OPCODE_SGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
 	{TGSI_OPCODE_MAD,	1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
 	{TGSI_OPCODE_SUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
 	{TGSI_OPCODE_LRP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lrp},
@@ -1253,7 +1253,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SFL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SGT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_slt},
 	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-- 
cgit v1.2.3


From 3af87162cd0d3107cb2af0812ce4e4680b177725 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 18 Aug 2010 16:10:16 +1000
Subject: r600g: add FRC, FLR, DDX and DDY

the first two are straight op2's and the DDX/DDY are taken from r600c.
---
 src/gallium/drivers/r600/r600_shader.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 1487c4e8b7..828082d10b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1227,9 +1227,9 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	/* gap */
 	{22,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{23,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FRC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FRC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
 	{TGSI_OPCODE_CLAMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_FLR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_FLR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
 	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
@@ -1241,8 +1241,8 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_RCC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DPH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DDX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DDY,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
+	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
 	{TGSI_OPCODE_KILP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},  /* predicated kill */
 	{TGSI_OPCODE_PK2H,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_PK2US,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-- 
cgit v1.2.3


From 0d48925a56ad4fb253386110b545abda82a25464 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 19 Aug 2010 11:41:18 +1000
Subject: r600g: add SSG, SEQ, SGT and SNE

---
 src/gallium/drivers/r600/r600_shader.c | 84 +++++++++++++++++++++++++++++-----
 src/gallium/drivers/r600/r600_sq.h     | 16 +++++++
 2 files changed, 88 insertions(+), 12 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 828082d10b..3caeaa3a2a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -684,7 +684,7 @@ static int tgsi_kill(struct r600_shader_ctx *ctx)
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = ctx->inst_info->r600_opcode;
 		alu.dst.chan = i;
-		alu.src[0].sel = 248;
+		alu.src[0].sel = SQ_ALU_SRC_0;
 		r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
 		if (r)
 			return r;
@@ -743,7 +743,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	/* dst.x, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
 	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-	alu.src[0].sel  = 249; /*1.0*/
+	alu.src[0].sel  = SQ_ALU_SRC_1; /*1.0*/
 	alu.src[0].chan = 0;
 	r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
 	if (r)
@@ -759,7 +759,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
 	if (r)
 		return r;
-	alu.src[1].sel  = 248; /*0.0*/
+	alu.src[1].sel  = SQ_ALU_SRC_0; /*0.0*/
 	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
 	r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
 	if (r)
@@ -780,7 +780,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	/* dst.w, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
 	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-	alu.src[0].sel  = 249;
+	alu.src[0].sel  = SQ_ALU_SRC_1;
 	alu.src[0].chan = 0;
 	r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
 	if (r)
@@ -919,6 +919,66 @@ static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_ssg(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	struct r600_bc_alu_src r600_src[3];
+	int i, j, r;
+
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+
+	/* tmp = (src > 0 ? 1 : src) */
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
+		alu.is_op3 = 1;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.write = 1;
+
+		alu.src[0] = r600_src[0];
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
+
+		alu.src[1].sel = SQ_ALU_SRC_1;
+
+		alu.src[2] = r600_src[0];
+		alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+
+	/* dst = (-tmp > 0 ? -1 : tmp) */
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
+		alu.is_op3 = 1;
+		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+		if (r)
+			return r;
+
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].neg = 1;
+
+		alu.src[1].sel = SQ_ALU_SRC_1;
+		alu.src[1].neg = 1;
+
+		alu.src[2].sel = ctx->temp_reg;
+
+		alu.dst.write = 1;
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return 0;
+}
+
 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
 {
 	struct r600_bc_alu alu;
@@ -1006,13 +1066,13 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
 		switch (ctx->inst_info->tgsi_opcode) {
 		case TGSI_OPCODE_DP2:
 			if (i > 1) {
-				alu.src[0].sel = alu.src[1].sel = 248;
+				alu.src[0].sel = alu.src[1].sel = SQ_ALU_SRC_0;
 				alu.src[0].chan = alu.src[1].chan = 0;
 			}
 			break;
 		case TGSI_OPCODE_DP3:
 			if (i > 2) {
-				alu.src[0].sel = alu.src[1].sel = 248;
+				alu.src[0].sel = alu.src[1].sel = SQ_ALU_SRC_0;
 				alu.src[0].chan = alu.src[1].chan = 0;
 			}
 			break;
@@ -1069,7 +1129,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		}
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-		alu.src[0].sel = 249;
+		alu.src[0].sel = SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = 3;
@@ -1136,7 +1196,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD;
-		alu.src[0].sel = 249;
+		alu.src[0].sel = SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 		alu.src[1] = r600_src[0];
 		alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
@@ -1249,12 +1309,12 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_PK4B,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_PK4UB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_RFL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SEQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SEQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
 	{TGSI_OPCODE_SFL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SGT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SGT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
 	{TGSI_OPCODE_SIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_slt},
-	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
 	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
 	{TGSI_OPCODE_TXD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -1269,7 +1329,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_BRA,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_CAL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_RET,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_SSG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, /* SGN */
+	{TGSI_OPCODE_SSG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
 	{TGSI_OPCODE_CMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SCS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index 002660c654..b0ad3d24bd 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -583,4 +583,20 @@
 #define   G_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) >> 29) & 0x7)
 #define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
 
+/*
+ * 248	SQ_ALU_SRC_0: special constant 0.0.
+ * 249	SQ_ALU_SRC_1: special constant 1.0 float.
+ * 250	SQ_ALU_SRC_1_INT: special constant 1 integer.
+ * 251	SQ_ALU_SRC_M_1_INT: special constant -1 integer.
+ * 252	SQ_ALU_SRC_0_5: special constant 0.5 float.
+ * 253	SQ_ALU_SRC_LITERAL: literal constant.
+ * 254	SQ_ALU_SRC_PV: previous vector result.
+ * 255	SQ_ALU_SRC_PS: previous scalar result.
+ */
+#define SQ_ALU_SRC_0 248
+#define SQ_ALU_SRC_1 249
+#define SQ_ALU_SRC_1_INT 250
+#define SQ_ALU_SRC_M_1_INT 251
+#define SQ_ALU_SRC_0_5 252
+
 #endif
-- 
cgit v1.2.3


From 098064e8cb6950f60c51a44e280cb335f07920b1 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 19 Aug 2010 14:43:11 +1000
Subject: r600g: add a chiprev type for r600/r700/evergreen instead of using
 family

---
 src/gallium/drivers/r600/r600_asm.c | 37 ++++++++++++++++++++++++-------------
 src/gallium/drivers/r600/r600_asm.h |  1 +
 2 files changed, 25 insertions(+), 13 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 9ea9d4354d..e6efae4c56 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -76,6 +76,27 @@ int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
 {
 	LIST_INITHEAD(&bc->cf);
 	bc->family = family;
+	switch (bc->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+		bc->chiprev = 0;
+		break;
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		bc->chiprev = 1;
+		break;
+	default:
+		R600_ERR("unknown family %d\n", bc->family);
+		return -EINVAL;
+	}
 	return 0;
 }
 
@@ -418,21 +439,11 @@ int r600_bc_build(struct r600_bc *bc)
 		switch (cf->inst) {
 		case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
 			LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
-				switch (bc->family) {
-				case CHIP_R600:
-				case CHIP_RV610:
-				case CHIP_RV630:
-				case CHIP_RV670:
-				case CHIP_RV620:
-				case CHIP_RV635:
-				case CHIP_RS780:
-				case CHIP_RS880:
+				switch(bc->chiprev) {
+				case 0:
 					r = r600_bc_alu_build(bc, alu, addr);
 					break;
-				case CHIP_RV770:
-				case CHIP_RV730:
-				case CHIP_RV710:
-				case CHIP_RV740:
+				case 1:
 					r = r700_bc_alu_build(bc, alu, addr);
 					break;
 				default:
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 10d98afaf0..e944bd02de 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -122,6 +122,7 @@ struct r600_bc_cf {
 
 struct r600_bc {
 	enum radeon_family		family;
+	int chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
 	struct list_head		cf;
 	struct r600_bc_cf		*cf_last;
 	unsigned			ndw;
-- 
cgit v1.2.3


From 88f5976484842671ecb2cefcfa91838a43032359 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 19 Aug 2010 14:43:44 +1000
Subject: r600g: add sin/cos

This pretty much ports the code from r600c, however it doesn't
always seem to work quite perfectly, but I can't find anything in this
code that is wrong. I'm guessing either literal input or constants
aren't working always.
---
 src/gallium/drivers/r600/r600_shader.c | 124 ++++++++++++++++++++++++++++++++-
 src/gallium/drivers/r600/r600_sq.h     |   1 +
 2 files changed, 123 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 3caeaa3a2a..4d390f9f62 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -674,6 +674,126 @@ static int tgsi_op2(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+/* 
+ * r600 - trunc to -PI..PI range
+ * r700 - normalize by dividing by 2PI
+ * see fdo bug 27901
+ */
+static int tgsi_trig(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
+	struct r600_bc_alu alu;
+	int i, r;
+	uint32_t lit_vals[4];
+
+	memset(lit_vals, 0, 4*4);
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+	lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
+	lit_vals[1] = fui(0.5f);
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
+	alu.is_op3 = 1;
+
+	alu.dst.chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+
+	alu.src[0] = r600_src[0];
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+		
+	alu.src[1].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[1].chan = 0;
+	alu.src[2].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[2].chan = 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	r = r600_bc_add_literal(ctx->bc, lit_vals);
+	if (r)
+		return r;
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
+		
+	alu.dst.chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 0;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+
+	if (ctx->bc->chiprev == 0) {
+		lit_vals[0] = fui(3.1415926535897f * 2.0f);
+		lit_vals[1] = fui(-3.1415926535897f);
+	} else {
+		lit_vals[0] = fui(1.0f);
+		lit_vals[1] = fui(-0.5f);
+	}
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
+	alu.is_op3 = 1;
+
+	alu.dst.chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 0;
+		
+	alu.src[1].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[1].chan = 0;
+	alu.src[2].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[2].chan = 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	r = r600_bc_add_literal(ctx->bc, lit_vals);
+	if (r)
+		return r;
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = ctx->inst_info->r600_opcode;
+	alu.dst.chan = 0;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 0;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+
+	/* replicate result */
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.src[0].sel = ctx->temp_reg;
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+		alu.dst.chan = i;
+		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+		if (r)
+			return r;
+		alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return 0;
+}
+
 static int tgsi_kill(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -1300,7 +1420,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_RCC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DPH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
 	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
 	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
 	{TGSI_OPCODE_KILP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},  /* predicated kill */
@@ -1312,7 +1432,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SEQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETE, tgsi_op2},
 	{TGSI_OPCODE_SFL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SGT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
-	{TGSI_OPCODE_SIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
 	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_slt},
 	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
 	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index b0ad3d24bd..da717783aa 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -598,5 +598,6 @@
 #define SQ_ALU_SRC_1_INT 250
 #define SQ_ALU_SRC_M_1_INT 251
 #define SQ_ALU_SRC_0_5 252
+#define SQ_ALU_SRC_LITERAL 253
 
 #endif
-- 
cgit v1.2.3


From 076c53879b90855ecf38602584f22e4ab6db7569 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Thu, 19 Aug 2010 12:06:20 -0400
Subject: r600g: update comments about ALU src operands

---
 src/gallium/drivers/r600/r600_shader.c | 10 ++++++++--
 src/gallium/drivers/r600/r600_sq.h     |  4 ++++
 2 files changed, 12 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 4d390f9f62..455730320e 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -362,9 +362,15 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	shader->processor_type = ctx.type;
 
 	/* register allocations */
-	/* Values [0,127] correspond to GPR[0..127]. 
-	 * Values [256,511] correspond to cfile constants c[0..255]. 
+	/* Values [0,127] correspond to GPR[0..127].
+	 * Values [128,159] correspond to constant buffer bank 0
+	 * Values [160,191] correspond to constant buffer bank 1
+	 * Values [256,511] correspond to cfile constants c[0..255].
 	 * Other special values are shown in the list below.
+	 * 244  ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
+	 * 245  ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
+	 * 246  ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
+	 * 247  ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
 	 * 248	SQ_ALU_SRC_0: special constant 0.0.
 	 * 249	SQ_ALU_SRC_1: special constant 1.0 float.
 	 * 250	SQ_ALU_SRC_1_INT: special constant 1 integer.
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index da717783aa..819624e689 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -584,6 +584,10 @@
 #define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
 
 /*
+ * 244  ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
+ * 245  ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
+ * 246  ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
+ * 247  ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
  * 248	SQ_ALU_SRC_0: special constant 0.0.
  * 249	SQ_ALU_SRC_1: special constant 1.0 float.
  * 250	SQ_ALU_SRC_1_INT: special constant 1 integer.
-- 
cgit v1.2.3


From 06991d87bedaaba5dde65027caa6fb49325b754e Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Thu, 19 Aug 2010 22:18:40 +0200
Subject: r300g: do not use fastfill with 16-bit zbuffers

To my knowledge, there is no way to flush zmask and thus write the clear
value.

This fixes zbuffer reads, among other things.
---
 src/gallium/drivers/r300/r300_hyperz.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_hyperz.c b/src/gallium/drivers/r300/r300_hyperz.c
index a471b7353b..b2526d6e41 100644
--- a/src/gallium/drivers/r300/r300_hyperz.c
+++ b/src/gallium/drivers/r300/r300_hyperz.c
@@ -357,6 +357,10 @@ void r300_zmask_alloc_block(struct r300_context *r300, struct r300_surface *surf
         tex->desc.b.b.target != PIPE_TEXTURE_2D)
         return;
 
+    /* Cannot flush zmask of 16-bit zbuffers. */
+    if (util_format_get_blocksizebits(tex->desc.b.b.format) == 16)
+        return;
+
     if (tex->zmask_mem[level])
         return;
 
-- 
cgit v1.2.3


From 11fde173c21039fdab18439641ffeb74bddaca9b Mon Sep 17 00:00:00 2001
From: Corbin Simpson <MostAwesomeDude@gmail.com>
Date: Thu, 19 Aug 2010 23:34:39 -0700
Subject: galahad: Make it obvious on stderr that Galahad's active.

---
 src/gallium/drivers/galahad/glhd_context.c | 2 ++
 src/gallium/drivers/galahad/glhd_screen.c  | 2 ++
 2 files changed, 4 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/galahad/glhd_context.c b/src/gallium/drivers/galahad/glhd_context.c
index fe14a287ef..ddf38860ab 100644
--- a/src/gallium/drivers/galahad/glhd_context.c
+++ b/src/gallium/drivers/galahad/glhd_context.c
@@ -972,5 +972,7 @@ galahad_context_create(struct pipe_screen *_screen, struct pipe_context *pipe)
 
    glhd_pipe->pipe = pipe;
 
+   glhd_warn("Created context %p", glhd_pipe);
+
    return &glhd_pipe->base;
 }
diff --git a/src/gallium/drivers/galahad/glhd_screen.c b/src/gallium/drivers/galahad/glhd_screen.c
index 4117485702..e1a1b59f20 100644
--- a/src/gallium/drivers/galahad/glhd_screen.c
+++ b/src/gallium/drivers/galahad/glhd_screen.c
@@ -330,5 +330,7 @@ galahad_screen_create(struct pipe_screen *screen)
 
    glhd_screen->screen = screen;
 
+   glhd_warn("Created screen %p", glhd_screen);
+
    return &glhd_screen->base;
 }
-- 
cgit v1.2.3


From cdc1c67b9896cd0d919f736fe61a4396bf0ad5c0 Mon Sep 17 00:00:00 2001
From: Corbin Simpson <MostAwesomeDude@gmail.com>
Date: Fri, 20 Aug 2010 00:00:40 -0700
Subject: galahad, i915g: Move over a few state asserts.

---
 src/gallium/drivers/galahad/glhd_context.c | 16 ++++++++++++++++
 src/gallium/drivers/i915/i915_state.c      |  3 ---
 2 files changed, 16 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/galahad/glhd_context.c b/src/gallium/drivers/galahad/glhd_context.c
index ddf38860ab..10e4679bf1 100644
--- a/src/gallium/drivers/galahad/glhd_context.c
+++ b/src/gallium/drivers/galahad/glhd_context.c
@@ -185,6 +185,12 @@ galahad_bind_fragment_sampler_states(struct pipe_context *_pipe,
    struct galahad_context *glhd_pipe = galahad_context(_pipe);
    struct pipe_context *pipe = glhd_pipe->pipe;
 
+   if (num_samplers > PIPE_MAX_SAMPLERS) {
+      glhd_error("%u fragment samplers requested, "
+         "but only %u are permitted by API",
+         num_samplers, PIPE_MAX_SAMPLERS);
+   }
+
    pipe->bind_fragment_sampler_states(pipe,
                                       num_samplers,
                                       samplers);
@@ -198,6 +204,12 @@ galahad_bind_vertex_sampler_states(struct pipe_context *_pipe,
    struct galahad_context *glhd_pipe = galahad_context(_pipe);
    struct pipe_context *pipe = glhd_pipe->pipe;
 
+   if (num_samplers > PIPE_MAX_VERTEX_SAMPLERS) {
+      glhd_error("%u vertex samplers requested, "
+         "but only %u are permitted by API",
+         num_samplers, PIPE_MAX_VERTEX_SAMPLERS);
+   }
+
    pipe->bind_vertex_sampler_states(pipe,
                                     num_samplers,
                                     samplers);
@@ -447,6 +459,10 @@ galahad_set_constant_buffer(struct pipe_context *_pipe,
    struct pipe_resource *unwrapped_resource;
    struct pipe_resource *resource = NULL;
 
+   if (shader >= PIPE_SHADER_TYPES) {
+      glhd_error("Unknown shader type %u", shader);
+   }
+
    /* XXX hmm? unwrap the input state */
    if (_resource) {
       unwrapped_resource = galahad_resource_unwrap(_resource);
diff --git a/src/gallium/drivers/i915/i915_state.c b/src/gallium/drivers/i915/i915_state.c
index 385c3b2d2d..cbddb214fb 100644
--- a/src/gallium/drivers/i915/i915_state.c
+++ b/src/gallium/drivers/i915/i915_state.c
@@ -294,8 +294,6 @@ static void i915_bind_sampler_states(struct pipe_context *pipe,
    struct i915_context *i915 = i915_context(pipe);
    unsigned i;
 
-   assert(num <= PIPE_MAX_SAMPLERS);
-
    /* Check for no-op */
    if (num == i915->num_samplers &&
        !memcmp(i915->sampler, sampler, num * sizeof(void *)))
@@ -529,7 +527,6 @@ static void i915_set_constant_buffer(struct pipe_context *pipe,
    struct i915_context *i915 = i915_context(pipe);
    draw_flush(i915->draw);
 
-   assert(shader < PIPE_SHADER_TYPES);
    assert(index == 0);
 
    /* Make a copy of shader constants.
-- 
cgit v1.2.3


From e0ef4800f5deb81ed57dccf8ba39e01c12f4beff Mon Sep 17 00:00:00 2001
From: Corbin Simpson <MostAwesomeDude@gmail.com>
Date: Fri, 20 Aug 2010 00:18:30 -0700
Subject: galahad, i915g: Copy over constant buffer index check.

---
 src/gallium/drivers/galahad/glhd_context.c | 9 +++++++++
 src/gallium/drivers/i915/i915_state.c      | 2 --
 2 files changed, 9 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/galahad/glhd_context.c b/src/gallium/drivers/galahad/glhd_context.c
index 10e4679bf1..383c448926 100644
--- a/src/gallium/drivers/galahad/glhd_context.c
+++ b/src/gallium/drivers/galahad/glhd_context.c
@@ -463,6 +463,15 @@ galahad_set_constant_buffer(struct pipe_context *_pipe,
       glhd_error("Unknown shader type %u", shader);
    }
 
+   if (index &&
+      index >=
+         pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_CONST_BUFFERS)) {
+      glhd_error("Access to constant buffer %u requested, "
+         "but only %d are supported",
+         index,
+         pipe->screen->get_param(pipe->screen, PIPE_CAP_MAX_CONST_BUFFERS));
+   }
+
    /* XXX hmm? unwrap the input state */
    if (_resource) {
       unwrapped_resource = galahad_resource_unwrap(_resource);
diff --git a/src/gallium/drivers/i915/i915_state.c b/src/gallium/drivers/i915/i915_state.c
index cbddb214fb..8c53b06931 100644
--- a/src/gallium/drivers/i915/i915_state.c
+++ b/src/gallium/drivers/i915/i915_state.c
@@ -527,8 +527,6 @@ static void i915_set_constant_buffer(struct pipe_context *pipe,
    struct i915_context *i915 = i915_context(pipe);
    draw_flush(i915->draw);
 
-   assert(index == 0);
-
    /* Make a copy of shader constants.
     * During fragment program translation we may add additional
     * constants to the array.
-- 
cgit v1.2.3


From ae0ef6f69f351cacdc7eaa9b21097a7c1b414e44 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Wed, 18 Aug 2010 17:28:08 +0200
Subject: gallium: make all checks for PIPE_TEXTURE_2D check for
 PIPE_TEXTURE_RECT too

Searched for them with:
git grep -E '[!=]=.*PIPE_TEXTURE_2D|PIPE_TEXTURE_2D.*[!=]=|case.*PIPE_TEXTURE_2D'

Behavior hasn't been changed.
---
 src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 7 +++++--
 src/gallium/auxiliary/util/u_blit.c               | 3 ++-
 src/gallium/auxiliary/util/u_blitter.c            | 3 +++
 src/gallium/auxiliary/util/u_gen_mipmap.c         | 1 +
 src/gallium/auxiliary/util/u_surfaces.h           | 4 ++--
 src/gallium/drivers/i915/i915_resource_texture.c  | 5 ++++-
 src/gallium/drivers/i965/brw_resource_texture.c   | 4 +++-
 src/gallium/drivers/llvmpipe/lp_screen.c          | 1 +
 src/gallium/drivers/llvmpipe/lp_texture.c         | 1 +
 src/gallium/drivers/nv50/nv50_miptree.c           | 3 ++-
 src/gallium/drivers/nv50/nv50_tex.c               | 1 +
 src/gallium/drivers/nvfx/nv30_fragtex.c           | 1 +
 src/gallium/drivers/nvfx/nv40_fragtex.c           | 1 +
 src/gallium/drivers/nvfx/nvfx_miptree.c           | 3 ++-
 src/gallium/drivers/r300/r300_hyperz.c            | 3 ++-
 src/gallium/drivers/r300/r300_texture.c           | 6 ++++--
 src/gallium/drivers/r300/r300_texture_desc.c      | 6 ++++--
 src/gallium/drivers/r600/r600_state.c             | 1 +
 src/gallium/drivers/r600/r600_texture.c           | 3 ++-
 src/gallium/drivers/softpipe/sp_screen.c          | 1 +
 src/gallium/drivers/softpipe/sp_tex_sample.c      | 2 ++
 src/gallium/drivers/svga/svga_resource_texture.c  | 3 ++-
 src/gallium/drivers/svga/svga_tgsi_emit.h         | 1 +
 src/gallium/tests/python/tests/texture_blit.py    | 2 +-
 src/mesa/state_tracker/st_cb_bitmap.c             | 2 +-
 25 files changed, 50 insertions(+), 18 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 806c7d56a8..f6b6162f63 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -176,6 +176,7 @@ texture_dims(enum pipe_texture_target tex)
    case PIPE_TEXTURE_1D:
       return 1;
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
    case PIPE_TEXTURE_CUBE:
       return 2;
    case PIPE_TEXTURE_3D:
@@ -1749,7 +1750,8 @@ lp_build_sample_2d_linear_aos(struct lp_build_sample_context *bld,
    LLVMValueRef unswizzled[4];
    LLVMValueRef stride;
 
-   assert(bld->static_state->target == PIPE_TEXTURE_2D);
+   assert(bld->static_state->target == PIPE_TEXTURE_2D
+         || bld->static_state->target == PIPE_TEXTURE_RECT);
    assert(bld->static_state->min_img_filter == PIPE_TEX_FILTER_LINEAR);
    assert(bld->static_state->mag_img_filter == PIPE_TEX_FILTER_LINEAR);
    assert(bld->static_state->min_mip_filter == PIPE_TEX_MIPFILTER_NONE);
@@ -2077,7 +2079,8 @@ lp_build_sample_soa(LLVMBuilderRef builder,
    }
    else if (util_format_fits_8unorm(bld.format_desc) &&
             bld.format_desc->nr_channels > 1 &&
-            static_state->target == PIPE_TEXTURE_2D &&
+            (static_state->target == PIPE_TEXTURE_2D ||
+                  static_state->target == PIPE_TEXTURE_RECT) &&
             static_state->min_img_filter == PIPE_TEX_FILTER_LINEAR &&
             static_state->mag_img_filter == PIPE_TEX_FILTER_LINEAR &&
             static_state->min_mip_filter == PIPE_TEX_MIPFILTER_NONE &&
diff --git a/src/gallium/auxiliary/util/u_blit.c b/src/gallium/auxiliary/util/u_blit.c
index 97fa99ec65..30c7a96462 100644
--- a/src/gallium/auxiliary/util/u_blit.c
+++ b/src/gallium/auxiliary/util/u_blit.c
@@ -347,7 +347,8 @@ util_blit_pixels_writemask(struct blit_state *ctx,
        dst->face == srcsub.face &&
        dst->level == srcsub.level &&
        dst->zslice == srcZ0) ||
-       src_tex->target != PIPE_TEXTURE_2D)
+       (src_tex->target != PIPE_TEXTURE_2D &&
+       src_tex->target != PIPE_TEXTURE_RECT))
    {
       struct pipe_resource texTemp;
       struct pipe_resource *tex;
diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util/u_blitter.c
index 49ee7bb31d..4b69a7fb6a 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -569,6 +569,8 @@ pipe_tex_to_tgsi_tex(enum pipe_texture_target pipe_tex_target)
       return TGSI_TEXTURE_1D;
    case PIPE_TEXTURE_2D:
       return TGSI_TEXTURE_2D;
+   case PIPE_TEXTURE_RECT:
+      return TGSI_TEXTURE_2D;
    case PIPE_TEXTURE_3D:
       return TGSI_TEXTURE_3D;
    case PIPE_TEXTURE_CUBE:
@@ -807,6 +809,7 @@ void util_blitter_copy_region(struct blitter_context *blitter,
       /* Draw the quad with the draw_rectangle callback. */
       case PIPE_TEXTURE_1D:
       case PIPE_TEXTURE_2D:
+      case PIPE_TEXTURE_RECT:
          {
             /* Set texture coordinates. */
             float coord[4];
diff --git a/src/gallium/auxiliary/util/u_gen_mipmap.c b/src/gallium/auxiliary/util/u_gen_mipmap.c
index b7fe2d3003..6a931a9581 100644
--- a/src/gallium/auxiliary/util/u_gen_mipmap.c
+++ b/src/gallium/auxiliary/util/u_gen_mipmap.c
@@ -1255,6 +1255,7 @@ fallback_gen_mipmap(struct gen_mipmap_state *ctx,
       make_1d_mipmap(ctx, pt, face, baseLevel, lastLevel);
       break;
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
    case PIPE_TEXTURE_CUBE:
       make_2d_mipmap(ctx, pt, face, baseLevel, lastLevel);
       break;
diff --git a/src/gallium/auxiliary/util/u_surfaces.h b/src/gallium/auxiliary/util/u_surfaces.h
index af978c7057..46f3ec5d7d 100644
--- a/src/gallium/auxiliary/util/u_surfaces.h
+++ b/src/gallium/auxiliary/util/u_surfaces.h
@@ -22,7 +22,7 @@ struct pipe_surface *util_surfaces_do_get(struct util_surfaces *us, unsigned sur
 static INLINE struct pipe_surface *
 util_surfaces_get(struct util_surfaces *us, unsigned surface_struct_size, struct pipe_screen *pscreen, struct pipe_resource *pt, unsigned face, unsigned level, unsigned zslice, unsigned flags)
 {
-   if(likely(pt->target == PIPE_TEXTURE_2D && us->u.array))
+   if(likely((pt->target == PIPE_TEXTURE_2D || pt->target == PIPE_TEXTURE_RECT) && us->u.array))
    {
       struct pipe_surface *ps = us->u.array[level];
       if(ps)
@@ -52,7 +52,7 @@ void util_surfaces_do_detach(struct util_surfaces *us, struct pipe_surface *ps);
 static INLINE void
 util_surfaces_detach(struct util_surfaces *us, struct pipe_surface *ps)
 {
-   if(likely(ps->texture->target == PIPE_TEXTURE_2D))
+   if(likely(ps->texture->target == PIPE_TEXTURE_2D || ps->texture->target == PIPE_TEXTURE_RECT))
    {
       us->u.array[ps->level] = 0;
       return;
diff --git a/src/gallium/drivers/i915/i915_resource_texture.c b/src/gallium/drivers/i915/i915_resource_texture.c
index 752ddaae7b..c5c6179b16 100644
--- a/src/gallium/drivers/i915/i915_resource_texture.c
+++ b/src/gallium/drivers/i915/i915_resource_texture.c
@@ -360,6 +360,7 @@ i915_texture_layout(struct i915_texture * tex)
    switch (pt->target) {
    case PIPE_TEXTURE_1D:
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
       if (!i9x5_special_layout(tex))
          i915_texture_layout_2d(tex);
       break;
@@ -605,6 +606,7 @@ i945_texture_layout(struct i915_texture * tex)
    switch (pt->target) {
    case PIPE_TEXTURE_1D:
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
       if (!i9x5_special_layout(tex))
          i945_texture_layout_2d(tex);
       break;
@@ -829,7 +831,8 @@ i915_texture_from_handle(struct pipe_screen * screen,
    buffer = iws->buffer_from_handle(iws, whandle, &stride);
 
    /* Only supports one type */
-   if (template->target != PIPE_TEXTURE_2D ||
+   if ((template->target != PIPE_TEXTURE_2D &&
+       template->target != PIPE_TEXTURE_RECT) ||
        template->last_level != 0 ||
        template->depth0 != 1) {
       return NULL;
diff --git a/src/gallium/drivers/i965/brw_resource_texture.c b/src/gallium/drivers/i965/brw_resource_texture.c
index ffd0f38672..3860d18a7a 100644
--- a/src/gallium/drivers/i965/brw_resource_texture.c
+++ b/src/gallium/drivers/i965/brw_resource_texture.c
@@ -66,6 +66,7 @@ static GLuint translate_tex_target( unsigned target )
       return BRW_SURFACE_1D;
 
    case PIPE_TEXTURE_2D: 
+   case PIPE_TEXTURE_RECT:
       return BRW_SURFACE_2D;
 
    case PIPE_TEXTURE_3D: 
@@ -498,7 +499,8 @@ brw_texture_from_handle(struct pipe_screen *screen,
    unsigned pitch;
    GLuint format;
 
-   if (template->target != PIPE_TEXTURE_2D ||
+   if ((template->target != PIPE_TEXTURE_2D
+         && template->target != PIPE_TEXTURE_RECT)  ||
        template->last_level != 0 ||
        template->depth0 != 1)
       return NULL;
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 167cb2ee2e..6968cda629 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -230,6 +230,7 @@ llvmpipe_is_format_supported( struct pipe_screen *_screen,
    assert(target == PIPE_BUFFER ||
           target == PIPE_TEXTURE_1D ||
           target == PIPE_TEXTURE_2D ||
+          target == PIPE_TEXTURE_RECT ||
           target == PIPE_TEXTURE_3D ||
           target == PIPE_TEXTURE_CUBE);
 
diff --git a/src/gallium/drivers/llvmpipe/lp_texture.c b/src/gallium/drivers/llvmpipe/lp_texture.c
index 25112c10a6..ff4773fd7c 100644
--- a/src/gallium/drivers/llvmpipe/lp_texture.c
+++ b/src/gallium/drivers/llvmpipe/lp_texture.c
@@ -67,6 +67,7 @@ resource_is_texture(const struct pipe_resource *resource)
       return FALSE;
    case PIPE_TEXTURE_1D:
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
    case PIPE_TEXTURE_3D:
    case PIPE_TEXTURE_CUBE:
       return TRUE;
diff --git a/src/gallium/drivers/nv50/nv50_miptree.c b/src/gallium/drivers/nv50/nv50_miptree.c
index b7cd92158f..c0f5cc10dd 100644
--- a/src/gallium/drivers/nv50/nv50_miptree.c
+++ b/src/gallium/drivers/nv50/nv50_miptree.c
@@ -235,7 +235,8 @@ nv50_miptree_from_handle(struct pipe_screen *pscreen,
 	unsigned stride;
 
 	/* Only supports 2D, non-mipmapped textures for the moment */
-	if (template->target != PIPE_TEXTURE_2D ||
+	if ((template->target != PIPE_TEXTURE_2D &&
+	      template->target != PIPE_TEXTURE_RECT) ||
 	    template->last_level != 0 ||
 	    template->depth0 != 1)
 		return NULL;
diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c
index 5ea0c1d726..4db53f7ec2 100644
--- a/src/gallium/drivers/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nv50/nv50_tex.c
@@ -131,6 +131,7 @@ nv50_tex_construct(struct nv50_sampler_view *view)
 		tic[2] |= NV50TIC_0_2_TARGET_1D;
 		break;
 	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
 		tic[2] |= NV50TIC_0_2_TARGET_2D;
 		break;
 	case PIPE_TEXTURE_3D:
diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
index dec073ac90..0cd70ca104 100644
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv30_fragtex.c
@@ -116,6 +116,7 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 		txf |= NV34TCL_TX_FORMAT_CUBIC;
 		/* fall-through */
 	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
 		txf |= NV34TCL_TX_FORMAT_DIMS_2D;
 		break;
 	case PIPE_TEXTURE_3D:
diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c
index 0068b1ba54..0d3e90dcb0 100644
--- a/src/gallium/drivers/nvfx/nv40_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv40_fragtex.c
@@ -135,6 +135,7 @@ nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
 		txf |= NV34TCL_TX_FORMAT_CUBIC;
 		/* fall-through */
 	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
 		txf |= NV34TCL_TX_FORMAT_DIMS_2D;
 		break;
 	case PIPE_TEXTURE_3D:
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index b5639bb464..1fec1ffa42 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -205,7 +205,8 @@ nvfx_miptree_from_handle(struct pipe_screen *pscreen,
 	unsigned stride;
 
 	/* Only supports 2D, non-mipmapped textures for the moment */
-	if (template->target != PIPE_TEXTURE_2D ||
+	if ((template->target != PIPE_TEXTURE_2D &&
+	      template->target != PIPE_TEXTURE_RECT) ||
 	    template->last_level != 0 ||
 	    template->depth0 != 1)
 		return NULL;
diff --git a/src/gallium/drivers/r300/r300_hyperz.c b/src/gallium/drivers/r300/r300_hyperz.c
index b2526d6e41..eb5b0c36f8 100644
--- a/src/gallium/drivers/r300/r300_hyperz.c
+++ b/src/gallium/drivers/r300/r300_hyperz.c
@@ -354,7 +354,8 @@ void r300_zmask_alloc_block(struct r300_context *r300, struct r300_surface *surf
     /* We currently don't handle decompression for 3D textures and cubemaps
      * correctly. */
     if (tex->desc.b.b.target != PIPE_TEXTURE_1D &&
-        tex->desc.b.b.target != PIPE_TEXTURE_2D)
+        tex->desc.b.b.target != PIPE_TEXTURE_2D &&
+        tex->desc.b.b.target != PIPE_TEXTURE_RECT)
         return;
 
     /* Cannot flush zmask of 16-bit zbuffers. */
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index da8eadd3b5..852acdd462 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -754,7 +754,8 @@ struct pipe_resource *r300_texture_create(struct pipe_screen *screen,
     /* Refuse to create a texture with size 0. */
     if (!base->width0 ||
         (!base->height0 && (base->target == PIPE_TEXTURE_2D ||
-                            base->target == PIPE_TEXTURE_CUBE)) ||
+                            base->target == PIPE_TEXTURE_CUBE ||
+                            base->target == PIPE_TEXTURE_RECT)) ||
         (!base->depth0 && base->target == PIPE_TEXTURE_3D)) {
         fprintf(stderr, "r300: texture_create: "
                 "Got invalid texture dimensions: %ix%ix%i\n",
@@ -787,7 +788,8 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen,
     unsigned stride, size;
 
     /* Support only 2D textures without mipmaps */
-    if (base->target != PIPE_TEXTURE_2D ||
+    if ((base->target != PIPE_TEXTURE_2D &&
+          base->target != PIPE_TEXTURE_RECT) ||
         base->depth0 != 1 ||
         base->last_level != 0) {
         return NULL;
diff --git a/src/gallium/drivers/r300/r300_texture_desc.c b/src/gallium/drivers/r300/r300_texture_desc.c
index 5d690e8c33..2fe5d72188 100644
--- a/src/gallium/drivers/r300/r300_texture_desc.c
+++ b/src/gallium/drivers/r300/r300_texture_desc.c
@@ -184,7 +184,8 @@ static unsigned r300_texture_get_nblocksy(struct r300_texture_desc *desc,
 
         /* This is needed for the kernel checker, unfortunately. */
         if ((desc->b.b.target != PIPE_TEXTURE_1D &&
-             desc->b.b.target != PIPE_TEXTURE_2D) ||
+             desc->b.b.target != PIPE_TEXTURE_2D &&
+             desc->b.b.target != PIPE_TEXTURE_RECT) ||
             desc->b.b.last_level != 0) {
             height = util_next_power_of_two(height);
         }
@@ -202,7 +203,8 @@ static unsigned r300_texture_get_nblocksy(struct r300_texture_desc *desc,
                  * Do so for 3 or more macrotiles in the Y direction. */
                 if (level == 0 && desc->b.b.last_level == 0 &&
                     (desc->b.b.target == PIPE_TEXTURE_1D ||
-                     desc->b.b.target == PIPE_TEXTURE_2D) &&
+                     desc->b.b.target == PIPE_TEXTURE_2D ||
+                     desc->b.b.target == PIPE_TEXTURE_RECT) &&
                     height >= tile_height * 3) {
                     height = align(height, tile_height * 2);
                 }
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index f78d1671ba..7d2b61f9b0 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1199,6 +1199,7 @@ static inline unsigned r600_tex_dim(unsigned dim)
 	case PIPE_TEXTURE_1D:
 		return V_038000_SQ_TEX_DIM_1D;
 	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
 		return V_038000_SQ_TEX_DIM_2D;
 	case PIPE_TEXTURE_3D:
 		return V_038000_SQ_TEX_DIM_3D;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index eabd7f7705..8a6b5f8764 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -170,7 +170,8 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	}
 
 	/* Support only 2D textures without mipmaps */
-	if (templ->target != PIPE_TEXTURE_2D || templ->depth0 != 1 || templ->last_level != 0)
+	if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
+	      templ->depth0 != 1 || templ->last_level != 0)
 		return NULL;
 
 	rtex = CALLOC_STRUCT(r600_resource_texture);
diff --git a/src/gallium/drivers/softpipe/sp_screen.c b/src/gallium/drivers/softpipe/sp_screen.c
index 93af6ee5b0..73ae2dea56 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -199,6 +199,7 @@ softpipe_is_format_supported( struct pipe_screen *screen,
    assert(target == PIPE_BUFFER ||
           target == PIPE_TEXTURE_1D ||
           target == PIPE_TEXTURE_2D ||
+          target == PIPE_TEXTURE_RECT ||
           target == PIPE_TEXTURE_3D ||
           target == PIPE_TEXTURE_CUBE);
 
diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c b/src/gallium/drivers/softpipe/sp_tex_sample.c
index cf7ab81405..e654bb77c2 100644
--- a/src/gallium/drivers/softpipe/sp_tex_sample.c
+++ b/src/gallium/drivers/softpipe/sp_tex_sample.c
@@ -1785,6 +1785,7 @@ get_lambda_func(const union sp_sampler_key key)
    case PIPE_TEXTURE_1D:
       return compute_lambda_1d;
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
    case PIPE_TEXTURE_CUBE:
       return compute_lambda_2d;
    case PIPE_TEXTURE_3D:
@@ -1809,6 +1810,7 @@ get_img_filter(const union sp_sampler_key key,
          return img_filter_1d_linear;
       break;
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
       /* Try for fast path:
        */
       if (key.bits.is_pot &&
diff --git a/src/gallium/drivers/svga/svga_resource_texture.c b/src/gallium/drivers/svga/svga_resource_texture.c
index ff83c750aa..26eb03a895 100644
--- a/src/gallium/drivers/svga/svga_resource_texture.c
+++ b/src/gallium/drivers/svga/svga_resource_texture.c
@@ -583,7 +583,8 @@ svga_texture_from_handle(struct pipe_screen *screen,
    assert(screen);
 
    /* Only supports one type */
-   if (template->target != PIPE_TEXTURE_2D ||
+   if ((template->target != PIPE_TEXTURE_2D &&
+       template->target != PIPE_TEXTURE_RECT) ||
        template->last_level != 0 ||
        template->depth0 != 1) {
       return NULL;
diff --git a/src/gallium/drivers/svga/svga_tgsi_emit.h b/src/gallium/drivers/svga/svga_tgsi_emit.h
index 48eced2ece..b4e90a957d 100644
--- a/src/gallium/drivers/svga/svga_tgsi_emit.h
+++ b/src/gallium/drivers/svga/svga_tgsi_emit.h
@@ -353,6 +353,7 @@ static INLINE ubyte svga_tgsi_sampler_type( struct svga_shader_emitter *emit,
    case PIPE_TEXTURE_1D:
       return SVGA3DSAMP_2D;
    case PIPE_TEXTURE_2D:
+   case PIPE_TEXTURE_RECT:
       return SVGA3DSAMP_2D;
    case PIPE_TEXTURE_3D:
       return SVGA3DSAMP_VOLUME;
diff --git a/src/gallium/tests/python/tests/texture_blit.py b/src/gallium/tests/python/tests/texture_blit.py
index 58706dab93..089d05c623 100755
--- a/src/gallium/tests/python/tests/texture_blit.py
+++ b/src/gallium/tests/python/tests/texture_blit.py
@@ -55,7 +55,7 @@ def tex_coords(texture, face, level, zslice):
         [0.0, 1.0],
     ] 
     
-    if texture.target == PIPE_TEXTURE_2D:
+    if texture.target == PIPE_TEXTURE_2D or texture.target == PIPE_TEXTURE_RECT:
         return [[s, t, 0.0] for s, t in st]
     elif texture.target == PIPE_TEXTURE_3D:
         depth = texture.get_depth(level)
diff --git a/src/mesa/state_tracker/st_cb_bitmap.c b/src/mesa/state_tracker/st_cb_bitmap.c
index 0b8ecd27cb..91037ab223 100644
--- a/src/mesa/state_tracker/st_cb_bitmap.c
+++ b/src/mesa/state_tracker/st_cb_bitmap.c
@@ -761,7 +761,7 @@ st_Bitmap(GLcontext *ctx, GLint x, GLint y, GLsizei width, GLsizei height,
    if (pt) {
       struct pipe_sampler_view *sv = st_create_texture_sampler_view(st->pipe, pt);
 
-      assert(pt->target == PIPE_TEXTURE_2D);
+      assert(pt->target == PIPE_TEXTURE_2D || pt->target == PIPE_TEXTURE_RECT);
 
       if (sv) {
          draw_bitmap_quad(ctx, x, y, ctx->Current.RasterPos[2],
-- 
cgit v1.2.3


From ccd08643577988d416b339b84fe7bfda6fb77ef6 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Thu, 19 Aug 2010 01:38:33 +0200
Subject: galahad: check resource_create template

---
 src/gallium/drivers/galahad/glhd_screen.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/galahad/glhd_screen.c b/src/gallium/drivers/galahad/glhd_screen.c
index e1a1b59f20..2d7383acba 100644
--- a/src/gallium/drivers/galahad/glhd_screen.c
+++ b/src/gallium/drivers/galahad/glhd_screen.c
@@ -30,6 +30,7 @@
 #include "pipe/p_screen.h"
 #include "pipe/p_state.h"
 #include "util/u_memory.h"
+#include "util/u_math.h"
 
 #include "glhd_public.h"
 #include "glhd_screen.h"
@@ -134,6 +135,34 @@ galahad_screen_resource_create(struct pipe_screen *_screen,
    struct pipe_screen *screen = glhd_screen->screen;
    struct pipe_resource *result;
 
+   if (templat->target >= PIPE_MAX_TEXTURE_TYPES)
+      glhd_warn("Received bogus resource target %d", templat->target);
+
+   if(templat->target != PIPE_TEXTURE_RECT && templat->target != PIPE_BUFFER && !screen->get_param(screen, PIPE_CAP_NPOT_TEXTURES))
+   {
+      if(!util_is_pot(templat->width0) || !util_is_pot(templat->height0))
+         glhd_warn("Requested NPOT (%ux%u) non-rectangle texture without NPOT support", templat->width0, templat->height0);
+   }
+
+   /* TODO: allow this for OpenCL flexible sampling */
+   if(templat->target == PIPE_TEXTURE_RECT && templat->last_level)
+      glhd_warn("Rectangle textures cannot have mipmaps, but last_level = %u", templat->last_level);
+
+   if(templat->target == PIPE_BUFFER && templat->last_level)
+      glhd_warn("Buffers cannot have mipmaps, but last_level = %u", templat->last_level);
+
+   if(templat->target != PIPE_TEXTURE_3D && templat->depth0 != 1)
+      glhd_warn("Only 3D textures can have depth != 1, but received target %u and depth %u", templat->target, templat->depth0);
+
+   if(templat->target == PIPE_TEXTURE_1D && templat->height0 != 1)
+     glhd_warn("1D textures must have height 1 but got asked for height %u", templat->height0);
+
+   if(templat->target == PIPE_BUFFER && templat->height0 != 1)
+     glhd_warn("Buffers must have height 1 but got asked for height %u", templat->height0);
+
+   if(templat->target == PIPE_TEXTURE_CUBE && templat->width0 != templat->height0)
+      glhd_warn("Cube maps must be square, but got asked for %ux%u", templat->width0, templat->height0);
+
    result = screen->resource_create(screen,
                                     templat);
 
-- 
cgit v1.2.3


From 09bf09cf92c3958c3b8268f38387804084ca30e2 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Wed, 18 Aug 2010 17:29:59 +0200
Subject: nv50: use NV50TIC_0_2_TARGET_RECT

---
 src/gallium/drivers/nv50/nv50_tex.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nv50/nv50_tex.c b/src/gallium/drivers/nv50/nv50_tex.c
index 4db53f7ec2..d41d9c5102 100644
--- a/src/gallium/drivers/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nv50/nv50_tex.c
@@ -131,9 +131,11 @@ nv50_tex_construct(struct nv50_sampler_view *view)
 		tic[2] |= NV50TIC_0_2_TARGET_1D;
 		break;
 	case PIPE_TEXTURE_2D:
-	case PIPE_TEXTURE_RECT:
 		tic[2] |= NV50TIC_0_2_TARGET_2D;
 		break;
+	case PIPE_TEXTURE_RECT:
+		tic[2] |= NV50TIC_0_2_TARGET_RECT;
+		break;
 	case PIPE_TEXTURE_3D:
 		tic[2] |= NV50TIC_0_2_TARGET_3D;
 		break;
-- 
cgit v1.2.3


From 7344e6d9b50e39960713503681d6b37299ce2ccf Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Fri, 20 Aug 2010 12:06:44 +0200
Subject: galahad: remove incorrect comment just added

---
 src/gallium/drivers/galahad/glhd_screen.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/galahad/glhd_screen.c b/src/gallium/drivers/galahad/glhd_screen.c
index 2d7383acba..a4eac11ae3 100644
--- a/src/gallium/drivers/galahad/glhd_screen.c
+++ b/src/gallium/drivers/galahad/glhd_screen.c
@@ -144,7 +144,6 @@ galahad_screen_resource_create(struct pipe_screen *_screen,
          glhd_warn("Requested NPOT (%ux%u) non-rectangle texture without NPOT support", templat->width0, templat->height0);
    }
 
-   /* TODO: allow this for OpenCL flexible sampling */
    if(templat->target == PIPE_TEXTURE_RECT && templat->last_level)
       glhd_warn("Rectangle textures cannot have mipmaps, but last_level = %u", templat->last_level);
 
-- 
cgit v1.2.3


From 63d010115c7972d854e0583f8f74e8d0c3407fcd Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 17 Aug 2010 16:07:23 +1000
Subject: r600g: add occlusion query support

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c      |  34 +++--
 src/gallium/drivers/r600/r600_context.c   |  13 +-
 src/gallium/drivers/r600/r600_context.h   |  37 +++++-
 src/gallium/drivers/r600/r600_query.c     | 208 +++++++++++++++++++++++++++++-
 src/gallium/drivers/r600/r600_state.c     |   1 -
 src/gallium/drivers/r600/radeon.h         |  30 +++--
 src/gallium/winsys/r600/drm/r600_state.c  |  36 ++++++
 src/gallium/winsys/r600/drm/r600_states.h |  25 ++--
 src/gallium/winsys/r600/drm/r600d.h       |   1 +
 src/gallium/winsys/r600/drm/radeon_ctx.c  |  36 +++++-
 10 files changed, 379 insertions(+), 42 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index db7aef7ebd..aef4fbd9af 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -32,8 +32,10 @@
 #include "r600_screen.h"
 #include "r600_context.h"
 
-static void r600_blitter_save_states(struct r600_context *rctx)
+static void r600_blitter_save_states(struct pipe_context *ctx)
 {
+	struct r600_context *rctx = r600_context(ctx);
+
 	util_blitter_save_blend(rctx->blitter, rctx->blend);
 	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
 	if (rctx->stencil_ref) {
@@ -47,8 +49,9 @@ static void r600_blitter_save_states(struct r600_context *rctx)
 	if (rctx->viewport) {
 		util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
 	}
-	if (rctx->clip)
- 	    util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
+	if (rctx->clip) {
+		util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
+	}
 	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
 					rctx->vertex_buffer);
 
@@ -60,37 +63,44 @@ static void r600_blitter_save_states(struct r600_context *rctx)
 	rctx->rasterizer = NULL;
 	rctx->dsa = NULL;
 	rctx->vertex_elements = NULL;
+
+	/* suspend queries */
+	r600_queries_suspend(ctx);
 }
 
 static void r600_clear(struct pipe_context *ctx, unsigned buffers,
-		       const float *rgba, double depth, unsigned stencil)
+			const float *rgba, double depth, unsigned stencil)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
-	r600_blitter_save_states(rctx);
+	r600_blitter_save_states(ctx);
 	util_blitter_clear(rctx->blitter, fb->width, fb->height,
 				fb->nr_cbufs, buffers, rgba, depth,
 				stencil);
+	/* resume queries */
+	r600_queries_resume(ctx);
 }
 
-static void r600_clear_render_target(struct pipe_context *pipe,
+static void r600_clear_render_target(struct pipe_context *ctx,
 				     struct pipe_surface *dst,
 				     const float *rgba,
 				     unsigned dstx, unsigned dsty,
 				     unsigned width, unsigned height)
 {
-	struct r600_context *rctx = r600_context(pipe);
+	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
-	r600_blitter_save_states(rctx);
+	r600_blitter_save_states(ctx);
 	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
 					 dstx, dsty, width, height);
+	/* resume queries */
+	r600_queries_resume(ctx);
 }
 
-static void r600_clear_depth_stencil(struct pipe_context *pipe,
+static void r600_clear_depth_stencil(struct pipe_context *ctx,
 				     struct pipe_surface *dst,
 				     unsigned clear_flags,
 				     double depth,
@@ -98,14 +108,16 @@ static void r600_clear_depth_stencil(struct pipe_context *pipe,
 				     unsigned dstx, unsigned dsty,
 				     unsigned width, unsigned height)
 {
-	struct r600_context *rctx = r600_context(pipe);
+	struct r600_context *rctx = r600_context(ctx);
 	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 
-	r600_blitter_save_states(rctx);
+	r600_blitter_save_states(ctx);
 	util_blitter_save_framebuffer(rctx->blitter, fb);
 
 	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
 					 dstx, dsty, width, height);
+	/* resume queries */
+	r600_queries_resume(ctx);
 }
 
 static void r600_resource_copy_region(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index edde80c660..2f59a550f5 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -34,6 +34,7 @@
 #include "r600_resource.h"
 #include "r600d.h"
 
+
 static void r600_destroy_context(struct pipe_context *context)
 {
 	struct r600_context *rctx = r600_context(context);
@@ -46,26 +47,34 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 {
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_screen *rscreen = rctx->screen;
+	struct r600_query *rquery;
 	static int dc = 0;
 	char dname[256];
 
+	/* suspend queries */
+	r600_queries_suspend(rctx);
 	if (radeon_ctx_pm4(rctx->ctx))
-		return;
+		goto out;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
 	if (!rctx->ctx->cpm4)
 		goto out;
 	sprintf(dname, "gallium-%08d.bof", dc);
-	if (dc < 1)
+	if (dc < 10)
 		radeon_ctx_dump_bof(rctx->ctx, dname);
 #if 1
 	radeon_ctx_submit(rctx->ctx);
 #endif
+	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+		rquery->flushed = true;
+	}
 	dc++;
 out:
 	rctx->ctx = radeon_ctx_decref(rctx->ctx);
 	rctx->ctx = radeon_ctx(rscreen->rw);
+	/* resume queries */
+	r600_queries_resume(rctx);
 }
 
 static void r600_init_config(struct r600_context *rctx)
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 2ce29720d9..900aa9fd0c 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -30,9 +30,32 @@
 #include <tgsi/tgsi_parse.h>
 #include <tgsi/tgsi_util.h>
 #include <util/u_blitter.h>
+#include <util/u_double_list.h>
 #include "radeon.h"
 #include "r600_shader.h"
 
+#define R600_QUERY_STATE_STARTED	(1 << 0)
+#define R600_QUERY_STATE_ENDED		(1 << 1)
+#define R600_QUERY_STATE_SUSPENDED	(1 << 2)
+
+struct r600_query {
+	u64					result;
+	/* The kind of query. Currently only OQ is supported. */
+	unsigned				type;
+	/* How many results have been written, in dwords. It's incremented
+	 * after end_query and flush. */
+	unsigned				num_results;
+	/* if we've flushed the query */
+	boolean					flushed;
+	unsigned				state;
+	/* The buffer where query results are stored. */
+	struct radeon_bo			*buffer;
+	unsigned				buffer_size;
+	/* linked list of queries */
+	struct list_head			list;
+	struct radeon_state			*rstate;
+};
+
 /* XXX move this to a more appropriate place */
 union pipe_states {
 	struct pipe_rasterizer_state		rasterizer;
@@ -142,7 +165,8 @@ struct r600_context {
 	struct r600_vertex_element	*vertex_elements;
 	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
 	struct pipe_index_buffer	index_buffer;
-	struct pipe_blend_color         blend_color;
+	struct pipe_blend_color		blend_color;
+	struct list_head		query_list;
 };
 
 /* Convenience cast wrapper. */
@@ -151,6 +175,11 @@ static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
     return (struct r600_context*)pipe;
 }
 
+static INLINE struct r600_query* r600_query(struct pipe_query* q)
+{
+    return (struct r600_query*)q;
+}
+
 struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state);
 struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate);
 struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate);
@@ -179,4 +208,10 @@ extern int r600_pipe_shader_update(struct pipe_context *ctx,
 uint32_t r600_translate_texformat(enum pipe_format format,
 				  const unsigned char *swizzle_view, 
 				  uint32_t *word4_p, uint32_t *yuv_format_p);
+
+/* query */
+extern void r600_queries_resume(struct pipe_context *ctx);
+extern void r600_queries_suspend(struct pipe_context *ctx);
+
+
 #endif
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 9b02ae680e..5929606cd2 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -24,39 +24,233 @@
  *      Jerome Glisse
  *      Corbin Simpson
  */
+#include <errno.h>
 #include <util/u_inlines.h>
 #include <util/u_format.h>
 #include <util/u_memory.h>
 #include "r600_screen.h"
 #include "r600_context.h"
 
-static struct pipe_query *r600_create_query(struct pipe_context *pipe, unsigned query_type)
+static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
 {
-	return NULL;
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
+	if (rstate == NULL)
+		return NULL;
+	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
-static void r600_destroy_query(struct pipe_context *pipe, struct pipe_query *query)
+static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
 {
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *q;
+
+	if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
+		return NULL;
+
+	q = CALLOC_STRUCT(r600_query);
+	if (!q)
+		return NULL;
+
+	q->type = query_type;
+	LIST_ADDTAIL(&q->list, &rctx->query_list);
+	q->buffer_size = 4096;
+
+	q->buffer = radeon_bo(rscreen->rw, 0, q->buffer_size, 1, NULL);
+	if (!q->buffer) {
+		FREE(q);
+		return NULL;
+	}
+	return (struct pipe_query *)q;
+}
+
+static void r600_destroy_query(struct pipe_context *ctx,
+			       struct pipe_query *query)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_query *q = r600_query(query);
+
+	radeon_bo_decref(rscreen->rw, q->buffer);
+	LIST_DEL(&q->list);
 	FREE(query);
 }
 
-static void r600_begin_query(struct pipe_context *pipe, struct pipe_query *query)
+static void r600_query_result(struct pipe_context *ctx, struct r600_query *rquery)
 {
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	u64 start, end;
+	u32 *results;
+	int i;
+
+	radeon_bo_wait(rscreen->rw, rquery->buffer);
+	radeon_bo_map(rscreen->rw, rquery->buffer);
+	results = rquery->buffer->data;
+	for (i = 0; i < rquery->num_results; i += 4) {
+		start = (u64)results[i] | (u64)results[i + 1] << 32;
+		end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
+		if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
+			rquery->result += end - start;
+		}
+	}
+	radeon_bo_unmap(rscreen->rw, rquery->buffer);
+	rquery->num_results = 0;
 }
 
-static void r600_end_query(struct pipe_context *pipe, struct pipe_query *query)
+static void r600_query_resume(struct pipe_context *ctx, struct r600_query *rquery)
 {
+	struct r600_context *rctx = r600_context(ctx);
+
+	if (rquery->num_results >= ((rquery->buffer_size >> 2) - 2)) {
+		/* running out of space */
+		if (!rquery->flushed) {
+			ctx->flush(ctx, 0, NULL);
+		}
+		r600_query_result(ctx, rquery);
+	}
+	rquery->rstate = radeon_state_decref(rquery->rstate);
+	rquery->rstate = r600_query_begin(rctx, rquery);
+	rquery->flushed = false;
+}
+
+static void r600_query_suspend(struct pipe_context *ctx, struct r600_query *rquery)
+{
+	struct r600_context *rctx = r600_context(ctx);
+
+	rquery->rstate = radeon_state_decref(rquery->rstate);
+	rquery->rstate = r600_query_end(rctx, rquery);
+	rquery->num_results += 16;
 }
 
-static boolean r600_get_query_result(struct pipe_context *pipe,
+static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery = r600_query(query);
+	int r;
+
+	rquery->state = R600_QUERY_STATE_STARTED;
+	rquery->num_results = 0;
+	rquery->flushed = false;
+	r600_query_resume(ctx, rquery);
+	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	if (r == -EBUSY) {
+		/* this shouldn't happen */
+		R600_ERR("had to flush while emitting end query\n");
+		ctx->flush(ctx, 0, NULL);
+		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	}
+}
+
+static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery = r600_query(query);
+	int r;
+
+	rquery->state &= ~R600_QUERY_STATE_STARTED;
+	rquery->state |= R600_QUERY_STATE_ENDED;
+	r600_query_suspend(ctx, rquery);
+	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	if (r == -EBUSY) {
+		/* this shouldn't happen */
+		R600_ERR("had to flush while emitting end query\n");
+		ctx->flush(ctx, 0, NULL);
+		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	}
+}
+
+void r600_queries_suspend(struct pipe_context *ctx)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery;
+	int r;
+
+	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+		if (rquery->state & R600_QUERY_STATE_STARTED) {
+			r600_query_suspend(ctx, rquery);
+			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			if (r == -EBUSY) {
+				/* this shouldn't happen */
+				R600_ERR("had to flush while emitting end query\n");
+				ctx->flush(ctx, 0, NULL);
+				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			}
+		}
+		rquery->state |= R600_QUERY_STATE_SUSPENDED;
+	}
+}
+
+void r600_queries_resume(struct pipe_context *ctx)
+{
+	struct r600_context *rctx = r600_context(ctx);
+	struct r600_query *rquery;
+	int r;
+
+	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
+		if (rquery->state & R600_QUERY_STATE_STARTED) {
+			r600_query_resume(ctx, rquery);
+			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			if (r == -EBUSY) {
+				/* this shouldn't happen */
+				R600_ERR("had to flush while emitting end query\n");
+				ctx->flush(ctx, 0, NULL);
+				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			}
+		}
+		rquery->state &= ~R600_QUERY_STATE_SUSPENDED;
+	}
+}
+
+static boolean r600_get_query_result(struct pipe_context *ctx,
 					struct pipe_query *query,
-					boolean wait, void *result)
+					boolean wait, void *vresult)
 {
+	struct r600_query *rquery = r600_query(query);
+	uint64_t *result = (uint64_t*)vresult;
+
+	if (!rquery->flushed) {
+		ctx->flush(ctx, 0, NULL);
+		rquery->flushed = true;
+	}
+	r600_query_result(ctx, rquery);
+	*result = rquery->result;
+	rquery->result = 0;
 	return TRUE;
 }
 
 void r600_init_query_functions(struct r600_context* rctx)
 {
+	LIST_INITHEAD(&rctx->query_list);
+
 	rctx->context.create_query = r600_create_query;
 	rctx->context.destroy_query = r600_destroy_query;
 	rctx->context.begin_query = r600_begin_query;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 7d2b61f9b0..3943ebacb3 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -268,7 +268,6 @@ static void r600_set_blend_color(struct pipe_context *ctx,
 static void r600_set_clip_state(struct pipe_context *ctx,
 				const struct pipe_clip_state *state)
 {
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_context_state *rstate;
 
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index d36c89d6a7..b2cc74f696 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -151,6 +151,7 @@ struct radeon_ctx *radeon_ctx(struct radeon *radeon);
 struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
 struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
 int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
 int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
 int radeon_ctx_pm4(struct radeon_ctx *ctx);
 int radeon_ctx_submit(struct radeon_ctx *ctx);
@@ -191,8 +192,8 @@ struct radeon_ctx {
  * R600/R700
  */
 
-#define R600_NSTATE				1286
-#define R600_NTYPE				33
+#define R600_NSTATE				1288
+#define R600_NTYPE				35
 
 #define R600_CONFIG				0
 #define R600_CONFIG_TYPE				0
@@ -252,14 +253,18 @@ struct radeon_ctx {
 #define R600_CB6_TYPE				27
 #define R600_CB7				1276
 #define R600_CB7_TYPE				28
-#define R600_DB				1277
-#define R600_DB_TYPE				29
-#define R600_CLIP				1278
-#define R600_CLIP_TYPE				30
-#define R600_VGT				1284
-#define R600_VGT_TYPE				31
-#define R600_DRAW				1285
-#define R600_DRAW_TYPE				32
+#define R600_QUERY_BEGIN			1277
+#define R600_QUERY_BEGIN_TYPE			29
+#define R600_QUERY_END				1278
+#define R600_QUERY_END_TYPE			30
+#define R600_DB					1279
+#define R600_DB_TYPE				31
+#define R600_CLIP				1280
+#define R600_CLIP_TYPE				32
+#define R600_VGT				1286
+#define R600_VGT_TYPE				33
+#define R600_DRAW				1287
+#define R600_DRAW_TYPE				34
 
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
@@ -653,4 +658,9 @@ struct radeon_ctx {
 #define R600_CLIP__PA_CL_UCP_W_0  3
 #define R600_CLIP_SIZE  4
 #define R600_CLIP_PM4 128
+/* R600 QUERY BEGIN/END */
+#define R600_QUERY__OFFSET			0
+#define R600_QUERY_SIZE				1
+#define R600_QUERY_PM4				128
+
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 2facec75de..9b7c11bdc0 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -38,6 +38,8 @@ static int r600_state_pm4_shader(struct radeon_state *state);
 static int r600_state_pm4_draw(struct radeon_state *state);
 static int r600_state_pm4_config(struct radeon_state *state);
 static int r600_state_pm4_generic(struct radeon_state *state);
+static int r600_state_pm4_query_begin(struct radeon_state *state);
+static int r600_state_pm4_query_end(struct radeon_state *state);
 static int r700_state_pm4_config(struct radeon_state *state);
 static int r700_state_pm4_cb0(struct radeon_state *state);
 static int r700_state_pm4_db(struct radeon_state *state);
@@ -240,6 +242,40 @@ static int r600_state_pm4_config(struct radeon_state *state)
 	return r600_state_pm4_generic(state);
 }
 
+static int r600_state_pm4_query_begin(struct radeon_state *state)
+{
+	int r;
+
+	state->cpm4 = 0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = 0x0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	return 0;
+}
+
+static int r600_state_pm4_query_end(struct radeon_state *state)
+{
+	int r;
+
+	state->cpm4 = 0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = 0x0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	return 0;
+}
+
 static int r700_state_pm4_config(struct radeon_state *state)
 {
 	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 2d7a1d31c8..b5365e4275 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -479,6 +479,10 @@ static const struct radeon_register R600_DRAW_names[] = {
 	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
 };
 
+static const struct radeon_register R600_VGT_EVENT_names[] = {
+	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
+};
+
 static struct radeon_type R600_types[] = {
 	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
 	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
@@ -509,11 +513,12 @@ static struct radeon_type R600_types[] = {
 	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
 	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
 	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
-	{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 static struct radeon_type R700_types[] = {
@@ -546,10 +551,12 @@ static struct radeon_type R700_types[] = {
 	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
 	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
 	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
-	{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
 };
 
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h
index 235b2b3d97..e8c2dc0651 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -82,6 +82,7 @@
 #define PKT3_SET_CTL_CONST                     0x6F
 #define PKT3_SURFACE_BASE_UPDATE               0x73
 
+#define EVENT_TYPE_ZPASS_DONE                  0x15
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT   0x16
 
 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index 45b706bb0f..bd050c4cf9 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -224,6 +224,41 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
 	return 0;
 }
 
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
+{
+	void *tmp;
+	int r = 0;
+
+	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
+	if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
+		return -EINVAL;
+	}
+	r = radeon_state_pm4(state);
+	if (r)
+		return r;
+	if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
+		/* need to flush */
+		return -EBUSY;
+	}
+	if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
+		fprintf(stderr, "%s single state too big %d, max %d\n",
+			__func__, state->cpm4, RADEON_CTX_MAX_PM4);
+		return -EINVAL;
+	}
+	tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
+	if (tmp == NULL)
+		return -ENOMEM;
+	ctx->state = tmp;
+	ctx->state[ctx->nstate++] = radeon_state_incref(state);
+	/* BEGIN/END query are balanced in the same cs so account for END
+	 * END query when scheduling BEGIN query
+	 */
+	if (state->type == R600_QUERY_BEGIN_TYPE) {
+		ctx->draw_cpm4 += state->cpm4 * 2;
+	}
+	return 0;
+}
+
 int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
 {
 	struct radeon_draw *pdraw = NULL;
@@ -366,7 +401,6 @@ printf("%d pm4\n", ctx->cpm4);
 		if (bo == NULL)
 			goto out_err;
 		size = bof_int32(ctx->bo[i]->size);
-printf("[%d] %d bo\n", i, size);
 		if (size == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "size", size))
-- 
cgit v1.2.3


From 921c987c6f43b4d63a98b61013d43bac97baff21 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 20 Aug 2010 17:57:38 +0200
Subject: r600g: cleanup definition, fix segfault when no valid pixel shader

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 30 ++++++++++++-------------
 src/gallium/drivers/r600/r600_sq.h     | 41 +++++++++++++++++-----------------
 src/gallium/drivers/r600/r600_state.c  |  6 ++++-
 3 files changed, 40 insertions(+), 37 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 455730320e..62cd8f567a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -711,9 +711,9 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 	alu.src[0] = r600_src[0];
 	alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
 		
-	alu.src[1].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
 	alu.src[1].chan = 0;
-	alu.src[2].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
 	alu.src[2].chan = 1;
 	alu.last = 1;
 	r = r600_bc_add_alu(ctx->bc, &alu);
@@ -756,9 +756,9 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 	alu.src[0].sel = ctx->temp_reg;
 	alu.src[0].chan = 0;
 		
-	alu.src[1].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[1].sel = V_SQ_ALU_SRC_LITERAL;
 	alu.src[1].chan = 0;
-	alu.src[2].sel = SQ_ALU_SRC_LITERAL;
+	alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
 	alu.src[2].chan = 1;
 	alu.last = 1;
 	r = r600_bc_add_alu(ctx->bc, &alu);
@@ -810,7 +810,7 @@ static int tgsi_kill(struct r600_shader_ctx *ctx)
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = ctx->inst_info->r600_opcode;
 		alu.dst.chan = i;
-		alu.src[0].sel = SQ_ALU_SRC_0;
+		alu.src[0].sel = V_SQ_ALU_SRC_0;
 		r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
 		if (r)
 			return r;
@@ -869,7 +869,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	/* dst.x, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
 	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-	alu.src[0].sel  = SQ_ALU_SRC_1; /*1.0*/
+	alu.src[0].sel  = V_SQ_ALU_SRC_1; /*1.0*/
 	alu.src[0].chan = 0;
 	r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
 	if (r)
@@ -885,7 +885,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
 	if (r)
 		return r;
-	alu.src[1].sel  = SQ_ALU_SRC_0; /*0.0*/
+	alu.src[1].sel  = V_SQ_ALU_SRC_0; /*0.0*/
 	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
 	r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
 	if (r)
@@ -906,7 +906,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	/* dst.w, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
 	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-	alu.src[0].sel  = SQ_ALU_SRC_1;
+	alu.src[0].sel  = V_SQ_ALU_SRC_1;
 	alu.src[0].chan = 0;
 	r = tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
 	if (r)
@@ -1050,7 +1050,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_alu alu;
 	struct r600_bc_alu_src r600_src[3];
-	int i, j, r;
+	int i, r;
 
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
@@ -1067,7 +1067,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 		alu.src[0] = r600_src[0];
 		alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
 
-		alu.src[1].sel = SQ_ALU_SRC_1;
+		alu.src[1].sel = V_SQ_ALU_SRC_1;
 
 		alu.src[2] = r600_src[0];
 		alu.src[2].chan = tgsi_chan(&inst->Src[0], i);
@@ -1090,7 +1090,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 		alu.src[0].sel = ctx->temp_reg;
 		alu.src[0].neg = 1;
 
-		alu.src[1].sel = SQ_ALU_SRC_1;
+		alu.src[1].sel = V_SQ_ALU_SRC_1;
 		alu.src[1].neg = 1;
 
 		alu.src[2].sel = ctx->temp_reg;
@@ -1192,13 +1192,13 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
 		switch (ctx->inst_info->tgsi_opcode) {
 		case TGSI_OPCODE_DP2:
 			if (i > 1) {
-				alu.src[0].sel = alu.src[1].sel = SQ_ALU_SRC_0;
+				alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
 				alu.src[0].chan = alu.src[1].chan = 0;
 			}
 			break;
 		case TGSI_OPCODE_DP3:
 			if (i > 2) {
-				alu.src[0].sel = alu.src[1].sel = SQ_ALU_SRC_0;
+				alu.src[0].sel = alu.src[1].sel = V_SQ_ALU_SRC_0;
 				alu.src[0].chan = alu.src[1].chan = 0;
 			}
 			break;
@@ -1255,7 +1255,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		}
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-		alu.src[0].sel = SQ_ALU_SRC_1;
+		alu.src[0].sel = V_SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = 3;
@@ -1322,7 +1322,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD;
-		alu.src[0].sel = SQ_ALU_SRC_1;
+		alu.src[0].sel = V_SQ_ALU_SRC_1;
 		alu.src[0].chan = 0;
 		alu.src[1] = r600_src[0];
 		alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index 819624e689..ad4de0b072 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -206,6 +206,26 @@
 #define   S_SQ_ALU_WORD0_SRC0_SEL(x)                                 (((x) & 0x1FF) << 0)
 #define   G_SQ_ALU_WORD0_SRC0_SEL(x)                                 (((x) >> 0) & 0x1FF)
 #define   C_SQ_ALU_WORD0_SRC0_SEL                                    0xFFFFFE00
+/*
+ * 244  ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
+ * 245  ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
+ * 246  ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
+ * 247  ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
+ * 248  SQ_ALU_SRC_0: special constant 0.0.
+ * 249  SQ_ALU_SRC_1: special constant 1.0 float.
+ * 250  SQ_ALU_SRC_1_INT: special constant 1 integer.
+ * 251  SQ_ALU_SRC_M_1_INT: special constant -1 integer.
+ * 252  SQ_ALU_SRC_0_5: special constant 0.5 float.
+ * 253  SQ_ALU_SRC_LITERAL: literal constant.
+ * 254  SQ_ALU_SRC_PV: previous vector result.
+ * 255  SQ_ALU_SRC_PS: previous scalar result.
+ */
+#define     V_SQ_ALU_SRC_0                                           0x000000F8
+#define     V_SQ_ALU_SRC_1                                           0x000000F9
+#define     V_SQ_ALU_SRC_1_INT                                       0x000000FA
+#define     V_SQ_ALU_SRC_M_1_INT                                     0x000000FB
+#define     V_SQ_ALU_SRC_0_5                                         0x000000FC
+#define     V_SQ_ALU_SRC_LITERAL                                     0x000000FD
 #define   S_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) & 0x1) << 9)
 #define   G_SQ_ALU_WORD0_SRC0_REL(x)                                 (((x) >> 9) & 0x1)
 #define   C_SQ_ALU_WORD0_SRC0_REL                                    0xFFFFFDFF
@@ -583,25 +603,4 @@
 #define   G_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) >> 29) & 0x7)
 #define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
 
-/*
- * 244  ALU_SRC_1_DBL_L: special constant 1.0 double-float, LSW. (RV670+)
- * 245  ALU_SRC_1_DBL_M: special constant 1.0 double-float, MSW. (RV670+)
- * 246  ALU_SRC_0_5_DBL_L: special constant 0.5 double-float, LSW. (RV670+)
- * 247  ALU_SRC_0_5_DBL_M: special constant 0.5 double-float, MSW. (RV670+)
- * 248	SQ_ALU_SRC_0: special constant 0.0.
- * 249	SQ_ALU_SRC_1: special constant 1.0 float.
- * 250	SQ_ALU_SRC_1_INT: special constant 1 integer.
- * 251	SQ_ALU_SRC_M_1_INT: special constant -1 integer.
- * 252	SQ_ALU_SRC_0_5: special constant 0.5 float.
- * 253	SQ_ALU_SRC_LITERAL: literal constant.
- * 254	SQ_ALU_SRC_PV: previous vector result.
- * 255	SQ_ALU_SRC_PS: previous scalar result.
- */
-#define SQ_ALU_SRC_0 248
-#define SQ_ALU_SRC_1 249
-#define SQ_ALU_SRC_1_INT 250
-#define SQ_ALU_SRC_M_1_INT 251
-#define SQ_ALU_SRC_0_5 252
-#define SQ_ALU_SRC_LITERAL 253
-
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 3943ebacb3..93fc68e42e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -980,15 +980,19 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	struct r600_screen *rscreen = rctx->screen;
 	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 	unsigned stencil_ref_mask, stencil_ref_mask_bf;
-	struct r600_shader *rshader = &rctx->ps_shader->shader;
+	struct r600_shader *rshader;
 	struct radeon_state *rstate;
 	int i;
 
+	if (rctx->ps_shader == NULL) {
+		return NULL;
+	}
 	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 	if (rstate == NULL)
 		return NULL;
 
 	db_shader_control = 0x210;
+	rshader = &rctx->ps_shader->shader;
 	for (i = 0; i < rshader->noutput; i++) {
 		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
 			db_shader_control |= 1;
-- 
cgit v1.2.3


From a4b10a56145ea253def4cf958410d770d0640bc9 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 20 Aug 2010 18:53:29 +0200
Subject: r600g: add POW instruction

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 91 +++++++++++++++++++++++++++-------
 1 file changed, 73 insertions(+), 18 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 62cd8f567a..da1af6702c 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1006,27 +1006,12 @@ static int tgsi_trans(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
-static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
+static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_alu alu;
-	int i, j, r;
+	int i, r;
 
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = ctx->inst_info->r600_opcode;
-	for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
-		r = tgsi_src(ctx, &inst->Src[j], &alu.src[j]);
-		if (r)
-			return r;
-		alu.src[j].chan = tgsi_chan(&inst->Src[j], 0);
-	}
-	alu.dst.sel = ctx->temp_reg;
-	alu.dst.write = 1;
-	alu.last = 1;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
-	/* replicate result */
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.src[0].sel = ctx->temp_reg;
@@ -1045,6 +1030,76 @@ static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int i, r;
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = ctx->inst_info->r600_opcode;
+	for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
+		r = tgsi_src(ctx, &inst->Src[i], &alu.src[i]);
+		if (r)
+			return r;
+		alu.src[i].chan = tgsi_chan(&inst->Src[i], 0);
+	}
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	/* replicate result */
+	return tgsi_helper_tempx_replicate(ctx);
+}
+
+static int tgsi_pow(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int r;
+
+	/* LOG2(a) */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE;
+	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+	if (r)
+		return r;
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	/* b * LOG2(a) */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE;
+	r = tgsi_src(ctx, &inst->Src[1], &alu.src[0]);
+	if (r)
+		return r;
+	alu.src[0].chan = tgsi_chan(&inst->Src[1], 0);
+	alu.src[1].sel = ctx->temp_reg;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	/* POW(a,b) = EXP2(b * LOG2(a))*/
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
+	alu.src[0].sel = ctx->temp_reg;
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	return tgsi_helper_tempx_replicate(ctx);
+}
+
 static int tgsi_ssg(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -1419,7 +1474,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
 	{TGSI_OPCODE_XPD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	/* gap */
 	{32,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-- 
cgit v1.2.3


From 29dde59ea718f70209788bcc3eaf1c3dd7c2ca69 Mon Sep 17 00:00:00 2001
From: Alex Corscadden <alexc@vmware.com>
Date: Tue, 17 Aug 2010 11:35:29 -0700
Subject: trace: Trace the correct version of the resource when setting the
 index buffer.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The trace driver was tracing the unwrapped version of the index buffer
when setting the index buffer.  This caused an assert validating that
a resource belonged to the trace driver to fail.  Instead, we'll log
the unmodified index buffer structure when setting the index buffer.

Signed-off-by: José Fonseca <jfonseca@vmware.com>
---
 src/gallium/drivers/trace/tr_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/trace/tr_context.c b/src/gallium/drivers/trace/tr_context.c
index 84e5a6a824..5d5bb41d94 100644
--- a/src/gallium/drivers/trace/tr_context.c
+++ b/src/gallium/drivers/trace/tr_context.c
@@ -1002,7 +1002,7 @@ trace_context_set_index_buffer(struct pipe_context *_pipe,
    trace_dump_call_begin("pipe_context", "set_index_buffer");
 
    trace_dump_arg(ptr, pipe);
-   trace_dump_arg(index_buffer, ib);
+   trace_dump_arg(index_buffer, _ib);
 
    pipe->set_index_buffer(pipe, ib);
 
-- 
cgit v1.2.3


From ce3a07c392fb0532f18dcb2d582b41a3f6bf198c Mon Sep 17 00:00:00 2001
From: Alex Corscadden <alexc@vmware.com>
Date: Tue, 17 Aug 2010 13:45:31 -0700
Subject: trace: Don't immediately destroy the pipe's sampler view in the trace
 driver.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The trace driver's implementation of sampler_view_destroy was calling
directly into the underlying pipe's sampler_view_destroy implementation.
This causes problems for pipes that keep references to sampler views
even after the state tracker has released them.  Instead, we'll simply
drop the trace driver's reference to the pipe's sampler view.

Signed-off-by: José Fonseca <jfonseca@vmware.com>
---
 src/gallium/drivers/trace/tr_context.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/trace/tr_context.c b/src/gallium/drivers/trace/tr_context.c
index 5d5bb41d94..9e8a23d35c 100644
--- a/src/gallium/drivers/trace/tr_context.c
+++ b/src/gallium/drivers/trace/tr_context.c
@@ -885,7 +885,7 @@ trace_sampler_view_destroy(struct pipe_context *_pipe,
    trace_dump_arg(ptr, pipe);
    trace_dump_arg(ptr, view);
 
-   pipe->sampler_view_destroy(pipe, view);
+   pipe_sampler_view_reference(&tr_view->sampler_view, NULL);
 
    trace_dump_call_end();
 
-- 
cgit v1.2.3


From 95acfd0c8a53738a89fe91cf7643a8563bbe2b4f Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 7 Aug 2010 02:49:48 +0200
Subject: nvfx: fix format support code for compressed texture

A source line was put in the wrong place.
---
 src/gallium/drivers/nvfx/nvfx_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index f2525ccb38..d354bd166a 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -198,7 +198,6 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 			break;
 		}
 	} else {
-		switch (format) {
 		if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
 			switch (format) {
 			case PIPE_FORMAT_DXT1_RGB:
@@ -210,6 +209,7 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 				break;
 			}
 		}
+		switch (format) {
 		case PIPE_FORMAT_B8G8R8A8_UNORM:
 		case PIPE_FORMAT_B8G8R8X8_UNORM:
 		case PIPE_FORMAT_B5G5R5A1_UNORM:
-- 
cgit v1.2.3


From e189823eb4427e091e052d65cc9db3d7353f02bf Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Fri, 6 Aug 2010 09:15:00 +0200
Subject: nvfx: reference count bound objects

---
 src/gallium/drivers/nvfx/nvfx_state.c | 36 ++++++++++++++++++++++++++++-------
 1 file changed, 29 insertions(+), 7 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index cd58e439d7..ab7bed0f93 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -1,6 +1,7 @@
 #include "pipe/p_state.h"
 #include "pipe/p_defines.h"
 #include "util/u_inlines.h"
+#include "util/u_framebuffer.h"
 
 #include "draw/draw_context.h"
 
@@ -507,7 +508,10 @@ nvfx_set_framebuffer_state(struct pipe_context *pipe,
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
 
-	nvfx->framebuffer = *fb;
+	if(fb)
+		util_copy_framebuffer_state(&nvfx->framebuffer, fb);
+	else
+		util_unreference_framebuffer_state(&nvfx->framebuffer);
 	nvfx->dirty |= NVFX_NEW_FB;
 }
 
@@ -548,7 +552,17 @@ nvfx_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
 
-	memcpy(nvfx->vtxbuf, vb, sizeof(*vb) * count);
+	for(unsigned i = 0; i < count; ++i)
+	{
+		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, vb[i].buffer);
+		nvfx->vtxbuf[i].buffer_offset = vb[i].buffer_offset;
+		nvfx->vtxbuf[i].max_index = vb[i].max_index;
+		nvfx->vtxbuf[i].stride = vb[i].stride;
+	}
+
+	for(unsigned i = count; i < nvfx->vtxbuf_nr; ++i)
+		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, 0);
+
 	nvfx->vtxbuf_nr = count;
 
 	nvfx->dirty |= NVFX_NEW_ARRAYS;
@@ -561,12 +575,20 @@ nvfx_set_index_buffer(struct pipe_context *pipe,
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
 
-	if (ib)
-		memcpy(&nvfx->idxbuf, ib, sizeof(nvfx->idxbuf));
-	else
-		memset(&nvfx->idxbuf, 0, sizeof(nvfx->idxbuf));
-
 	/* TODO make this more like a state */
+
+	if(ib)
+	{
+		pipe_resource_reference(&nvfx->idxbuf.buffer, ib->buffer);
+		nvfx->idxbuf.index_size = ib->index_size;
+		nvfx->idxbuf.offset = ib->offset;
+	}
+	else
+	{
+		pipe_resource_reference(&nvfx->idxbuf.buffer, 0);
+		nvfx->idxbuf.index_size = 0;
+		nvfx->idxbuf.offset = 0;
+	}
 }
 
 static void *
-- 
cgit v1.2.3


From 6a73d99a5236eeb822e9bdd26bd669638cf036c6 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 9 Aug 2010 05:05:12 +0200
Subject: nvfx: properly unreference bound objects on context destruction

---
 src/gallium/drivers/nvfx/nvfx_context.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 7218abff22..3d45f5f0ba 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -1,5 +1,6 @@
 #include "draw/draw_context.h"
 #include "pipe/p_defines.h"
+#include "util/u_framebuffer.h"
 
 #include "nvfx_context.h"
 #include "nvfx_screen.h"
@@ -31,6 +32,13 @@ nvfx_destroy(struct pipe_context *pipe)
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
 
+	for(unsigned i = 0; i < nvfx->vtxbuf_nr; ++i)
+		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, 0);
+	pipe_resource_reference(&nvfx->idxbuf.buffer, 0);
+	util_unreference_framebuffer_state(&nvfx->framebuffer);
+	for(unsigned i = 0; i < PIPE_MAX_SAMPLERS; ++i)
+		pipe_sampler_view_reference(&nvfx->fragment_sampler_views[i], 0);
+
 	if (nvfx->draw)
 		draw_destroy(nvfx->draw);
 	FREE(nvfx);
-- 
cgit v1.2.3


From 37fa0cf4eaf6e67876a1f6b33389f17f99b02461 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 3 Aug 2010 22:50:19 +0200
Subject: nvfx: add linear flag for buffers

---
 src/gallium/drivers/nvfx/nv04_surface_2d.c | 1 +
 src/gallium/drivers/nvfx/nv04_surface_2d.h | 2 --
 src/gallium/drivers/nvfx/nvfx_buffer.c     | 2 ++
 src/gallium/drivers/nvfx/nvfx_resource.h   | 2 ++
 4 files changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv04_surface_2d.c b/src/gallium/drivers/nvfx/nv04_surface_2d.c
index 7acbb505df..cd0f4ce4c9 100644
--- a/src/gallium/drivers/nvfx/nv04_surface_2d.c
+++ b/src/gallium/drivers/nvfx/nv04_surface_2d.c
@@ -8,6 +8,7 @@
 #include "nouveau/nouveau_util.h"
 #include "nouveau/nouveau_screen.h"
 #include "nv04_surface_2d.h"
+#include "nvfx_resource.h"
 
 static INLINE int
 nv04_surface_format(enum pipe_format format)
diff --git a/src/gallium/drivers/nvfx/nv04_surface_2d.h b/src/gallium/drivers/nvfx/nv04_surface_2d.h
index 2123c3ed08..b9020dbe96 100644
--- a/src/gallium/drivers/nvfx/nv04_surface_2d.h
+++ b/src/gallium/drivers/nvfx/nv04_surface_2d.h
@@ -38,6 +38,4 @@ nv04_surface_2d_takedown(struct nv04_surface_2d **);
 struct nv04_surface*
 nv04_surface_wrap_for_render(struct pipe_screen *pscreen, struct nv04_surface_2d* eng2d, struct nv04_surface* ns);
 
-#define NVFX_RESOURCE_FLAG_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
-
 #endif
diff --git a/src/gallium/drivers/nvfx/nvfx_buffer.c b/src/gallium/drivers/nvfx/nvfx_buffer.c
index 05b824b8f7..4482d9683e 100644
--- a/src/gallium/drivers/nvfx/nvfx_buffer.c
+++ b/src/gallium/drivers/nvfx/nvfx_buffer.c
@@ -97,6 +97,7 @@ nvfx_buffer_create(struct pipe_screen *pscreen,
 		return NULL;
 
 	buffer->base = *template;
+	buffer->base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
 	buffer->vtbl = &nvfx_buffer_vtbl;
 	pipe_reference_init(&buffer->base.reference, 1);
 	buffer->base.screen = pscreen;
@@ -132,6 +133,7 @@ nvfx_user_buffer_create(struct pipe_screen *pscreen,
 
 	pipe_reference_init(&buffer->base.reference, 1);
 	buffer->vtbl = &nvfx_buffer_vtbl;
+	buffer->base.flags = NVFX_RESOURCE_FLAG_LINEAR;
 	buffer->base.screen = pscreen;
 	buffer->base.format = PIPE_FORMAT_R8_UNORM;
 	buffer->base.usage = PIPE_USAGE_IMMUTABLE;
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
index a68c14cf3f..d28bfab961 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ b/src/gallium/drivers/nvfx/nvfx_resource.h
@@ -20,6 +20,8 @@ struct nvfx_resource {
 	struct nouveau_bo *bo;
 };
 
+#define NVFX_RESOURCE_FLAG_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
+
 #define NVFX_MAX_TEXTURE_LEVELS  16
 
 struct nvfx_miptree {
-- 
cgit v1.2.3


From ac97e8dba654b9b3c5a9459953ce27056bcbb021 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 7 Aug 2010 01:56:01 +0200
Subject: nvfx: add nouveau_resource_on_gpu

Add a function to get whether a resource is likely on the GPU or not.

Currently always returns TRUE.
---
 src/gallium/drivers/nvfx/nvfx_resource.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
index d28bfab961..bdbf3dd3d8 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ b/src/gallium/drivers/nvfx/nvfx_resource.h
@@ -3,9 +3,11 @@
 #define NVFX_RESOURCE_H
 
 #include "util/u_transfer.h"
+#include "util/u_format.h"
+#include "util/u_math.h"
+#include <nouveau/nouveau_bo.h>
 
 struct pipe_resource;
-struct nouveau_bo;
 
 
 /* This gets further specialized into either buffer or texture
@@ -22,6 +24,18 @@ struct nvfx_resource {
 
 #define NVFX_RESOURCE_FLAG_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
 
+static inline int
+nvfx_resource_on_gpu(struct pipe_resource* pr)
+{
+#if 0
+	// a compiler error here means you need to apply libdrm-nouveau-add-domain.patch to libdrm
+	// TODO: return FALSE if not VRAM and on a PCI-E system
+	return ((struct nvfx_resource*)pr)->bo->domain & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART);
+#else
+	return TRUE;
+#endif
+}
+
 #define NVFX_MAX_TEXTURE_LEVELS  16
 
 struct nvfx_miptree {
-- 
cgit v1.2.3


From ed2930e7e2c064458da33089cff902574008bf30 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Fri, 15 Jan 2010 10:11:11 +0100
Subject: nvfx: new 2D: rewrite miptree code, adapt transfers

Changes:
- Disable swizzling on non-RGBA 2D textures, since the current 2D
  code is mostly broken in those cases. A later patch will fix this.
  Thanks to Andrew Randrianasulu who reported this.
- Fix compressed texture transfers and hack around the current 2D
  code inability to copy compressed textures by using direct access.
  Thanks to Andrew Randrianasulu who reported this.

This patch rewrites all the miptree layout and transfer code in the
nvfx driver.

The current code is broken in several ways:
1. 3D textures are laid out first by face, then by level, which is
incorrect
2. Cube maps should have 128-byte aligned faces
3. Swizzled textures have a strange alignment test that seems
unnecessary
4. We store the image_offsets for each face/slice but they can be
easily computed instead
5. "Swizzling" is not supported for compressed formats. They can be
"swizzled" but swizzling only means that there are no gaps (pitch is
level-dependant) and the layout is still linear
6. Swizzling is not supported for non-RGBA formats. All formats (except
possibly depth) can be swizzled according to my testing.

The miptree layout is rewritten based on my empirical testing, which I
posted in the "miptree findings" mail.
The image_offset array is removed, since it can be calculated with a
simple multiplication; the only array in the miptree structure is now
the one for mipmap level starts, which it seems cannot be easily
computed in constant time.

Also, we now directly store a nouveau_bo instead of a pipe_buffer in
the miptree structure, like nv50 does.

Support for render temporaries is removed, and will be readded in a
later patch.

Note that the current temporary code is broken, because it does not
copy the temporary back on render cache flushes.
---
 src/gallium/drivers/nvfx/nv30_fragtex.c  |   6 +-
 src/gallium/drivers/nvfx/nv40_fragtex.c  |  12 +-
 src/gallium/drivers/nvfx/nvfx_miptree.c  | 332 ++++++++++++++-----------------
 src/gallium/drivers/nvfx/nvfx_resource.h |  48 ++++-
 src/gallium/drivers/nvfx/nvfx_state_fb.c |   6 +-
 src/gallium/drivers/nvfx/nvfx_transfer.c |  27 +--
 6 files changed, 207 insertions(+), 224 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
index 0cd70ca104..85489eab28 100644
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv30_fragtex.c
@@ -92,9 +92,9 @@ void
 nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 {
 	struct nvfx_sampler_state *ps = nvfx->tex_sampler[unit];
-	struct nvfx_miptree *nv30mt = (struct nvfx_miptree *)nvfx->fragment_sampler_views[unit]->texture;
-	struct pipe_resource *pt = &nv30mt->base.base;
-	struct nouveau_bo *bo = nv30mt->base.bo;
+	struct nvfx_miptree *mt = (struct nvfx_miptree *)nvfx->fragment_sampler_views[unit]->texture;
+	struct pipe_resource *pt = &mt->base.base;
+	struct nouveau_bo *bo = mt->base.bo;
 	struct nv30_texture_format *tf;
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	uint32_t txf, txs;
diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c
index 0d3e90dcb0..45c34c7ffd 100644
--- a/src/gallium/drivers/nvfx/nv40_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv40_fragtex.c
@@ -111,9 +111,9 @@ nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	struct nvfx_sampler_state *ps = nvfx->tex_sampler[unit];
-	struct nvfx_miptree *nv40mt = (struct nvfx_miptree *)nvfx->fragment_sampler_views[unit]->texture;
-	struct nouveau_bo *bo = nv40mt->base.bo;
-	struct pipe_resource *pt = &nv40mt->base.base;
+	struct nvfx_miptree *mt = (struct nvfx_miptree *)nvfx->fragment_sampler_views[unit]->texture;
+	struct nouveau_bo *bo = mt->base.bo;
+	struct pipe_resource *pt = &mt->base.base;
 	struct nv40_texture_format *tf;
 
 	uint32_t txf, txs, txp;
@@ -149,10 +149,10 @@ nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
 		return;
 	}
 
-	if (!(pt->flags & NVFX_RESOURCE_FLAG_LINEAR)) {
+	if (!mt->linear_pitch)
 		txp = 0;
-	} else {
-		txp  = nv40mt->level[0].pitch;
+	else {
+		txp  = mt->linear_pitch;
 		txf |= NV40TCL_TEX_FORMAT_LINEAR;
 	}
 
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 1fec1ffa42..0b08f88884 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -2,69 +2,111 @@
 #include "pipe/p_defines.h"
 #include "util/u_inlines.h"
 #include "util/u_format.h"
+#include "util/u_memory.h"
 #include "util/u_math.h"
-
+#include "state_tracker/drm_driver.h"
+#include "nouveau/nouveau_winsys.h"
+#include "nouveau/nouveau_screen.h"
+#include "nv04_surface_2d.h"
 #include "nvfx_context.h"
 #include "nvfx_resource.h"
 #include "nvfx_transfer.h"
-#include "nv04_surface_2d.h"
-
-/* Currently using separate implementations for buffers and textures,
- * even though gallium has a unified abstraction of these objects.
- * Eventually these should be combined, and mechanisms like transfers
- * be adapted to work for both buffer and texture uploads.
- */
 
 static void
-nvfx_miptree_layout(struct nvfx_miptree *mt)
+nvfx_miptree_choose_format(struct nvfx_miptree *mt)
 {
 	struct pipe_resource *pt = &mt->base.base;
-	uint width = pt->width0;
-	uint offset = 0;
-	int nr_faces, l, f;
-	uint wide_pitch = pt->bind & (PIPE_BIND_SAMPLER_VIEW |
-				      PIPE_BIND_DEPTH_STENCIL |
-				      PIPE_BIND_RENDER_TARGET |
-				      PIPE_BIND_DISPLAY_TARGET |
-				      PIPE_BIND_SCANOUT);
-
-	if (pt->target == PIPE_TEXTURE_CUBE) {
-		nr_faces = 6;
-	} else
-	if (pt->target == PIPE_TEXTURE_3D) {
-		nr_faces = pt->depth0;
-	} else {
-		nr_faces = 1;
+	unsigned uniform_pitch = 0;
+	static int no_swizzle = -1;
+	if(no_swizzle < 0)
+		no_swizzle = debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE);
+
+	/* Non-uniform pitch textures must be POT */
+	if (pt->width0 & (pt->width0 - 1) ||
+	    pt->height0 & (pt->height0 - 1) ||
+	    pt->depth0 & (pt->depth0 - 1)
+	    )
+		uniform_pitch = 1;
+
+	/* All texture formats except compressed ones can be swizzled
+	 * Unsure about depth, let's prevent swizzling for now
+	 */
+	if (
+		(pt->bind & (PIPE_BIND_SCANOUT | PIPE_BIND_DISPLAY_TARGET))
+		|| (pt->usage & PIPE_USAGE_DYNAMIC) || (pt->usage & PIPE_USAGE_STAGING)
+		|| util_format_is_depth_or_stencil(pt->format)
+		|| util_format_is_compressed(pt->format)
+		// disable swizzled textures on NV04-NV20 as our current drivers don't fully support that
+		// TODO: hardware should support them, fix the drivers and reenable
+		|| nouveau_screen(pt->screen)->device->chipset < 0x30
+		|| no_swizzle
+
+		// disable swizzling for non-RGBA 2D because our current 2D code can't handle anything
+		// else correctly, and even that is semi-broken
+		|| pt->target != PIPE_TEXTURE_2D
+		|| (pt->format != PIPE_FORMAT_B8G8R8A8_UNORM && pt->format != PIPE_FORMAT_B8G8R8X8_UNORM)
+	)
+		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
+
+	/* non compressed formats with uniform pitch must be linear, and vice versa */
+	if(!util_format_is_s3tc(pt->format)
+		&& (uniform_pitch || mt->base.base.flags & NVFX_RESOURCE_FLAG_LINEAR))
+	{
+		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
+		uniform_pitch = 1;
 	}
 
-	for (l = 0; l <= pt->last_level; l++) {
-		if (wide_pitch && (pt->flags & NVFX_RESOURCE_FLAG_LINEAR))
-			mt->level[l].pitch = align(util_format_get_stride(pt->format, pt->width0), 64);
-		else
-			mt->level[l].pitch = util_format_get_stride(pt->format, width);
+	if(uniform_pitch)
+	{
+		mt->linear_pitch = util_format_get_stride(pt->format, pt->width0);
+
+		// TODO: this is only a constraint for rendering and not sampling, apparently
+		// we may also want this unconditionally
+		if(pt->bind & (PIPE_BIND_SAMPLER_VIEW |
+			PIPE_BIND_DEPTH_STENCIL |
+			PIPE_BIND_RENDER_TARGET |
+			PIPE_BIND_DISPLAY_TARGET |
+			PIPE_BIND_SCANOUT))
+			mt->linear_pitch = align(mt->linear_pitch, 64);
+	}
+	else
+		mt->linear_pitch = 0;
+}
 
-		mt->level[l].image_offset =
-			CALLOC(nr_faces, sizeof(unsigned));
+static unsigned
+nvfx_miptree_layout(struct nvfx_miptree *mt)
+{
+	struct pipe_resource* pt = &mt->base.base;
+        uint offset = 0;
 
-		width  = u_minify(width, 1);
+	if(!nvfx_screen(pt->screen)->is_nv4x)
+	{
+		assert(pt->target == PIPE_TEXTURE_RECT
+			|| (util_is_pot(pt->width0) && util_is_pot(pt->height0)));
 	}
 
-	for (f = 0; f < nr_faces; f++) {
-		for (l = 0; l < pt->last_level; l++) {
-			mt->level[l].image_offset[f] = offset;
+	for (unsigned l = 0; l <= pt->last_level; l++)
+	{
+		unsigned size;
+		mt->level_offset[l] = offset;
+
+		if(mt->linear_pitch)
+			size = mt->linear_pitch;
+		else
+			size = util_format_get_stride(pt->format, u_minify(pt->width0, l));
+		size = util_format_get_2d_size(pt->format, size, u_minify(pt->height0, l));
 
-			if (!(pt->flags & NVFX_RESOURCE_FLAG_LINEAR) &&
-			    u_minify(pt->width0, l + 1) > 1 && u_minify(pt->height0, l + 1) > 1)
-				offset += align(mt->level[l].pitch * u_minify(pt->height0, l), 64);
-			else
-				offset += mt->level[l].pitch * u_minify(pt->height0, l);
-		}
+		if(pt->target == PIPE_TEXTURE_3D)
+			size *= u_minify(pt->depth0, l);
 
-		mt->level[l].image_offset[f] = offset;
-		offset += mt->level[l].pitch * u_minify(pt->height0, l);
+		offset += size;
 	}
 
-	mt->total_size = offset;
+	offset = align(offset, 128);
+	mt->face_size = offset;
+	if(mt->base.base.target == PIPE_TEXTURE_CUBE)
+		offset += 5 * mt->face_size;
+	return offset;
 }
 
 static boolean
@@ -79,7 +121,7 @@ nvfx_miptree_get_handle(struct pipe_screen *pscreen,
 
 	return nouveau_screen_bo_get_handle(pscreen,
 					    mt->base.bo,
-					    mt->level[0].pitch,
+					    mt->linear_pitch,
 					    whandle);
 }
 
@@ -88,15 +130,7 @@ static void
 nvfx_miptree_destroy(struct pipe_screen *screen, struct pipe_resource *pt)
 {
 	struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
-	int l;
-
 	nouveau_screen_bo_release(screen, mt->base.bo);
-
-	for (l = 0; l <= pt->last_level; l++) {
-		if (mt->level[l].image_offset)
-			FREE(mt->level[l].image_offset);
-	}
-
 	FREE(mt);
 }
 
@@ -116,76 +150,50 @@ struct u_resource_vtbl nvfx_miptree_vtbl =
    u_default_transfer_inline_write    /* transfer_inline_write */
 };
 
+static struct nvfx_miptree*
+nvfx_miptree_create_skeleton(struct pipe_screen *pscreen, const struct pipe_resource *pt)
+{
+        struct nvfx_miptree *mt;
+
+        if(pt->width0 > 4096 || pt->height0 > 4096)
+                return NULL;
+
+        mt = CALLOC_STRUCT(nvfx_miptree);
+        if (!mt)
+                return NULL;
+
+        mt->base.base = *pt;
+        mt->base.vtbl = &nvfx_miptree_vtbl;
+        pipe_reference_init(&mt->base.base.reference, 1);
+        mt->base.base.screen = pscreen;
+
+        // set this to the actual capabilities, we use it to decide whether to use the 3D engine for copies
+        // TODO: is this the correct way to use Gallium?
+        mt->base.base.bind = pt->bind | PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_DEPTH_STENCIL;
+
+        // on our current driver (and the driver too), format support does not depend on geometry, so don't bother computing it
+        // TODO: may want to revisit this
+        if(!pscreen->is_format_supported(pscreen, pt->format, pt->target, 0, PIPE_BIND_RENDER_TARGET, 0))
+                mt->base.base.bind &=~ PIPE_BIND_RENDER_TARGET;
+        if(!pscreen->is_format_supported(pscreen, pt->format, pt->target, 0, PIPE_BIND_SAMPLER_VIEW, 0))
+                mt->base.base.bind &=~ PIPE_BIND_SAMPLER_VIEW;
+        if(!pscreen->is_format_supported(pscreen, pt->format, pt->target, 0, PIPE_BIND_DEPTH_STENCIL, 0))
+                mt->base.base.bind &=~ PIPE_BIND_DEPTH_STENCIL;
+
+        return mt;
+}
 
 
 struct pipe_resource *
 nvfx_miptree_create(struct pipe_screen *pscreen, const struct pipe_resource *pt)
 {
-	struct nvfx_miptree *mt;
-	static int no_swizzle = -1;
-	if(no_swizzle < 0)
-		no_swizzle = debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE);
-
-	mt = CALLOC_STRUCT(nvfx_miptree);
-	if (!mt)
-		return NULL;
-
-	mt->base.base = *pt;
-	mt->base.vtbl = &nvfx_miptree_vtbl;
-	pipe_reference_init(&mt->base.base.reference, 1);
-	mt->base.base.screen = pscreen;
-
-	/* Swizzled textures must be POT */
-	if (pt->width0 & (pt->width0 - 1) ||
-	    pt->height0 & (pt->height0 - 1))
-		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-	else
-	if (pt->bind & (PIPE_BIND_SCANOUT |
-			PIPE_BIND_DISPLAY_TARGET |
-			PIPE_BIND_DEPTH_STENCIL))
-		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-	else
-	if (pt->usage == PIPE_USAGE_DYNAMIC)
-		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-	else {
-		switch (pt->format) {
-		case PIPE_FORMAT_B5G6R5_UNORM:
-		case PIPE_FORMAT_L8A8_UNORM:
-		case PIPE_FORMAT_A8_UNORM:
-		case PIPE_FORMAT_L8_UNORM:
-		case PIPE_FORMAT_I8_UNORM:
-			/* TODO: we can actually swizzle these formats on nv40, we
-				are just preserving the pre-unification behavior.
-				The whole 2D code is going to be rewritten anyway. */
-			if(nvfx_screen(pscreen)->is_nv4x) {
-				mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-				break;
-			}
-		/* TODO: Figure out which formats can be swizzled */
-		case PIPE_FORMAT_B8G8R8A8_UNORM:
-		case PIPE_FORMAT_B8G8R8X8_UNORM:
-		case PIPE_FORMAT_R16_SNORM:
-		{
-			if (no_swizzle)
-				mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-			break;
-		}
-		default:
-			mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-		}
-	}
+	struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, pt);
+	nvfx_miptree_choose_format(mt);
 
-	/* apparently we can't render to swizzled surfaces smaller than 64 bytes, so make them linear.
-	 * If the user did not ask for a render target, they can still render to it, but it will cost them an extra copy.
-	 * This also happens for small mipmaps of large textures. */
-	if (pt->bind & PIPE_BIND_RENDER_TARGET &&
-	    util_format_get_stride(pt->format, pt->width0) < 64)
-		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
+        unsigned size = nvfx_miptree_layout(mt);
 
-	nvfx_miptree_layout(mt);
+	mt->base.bo = nouveau_screen_bo_new(pscreen, 256, pt->usage, pt->bind, size);
 
-	mt->base.bo = nouveau_screen_bo_new(pscreen, 256,
-            pt->usage, pt->bind, mt->total_size);
 	if (!mt->base.bo) {
 		FREE(mt);
 		return NULL;
@@ -193,54 +201,28 @@ nvfx_miptree_create(struct pipe_screen *pscreen, const struct pipe_resource *pt)
 	return &mt->base.base;
 }
 
-
-
-
+// TODO: redo this, just calling miptree_layout
 struct pipe_resource *
-nvfx_miptree_from_handle(struct pipe_screen *pscreen,
-			 const struct pipe_resource *template,
-			 struct winsys_handle *whandle)
+nvfx_miptree_from_handle(struct pipe_screen *pscreen, const struct pipe_resource *template, struct winsys_handle *whandle)
 {
-	struct nvfx_miptree *mt;
-	unsigned stride;
-
-	/* Only supports 2D, non-mipmapped textures for the moment */
-	if ((template->target != PIPE_TEXTURE_2D &&
-	      template->target != PIPE_TEXTURE_RECT) ||
-	    template->last_level != 0 ||
-	    template->depth0 != 1)
-		return NULL;
-
-	mt = CALLOC_STRUCT(nvfx_miptree);
-	if (!mt)
-		return NULL;
-
-	mt->base.bo = nouveau_screen_bo_from_handle(pscreen, whandle, &stride);
-	if (mt->base.bo == NULL) {
-		FREE(mt);
-		return NULL;
-	}
-
-	mt->base.base = *template;
-	mt->base.vtbl = &nvfx_miptree_vtbl;
-	pipe_reference_init(&mt->base.base.reference, 1);
-	mt->base.base.screen = pscreen;
-	mt->level[0].pitch = stride;
-	mt->level[0].image_offset = CALLOC(1, sizeof(unsigned));
-
-	/* Assume whoever created this buffer expects it to be linear for now */
-	mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-
-	/* XXX: Need to adjust bo refcount??
-	 */
-	/* nouveau_bo_ref(bo, &mt->base.bo); */
-	return &mt->base.base;
+        struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, template);
+        if(whandle->stride) {
+		mt->linear_pitch = whandle->stride;
+		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
+        } else
+		nvfx_miptree_choose_format(mt);
+
+        nvfx_miptree_layout(mt);
+
+        unsigned stride;
+        mt->base.bo = nouveau_screen_bo_from_handle(pscreen, whandle, &stride);
+        if (mt->base.bo == NULL) {
+                FREE(mt);
+                return NULL;
+        }
+        return &mt->base.base;
 }
 
-
-
-
-
 /* Surface helpers, not strictly required to implement the resource vtbl:
  */
 struct pipe_surface *
@@ -248,7 +230,6 @@ nvfx_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
 			 unsigned face, unsigned level, unsigned zslice,
 			 unsigned flags)
 {
-	struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
 	struct nv04_surface *ns;
 
 	ns = CALLOC_STRUCT(nv04_surface);
@@ -263,33 +244,8 @@ nvfx_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
 	ns->base.face = face;
 	ns->base.level = level;
 	ns->base.zslice = zslice;
-	ns->pitch = mt->level[level].pitch;
-
-	if (pt->target == PIPE_TEXTURE_CUBE) {
-		ns->base.offset = mt->level[level].image_offset[face];
-	} else
-	if (pt->target == PIPE_TEXTURE_3D) {
-		ns->base.offset = mt->level[level].image_offset[zslice];
-	} else {
-		ns->base.offset = mt->level[level].image_offset[0];
-	}
-
-	/* create a linear temporary that we can render into if
-	 * necessary.
-	 *
-	 * Note that ns->pitch is always a multiple of 64 for linear
-	 * surfaces and swizzled surfaces are POT, so ns->pitch & 63
-	 * is equivalent to (ns->pitch < 64 && swizzled)
-	 */
-
-	if ((ns->pitch & 63) && 
-	    (ns->base.usage & PIPE_BIND_RENDER_TARGET))
-	{
-		struct nv04_surface_2d* eng2d  =
-			((struct nvfx_screen*)pscreen)->eng2d;
-
-		ns = nv04_surface_wrap_for_render(pscreen, eng2d, ns);
-	}
+	ns->pitch = nvfx_subresource_pitch(pt, level);
+	ns->base.offset = nvfx_subresource_offset(pt, face, level, zslice);
 
 	return &ns->base;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
index bdbf3dd3d8..0e24ec2f1f 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ b/src/gallium/drivers/nvfx/nvfx_resource.h
@@ -39,15 +39,11 @@ nvfx_resource_on_gpu(struct pipe_resource* pr)
 #define NVFX_MAX_TEXTURE_LEVELS  16
 
 struct nvfx_miptree {
-	struct nvfx_resource base;
-	uint total_size;
+        struct nvfx_resource base;
 
-	struct {
-		uint pitch;
-		uint *image_offset;
-	} level[NVFX_MAX_TEXTURE_LEVELS];
-
-	unsigned image_nr;
+        unsigned linear_pitch; /* for linear textures, 0 for swizzled and compressed textures with level-dependent minimal pitch */
+        unsigned face_size; /* 128-byte aligned face/total size */
+        unsigned level_offset[NVFX_MAX_TEXTURE_LEVELS];
 };
 
 static INLINE 
@@ -103,5 +99,41 @@ nvfx_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
 			 unsigned face, unsigned level, unsigned zslice,
 			 unsigned flags);
 
+/* only for miptrees, don't use for buffers */
+
+/* NOTE: for swizzled 3D textures, this just returns the offset of the mipmap level */
+static inline unsigned
+nvfx_subresource_offset(struct pipe_resource* pt, unsigned face, unsigned level, unsigned zslice)
+{
+	if(pt->target == PIPE_BUFFER)
+		return 0;
+	else
+	{
+		struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
+
+		unsigned offset = mt->level_offset[level];
+		if (pt->target == PIPE_TEXTURE_CUBE)
+			offset += mt->face_size * face;
+		else if (pt->target == PIPE_TEXTURE_3D && mt->linear_pitch)
+			offset += zslice * util_format_get_2d_size(pt->format, (mt->linear_pitch ? mt->linear_pitch : util_format_get_stride(pt->format, u_minify(pt->width0, level))),  u_minify(pt->height0, level));
+		return offset;
+	}
+}
+
+static inline unsigned
+nvfx_subresource_pitch(struct pipe_resource* pt, unsigned level)
+{
+	if(pt->target == PIPE_BUFFER)
+		return ((struct nvfx_resource*)pt)->bo->size;
+	else
+	{
+		struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
+
+		if(mt->linear_pitch)
+			return mt->linear_pitch;
+		else
+			return util_format_get_stride(pt->format, u_minify(pt->width0, level));
+	}
+}
 
 #endif
diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c
index 360e569f77..657e315f06 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_fb.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c
@@ -29,7 +29,7 @@ nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 			colour_format = fb->cbufs[i]->format;
 
 		rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
-		nvfx->hw_rt[i].bo = nvfx_surface_buffer(fb->cbufs[i]);
+		nvfx->hw_rt[i].bo = ((struct nvfx_miptree*)fb->cbufs[i]->texture)->base.bo;
 		nvfx->hw_rt[i].offset = fb->cbufs[i]->offset;
 		nvfx->hw_rt[i].pitch = ((struct nv04_surface *)fb->cbufs[i])->pitch;
 	}
@@ -42,7 +42,7 @@ nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 
 	if (fb->zsbuf) {
 		zeta_format = fb->zsbuf->format;
-		nvfx->hw_zeta.bo = nvfx_surface_buffer(fb->zsbuf);
+		nvfx->hw_zeta.bo = ((struct nvfx_miptree*)fb->zsbuf->texture)->base.bo;
 		nvfx->hw_zeta.offset = fb->zsbuf->offset;
 		nvfx->hw_zeta.pitch = ((struct nv04_surface *)fb->zsbuf)->pitch;
 	}
@@ -67,7 +67,7 @@ nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 		depth_only = 1;
 
 		/* Render to depth buffer only */
-		if (!(fb->zsbuf->texture->usage & NVFX_RESOURCE_FLAG_LINEAR)) {
+		if (!(fb->zsbuf->texture->flags & NVFX_RESOURCE_FLAG_LINEAR)) {
 			assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
 
 			rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
diff --git a/src/gallium/drivers/nvfx/nvfx_transfer.c b/src/gallium/drivers/nvfx/nvfx_transfer.c
index 9ff0a93d30..957e586f81 100644
--- a/src/gallium/drivers/nvfx/nvfx_transfer.c
+++ b/src/gallium/drivers/nvfx/nvfx_transfer.c
@@ -59,14 +59,9 @@ nvfx_miptree_transfer_new(struct pipe_context *pipe,
 			  const struct pipe_box *box)
 {
 	struct pipe_screen *pscreen = pipe->screen;
-	struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
 	struct nvfx_transfer *tx;
 	struct pipe_resource tx_tex_template, *tx_tex;
-	static int no_transfer = -1;
 	unsigned bind = nvfx_transfer_bind_flags(usage);
-	if(no_transfer < 0)
-		no_transfer = debug_get_bool_option("NOUVEAU_NO_TRANSFER", FALSE);
-
 
 	tx = CALLOC_STRUCT(nvfx_transfer);
 	if (!tx)
@@ -78,13 +73,13 @@ nvfx_miptree_transfer_new(struct pipe_context *pipe,
 
 	pipe_resource_reference(&tx->base.resource, pt);
 	tx->base.sr = sr;
+	tx->base.stride = nvfx_subresource_pitch(pt, sr.level);
+	tx->base.slice_stride = tx->base.stride * u_minify(pt->height0, sr.level);
 	tx->base.usage = usage;
 	tx->base.box = *box;
-	tx->base.stride = mt->level[sr.level].pitch;
 
 	/* Direct access to texture */
-	if ((pt->usage == PIPE_USAGE_DYNAMIC ||
-	     no_transfer) &&
+	if ((util_format_is_s3tc(pt->format) || pt->usage & PIPE_USAGE_DYNAMIC) &&
 	    pt->flags & NVFX_RESOURCE_FLAG_LINEAR)
 	{
 		tx->direct = true;
@@ -109,7 +104,8 @@ nvfx_miptree_transfer_new(struct pipe_context *pipe,
 		return NULL;
 	}
 
-	tx->base.stride = ((struct nvfx_miptree*)tx_tex)->level[0].pitch;
+	tx->base.stride = ((struct nvfx_miptree*)tx_tex)->linear_pitch;
+	tx->base.slice_stride = tx->base.stride * box->height;
 
 	tx->surface = pscreen->get_tex_surface(pscreen, tx_tex,
 	                                       0, 0, 0,
@@ -181,27 +177,26 @@ nvfx_miptree_transfer_del(struct pipe_context *pipe,
 void *
 nvfx_miptree_transfer_map(struct pipe_context *pipe, struct pipe_transfer *ptx)
 {
-	struct pipe_screen *pscreen = pipe->screen;
 	struct nvfx_transfer *tx = (struct nvfx_transfer *)ptx;
 	struct nv04_surface *ns = (struct nv04_surface *)tx->surface;
 	struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->surface->texture;
-	uint8_t *map = nouveau_screen_bo_map(pscreen, mt->base.bo,
+
+	uint8_t *map = nouveau_screen_bo_map(pipe->screen, mt->base.bo,
 					     nouveau_screen_transfer_flags(ptx->usage));
 
 	if(!tx->direct)
 		return map + ns->base.offset;
 	else
-		return (map + ns->base.offset + 
-			ptx->box.y * ns->pitch + 
-			ptx->box.x * util_format_get_blocksize(ptx->resource->format));
+		return map + ns->base.offset
+		+ util_format_get_2d_size(ns->base.format, ns->pitch, ptx->box.y)
+		+ util_format_get_stride(ptx->resource->format, ptx->box.x);
 }
 
 void
 nvfx_miptree_transfer_unmap(struct pipe_context *pipe, struct pipe_transfer *ptx)
 {
-	struct pipe_screen *pscreen = pipe->screen;
 	struct nvfx_transfer *tx = (struct nvfx_transfer *)ptx;
 	struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->surface->texture;
 
-	nouveau_screen_bo_unmap(pscreen, mt->base.bo);
+	nouveau_screen_bo_unmap(pipe->screen, mt->base.bo);
 }
-- 
cgit v1.2.3


From 23639dc046435716042b68359ac6208d99be82f4 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 3 Aug 2010 21:32:42 +0200
Subject: nvfx: new 2D: rewrite transfer code to use staging transfers

This greatly simplifies the code, and avoids ad-hoc copy code.

Also, these new transfers work for buffers too, even though they
are still used for miptrees only.
---
 src/gallium/drivers/nvfx/nvfx_miptree.c  |   9 +-
 src/gallium/drivers/nvfx/nvfx_transfer.c | 215 ++++++++-----------------------
 src/gallium/drivers/nvfx/nvfx_transfer.h |  10 +-
 3 files changed, 61 insertions(+), 173 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 0b08f88884..27bfa24b28 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -4,6 +4,7 @@
 #include "util/u_format.h"
 #include "util/u_memory.h"
 #include "util/u_math.h"
+#include "util/u_staging.h"
 #include "state_tracker/drm_driver.h"
 #include "nouveau/nouveau_winsys.h"
 #include "nouveau/nouveau_screen.h"
@@ -142,11 +143,11 @@ struct u_resource_vtbl nvfx_miptree_vtbl =
    nvfx_miptree_get_handle,	      /* get_handle */
    nvfx_miptree_destroy,	      /* resource_destroy */
    NULL,			      /* is_resource_referenced */
-   nvfx_miptree_transfer_new,	      /* get_transfer */
-   nvfx_miptree_transfer_del,     /* transfer_destroy */
-   nvfx_miptree_transfer_map,	      /* transfer_map */
+   nvfx_transfer_new,	  	      /* get_transfer */
+   util_staging_transfer_destroy,     /* transfer_destroy */
+   nvfx_transfer_map,		      /* transfer_map */
    u_default_transfer_flush_region,   /* transfer_flush_region */
-   nvfx_miptree_transfer_unmap,	      /* transfer_unmap */
+   nvfx_transfer_unmap,	              /* transfer_unmap */
    u_default_transfer_inline_write    /* transfer_inline_write */
 };
 
diff --git a/src/gallium/drivers/nvfx/nvfx_transfer.c b/src/gallium/drivers/nvfx/nvfx_transfer.c
index 957e586f81..e9c3dd7e55 100644
--- a/src/gallium/drivers/nvfx/nvfx_transfer.c
+++ b/src/gallium/drivers/nvfx/nvfx_transfer.c
@@ -4,199 +4,88 @@
 #include "util/u_format.h"
 #include "util/u_memory.h"
 #include "util/u_math.h"
-#include "nouveau/nouveau_winsys.h"
+#include "util/u_staging.h"
 #include "nvfx_context.h"
 #include "nvfx_screen.h"
 #include "nvfx_state.h"
 #include "nvfx_resource.h"
 #include "nvfx_transfer.h"
 
-struct nvfx_transfer {
-	struct pipe_transfer base;
-	struct pipe_surface *surface;
-	boolean direct;
-};
-
-static void
-nvfx_compatible_transfer_tex(struct pipe_resource *pt, unsigned width, unsigned height,
-			     unsigned bind,
-                             struct pipe_resource *template)
-{
-	memset(template, 0, sizeof(struct pipe_resource));
-	template->target = pt->target;
-	template->format = pt->format;
-	template->width0 = width;
-	template->height0 = height;
-	template->depth0 = 1;
-	template->last_level = 0;
-	template->nr_samples = pt->nr_samples;
-	template->bind = bind;
-	template->usage = PIPE_USAGE_DYNAMIC;
-	template->flags = NVFX_RESOURCE_FLAG_LINEAR;
-}
-
-
-static unsigned nvfx_transfer_bind_flags( unsigned transfer_usage )
+struct nvfx_staging_transfer
 {
-	unsigned bind = 0;
+	struct util_staging_transfer base;
 
-#if 0
-	if (transfer_usage & PIPE_TRANSFER_WRITE)
-		bind |= PIPE_BIND_BLIT_SOURCE;
-
-	if (transfer_usage & PIPE_TRANSFER_READ)
-		bind |= PIPE_BIND_BLIT_DESTINATION;
-#endif
-
-	return bind;
-}
+	unsigned offset;
+	unsigned map_count;
+};
 
 struct pipe_transfer *
-nvfx_miptree_transfer_new(struct pipe_context *pipe,
+nvfx_transfer_new(struct pipe_context *pipe,
 			  struct pipe_resource *pt,
 			  struct pipe_subresource sr,
 			  unsigned usage,
 			  const struct pipe_box *box)
 {
-	struct pipe_screen *pscreen = pipe->screen;
-	struct nvfx_transfer *tx;
-	struct pipe_resource tx_tex_template, *tx_tex;
-	unsigned bind = nvfx_transfer_bind_flags(usage);
+	struct nvfx_staging_transfer* tx;
+	bool direct = !nvfx_resource_on_gpu(pt) && pt->flags & NVFX_RESOURCE_FLAG_LINEAR;
 
-	tx = CALLOC_STRUCT(nvfx_transfer);
-	if (!tx)
+	tx = CALLOC_STRUCT(nvfx_staging_transfer);
+	if(!tx)
 		return NULL;
 
-	/* Don't handle 3D transfers yet.
-	 */
-	assert(box->depth == 1);
-
-	pipe_resource_reference(&tx->base.resource, pt);
-	tx->base.sr = sr;
-	tx->base.stride = nvfx_subresource_pitch(pt, sr.level);
-	tx->base.slice_stride = tx->base.stride * u_minify(pt->height0, sr.level);
-	tx->base.usage = usage;
-	tx->base.box = *box;
+	util_staging_transfer_init(pipe, pt, sr, usage, box, direct, tx);
 
-	/* Direct access to texture */
-	if ((util_format_is_s3tc(pt->format) || pt->usage & PIPE_USAGE_DYNAMIC) &&
-	    pt->flags & NVFX_RESOURCE_FLAG_LINEAR)
+	if(pt->target == PIPE_BUFFER)
 	{
-		tx->direct = true;
-
-		/* XXX: just call the internal nvfx function.  
-		 */
-		tx->surface = pscreen->get_tex_surface(pscreen, pt,
-	                                               sr.face, sr.level,
-						       box->z,
-	                                               bind);
-		return &tx->base;
+		tx->base.base.slice_stride = tx->base.base.stride = ((struct nvfx_resource*)tx->base.staging_resource)->bo->size;
+		if(direct)
+			tx->offset = util_format_get_stride(pt->format, box->x);
+		else
+			tx->offset = 0;
 	}
-
-	tx->direct = false;
-
-	nvfx_compatible_transfer_tex(pt, box->width, box->height, bind, &tx_tex_template);
-
-	tx_tex = pscreen->resource_create(pscreen, &tx_tex_template);
-	if (!tx_tex)
+	else
 	{
-		FREE(tx);
-		return NULL;
+		if(direct)
+		{
+			tx->base.base.stride = nvfx_subresource_pitch(pt, sr.level);
+			tx->base.base.slice_stride = tx->base.base.stride * u_minify(pt->height0, sr.level);
+			tx->offset = nvfx_subresource_offset(pt, sr.face, sr.level, box->z)
+				+ util_format_get_2d_size(pt->format, tx->base.base.stride, box->y)
+				+ util_format_get_stride(pt->format, box->x);
+		}
+		else
+		{
+			tx->base.base.stride = nvfx_subresource_pitch(tx->base.staging_resource, 0);
+			tx->base.base.slice_stride = tx->base.base.stride * tx->base.staging_resource->height0;
+			tx->offset = 0;
+		}
+
+		assert(tx->base.base.stride);
+
+		return &tx->base.base;
 	}
-
-	tx->base.stride = ((struct nvfx_miptree*)tx_tex)->linear_pitch;
-	tx->base.slice_stride = tx->base.stride * box->height;
-
-	tx->surface = pscreen->get_tex_surface(pscreen, tx_tex,
-	                                       0, 0, 0,
-	                                       bind);
-
-	pipe_resource_reference(&tx_tex, NULL);
-
-	if (!tx->surface)
-	{
-		pipe_surface_reference(&tx->surface, NULL);
-		FREE(tx);
-		return NULL;
-	}
-
-	if (usage & PIPE_TRANSFER_READ) {
-		struct nvfx_screen *nvscreen = nvfx_screen(pscreen);
-		struct pipe_surface *src;
-
-		src = pscreen->get_tex_surface(pscreen, pt,
-	                                       sr.face, sr.level, box->z,
-	                                       0 /*PIPE_BIND_BLIT_SOURCE*/);
-
-		/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
-		/* TODO: Check if SIFM can un-swizzle */
-		nvscreen->eng2d->copy(nvscreen->eng2d,
-		                      tx->surface, 0, 0,
-		                      src,
-				      box->x, box->y,
-		                      box->width, box->height);
-
-		pipe_surface_reference(&src, NULL);
-	}
-
-	return &tx->base;
-}
-
-void
-nvfx_miptree_transfer_del(struct pipe_context *pipe,
-			  struct pipe_transfer *ptx)
-{
-	struct nvfx_transfer *tx = (struct nvfx_transfer *)ptx;
-
-	if (!tx->direct && (ptx->usage & PIPE_TRANSFER_WRITE)) {
-		struct pipe_screen *pscreen = pipe->screen;
-		struct nvfx_screen *nvscreen = nvfx_screen(pscreen);
-		struct pipe_surface *dst;
-
-		dst = pscreen->get_tex_surface(pscreen,
-					       ptx->resource,
-	                                       ptx->sr.face,
-					       ptx->sr.level,
-					       ptx->box.z,
-	                                       0 /*PIPE_BIND_BLIT_DESTINATION*/);
-
-		/* TODO: Check if SIFM can deal with x,y,w,h when swizzling */
-		nvscreen->eng2d->copy(nvscreen->eng2d,
-		                      dst, ptx->box.x, ptx->box.y,
-		                      tx->surface, 0, 0,
-		                      ptx->box.width, ptx->box.height);
-
-		pipe_surface_reference(&dst, NULL);
-	}
-
-	pipe_surface_reference(&tx->surface, NULL);
-	pipe_resource_reference(&ptx->resource, NULL);
-	FREE(ptx);
 }
 
 void *
-nvfx_miptree_transfer_map(struct pipe_context *pipe, struct pipe_transfer *ptx)
+nvfx_transfer_map(struct pipe_context *pipe, struct pipe_transfer *ptx)
 {
-	struct nvfx_transfer *tx = (struct nvfx_transfer *)ptx;
-	struct nv04_surface *ns = (struct nv04_surface *)tx->surface;
-	struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->surface->texture;
-
-	uint8_t *map = nouveau_screen_bo_map(pipe->screen, mt->base.bo,
-					     nouveau_screen_transfer_flags(ptx->usage));
-
-	if(!tx->direct)
-		return map + ns->base.offset;
-	else
-		return map + ns->base.offset
-		+ util_format_get_2d_size(ns->base.format, ns->pitch, ptx->box.y)
-		+ util_format_get_stride(ptx->resource->format, ptx->box.x);
+	struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
+	if(!ptx->data)
+	{
+		struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
+		uint8_t *map = nouveau_screen_bo_map(pipe->screen, mt->base.bo, nouveau_screen_transfer_flags(ptx->usage));
+		ptx->data = map + tx->offset;
+	}
+	++tx->map_count;
+	return ptx->data;
 }
 
 void
-nvfx_miptree_transfer_unmap(struct pipe_context *pipe, struct pipe_transfer *ptx)
+nvfx_transfer_unmap(struct pipe_context *pipe, struct pipe_transfer *ptx)
 {
-	struct nvfx_transfer *tx = (struct nvfx_transfer *)ptx;
-	struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->surface->texture;
+	struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
+	struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
 
-	nouveau_screen_bo_unmap(pipe->screen, mt->base.bo);
+	if(!--tx->map_count)
+		nouveau_screen_bo_unmap(pipe->screen, mt->base.bo);
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_transfer.h b/src/gallium/drivers/nvfx/nvfx_transfer.h
index 3e3317b2c7..20f20d5b0b 100644
--- a/src/gallium/drivers/nvfx/nvfx_transfer.h
+++ b/src/gallium/drivers/nvfx/nvfx_transfer.h
@@ -7,19 +7,17 @@
 
 
 struct pipe_transfer *
-nvfx_miptree_transfer_new(struct pipe_context *pcontext,
+nvfx_transfer_new(struct pipe_context *pcontext,
 			  struct pipe_resource *pt,
 			  struct pipe_subresource sr,
 			  unsigned usage,
 			  const struct pipe_box *box);
-void
-nvfx_miptree_transfer_del(struct pipe_context *pcontext,
-			  struct pipe_transfer *ptx);
+
 void *
-nvfx_miptree_transfer_map(struct pipe_context *pcontext,
+nvfx_transfer_map(struct pipe_context *pcontext,
 			  struct pipe_transfer *ptx);
 void
-nvfx_miptree_transfer_unmap(struct pipe_context *pcontext,
+nvfx_transfer_unmap(struct pipe_context *pcontext,
 			    struct pipe_transfer *ptx);
 
 
-- 
cgit v1.2.3


From 24a4ea003f14a96ed07fdc4e92a67610655befad Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 19 Jan 2010 18:51:10 +0100
Subject: nv04-nv40: new 2D: add new Gallium-independent 2D engine

This patch add a brand new nv04-nv40 2D engine module.
It should correctly implement all operations involving swizzled, and 3D-swizzled surfaces.

This code is independent from the Gallium framework and can thus be reused in the DDX and classic Mesa drivers (it's only likely to be useful in the latter, though).

Currently, surface_copy and surface_fill are broken for 3D textures, for swizzled source textures and possibly for some misaligned cases

The code is based around the new nv04_region structure, which encapsulates the information from pipe_surface needed for the 2D engine and CPU copies.
The use of nv04_region makes the code independent of the Gallium framework and allows to transform the nv04_region without clobbering the nv04_region.
The existing M2MF, blitter, and SWIZZLED_SURFACE paths have been improved and a new CPU path has been added.
There is also support to tell the caller to use the 3D engine.

The main feature of the copy/fill setup algorithm is linearization/contiguous-linearization of swizzled surfaces.
The idea of linearization is that some swizzled surfaces are laid out like linear ones (1xN, 2xN, Nx1) and can thus be used as such (e.g. useful for copying single pixels).
Also, some rectangles (e.g. the whole surface) are contiguous in memory. If both the source and destination rectangles are swizzled but contiguous, then they can be regarded as both linear: this is the idea of "contiguous linearization".
This, for instance, allows to use the 2D engine to duplicate the content of a swizzled surface to another swizzled surface, by pretending they are actually linear.
After linearization, the result may not be 64-byte aligned. Another transformation is done to enlarge the linear surface so that it becomes 64-byte aligned.
This is also used to 64-byte align swizzled texture mipmaps.

The inner loop of the CPU path is as optimized as possible without using SSE/SSE2.
Future improvements could include SSE/SSE2 support, and possibly a faster coordinate swizzling algorithm (which is however not used in the inner loop).
It may be a good idea to autogenerate swizzling code at least for all possible POT 2D texture dimensions  (less than 256), maybe for all 3D ones too (less than 4096).
Also, it woud be a very good idea to make a copy with the GPU first if the source surface is in uncached memory.
---
 src/gallium/drivers/nvfx/Makefile        |    1 +
 src/gallium/drivers/nvfx/nv04_2d.c       | 1320 ++++++++++++++++++++++++++++++
 src/gallium/drivers/nvfx/nv04_2d.h       |   87 ++
 src/gallium/drivers/nvfx/nv04_2d_loops.h |   70 ++
 4 files changed, 1478 insertions(+)
 create mode 100644 src/gallium/drivers/nvfx/nv04_2d.c
 create mode 100644 src/gallium/drivers/nvfx/nv04_2d.h
 create mode 100644 src/gallium/drivers/nvfx/nv04_2d_loops.h

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/Makefile b/src/gallium/drivers/nvfx/Makefile
index c1d57ca396..6536343e44 100644
--- a/src/gallium/drivers/nvfx/Makefile
+++ b/src/gallium/drivers/nvfx/Makefile
@@ -5,6 +5,7 @@ LIBNAME = nvfx
 
 C_SOURCES = \
 	nv04_surface_2d.c \
+	nv04_2d.c \
 	nvfx_buffer.c \
 	nvfx_context.c \
 	nvfx_clear.c \
diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c
new file mode 100644
index 0000000000..b2f2ae79e1
--- /dev/null
+++ b/src/gallium/drivers/nvfx/nv04_2d.c
@@ -0,0 +1,1320 @@
+/**************************************************************************
+ *
+ * Copyright 2009 Ben Skeggs
+ * Copyright 2009 Younes Manton
+ * Copyright 2010 Luca Barbieri
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ **************************************************************************/
+
+/* this code has no Mesa or Gallium dependency and can be reused in the classic Mesa driver or DDX */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <nouveau/nouveau_class.h>
+#include <nouveau/nouveau_device.h>
+#include <nouveau/nouveau_pushbuf.h>
+#include <nouveau/nouveau_channel.h>
+#include <nouveau/nouveau_bo.h>
+#include <nouveau/nouveau_notifier.h>
+#include <nouveau/nouveau_grobj.h>
+#include "nv04_2d.h"
+
+/* avoid depending on Mesa/Gallium */
+#ifdef __GNUC__
+#define likely(x) __builtin_expect(!!(x), 1)
+#define unlikely(x) __builtin_expect(!!(x), 0)
+#else
+#define likely(x) !!(x)
+#define unlikely(x) !!(x)
+#endif
+
+#define MIN2( A, B )   ( (A)<(B) ? (A) : (B) )
+#define MAX2( A, B )   ( (A)>(B) ? (A) : (B) )
+
+struct nv04_2d_context
+{
+	struct nouveau_notifier *ntfy;
+	struct nouveau_grobj *surf2d;
+	struct nouveau_grobj *swzsurf;
+	struct nouveau_grobj *m2mf;
+	struct nouveau_grobj *rect;
+	struct nouveau_grobj *sifm;
+	struct nouveau_grobj *blit;
+};
+
+static inline int
+align(int value, int alignment)
+{
+   return (value + alignment - 1) & ~(alignment - 1);
+}
+
+static inline int
+util_is_pot(unsigned x)
+{
+   return (x & (x - 1)) == 0;
+}
+
+/* Integer base-2 logarithm, rounded towards zero. */
+static inline unsigned log2i(unsigned i)
+{
+	unsigned r = 0;
+
+	if (i & 0xffff0000) {
+		i >>= 16;
+		r += 16;
+	}
+	if (i & 0x0000ff00) {
+		i >>= 8;
+		r += 8;
+	}
+	if (i & 0x000000f0) {
+		i >>= 4;
+		r += 4;
+	}
+	if (i & 0x0000000c) {
+		i >>= 2;
+		r += 2;
+	}
+	if (i & 0x00000002) {
+		r += 1;
+	}
+	return r;
+}
+
+//#define NV04_REGION_DEBUG
+
+// Yes, we really want to inline everything, since all the functions are used only once
+#if defined(__GNUC__) && defined(DEBUG)
+#define inline __attribute__((always_inline)) inline
+#endif
+
+static inline unsigned
+nv04_swizzle_bits_square(unsigned x, unsigned y)
+{
+	unsigned u = (x & 0x001) << 0 |
+		     (x & 0x002) << 1 |
+		     (x & 0x004) << 2 |
+		     (x & 0x008) << 3 |
+		     (x & 0x010) << 4 |
+		     (x & 0x020) << 5 |
+		     (x & 0x040) << 6 |
+		     (x & 0x080) << 7 |
+		     (x & 0x100) << 8 |
+		     (x & 0x200) << 9 |
+		     (x & 0x400) << 10 |
+		     (x & 0x800) << 11;
+
+	unsigned v = (y & 0x001) << 1 |
+		     (y & 0x002) << 2 |
+		     (y & 0x004) << 3 |
+		     (y & 0x008) << 4 |
+		     (y & 0x010) << 5 |
+		     (y & 0x020) << 6 |
+		     (y & 0x040) << 7 |
+		     (y & 0x080) << 8 |
+		     (y & 0x100) << 9 |
+		     (y & 0x200) << 10 |
+		     (y & 0x400) << 11 |
+		     (y & 0x800) << 12;
+	return v | u;
+}
+
+/* rectangular swizzled textures are linear concatenations of swizzled square tiles */
+static inline unsigned
+nv04_swizzle_bits_2d(unsigned x, unsigned y, unsigned w, unsigned h)
+{
+	if(h <= 1)
+		return x;
+	else
+	{
+		unsigned s = MIN2(w, h);
+		unsigned m = s - 1;
+		return (((x | y) & ~m) * s) | nv04_swizzle_bits_square(x & m, y & m);
+	}
+}
+
+// general 3D texture case
+static inline unsigned
+nv04_swizzle_bits(unsigned x, unsigned y, unsigned z, unsigned w, unsigned h, unsigned d)
+{
+	if(d <= 1)
+		return nv04_swizzle_bits_2d(x, y, w, h);
+	else
+	{
+		// TODO: autogenerate code for all possible texture sizes (13 * 13 * 13 with dims <= 4096) and do a single indirect call
+		unsigned v = 0;
+		w >>= 1;
+		h >>= 1;
+		d >>= 1;
+		for(int i = 0;;)
+		{
+			int oldi = i;
+			if(likely(w))
+			{
+				v |= (x & 1) << i;
+				x >>= 1;
+				w >>= 1;
+				++i;
+			}
+
+			if(likely(h))
+			{
+				v |= (y & 1) << i;
+				y >>= 1;
+				h >>= 1;
+				++i;
+			}
+
+			if(likely(d))
+			{
+				v |= (z & 1) << i;
+				z >>= 1;
+				d >>= 1;
+				++i;
+			}
+
+			if(i == oldi)
+				break;
+		}
+		return v;
+	}
+}
+
+unsigned
+nv04_region_begin(struct nv04_region* rgn, unsigned w, unsigned h)
+{
+	if(rgn->pitch)
+		return rgn->pitch * rgn->y + (rgn->x << rgn->bpps);
+	else
+		return nv04_swizzle_bits(rgn->x, rgn->y, rgn->z, rgn->w, rgn->h, rgn->d) << rgn->bpps;
+}
+
+unsigned
+nv04_region_end(struct nv04_region* rgn, unsigned w, unsigned h)
+{
+	if(rgn->pitch)
+		return rgn->pitch * (rgn->y + h - 1) + ((rgn->x + w) << rgn->bpps);
+	else
+		return (nv04_swizzle_bits(rgn->x + w - 1, rgn->y + h - 1, rgn->z, rgn->w, rgn->h, rgn->d) + 1) << rgn->bpps;
+}
+
+// *pitch = -1 -> use 3D swizzling for (x, y), *pitch = 0 -> use 2D swizzling, other *pitch -> use linear calculations
+// returns 2 if pixel order is 3D-swizzled and 1 if subrect is 2D-swizzled
+/* *pitch == -1 ret = 0 -> 3D swizzled subrect
+ * *pitch == 0 ret = 0 -> 2D swizzled subrect
+ * *pitch > 0 ret = 0 -> linear subrect
+ * *pitch > 0 ret = 1 -> linear subrect, but with swizzled 3D data inside
+ */
+
+static inline void
+nv04_region_print(struct nv04_region* rgn)
+{
+	fprintf(stderr, "<%i[%i]> ", rgn->bo->handle, rgn->offset);
+	if(rgn->pitch)
+		fprintf(stderr, "lin %i", rgn->pitch);
+	else
+		fprintf(stderr, "swz %ix%ix%i", rgn->w, rgn->h, rgn->d);
+	fprintf(stderr, " (%i, %i, %i)", rgn->x, rgn->y, rgn->z);
+}
+
+static inline void
+nv04_region_assert(struct nv04_region* rgn, unsigned w, unsigned h)
+{
+	unsigned end = rgn->offset + nv04_region_end(rgn, w, h);
+
+	assert(rgn->offset <= (int)rgn->bo->size);
+	assert(end <= rgn->bo->size);
+	if(!rgn->pitch) {
+		assert(util_is_pot(rgn->w));
+		assert(util_is_pot(rgn->h));
+	}
+}
+
+/* determine if region can be linearized or fake-linearized */
+static inline int
+nv04_region_is_contiguous(struct nv04_region* rgn, int w, int h)
+{
+	if(rgn->pitch)
+		return rgn->pitch == w << rgn->bpps;
+
+	// redundant, but this is the fast path for the common case
+	if(w == rgn->w && h == rgn->h && rgn->d <= 1)
+		return 1;
+
+	// must be POT
+	if((w & (w - 1)) || (h & (h - 1)))
+		return 0;
+
+	// must be aligned
+	if((rgn->x & (w - 1)) || (rgn->y & (h - 1)))
+		return 0;
+
+	if(rgn->d > 1)
+		return 0;
+
+	int surf_min = MIN2(rgn->w, rgn->h);
+	int rect_min = MIN2(w, h);
+
+	if((rect_min == surf_min) || (w == h) || (w == 2 * h))
+		return 1;
+
+	return 0;
+}
+
+// double the pitch until it is larger than the alignment, or the height becomes odd or 1
+static inline void
+nv04_region_contiguous_shape(struct nv04_region* rgn, int* w, int* h, int align)
+{
+	while(!(*h & 1) && (*w << rgn->bpps) < (1 << align))
+	{
+		*w <<= 1;
+		*h >>= 1;
+	}
+
+	while((*w << rgn->bpps) > 16384 && !(*w & 1))
+	{
+		*w >>= 1;
+		*h <<= 1;
+	}
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tCONTIGUOUS %ix%i\n", *w, *h);
+#endif
+}
+
+static inline void
+nv04_region_linearize_contiguous(struct nv04_region* rgn, unsigned w, unsigned h)
+{
+	int pos;
+	if(rgn->pitch)
+	{
+		rgn->offset += rgn->y * rgn->pitch + (rgn->x << rgn->bpps);
+		rgn->x = 0;
+		rgn->y = 0;
+	}
+	else
+	{
+		rgn->offset += (rgn->w * rgn->h * rgn->z) << rgn->bpps;
+		pos = nv04_swizzle_bits(rgn->x, rgn->y, rgn->z, rgn->w, rgn->h, rgn->d);
+		rgn->x = pos & (w - 1);
+		rgn->y = pos / w;
+	}
+	rgn->pitch = w << rgn->bpps;
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tLINEARIZE ");
+	nv04_region_print(rgn);
+	fprintf(stderr, "\n");
+#endif
+}
+
+	/* preserve the offset! */
+	/*
+	rgn->pitch = util_format_get_stride(rgn->format, w);
+	int pos = nv04_swizzle_bits(rgn->x, rgn->y, rgn->z, rgn->w, rgn->h, rgn->d);
+	rgn->x = pos & (w - 1);
+	rgn->y = pos & ~(w - 1);
+	*/
+
+	/*
+	rgn->offset +=
+	rgn->pitch = util_format_get_stride(rgn->format, w);
+	rgn->x = 0;
+	rgn->y = 0;
+	*/
+
+/* This code will get used for, and always succeed on:
+ * - 4x2 1bpp swizzled texture mipmap levels
+ * - linear regions created by linearization
+ *
+ * This code will get used for, and MAY work for:
+ * - misaligned texture blanket
+ * - linear surfaces created without wide_pitch (in this case, it will only work if we are lucky)
+ *
+ * The general case requires splitting the region in 2.
+ */
+static inline int
+nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int shift)
+{
+	if(rgn->pitch > 0)
+	{
+		assert(!(rgn->offset & ((1 << rgn->bpps) - 1))); // fatal!
+		int delta = rgn->offset & ((1 << shift) - 1);
+
+		if(h <= 1)
+		{
+			rgn->x += delta >> rgn->bpps;
+			rgn->offset -= delta;
+			rgn->pitch = align((rgn->x + w) << rgn->bpps, 1 << shift);
+		}
+		else
+		{
+			int newxo = (rgn->x << rgn->bpps) + delta;
+			int dy = newxo / rgn->pitch;
+			newxo -= dy * rgn->pitch;
+			if((newxo + (w << rgn->bpps)) > rgn->pitch)
+			{
+				// TODO: split the region into two rectangles (!) if *really* necessary, unless the hardware actually supports "wrapping" rectangles
+				// this does not happen if the surface is pitch-aligned, which it should always be
+				assert(0);
+				return -1;
+			}
+			rgn->x = newxo >> rgn->bpps;
+			rgn->y += dy;
+		}
+	}
+	else
+	{
+		// we don't care about the alignment of 3D surfaces since the 2D engine can't use them
+		if(rgn->d < 0)
+			return -1;
+
+		int size;
+		int min = MIN2(rgn->w, rgn->h);
+		size = min * min << rgn->bpps;
+
+		// this is unfixable, and should not be happening
+		if(rgn->offset & (size - 1))
+			return -1;
+
+		int v = (rgn->offset & ((1 << shift) - 1)) / size;
+		rgn->offset -= v * size;
+
+		if(rgn->h == min)
+		{
+			unsigned w;
+			rgn->x += rgn->h * v;
+			w = rgn->w + rgn->h * v;
+
+			while(rgn->w < w)
+				rgn->w += rgn->w;
+		}
+		else
+		{
+			unsigned h;
+			rgn->y += rgn->w * v;
+			h = rgn->h + rgn->w * v;
+
+			while(rgn->h < h)
+				rgn->h += rgn->h;
+		}
+	}
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tALIGNED ");
+	nv04_region_print(rgn);
+	fprintf(stderr, "\n");
+#endif
+	return 0;
+}
+
+// both pitch and shift
+// will leave the region unchanged if it fails
+static inline int
+nv04_region_align(struct nv04_region* rgn, unsigned w, unsigned h, int shift)
+{
+	if(rgn->pitch & ((1 << shift) - 1))
+	{
+		if(h == 1)
+			goto do_align; /* this will fix pitch too in this case */
+		else
+			return -1;
+	}
+
+	if(rgn->offset & ((1 << shift) - 1))
+	{
+		do_align:
+		if(nv04_region_do_align_offset(rgn, w, h, shift))
+			return -1;
+	}
+	return 0;
+}
+
+/* this contains 22 different copy loops after preprocessing. unfortunately, it's necessary */
+void
+nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, int h)
+{
+	if(dst->bo != src->bo)
+	{
+		nouveau_bo_map(dst->bo, NOUVEAU_BO_WR);
+		nouveau_bo_map(src->bo, NOUVEAU_BO_RD);
+	}
+	else
+		nouveau_bo_map(dst->bo, NOUVEAU_BO_WR | NOUVEAU_BO_RD);
+
+	uint8_t* mdst = dst->bo->map + dst->offset;
+	uint8_t* msrc = src->bo->map + src->offset;
+
+	int size = w << dst->bpps;
+
+	nv04_region_assert(dst, w, h);
+	nv04_region_assert(src, w, h);
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tRGN_COPY_CPU [%i, %i: %i] ", w, h, dst->bpps);
+	for(int i = 0; i < 2; ++i)
+	{
+		nv04_region_print(i ? src : dst);
+		fprintf(stderr, i ? "\n" : " <- ");
+	}
+
+//	for(int i = 0; i < 16; ++i)
+//		fprintf(stderr, "%02x ", msrc[i]);
+//	fprintf(stderr, "\n");
+#endif
+
+	// TODO: support overlapping copies!
+	if(src->pitch && dst->pitch)
+	{
+		mdst += dst->y * dst->pitch + (dst->x << dst->bpps);
+		msrc += src->y * src->pitch + (src->x << src->bpps);
+		if(dst->bo != src->bo)
+			goto simple;
+		else if(mdst < msrc)
+		{
+			if(mdst + size <= msrc)
+			{
+simple:
+				for(int iy = 0; iy < h; ++iy)
+				{
+					assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
+					assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
+					memcpy(mdst, msrc, size);
+					msrc += src->pitch; mdst += dst->pitch;
+				}
+			}
+			else
+			{
+				for(int iy = 0; iy < h; ++iy)
+				{
+					assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
+					assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
+					memmove(mdst, msrc, size);
+					msrc += src->pitch; mdst += dst->pitch;
+				}
+			}
+		}
+		else
+		{
+			/* copy backwards so we don't destroy data we have to read yet */
+			if(msrc + size <= mdst)
+			{
+				for(int iy = h - 1; iy >= 0; --iy)
+				{
+					assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
+					assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
+					memcpy(mdst, msrc, size);
+					msrc += src->pitch; mdst += dst->pitch;
+				}
+			}
+			else
+			{
+				for(int iy = h - 1; iy >= 0; --iy)
+				{
+					assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
+					assert(msrc + size <= (uint8_t*)src->bo->map + src->bo->size);
+					memmove(mdst, msrc, size);
+					msrc += src->pitch; mdst += dst->pitch;
+				}
+			}
+		}
+	}
+	else
+	{
+		int* dswx;
+		int* dswy;
+		int* sswx;
+		int* sswy;
+
+		if(!dst->pitch)
+		{
+			dswx = alloca(w * sizeof(int));
+			for(int ix = 0; ix < w; ++ix) // we are adding, so z cannot be contributed by both
+				dswx[ix] = nv04_swizzle_bits(dst->x + ix, 0, 0, dst->w, dst->h, dst->d);
+			dswy = alloca(h * sizeof(int));
+			for(int iy = 0; iy < h; ++iy)
+				dswy[iy] = nv04_swizzle_bits(0, dst->y + iy, dst->z, dst->w, dst->h, dst->d);
+		}
+
+		if(!src->pitch)
+		{
+			sswx = alloca(w * sizeof(int));
+			for(int ix = 0; ix < w; ++ix)
+				sswx[ix] = nv04_swizzle_bits(src->x + ix, 0, 0, src->w, src->h, src->d);
+			sswy = alloca(h * sizeof(int));
+			for(int iy = 0; iy < h; ++iy)
+				sswy[iy] = nv04_swizzle_bits(0, src->y + iy, src->z, src->w, src->h, src->d);
+		}
+
+		int dir = 1;
+		/* do backwards copies for overlapping swizzled surfaces */
+		if(dst->pitch == src->pitch && dst->offset == src->offset)
+		{
+			if(dst->y > src->y || (dst->y == src->y && dst->x > src->x))
+				dir = -1;
+		}
+
+#define SWIZZLED_COPY_LOOPS
+		if(dir == 1)
+		{
+			int dir = 1;
+#define LOOP_Y for(int iy = 0; iy < h; ++iy)
+#define LOOP_X for(int ix = 0; ix < w; ++ix)
+#include "nv04_2d_loops.h"
+#undef LOOP_X
+#undef LOOP_Y
+		}
+		else
+		{
+			int dir = -1;
+#define LOOP_Y for(int iy = h - 1; iy >= 0; --iy)
+#define LOOP_X for(int ix = w - 1; ix >= 0; --ix)
+#include "nv04_2d_loops.h"
+#undef LOOP_X
+#undef LOOP_Y
+		}
+#undef SWIZZLED_COPY_LOOP
+	}
+
+	if(src->bo != dst->bo)
+		nouveau_bo_unmap(src->bo);
+	nouveau_bo_unmap(dst->bo);
+}
+
+/* TODO: if the destination is swizzled, we are doing random writes, which causes write combining to fail
+ * the alternative is to read, modify and copy back, which may or may not be faster
+ * loading 3D textures is a common case that hits this and could probably benefit from the temporary
+ */
+void
+nv04_region_fill_cpu(struct nv04_region* dst, int w, int h, unsigned value)
+{
+	uint8_t* mdst = (nouveau_bo_map(dst->bo, NOUVEAU_BO_WR), dst->bo->map + dst->offset);
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tRGN_FILL_CPU ");
+	nv04_region_print(dst);
+	fprintf(stderr, "\n");
+#endif
+
+	nv04_region_assert(dst, w, h);
+
+	if(dst->pitch)
+	{
+		unsigned size = w << dst->bpps;
+
+#define FILL(T) do { \
+			for(int iy = 0; iy < h; ++iy) \
+			{ \
+				assert((char*)((T*)mdst + w) <= (char*)dst->bo->map + dst->bo->size); \
+				for(int ix = 0; ix < w; ++ix) \
+					((T*)mdst)[ix] = (T)value; \
+				mdst += dst->pitch; \
+			} \
+		} while(0)
+
+		mdst += dst->y * dst->pitch + (dst->x << dst->bpps);
+
+		if(dst->bpps == 0)
+		{
+ms:
+			assert(mdst + size * h <= (uint8_t*)dst->bo->map + dst->bo->size);
+			if(size == dst->pitch)
+				memset(mdst, (uint8_t)value, size * h);
+			else
+			{
+				for(int iy = 0; iy < h; ++iy)
+				{
+					assert(mdst + size <= (uint8_t*)dst->bo->map + dst->bo->size);
+					memset(mdst, (uint8_t)value, size);
+					mdst += dst->pitch;
+				}
+			}
+		}
+		else if(dst->bpps == 1)
+		{
+			if(!((uint8_t)value ^ (uint8_t)(value >> 8)))
+				goto ms;
+
+			FILL(uint16_t);
+		}
+		else if(dst->bpps == 2)
+		{
+			if(value == (uint8_t)value * 0x1010101)
+				goto ms;
+			FILL(uint32_t);
+		}
+		else
+			assert(0);
+#undef FILL
+	}
+	else
+	{
+		int* dswx;
+		int* dswy;
+
+		dswx = alloca(w * sizeof(int));
+		for(int ix = 0; ix < w; ++ix)
+			dswx[ix] = nv04_swizzle_bits(dst->x + ix, 0, dst->z, dst->w, dst->h, dst->d);
+		dswy = alloca(h * sizeof(int));
+		for(int iy = 0; iy < h; ++iy)
+			dswy[iy] = nv04_swizzle_bits(0, dst->y + iy, dst->z, dst->w, dst->h, dst->d);
+
+#define FILL(T) do { \
+			T tvalue = (T)value; \
+			for(int iy = 0; iy < h; ++iy) \
+			{ \
+				T* pdst = (T*)mdst + dswy[iy]; \
+				for(int ix = 0; ix < w; ++ix) \
+				{ \
+					assert((uint8_t*)&pdst[dswx[ix] + 1] <= (uint8_t*)dst->bo->map + dst->bo->size); \
+					pdst[dswx[ix]] = tvalue; \
+				} \
+			} \
+		} while(0)
+
+		if(dst->bpps == 0)
+			FILL(uint8_t);
+		else if(dst->bpps == 1)
+			FILL(uint16_t);
+		else if(dst->bpps == 2)
+			FILL(uint32_t);
+		else
+			assert(0 && "unhandled bpp");
+#undef FILL
+	}
+
+	nouveau_bo_unmap(dst->bo);
+}
+
+static void
+nv04_region_copy_swizzle(struct nv04_2d_context *ctx,
+			  struct nv04_region* dst,
+			  struct nv04_region* src,
+			  int w, int h, int cs2d_format, int sifm_format)
+{
+	struct nouveau_channel *chan = ctx->swzsurf->channel;
+	struct nouveau_grobj *swzsurf = ctx->swzsurf;
+	struct nouveau_grobj *sifm = ctx->sifm;
+	/* Max width & height may not be the same on all HW, but must be POT */
+	unsigned max_shift = 10;
+	unsigned cw = 1 << max_shift;
+	unsigned ch = 1 << max_shift;
+	unsigned sx = dst->x >> max_shift;
+	unsigned sy = dst->y >> max_shift;
+	unsigned ex = (dst->x + w - 1) >> max_shift;
+	unsigned ey = (dst->y + h - 1) >> max_shift;
+	unsigned chunks = (ex - sx + 1) * (ey - sy + 1);
+	if(dst->w < cw)
+		cw = dst->w;
+	if(dst->h < ch)
+		ch = dst->h;
+	unsigned chunk_size = cw * ch << dst->bpps;
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tRGN_COPY_SWIZZLE [%i, %i: %i] ", w, h, dst->bpps);
+	for(int i = 0; i < 2; ++i)
+	{
+		nv04_region_print(i ? src : dst);
+		fprintf(stderr, i ? "\n" : " <- ");
+	}
+#endif
+
+	nv04_region_assert(dst, w, h);
+	nv04_region_assert(src, w, h);
+
+	MARK_RING (chan, 8 + chunks * 17, 2 + chunks * 2);
+
+	BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
+	OUT_RELOCo(chan, dst->bo,
+			NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+	BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
+	OUT_RING  (chan, cs2d_format |
+			 log2i(cw) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
+			 log2i(ch) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
+
+	BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
+	OUT_RELOCo(chan, src->bo,
+			 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+	BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
+	OUT_RING  (chan, swzsurf->handle);
+
+	assert(!(dst->offset & 63));
+
+	for (int cy = sy; cy <= ey; ++cy) {
+	  int ry = MAX2(0, (int)(dst->y - ch * cy));
+	  int rh = MIN2((int)ch, (int)(dst->y - ch * cy + h)) - ry;
+	  for (int cx = sx; cx <= ex; ++cx) {
+	    int rx = MAX2(0, (int)(dst->x - cw * cx));
+	    int rw = MIN2((int)cw, (int)(dst->x - cw * cx + w)) - rx;
+
+	    BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
+
+	    unsigned dst_offset = dst->offset + (nv04_swizzle_bits_2d(cx * cw, cy * ch, dst->w, dst->h) << dst->bpps);
+	    assert(dst_offset <= dst->bo->size);
+	    assert(dst_offset + chunk_size <= dst->bo->size);
+	    OUT_RELOCl(chan, dst->bo, dst_offset,
+			    NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+	    BEGIN_RING(chan, sifm, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
+	    OUT_RING  (chan, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
+	    OUT_RING  (chan, sifm_format);
+	    OUT_RING  (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
+	    OUT_RING  (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT));
+	    OUT_RING  (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | rw);
+	    OUT_RING  (chan, rx | (ry << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT));
+	    OUT_RING  (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | rw);
+	    OUT_RING  (chan, 1 << 20);
+	    OUT_RING  (chan, 1 << 20);
+
+	    BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
+	    OUT_RING  (chan, rh << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | align(rw, 8));
+	    OUT_RING  (chan, src->pitch |
+			     NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
+			     NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
+	    unsigned src_offset = src->offset + (cy * ch + ry + src->y - dst->y) * src->pitch + ((cx * cw + rx + src->x - dst->x) << src->bpps);
+	    assert(src_offset <= src->bo->size);
+	    assert(src_offset + (src->pitch * (rh - 1)) + (rw << src->bpps) <= src->bo->size);
+	    OUT_RELOCl(chan, src->bo, src_offset,
+			     NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+	    OUT_RING  (chan, 0);
+	  }
+	}
+}
+
+static inline void
+nv04_copy_m2mf_begin(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, struct nouveau_bo* srcbo, unsigned commands)
+{
+	struct nouveau_channel *chan = ctx->m2mf->channel;
+	struct nouveau_grobj *m2mf = ctx->m2mf;
+	MARK_RING (chan, 3 + commands * 9, 2 + commands * 2);
+	BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
+	OUT_RELOCo(chan, srcbo,
+		   NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+	OUT_RELOCo(chan, dstbo,
+		   NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+}
+
+static inline void
+nv04_copy_m2mf_body(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int* pdstoff, unsigned dstpitch, struct nouveau_bo* srcbo, int* psrcoff, unsigned srcpitch, unsigned size, unsigned lines)
+{
+	struct nouveau_channel *chan = ctx->m2mf->channel;
+	struct nouveau_grobj *m2mf = ctx->m2mf;
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\t\t\tCOPY_M2MF_BODY [%i, %i] <%i[%u]> lin %u <- <%i[%u]> lin %u\n", size, lines, dstbo->handle, *pdstoff, dstpitch, srcbo->handle, *psrcoff, srcpitch);
+#endif
+
+	BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
+	OUT_RELOCl(chan, srcbo, *psrcoff,
+		   NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
+	OUT_RELOCl(chan, dstbo, *pdstoff,
+		   NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
+	OUT_RING  (chan, srcpitch);
+	OUT_RING  (chan, dstpitch);
+	OUT_RING  (chan, size);
+	OUT_RING  (chan, lines);
+	OUT_RING  (chan, 0x0101);
+	OUT_RING  (chan, 0);
+
+	*psrcoff += srcpitch * lines;
+	*pdstoff += dstpitch * lines;
+}
+
+static void
+nv04_copy_m2mf(struct nv04_2d_context *ctx,
+		struct nouveau_bo* dstbo, int dstoff, unsigned dstpitch,
+		struct nouveau_bo* srcbo, int srcoff, unsigned srcpitch,
+		unsigned size, unsigned h)
+{
+	unsigned max_pitch = 32767;
+	unsigned max_lines = 2047;
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\t\tCOPY_M2MF [%i, %i] <%i[%i]> lin %u <- <%i[%i]> lin %u\n", size, h, dstbo->handle, dstoff, dstpitch, srcbo->handle, srcoff, srcpitch);
+#endif
+
+	if(srcpitch <= max_pitch && dstpitch <= max_pitch)
+	{
+		unsigned full_pages = h / max_lines;
+		unsigned leftover_lines = h - full_pages * max_lines;
+
+		nv04_copy_m2mf_begin(ctx, dstbo, srcbo, full_pages + !!leftover_lines);
+
+		for(unsigned i = 0; i < full_pages; ++i)
+			nv04_copy_m2mf_body(ctx, dstbo, &dstoff, dstpitch, srcbo, &srcoff, srcpitch, size, max_lines);
+
+		if(leftover_lines)
+			nv04_copy_m2mf_body(ctx, dstbo, &dstoff, dstpitch, srcbo, &srcoff, srcpitch, size, leftover_lines);
+	}
+	else
+	{
+		unsigned lines = size / max_pitch;
+		unsigned leftover = size - lines * max_pitch;
+		unsigned full_pages = lines / max_lines;
+		unsigned leftover_lines = lines - full_pages * max_lines;
+		unsigned srcgap = srcpitch - size;
+		unsigned dstgap = dstpitch - size;
+
+		nv04_copy_m2mf_begin(ctx, dstbo, srcbo, h * (full_pages + !!leftover_lines + !!leftover));
+
+		for(unsigned i = 0; i < h; ++i)
+		{
+			for(unsigned j = 0; j < full_pages; ++j)
+				nv04_copy_m2mf_body(ctx, dstbo, &dstoff, max_pitch, srcbo, &srcoff, max_pitch, max_pitch, max_lines);
+
+			if(leftover_lines)
+				nv04_copy_m2mf_body(ctx, dstbo, &dstoff, max_pitch, srcbo, &srcoff, max_pitch, max_pitch, leftover_lines);
+
+			if(leftover)
+				nv04_copy_m2mf_body(ctx, dstbo, &dstoff, leftover, srcbo, &srcoff, leftover, leftover, 1);
+
+			srcoff += srcgap;
+			dstoff += dstgap;
+		}
+	}
+}
+
+void
+nv04_memcpy(struct nv04_2d_context *ctx, struct nouveau_bo* dstbo, int dstoff, struct nouveau_bo* srcbo, int srcoff, unsigned size)
+{
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tMEMCPY [%i] <%i[%i]> <- <%i[%i]>\n", size, dstbo->handle, dstoff, srcbo->handle, srcoff);
+#endif
+
+	nv04_copy_m2mf(ctx, dstbo, dstoff, size, srcbo, srcoff, size, size, 1);
+}
+
+static void
+nv04_region_copy_m2mf(struct nv04_2d_context *ctx, struct nv04_region *dst, struct nv04_region *src, int w, int h)
+{
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tRGN_COPY_M2MF [%i, %i: %i] ", w, h, dst->bpps);
+	for(int i = 0; i < 2; ++i)
+	{
+		nv04_region_print(i ? src : dst);
+		fprintf(stderr, i ? "\n" : " <- ");
+	}
+#endif
+
+	nv04_region_assert(dst, w, h);
+	nv04_region_assert(src, w, h);
+	assert(src->pitch);
+	assert(dst->pitch);
+
+	nv04_copy_m2mf(ctx,
+			dst->bo, dst->offset + dst->y * dst->pitch + (dst->x << dst->bpps), dst->pitch,
+			src->bo, src->offset + src->y * src->pitch + (src->x << src->bpps), src->pitch,
+			w << src->bpps, h);
+}
+
+static inline void
+nv04_region_copy_blit(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src, int w, int h, int format)
+{
+	struct nouveau_channel *chan = ctx->surf2d->channel;
+	struct nouveau_grobj *surf2d = ctx->surf2d;
+	struct nouveau_grobj *blit = ctx->blit;
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tRGN_COPY_BLIT [%i, %i: %i] ", w, h, dst->bpps);
+	for(int i = 0; i < 2; ++i)
+	{
+		nv04_region_print(i ? src : dst);
+		fprintf(stderr, i ? "\n" : " <- ");
+	}
+#endif
+
+	assert(!(src->pitch & 63) && src->pitch);
+	assert(!(dst->pitch & 63) && dst->pitch);
+	nv04_region_assert(dst, w, h);
+	nv04_region_assert(src, w, h);
+
+	MARK_RING (chan, 12, 4);
+	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
+	OUT_RELOCo(chan, src->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+	OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
+	OUT_RING  (chan, format);
+	OUT_RING  (chan, (dst->pitch << 16) | src->pitch);
+	OUT_RELOCl(chan, src->bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
+	OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+	BEGIN_RING(chan, blit, 0x0300, 3);
+	OUT_RING  (chan, (src->y << 16) | src->x);
+	OUT_RING  (chan, (dst->y << 16) | dst->x);
+	OUT_RING  (chan, ( h << 16) |  w);
+}
+
+/* THEOREM: a non-linearizable swizzled destination is always 64 byte aligned, except for 4x2 mipmap levels of swizzled 1bpp surfaces
+ * HYPOTESIS:
+ * 1. The first mipmap level is 64-byte-aligned
+ * PROOF:
+ * 1. Thus, all mipmaps level with a parent which is 64-byte or more in size are.
+ * 2. At 1bpp, the smallest levels with a <= 32-byte parent are either Nx1 or 1xN or size <=8, thus 4x2, 2x2 or 2x4
+ * 3. Nx1, 1xN, 2x4, 2x2 have all subrects linearizable. 4x2 does not.
+ * 4. At 2/4bpp or more, the smallest levels with a 32-byte parent are 1xN, Nx1 or 2x2
+ *
+ * However, nv04_region_align handles that.
+ */
+
+// 0 -> done, 1 -> do with 3D engine or CPU, -1 -> do with CPU
+// dst and src may be modified, and the possibly modified version should be passed to nv04_region_cpu if necessary
+int
+nv04_region_copy_2d(struct nv04_2d_context *ctx, struct nv04_region* dst, struct nv04_region* src,
+		int w, int h, int cs2d_format, int sifm_format, int dst_to_gpu, int src_on_gpu)
+{
+	assert(src->bpps == dst->bpps);
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "RGN_COPY%s [%i, %i: %i] ", (cs2d_format >= 0) ? "_2D" : "_NO2D", w, h, dst->bpps);
+	for(int i = 0; i < 2; ++i)
+	{
+		int gpu = i ? src_on_gpu : dst_to_gpu;
+		nv04_region_print(i ? src : dst);
+		fprintf(stderr, " %s", gpu ? "gpu" : "cpu");
+		fprintf(stderr, i ? "\n" : " <- ");
+	}
+#endif
+
+	// if they are contiguous and either both swizzled or both linear, reshape
+	if(!dst->pitch == !src->pitch
+		&& nv04_region_is_contiguous(dst, w, h)
+		&& nv04_region_is_contiguous(src, w, h))
+	{
+		nv04_region_contiguous_shape(dst, &w, &h, 6);
+		nv04_region_linearize_contiguous(dst, w, h);
+		nv04_region_linearize_contiguous(src, w, h);
+	}
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tOPT ");
+	for(int i = 0; i < 2; ++i)
+	{
+		nv04_region_print(i ? src : dst);
+		fprintf(stderr, i ? "\n" : " <- ");
+	}
+#endif
+
+	/* if the destination is not for GPU _and_ source is on CPU, use CPU */
+	/* if the destination is not for GPU _or_ source is on CPU, use CPU only if we think it's faster than the GPU */
+	/* TODO: benchmark to find out in which cases exactly we should prefer the CPU */
+	 if((!dst_to_gpu && !src_on_gpu)
+		|| (!dst->pitch && dst->d > 1)
+		/* 3D swizzled destination are unwritable by the GPU, and 2D swizzled ones are readable only by the 3D engine */
+	 )
+		 return -1;
+	/* there is no known way to read 2D/3D-swizzled surfaces with the 2D engine
+	 * ask the caller to use the 3D engine
+	 * If a format cannot be sampled from the 3D engine there is no point in making it swizzled, so we must not do so
+	 */
+	 else if(!src->pitch)
+	 {
+#ifdef NV04_REGION_DEBUG
+		fprintf(stderr, "\tCOPY_ENG3D\n");
+#endif
+		 return 1;
+	 }
+	/* Setup transfer to swizzle the texture to vram if needed */
+	else
+	{
+		if (!dst->pitch)
+		{
+			if(cs2d_format < 0 || sifm_format < 0 || !dst_to_gpu)
+			{
+#ifdef NV04_REGION_DEBUG
+				fprintf(stderr, "\tCOPY_ENG3D\n");
+#endif
+				return 1;
+			}
+			else
+			{
+				assert(!nv04_region_align(dst, w, h, 6));
+
+				nv04_region_copy_swizzle(ctx, dst, src, w, h, cs2d_format, sifm_format);
+				return 0;
+			}
+		}
+		else
+		{
+			/* NV_CONTEXT_SURFACES_2D has buffer alignment restrictions, fallback
+			 * to NV_MEMORY_TO_MEMORY_FORMAT in this case.
+			 * TODO: is this also true for the source? possibly not
+			 */
+
+			if ((cs2d_format < 0)
+				|| !dst_to_gpu
+				|| nv04_region_align(src, w, h, 6)
+				|| nv04_region_align(dst, w, h, 6)
+				)
+				nv04_region_copy_m2mf(ctx, dst, src, w, h);
+			else
+				nv04_region_copy_blit(ctx, dst, src, w, h, cs2d_format);
+
+			return 0;
+		}
+	}
+}
+
+static inline void
+nv04_region_fill_gdirect(struct nv04_2d_context *ctx, struct nv04_region* dst, int w, int h, unsigned value)
+{
+	struct nouveau_channel *chan = ctx->surf2d->channel;
+	struct nouveau_grobj *surf2d = ctx->surf2d;
+	struct nouveau_grobj *rect = ctx->rect;
+	int cs2d_format, gdirect_format;
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "\tFILL_GDIRECT\n");
+#endif
+
+	assert(!(dst->pitch & 63) && dst->pitch);
+	nv04_region_assert(dst, w, h);
+
+	if(dst->bpps == 0)
+	{
+		gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
+		cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
+	}
+	else if(dst->bpps == 1)
+	{
+		gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
+		cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y16;
+	}
+	else if(dst->bpps == 2)
+	{
+		gdirect_format = NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
+		cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
+	}
+	else
+		assert(0);
+
+	MARK_RING (chan, 15, 4);
+	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
+	OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+	OUT_RELOCo(chan, dst->bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
+	OUT_RING  (chan, cs2d_format);
+	OUT_RING  (chan, (dst->pitch << 16) | dst->pitch);
+	OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+	OUT_RELOCl(chan, dst->bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
+	BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
+	OUT_RING  (chan, gdirect_format);
+	BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
+	OUT_RING  (chan, value);
+	BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
+	OUT_RING  (chan, (dst->x << 16) | dst->y);
+	OUT_RING  (chan, ( w << 16) |  h);
+}
+
+int
+nv04_region_fill_2d(struct nv04_2d_context *ctx, struct nv04_region *dst,
+		  int w, int h, unsigned value)
+{
+	if(!w || !h)
+		return 0;
+
+#ifdef NV04_REGION_DEBUG
+	fprintf(stderr, "FILL [%i, %i: %i] ", w, h, dst->bpps);
+	nv04_region_print(dst);
+	fprintf(stderr, " <- 0x%x\n", value);
+#endif
+
+	if(nv04_region_is_contiguous(dst, w, h))
+	{
+		nv04_region_contiguous_shape(dst, &w, &h, 6);
+		nv04_region_linearize_contiguous(dst, w, h);
+	}
+
+	// TODO: maybe do intermediate copies for some cases instead of using the 3D engine/CPU
+	/* GdiRect doesn't work together with swzsurf, so the 3D engine, or an intermediate copy, is the only option here */
+	if(!dst->pitch)
+	{
+#ifdef NV04_REGION_DEBUG
+		fprintf(stderr, "\tFILL_ENG3D\n");
+#endif
+		return 1;
+	}
+	else if(!nv04_region_align(dst, w, h, 6))
+	{
+		nv04_region_fill_gdirect(ctx, dst, w, h, value);
+		return 0;
+	}
+	else
+		return -1;
+}
+
+
+void
+nv04_2d_context_takedown(struct nv04_2d_context *ctx)
+{
+	nouveau_notifier_free(&ctx->ntfy);
+	nouveau_grobj_free(&ctx->m2mf);
+	nouveau_grobj_free(&ctx->surf2d);
+	nouveau_grobj_free(&ctx->swzsurf);
+	nouveau_grobj_free(&ctx->rect);
+	nouveau_grobj_free(&ctx->blit);
+	nouveau_grobj_free(&ctx->sifm);
+
+	free(ctx);
+}
+
+struct nv04_2d_context *
+nv04_2d_context_init(struct nouveau_channel* chan)
+{
+	struct nv04_2d_context *ctx = calloc(1, sizeof(struct nv04_2d_context));
+	unsigned handle = 0x88000000, class;
+	int ret;
+
+	if (!ctx)
+		return NULL;
+
+	ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
+	if (ret) {
+		nv04_2d_context_takedown(ctx);
+		return NULL;
+	}
+
+	ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
+	if (ret) {
+		nv04_2d_context_takedown(ctx);
+		return NULL;
+	}
+
+	BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
+	OUT_RING  (chan, ctx->ntfy->handle);
+
+	if (chan->device->chipset < 0x10)
+		class = NV04_CONTEXT_SURFACES_2D;
+	else
+		class = NV10_CONTEXT_SURFACES_2D;
+
+	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
+	if (ret) {
+		nv04_2d_context_takedown(ctx);
+		return NULL;
+	}
+
+	BEGIN_RING(chan, ctx->surf2d,
+			 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
+	OUT_RING  (chan, chan->vram->handle);
+	OUT_RING  (chan, chan->vram->handle);
+
+	if (chan->device->chipset < 0x10)
+		class = NV04_IMAGE_BLIT;
+	else
+		class = NV12_IMAGE_BLIT;
+
+	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
+	if (ret) {
+		nv04_2d_context_takedown(ctx);
+		return NULL;
+	}
+
+	BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1);
+	OUT_RING  (chan, ctx->ntfy->handle);
+	BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
+	OUT_RING  (chan, ctx->surf2d->handle);
+	BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1);
+	OUT_RING  (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY);
+
+	ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
+				  &ctx->rect);
+	if (ret) {
+		nv04_2d_context_takedown(ctx);
+		return NULL;
+	}
+
+	BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
+	OUT_RING  (chan, ctx->ntfy->handle);
+	BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
+	OUT_RING  (chan, ctx->surf2d->handle);
+	BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
+	OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
+	BEGIN_RING(chan, ctx->rect,
+			 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
+	OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
+
+	switch (chan->device->chipset & 0xf0) {
+	case 0x00:
+	case 0x10:
+		class = NV04_SWIZZLED_SURFACE;
+		break;
+	case 0x20:
+		class = NV20_SWIZZLED_SURFACE;
+		break;
+	case 0x30:
+		class = NV30_SWIZZLED_SURFACE;
+		break;
+	case 0x40:
+	case 0x60:
+		class = NV40_SWIZZLED_SURFACE;
+		break;
+	default:
+		/* Famous last words: this really can't happen.. */
+		assert(0);
+		break;
+	}
+
+	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
+	if (ret) {
+		nv04_2d_context_takedown(ctx);
+		return NULL;
+	}
+
+	/* all the Gallium MARK_RING calculations assume no autobinding, so do that now */
+	if(ctx->swzsurf->bound == NOUVEAU_GROBJ_UNBOUND)
+		nouveau_grobj_autobind(ctx->swzsurf);
+
+	switch (chan->device->chipset & 0xf0) {
+	case 0x10:
+	case 0x20:
+		class = NV10_SCALED_IMAGE_FROM_MEMORY;
+		break;
+	case 0x30:
+		class = NV30_SCALED_IMAGE_FROM_MEMORY;
+		break;
+	case 0x40:
+	case 0x60:
+		class = NV40_SCALED_IMAGE_FROM_MEMORY;
+		break;
+	default:
+		class = NV04_SCALED_IMAGE_FROM_MEMORY;
+		break;
+	}
+
+	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
+	if (ret) {
+		nv04_2d_context_takedown(ctx);
+		return NULL;
+	}
+
+	/* all the Gallium MARK_RING calculations assume no autobinding, so do that now */
+	if(ctx->sifm->bound == NOUVEAU_GROBJ_UNBOUND)
+		nouveau_grobj_autobind(ctx->sifm);
+
+	return ctx;
+}
diff --git a/src/gallium/drivers/nvfx/nv04_2d.h b/src/gallium/drivers/nvfx/nv04_2d.h
new file mode 100644
index 0000000000..e638b8c874
--- /dev/null
+++ b/src/gallium/drivers/nvfx/nv04_2d.h
@@ -0,0 +1,87 @@
+/**************************************************************************
+ *
+ * Copyright 2009 Ben Skeggs
+ * Copyright 2009 Younes Manton
+ * Copyright 2010 Luca Barbieri
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ **************************************************************************/
+
+/* this code has no Mesa or Gallium dependency and can be reused in the classic Mesa driver or DDX */
+
+#ifndef __NV04_2D_H__
+#define __NV04_2D_H__
+
+struct nv04_2d_context;
+struct nouveau_channel;
+struct nouveau_bo;
+
+// NOTE: all functions taking this as a parameter will CLOBBER it (except for ->bo)
+struct nv04_region {
+	struct nouveau_bo* bo;
+	int offset;
+	unsigned pitch; // 0 -> swizzled
+	unsigned bpps; // bpp shift (0, 1, 2; 3, 4 for fp/compressed)
+	unsigned x, y, z;
+	unsigned w, h, d;
+};
+
+void
+nv04_memcpy(struct nv04_2d_context *ctx,
+		struct nouveau_bo* dstbo, int dstoff,
+		struct nouveau_bo* srcbo, int srcoff,
+		unsigned size);
+
+unsigned
+nv04_region_begin(struct nv04_region* rgn, unsigned w, unsigned h);
+
+unsigned
+nv04_region_end(struct nv04_region* rgn, unsigned w, unsigned h);
+
+void
+nv04_2d_context_takedown(struct nv04_2d_context *pctx);
+
+struct nv04_2d_context *
+nv04_2d_context_init(struct nouveau_channel* chan);
+
+void
+nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, int h);
+
+void
+nv04_region_fill_cpu(struct nv04_region* dst, int w, int h, unsigned value);
+
+int
+nv04_region_copy_2d(struct nv04_2d_context *ctx,
+		struct nv04_region* dst, struct nv04_region* src,
+		int w, int h,
+		int cs2d_format, int sifm_format,
+		int dst_to_gpu, int src_on_gpu);
+
+int
+nv04_region_fill_2d(struct nv04_2d_context *ctx,
+		struct nv04_region *dst,
+                int w, int h,
+                unsigned value);
+
+#endif
diff --git a/src/gallium/drivers/nvfx/nv04_2d_loops.h b/src/gallium/drivers/nvfx/nv04_2d_loops.h
new file mode 100644
index 0000000000..3a6787c071
--- /dev/null
+++ b/src/gallium/drivers/nvfx/nv04_2d_loops.h
@@ -0,0 +1,70 @@
+#ifndef T
+{
+	if(dst->bpps == 0)
+#define T uint8_t
+#include "nv04_2d_loops.h"
+#undef T
+	else if(dst->bpps == 1)
+#define T uint16_t
+#include "nv04_2d_loops.h"
+#undef T
+	else if(dst->bpps == 2)
+#define T uint32_t
+#include "nv04_2d_loops.h"
+#undef T
+	else
+		assert(0);
+}
+#else
+#ifdef SWIZZLED_COPY_LOOPS
+{
+	if(!dst->pitch)
+	{
+		if(!src->pitch)
+		{
+			LOOP_Y
+			{
+				T* pdst = (T*)mdst + dswy[iy];
+				T* psrc = (T*)msrc + sswy[iy];
+				LOOP_X
+				{
+					assert((char*)&psrc[sswx[ix] + 1] <= ((char*)src->bo->map + src->bo->size));
+					assert((char*)&pdst[dswx[ix] + 1] <= ((char*)dst->bo->map + dst->bo->size));
+					pdst[dswx[ix]] = psrc[sswx[ix]];
+				}
+			}
+		}
+		else
+		{
+			T* psrc = (T*)(msrc + ((dir > 0) ? src->y : (src->y + h - 1)) * src->pitch) + src->x;
+			LOOP_Y
+			{
+				T* pdst = (T*)mdst + dswy[iy];
+				LOOP_X
+				{
+					assert((char*)&psrc[ix + 1] <= ((char*)src->bo->map + src->bo->size));
+					assert((char*)&pdst[dswx[ix] + 1] <= ((char*)dst->bo->map + dst->bo->size));
+					pdst[dswx[ix]] = psrc[ix];
+				}
+				psrc = (T*)((char*)psrc + dir * src->pitch);
+			}
+		}
+	}
+	else
+	{
+		T* pdst = (T*)(mdst + ((dir > 0) ? dst->y : (dst->y + h - 1)) * dst->pitch) + dst->x;
+		LOOP_Y
+		{
+			T* psrc = (T*)msrc + sswy[iy];
+			LOOP_X
+			{
+				assert((char*)&psrc[sswx[ix] + 1] <= ((char*)src->bo->map + src->bo->size));
+				assert((char*)&pdst[ix + 1] <= ((char*)dst->bo->map + dst->bo->size));
+				pdst[ix] = psrc[sswx[ix]];
+			}
+			pdst = (T*)((char*)pdst + dir * dst->pitch);
+		}
+	}
+}
+#endif
+#endif
-- 
cgit v1.2.3


From 9ed0686e8e6157ce38c9fa284cd7399289a2e698 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 3 Aug 2010 06:24:22 +0200
Subject: nvfx: new 2D: use new 2D engine in Gallium

This patch implements nv04_surface_copy/fill using the new 2D engine module.
It supports falling back to the 3D engine using the u_blitter module, which will be
added in a later patch.

Also adds support for using the 3D engine, reusing the u_blitter module
created for r300.
This is used for unswizzling and copies between swizzled surfaces.
---
 src/gallium/drivers/nvfx/Makefile          |   1 -
 src/gallium/drivers/nvfx/nv04_surface_2d.c | 533 -----------------------------
 src/gallium/drivers/nvfx/nv04_surface_2d.h |  41 ---
 src/gallium/drivers/nvfx/nvfx_context.h    |   2 +
 src/gallium/drivers/nvfx/nvfx_miptree.c    |  16 +-
 src/gallium/drivers/nvfx/nvfx_resource.h   |   5 +
 src/gallium/drivers/nvfx/nvfx_screen.c     |   6 +-
 src/gallium/drivers/nvfx/nvfx_screen.h     |  10 +-
 src/gallium/drivers/nvfx/nvfx_state_fb.c   |   6 +-
 src/gallium/drivers/nvfx/nvfx_surface.c    | 346 +++++++++++++++++--
 10 files changed, 340 insertions(+), 626 deletions(-)
 delete mode 100644 src/gallium/drivers/nvfx/nv04_surface_2d.c
 delete mode 100644 src/gallium/drivers/nvfx/nv04_surface_2d.h

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/Makefile b/src/gallium/drivers/nvfx/Makefile
index 6536343e44..2834f8984c 100644
--- a/src/gallium/drivers/nvfx/Makefile
+++ b/src/gallium/drivers/nvfx/Makefile
@@ -4,7 +4,6 @@ include $(TOP)/configs/current
 LIBNAME = nvfx
 
 C_SOURCES = \
-	nv04_surface_2d.c \
 	nv04_2d.c \
 	nvfx_buffer.c \
 	nvfx_context.c \
diff --git a/src/gallium/drivers/nvfx/nv04_surface_2d.c b/src/gallium/drivers/nvfx/nv04_surface_2d.c
deleted file mode 100644
index cd0f4ce4c9..0000000000
--- a/src/gallium/drivers/nvfx/nv04_surface_2d.c
+++ /dev/null
@@ -1,533 +0,0 @@
-#include "pipe/p_context.h"
-#include "pipe/p_format.h"
-#include "util/u_format.h"
-#include "util/u_math.h"
-#include "util/u_memory.h"
-
-#include "nouveau/nouveau_winsys.h"
-#include "nouveau/nouveau_util.h"
-#include "nouveau/nouveau_screen.h"
-#include "nv04_surface_2d.h"
-#include "nvfx_resource.h"
-
-static INLINE int
-nv04_surface_format(enum pipe_format format)
-{
-	switch (format) {
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-		return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
-	case PIPE_FORMAT_R16_SNORM:
-	case PIPE_FORMAT_B5G6R5_UNORM:
-	case PIPE_FORMAT_Z16_UNORM:
-	case PIPE_FORMAT_L8A8_UNORM:
-		return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-		return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-	case PIPE_FORMAT_X8Z24_UNORM:
-		return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
-	default:
-		return -1;
-	}
-}
-
-static INLINE int
-nv04_rect_format(enum pipe_format format)
-{
-	switch (format) {
-	case PIPE_FORMAT_A8_UNORM:
-		return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
-	case PIPE_FORMAT_B5G6R5_UNORM:
-	case PIPE_FORMAT_L8A8_UNORM:
-	case PIPE_FORMAT_Z16_UNORM:
-		return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-	case PIPE_FORMAT_X8Z24_UNORM:
-		return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
-	default:
-		return -1;
-	}
-}
-
-static INLINE int
-nv04_scaled_image_format(enum pipe_format format)
-{
-	switch (format) {
-	case PIPE_FORMAT_A8_UNORM:
-	case PIPE_FORMAT_L8_UNORM:
-	case PIPE_FORMAT_I8_UNORM:
-		return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
-	case PIPE_FORMAT_B5G5R5A1_UNORM:
-		return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-		return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-		return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
-	case PIPE_FORMAT_B5G6R5_UNORM:
-	case PIPE_FORMAT_R16_SNORM:
-	case PIPE_FORMAT_L8A8_UNORM:
-		return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
-	default:
-		return -1;
-	}
-}
-
-static INLINE unsigned
-nv04_swizzle_bits_square(unsigned x, unsigned y)
-{
-	unsigned u = (x & 0x001) << 0 |
-	             (x & 0x002) << 1 |
-	             (x & 0x004) << 2 |
-	             (x & 0x008) << 3 |
-	             (x & 0x010) << 4 |
-	             (x & 0x020) << 5 |
-	             (x & 0x040) << 6 |
-	             (x & 0x080) << 7 |
-	             (x & 0x100) << 8 |
-	             (x & 0x200) << 9 |
-	             (x & 0x400) << 10 |
-	             (x & 0x800) << 11;
-
-	unsigned v = (y & 0x001) << 1 |
-	             (y & 0x002) << 2 |
-	             (y & 0x004) << 3 |
-	             (y & 0x008) << 4 |
-	             (y & 0x010) << 5 |
-	             (y & 0x020) << 6 |
-	             (y & 0x040) << 7 |
-	             (y & 0x080) << 8 |
-	             (y & 0x100) << 9 |
-	             (y & 0x200) << 10 |
-	             (y & 0x400) << 11 |
-	             (y & 0x800) << 12;
-	return v | u;
-}
-
-/* rectangular swizzled textures are linear concatenations of swizzled square tiles */
-static INLINE unsigned
-nv04_swizzle_bits(unsigned x, unsigned y, unsigned w, unsigned h)
-{
-	unsigned s = MIN2(w, h);
-	unsigned m = s - 1;
-	return (((x | y) & ~m) * s) | nv04_swizzle_bits_square(x & m, y & m);
-}
-
-static int
-nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
-			  struct pipe_surface *dst, int dx, int dy,
-			  struct pipe_surface *src, int sx, int sy,
-			  int w, int h)
-{
-	struct nouveau_channel *chan = ctx->swzsurf->channel;
-	struct nouveau_grobj *swzsurf = ctx->swzsurf;
-	struct nouveau_grobj *sifm = ctx->sifm;
-	struct nouveau_bo *src_bo = ctx->buf(src);
-	struct nouveau_bo *dst_bo = ctx->buf(dst);
-	const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
-        /* Max width & height may not be the same on all HW, but must be POT */
-	const unsigned max_w = 1024;
-	const unsigned max_h = 1024;
-	unsigned sub_w = w > max_w ? max_w : w;
-	unsigned sub_h = h > max_h ? max_h : h;
-	unsigned x;
-	unsigned y;
-
-        /* Swizzled surfaces must be POT  */
-	assert(util_is_pot(dst->width) && util_is_pot(dst->height));
-
-        /* If area is too large to copy in one shot we must copy it in POT chunks to meet alignment requirements */
-	assert(sub_w == w || util_is_pot(sub_w));
-	assert(sub_h == h || util_is_pot(sub_h));
-
-	MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
-			 ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
-
-	BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
-	OUT_RELOCo(chan, dst_bo,
-	                 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-
-	BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
-	OUT_RING  (chan, nv04_surface_format(dst->format) |
-	                 log2i(dst->width) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
-	                 log2i(dst->height) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
-
-	BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
-	OUT_RELOCo(chan, src_bo,
-	                 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
-	BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
-	OUT_RING  (chan, swzsurf->handle);
-
-	for (y = 0; y < h; y += sub_h) {
-	  sub_h = MIN2(sub_h, h - y);
-
-	  for (x = 0; x < w; x += sub_w) {
-	    sub_w = MIN2(sub_w, w - x);
-
-	    assert(!(dst->offset & 63));
-
-	    BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
-	    OUT_RELOCl(chan, dst_bo, dst->offset,
-                             NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-
-	    BEGIN_RING(chan, sifm, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
-	    OUT_RING  (chan, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
-	    OUT_RING  (chan, nv04_scaled_image_format(src->format));
-	    OUT_RING  (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
-	    OUT_RING  (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT));
-	    OUT_RING  (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | sub_w);
-	    OUT_RING  (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT));
-	    OUT_RING  (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | sub_w);
-	    OUT_RING  (chan, 1 << 20);
-	    OUT_RING  (chan, 1 << 20);
-
-	    BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
-	    OUT_RING  (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | sub_w);
-	    OUT_RING  (chan, src_pitch |
-			     NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
-			     NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
-	    OUT_RELOCl(chan, src_bo, src->offset + (sy+y) * src_pitch + (sx+x) * util_format_get_blocksize(src->texture->format),
-                             NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
-	    OUT_RING  (chan, 0);
-	  }
-	}
-
-	return 0;
-}
-
-static int
-nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
-		       struct pipe_surface *dst, int dx, int dy,
-		       struct pipe_surface *src, int sx, int sy, int w, int h)
-{
-	struct nouveau_channel *chan = ctx->m2mf->channel;
-	struct nouveau_grobj *m2mf = ctx->m2mf;
-	struct nouveau_bo *src_bo = ctx->buf(src);
-	struct nouveau_bo *dst_bo = ctx->buf(dst);
-	unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
-	unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
-	unsigned dst_offset = dst->offset + dy * dst_pitch +
-	                      dx * util_format_get_blocksize(dst->texture->format);
-	unsigned src_offset = src->offset + sy * src_pitch +
-	                      sx * util_format_get_blocksize(src->texture->format);
-
-	MARK_RING (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2);
-	BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
-	OUT_RELOCo(chan, src_bo,
-		   NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
-	OUT_RELOCo(chan, dst_bo,
-		   NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-
-	while (h) {
-		int count = (h > 2047) ? 2047 : h;
-
-		BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
-		OUT_RELOCl(chan, src_bo, src_offset,
-			   NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
-		OUT_RELOCl(chan, dst_bo, dst_offset,
-			   NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
-		OUT_RING  (chan, src_pitch);
-		OUT_RING  (chan, dst_pitch);
-		OUT_RING  (chan, w * util_format_get_blocksize(src->texture->format));
-		OUT_RING  (chan, count);
-		OUT_RING  (chan, 0x0101);
-		OUT_RING  (chan, 0);
-
-		h -= count;
-		src_offset += src_pitch * count;
-		dst_offset += dst_pitch * count;
-	}
-
-	return 0;
-}
-
-static int
-nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
-		       int dx, int dy, struct pipe_surface *src, int sx, int sy,
-		       int w, int h)
-{
-	struct nouveau_channel *chan = ctx->surf2d->channel;
-	struct nouveau_grobj *surf2d = ctx->surf2d;
-	struct nouveau_grobj *blit = ctx->blit;
-	struct nouveau_bo *src_bo = ctx->buf(src);
-	struct nouveau_bo *dst_bo = ctx->buf(dst);
-	unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
-	unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
-	int format;
-
-	format = nv04_surface_format(dst->format);
-	if (format < 0)
-		return 1;
-
-	MARK_RING (chan, 12, 4);
-	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
-	OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
-	OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
-	OUT_RING  (chan, format);
-	OUT_RING  (chan, (dst_pitch << 16) | src_pitch);
-	OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
-	OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-
-	BEGIN_RING(chan, blit, 0x0300, 3);
-	OUT_RING  (chan, (sy << 16) | sx);
-	OUT_RING  (chan, (dy << 16) | dx);
-	OUT_RING  (chan, ( h << 16) |  w);
-
-	return 0;
-}
-
-static void
-nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
-		  int dx, int dy, struct pipe_surface *src, int sx, int sy,
-		  int w, int h)
-{
-	int src_linear = src->texture->flags & NVFX_RESOURCE_FLAG_LINEAR;
-	int dst_linear = dst->texture->flags & NVFX_RESOURCE_FLAG_LINEAR;
-
-	assert(src->format == dst->format);
-
-	/* Setup transfer to swizzle the texture to vram if needed */
-        if (src_linear && !dst_linear && w > 1 && h > 1) {
-           nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
-           return;
-        }
-
-        /* Use M2MF instead of the blitter since it always works
-         * Any possible performance drop is likely to be not very significant
-         * and dwarfed anyway by the current buffer management problems
-         */
-        nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
-}
-
-static void
-nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
-		  int dx, int dy, int w, int h, unsigned value)
-{
-	struct nouveau_channel *chan = ctx->surf2d->channel;
-	struct nouveau_grobj *surf2d = ctx->surf2d;
-	struct nouveau_grobj *rect = ctx->rect;
-	struct nouveau_bo *dst_bo = ctx->buf(dst);
-	unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
-	int cs2d_format, gdirect_format;
-
-	cs2d_format = nv04_surface_format(dst->format);
-	assert(cs2d_format >= 0);
-
-	gdirect_format = nv04_rect_format(dst->format);
-	assert(gdirect_format >= 0);
-
-	MARK_RING (chan, 16, 4);
-	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
-	OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-	OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
-	OUT_RING  (chan, cs2d_format);
-	OUT_RING  (chan, (dst_pitch << 16) | dst_pitch);
-	OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-	OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
-
-	BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
-	OUT_RING  (chan, gdirect_format);
-	BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
-	OUT_RING  (chan, value);
-	BEGIN_RING(chan, rect,
-		   NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
-	OUT_RING  (chan, (dx << 16) | dy);
-	OUT_RING  (chan, ( w << 16) |  h);
-}
-
-void
-nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
-{
-	struct nv04_surface_2d *ctx;
-
-	if (!pctx || !*pctx)
-		return;
-	ctx = *pctx;
-	*pctx = NULL;
-
-	nouveau_notifier_free(&ctx->ntfy);
-	nouveau_grobj_free(&ctx->m2mf);
-	nouveau_grobj_free(&ctx->surf2d);
-	nouveau_grobj_free(&ctx->swzsurf);
-	nouveau_grobj_free(&ctx->rect);
-	nouveau_grobj_free(&ctx->blit);
-	nouveau_grobj_free(&ctx->sifm);
-
-	FREE(ctx);
-}
-
-struct nv04_surface_2d *
-nv04_surface_2d_init(struct nouveau_screen *screen)
-{
-	struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
-	struct nouveau_channel *chan = screen->channel;
-	unsigned handle = 0x88000000, class;
-	int ret;
-
-	if (!ctx)
-		return NULL;
-
-	ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
-	if (ret) {
-		nv04_surface_2d_takedown(&ctx);
-		return NULL;
-	}
-
-	ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
-	if (ret) {
-		nv04_surface_2d_takedown(&ctx);
-		return NULL;
-	}
-
-	BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
-	OUT_RING  (chan, ctx->ntfy->handle);
-
-	if (chan->device->chipset < 0x10)
-		class = NV04_CONTEXT_SURFACES_2D;
-	else
-		class = NV10_CONTEXT_SURFACES_2D;
-
-	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
-	if (ret) {
-		nv04_surface_2d_takedown(&ctx);
-		return NULL;
-	}
-
-	BEGIN_RING(chan, ctx->surf2d,
-			 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
-	OUT_RING  (chan, chan->vram->handle);
-	OUT_RING  (chan, chan->vram->handle);
-
-	if (chan->device->chipset < 0x10)
-		class = NV04_IMAGE_BLIT;
-	else
-		class = NV12_IMAGE_BLIT;
-
-	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
-	if (ret) {
-		nv04_surface_2d_takedown(&ctx);
-		return NULL;
-	}
-
-	BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1);
-	OUT_RING  (chan, ctx->ntfy->handle);
-	BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
-	OUT_RING  (chan, ctx->surf2d->handle);
-	BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1);
-	OUT_RING  (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY);
-
-	ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
-				  &ctx->rect);
-	if (ret) {
-		nv04_surface_2d_takedown(&ctx);
-		return NULL;
-	}
-
-	BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
-	OUT_RING  (chan, ctx->ntfy->handle);
-	BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
-	OUT_RING  (chan, ctx->surf2d->handle);
-	BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
-	OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
-	BEGIN_RING(chan, ctx->rect,
-			 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
-	OUT_RING  (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
-
-	switch (chan->device->chipset & 0xf0) {
-	case 0x00:
-	case 0x10:
-		class = NV04_SWIZZLED_SURFACE;
-		break;
-	case 0x20:
-		class = NV20_SWIZZLED_SURFACE;
-		break;
-	case 0x30:
-		class = NV30_SWIZZLED_SURFACE;
-		break;
-	case 0x40:
-	case 0x60:
-		class = NV40_SWIZZLED_SURFACE;
-		break;
-	default:
-		/* Famous last words: this really can't happen.. */
-		assert(0);
-		break;
-	}
-
-	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
-	if (ret) {
-		nv04_surface_2d_takedown(&ctx);
-		return NULL;
-	}
-
-	switch (chan->device->chipset & 0xf0) {
-	case 0x10:
-	case 0x20:
-		class = NV10_SCALED_IMAGE_FROM_MEMORY;
-		break;
-	case 0x30:
-		class = NV30_SCALED_IMAGE_FROM_MEMORY;
-		break;
-	case 0x40:
-	case 0x60:
-		class = NV40_SCALED_IMAGE_FROM_MEMORY;
-		break;
-	default:
-		class = NV04_SCALED_IMAGE_FROM_MEMORY;
-		break;
-	}
-
-	ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
-	if (ret) {
-		nv04_surface_2d_takedown(&ctx);
-		return NULL;
-	}
-
-	ctx->copy = nv04_surface_copy;
-	ctx->fill = nv04_surface_fill;
-	return ctx;
-}
-
-struct nv04_surface*
-nv04_surface_wrap_for_render(struct pipe_screen *pscreen,
-			     struct nv04_surface_2d* eng2d, struct nv04_surface* ns)
-{
-	struct pipe_resource templ;
-	struct pipe_resource* temp_tex;
-	struct nv04_surface* temp_ns;
-	int temp_flags;
-
-	temp_flags = ns->base.usage;
-
-	ns->base.usage = 0;
-
-	memset(&templ, 0, sizeof(templ));
-	templ.format = ns->base.texture->format;
-	templ.target = PIPE_TEXTURE_2D;
-	templ.width0 = ns->base.width;
-	templ.height0 = ns->base.height;
-	templ.depth0 = 1;
-	templ.last_level = 0;
-
-	// TODO: this is probably wrong and we should specifically handle multisampling somehow once it is implemented
-	templ.nr_samples = ns->base.texture->nr_samples;
-
-	templ.bind = ns->base.texture->bind | PIPE_BIND_RENDER_TARGET;
-
-	temp_tex = pscreen->resource_create(pscreen, &templ);
-	temp_ns = (struct nv04_surface*)pscreen->get_tex_surface(pscreen, temp_tex, 0, 0, 0, temp_flags);
-	temp_ns->backing = ns;
-
-	if(1) /* hmm */
-		eng2d->copy(eng2d, &temp_ns->backing->base,
-			    0, 0, &ns->base,
-			    0, 0, ns->base.width, ns->base.height);
-
-	return temp_ns;
-}
diff --git a/src/gallium/drivers/nvfx/nv04_surface_2d.h b/src/gallium/drivers/nvfx/nv04_surface_2d.h
deleted file mode 100644
index b9020dbe96..0000000000
--- a/src/gallium/drivers/nvfx/nv04_surface_2d.h
+++ /dev/null
@@ -1,41 +0,0 @@
-#ifndef __NV04_SURFACE_2D_H__
-#define __NV04_SURFACE_2D_H__
-
-#include "pipe/p_state.h"
-
-struct nouveau_screen;
-
-struct nv04_surface {
-	struct pipe_surface base;
-	unsigned pitch;
-	struct nv04_surface* backing;
-};
-
-struct nv04_surface_2d {
-	struct nouveau_notifier *ntfy;
-	struct nouveau_grobj *surf2d;
-	struct nouveau_grobj *swzsurf;
-	struct nouveau_grobj *m2mf;
-	struct nouveau_grobj *rect;
-	struct nouveau_grobj *blit;
-	struct nouveau_grobj *sifm;
-
-	struct nouveau_bo *(*buf)(struct pipe_surface *);
-
-	void (*copy)(struct nv04_surface_2d *, struct pipe_surface *dst,
-		     int dx, int dy, struct pipe_surface *src, int sx, int sy,
-		     int w, int h);
-	void (*fill)(struct nv04_surface_2d *, struct pipe_surface *dst,
-		     int dx, int dy, int w, int h, unsigned value);
-};
-
-struct nv04_surface_2d *
-nv04_surface_2d_init(struct nouveau_screen *screen);
-
-void
-nv04_surface_2d_takedown(struct nv04_surface_2d **);
-
-struct nv04_surface*
-nv04_surface_wrap_for_render(struct pipe_screen *pscreen, struct nv04_surface_2d* eng2d, struct nv04_surface* ns);
-
-#endif
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 89f94c10bd..278be94d52 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -13,6 +13,7 @@
 #include "util/u_inlines.h"
 
 #include "draw/draw_vertex.h"
+#include "util/u_blitter.h"
 
 #include "nouveau/nouveau_winsys.h"
 #include "nouveau/nouveau_gldefs.h"
@@ -88,6 +89,7 @@ struct nvfx_context {
 	unsigned is_nv4x; /* either 0 or ~0 */
 
 	struct draw_context *draw;
+	struct blitter_context* blitter;
 
 	/* HW state derived from pipe states */
 	struct nvfx_state state;
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 27bfa24b28..b8ec726624 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -8,8 +8,7 @@
 #include "state_tracker/drm_driver.h"
 #include "nouveau/nouveau_winsys.h"
 #include "nouveau/nouveau_screen.h"
-#include "nv04_surface_2d.h"
-#include "nvfx_context.h"
+#include "nvfx_screen.h"
 #include "nvfx_resource.h"
 #include "nvfx_transfer.h"
 
@@ -231,9 +230,9 @@ nvfx_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
 			 unsigned face, unsigned level, unsigned zslice,
 			 unsigned flags)
 {
-	struct nv04_surface *ns;
+	struct nvfx_surface *ns;
 
-	ns = CALLOC_STRUCT(nv04_surface);
+	ns = CALLOC_STRUCT(nvfx_surface);
 	if (!ns)
 		return NULL;
 	pipe_resource_reference(&ns->base.texture, pt);
@@ -254,15 +253,6 @@ nvfx_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
 void
 nvfx_miptree_surface_del(struct pipe_surface *ps)
 {
-	struct nv04_surface* ns = (struct nv04_surface*)ps;
-	if(ns->backing)
-	{
-		struct nvfx_screen* screen = (struct nvfx_screen*)ps->texture->screen;
-		if(1 /*ns->backing->base.usage & PIPE_BIND_BLIT_DESTINATION*/)
-			screen->eng2d->copy(screen->eng2d, &ns->backing->base, 0, 0, ps, 0, 0, ns->base.width, ns->base.height);
-		nvfx_miptree_surface_del(&ns->backing->base);
-	}
-
 	pipe_resource_reference(&ps->texture, NULL);
 	FREE(ps);
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
index 0e24ec2f1f..42d04ebb37 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ b/src/gallium/drivers/nvfx/nvfx_resource.h
@@ -46,6 +46,11 @@ struct nvfx_miptree {
         unsigned level_offset[NVFX_MAX_TEXTURE_LEVELS];
 };
 
+struct nvfx_surface {
+	struct pipe_surface base;
+	unsigned pitch;
+};
+
 static INLINE 
 struct nvfx_resource *nvfx_resource(struct pipe_resource *resource)
 {
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index d354bd166a..a1b7c218f1 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -233,7 +233,6 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 	return FALSE;
 }
 
-
 static void
 nvfx_screen_destroy(struct pipe_screen *pscreen)
 {
@@ -245,7 +244,7 @@ nvfx_screen_destroy(struct pipe_screen *pscreen)
 	nouveau_notifier_free(&screen->query);
 	nouveau_notifier_free(&screen->sync);
 	nouveau_grobj_free(&screen->eng3d);
-	nv04_surface_2d_takedown(&screen->eng2d);
+	nvfx_screen_surface_takedown(pscreen);
 
 	nouveau_screen_fini(&screen->base);
 
@@ -451,8 +450,7 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	}
 
 	/* 2D engine setup */
-	screen->eng2d = nv04_surface_2d_init(&screen->base);
-	screen->eng2d->buf = nvfx_surface_buffer;
+	nvfx_screen_surface_init(pscreen);
 
 	/* Notifier for sync purposes */
 	ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.h b/src/gallium/drivers/nvfx/nvfx_screen.h
index 5e1c3945ae..4dedbe9cb4 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.h
+++ b/src/gallium/drivers/nvfx/nvfx_screen.h
@@ -3,9 +3,9 @@
 
 #include "util/u_double_list.h"
 #include "nouveau/nouveau_screen.h"
-#include "nv04_surface_2d.h"
+#include "nvfx_context.h"
 
-struct nvfx_context;
+struct nv04_2d_context;
 
 struct nvfx_screen {
 	struct nouveau_screen base;
@@ -20,7 +20,6 @@ struct nvfx_screen {
 	unsigned index_buffer_reloc_flags;
 
 	/* HW graphics objects */
-	struct nv04_surface_2d *eng2d;
 	struct nouveau_grobj *eng3d;
 	struct nouveau_notifier *sync;
 
@@ -32,6 +31,8 @@ struct nvfx_screen {
 	/* Vtxprog resources */
 	struct nouveau_resource *vp_exec_heap;
 	struct nouveau_resource *vp_data_heap;
+
+	struct nv04_2d_context* eng2d;
 };
 
 static INLINE struct nvfx_screen *
@@ -40,4 +41,7 @@ nvfx_screen(struct pipe_screen *screen)
 	return (struct nvfx_screen *)screen;
 }
 
+int nvfx_screen_surface_init(struct pipe_screen *pscreen);
+void nvfx_screen_surface_takedown(struct pipe_screen *pscreen);
+
 #endif
diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c
index 657e315f06..e111d11627 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_fb.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c
@@ -2,8 +2,6 @@
 #include "nvfx_resource.h"
 #include "nouveau/nouveau_util.h"
 
-
-
 void
 nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 {
@@ -31,7 +29,7 @@ nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 		rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
 		nvfx->hw_rt[i].bo = ((struct nvfx_miptree*)fb->cbufs[i]->texture)->base.bo;
 		nvfx->hw_rt[i].offset = fb->cbufs[i]->offset;
-		nvfx->hw_rt[i].pitch = ((struct nv04_surface *)fb->cbufs[i])->pitch;
+		nvfx->hw_rt[i].pitch = ((struct nvfx_surface *)fb->cbufs[i])->pitch;
 	}
 	for(; i < 4; ++i)
 		nvfx->hw_rt[i].bo = 0;
@@ -44,7 +42,7 @@ nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 		zeta_format = fb->zsbuf->format;
 		nvfx->hw_zeta.bo = ((struct nvfx_miptree*)fb->zsbuf->texture)->base.bo;
 		nvfx->hw_zeta.offset = fb->zsbuf->offset;
-		nvfx->hw_zeta.pitch = ((struct nv04_surface *)fb->zsbuf)->pitch;
+		nvfx->hw_zeta.pitch = ((struct nvfx_surface *)fb->zsbuf)->pitch;
 	}
 	else
 		nvfx->hw_zeta.bo = 0;
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
index a605d2b754..a97f342c64 100644
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ b/src/gallium/drivers/nvfx/nvfx_surface.c
@@ -26,33 +26,319 @@
  *
  **************************************************************************/
 
+#include "pipe/p_context.h"
+#include "pipe/p_format.h"
+#include "util/u_format.h"
+#include "util/u_math.h"
+#include "util/u_memory.h"
+#include "util/u_pack_color.h"
+#include "util/u_rect.h"
+#include "util/u_blitter.h"
+
+#include "nouveau/nouveau_winsys.h"
+#include "nouveau/nouveau_util.h"
+#include "nouveau/nouveau_screen.h"
 #include "nvfx_context.h"
+#include "nvfx_screen.h"
 #include "nvfx_resource.h"
-#include "pipe/p_defines.h"
-#include "util/u_inlines.h"
-#include "util/u_pack_color.h"
+#include "nv04_2d.h"
+
+#include <nouveau/nouveau_bo.h>
+
+static INLINE void
+nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format)
+{
+	unsigned bits = util_format_get_blocksizebits(format);
+	switch(bits)
+	{
+	case 8:
+		rgn->bpps = 0;
+		break;
+	case 16:
+		rgn->bpps = 1;
+		break;
+	case 32:
+		rgn->bpps = 2;
+		break;
+	default:
+		assert(util_is_pot(bits));
+		int shift = log2i(bits) - 3;
+		assert(shift >= 2);
+		rgn->bpps = 2;
+		shift -= 2;
+
+		rgn->x = util_format_get_nblocksx(format, rgn->x) << shift;
+		rgn->y = util_format_get_nblocksy(format, rgn->y);
+	}
+}
+
+static INLINE void
+nvfx_region_fixup_swizzled(struct nv04_region* rgn, unsigned zslice, unsigned width, unsigned height, unsigned depth)
+{
+	// TODO: move this code to surface creation?
+	if((depth <= 1) && (height <= 1 || width <= 2))
+		rgn->pitch = width << rgn->bpps;
+	else if(depth > 1 && height <= 2 && width <= 2)
+	{
+		rgn->pitch = width << rgn->bpps;
+		rgn->offset += (zslice * width * height) << rgn->bpps;
+	}
+	else
+	{
+		rgn->pitch = 0;
+		rgn->z = zslice;
+		rgn->w = width;
+		rgn->h = height;
+		rgn->d = depth;
+	}
+}
+
+static INLINE void
+nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, unsigned x, unsigned y)
+{
+	rgn->bo = ((struct nvfx_resource*)surf->base.texture)->bo;
+	rgn->offset = surf->base.offset;
+	rgn->pitch = surf->pitch;
+	rgn->x = x;
+	rgn->y = y;
+	rgn->z = 0;
+
+	nvfx_region_set_format(rgn, surf->base.format);
+	if(!(surf->base.texture->flags & NVFX_RESOURCE_FLAG_LINEAR))
+		nvfx_region_fixup_swizzled(rgn, surf->base.zslice, surf->base.width, surf->base.height, u_minify(surf->base.texture->depth0, surf->base.level));
+}
+
+static INLINE void
+nvfx_region_init_for_subresource(struct nv04_region* rgn, struct pipe_resource* pt, struct pipe_subresource sub, unsigned x, unsigned y, unsigned z)
+{
+	rgn->bo = ((struct nvfx_resource*)pt)->bo;
+	rgn->offset = nvfx_subresource_offset(pt, sub.face, sub.level, z);
+	rgn->pitch = nvfx_subresource_pitch(pt, sub.level);
+	rgn->x = x;
+	rgn->y = y;
+	rgn->z = 0;
+
+	nvfx_region_set_format(rgn, pt->format);
+	if(!(pt->flags & NVFX_RESOURCE_FLAG_LINEAR))
+		nvfx_region_fixup_swizzled(rgn, z, u_minify(pt->width0, sub.level), u_minify(pt->height0, sub.level), u_minify(pt->depth0, sub.level));
+}
+
+// TODO: actually test this for all formats, it's probably wrong for some...
+
+static INLINE int
+nvfx_surface_format(enum pipe_format format)
+{
+	switch(util_format_get_blocksize(format)) {
+	case 1:
+		return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
+	case 2:
+		//return NV04_CONTEXT_SURFACES_2D_FORMAT_Y16;
+		return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
+	case 4:
+		//if(format == PIPE_FORMAT_B8G8R8X8_UNORM || format == PIPE_FORMAT_B8G8R8A8_UNORM)
+			return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
+		//else
+		//	return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
+	default:
+		return -1;
+	}
+}
+
+static INLINE int
+nv04_scaled_image_format(enum pipe_format format)
+{
+	switch(util_format_get_blocksize(format)) {
+	case 1:
+		return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
+	case 2:
+		//if(format == PIPE_FORMAT_B5G5R5A1_UNORM)
+		//	return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
+		//else
+			return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
+	case 4:
+		if(format == PIPE_FORMAT_B8G8R8X8_UNORM)
+			return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
+		else
+			return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
+	default:
+		return -1;
+	}
+}
+
+static struct blitter_context*
+nvfx_get_blitter(struct pipe_context* pipe, int copy)
+{
+	struct nvfx_context* nvfx = nvfx_context(pipe);
+
+	struct blitter_context* blitter = nvfx->blitter;
+	if(!blitter)
+		nvfx->blitter = blitter = util_blitter_create(pipe);
+
+	util_blitter_save_blend(blitter, nvfx->blend);
+	util_blitter_save_depth_stencil_alpha(blitter, nvfx->zsa);
+	util_blitter_save_stencil_ref(blitter, &nvfx->stencil_ref);
+	util_blitter_save_rasterizer(blitter, nvfx->rasterizer);
+	util_blitter_save_fragment_shader(blitter, nvfx->fragprog);
+	util_blitter_save_vertex_shader(blitter, nvfx->vertprog);
+	util_blitter_save_viewport(blitter, &nvfx->viewport);
+	util_blitter_save_framebuffer(blitter, &nvfx->framebuffer);
+	util_blitter_save_clip(blitter, &nvfx->clip);
+	util_blitter_save_vertex_elements(blitter, nvfx->vtxelt);
+	util_blitter_save_vertex_buffers(blitter, nvfx->vtxbuf_nr, nvfx->vtxbuf);
+
+	if(copy)
+	{
+		util_blitter_save_fragment_sampler_states(blitter, nvfx->nr_samplers, (void**)nvfx->tex_sampler);
+		util_blitter_save_fragment_sampler_views(blitter, nvfx->nr_textures, nvfx->fragment_sampler_views);
+	}
+
+	return blitter;
+}
+
+static unsigned
+nvfx_region_clone(struct nv04_2d_context* ctx, struct nv04_region* rgn, unsigned w, unsigned h, boolean for_read)
+{
+	unsigned begin = nv04_region_begin(rgn, w, h);
+	unsigned end = nv04_region_end(rgn, w, h);
+	unsigned size = end - begin;
+	struct nouveau_bo* bo = 0;
+	nouveau_bo_new(rgn->bo->device, NOUVEAU_BO_MAP | NOUVEAU_BO_GART, 256, size, &bo);
+
+	if(for_read || (size > ((w * h) << rgn->bpps)))
+		nv04_memcpy(ctx, bo, 0, rgn->bo, rgn->offset + begin, size);
+
+	rgn->bo = bo;
+	rgn->offset = -begin;
+	return begin;
+}
 
 static void
-nvfx_surface_copy(struct pipe_context *pipe,
-		  struct pipe_resource *dest, struct pipe_subresource subdst,
-		  unsigned destx, unsigned desty, unsigned destz,
-		  struct pipe_resource *src, struct pipe_subresource subsrc,
+nvfx_resource_copy_region(struct pipe_context *pipe,
+		  struct pipe_resource *dstr, struct pipe_subresource subdst,
+		  unsigned dstx, unsigned dsty, unsigned dstz,
+		  struct pipe_resource *srcr, struct pipe_subresource subsrc,
 		  unsigned srcx, unsigned srcy, unsigned srcz,
-		  unsigned width, unsigned height)
+		  unsigned w, unsigned h)
 {
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nv04_surface_2d *eng2d = nvfx->screen->eng2d;
-	struct pipe_surface *ps_dst, *ps_src;
+	struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
+	struct nv04_region dst, src;
+
+	if(!w || !h)
+		return;
+
+	static int copy_threshold = -1;
+	if(copy_threshold < 0)
+	{
+		copy_threshold = debug_get_num_option("NOUVEAU_COPY_THRESHOLD", 0);
+		if(copy_threshold < 0)
+			copy_threshold = 0;
+	}
 
-	ps_src = nvfx_miptree_surface_new(pipe->screen, src, subsrc.face,
-					  subsrc.level, srcz, 0 /* bind flags */);
-	ps_dst = nvfx_miptree_surface_new(pipe->screen, dest, subdst.face,
-					  subdst.level, destz, 0 /* bindflags */);
+	int dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING;
+	int src_on_gpu = nvfx_resource_on_gpu(srcr);
 
-	eng2d->copy(eng2d, ps_dst, destx, desty, ps_src, srcx, srcy, width, height);
+	nvfx_region_init_for_subresource(&dst, dstr, subdst, dstx, dsty, dstz);
+	nvfx_region_init_for_subresource(&src, srcr, subsrc, srcx, srcy, srcz);
+	w = util_format_get_stride(dstr->format, w) >> dst.bpps;
+	h = util_format_get_nblocksy(dstr->format, h);
 
-	nvfx_miptree_surface_del(ps_src);
-	nvfx_miptree_surface_del(ps_dst);
+	int ret;
+	boolean small = (w * h <= copy_threshold);
+	if((!dst_to_gpu || !src_on_gpu) && small)
+		ret = -1; /* use the CPU */
+	else
+		ret = nv04_region_copy_2d(ctx, &dst, &src, w, h,
+			dstr->target == PIPE_BUFFER ? -1 : nvfx_surface_format(dstr->format),
+			dstr->target == PIPE_BUFFER ? -1 : nv04_scaled_image_format(dstr->format),
+			dst_to_gpu, src_on_gpu);
+	if(!ret)
+	{}
+	else if(ret > 0 && dstr->bind & PIPE_BIND_RENDER_TARGET && srcr->bind & PIPE_BIND_SAMPLER_VIEW)
+	{
+		struct blitter_context* blitter = nvfx_get_blitter(pipe, 1);
+		util_blitter_copy_region(blitter, dstr, subdst, dstx, dsty, dstz, srcr, subsrc, srcx, srcy, srcz, w, h, TRUE);
+	}
+	else
+	{
+		struct nv04_region dstt = dst;
+		struct nv04_region srct = src;
+		unsigned dstbegin = 0;
+
+		if(!small)
+		{
+			if(src_on_gpu)
+				nvfx_region_clone(ctx, &srct, w, h, TRUE);
+
+			if(dst_to_gpu)
+				dstbegin = nvfx_region_clone(ctx, &dstt, w, h, FALSE);
+		}
+
+		nv04_region_copy_cpu(&dstt, &srct, w, h);
+
+		if(srct.bo != src.bo)
+			nouveau_screen_bo_release(pipe->screen, srct.bo);
+
+		if(dstt.bo != dst.bo)
+		{
+			nv04_memcpy(ctx, dst.bo, dst.offset + dstbegin, dstt.bo, 0, dstt.bo->size);
+			nouveau_screen_bo_release(pipe->screen, dstt.bo);
+		}
+	}
+}
+
+static int
+nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts,
+		  unsigned dx, unsigned dy, unsigned w, unsigned h, unsigned value)
+{
+	struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
+	struct nv04_region dst;
+	/* Always try to use the GPU right now, if possible
+	 * If the user wanted the surface data on the CPU, he would have cleared with memset */
+
+	// we don't care about interior pixel order since we set all them to the same value
+	nvfx_region_init_for_surface(&dst, (struct nvfx_surface*)dsts, dx, dy);
+	w = util_format_get_stride(dsts->format, w) >> dst.bpps;
+	h = util_format_get_nblocksy(dsts->format, h);
+
+	int ret = nv04_region_fill_2d(ctx, &dst, w, h, value);
+	if(ret > 0 && dsts->texture->bind & PIPE_BIND_RENDER_TARGET)
+		return 1;
+	else if(ret)
+	{
+		struct nv04_region dstt = dst;
+		unsigned dstbegin = 0;
+
+		if(nvfx_resource_on_gpu(dsts->texture))
+			dstbegin = nvfx_region_clone(ctx, &dstt, w, h, FALSE);
+
+		nv04_region_fill_cpu(&dstt, w, h, value);
+
+		if(dstt.bo != dst.bo)
+		{
+			nv04_memcpy(ctx, dst.bo, dst.offset + dstbegin, dstt.bo, 0, dstt.bo->size);
+			nouveau_screen_bo_release(pipe->screen, dstt.bo);
+		}
+	}
+
+	return 0;
+}
+
+
+void
+nvfx_screen_surface_takedown(struct pipe_screen *pscreen)
+{
+	nv04_2d_context_takedown(nvfx_screen(pscreen)->eng2d);
+	nvfx_screen(pscreen)->eng2d = 0;
+}
+
+int
+nvfx_screen_surface_init(struct pipe_screen *pscreen)
+{
+	struct nv04_2d_context* ctx = nv04_2d_context_init(nouveau_screen(pscreen)->channel);
+	if(!ctx)
+		return -1;
+	nvfx_screen(pscreen)->eng2d = ctx;
+	return 0;
 }
 
 static void
@@ -62,12 +348,16 @@ nvfx_clear_render_target(struct pipe_context *pipe,
 			 unsigned dstx, unsigned dsty,
 			 unsigned width, unsigned height)
 {
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nv04_surface_2d *eng2d = nvfx->screen->eng2d;
 	union util_color uc;
 	util_pack_color(rgba, dst->format, &uc);
 
-	eng2d->fill(eng2d, dst, dstx, dsty, width, height, uc.ui);
+	if(util_format_get_blocksizebits(dst->format) > 32
+		|| nvfx_surface_fill(pipe, dst, dstx, dsty, width, height, uc.ui))
+	{
+		// TODO: probably should use hardware clear here instead if possible
+		struct blitter_context* blitter = nvfx_get_blitter(pipe, 0);
+		util_blitter_clear_render_target(blitter, dst, rgba, dstx, dsty, width, height);
+	}
 }
 
 static void
@@ -79,18 +369,20 @@ nvfx_clear_depth_stencil(struct pipe_context *pipe,
 			 unsigned dstx, unsigned dsty,
 			 unsigned width, unsigned height)
 {
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nv04_surface_2d *eng2d = nvfx->screen->eng2d;
-
-	eng2d->fill(eng2d, dst, dstx, dsty, width, height,
-		    util_pack_z_stencil(dst->format, depth, stencil));
+	if(util_format_get_blocksizebits(dst->format) > 32
+		|| nvfx_surface_fill(pipe, dst, dstx, dsty, width, height, util_pack_z_stencil(dst->format, depth, stencil)))
+	{
+		// TODO: probably should use hardware clear here instead if possible
+		struct blitter_context* blitter = nvfx_get_blitter(pipe, 0);
+		util_blitter_clear_depth_stencil(blitter, dst, clear_flags, depth, stencil, dstx, dsty, width, height);
+	}
 }
 
 
 void
 nvfx_init_surface_functions(struct nvfx_context *nvfx)
 {
-	nvfx->pipe.resource_copy_region = nvfx_surface_copy;
+	nvfx->pipe.resource_copy_region = nvfx_resource_copy_region;
 	nvfx->pipe.clear_render_target = nvfx_clear_render_target;
 	nvfx->pipe.clear_depth_stencil = nvfx_clear_depth_stencil;
 }
-- 
cgit v1.2.3


From d983701267de0083cc702e460c841741292cc9b8 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 18 Jan 2010 23:40:22 +0100
Subject: nvfx: new 2D: enable swizzling for all surfaces

Now that the new 2D code is in place, swizzling can be safely enabled.

Render temporaries are needed in some cases, so this may degrade nv30
a bit until it gets render temporaries too.
---
 src/gallium/drivers/nvfx/nvfx_miptree.c | 21 ++++-----------------
 1 file changed, 4 insertions(+), 17 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index b8ec726624..ffacf8a8e5 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -19,32 +19,19 @@ nvfx_miptree_choose_format(struct nvfx_miptree *mt)
 	unsigned uniform_pitch = 0;
 	static int no_swizzle = -1;
 	if(no_swizzle < 0)
-		no_swizzle = debug_get_bool_option("NOUVEAU_NO_SWIZZLE", FALSE);
+		no_swizzle = debug_get_bool_option("NV40_NO_SWIZZLE", FALSE); /* this will break things on nv30 */
 
-	/* Non-uniform pitch textures must be POT */
-	if (pt->width0 & (pt->width0 - 1) ||
-	    pt->height0 & (pt->height0 - 1) ||
-	    pt->depth0 & (pt->depth0 - 1)
+	if (!util_is_pot(pt->width0) ||
+	    !util_is_pot(pt->height0) ||
+	    !util_is_pot(pt->depth0)
 	    )
 		uniform_pitch = 1;
 
-	/* All texture formats except compressed ones can be swizzled
-	 * Unsure about depth, let's prevent swizzling for now
-	 */
 	if (
 		(pt->bind & (PIPE_BIND_SCANOUT | PIPE_BIND_DISPLAY_TARGET))
 		|| (pt->usage & PIPE_USAGE_DYNAMIC) || (pt->usage & PIPE_USAGE_STAGING)
-		|| util_format_is_depth_or_stencil(pt->format)
 		|| util_format_is_compressed(pt->format)
-		// disable swizzled textures on NV04-NV20 as our current drivers don't fully support that
-		// TODO: hardware should support them, fix the drivers and reenable
-		|| nouveau_screen(pt->screen)->device->chipset < 0x30
 		|| no_swizzle
-
-		// disable swizzling for non-RGBA 2D because our current 2D code can't handle anything
-		// else correctly, and even that is semi-broken
-		|| pt->target != PIPE_TEXTURE_2D
-		|| (pt->format != PIPE_FORMAT_B8G8R8A8_UNORM && pt->format != PIPE_FORMAT_B8G8R8X8_UNORM)
 	)
 		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
 
-- 
cgit v1.2.3


From 4793f48a19465ad27c3a33d9453a0def78775736 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 23 Feb 2010 12:47:45 +0100
Subject: nvfx: new 2D: optimize fragtex format lookup

Use an array indexed by the pipe format instead of doing a linear scan.
---
 src/gallium/drivers/nvfx/nv30_fragtex.c | 30 +++++-------------------------
 src/gallium/drivers/nvfx/nv40_fragtex.c | 30 +++++-------------------------
 2 files changed, 10 insertions(+), 50 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
index 85489eab28..a812d88353 100644
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv30_fragtex.c
@@ -35,9 +35,7 @@ nv30_sampler_state_init(struct pipe_context *pipe,
 }
 
 #define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w)                        \
-{                                                                              \
-  TRUE,                                                                        \
-  PIPE_FORMAT_##m,                                                             \
+[PIPE_FORMAT_##m] = {                                                                              \
   NV34TCL_TX_FORMAT_FORMAT_##tf,                                               \
   (NV34TCL_TX_SWIZZLE_S0_X_##ts0x | NV34TCL_TX_SWIZZLE_S0_Y_##ts0y |           \
    NV34TCL_TX_SWIZZLE_S0_Z_##ts0z | NV34TCL_TX_SWIZZLE_S0_W_##ts0w |           \
@@ -46,14 +44,13 @@ nv30_sampler_state_init(struct pipe_context *pipe,
 }
 
 struct nv30_texture_format {
-	boolean defined;
-	uint	pipe;
 	int     format;
 	int     swizzle;
 };
 
 static struct nv30_texture_format
-nv30_texture_formats[] = {
+nv30_texture_formats[PIPE_FORMAT_COUNT] = {
+	[0 ... PIPE_FORMAT_COUNT - 1] = {-1, 0},
 	_(B8G8R8X8_UNORM, A8R8G8B8,   S1,   S1,   S1,  ONE, X, Y, Z, W),
 	_(B8G8R8A8_UNORM, A8R8G8B8,   S1,   S1,   S1,   S1, X, Y, Z, W),
 	_(B5G5R5A1_UNORM, A1R5G5B5,   S1,   S1,   S1,   S1, X, Y, Z, W),
@@ -72,22 +69,6 @@ nv30_texture_formats[] = {
 	{},
 };
 
-static struct nv30_texture_format *
-nv30_fragtex_format(uint pipe_format)
-{
-	struct nv30_texture_format *tf = nv30_texture_formats;
-
-	while (tf->defined) {
-		if (tf->pipe == pipe_format)
-			return tf;
-		tf++;
-	}
-
-	NOUVEAU_ERR("unknown texture format %s\n", util_format_name(pipe_format));
-	return NULL;
-}
-
-
 void
 nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 {
@@ -100,9 +81,8 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 	uint32_t txf, txs;
 	unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 
-	tf = nv30_fragtex_format(pt->format);
-	if (!tf)
-		return;
+	tf = &nv30_texture_formats[pt->format];
+	assert(tf->format >= 0);
 
 	txf  = tf->format;
 	txf |= ((pt->last_level>0) ? NV34TCL_TX_FORMAT_MIPMAP : 0);
diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c
index 45c34c7ffd..87aa7eb1a2 100644
--- a/src/gallium/drivers/nvfx/nv40_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv40_fragtex.c
@@ -49,9 +49,7 @@ nv40_sampler_state_init(struct pipe_context *pipe,
 }
 
 #define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sx,sy,sz,sw)            \
-{                                                                              \
-  TRUE,                                                                        \
-  PIPE_FORMAT_##m,                                                             \
+[PIPE_FORMAT_##m] = {                                                                              \
   NV40TCL_TEX_FORMAT_FORMAT_##tf,                                              \
   (NV34TCL_TX_SWIZZLE_S0_X_##ts0x | NV34TCL_TX_SWIZZLE_S0_Y_##ts0y |         \
    NV34TCL_TX_SWIZZLE_S0_Z_##ts0z | NV34TCL_TX_SWIZZLE_S0_W_##ts0w |         \
@@ -62,15 +60,14 @@ nv40_sampler_state_init(struct pipe_context *pipe,
 }
 
 struct nv40_texture_format {
-	boolean defined;
-	uint	pipe;
 	int     format;
 	int     swizzle;
 	int     sign;
 };
 
 static struct nv40_texture_format
-nv40_texture_formats[] = {
+nv40_texture_formats[PIPE_FORMAT_COUNT] = {
+	[0 ... PIPE_FORMAT_COUNT - 1] = {-1, 0, 0},
 	_(B8G8R8X8_UNORM, A8R8G8B8,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0, 0, 0, 0),
 	_(B8G8R8A8_UNORM, A8R8G8B8,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
 	_(B5G5R5A1_UNORM, A1R5G5B5,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
@@ -90,22 +87,6 @@ nv40_texture_formats[] = {
 	{},
 };
 
-static struct nv40_texture_format *
-nv40_fragtex_format(uint pipe_format)
-{
-	struct nv40_texture_format *tf = nv40_texture_formats;
-
-	while (tf->defined) {
-		if (tf->pipe == pipe_format)
-			return tf;
-		tf++;
-	}
-
-	NOUVEAU_ERR("unknown texture format %s\n", util_format_name(pipe_format));
-	return NULL;
-}
-
-
 void
 nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
 {
@@ -119,9 +100,8 @@ nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
 	uint32_t txf, txs, txp;
 	unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 
-	tf = nv40_fragtex_format(pt->format);
-	if (!tf)
-		assert(0);
+	tf = &nv40_texture_formats[pt->format];
+	assert(tf->format >= 0);
 
 	txf  = ps->fmt;
 	txf |= tf->format | 0x8000;
-- 
cgit v1.2.3


From ff74143fcc80b0157875bb0ce4b34a80f92e09c2 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Thu, 11 Mar 2010 18:06:28 +0100
Subject: nv30: new 2D: support ARB_texture_rectangle

This uses nv30's _RECT formats.
---
 src/gallium/drivers/nvfx/nv30_fragtex.c | 36 +++++++++++++++++++++++++++++++--
 src/gallium/drivers/nvfx/nvfx_miptree.c |  3 ++-
 2 files changed, 36 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
index a812d88353..fbc69cf44a 100644
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv30_fragtex.c
@@ -37,6 +37,7 @@ nv30_sampler_state_init(struct pipe_context *pipe,
 #define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w)                        \
 [PIPE_FORMAT_##m] = {                                                                              \
   NV34TCL_TX_FORMAT_FORMAT_##tf,                                               \
+  NV34TCL_TX_FORMAT_FORMAT_##tf##_RECT,                                               \
   (NV34TCL_TX_SWIZZLE_S0_X_##ts0x | NV34TCL_TX_SWIZZLE_S0_Y_##ts0y |           \
    NV34TCL_TX_SWIZZLE_S0_Z_##ts0z | NV34TCL_TX_SWIZZLE_S0_W_##ts0w |           \
    NV34TCL_TX_SWIZZLE_S1_X_##ts1x | NV34TCL_TX_SWIZZLE_S1_Y_##ts1y |           \
@@ -45,12 +46,17 @@ nv30_sampler_state_init(struct pipe_context *pipe,
 
 struct nv30_texture_format {
 	int     format;
+	int     rect_format;
 	int     swizzle;
 };
 
+#define NV34TCL_TX_FORMAT_FORMAT_DXT1_RECT NV34TCL_TX_FORMAT_FORMAT_DXT1
+#define NV34TCL_TX_FORMAT_FORMAT_DXT3_RECT NV34TCL_TX_FORMAT_FORMAT_DXT3
+#define NV34TCL_TX_FORMAT_FORMAT_DXT5_RECT NV34TCL_TX_FORMAT_FORMAT_DXT5
+
 static struct nv30_texture_format
 nv30_texture_formats[PIPE_FORMAT_COUNT] = {
-	[0 ... PIPE_FORMAT_COUNT - 1] = {-1, 0},
+	[0 ... PIPE_FORMAT_COUNT - 1] = {-1, 0, 0},
 	_(B8G8R8X8_UNORM, A8R8G8B8,   S1,   S1,   S1,  ONE, X, Y, Z, W),
 	_(B8G8R8A8_UNORM, A8R8G8B8,   S1,   S1,   S1,   S1, X, Y, Z, W),
 	_(B5G5R5A1_UNORM, A1R5G5B5,   S1,   S1,   S1,   S1, X, Y, Z, W),
@@ -80,11 +86,34 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	uint32_t txf, txs;
 	unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
+	unsigned use_rect;
 
 	tf = &nv30_texture_formats[pt->format];
 	assert(tf->format >= 0);
 
-	txf  = tf->format;
+	if(pt->height0 <= 1 || util_format_is_compressed(pt->format))
+	{
+		/* in the case of compressed or 1D textures, we can get away with this,
+		 * since the layout is the same
+		 */
+		use_rect = ps->fmt;
+	}
+	else
+	{
+		static int warned = 0;
+		if(!warned && !ps->fmt != !(pt->flags & NVFX_RESOURCE_FLAG_LINEAR)) {
+			warned = 1;
+			fprintf(stderr,
+					"Unimplemented: coordinate normalization mismatch. Possible reasons:\n"
+					"1. ARB_texture_non_power_of_two is being used despite the fact it isn't supported\n"
+					"2. The state tracker is not using the appropriate coordinate normalization\n"
+					"3. The state tracker is not supported\n");
+		}
+
+		use_rect  = pt->flags & NVFX_RESOURCE_FLAG_LINEAR;
+	}
+
+	txf = use_rect ? tf->rect_format : tf->format;
 	txf |= ((pt->last_level>0) ? NV34TCL_TX_FORMAT_MIPMAP : 0);
 	txf |= log2i(pt->width0) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT;
 	txf |= log2i(pt->height0) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT;
@@ -112,6 +141,9 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 
 	txs = tf->swizzle;
 
+	if(use_rect)
+		txs |= nvfx_subresource_pitch(&mt->base, 0) << NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT;
+
 	MARK_RING(chan, 9, 2);
 	OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8));
 	OUT_RELOC(chan, bo, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0);
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index ffacf8a8e5..7deb9d7b9a 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -23,7 +23,8 @@ nvfx_miptree_choose_format(struct nvfx_miptree *mt)
 
 	if (!util_is_pot(pt->width0) ||
 	    !util_is_pot(pt->height0) ||
-	    !util_is_pot(pt->depth0)
+	    !util_is_pot(pt->depth0) ||
+	    (!nvfx_screen(pt->screen)->is_nv4x && pt->target == PIPE_TEXTURE_RECT)
 	    )
 		uniform_pitch = 1;
 
-- 
cgit v1.2.3


From 28eb392a853bb43bdc6cfe7ba814f046c39ca7ae Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 3 Aug 2010 05:47:41 +0200
Subject: nvfx: new 2D: new render temporaries with resources

This patch adds support for creating temporary surfaces to allow
rendering to surfaces that cannot be rendered to.
It uses the _second_ version of the render temporary infrastructure.

This is necessary for swizzled 3D textures and small mipmaps of
swizzled 2D textures.

This version of the patch creates a resource to use as a temporary
instead of a raw BO, making the code simpler.
---
 src/gallium/drivers/nvfx/nvfx_context.c    |   4 +
 src/gallium/drivers/nvfx/nvfx_context.h    |   6 +-
 src/gallium/drivers/nvfx/nvfx_fragtex.c    |   4 +
 src/gallium/drivers/nvfx/nvfx_miptree.c    |  51 +++---
 src/gallium/drivers/nvfx/nvfx_resource.h   |  36 ++++-
 src/gallium/drivers/nvfx/nvfx_state_emit.c |  81 ++++++++--
 src/gallium/drivers/nvfx/nvfx_state_fb.c   | 251 ++++++++++++++++++-----------
 src/gallium/drivers/nvfx/nvfx_surface.c    | 121 ++++++++++++--
 8 files changed, 408 insertions(+), 146 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 3d45f5f0ba..7ab81de7dd 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -15,6 +15,7 @@ nvfx_flush(struct pipe_context *pipe, unsigned flags,
 	struct nouveau_channel *chan = screen->base.channel;
 	struct nouveau_grobj *eng3d = screen->eng3d;
 
+	/* XXX: we need to actually be intelligent here */
 	if (flags & PIPE_FLUSH_TEXTURE_CACHE) {
 		BEGIN_RING(chan, eng3d, 0x1fd8, 1);
 		OUT_RING  (chan, 2);
@@ -87,5 +88,8 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	/* set these to that we init them on first validation */
 	nvfx->state.scissor_enabled = ~0;
 	nvfx->state.stipple_enabled = ~0;
+
+	LIST_INITHEAD(&nvfx->render_cache);
+
 	return &nvfx->pipe;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 278be94d52..a6ea913967 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -11,6 +11,7 @@
 #include "util/u_memory.h"
 #include "util/u_math.h"
 #include "util/u_inlines.h"
+#include "util/u_double_list.h"
 
 #include "draw/draw_vertex.h"
 #include "util/u_blitter.h"
@@ -67,6 +68,7 @@ struct nvfx_state {
 	unsigned scissor_enabled;
 	unsigned stipple_enabled;
 	unsigned fp_samplers;
+	unsigned render_temps;
 };
 
 struct nvfx_vtxelt_state {
@@ -90,6 +92,7 @@ struct nvfx_context {
 
 	struct draw_context *draw;
 	struct blitter_context* blitter;
+	struct list_head render_cache;
 
 	/* HW state derived from pipe states */
 	struct nvfx_state state;
@@ -185,7 +188,8 @@ extern void nvfx_draw_elements_swtnl(struct pipe_context *pipe,
 extern void nvfx_vtxfmt_validate(struct nvfx_context *nvfx);
 
 /* nvfx_fb.c */
-extern void nvfx_state_framebuffer_validate(struct nvfx_context *nvfx);
+extern int nvfx_framebuffer_prepare(struct nvfx_context *nvfx);
+extern void nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result);
 void
 nvfx_framebuffer_relocate(struct nvfx_context *nvfx);
 
diff --git a/src/gallium/drivers/nvfx/nvfx_fragtex.c b/src/gallium/drivers/nvfx/nvfx_fragtex.c
index 0b4a434fec..6605745433 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragtex.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragtex.c
@@ -16,6 +16,10 @@ nvfx_fragtex_validate(struct nvfx_context *nvfx)
 		samplers &= ~(1 << unit);
 
 		if(nvfx->fragment_sampler_views[unit] && nvfx->tex_sampler[unit]) {
+			util_dirty_surfaces_use_for_sampling(&nvfx->pipe,
+					&((struct nvfx_miptree*)nvfx->fragment_sampler_views[unit]->texture)->dirty_surfaces,
+					nvfx_surface_flush);
+
 			if(!nvfx->is_nv4x)
 				nv30_fragtex_set(nvfx, unit);
 			else
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 7deb9d7b9a..530d705e13 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -11,6 +11,7 @@
 #include "nvfx_screen.h"
 #include "nvfx_resource.h"
 #include "nvfx_transfer.h"
+#include "nv04_2d.h"
 
 static void
 nvfx_miptree_choose_format(struct nvfx_miptree *mt)
@@ -114,17 +115,24 @@ nvfx_miptree_get_handle(struct pipe_screen *pscreen,
 }
 
 
+static void
+nvfx_miptree_surface_final_destroy(struct pipe_surface* ps)
+{
+	struct nvfx_surface* ns = (struct nvfx_surface*)ps;
+	pipe_resource_reference(&ps->texture, 0);
+	pipe_resource_reference((struct pipe_resource**)&ns->temp, 0);
+	FREE(ps);
+}
+
 static void
 nvfx_miptree_destroy(struct pipe_screen *screen, struct pipe_resource *pt)
 {
 	struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
+	util_surfaces_destroy(&mt->surfaces, pt, nvfx_miptree_surface_final_destroy);
 	nouveau_screen_bo_release(screen, mt->base.bo);
 	FREE(mt);
 }
 
-
-
-
 struct u_resource_vtbl nvfx_miptree_vtbl = 
 {
    nvfx_miptree_get_handle,	      /* get_handle */
@@ -152,6 +160,8 @@ nvfx_miptree_create_skeleton(struct pipe_screen *pscreen, const struct pipe_reso
 
         mt->base.base = *pt;
         mt->base.vtbl = &nvfx_miptree_vtbl;
+        util_dirty_surfaces_init(&mt->dirty_surfaces);
+
         pipe_reference_init(&mt->base.base.reference, 1);
         mt->base.base.screen = pscreen;
 
@@ -218,29 +228,28 @@ nvfx_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
 			 unsigned face, unsigned level, unsigned zslice,
 			 unsigned flags)
 {
+	struct nvfx_miptree* mt = (struct nvfx_miptree*)pt;
 	struct nvfx_surface *ns;
 
-	ns = CALLOC_STRUCT(nvfx_surface);
-	if (!ns)
-		return NULL;
-	pipe_resource_reference(&ns->base.texture, pt);
-	ns->base.format = pt->format;
-	ns->base.width = u_minify(pt->width0, level);
-	ns->base.height = u_minify(pt->height0, level);
-	ns->base.usage = flags;
-	pipe_reference_init(&ns->base.reference, 1);
-	ns->base.face = face;
-	ns->base.level = level;
-	ns->base.zslice = zslice;
-	ns->pitch = nvfx_subresource_pitch(pt, level);
-	ns->base.offset = nvfx_subresource_offset(pt, face, level, zslice);
-
-	return &ns->base;
+	ns = (struct nvfx_surface*)util_surfaces_get(&mt->surfaces, sizeof(struct nvfx_surface), pscreen, pt, face, level, zslice, flags);
+	if(ns->base.base.offset == ~0) {
+		util_dirty_surface_init(&ns->base);
+		ns->pitch = nvfx_subresource_pitch(pt, level);
+		ns->base.base.offset = nvfx_subresource_offset(pt, face, level, zslice);
+	}
+
+	return &ns->base.base;
 }
 
 void
 nvfx_miptree_surface_del(struct pipe_surface *ps)
 {
-	pipe_resource_reference(&ps->texture, NULL);
-	FREE(ps);
+	struct nvfx_surface* ns = (struct nvfx_surface*)ps;
+
+	if(!ns->temp)
+	{
+		util_surfaces_detach(&((struct nvfx_miptree*)ps->texture)->surfaces, ps);
+		pipe_resource_reference(&ps->texture, 0);
+		FREE(ps);
+	}
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
index 42d04ebb37..be1845dd9c 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ b/src/gallium/drivers/nvfx/nvfx_resource.h
@@ -1,13 +1,16 @@
-
 #ifndef NVFX_RESOURCE_H
 #define NVFX_RESOURCE_H
 
 #include "util/u_transfer.h"
 #include "util/u_format.h"
 #include "util/u_math.h"
+#include "util/u_double_list.h"
+#include "util/u_surfaces.h"
+#include "util/u_dirty_surfaces.h"
 #include <nouveau/nouveau_bo.h>
 
 struct pipe_resource;
+struct nv04_region;
 
 
 /* This gets further specialized into either buffer or texture
@@ -38,17 +41,34 @@ nvfx_resource_on_gpu(struct pipe_resource* pr)
 
 #define NVFX_MAX_TEXTURE_LEVELS  16
 
+/* We have the following invariants for render temporaries
+ *
+ * 1. Render temporaries are always linear
+ * 2. Render temporaries are always up to date
+ * 3. Currently, render temporaries are destroyed when the resource is used for sampling, but kept for any other use
+ *
+ * Also, we do NOT flush temporaries on any pipe->flush().
+ * This is fine, as long as scanout targets and shared resources never need temps.
+ *
+ * TODO: we may want to also support swizzled temporaries to improve performance in some cases.
+ */
+
 struct nvfx_miptree {
         struct nvfx_resource base;
 
         unsigned linear_pitch; /* for linear textures, 0 for swizzled and compressed textures with level-dependent minimal pitch */
         unsigned face_size; /* 128-byte aligned face/total size */
         unsigned level_offset[NVFX_MAX_TEXTURE_LEVELS];
+
+        struct util_surfaces surfaces;
+        struct util_dirty_surfaces dirty_surfaces;
 };
 
 struct nvfx_surface {
-	struct pipe_surface base;
+	struct util_dirty_surface base;
 	unsigned pitch;
+
+	struct nvfx_miptree* temp;
 };
 
 static INLINE 
@@ -65,6 +85,12 @@ nvfx_surface_buffer(struct pipe_surface *surf)
 	return mt->bo;
 }
 
+static INLINE struct util_dirty_surfaces*
+nvfx_surface_get_dirty_surfaces(struct pipe_surface* surf)
+{
+	struct nvfx_miptree *mt = (struct nvfx_miptree *)surf->texture;
+	return &mt->dirty_surfaces;
+}
 
 void
 nvfx_init_resource_functions(struct pipe_context *pipe);
@@ -141,4 +167,10 @@ nvfx_subresource_pitch(struct pipe_resource* pt, unsigned level)
 	}
 }
 
+void
+nvfx_surface_create_temp(struct pipe_context* pipe, struct pipe_surface* surf);
+
+void
+nvfx_surface_flush(struct pipe_context* pipe, struct pipe_surface* surf);
+
 #endif
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index f91ae19ecd..dc70f3de87 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -1,15 +1,48 @@
 #include "nvfx_context.h"
 #include "nvfx_state.h"
+#include "nvfx_resource.h"
 #include "draw/draw_context.h"
 
 static boolean
 nvfx_state_validate_common(struct nvfx_context *nvfx)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	unsigned dirty = nvfx->dirty;
+	unsigned dirty;
+	int all_swizzled = -1;
+	boolean flush_tex_cache = FALSE;
 
 	if(nvfx != nvfx->screen->cur_ctx)
-		dirty = ~0;
+	{
+		nvfx->dirty = ~0;
+		nvfx->screen->cur_ctx = nvfx;
+	}
+
+	/* These can trigger use the of 3D engine to copy temporaries.
+	 * That will recurse here and thus dirty all 3D state, so we need to this before anything else, and in a loop..
+	 * This converges to having clean temps, then binding both fragtexes and framebuffers.
+	 */
+	while(nvfx->dirty & (NVFX_NEW_FB | NVFX_NEW_SAMPLER))
+	{
+		if(nvfx->dirty & NVFX_NEW_SAMPLER)
+		{
+			nvfx->dirty &=~ NVFX_NEW_SAMPLER;
+			nvfx_fragtex_validate(nvfx);
+
+			// TODO: only set this if really necessary
+			flush_tex_cache = TRUE;
+		}
+
+		if(nvfx->dirty & NVFX_NEW_FB)
+		{
+			nvfx->dirty &=~ NVFX_NEW_FB;
+			all_swizzled = nvfx_framebuffer_prepare(nvfx);
+
+			// TODO: make sure this doesn't happen, i.e. fbs have matching formats
+			assert(all_swizzled >= 0);
+		}
+	}
+
+	dirty = nvfx->dirty;
 
 	if(nvfx->render_mode == HW)
 	{
@@ -35,9 +68,6 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 			nvfx_vtxfmt_validate(nvfx);
 	}
 
-	if(dirty & NVFX_NEW_FB)
-		nvfx_state_framebuffer_validate(nvfx);
-
 	if(dirty & NVFX_NEW_RAST)
 		sb_emit(chan, nvfx->rasterizer->sb, nvfx->rasterizer->sb_len);
 
@@ -48,10 +78,14 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 		nvfx_state_stipple_validate(nvfx);
 
 	if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST))
+	{
 		nvfx_fragprog_validate(nvfx);
+		if(dirty & NVFX_NEW_FRAGPROG)
+			flush_tex_cache = TRUE; // TODO: do we need this?
+	}
 
-	if(dirty & NVFX_NEW_SAMPLER)
-		nvfx_fragtex_validate(nvfx);
+	if(all_swizzled >= 0)
+		nvfx_framebuffer_validate(nvfx, all_swizzled);
 
 	if(dirty & NVFX_NEW_BLEND)
 		sb_emit(chan, nvfx->blend->sb, nvfx->blend->sb_len);
@@ -72,13 +106,17 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_FB))
 		nvfx_state_viewport_validate(nvfx);
 
-	/* TODO: could nv30 need this or something similar too? */
-	if((dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_SAMPLER)) && nvfx->is_nv4x) {
-		WAIT_RING(chan, 4);
-		OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1));
-		OUT_RING(chan, 2);
-		OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1));
-		OUT_RING(chan, 1);
+	if(flush_tex_cache)
+	{
+		// TODO: what about nv30?
+		if(nvfx->is_nv4x)
+		{
+			WAIT_RING(chan, 4);
+			OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1));
+			OUT_RING(chan, 2);
+			OUT_RING(chan, RING_3D(NV40TCL_TEX_CACHE_CTL, 1));
+			OUT_RING(chan, 1);
+		}
 	}
 	nvfx->dirty = 0;
 	return TRUE;
@@ -99,6 +137,21 @@ nvfx_state_emit(struct nvfx_context *nvfx)
 	      ;
 	MARK_RING(chan, max_relocs * 2, max_relocs * 2);
 	nvfx_state_relocate(nvfx);
+
+	unsigned render_temps = nvfx->state.render_temps;
+	if(render_temps)
+	{
+		for(int i = 0; i < nvfx->framebuffer.nr_cbufs; ++i)
+		{
+			if(render_temps & (1 << i))
+				util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.cbufs[i]),
+						(struct util_dirty_surface*)nvfx->framebuffer.cbufs[i]);
+		}
+
+		if(render_temps & 0x80)
+			util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.zsbuf),
+					(struct util_dirty_surface*)nvfx->framebuffer.zsbuf);
+	}
 }
 
 void
diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c
index e111d11627..80b0f21575 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_fb.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c
@@ -1,19 +1,56 @@
 #include "nvfx_context.h"
 #include "nvfx_resource.h"
 #include "nouveau/nouveau_util.h"
+#include "util/u_format.h"
 
-void
-nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
+static inline boolean
+nvfx_surface_linear_renderable(struct pipe_surface* surf)
+{
+	return (surf->texture->flags & NVFX_RESOURCE_FLAG_LINEAR)
+		&& !(surf->offset & 63)
+		&& !(((struct nvfx_surface*)surf)->pitch & 63);
+}
+
+static inline boolean
+nvfx_surface_swizzled_renderable(struct pipe_framebuffer_state* fb, struct pipe_surface* surf)
+{
+	/* TODO: return FALSE if we have a format not supporting swizzled rendering (e.g. r8); currently those are not supported at all */
+	return !((struct nvfx_miptree*)surf->texture)->linear_pitch
+		&& (surf->texture->target != PIPE_TEXTURE_3D || u_minify(surf->texture->depth0, surf->level) <= 1)
+		&& !(surf->offset & 127)
+		&& (surf->width == fb->width)
+		&& (surf->height == fb->height)
+		&& !((struct nvfx_surface*)surf)->temp;
+}
+
+static boolean
+nvfx_surface_get_render_target(struct pipe_surface* surf, int all_swizzled, struct nvfx_render_target* target)
+{
+	struct nvfx_surface* ns = (struct nvfx_surface*)surf;
+	if(!ns->temp)
+	{
+		target->bo = ((struct nvfx_miptree*)surf->texture)->base.bo;
+		target->offset = surf->offset;
+		target->pitch = align(ns->pitch, 64);
+		assert(target->pitch);
+		return FALSE;
+	}
+	else
+	{
+		target->offset = 0;
+		target->pitch = ns->temp->linear_pitch;
+		target->bo = ns->temp->base.bo;
+		assert(target->pitch);
+		return TRUE;
+	}
+}
+
+int
+nvfx_framebuffer_prepare(struct nvfx_context *nvfx)
 {
 	struct pipe_framebuffer_state *fb = &nvfx->framebuffer;
-	struct nouveau_channel *chan = nvfx->screen->base.channel;
-	uint32_t rt_enable = 0, rt_format = 0;
-	int i, colour_format = 0, zeta_format = 0;
-	int depth_only = 0;
-	unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
-	unsigned w = fb->width;
-	unsigned h = fb->height;
-	int colour_bits = 32, zeta_bits = 32;
+	int i, color_format = 0, zeta_format = 0;
+	int all_swizzled = 1;
 
 	if(!nvfx->is_nv4x)
 		assert(fb->nr_cbufs <= 2);
@@ -21,113 +58,135 @@ nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 		assert(fb->nr_cbufs <= 4);
 
 	for (i = 0; i < fb->nr_cbufs; i++) {
-		if (colour_format)
-			assert(colour_format == fb->cbufs[i]->format);
-		else
-			colour_format = fb->cbufs[i]->format;
-
-		rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
-		nvfx->hw_rt[i].bo = ((struct nvfx_miptree*)fb->cbufs[i]->texture)->base.bo;
-		nvfx->hw_rt[i].offset = fb->cbufs[i]->offset;
-		nvfx->hw_rt[i].pitch = ((struct nvfx_surface *)fb->cbufs[i])->pitch;
+		if (color_format) {
+			if(color_format != fb->cbufs[i]->format)
+				return -1;
+		} else
+			color_format = fb->cbufs[i]->format;
+
+		if(!nvfx_surface_swizzled_renderable(fb, fb->cbufs[i]))
+			all_swizzled = 0;
 	}
-	for(; i < 4; ++i)
-		nvfx->hw_rt[i].bo = 0;
 
+	if (fb->zsbuf) {
+		/* TODO: return FALSE if we have a format not supporting a depth buffer (e.g. r8); currently those are not supported at all */
+		if(!nvfx_surface_swizzled_renderable(fb, fb->zsbuf))
+			all_swizzled = 0;
+
+		if(all_swizzled && util_format_get_blocksize(color_format) != util_format_get_blocksize(zeta_format))
+			all_swizzled = 0;
+	}
+
+	for (i = 0; i < fb->nr_cbufs; i++) {
+		if(!((struct nvfx_surface*)fb->cbufs[i])->temp && !all_swizzled && !nvfx_surface_linear_renderable(fb->cbufs[i]))
+			nvfx_surface_create_temp(&nvfx->pipe, fb->cbufs[i]);
+	}
+
+	if(fb->zsbuf) {
+		if(!((struct nvfx_surface*)fb->zsbuf)->temp && !all_swizzled && !nvfx_surface_linear_renderable(fb->zsbuf))
+			nvfx_surface_create_temp(&nvfx->pipe, fb->zsbuf);
+	}
+
+	return all_swizzled;
+}
+
+void
+nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
+{
+	struct pipe_framebuffer_state *fb = &nvfx->framebuffer;
+	struct nouveau_channel *chan = nvfx->screen->base.channel;
+	uint32_t rt_enable, rt_format;
+	int i;
+	unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
+	unsigned w = fb->width;
+	unsigned h = fb->height;
+
+	rt_enable = (NV34TCL_RT_ENABLE_COLOR0 << fb->nr_cbufs) - 1;
 	if (rt_enable & (NV34TCL_RT_ENABLE_COLOR1 |
 			 NV40TCL_RT_ENABLE_COLOR2 | NV40TCL_RT_ENABLE_COLOR3))
 		rt_enable |= NV34TCL_RT_ENABLE_MRT;
 
+	nvfx->state.render_temps = 0;
+
+	for (i = 0; i < fb->nr_cbufs; i++)
+		nvfx->state.render_temps |= nvfx_surface_get_render_target(fb->cbufs[i], prepare_result, &nvfx->hw_rt[i]) << i;
+
+	for(; i < 4; ++i)
+		nvfx->hw_rt[i].bo = 0;
+
 	if (fb->zsbuf) {
-		zeta_format = fb->zsbuf->format;
-		nvfx->hw_zeta.bo = ((struct nvfx_miptree*)fb->zsbuf->texture)->base.bo;
-		nvfx->hw_zeta.offset = fb->zsbuf->offset;
-		nvfx->hw_zeta.pitch = ((struct nvfx_surface *)fb->zsbuf)->pitch;
-	}
-	else
-		nvfx->hw_zeta.bo = 0;
-
-	if (rt_enable & (NV34TCL_RT_ENABLE_COLOR0 | NV34TCL_RT_ENABLE_COLOR1 |
-		NV40TCL_RT_ENABLE_COLOR2 | NV40TCL_RT_ENABLE_COLOR3)) {
-		/* Render to at least a colour buffer */
-		if (!(fb->cbufs[0]->texture->flags & NVFX_RESOURCE_FLAG_LINEAR)) {
-			assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
-			for (i = 1; i < fb->nr_cbufs; i++)
-				assert(!(fb->cbufs[i]->texture->flags & NVFX_RESOURCE_FLAG_LINEAR));
-
-			rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
-				(log2i(fb->cbufs[0]->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
-				(log2i(fb->cbufs[0]->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
-		}
-		else
-			rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
-	} else if (fb->zsbuf) {
-		depth_only = 1;
-
-		/* Render to depth buffer only */
-		if (!(fb->zsbuf->texture->flags & NVFX_RESOURCE_FLAG_LINEAR)) {
-			assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
-
-			rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
-				(log2i(fb->zsbuf->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
-				(log2i(fb->zsbuf->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
-		}
-		else
-			rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
-	} else {
-		return;
+		nvfx->state.render_temps |= nvfx_surface_get_render_target(fb->zsbuf, prepare_result, &nvfx->hw_zeta) << 7;
+
+		assert(util_format_get_stride(fb->zsbuf->format, fb->width) <= nvfx->hw_zeta.pitch);
+		assert(nvfx->hw_zeta.offset + nvfx->hw_zeta.pitch * fb->height <= nvfx->hw_zeta.bo->size);
 	}
 
-	switch (colour_format) {
-	case PIPE_FORMAT_B8G8R8X8_UNORM:
-		rt_format |= NV34TCL_RT_FORMAT_COLOR_X8R8G8B8;
-		break;
-	case PIPE_FORMAT_B8G8R8A8_UNORM:
-	case 0:
-		rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
-		break;
-	case PIPE_FORMAT_B5G6R5_UNORM:
+	if (prepare_result) {
+		assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
+
+		rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
+			(log2i(fb->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
+			(log2i(fb->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
+	} else
+		rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
+
+	if(fb->nr_cbufs > 0) {
+		switch (fb->cbufs[0]->format) {
+		case PIPE_FORMAT_B8G8R8X8_UNORM:
+			rt_format |= NV34TCL_RT_FORMAT_COLOR_X8R8G8B8;
+			break;
+		case PIPE_FORMAT_B8G8R8A8_UNORM:
+		case 0:
+			rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
+			break;
+		case PIPE_FORMAT_B5G6R5_UNORM:
+			rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
+			break;
+		default:
+			assert(0);
+		}
+	} else if(fb->zsbuf && util_format_get_blocksize(fb->zsbuf->format) == 2)
 		rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
-		colour_bits = 16;
-		break;
-	default:
-		assert(0);
-	}
+	else
+		rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
 
-	switch (zeta_format) {
-	case PIPE_FORMAT_Z16_UNORM:
+	if(fb->zsbuf) {
+		switch (fb->zsbuf->format) {
+		case PIPE_FORMAT_Z16_UNORM:
+			rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
+			break;
+		case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
+		case PIPE_FORMAT_X8Z24_UNORM:
+		case 0:
+			rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
+			break;
+		default:
+			assert(0);
+		}
+	} else if(fb->nr_cbufs && util_format_get_blocksize(fb->cbufs[0]->format) == 2)
 		rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
-		zeta_bits = 16;
-		break;
-	case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-	case PIPE_FORMAT_X8Z24_UNORM:
-	case 0:
+	else
 		rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
-		break;
-	default:
-		assert(0);
-	}
 
-	if ((!nvfx->is_nv4x) && colour_bits > zeta_bits) {
-		/* TODO: does this limitation really exist?
-		   TODO: can it be worked around somehow? */
-		assert(0);
-	}
+	if ((rt_enable & NV34TCL_RT_ENABLE_COLOR0) || fb->zsbuf) {
+		struct nvfx_render_target *rt0 = &nvfx->hw_rt[0];
+		uint32_t pitch;
+
+		if(!(rt_enable & NV34TCL_RT_ENABLE_COLOR0))
+			rt0 = &nvfx->hw_zeta;
 
-	if ((rt_enable & NV34TCL_RT_ENABLE_COLOR0)
-		|| ((!nvfx->is_nv4x) && depth_only)) {
-		struct nvfx_render_target *rt0 = (depth_only ? &nvfx->hw_zeta : &nvfx->hw_rt[0]);
-		uint32_t pitch = rt0->pitch;
+		pitch = rt0->pitch;
 
 		if(!nvfx->is_nv4x)
 		{
-			if (nvfx->hw_zeta.bo) {
+			if (nvfx->hw_zeta.bo)
 				pitch |= (nvfx->hw_zeta.pitch << 16);
-			} else {
+			else
 				pitch |= (pitch << 16);
-			}
 		}
 
+		//printf("rendering to bo %p [%i] at offset %i with pitch %i\n", rt0->bo, rt0->bo->handle, rt0->offset, pitch);
+
 		OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 1));
 		OUT_RELOC(chan, rt0->bo, 0,
 			      rt_flags | NOUVEAU_BO_OR,
@@ -180,7 +239,7 @@ nvfx_state_framebuffer_validate(struct nvfx_context *nvfx)
 		}
 	}
 
-	if (zeta_format) {
+	if (fb->zsbuf) {
 		OUT_RING(chan, RING_3D(NV34TCL_DMA_ZETA, 1));
 		OUT_RELOC(chan, nvfx->hw_zeta.bo, 0,
 			      rt_flags | NOUVEAU_BO_OR,
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
index a97f342c64..8208c67f2a 100644
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ b/src/gallium/drivers/nvfx/nvfx_surface.c
@@ -94,23 +94,44 @@ nvfx_region_fixup_swizzled(struct nv04_region* rgn, unsigned zslice, unsigned wi
 }
 
 static INLINE void
-nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, unsigned x, unsigned y)
+nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, unsigned x, unsigned y, bool for_write)
 {
-	rgn->bo = ((struct nvfx_resource*)surf->base.texture)->bo;
-	rgn->offset = surf->base.offset;
-	rgn->pitch = surf->pitch;
 	rgn->x = x;
 	rgn->y = y;
 	rgn->z = 0;
+	nvfx_region_set_format(rgn, surf->base.base.format);
 
-	nvfx_region_set_format(rgn, surf->base.format);
-	if(!(surf->base.texture->flags & NVFX_RESOURCE_FLAG_LINEAR))
-		nvfx_region_fixup_swizzled(rgn, surf->base.zslice, surf->base.width, surf->base.height, u_minify(surf->base.texture->depth0, surf->base.level));
+	if(surf->temp)
+	{
+		rgn->bo = surf->temp->base.bo;
+		rgn->offset = 0;
+		rgn->pitch = surf->temp->linear_pitch;
+
+		if(for_write)
+			util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(&surf->base.base), &surf->base);
+	} else {
+		rgn->bo = ((struct nvfx_resource*)surf->base.base.texture)->bo;
+		rgn->offset = surf->base.base.offset;
+		rgn->pitch = surf->pitch;
+
+	        if(!(surf->base.base.texture->flags & NVFX_RESOURCE_FLAG_LINEAR))
+		        nvfx_region_fixup_swizzled(rgn, surf->base.base.zslice, surf->base.base.width, surf->base.base.height, u_minify(surf->base.base.texture->depth0, surf->base.base.level));
+	}
 }
 
 static INLINE void
-nvfx_region_init_for_subresource(struct nv04_region* rgn, struct pipe_resource* pt, struct pipe_subresource sub, unsigned x, unsigned y, unsigned z)
+nvfx_region_init_for_subresource(struct nv04_region* rgn, struct pipe_resource* pt, struct pipe_subresource sub, unsigned x, unsigned y, unsigned z, bool for_write)
 {
+	if(pt->target != PIPE_BUFFER)
+	{
+		struct nvfx_surface* ns = (struct nvfx_surface*)util_surfaces_peek(&((struct nvfx_miptree*)pt)->surfaces, pt, sub.face, sub.level, z);
+		if(ns && util_dirty_surface_is_dirty(&ns->base))
+		{
+			nvfx_region_init_for_surface(rgn, ns, x, y, for_write);
+			return;
+		}
+	}
+
 	rgn->bo = ((struct nvfx_resource*)pt)->bo;
 	rgn->offset = nvfx_subresource_offset(pt, sub.face, sub.level, z);
 	rgn->pitch = nvfx_subresource_pitch(pt, sub.level);
@@ -165,6 +186,7 @@ nv04_scaled_image_format(enum pipe_format format)
 	}
 }
 
+// XXX: must save index buffer too!
 static struct blitter_context*
 nvfx_get_blitter(struct pipe_context* pipe, int copy)
 {
@@ -237,8 +259,8 @@ nvfx_resource_copy_region(struct pipe_context *pipe,
 	int dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING;
 	int src_on_gpu = nvfx_resource_on_gpu(srcr);
 
-	nvfx_region_init_for_subresource(&dst, dstr, subdst, dstx, dsty, dstz);
-	nvfx_region_init_for_subresource(&src, srcr, subsrc, srcx, srcy, srcz);
+	nvfx_region_init_for_subresource(&dst, dstr, subdst, dstx, dsty, dstz, TRUE);
+	nvfx_region_init_for_subresource(&src, srcr, subsrc, srcx, srcy, srcz, FALSE);
 	w = util_format_get_stride(dstr->format, w) >> dst.bpps;
 	h = util_format_get_nblocksy(dstr->format, h);
 
@@ -293,10 +315,11 @@ nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts,
 	struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
 	struct nv04_region dst;
 	/* Always try to use the GPU right now, if possible
-	 * If the user wanted the surface data on the CPU, he would have cleared with memset */
+	 * If the user wanted the surface data on the CPU, he would have cleared with memset (hopefully) */
 
 	// we don't care about interior pixel order since we set all them to the same value
-	nvfx_region_init_for_surface(&dst, (struct nvfx_surface*)dsts, dx, dy);
+	nvfx_region_init_for_surface(&dst, (struct nvfx_surface*)dsts, dx, dy, TRUE);
+
 	w = util_format_get_stride(dsts->format, w) >> dst.bpps;
 	h = util_format_get_nblocksy(dsts->format, h);
 
@@ -341,6 +364,80 @@ nvfx_screen_surface_init(struct pipe_screen *pscreen)
 	return 0;
 }
 
+static void
+nvfx_surface_copy_temp(struct pipe_context* pipe, struct pipe_surface* surf, int to_temp)
+{
+	struct nvfx_surface* ns = (struct nvfx_surface*)surf;
+	struct pipe_subresource tempsr, surfsr;
+	struct pipe_resource *idxbuf_buffer;
+	unsigned idxbuf_format;
+
+	tempsr.face = 0;
+	tempsr.level = 0;
+	surfsr.face = surf->face;
+	surfsr.level = surf->level;
+
+	// TODO: do this properly, in blitter save
+	idxbuf_buffer = ((struct nvfx_context*)pipe)->idxbuf_buffer;
+	idxbuf_format = ((struct nvfx_context*)pipe)->idxbuf_format;
+
+	if(to_temp)
+		nvfx_resource_copy_region(pipe, &ns->temp->base.base, tempsr, 0, 0, 0, surf->texture, surfsr, 0, 0, surf->zslice, surf->width, surf->height);
+	else
+		nvfx_resource_copy_region(pipe, surf->texture, surfsr, 0, 0, surf->zslice, &ns->temp->base.base, tempsr, 0, 0, 0, surf->width, surf->height);
+
+	((struct nvfx_context*)pipe)->idxbuf_buffer = idxbuf_buffer;
+	((struct nvfx_context*)pipe)->idxbuf_format = idxbuf_format;
+}
+
+void
+nvfx_surface_create_temp(struct pipe_context* pipe, struct pipe_surface* surf)
+{
+	struct nvfx_surface* ns = (struct nvfx_surface*)surf;
+	struct pipe_resource template;
+	memset(&template, 0, sizeof(struct pipe_resource));
+	template.target = PIPE_TEXTURE_2D;
+	template.format = surf->format;
+	template.width0 = surf->width;
+	template.height0 = surf->height;
+	template.depth0 = 1;
+	template.nr_samples = surf->texture->nr_samples;
+	template.flags = NVFX_RESOURCE_FLAG_LINEAR;
+
+	ns->temp = (struct nvfx_miptree*)nvfx_miptree_create(pipe->screen, &template);
+	nvfx_surface_copy_temp(pipe, surf, 1);
+}
+
+void
+nvfx_surface_flush(struct pipe_context* pipe, struct pipe_surface* surf)
+{
+	struct nvfx_context* nvfx = (struct nvfx_context*)pipe;
+	struct nvfx_surface* ns = (struct nvfx_surface*)surf;
+	boolean bound = FALSE;
+
+	/* must be done before the copy, otherwise the copy will use the temp as destination */
+	util_dirty_surface_set_clean(nvfx_surface_get_dirty_surfaces(surf), &ns->base);
+
+	nvfx_surface_copy_temp(pipe, surf, 0);
+
+	if(nvfx->framebuffer.zsbuf == surf)
+		bound = TRUE;
+	else
+	{
+		for(unsigned i = 0; i < nvfx->framebuffer.nr_cbufs; ++i)
+		{
+			if(nvfx->framebuffer.cbufs[i] == surf)
+			{
+				bound = TRUE;
+				break;
+			}
+		}
+	}
+
+	if(!bound)
+		pipe_resource_reference((struct pipe_resource**)&ns->temp, 0);
+}
+
 static void
 nvfx_clear_render_target(struct pipe_context *pipe,
 			 struct pipe_surface *dst,
-- 
cgit v1.2.3


From 0481ed25c9c35178bf5151c80f4c36ad42b75648 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 18 Apr 2010 16:43:19 +0200
Subject: nvfx: new 2D: use a CPU copy for up to 4 pixels, up from 0

Seems a reasonable threshold for now.

Significantly speeds up Piglit's 1x1 glReadPixels (but, you know,
reading pixels in 1x1 blocks is NOT a good idea, especially if you
might be running on a less-than-perfect driver).
---
 src/gallium/drivers/nvfx/nvfx_surface.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
index 8208c67f2a..7efdd954b4 100644
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ b/src/gallium/drivers/nvfx/nvfx_surface.c
@@ -250,11 +250,7 @@ nvfx_resource_copy_region(struct pipe_context *pipe,
 
 	static int copy_threshold = -1;
 	if(copy_threshold < 0)
-	{
-		copy_threshold = debug_get_num_option("NOUVEAU_COPY_THRESHOLD", 0);
-		if(copy_threshold < 0)
-			copy_threshold = 0;
-	}
+		copy_threshold = debug_get_num_option("NOUVEAU_COPY_THRESHOLD", 4);
 
 	int dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING;
 	int src_on_gpu = nvfx_resource_on_gpu(srcr);
-- 
cgit v1.2.3


From 4e2080a86e0cbb93c72bbf4acace53867fac8276 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 3 Aug 2010 22:49:19 +0200
Subject: nvfx: new 2D: unify textures and buffers

Stop using the vtbl, and use real transfers for buffers too.
---
 src/gallium/drivers/nvfx/nvfx_buffer.c   | 77 +-------------------------------
 src/gallium/drivers/nvfx/nvfx_miptree.c  | 35 +--------------
 src/gallium/drivers/nvfx/nvfx_resource.c | 55 ++++++++++++++---------
 src/gallium/drivers/nvfx/nvfx_resource.h | 16 +++----
 4 files changed, 46 insertions(+), 137 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_buffer.c b/src/gallium/drivers/nvfx/nvfx_buffer.c
index 4482d9683e..44680e5195 100644
--- a/src/gallium/drivers/nvfx/nvfx_buffer.c
+++ b/src/gallium/drivers/nvfx/nvfx_buffer.c
@@ -7,13 +7,7 @@
 #include "nouveau/nouveau_winsys.h"
 #include "nvfx_resource.h"
 
-
-/* Currently using separate implementations for buffers and textures,
- * even though gallium has a unified abstraction of these objects.
- * Eventually these should be combined, and mechanisms like transfers
- * be adapted to work for both buffer and texture uploads.
- */
-static void nvfx_buffer_destroy(struct pipe_screen *pscreen,
+void nvfx_buffer_destroy(struct pipe_screen *pscreen,
 				struct pipe_resource *presource)
 {
 	struct nvfx_resource *buffer = nvfx_resource(presource);
@@ -22,70 +16,6 @@ static void nvfx_buffer_destroy(struct pipe_screen *pscreen,
 	FREE(buffer);
 }
 
-
-
-
-/* Utility functions for transfer create/destroy are hooked in and
- * just record the arguments to those functions.
- */
-static void *
-nvfx_buffer_transfer_map( struct pipe_context *pipe,
-			  struct pipe_transfer *transfer )
-{
-	struct nvfx_resource *buffer = nvfx_resource(transfer->resource);
-	uint8_t *map;
-
-	map = nouveau_screen_bo_map_range( pipe->screen,
-					   buffer->bo,
-					   transfer->box.x,
-					   transfer->box.width,
-					   nouveau_screen_transfer_flags(transfer->usage) );
-	if (map == NULL)
-		return NULL;
-	
-	return map + transfer->box.x;
-}
-
-
-
-static void nvfx_buffer_transfer_flush_region( struct pipe_context *pipe,
-					       struct pipe_transfer *transfer,
-					       const struct pipe_box *box)
-{
-	struct nvfx_resource *buffer = nvfx_resource(transfer->resource);
-
-	nouveau_screen_bo_map_flush_range(pipe->screen,
-					  buffer->bo,
-					  transfer->box.x + box->x,
-					  box->width);
-}
-
-static void nvfx_buffer_transfer_unmap( struct pipe_context *pipe,
-					struct pipe_transfer *transfer )
-{
-	struct nvfx_resource *buffer = nvfx_resource(transfer->resource);
-
-	nouveau_screen_bo_unmap(pipe->screen, buffer->bo);
-}
-
-
-
-
-struct u_resource_vtbl nvfx_buffer_vtbl = 
-{
-	u_default_resource_get_handle,      /* get_handle */
-	nvfx_buffer_destroy,		     /* resource_destroy */
-	NULL,			    /* is_resource_referenced */
-	u_default_get_transfer,	     /* get_transfer */
-	u_default_transfer_destroy,	     /* transfer_destroy */
-	nvfx_buffer_transfer_map,	     /* transfer_map */
-	nvfx_buffer_transfer_flush_region,  /* transfer_flush_region */
-	nvfx_buffer_transfer_unmap,	     /* transfer_unmap */
-	u_default_transfer_inline_write   /* transfer_inline_write */
-};
-
-
-
 struct pipe_resource *
 nvfx_buffer_create(struct pipe_screen *pscreen,
 		   const struct pipe_resource *template)
@@ -98,7 +28,6 @@ nvfx_buffer_create(struct pipe_screen *pscreen,
 
 	buffer->base = *template;
 	buffer->base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-	buffer->vtbl = &nvfx_buffer_vtbl;
 	pipe_reference_init(&buffer->base.reference, 1);
 	buffer->base.screen = pscreen;
 
@@ -132,7 +61,6 @@ nvfx_user_buffer_create(struct pipe_screen *pscreen,
 		return NULL;
 
 	pipe_reference_init(&buffer->base.reference, 1);
-	buffer->vtbl = &nvfx_buffer_vtbl;
 	buffer->base.flags = NVFX_RESOURCE_FLAG_LINEAR;
 	buffer->base.screen = pscreen;
 	buffer->base.format = PIPE_FORMAT_R8_UNORM;
@@ -145,11 +73,10 @@ nvfx_user_buffer_create(struct pipe_screen *pscreen,
 	buffer->bo = nouveau_screen_bo_user(pscreen, ptr, bytes);
 	if (!buffer->bo)
 		goto fail;
-	
+
 	return &buffer->base;
 
 fail:
 	FREE(buffer);
 	return NULL;
 }
-
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 530d705e13..559e832109 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -98,23 +98,6 @@ nvfx_miptree_layout(struct nvfx_miptree *mt)
 	return offset;
 }
 
-static boolean
-nvfx_miptree_get_handle(struct pipe_screen *pscreen,
-			struct pipe_resource *ptexture,
-			struct winsys_handle *whandle)
-{
-	struct nvfx_miptree* mt = (struct nvfx_miptree*)ptexture;
-
-	if (!mt || !mt->base.bo)
-		return FALSE;
-
-	return nouveau_screen_bo_get_handle(pscreen,
-					    mt->base.bo,
-					    mt->linear_pitch,
-					    whandle);
-}
-
-
 static void
 nvfx_miptree_surface_final_destroy(struct pipe_surface* ps)
 {
@@ -124,7 +107,7 @@ nvfx_miptree_surface_final_destroy(struct pipe_surface* ps)
 	FREE(ps);
 }
 
-static void
+void
 nvfx_miptree_destroy(struct pipe_screen *screen, struct pipe_resource *pt)
 {
 	struct nvfx_miptree *mt = (struct nvfx_miptree *)pt;
@@ -133,19 +116,6 @@ nvfx_miptree_destroy(struct pipe_screen *screen, struct pipe_resource *pt)
 	FREE(mt);
 }
 
-struct u_resource_vtbl nvfx_miptree_vtbl = 
-{
-   nvfx_miptree_get_handle,	      /* get_handle */
-   nvfx_miptree_destroy,	      /* resource_destroy */
-   NULL,			      /* is_resource_referenced */
-   nvfx_transfer_new,	  	      /* get_transfer */
-   util_staging_transfer_destroy,     /* transfer_destroy */
-   nvfx_transfer_map,		      /* transfer_map */
-   u_default_transfer_flush_region,   /* transfer_flush_region */
-   nvfx_transfer_unmap,	              /* transfer_unmap */
-   u_default_transfer_inline_write    /* transfer_inline_write */
-};
-
 static struct nvfx_miptree*
 nvfx_miptree_create_skeleton(struct pipe_screen *pscreen, const struct pipe_resource *pt)
 {
@@ -159,7 +129,6 @@ nvfx_miptree_create_skeleton(struct pipe_screen *pscreen, const struct pipe_reso
                 return NULL;
 
         mt->base.base = *pt;
-        mt->base.vtbl = &nvfx_miptree_vtbl;
         util_dirty_surfaces_init(&mt->dirty_surfaces);
 
         pipe_reference_init(&mt->base.base.reference, 1);
@@ -221,8 +190,6 @@ nvfx_miptree_from_handle(struct pipe_screen *pscreen, const struct pipe_resource
         return &mt->base.base;
 }
 
-/* Surface helpers, not strictly required to implement the resource vtbl:
- */
 struct pipe_surface *
 nvfx_miptree_surface_new(struct pipe_screen *pscreen, struct pipe_resource *pt,
 			 unsigned face, unsigned level, unsigned zslice,
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.c b/src/gallium/drivers/nvfx/nvfx_resource.c
index 10cdeed2a3..1c921b4710 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.c
+++ b/src/gallium/drivers/nvfx/nvfx_resource.c
@@ -1,23 +1,16 @@
 
 #include "pipe/p_context.h"
+#include "util/u_staging.h"
 #include "nvfx_resource.h"
+#include "nvfx_transfer.h"
 #include "nouveau/nouveau_screen.h"
 
-
-/* This doesn't look quite right - this query is supposed to ask
- * whether the particular context has references to the resource in
- * any unflushed rendering command buffer, and hence requires a
- * pipe->flush() for serializing some modification to that resource.
- *
- * This seems to be answering the question of whether the resource is
- * currently on hardware.
- */
 static unsigned int
 nvfx_resource_is_referenced(struct pipe_context *pipe,
-			    struct pipe_resource *resource,
+			    struct pipe_resource *pr,
 			    unsigned face, unsigned level)
 {
-	return nouveau_reference_flags(nvfx_resource(resource)->bo);
+	return !!nouveau_reference_flags(nvfx_resource(pr)->bo);
 }
 
 static struct pipe_resource *
@@ -30,6 +23,15 @@ nvfx_resource_create(struct pipe_screen *screen,
 		return nvfx_miptree_create(screen, template);
 }
 
+static void
+nvfx_resource_destroy(struct pipe_screen *screen, struct pipe_resource *pr)
+{
+	if (pr->target == PIPE_BUFFER)
+		return nvfx_buffer_destroy(screen, pr);
+	else
+		return nvfx_miptree_destroy(screen, pr);
+}
+
 static struct pipe_resource *
 nvfx_resource_from_handle(struct pipe_screen * screen,
 			  const struct pipe_resource *template,
@@ -41,15 +43,28 @@ nvfx_resource_from_handle(struct pipe_screen * screen,
 		return nvfx_miptree_from_handle(screen, template, whandle);
 }
 
+static boolean
+nvfx_resource_get_handle(struct pipe_screen *pscreen,
+                        struct pipe_resource *pr,
+                        struct winsys_handle *whandle)
+{
+	struct nvfx_resource* res = (struct nvfx_resource*)pr;
+
+	if (!res || !res->bo)
+		return FALSE;
+
+	return nouveau_screen_bo_get_handle(pscreen, res->bo, nvfx_subresource_pitch(pr, 0), whandle);
+}
+
 void
 nvfx_init_resource_functions(struct pipe_context *pipe)
 {
-	pipe->get_transfer = u_get_transfer_vtbl;
-	pipe->transfer_map = u_transfer_map_vtbl;
-	pipe->transfer_flush_region = u_transfer_flush_region_vtbl;
-	pipe->transfer_unmap = u_transfer_unmap_vtbl;
-	pipe->transfer_destroy = u_transfer_destroy_vtbl;
-	pipe->transfer_inline_write = u_transfer_inline_write_vtbl;
+	pipe->get_transfer = nvfx_transfer_new;
+	pipe->transfer_map = nvfx_transfer_map;
+	pipe->transfer_flush_region = u_default_transfer_flush_region;
+	pipe->transfer_unmap = nvfx_transfer_unmap;
+	pipe->transfer_destroy = util_staging_transfer_destroy;
+	pipe->transfer_inline_write = u_default_transfer_inline_write;
 	pipe->is_resource_referenced = nvfx_resource_is_referenced;
 }
 
@@ -58,10 +73,10 @@ nvfx_screen_init_resource_functions(struct pipe_screen *pscreen)
 {
 	pscreen->resource_create = nvfx_resource_create;
 	pscreen->resource_from_handle = nvfx_resource_from_handle;
-	pscreen->resource_get_handle = u_resource_get_handle_vtbl;
-	pscreen->resource_destroy = u_resource_destroy_vtbl;
+	pscreen->resource_get_handle = nvfx_resource_get_handle;
+	pscreen->resource_destroy = nvfx_resource_destroy;
 	pscreen->user_buffer_create = nvfx_user_buffer_create;
-   
+
 	pscreen->get_tex_surface = nvfx_miptree_surface_new;
 	pscreen->tex_surface_destroy = nvfx_miptree_surface_del;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
index be1845dd9c..ff86f6d9cb 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ b/src/gallium/drivers/nvfx/nvfx_resource.h
@@ -12,16 +12,8 @@
 struct pipe_resource;
 struct nv04_region;
 
-
-/* This gets further specialized into either buffer or texture
- * structures.  In the future we'll want to remove much of that
- * distinction, but for now try to keep as close to the existing code
- * as possible and use the vtbl struct to choose between the two
- * underlying implementations.
- */
 struct nvfx_resource {
 	struct pipe_resource base;
-	struct u_resource_vtbl *vtbl;
 	struct nouveau_bo *bo;
 };
 
@@ -105,6 +97,10 @@ nvfx_screen_init_resource_functions(struct pipe_screen *pscreen);
 struct pipe_resource *
 nvfx_miptree_create(struct pipe_screen *pscreen, const struct pipe_resource *pt);
 
+void
+nvfx_miptree_destroy(struct pipe_screen *pscreen,
+                     struct pipe_resource *presource);
+
 struct pipe_resource *
 nvfx_miptree_from_handle(struct pipe_screen *pscreen,
 			 const struct pipe_resource *template,
@@ -114,6 +110,10 @@ struct pipe_resource *
 nvfx_buffer_create(struct pipe_screen *pscreen,
 		   const struct pipe_resource *template);
 
+void
+nvfx_buffer_destroy(struct pipe_screen *pscreen,
+                    struct pipe_resource *presource);
+
 struct pipe_resource *
 nvfx_user_buffer_create(struct pipe_screen *screen,
 			void *ptr,
-- 
cgit v1.2.3


From 73b7c6fb336ad3e717f8e961f4e2df761e94cd2f Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 7 Aug 2010 03:47:25 +0200
Subject: nvfx: refactor sampling code, add support for swizzles and depth tex

This is a significant refactoring of the sampling code that:
- Moves all generic functions in nvfx_fragtex.c
- Adds a driver-specific sampler view structure and uses it to
  precompute texture setup as it should be done
- Unifies a bit more of code between nv30 and nv40
- Adds support for sampler view swizzles
- Support for specifying as sampler view format different from the
  resource one (only trivially)
- Support for sampler view specification of first and last level
- Support for depth textures on nv30, both for reading depth and
  for compare
- Support for sRGB textures
- Unifies the format table between nv30 and nv40
- Expands the format table to include essentially all supportable formats
  except mixed sign and "autonormal" formats
- Fixes the "is format supported" logic, which was quite broken, and
  makes it use the format table

Only tested on nv30 currently.
---
 src/gallium/drivers/nouveau/nouveau_class.h |   4 +
 src/gallium/drivers/nvfx/nv30_fragtex.c     | 174 +++++++---------
 src/gallium/drivers/nvfx/nv40_fragtex.c     | 166 ++++++----------
 src/gallium/drivers/nvfx/nvfx_context.c     |   1 +
 src/gallium/drivers/nvfx/nvfx_context.h     |  12 +-
 src/gallium/drivers/nvfx/nvfx_fragtex.c     | 295 ++++++++++++++++++++++++++++
 src/gallium/drivers/nvfx/nvfx_screen.c      |  64 +++---
 src/gallium/drivers/nvfx/nvfx_state.c       | 112 -----------
 src/gallium/drivers/nvfx/nvfx_tex.h         |  90 ++++++---
 9 files changed, 525 insertions(+), 393 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nouveau/nouveau_class.h b/src/gallium/drivers/nouveau/nouveau_class.h
index adfdd37b1b..685fa00b45 100644
--- a/src/gallium/drivers/nouveau/nouveau_class.h
+++ b/src/gallium/drivers/nouveau/nouveau_class.h
@@ -6328,6 +6328,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define    NV34TCL_TX_FORMAT_FORMAT_R8G8B8_RECT						0x00001e00
 #define    NV34TCL_TX_FORMAT_FORMAT_A8L8_RECT						0x00002000
 #define    NV34TCL_TX_FORMAT_FORMAT_DSDT8						0x00002800
+#define    NV34TCL_TX_FORMAT_FORMAT_Z24							0x2a00
+#define    NV34TCL_TX_FORMAT_FORMAT_Z24_RECT						0x2b00 /* XXX: guess! */
+#define    NV34TCL_TX_FORMAT_FORMAT_Z16							0x2c00
+#define    NV34TCL_TX_FORMAT_FORMAT_Z16_RECT						0x2d00 /* XXX: guess! */
 #define    NV34TCL_TX_FORMAT_FORMAT_HILO16						0x00003300
 #define    NV34TCL_TX_FORMAT_FORMAT_HILO16_RECT						0x00003600
 #define    NV34TCL_TX_FORMAT_FORMAT_HILO8						0x00004400
diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
index fbc69cf44a..63c578a0ce 100644
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv30_fragtex.c
@@ -10,88 +10,75 @@ nv30_sampler_state_init(struct pipe_context *pipe,
 			  struct nvfx_sampler_state *ps,
 			  const struct pipe_sampler_state *cso)
 {
-	if (cso->max_anisotropy >= 8) {
-		ps->en |= NV34TCL_TX_ENABLE_ANISO_8X;
-	} else
-	if (cso->max_anisotropy >= 4) {
-		ps->en |= NV34TCL_TX_ENABLE_ANISO_4X;
-	} else
-	if (cso->max_anisotropy >= 2) {
-		ps->en |= NV34TCL_TX_ENABLE_ANISO_2X;
-	}
+	float limit;
 
+	if (cso->max_anisotropy >= 2)
 	{
-		float limit;
+		if (cso->max_anisotropy >= 8)
+			ps->en |= NV34TCL_TX_ENABLE_ANISO_8X;
+		else if (cso->max_anisotropy >= 4)
+			ps->en |= NV34TCL_TX_ENABLE_ANISO_4X;
+		else if (cso->max_anisotropy >= 2)
+			ps->en |= NV34TCL_TX_ENABLE_ANISO_2X;
+	}
 
-		limit = CLAMP(cso->lod_bias, -16.0, 15.0);
-		ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
+	limit = CLAMP(cso->lod_bias, -16.0, 15.0);
+	ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
 
-		limit = CLAMP(cso->max_lod, 0.0, 15.0);
-		ps->en |= (int)(limit) << 14 /*NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT*/;
+	ps->max_lod = (int)CLAMP(cso->max_lod, 0.0, 15.0);
+	ps->min_lod = (int)CLAMP(cso->min_lod, 0.0, 15.0);
 
-		limit = CLAMP(cso->min_lod, 0.0, 15.0);
-		ps->en |= (int)(limit) << 26 /*NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT*/;
-	}
+	ps->en |= NV34TCL_TX_ENABLE_ENABLE;
 }
 
-#define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w)                        \
-[PIPE_FORMAT_##m] = {                                                                              \
-  NV34TCL_TX_FORMAT_FORMAT_##tf,                                               \
-  NV34TCL_TX_FORMAT_FORMAT_##tf##_RECT,                                               \
-  (NV34TCL_TX_SWIZZLE_S0_X_##ts0x | NV34TCL_TX_SWIZZLE_S0_Y_##ts0y |           \
-   NV34TCL_TX_SWIZZLE_S0_Z_##ts0z | NV34TCL_TX_SWIZZLE_S0_W_##ts0w |           \
-   NV34TCL_TX_SWIZZLE_S1_X_##ts1x | NV34TCL_TX_SWIZZLE_S1_Y_##ts1y |           \
-   NV34TCL_TX_SWIZZLE_S1_Z_##ts1z | NV34TCL_TX_SWIZZLE_S1_W_##ts1w)            \
-}
+void
+nv30_sampler_view_init(struct pipe_context *pipe,
+			  struct nvfx_sampler_view *sv)
+{
+	struct pipe_resource* pt = sv->base.texture;
+	struct nvfx_texture_format *tf = &nvfx_texture_formats[sv->base.format];
+	unsigned txf;
+	unsigned level = pt->target == PIPE_TEXTURE_CUBE ? 0 : sv->base.first_level;
+
+	assert(tf->fmt[0] >= 0);
+
+	txf = sv->u.init_fmt;
+	txf |= (level != sv->base.last_level ? NV34TCL_TX_FORMAT_MIPMAP : 0);
+	txf |= log2i(u_minify(pt->width0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT;
+	txf |= log2i(u_minify(pt->height0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT;
+	txf |= log2i(u_minify(pt->depth0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT;
+	txf |=  0x10000;
+
+	sv->u.nv30.fmt[0] = tf->fmt[0] | txf;
+	sv->u.nv30.fmt[1] = tf->fmt[1] | txf;
+	sv->u.nv30.fmt[2] = tf->fmt[2] | txf;
+	sv->u.nv30.fmt[3] = tf->fmt[3] | txf;
 
-struct nv30_texture_format {
-	int     format;
-	int     rect_format;
-	int     swizzle;
-};
-
-#define NV34TCL_TX_FORMAT_FORMAT_DXT1_RECT NV34TCL_TX_FORMAT_FORMAT_DXT1
-#define NV34TCL_TX_FORMAT_FORMAT_DXT3_RECT NV34TCL_TX_FORMAT_FORMAT_DXT3
-#define NV34TCL_TX_FORMAT_FORMAT_DXT5_RECT NV34TCL_TX_FORMAT_FORMAT_DXT5
-
-static struct nv30_texture_format
-nv30_texture_formats[PIPE_FORMAT_COUNT] = {
-	[0 ... PIPE_FORMAT_COUNT - 1] = {-1, 0, 0},
-	_(B8G8R8X8_UNORM, A8R8G8B8,   S1,   S1,   S1,  ONE, X, Y, Z, W),
-	_(B8G8R8A8_UNORM, A8R8G8B8,   S1,   S1,   S1,   S1, X, Y, Z, W),
-	_(B5G5R5A1_UNORM, A1R5G5B5,   S1,   S1,   S1,   S1, X, Y, Z, W),
-	_(B4G4R4A4_UNORM, A4R4G4B4,   S1,   S1,   S1,   S1, X, Y, Z, W),
-	_(B5G6R5_UNORM  , R5G6B5  ,   S1,   S1,   S1,  ONE, X, Y, Z, W),
-	_(L8_UNORM      , L8      ,   S1,   S1,   S1,  ONE, X, X, X, X),
-	_(A8_UNORM      , L8      , ZERO, ZERO, ZERO,   S1, X, X, X, X),
-	_(I8_UNORM      , L8      ,   S1,   S1,   S1,   S1, X, X, X, X),
-	_(L8A8_UNORM    , A8L8    ,   S1,   S1,   S1,   S1, X, X, X, Y),
-	_(Z16_UNORM     , R5G6B5  ,   S1,   S1,   S1,  ONE, X, X, X, X),
-	_(S8_USCALED_Z24_UNORM   , A8R8G8B8,   S1,   S1,   S1,  ONE, X, X, X, X),
-	_(DXT1_RGB      , DXT1    ,   S1,   S1,   S1,  ONE, X, Y, Z, W),
-	_(DXT1_RGBA     , DXT1    ,   S1,   S1,   S1,   S1, X, Y, Z, W),
-	_(DXT3_RGBA     , DXT3    ,   S1,   S1,   S1,   S1, X, Y, Z, W),
-	_(DXT5_RGBA     , DXT5    ,   S1,   S1,   S1,   S1, X, Y, Z, W),
-	{},
-};
+	sv->swizzle  |= (nvfx_subresource_pitch(pt, 0) << NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT);
+
+	if(pt->height0 <= 1 || util_format_is_compressed(sv->base.format))
+		sv->u.nv30.rect = -1;
+	else
+		sv->u.nv30.rect = !!(pt->flags & NVFX_RESOURCE_FLAG_LINEAR);
+
+	sv->lod_offset = sv->base.first_level - level;
+	sv->max_lod_limit = sv->base.last_level - level;
+}
 
 void
 nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 {
 	struct nvfx_sampler_state *ps = nvfx->tex_sampler[unit];
-	struct nvfx_miptree *mt = (struct nvfx_miptree *)nvfx->fragment_sampler_views[unit]->texture;
-	struct pipe_resource *pt = &mt->base.base;
-	struct nouveau_bo *bo = mt->base.bo;
-	struct nv30_texture_format *tf;
+	struct nvfx_sampler_view* sv = (struct nvfx_sampler_view*)nvfx->fragment_sampler_views[unit];
+	struct nouveau_bo *bo = ((struct nvfx_miptree *)sv->base.texture)->base.bo;
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	uint32_t txf, txs;
+	unsigned txf;
 	unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
 	unsigned use_rect;
+	unsigned max_lod = MIN2(ps->max_lod + sv->lod_offset, sv->max_lod_limit);
+	unsigned min_lod = MIN2(ps->min_lod + sv->lod_offset, max_lod) ;
 
-	tf = &nv30_texture_formats[pt->format];
-	assert(tf->format >= 0);
-
-	if(pt->height0 <= 1 || util_format_is_compressed(pt->format))
+	if(sv->u.nv30.rect < 0)
 	{
 		/* in the case of compressed or 1D textures, we can get away with this,
 		 * since the layout is the same
@@ -100,9 +87,9 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 	}
 	else
 	{
-		static int warned = 0;
-		if(!warned && !ps->fmt != !(pt->flags & NVFX_RESOURCE_FLAG_LINEAR)) {
-			warned = 1;
+		static boolean warned = FALSE;
+		if( !!ps->fmt != sv->u.nv30.rect && !warned) {
+			warned = TRUE;
 			fprintf(stderr,
 					"Unimplemented: coordinate normalization mismatch. Possible reasons:\n"
 					"1. ARB_texture_non_power_of_two is being used despite the fact it isn't supported\n"
@@ -110,51 +97,22 @@ nv30_fragtex_set(struct nvfx_context *nvfx, int unit)
 					"3. The state tracker is not supported\n");
 		}
 
-		use_rect  = pt->flags & NVFX_RESOURCE_FLAG_LINEAR;
-	}
-
-	txf = use_rect ? tf->rect_format : tf->format;
-	txf |= ((pt->last_level>0) ? NV34TCL_TX_FORMAT_MIPMAP : 0);
-	txf |= log2i(pt->width0) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT;
-	txf |= log2i(pt->height0) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT;
-	txf |= log2i(pt->depth0) << NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT;
-	txf |= NV34TCL_TX_FORMAT_NO_BORDER | 0x10000;
-
-	switch (pt->target) {
-	case PIPE_TEXTURE_CUBE:
-		txf |= NV34TCL_TX_FORMAT_CUBIC;
-		/* fall-through */
-	case PIPE_TEXTURE_2D:
-	case PIPE_TEXTURE_RECT:
-		txf |= NV34TCL_TX_FORMAT_DIMS_2D;
-		break;
-	case PIPE_TEXTURE_3D:
-		txf |= NV34TCL_TX_FORMAT_DIMS_3D;
-		break;
-	case PIPE_TEXTURE_1D:
-		txf |= NV34TCL_TX_FORMAT_DIMS_1D;
-		break;
-	default:
-		NOUVEAU_ERR("Unknown target %d\n", pt->target);
-		return;
+		use_rect  = sv->u.nv30.rect;
 	}
 
-	txs = tf->swizzle;
-
-	if(use_rect)
-		txs |= nvfx_subresource_pitch(&mt->base, 0) << NV34TCL_TX_SWIZZLE_RECT_PITCH_SHIFT;
+	txf = sv->u.nv30.fmt[ps->compare + (use_rect ? 2 : 0)];
 
 	MARK_RING(chan, 9, 2);
 	OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8));
-	OUT_RELOC(chan, bo, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0);
-	OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR,
-		      NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
-	OUT_RING(chan, ps->wrap);
-	OUT_RING(chan, NV34TCL_TX_ENABLE_ENABLE | ps->en);
-	OUT_RING(chan, txs);
-	OUT_RING(chan, ps->filt | 0x2000 /*voodoo*/);
-	OUT_RING(chan, (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) |
-		       pt->height0);
+	OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0);
+	OUT_RELOC(chan, bo, txf,
+		tex_flags | NOUVEAU_BO_OR,
+		NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
+	OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap);
+	OUT_RING(chan, ps->en | (min_lod << NV34TCL_TX_ENABLE_MIPMAP_MIN_LOD_SHIFT) | (max_lod << NV34TCL_TX_ENABLE_MIPMAP_MAX_LOD_SHIFT));
+	OUT_RING(chan, sv->swizzle);
+	OUT_RING(chan, ps->filt | sv->filt);
+	OUT_RING(chan, sv->npot_size);
 	OUT_RING(chan, ps->bcol);
 
 	nvfx->hw_txf[unit] = txf;
diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c
index 87aa7eb1a2..5fe742f260 100644
--- a/src/gallium/drivers/nvfx/nv40_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv40_fragtex.c
@@ -8,149 +8,97 @@ nv40_sampler_state_init(struct pipe_context *pipe,
 			  struct nvfx_sampler_state *ps,
 			  const struct pipe_sampler_state *cso)
 {
+	float limit;
 	if (cso->max_anisotropy >= 2) {
 		/* no idea, binary driver sets it, works without it.. meh.. */
 		ps->wrap |= (1 << 5);
 
-		if (cso->max_anisotropy >= 16) {
+		if (cso->max_anisotropy >= 16)
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_16X;
-		} else
-		if (cso->max_anisotropy >= 12) {
+		else if (cso->max_anisotropy >= 12)
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_12X;
-		} else
-		if (cso->max_anisotropy >= 10) {
+		else if (cso->max_anisotropy >= 10)
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_10X;
-		} else
-		if (cso->max_anisotropy >= 8) {
+		else if (cso->max_anisotropy >= 8)
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_8X;
-		} else
-		if (cso->max_anisotropy >= 6) {
+		else if (cso->max_anisotropy >= 6)
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_6X;
-		} else
-		if (cso->max_anisotropy >= 4) {
+		else if (cso->max_anisotropy >= 4)
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_4X;
-		} else {
+		else
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
-		}
 	}
 
-	{
-		float limit;
+	limit = CLAMP(cso->lod_bias, -16.0, 15.0);
+	ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
 
-		limit = CLAMP(cso->lod_bias, -16.0, 15.0);
-		ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
+	ps->max_lod = (int)(CLAMP(cso->max_lod, 0.0, 15.0) * 256.0);
+	ps->min_lod = (int)(CLAMP(cso->min_lod, 0.0, 15.0) * 256.0);
 
-		limit = CLAMP(cso->max_lod, 0.0, 15.0);
-		ps->en |= (int)(limit * 256.0) << 7;
+	ps->en |= NV40TCL_TEX_ENABLE_ENABLE;
+}
+
+void
+nv40_sampler_view_init(struct pipe_context *pipe,
+			  struct nvfx_sampler_view *sv)
+{
+	struct pipe_resource* pt = sv->base.texture;
+	struct nvfx_miptree* mt = (struct nvfx_miptree*)pt;
+	struct nvfx_texture_format *tf = &nvfx_texture_formats[sv->base.format];
+	unsigned txf;
+	unsigned level = pt->target == PIPE_TEXTURE_CUBE ? 0 : sv->base.first_level;
+	assert(tf->fmt[4] >= 0);
+
+	txf = sv->u.init_fmt;
+	txf |= 0x8000;
+	if(pt->target == PIPE_TEXTURE_CUBE)
+		txf |= ((pt->last_level + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
+	else
+		txf |= (((sv->base.last_level - sv->base.first_level) + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
 
-		limit = CLAMP(cso->min_lod, 0.0, 15.0);
-		ps->en |= (int)(limit * 256.0) << 19;
+	if (!mt->linear_pitch)
+		sv->u.nv40.npot_size2 = 0;
+	else {
+		sv->u.nv40.npot_size2  = mt->linear_pitch;
+		txf |= NV40TCL_TEX_FORMAT_LINEAR;
 	}
-}
 
-#define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sx,sy,sz,sw)            \
-[PIPE_FORMAT_##m] = {                                                                              \
-  NV40TCL_TEX_FORMAT_FORMAT_##tf,                                              \
-  (NV34TCL_TX_SWIZZLE_S0_X_##ts0x | NV34TCL_TX_SWIZZLE_S0_Y_##ts0y |         \
-   NV34TCL_TX_SWIZZLE_S0_Z_##ts0z | NV34TCL_TX_SWIZZLE_S0_W_##ts0w |         \
-   NV34TCL_TX_SWIZZLE_S1_X_##ts1x | NV34TCL_TX_SWIZZLE_S1_Y_##ts1y |         \
-   NV34TCL_TX_SWIZZLE_S1_Z_##ts1z | NV34TCL_TX_SWIZZLE_S1_W_##ts1w),         \
-  ((NV34TCL_TX_FILTER_SIGNED_RED*sx) | (NV34TCL_TX_FILTER_SIGNED_GREEN*sy) |       \
-   (NV34TCL_TX_FILTER_SIGNED_BLUE*sz) | (NV34TCL_TX_FILTER_SIGNED_ALPHA*sw))       \
-}
+	sv->u.nv40.fmt[0] = tf->fmt[4] | txf;
+	sv->u.nv40.fmt[1] = tf->fmt[5] | txf;
 
-struct nv40_texture_format {
-	int     format;
-	int     swizzle;
-	int     sign;
-};
+	sv->u.nv40.npot_size2 |= (u_minify(pt->depth0, level) << NV40TCL_TEX_SIZE1_DEPTH_SHIFT);
 
-static struct nv40_texture_format
-nv40_texture_formats[PIPE_FORMAT_COUNT] = {
-	[0 ... PIPE_FORMAT_COUNT - 1] = {-1, 0, 0},
-	_(B8G8R8X8_UNORM, A8R8G8B8,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0, 0, 0, 0),
-	_(B8G8R8A8_UNORM, A8R8G8B8,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(B5G5R5A1_UNORM, A1R5G5B5,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(B4G4R4A4_UNORM, A4R4G4B4,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(B5G6R5_UNORM  , R5G6B5  ,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0, 0, 0, 0),
-	_(L8_UNORM      , L8      ,   S1,   S1,   S1,  ONE, X, X, X, X, 0, 0, 0, 0),
-	_(A8_UNORM      , L8      , ZERO, ZERO, ZERO,   S1, X, X, X, X, 0, 0, 0, 0),
-	_(R16_SNORM     , A16     , ZERO, ZERO,   S1,  ONE, X, X, X, Y, 1, 1, 1, 1),
-	_(I8_UNORM      , L8      ,   S1,   S1,   S1,   S1, X, X, X, X, 0, 0, 0, 0),
-	_(L8A8_UNORM    , A8L8    ,   S1,   S1,   S1,   S1, X, X, X, Y, 0, 0, 0, 0),
-	_(Z16_UNORM     , Z16     ,   S1,   S1,   S1,  ONE, X, X, X, X, 0, 0, 0, 0),
-	_(S8_USCALED_Z24_UNORM   , Z24     ,   S1,   S1,   S1,  ONE, X, X, X, X, 0, 0, 0, 0),
-	_(DXT1_RGB      , DXT1    ,   S1,   S1,   S1,  ONE, X, Y, Z, W, 0, 0, 0, 0),
-	_(DXT1_RGBA     , DXT1    ,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(DXT3_RGBA     , DXT3    ,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	_(DXT5_RGBA     , DXT5    ,   S1,   S1,   S1,   S1, X, Y, Z, W, 0, 0, 0, 0),
-	{},
-};
+	sv->lod_offset = (sv->base.first_level - level) * 256;
+	sv->max_lod_limit = (sv->base.last_level - level) * 256;
+}
 
 void
 nv40_fragtex_set(struct nvfx_context *nvfx, int unit)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	struct nvfx_sampler_state *ps = nvfx->tex_sampler[unit];
-	struct nvfx_miptree *mt = (struct nvfx_miptree *)nvfx->fragment_sampler_views[unit]->texture;
-	struct nouveau_bo *bo = mt->base.bo;
-	struct pipe_resource *pt = &mt->base.base;
-	struct nv40_texture_format *tf;
-
-	uint32_t txf, txs, txp;
+	struct nvfx_sampler_view* sv = (struct nvfx_sampler_view*)nvfx->fragment_sampler_views[unit];
+	struct nouveau_bo *bo = ((struct nvfx_miptree *)sv->base.texture)->base.bo;
 	unsigned tex_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD;
+	unsigned txf;
+	unsigned max_lod = MIN2(ps->max_lod + sv->lod_offset, sv->max_lod_limit);
+	unsigned min_lod = MIN2(ps->min_lod + sv->lod_offset, max_lod);
 
-	tf = &nv40_texture_formats[pt->format];
-	assert(tf->format >= 0);
-
-	txf  = ps->fmt;
-	txf |= tf->format | 0x8000;
-	txf |= ((pt->last_level + 1) << NV40TCL_TEX_FORMAT_MIPMAP_COUNT_SHIFT);
-
-	if (1) /* XXX */
-		txf |= NV34TCL_TX_FORMAT_NO_BORDER;
-
-	switch (pt->target) {
-	case PIPE_TEXTURE_CUBE:
-		txf |= NV34TCL_TX_FORMAT_CUBIC;
-		/* fall-through */
-	case PIPE_TEXTURE_2D:
-	case PIPE_TEXTURE_RECT:
-		txf |= NV34TCL_TX_FORMAT_DIMS_2D;
-		break;
-	case PIPE_TEXTURE_3D:
-		txf |= NV34TCL_TX_FORMAT_DIMS_3D;
-		break;
-	case PIPE_TEXTURE_1D:
-		txf |= NV34TCL_TX_FORMAT_DIMS_1D;
-		break;
-	default:
-		NOUVEAU_ERR("Unknown target %d\n", pt->target);
-		return;
-	}
-
-	if (!mt->linear_pitch)
-		txp = 0;
-	else {
-		txp  = mt->linear_pitch;
-		txf |= NV40TCL_TEX_FORMAT_LINEAR;
-	}
-
-	txs = tf->swizzle;
+	txf = sv->u.nv40.fmt[ps->compare] | ps->fmt;
 
-	MARK_RING(chan, 11 + 2 * !unit, 2);
+	MARK_RING(chan, 11, 2);
 	OUT_RING(chan, RING_3D(NV34TCL_TX_OFFSET(unit), 8));
-	OUT_RELOC(chan, bo, 0, tex_flags | NOUVEAU_BO_LOW, 0, 0);
+	OUT_RELOC(chan, bo, sv->offset, tex_flags | NOUVEAU_BO_LOW, 0, 0);
 	OUT_RELOC(chan, bo, txf, tex_flags | NOUVEAU_BO_OR,
 			NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
-	OUT_RING(chan, ps->wrap);
-	OUT_RING(chan, NV40TCL_TEX_ENABLE_ENABLE | ps->en);
-	OUT_RING(chan, txs);
-	OUT_RING(chan, ps->filt | tf->sign | 0x2000 /*voodoo*/);
-	OUT_RING(chan, (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | pt->height0);
+	OUT_RING(chan, (ps->wrap & sv->wrap_mask) | sv->wrap);
+	OUT_RING(chan, ps->en | (min_lod << 19) | (max_lod << 7));
+	OUT_RING(chan, sv->swizzle);
+	OUT_RING(chan, ps->filt | sv->filt);
+	OUT_RING(chan, sv->npot_size);
 	OUT_RING(chan, ps->bcol);
 	OUT_RING(chan, RING_3D(NV40TCL_TEX_SIZE1(unit), 1));
-	OUT_RING(chan, (pt->depth0 << NV40TCL_TEX_SIZE1_DEPTH_SHIFT) | txp);
+	OUT_RING(chan, sv->u.nv40.npot_size2);
 
 	nvfx->hw_txf[unit] = txf;
 	nvfx->hw_samplers |= (1 << unit);
diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 7ab81de7dd..1980176b23 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -75,6 +75,7 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	nvfx_init_query_functions(nvfx);
 	nvfx_init_surface_functions(nvfx);
 	nvfx_init_state_functions(nvfx);
+	nvfx_init_sampling_functions(nvfx);
 	nvfx_init_resource_functions(&nvfx->pipe);
 
 	/* Create, configure, and install fallback swtnl path */
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index a6ea913967..bce19df044 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -201,15 +201,20 @@ extern void
 nvfx_fragprog_relocate(struct nvfx_context *nvfx);
 
 /* nvfx_fragtex.c */
+extern void nvfx_init_sampling_functions(struct nvfx_context *nvfx);
 extern void nvfx_fragtex_validate(struct nvfx_context *nvfx);
-extern void
-nvfx_fragtex_relocate(struct nvfx_context *nvfx);
+extern void nvfx_fragtex_relocate(struct nvfx_context *nvfx);
+
+struct nvfx_sampler_view;
 
 /* nv30_fragtex.c */
 extern void
 nv30_sampler_state_init(struct pipe_context *pipe,
 			  struct nvfx_sampler_state *ps,
 			  const struct pipe_sampler_state *cso);
+extern void
+nv30_sampler_view_init(struct pipe_context *pipe,
+			  struct nvfx_sampler_view *sv);
 extern void nv30_fragtex_set(struct nvfx_context *nvfx, int unit);
 
 /* nv40_fragtex.c */
@@ -217,6 +222,9 @@ extern void
 nv40_sampler_state_init(struct pipe_context *pipe,
 			  struct nvfx_sampler_state *ps,
 			  const struct pipe_sampler_state *cso);
+extern void
+nv40_sampler_view_init(struct pipe_context *pipe,
+			  struct nvfx_sampler_view *sv);
 extern void nv40_fragtex_set(struct nvfx_context *nvfx, int unit);
 
 /* nvfx_state.c */
diff --git a/src/gallium/drivers/nvfx/nvfx_fragtex.c b/src/gallium/drivers/nvfx/nvfx_fragtex.c
index 6605745433..00c47be76a 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragtex.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragtex.c
@@ -1,5 +1,177 @@
 #include "nvfx_context.h"
 #include "nvfx_resource.h"
+#include "nvfx_tex.h"
+
+static void *
+nvfx_sampler_state_create(struct pipe_context *pipe,
+			  const struct pipe_sampler_state *cso)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+	struct nvfx_sampler_state *ps;
+
+	ps = MALLOC(sizeof(struct nvfx_sampler_state));
+
+	/* on nv30, we use this as an internal flag */
+	ps->fmt = cso->normalized_coords ? 0 : NV40TCL_TEX_FORMAT_RECT;
+	ps->en = 0;
+	ps->filt = nvfx_tex_filter(cso) | 0x2000; /*voodoo*/
+	ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) |
+		    (nvfx_tex_wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) |
+		    (nvfx_tex_wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT);
+	ps->compare = FALSE;
+
+	if(cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE)
+	{
+		ps->wrap |= nvfx_tex_wrap_compare_mode(cso->compare_func);
+		ps->compare = TRUE;
+	}
+	ps->bcol = nvfx_tex_border_color(cso->border_color);
+
+	if(nvfx->is_nv4x)
+		nv40_sampler_state_init(pipe, ps, cso);
+	else
+		nv30_sampler_state_init(pipe, ps, cso);
+
+	return (void *)ps;
+}
+
+static void
+nvfx_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+	FREE(hwcso);
+}
+
+static void
+nvfx_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+	unsigned unit;
+
+	for (unit = 0; unit < nr; unit++) {
+		nvfx->tex_sampler[unit] = sampler[unit];
+		nvfx->dirty_samplers |= (1 << unit);
+	}
+
+	for (unit = nr; unit < nvfx->nr_samplers; unit++) {
+		nvfx->tex_sampler[unit] = NULL;
+		nvfx->dirty_samplers |= (1 << unit);
+	}
+
+	nvfx->nr_samplers = nr;
+	nvfx->dirty |= NVFX_NEW_SAMPLER;
+}
+
+static struct pipe_sampler_view *
+nvfx_create_sampler_view(struct pipe_context *pipe,
+			 struct pipe_resource *pt,
+			 const struct pipe_sampler_view *templ)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+	struct nvfx_sampler_view *sv = CALLOC_STRUCT(nvfx_sampler_view);
+	struct nvfx_texture_format *tf = &nvfx_texture_formats[templ->format];
+	unsigned txf;
+
+	if (!sv)
+		return NULL;
+
+	sv->base = *templ;
+	sv->base.reference.count = 1;
+	sv->base.texture = NULL;
+	pipe_resource_reference(&sv->base.texture, pt);
+	sv->base.context = pipe;
+
+	txf = NV34TCL_TX_FORMAT_NO_BORDER;
+
+	switch (pt->target) {
+	case PIPE_TEXTURE_CUBE:
+		txf |= NV34TCL_TX_FORMAT_CUBIC;
+		/* fall-through */
+	case PIPE_TEXTURE_2D:
+	case PIPE_TEXTURE_RECT:
+		txf |= NV34TCL_TX_FORMAT_DIMS_2D;
+		break;
+	case PIPE_TEXTURE_3D:
+		txf |= NV34TCL_TX_FORMAT_DIMS_3D;
+		break;
+	case PIPE_TEXTURE_1D:
+		txf |= NV34TCL_TX_FORMAT_DIMS_1D;
+		break;
+	default:
+		assert(0);
+	}
+	sv->u.init_fmt = txf;
+
+	sv->swizzle = 0
+			| (tf->src[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S0_Z_SHIFT)
+			| (tf->src[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S0_Y_SHIFT)
+			| (tf->src[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S0_X_SHIFT)
+			| (tf->src[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S0_W_SHIFT)
+			| (tf->comp[sv->base.swizzle_r] << NV34TCL_TX_SWIZZLE_S1_Z_SHIFT)
+			| (tf->comp[sv->base.swizzle_g] << NV34TCL_TX_SWIZZLE_S1_Y_SHIFT)
+			| (tf->comp[sv->base.swizzle_b] << NV34TCL_TX_SWIZZLE_S1_X_SHIFT)
+			| (tf->comp[sv->base.swizzle_a] << NV34TCL_TX_SWIZZLE_S1_W_SHIFT);
+
+	sv->filt = tf->sign;
+	sv->wrap = tf->wrap;
+	sv->wrap_mask = ~0;
+
+	if (pt->target == PIPE_TEXTURE_CUBE)
+	{
+		sv->offset = 0;
+		sv->npot_size = (pt->width0 << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | pt->height0;
+	}
+	else
+	{
+		sv->offset = nvfx_subresource_offset(pt, 0, sv->base.first_level, 0);
+		sv->npot_size = (u_minify(pt->width0, sv->base.first_level) << NV34TCL_TX_NPOT_SIZE_W_SHIFT) | u_minify(pt->height0, sv->base.first_level);
+
+		/* apparently, we need to ignore the t coordinate for 1D textures to fix piglit tex1d-2dborder */
+		if(pt->target == PIPE_TEXTURE_1D)
+		{
+			sv->wrap_mask &=~ NV34TCL_TX_WRAP_T_MASK;
+			sv->wrap |= NV34TCL_TX_WRAP_T_REPEAT;
+		}
+	}
+
+	if(nvfx->is_nv4x)
+		nv40_sampler_view_init(pipe, sv);
+	else
+		nv30_sampler_view_init(pipe, sv);
+
+	return &sv->base;
+}
+
+static void
+nvfx_sampler_view_destroy(struct pipe_context *pipe,
+			  struct pipe_sampler_view *view)
+{
+	pipe_resource_reference(&view->texture, NULL);
+	FREE(view);
+}
+
+static void
+nvfx_set_fragment_sampler_views(struct pipe_context *pipe,
+				unsigned nr,
+				struct pipe_sampler_view **views)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+	unsigned unit;
+
+	for (unit = 0; unit < nr; unit++) {
+		pipe_sampler_view_reference(&nvfx->fragment_sampler_views[unit],
+                                            views[unit]);
+		nvfx->dirty_samplers |= (1 << unit);
+	}
+
+	for (unit = nr; unit < nvfx->nr_textures; unit++) {
+		pipe_sampler_view_reference(&nvfx->fragment_sampler_views[unit],
+                                            NULL);
+		nvfx->dirty_samplers |= (1 << unit);
+	}
+
+	nvfx->nr_textures = nr;
+	nvfx->dirty |= NVFX_NEW_SAMPLER;
+}
 
 void
 nvfx_fragtex_validate(struct nvfx_context *nvfx)
@@ -60,3 +232,126 @@ nvfx_fragtex_relocate(struct nvfx_context *nvfx)
 				NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
 	}
 }
+
+void
+nvfx_init_sampling_functions(struct nvfx_context *nvfx)
+{
+	nvfx->pipe.create_sampler_state = nvfx_sampler_state_create;
+	nvfx->pipe.bind_fragment_sampler_states = nvfx_sampler_state_bind;
+	nvfx->pipe.delete_sampler_state = nvfx_sampler_state_delete;
+	nvfx->pipe.set_fragment_sampler_views = nvfx_set_fragment_sampler_views;
+	nvfx->pipe.create_sampler_view = nvfx_create_sampler_view;
+	nvfx->pipe.sampler_view_destroy = nvfx_sampler_view_destroy;
+}
+
+#define NV34TCL_TX_FORMAT_FORMAT_DXT1_RECT NV34TCL_TX_FORMAT_FORMAT_DXT1
+#define NV34TCL_TX_FORMAT_FORMAT_DXT3_RECT NV34TCL_TX_FORMAT_FORMAT_DXT3
+#define NV34TCL_TX_FORMAT_FORMAT_DXT5_RECT NV34TCL_TX_FORMAT_FORMAT_DXT5
+
+#define NV40TCL_TEX_FORMAT_FORMAT_HILO16 NV40TCL_TEX_FORMAT_FORMAT_A16L16
+
+#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F 0x00004a00
+#define NV34TCL_TX_FORMAT_FORMAT_RGBA16F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA16F
+#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F 0x00004b00
+#define NV34TCL_TX_FORMAT_FORMAT_RGBA32F_RECT NV34TCL_TX_FORMAT_FORMAT_RGBA32F
+#define NV34TCL_TX_FORMAT_FORMAT_R32F 0x00004c00
+#define NV34TCL_TX_FORMAT_FORMAT_R32F_RECT NV34TCL_TX_FORMAT_FORMAT_R32F
+
+// TODO: guess!
+#define NV40TCL_TEX_FORMAT_FORMAT_R32F 0x00001c00
+
+#define SRGB 0x00700000
+
+#define __(m,tf,tfc,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign,wrap) \
+[PIPE_FORMAT_##m] = { \
+  {NV34TCL_TX_FORMAT_FORMAT_##tf, \
+  NV34TCL_TX_FORMAT_FORMAT_##tfc, \
+  NV34TCL_TX_FORMAT_FORMAT_##tf##_RECT, \
+  NV34TCL_TX_FORMAT_FORMAT_##tfc##_RECT, \
+  NV40TCL_TEX_FORMAT_FORMAT_##tf, \
+  NV40TCL_TEX_FORMAT_FORMAT_##tfc}, \
+  sign, wrap, \
+  {ts0z, ts0y, ts0x, ts0w, 0, 1}, {ts1z, ts1y, ts1x, ts1w, 0, 0} \
+}
+
+#define _(m,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign, wrap) \
+	__(m,tf,tf,ts0x,ts0y,ts0z,ts0w,ts1x,ts1y,ts1z,ts1w,sign, wrap)
+
+/* Depth formats works by reading the depth value most significant 8/16 bits.
+ * We are losing precision, but nVidia loses even more by using A8R8G8B8 instead of HILO16
+ * There is no 32-bit integer texture support, so other things are infeasible.
+ *
+ * TODO: is it possible to read 16 bits for Z16? A16 doesn't seem to work, either due to normalization or endianness issues
+ */
+
+#define T 2
+
+#define X 3
+#define Y 2
+#define Z 1
+#define W 0
+
+#define SNORM ((NV34TCL_TX_FILTER_SIGNED_RED) | (NV34TCL_TX_FILTER_SIGNED_GREEN) | (NV34TCL_TX_FILTER_SIGNED_BLUE) | (NV34TCL_TX_FILTER_SIGNED_ALPHA))
+#define UNORM 0
+
+struct nvfx_texture_format
+nvfx_texture_formats[PIPE_FORMAT_COUNT] = {
+	[0 ... PIPE_FORMAT_COUNT - 1] = {{-1, -1, -1, -1, -1, -1}},
+	_(B8G8R8X8_UNORM,	A8R8G8B8,	T, T, T, 1, X, Y, Z, W, UNORM, 0),
+	_(B8G8R8X8_SRGB,	A8R8G8B8,	T, T, T, 1, X, Y, Z, W, UNORM, SRGB),
+	_(B8G8R8A8_UNORM,	A8R8G8B8,	T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(B8G8R8A8_SRGB,	A8R8G8B8,	T, T, T, T, X, Y, Z, W, UNORM, SRGB),
+
+	_(R8G8B8A8_UNORM,	A8R8G8B8,	T, T, T, T, Z, Y, X, W, UNORM, 0),
+	_(R8G8B8A8_SRGB,	A8R8G8B8,	T, T, T, T, Z, Y, X, W, UNORM, SRGB),
+	_(R8G8B8X8_UNORM,	A8R8G8B8,	T, T, T, 1, Z, Y, X, W, UNORM, 0),
+
+	_(A8R8G8B8_UNORM,	A8R8G8B8,	T, T, T, T, W, Z, Y, X, UNORM, 0),
+	_(A8R8G8B8_SRGB,	A8R8G8B8,	T, T, T, T, W, Z, Y, X, UNORM, SRGB),
+	_(A8B8G8R8_UNORM,	A8R8G8B8,	T, T, T, T, W, X, Y, Z, UNORM, 0),
+	_(A8B8G8R8_SRGB,	A8R8G8B8,	T, T, T, T, W, X, Y, Z, UNORM, SRGB),
+	_(X8R8G8B8_UNORM,	A8R8G8B8,	T, T, T, 1, W, Z, Y, X, UNORM, 0),
+	_(X8R8G8B8_SRGB,	A8R8G8B8,	T, T, T, 1, W, Z, Y, X, UNORM, SRGB),
+
+	_(B5G5R5A1_UNORM,	A1R5G5B5, 	T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(B5G5R5X1_UNORM,	A1R5G5B5, 	T, T, T, 1, X, Y, Z, W, UNORM, 0),
+
+	_(B4G4R4A4_UNORM,	A4R4G4B4, 	T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(B4G4R4X4_UNORM,	A4R4G4B4, 	T, T, T, 1, X, Y, Z, W, UNORM, 0),
+
+	_(B5G6R5_UNORM,		R5G6B5, 	T, T, T, 1, X, Y, Z, W, UNORM, 0),
+
+	_(R8_UNORM,		L8,		T, 0, 0, 1, X, X, X, X, UNORM, 0),
+	_(R8_SNORM,		L8,		T, 0, 0, 1, X, X, X, X, SNORM, 0),
+	_(L8_UNORM,		L8,		T, T, T, 1, X, X, X, X, UNORM, 0),
+	_(L8_SRGB,		L8,		T, T, T, 1, X, X, X, X, UNORM, SRGB),
+	_(A8_UNORM,		L8, 		0, 0, 0, T, X, X, X, X, UNORM, 0),
+	_(I8_UNORM,		L8, 		T, T, T, T, X, X, X, X, UNORM, 0),
+
+	_(R8G8_UNORM,		A8L8, 		T, T, T, T, X, X, X, W, UNORM, 0),
+	_(R8G8_SNORM,		A8L8, 		T, T, T, T, X, X, X, W, SNORM, 0),
+	_(L8A8_UNORM,		A8L8, 		T, T, T, T, X, X, X, W, UNORM, 0),
+	_(L8A8_SRGB,		A8L8,		T, T, T, T, X, X, X, W, UNORM, SRGB),
+
+	_(DXT1_RGB,		DXT1,		T, T, T, 1, X, Y, Z, W, UNORM, 0),
+	_(DXT1_SRGB,		DXT1,		T, T, T, 1, X, Y, Z, W, UNORM, SRGB),
+	_(DXT1_RGBA,		DXT1,		T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(DXT1_SRGBA,		DXT1,		T, T, T, T, X, Y, Z, W, UNORM, SRGB),
+	_(DXT3_RGBA,		DXT3,		T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(DXT3_SRGBA,		DXT3,		T, T, T, T, X, Y, Z, W, UNORM, SRGB),
+	_(DXT5_RGBA,		DXT5,		T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(DXT5_SRGBA,		DXT5,		T, T, T, T, X, Y, Z, W, UNORM, SRGB),
+
+	__(Z16_UNORM,		A8L8, Z16,	T, T, T, 1, W, W, W, W, UNORM, 0),
+	__(S8_USCALED_Z24_UNORM,HILO16,Z24,	T, T, T, 1, W, W, W, W, UNORM, 0),
+	__(X8Z24_UNORM,		HILO16,Z24,	T, T, T, 1, W, W, W, W, UNORM, 0),
+
+	_(R16_UNORM,		A16,		T, 0, 0, 1, X, X, X, X, UNORM, 0),
+	_(R16_SNORM,		A16,		T, 0, 0, 1, X, X, X, X, SNORM, 0),
+	_(R16G16_UNORM,		HILO16,		T, T, 0, 1, X, Y, X, X, UNORM, 0),
+	_(R16G16_SNORM,		HILO16,		T, T, 0, 1, X, Y, X, X, SNORM, 0),
+
+	_(R16G16B16A16_FLOAT,		RGBA16F,	T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(R32G32B32A32_FLOAT,		RGBA32F,	T, T, T, T, X, Y, Z, W, UNORM, 0),
+	_(R32_FLOAT,		R32F,	T, 0, 0, 1, X, X, X, X, UNORM, 0)
+};
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index a1b7c218f1..a1b8361a9a 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -8,6 +8,7 @@
 #include "nvfx_context.h"
 #include "nvfx_screen.h"
 #include "nvfx_resource.h"
+#include "nvfx_tex.h"
 
 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
@@ -179,58 +180,45 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 		case PIPE_FORMAT_B8G8R8A8_UNORM:
 		case PIPE_FORMAT_B8G8R8X8_UNORM:
 		case PIPE_FORMAT_B5G6R5_UNORM:
-			return TRUE;
-		default:
 			break;
+		default:
+			return FALSE;
 		}
-	} else
+	}
+
 	if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 		switch (format) {
 		case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 		case PIPE_FORMAT_X8Z24_UNORM:
-			return TRUE;
+			break;
 		case PIPE_FORMAT_Z16_UNORM:
 			/* TODO: this nv30 limitation probably does not exist */
-			if (!screen->is_nv4x && front)
-				return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
-			return TRUE;
-		default:
+			if (!screen->is_nv4x && front && front->format != PIPE_FORMAT_B5G6R5_UNORM)
+				return FALSE;
 			break;
+		default:
+			return FALSE;
 		}
-	} else {
-		if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
-			switch (format) {
-			case PIPE_FORMAT_DXT1_RGB:
-			case PIPE_FORMAT_DXT1_RGBA:
-			case PIPE_FORMAT_DXT3_RGBA:
-			case PIPE_FORMAT_DXT5_RGBA:
-				return util_format_s3tc_enabled;
-			default:
-				break;
-			}
+	}
+
+	if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
+		struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
+		if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
+			return FALSE;
+
+		if(screen->is_nv4x)
+		{
+			if(tf->fmt[4] < 0)
+				return FALSE;
 		}
-		switch (format) {
-		case PIPE_FORMAT_B8G8R8A8_UNORM:
-		case PIPE_FORMAT_B8G8R8X8_UNORM:
-		case PIPE_FORMAT_B5G5R5A1_UNORM:
-		case PIPE_FORMAT_B4G4R4A4_UNORM:
-		case PIPE_FORMAT_B5G6R5_UNORM:
-		case PIPE_FORMAT_L8_UNORM:
-		case PIPE_FORMAT_A8_UNORM:
-		case PIPE_FORMAT_I8_UNORM:
-		case PIPE_FORMAT_L8A8_UNORM:
-		case PIPE_FORMAT_Z16_UNORM:
-		case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
-			return TRUE;
-		/* TODO: does nv30 support this? */
-		case PIPE_FORMAT_R16_SNORM:
-			return !!screen->is_nv4x;
-		default:
-			break;
+		else
+		{
+			if(tf->fmt[0] < 0)
+				return FALSE;
 		}
 	}
 
-	return FALSE;
+	return TRUE;
 }
 
 static void
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index ab7bed0f93..d459f9a880 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -81,111 +81,6 @@ nvfx_blend_state_delete(struct pipe_context *pipe, void *hwcso)
 	FREE(bso);
 }
 
-static void *
-nvfx_sampler_state_create(struct pipe_context *pipe,
-			  const struct pipe_sampler_state *cso)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nvfx_sampler_state *ps;
-
-	ps = MALLOC(sizeof(struct nvfx_sampler_state));
-
-	/* on nv30, we use this as an internal flag */
-	ps->fmt = cso->normalized_coords ? 0 : NV40TCL_TEX_FORMAT_RECT;
-	ps->en = 0;
-	ps->filt = nvfx_tex_filter(cso);
-	ps->wrap = (nvfx_tex_wrap_mode(cso->wrap_s) << NV34TCL_TX_WRAP_S_SHIFT) |
-		    (nvfx_tex_wrap_mode(cso->wrap_t) << NV34TCL_TX_WRAP_T_SHIFT) |
-		    (nvfx_tex_wrap_mode(cso->wrap_r) << NV34TCL_TX_WRAP_R_SHIFT) |
-		    nvfx_tex_wrap_compare_mode(cso);
-	ps->bcol = nvfx_tex_border_color(cso->border_color);
-
-	if(nvfx->is_nv4x)
-		nv40_sampler_state_init(pipe, ps, cso);
-	else
-		nv30_sampler_state_init(pipe, ps, cso);
-
-	return (void *)ps;
-}
-
-static void
-nvfx_sampler_state_bind(struct pipe_context *pipe, unsigned nr, void **sampler)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	unsigned unit;
-
-	for (unit = 0; unit < nr; unit++) {
-		nvfx->tex_sampler[unit] = sampler[unit];
-		nvfx->dirty_samplers |= (1 << unit);
-	}
-
-	for (unit = nr; unit < nvfx->nr_samplers; unit++) {
-		nvfx->tex_sampler[unit] = NULL;
-		nvfx->dirty_samplers |= (1 << unit);
-	}
-
-	nvfx->nr_samplers = nr;
-	nvfx->dirty |= NVFX_NEW_SAMPLER;
-}
-
-static void
-nvfx_sampler_state_delete(struct pipe_context *pipe, void *hwcso)
-{
-	FREE(hwcso);
-}
-
-static void
-nvfx_set_fragment_sampler_views(struct pipe_context *pipe,
-				unsigned nr,
-				struct pipe_sampler_view **views)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	unsigned unit;
-
-	for (unit = 0; unit < nr; unit++) {
-		pipe_sampler_view_reference(&nvfx->fragment_sampler_views[unit],
-                                            views[unit]);
-		nvfx->dirty_samplers |= (1 << unit);
-	}
-
-	for (unit = nr; unit < nvfx->nr_textures; unit++) {
-		pipe_sampler_view_reference(&nvfx->fragment_sampler_views[unit],
-                                            NULL);
-		nvfx->dirty_samplers |= (1 << unit);
-	}
-
-	nvfx->nr_textures = nr;
-	nvfx->dirty |= NVFX_NEW_SAMPLER;
-}
-
-
-static struct pipe_sampler_view *
-nvfx_create_sampler_view(struct pipe_context *pipe,
-			 struct pipe_resource *texture,
-			 const struct pipe_sampler_view *templ)
-{
-	struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
-
-	if (view) {
-		*view = *templ;
-		view->reference.count = 1;
-		view->texture = NULL;
-		pipe_resource_reference(&view->texture, texture);
-		view->context = pipe;
-	}
-
-	return view;
-}
-
-
-static void
-nvfx_sampler_view_destroy(struct pipe_context *pipe,
-			  struct pipe_sampler_view *view)
-{
-	pipe_resource_reference(&view->texture, NULL);
-	FREE(view);
-}
-
 static void *
 nvfx_rasterizer_state_create(struct pipe_context *pipe,
 			     const struct pipe_rasterizer_state *cso)
@@ -630,13 +525,6 @@ nvfx_init_state_functions(struct nvfx_context *nvfx)
 	nvfx->pipe.bind_blend_state = nvfx_blend_state_bind;
 	nvfx->pipe.delete_blend_state = nvfx_blend_state_delete;
 
-	nvfx->pipe.create_sampler_state = nvfx_sampler_state_create;
-	nvfx->pipe.bind_fragment_sampler_states = nvfx_sampler_state_bind;
-	nvfx->pipe.delete_sampler_state = nvfx_sampler_state_delete;
-	nvfx->pipe.set_fragment_sampler_views = nvfx_set_fragment_sampler_views;
-        nvfx->pipe.create_sampler_view = nvfx_create_sampler_view;
-        nvfx->pipe.sampler_view_destroy = nvfx_sampler_view_destroy;
-
 	nvfx->pipe.create_rasterizer_state = nvfx_rasterizer_state_create;
 	nvfx->pipe.bind_rasterizer_state = nvfx_rasterizer_state_bind;
 	nvfx->pipe.delete_rasterizer_state = nvfx_rasterizer_state_delete;
diff --git a/src/gallium/drivers/nvfx/nvfx_tex.h b/src/gallium/drivers/nvfx/nvfx_tex.h
index 69187a79e7..34be936a89 100644
--- a/src/gallium/drivers/nvfx/nvfx_tex.h
+++ b/src/gallium/drivers/nvfx/nvfx_tex.h
@@ -1,6 +1,11 @@
 #ifndef NVFX_TEX_H_
 #define NVFX_TEX_H_
 
+#include "util/u_math.h"
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+#include <nouveau/nouveau_class.h>
+
 static inline unsigned
 nvfx_tex_wrap_mode(unsigned wrap) {
 	unsigned ret;
@@ -31,7 +36,7 @@ nvfx_tex_wrap_mode(unsigned wrap) {
 		ret = NV40TCL_TEX_WRAP_S_MIRROR_CLAMP;
 		break;
 	default:
-		NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
+		assert(0);
 		ret = NV34TCL_TX_WRAP_S_REPEAT;
 		break;
 	}
@@ -40,31 +45,29 @@ nvfx_tex_wrap_mode(unsigned wrap) {
 }
 
 static inline unsigned
-nvfx_tex_wrap_compare_mode(const struct pipe_sampler_state* cso)
+nvfx_tex_wrap_compare_mode(unsigned func)
 {
-	if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
-		switch (cso->compare_func) {
-		case PIPE_FUNC_NEVER:
-			return NV34TCL_TX_WRAP_RCOMP_NEVER;
-		case PIPE_FUNC_GREATER:
-			return NV34TCL_TX_WRAP_RCOMP_GREATER;
-		case PIPE_FUNC_EQUAL:
-			return NV34TCL_TX_WRAP_RCOMP_EQUAL;
-		case PIPE_FUNC_GEQUAL:
-			return NV34TCL_TX_WRAP_RCOMP_GEQUAL;
-		case PIPE_FUNC_LESS:
-			return NV34TCL_TX_WRAP_RCOMP_LESS;
-		case PIPE_FUNC_NOTEQUAL:
-			return NV34TCL_TX_WRAP_RCOMP_NOTEQUAL;
-		case PIPE_FUNC_LEQUAL:
-			return NV34TCL_TX_WRAP_RCOMP_LEQUAL;
-		case PIPE_FUNC_ALWAYS:
-			return NV34TCL_TX_WRAP_RCOMP_ALWAYS;
-		default:
-			break;
-		}
+	switch (func) {
+	case PIPE_FUNC_NEVER:
+		return NV34TCL_TX_WRAP_RCOMP_NEVER;
+	case PIPE_FUNC_GREATER:
+		return NV34TCL_TX_WRAP_RCOMP_GREATER;
+	case PIPE_FUNC_EQUAL:
+		return NV34TCL_TX_WRAP_RCOMP_EQUAL;
+	case PIPE_FUNC_GEQUAL:
+		return NV34TCL_TX_WRAP_RCOMP_GEQUAL;
+	case PIPE_FUNC_LESS:
+		return NV34TCL_TX_WRAP_RCOMP_LESS;
+	case PIPE_FUNC_NOTEQUAL:
+		return NV34TCL_TX_WRAP_RCOMP_NOTEQUAL;
+	case PIPE_FUNC_LEQUAL:
+		return NV34TCL_TX_WRAP_RCOMP_LEQUAL;
+	case PIPE_FUNC_ALWAYS:
+		return NV34TCL_TX_WRAP_RCOMP_ALWAYS;
+	default:
+		assert(0);
+		return 0;
 	}
-	return 0;
 }
 
 static inline unsigned nvfx_tex_filter(const struct pipe_sampler_state* cso)
@@ -128,6 +131,45 @@ struct nvfx_sampler_state {
 	uint32_t en;
 	uint32_t filt;
 	uint32_t bcol;
+	uint32_t min_lod;
+	uint32_t max_lod;
+	boolean compare;
+};
+
+struct nvfx_sampler_view {
+	struct pipe_sampler_view base;
+	int offset;
+	uint32_t swizzle;
+	uint32_t npot_size;
+	uint32_t filt;
+	uint32_t wrap_mask;
+	uint32_t wrap;
+	uint32_t lod_offset;
+	uint32_t max_lod_limit;
+	union
+	{
+		struct
+		{
+			uint32_t fmt[4]; /* nv30 has 4 entries, nv40 one */
+			int rect;
+		} nv30;
+		struct
+		{
+			uint32_t fmt[2]; /* nv30 has 4 entries, nv40 one */
+			uint32_t npot_size2; /* nv40 only */
+		} nv40;
+		uint32_t init_fmt;
+	} u;
 };
 
+struct nvfx_texture_format {
+	int fmt[6];
+	unsigned sign;
+	unsigned wrap;
+	unsigned char src[6];
+	unsigned char comp[6];
+};
+
+extern struct nvfx_texture_format nvfx_texture_formats[PIPE_FORMAT_COUNT];
+
 #endif /* NVFX_TEX_H_ */
-- 
cgit v1.2.3


From 8eb0fc430a8c1687627156a06faf5762144022f3 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 7 Aug 2010 05:39:18 +0200
Subject: nvfx: rewrite draw code and buffer code

This is a full rewrite of the drawing and buffer management logic.

It offers a lot of improvements:
1. A copy of buffers is now always kept in system memory. This is
   necessary to allow software processing of them, which is necessary
   or improves performance in many cases.
2. Support for pushing vertices on the FIFO, with index lookup if necessary.
3. "Smart" draw code that tries to intelligently choose the cheapest
  way to draw something: whether to use inline vertices or hardware
  vertex buffer, and whether to use hardware index buffers
4. Support for all vertex formats supported by the hardware
5. Usage of translate to push vertices, supporting all formats that are
   sensible to use as vertex formats
6. Support for base vertex
7. Usage of Ben Skeggs' primitive splitter originally for nv50, allowing
   correct splitting of line loops, triangle fans, etc.
8. Support for instancing
9. Precomputation using the vertex elements CSO

Thanks to Ben Skeggs for his primitive splitter originally for nv50.

Thanks to Christoph Bumiller for his nv50 push code, that was the basis
of this work, even though I changed his code dramatically, in particular
to replace his ad-hoc vertex data emitter with translate.

The changes could also go into nv50 too, but there are substantial
differences due to the additional nv50 hardware features.
---
 src/gallium/drivers/nouveau/nouveau_class.h |   12 +-
 src/gallium/drivers/nouveau/nouveau_util.h  |   91 ---
 src/gallium/drivers/nvfx/Makefile           |    1 +
 src/gallium/drivers/nvfx/nv30_fragtex.c     |    7 +-
 src/gallium/drivers/nvfx/nvfx_buffer.c      |   98 +--
 src/gallium/drivers/nvfx/nvfx_context.c     |    3 +
 src/gallium/drivers/nvfx/nvfx_context.h     |   99 ++-
 src/gallium/drivers/nvfx/nvfx_draw.c        |   59 +-
 src/gallium/drivers/nvfx/nvfx_fragprog.c    |    7 +-
 src/gallium/drivers/nvfx/nvfx_push.c        |  402 +++++++++++
 src/gallium/drivers/nvfx/nvfx_resource.c    |    6 -
 src/gallium/drivers/nvfx/nvfx_resource.h    |   91 ++-
 src/gallium/drivers/nvfx/nvfx_screen.c      |   33 +-
 src/gallium/drivers/nvfx/nvfx_screen.h      |   13 +
 src/gallium/drivers/nvfx/nvfx_state.c       |   84 ---
 src/gallium/drivers/nvfx/nvfx_state_emit.c  |   51 +-
 src/gallium/drivers/nvfx/nvfx_state_fb.c    |    5 +-
 src/gallium/drivers/nvfx/nvfx_surface.c     |   23 +-
 src/gallium/drivers/nvfx/nvfx_transfer.c    |  173 ++++-
 src/gallium/drivers/nvfx/nvfx_vbo.c         | 1016 +++++++++++++--------------
 src/gallium/drivers/nvfx/nvfx_vertprog.c    |   12 +-
 21 files changed, 1365 insertions(+), 921 deletions(-)
 delete mode 100644 src/gallium/drivers/nouveau/nouveau_util.h
 create mode 100644 src/gallium/drivers/nvfx/nvfx_push.c

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nouveau/nouveau_class.h b/src/gallium/drivers/nouveau/nouveau_class.h
index 685fa00b45..14c11b278a 100644
--- a/src/gallium/drivers/nouveau/nouveau_class.h
+++ b/src/gallium/drivers/nouveau/nouveau_class.h
@@ -6149,6 +6149,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define   NV34TCL_FP_REG_CONTROL_UNK1_MASK						0xffff0000
 #define   NV34TCL_FP_REG_CONTROL_UNK0_SHIFT						0
 #define   NV34TCL_FP_REG_CONTROL_UNK0_MASK						0x0000ffff
+#define  NV34TCL_EDGEFLAG_ENABLE							0x0000145c
 #define  NV34TCL_VP_CLIP_PLANES_ENABLE							0x00001478
 #define   NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0						(1 <<  1)
 #define   NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1						(1 <<  5)
@@ -6182,10 +6183,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define  NV34TCL_VTXFMT__SIZE								0x00000010
 #define   NV34TCL_VTXFMT_TYPE_SHIFT							0
 #define   NV34TCL_VTXFMT_TYPE_MASK							0x0000000f
-#define    NV34TCL_VTXFMT_TYPE_FLOAT							0x00000002
-#define    NV34TCL_VTXFMT_TYPE_HALF							0x00000003
-#define    NV34TCL_VTXFMT_TYPE_UBYTE							0x00000004
-#define    NV34TCL_VTXFMT_TYPE_USHORT							0x00000005
+#define    NV34TCL_VTXFMT_TYPE_16_SNORM							0x00000001
+#define    NV34TCL_VTXFMT_TYPE_32_FLOAT							0x00000002
+#define    NV34TCL_VTXFMT_TYPE_16_FLOAT							0x00000003
+#define    NV34TCL_VTXFMT_TYPE_8_UNORM							0x00000004
+#define    NV34TCL_VTXFMT_TYPE_16_SSCALED							0x00000005
+#define    NV34TCL_VTXFMT_TYPE_11_11_10_SNORM							0x00000006
+#define    NV34TCL_VTXFMT_TYPE_8_USCALED							0x00000007
 #define   NV34TCL_VTXFMT_SIZE_SHIFT							4
 #define   NV34TCL_VTXFMT_SIZE_MASK							0x000000f0
 #define   NV34TCL_VTXFMT_STRIDE_SHIFT							8
diff --git a/src/gallium/drivers/nouveau/nouveau_util.h b/src/gallium/drivers/nouveau/nouveau_util.h
deleted file mode 100644
index b165f7a611..0000000000
--- a/src/gallium/drivers/nouveau/nouveau_util.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef __NOUVEAU_UTIL_H__
-#define __NOUVEAU_UTIL_H__
-
-/* Determine how many vertices can be pushed into the command stream.
- * Where the remaining space isn't large enough to represent all verices,
- * split the buffer at primitive boundaries.
- *
- * Returns a count of vertices that can be rendered, and an index to
- * restart drawing at after a flush.
- */
-static INLINE unsigned
-nouveau_vbuf_split(unsigned remaining, unsigned overhead, unsigned vpp,
-		   unsigned mode, unsigned start, unsigned count,
-		   unsigned *restart)
-{
-	int max, adj = 0;
-
-	max  = remaining - overhead;
-	if (max < 0)
-		return 0;
-
-	max *= vpp;
-	if (max >= count)
-		return count;
-
-	switch (mode) {
-	case PIPE_PRIM_POINTS:
-		break;
-	case PIPE_PRIM_LINES:
-		max = max & 1;
-		break;
-	case PIPE_PRIM_TRIANGLES:
-		max = max - (max % 3);
-		break;
-	case PIPE_PRIM_QUADS:
-		max = max & ~3;
-		break;
-	case PIPE_PRIM_LINE_LOOP:
-	case PIPE_PRIM_LINE_STRIP:
-		if (max < 2)
-			max = 0;
-		adj = 1;
-		break;
-	case PIPE_PRIM_POLYGON:
-	case PIPE_PRIM_TRIANGLE_STRIP:
-	case PIPE_PRIM_TRIANGLE_FAN:
-		if (max < 3)
-			max = 0;
-		adj = 2;
-		break;
-	case PIPE_PRIM_QUAD_STRIP:
-		if (max < 4)
-			max = 0;
-		adj = 3;
-		break;
-	default:
-		assert(0);
-	}
-
-	*restart = start + max - adj;
-	return max;
-}
-
-/* Integer base-2 logarithm, rounded towards zero. */
-static INLINE unsigned log2i(unsigned i)
-{
-	unsigned r = 0;
-
-	if (i & 0xffff0000) {
-		i >>= 16;
-		r += 16;
-	}
-	if (i & 0x0000ff00) {
-		i >>= 8;
-		r += 8;
-	}
-	if (i & 0x000000f0) {
-		i >>= 4;
-		r += 4;
-	}
-	if (i & 0x0000000c) {
-		i >>= 2;
-		r += 2;
-	}
-	if (i & 0x00000002) {
-		r += 1;
-	}
-	return r;
-}
-
-#endif
diff --git a/src/gallium/drivers/nvfx/Makefile b/src/gallium/drivers/nvfx/Makefile
index 2834f8984c..6cbbad699e 100644
--- a/src/gallium/drivers/nvfx/Makefile
+++ b/src/gallium/drivers/nvfx/Makefile
@@ -14,6 +14,7 @@ C_SOURCES = \
 	nv30_fragtex.c \
 	nv40_fragtex.c \
 	nvfx_miptree.c \
+	nvfx_push.c \
 	nvfx_query.c \
 	nvfx_resource.c \
 	nvfx_screen.c \
diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
index 63c578a0ce..db8a8fc4b0 100644
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv30_fragtex.c
@@ -1,7 +1,6 @@
 #include "util/u_format.h"
 
 #include "nvfx_context.h"
-#include "nouveau/nouveau_util.h"
 #include "nvfx_tex.h"
 #include "nvfx_resource.h"
 
@@ -44,9 +43,9 @@ nv30_sampler_view_init(struct pipe_context *pipe,
 
 	txf = sv->u.init_fmt;
 	txf |= (level != sv->base.last_level ? NV34TCL_TX_FORMAT_MIPMAP : 0);
-	txf |= log2i(u_minify(pt->width0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT;
-	txf |= log2i(u_minify(pt->height0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT;
-	txf |= log2i(u_minify(pt->depth0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT;
+	txf |= util_logbase2(u_minify(pt->width0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_U_SHIFT;
+	txf |= util_logbase2(u_minify(pt->height0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_V_SHIFT;
+	txf |= util_logbase2(u_minify(pt->depth0, level)) << NV34TCL_TX_FORMAT_BASE_SIZE_W_SHIFT;
 	txf |=  0x10000;
 
 	sv->u.nv30.fmt[0] = tf->fmt[0] | txf;
diff --git a/src/gallium/drivers/nvfx/nvfx_buffer.c b/src/gallium/drivers/nvfx/nvfx_buffer.c
index 44680e5195..89bb8570ef 100644
--- a/src/gallium/drivers/nvfx/nvfx_buffer.c
+++ b/src/gallium/drivers/nvfx/nvfx_buffer.c
@@ -6,13 +6,16 @@
 #include "nouveau/nouveau_screen.h"
 #include "nouveau/nouveau_winsys.h"
 #include "nvfx_resource.h"
+#include "nvfx_screen.h"
 
 void nvfx_buffer_destroy(struct pipe_screen *pscreen,
 				struct pipe_resource *presource)
 {
-	struct nvfx_resource *buffer = nvfx_resource(presource);
+	struct nvfx_buffer *buffer = nvfx_buffer(presource);
 
-	nouveau_screen_bo_release(pscreen, buffer->bo);
+	if(!(buffer->base.base.flags & NVFX_RESOURCE_FLAG_USER))
+		align_free(buffer->data);
+	nouveau_screen_bo_release(pscreen, buffer->base.bo);
 	FREE(buffer);
 }
 
@@ -20,31 +23,22 @@ struct pipe_resource *
 nvfx_buffer_create(struct pipe_screen *pscreen,
 		   const struct pipe_resource *template)
 {
-	struct nvfx_resource *buffer;
+	struct nvfx_screen* screen = nvfx_screen(pscreen);
+	struct nvfx_buffer* buffer;
 
-	buffer = CALLOC_STRUCT(nvfx_resource);
+	buffer = CALLOC_STRUCT(nvfx_buffer);
 	if (!buffer)
 		return NULL;
 
-	buffer->base = *template;
-	buffer->base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
-	pipe_reference_init(&buffer->base.reference, 1);
-	buffer->base.screen = pscreen;
+	buffer->base.base = *template;
+	buffer->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
+	pipe_reference_init(&buffer->base.base.reference, 1);
+	buffer->base.base.screen = pscreen;
+	buffer->size = util_format_get_stride(template->format, template->width0);
+	buffer->bytes_to_draw_until_static = buffer->size * screen->static_reuse_threshold;
+	buffer->data = align_malloc(buffer->size, 16);
 
-	buffer->bo = nouveau_screen_bo_new(pscreen,
-					   16,
-					   buffer->base.usage,
-					   buffer->base.bind,
-					   buffer->base.width0);
-
-	if (buffer->bo == NULL)
-		goto fail;
-
-	return &buffer->base;
-
-fail:
-	FREE(buffer);
-	return NULL;
+	return &buffer->base.base;
 }
 
 
@@ -54,29 +48,49 @@ nvfx_user_buffer_create(struct pipe_screen *pscreen,
 			unsigned bytes,
 			unsigned usage)
 {
-	struct nvfx_resource *buffer;
+	struct nvfx_screen* screen = nvfx_screen(pscreen);
+	struct nvfx_buffer* buffer;
 
-	buffer = CALLOC_STRUCT(nvfx_resource);
+	buffer = CALLOC_STRUCT(nvfx_buffer);
 	if (!buffer)
 		return NULL;
 
-	pipe_reference_init(&buffer->base.reference, 1);
-	buffer->base.flags = NVFX_RESOURCE_FLAG_LINEAR;
-	buffer->base.screen = pscreen;
-	buffer->base.format = PIPE_FORMAT_R8_UNORM;
-	buffer->base.usage = PIPE_USAGE_IMMUTABLE;
-	buffer->base.bind = usage;
-	buffer->base.width0 = bytes;
-	buffer->base.height0 = 1;
-	buffer->base.depth0 = 1;
-
-	buffer->bo = nouveau_screen_bo_user(pscreen, ptr, bytes);
-	if (!buffer->bo)
-		goto fail;
-
-	return &buffer->base;
+	pipe_reference_init(&buffer->base.base.reference, 1);
+	buffer->base.base.flags = NVFX_RESOURCE_FLAG_LINEAR | NVFX_RESOURCE_FLAG_USER;
+	buffer->base.base.screen = pscreen;
+	buffer->base.base.format = PIPE_FORMAT_R8_UNORM;
+	buffer->base.base.usage = PIPE_USAGE_IMMUTABLE;
+	buffer->base.base.bind = usage;
+	buffer->base.base.width0 = bytes;
+	buffer->base.base.height0 = 1;
+	buffer->base.base.depth0 = 1;
+	buffer->data = ptr;
+	buffer->size = bytes;
+	buffer->bytes_to_draw_until_static = bytes * screen->static_reuse_threshold;
+	buffer->dirty_end = bytes;
+
+	return &buffer->base.base;
+}
 
-fail:
-	FREE(buffer);
-	return NULL;
+void nvfx_buffer_upload(struct nvfx_buffer* buffer)
+{
+	unsigned dirty = buffer->dirty_end - buffer->dirty_begin;
+	if(!buffer->base.bo)
+	{
+		buffer->base.bo = nouveau_screen_bo_new(buffer->base.base.screen,
+					   16,
+					   buffer->base.base.usage,
+					   buffer->base.base.bind,
+					   buffer->base.base.width0);
+	}
+
+	if(dirty)
+	{
+		// TODO: may want to use a temporary in some cases
+		nouveau_bo_map(buffer->base.bo, NOUVEAU_BO_WR
+				| (buffer->dirty_unsynchronized ? NOUVEAU_BO_NOSYNC : 0));
+		memcpy(buffer->base.bo->map + buffer->dirty_begin, buffer->data + buffer->dirty_begin, dirty);
+		nouveau_bo_unmap(buffer->base.bo);
+		buffer->dirty_begin = buffer->dirty_end = 0;
+	}
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 1980176b23..94c854b22b 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -76,7 +76,9 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	nvfx_init_surface_functions(nvfx);
 	nvfx_init_state_functions(nvfx);
 	nvfx_init_sampling_functions(nvfx);
+	nvfx_init_vbo_functions(nvfx);
 	nvfx_init_resource_functions(&nvfx->pipe);
+	nvfx_init_transfer_functions(&nvfx->pipe);
 
 	/* Create, configure, and install fallback swtnl path */
 	nvfx->draw = draw_create(&nvfx->pipe);
@@ -89,6 +91,7 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	/* set these to that we init them on first validation */
 	nvfx->state.scissor_enabled = ~0;
 	nvfx->state.stipple_enabled = ~0;
+	nvfx->use_vertex_buffers = -1;
 
 	LIST_INITHEAD(&nvfx->render_cache);
 
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index bce19df044..8899bf991e 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -44,6 +44,7 @@
 #define NVFX_NEW_SR		(1 << 13)
 #define NVFX_NEW_VERTCONST	(1 << 14)
 #define NVFX_NEW_FRAGCONST	(1 << 15)
+#define NVFX_NEW_INDEX	(1 << 16)
 
 struct nvfx_rasterizer_state {
 	struct pipe_rasterizer_state pipe;
@@ -71,9 +72,53 @@ struct nvfx_state {
 	unsigned render_temps;
 };
 
+struct nvfx_per_vertex_element {
+	unsigned idx;
+        unsigned vertex_buffer_index;
+        unsigned src_offset;
+};
+
+struct nvfx_low_frequency_element {
+	unsigned idx;
+	unsigned vertex_buffer_index;
+	unsigned src_offset;
+        void (*fetch_rgba_float)(float *dst, const uint8_t *src, unsigned i, unsigned j);
+        unsigned ncomp;
+};
+
+struct nvfx_per_instance_element {
+	struct nvfx_low_frequency_element base;
+	unsigned instance_divisor;
+};
+
+struct nvfx_per_vertex_buffer_info
+{
+	unsigned vertex_buffer_index;
+	unsigned per_vertex_size;
+};
+
 struct nvfx_vtxelt_state {
 	struct pipe_vertex_element pipe[16];
 	unsigned num_elements;
+	unsigned vtxfmt[16];
+
+	unsigned num_per_vertex_buffer_infos;
+	struct nvfx_per_vertex_buffer_info per_vertex_buffer_info[16];
+
+	unsigned num_per_vertex;
+	struct nvfx_per_vertex_element per_vertex[16];
+
+	unsigned num_per_instance;
+	struct nvfx_per_instance_element per_instance[16];
+
+	unsigned num_constant;
+	struct nvfx_low_frequency_element constant[16];
+
+	boolean needs_translate;
+	struct translate* translate;
+
+	unsigned vertex_length;
+	unsigned max_vertices_per_packet;
 };
 
 struct nvfx_render_target {
@@ -127,8 +172,6 @@ struct nvfx_context {
 	struct pipe_viewport_state viewport;
 	struct pipe_framebuffer_state framebuffer;
 	struct pipe_index_buffer idxbuf;
-	struct pipe_resource *idxbuf_buffer;
-	unsigned idxbuf_format;
 	struct nvfx_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
 	struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS];
 	unsigned nr_samplers;
@@ -137,8 +180,14 @@ struct nvfx_context {
 	struct pipe_vertex_buffer vtxbuf[PIPE_MAX_ATTRIBS];
 	unsigned vtxbuf_nr;
 	struct nvfx_vtxelt_state *vtxelt;
+	int base_vertex;
+	boolean use_index_buffer;
+	/* -1 = hardware input setup is outdated
+	 * 0 = hardware input setup is for inline vertices
+	 * 1 = hardware input setup is for hardware vertices
+	 */
+	int use_vertex_buffers;
 
-	unsigned vbo_bo;
 	unsigned hw_vtxelt_nr;
 	uint8_t hw_samplers;
 	uint32_t hw_txf[8];
@@ -180,11 +229,7 @@ extern void nvfx_clear(struct pipe_context *pipe, unsigned buffers,
 
 /* nvfx_draw.c */
 extern struct draw_stage *nvfx_draw_render_stage(struct nvfx_context *nvfx);
-extern void nvfx_draw_elements_swtnl(struct pipe_context *pipe,
-                                     struct pipe_resource *idxbuf,
-                                     unsigned ib_size, int ib_bias,
-                                     unsigned mode,
-                                     unsigned start, unsigned count);
+extern void nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info);
 extern void nvfx_vtxfmt_validate(struct nvfx_context *nvfx);
 
 /* nvfx_fb.c */
@@ -245,17 +290,53 @@ extern boolean nvfx_state_validate_swtnl(struct nvfx_context *nvfx);
 extern void nvfx_state_emit(struct nvfx_context *nvfx);
 
 /* nvfx_transfer.c */
-extern void nvfx_init_transfer_functions(struct nvfx_context *nvfx);
+extern void nvfx_init_transfer_functions(struct pipe_context *pipe);
 
 /* nvfx_vbo.c */
 extern boolean nvfx_vbo_validate(struct nvfx_context *nvfx);
 extern void nvfx_vbo_relocate(struct nvfx_context *nvfx);
+extern void nvfx_idxbuf_validate(struct nvfx_context* nvfx);
+extern void nvfx_idxbuf_relocate(struct nvfx_context* nvfx);
 extern void nvfx_draw_vbo(struct pipe_context *pipe,
                           const struct pipe_draw_info *info);
+extern void nvfx_init_vbo_functions(struct nvfx_context *nvfx);
+extern unsigned nvfx_vertex_formats[];
 
 /* nvfx_vertprog.c */
 extern boolean nvfx_vertprog_validate(struct nvfx_context *nvfx);
 extern void nvfx_vertprog_destroy(struct nvfx_context *,
 				  struct nvfx_vertex_program *);
 
+/* nvfx_push.c */
+extern void nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info);
+
+/* must WAIT_RING(chan, ncomp + 1) or equivalent beforehand! */
+static inline void nvfx_emit_vtx_attr(struct nouveau_channel* chan, unsigned attrib, float* v, unsigned ncomp)
+{
+	switch (ncomp) {
+	case 4:
+		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_4F_X(attrib), 4));
+		OUT_RING(chan, fui(v[0]));
+		OUT_RING(chan, fui(v[1]));
+		OUT_RING(chan,  fui(v[2]));
+		OUT_RING(chan,  fui(v[3]));
+		break;
+	case 3:
+		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_3F_X(attrib), 3));
+		OUT_RING(chan,  fui(v[0]));
+		OUT_RING(chan,  fui(v[1]));
+		OUT_RING(chan,  fui(v[2]));
+		break;
+	case 2:
+		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_2F_X(attrib), 2));
+		OUT_RING(chan,  fui(v[0]));
+		OUT_RING(chan,  fui(v[1]));
+		break;
+	case 1:
+		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_1F(attrib), 1));
+		OUT_RING(chan,  fui(v[0]));
+		break;
+	}
+}
+
 #endif
diff --git a/src/gallium/drivers/nvfx/nvfx_draw.c b/src/gallium/drivers/nvfx/nvfx_draw.c
index 22cff370b7..331e28418a 100644
--- a/src/gallium/drivers/nvfx/nvfx_draw.c
+++ b/src/gallium/drivers/nvfx/nvfx_draw.c
@@ -9,6 +9,7 @@
 #include "draw/draw_pipe.h"
 
 #include "nvfx_context.h"
+#include "nvfx_resource.h"
 
 /* Simple, but crappy, swtnl path, hopefully we wont need to hit this very
  * often at all.  Uses "quadro style" vertex submission + a fixed vertex
@@ -39,30 +40,21 @@ nvfx_render_vertex(struct nvfx_context *nvfx, const struct vertex_header *v)
 		unsigned idx = nvfx->swtnl.draw[i];
 		unsigned hw = nvfx->swtnl.hw[i];
 
+		WAIT_RING(chan, 5);
 		switch (nvfx->swtnl.emit[i]) {
 		case EMIT_OMIT:
 			break;
 		case EMIT_1F:
-			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_1F(hw), 1);
-			OUT_RING  (chan, fui(v->data[idx][0]));
+			nvfx_emit_vtx_attr(chan, hw, v->data[idx], 1);
 			break;
 		case EMIT_2F:
-			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_2F_X(hw), 2);
-			OUT_RING  (chan, fui(v->data[idx][0]));
-			OUT_RING  (chan, fui(v->data[idx][1]));
+			nvfx_emit_vtx_attr(chan, hw, v->data[idx], 2);
 			break;
 		case EMIT_3F:
-			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_3F_X(hw), 3);
-			OUT_RING  (chan, fui(v->data[idx][0]));
-			OUT_RING  (chan, fui(v->data[idx][1]));
-			OUT_RING  (chan, fui(v->data[idx][2]));
+			nvfx_emit_vtx_attr(chan, hw, v->data[idx], 3);
 			break;
 		case EMIT_4F:
-			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4F_X(hw), 4);
-			OUT_RING  (chan, fui(v->data[idx][0]));
-			OUT_RING  (chan, fui(v->data[idx][1]));
-			OUT_RING  (chan, fui(v->data[idx][2]));
-			OUT_RING  (chan, fui(v->data[idx][3]));
+			nvfx_emit_vtx_attr(chan, hw, v->data[idx], 4);
 			break;
 		case 0xff:
 			BEGIN_RING(chan, eng3d, NV34TCL_VTX_ATTR_4F_X(hw), 4);
@@ -231,15 +223,9 @@ nvfx_draw_render_stage(struct nvfx_context *nvfx)
 }
 
 void
-nvfx_draw_elements_swtnl(struct pipe_context *pipe,
-			 struct pipe_resource *idxbuf,
-			 unsigned idxbuf_size, int idxbuf_bias,
-			 unsigned mode, unsigned start, unsigned count)
+nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info)
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
-	struct pipe_transfer *ib_transfer = NULL;
-	struct pipe_transfer *cb_transfer = NULL;
 	unsigned i;
 	void *map;
 
@@ -247,18 +233,15 @@ nvfx_draw_elements_swtnl(struct pipe_context *pipe,
 		return;
 	nvfx_state_emit(nvfx);
 
+	/* these must be passed without adding the offsets */
 	for (i = 0; i < nvfx->vtxbuf_nr; i++) {
-		map = pipe_buffer_map(pipe, nvfx->vtxbuf[i].buffer,
-                                      PIPE_TRANSFER_READ,
-				      &vb_transfer[i]);
+		map = nvfx_buffer(nvfx->vtxbuf[i].buffer)->data;
 		draw_set_mapped_vertex_buffer(nvfx->draw, i, map);
 	}
 
-	if (idxbuf) {
-		map = pipe_buffer_map(pipe, idxbuf,
-				      PIPE_TRANSFER_READ,
-				      &ib_transfer);
-		draw_set_mapped_element_buffer(nvfx->draw, idxbuf_size, idxbuf_bias, map);
+	if (info->indexed) {
+		map = nvfx_buffer(nvfx->idxbuf.buffer)->data + nvfx->idxbuf.offset;
+		draw_set_mapped_element_buffer_range(nvfx->draw, nvfx->idxbuf.index_size, info->index_bias, info->min_index, info->max_index, map);
 	} else {
 		draw_set_mapped_element_buffer(nvfx->draw, 0, 0, NULL);
 	}
@@ -266,28 +249,14 @@ nvfx_draw_elements_swtnl(struct pipe_context *pipe,
 	if (nvfx->constbuf[PIPE_SHADER_VERTEX]) {
 		const unsigned nr = nvfx->constbuf_nr[PIPE_SHADER_VERTEX];
 
-		map = pipe_buffer_map(pipe,
-				      nvfx->constbuf[PIPE_SHADER_VERTEX],
-				      PIPE_TRANSFER_READ,
-				      &cb_transfer);
+		map = nvfx_buffer(nvfx->constbuf[PIPE_SHADER_VERTEX])->data;
 		draw_set_mapped_constant_buffer(nvfx->draw, PIPE_SHADER_VERTEX, 0,
                                                 map, nr);
 	}
 
-	draw_arrays(nvfx->draw, mode, start, count);
-
-	for (i = 0; i < nvfx->vtxbuf_nr; i++)
-		pipe_buffer_unmap(pipe, nvfx->vtxbuf[i].buffer, vb_transfer[i]);
-
-	if (idxbuf)
-		pipe_buffer_unmap(pipe, idxbuf, ib_transfer);
-
-	if (nvfx->constbuf[PIPE_SHADER_VERTEX])
-		pipe_buffer_unmap(pipe, nvfx->constbuf[PIPE_SHADER_VERTEX],
-				  cb_transfer);
+	draw_arrays_instanced(nvfx->draw, info->mode, info->start, info->count, info->start_instance, info->instance_count);
 
 	draw_flush(nvfx->draw);
-	pipe->flush(pipe, 0, NULL);
 }
 
 static INLINE void
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index ee41f03b9b..ae4fe3aa26 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -9,6 +9,7 @@
 
 #include "nvfx_context.h"
 #include "nvfx_shader.h"
+#include "nvfx_resource.h"
 
 #define MAX_CONSTS 128
 #define MAX_IMM 32
@@ -925,10 +926,7 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 
 		if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
 			struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
-			// TODO: avoid using transfers, just directly the buffer
-			struct pipe_transfer* transfer;
-			// TODO: does this check make any sense, or should we do this unconditionally?
-			uint32_t* map = pipe_buffer_map(&nvfx->pipe, constbuf, PIPE_TRANSFER_READ, &transfer);
+			uint32_t* map = (uint32_t*)nvfx_buffer(constbuf)->data;
 			uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
 			uint32_t* buf = (uint32_t*)((char*)fp->fpbo->insn + offset);
 			int i;
@@ -942,7 +940,6 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 					nvfx_fp_memcpy(&fpmap[off], &map[idx], 4 * sizeof(uint32_t));
 				}
 			}
-			pipe_buffer_unmap(&nvfx->pipe, constbuf, transfer);
 		}
 	}
 
diff --git a/src/gallium/drivers/nvfx/nvfx_push.c b/src/gallium/drivers/nvfx/nvfx_push.c
new file mode 100644
index 0000000000..52e891c667
--- /dev/null
+++ b/src/gallium/drivers/nvfx/nvfx_push.c
@@ -0,0 +1,402 @@
+#include "pipe/p_context.h"
+#include "pipe/p_state.h"
+#include "util/u_inlines.h"
+#include "util/u_format.h"
+#include "util/u_split_prim.h"
+#include "translate/translate.h"
+
+#include "nvfx_context.h"
+#include "nvfx_resource.h"
+
+struct push_context {
+	struct nouveau_channel* chan;
+
+	void *idxbuf;
+	int32_t idxbias;
+
+	float edgeflag;
+	int edgeflag_attr;
+
+	unsigned vertex_length;
+	unsigned max_vertices_per_packet;
+
+	struct translate* translate;
+};
+
+static void
+emit_edgeflag(void *priv, boolean enabled)
+{
+	struct push_context* ctx = priv;
+	struct nouveau_channel *chan = ctx->chan;
+
+	OUT_RING(chan, RING_3D(NV34TCL_EDGEFLAG_ENABLE, 1));
+	OUT_RING(chan, enabled ? 1 : 0);
+}
+
+static void
+emit_vertices_lookup8(void *priv, unsigned start, unsigned count)
+{
+        struct push_context *ctx = priv;
+        uint8_t* elts = (uint8_t*)ctx->idxbuf + start;
+
+        while(count)
+        {
+                unsigned push = MIN2(count, ctx->max_vertices_per_packet);
+                unsigned length = push * ctx->vertex_length;
+
+                OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
+                ctx->translate->run_elts8(ctx->translate, elts, push, 0, ctx->chan->cur);
+                ctx->chan->cur += length;
+
+                count -= push;
+                elts += push;
+        }
+}
+
+static void
+emit_vertices_lookup16(void *priv, unsigned start, unsigned count)
+{
+	struct push_context *ctx = priv;
+        uint16_t* elts = (uint16_t*)ctx->idxbuf + start;
+
+        while(count)
+        {
+                unsigned push = MIN2(count, ctx->max_vertices_per_packet);
+                unsigned length = push * ctx->vertex_length;
+
+                OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
+                ctx->translate->run_elts16(ctx->translate, elts, push, 0, ctx->chan->cur);
+                ctx->chan->cur += length;
+
+                count -= push;
+                elts += push;
+        }
+}
+
+static void
+emit_vertices_lookup32(void *priv, unsigned start, unsigned count)
+{
+        struct push_context *ctx = priv;
+        uint32_t* elts = (uint32_t*)ctx->idxbuf + start;
+
+        while(count)
+        {
+                unsigned push = MIN2(count, ctx->max_vertices_per_packet);
+                unsigned length = push * ctx->vertex_length;
+
+                OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
+                ctx->translate->run_elts(ctx->translate, elts, push, 0, ctx->chan->cur);
+                ctx->chan->cur += length;
+
+                count -= push;
+                elts += push;
+        }
+}
+
+static void
+emit_vertices(void *priv, unsigned start, unsigned count)
+{
+        struct push_context *ctx = priv;
+
+        while(count)
+        {
+		unsigned push = MIN2(count, ctx->max_vertices_per_packet);
+		unsigned length = push * ctx->vertex_length;
+
+		OUT_RING(ctx->chan, RING_3D_NI(NV34TCL_VERTEX_DATA, length));
+		ctx->translate->run(ctx->translate, start, push, 0, ctx->chan->cur);
+		ctx->chan->cur += length;
+
+		count -= push;
+		start += push;
+        }
+}
+
+static void
+emit_ranges(void* priv, unsigned start, unsigned vc, unsigned reg)
+{
+	struct push_context* ctx = priv;
+	struct nouveau_channel *chan = ctx->chan;
+	unsigned nr = (vc & 0xff);
+	if (nr) {
+		OUT_RING(chan, RING_3D(reg, 1));
+		OUT_RING  (chan, ((nr - 1) << 24) | start);
+		start += nr;
+	}
+
+	nr = vc >> 8;
+	while (nr) {
+		unsigned push = nr > 2047 ? 2047 : nr;
+
+		nr -= push;
+
+		OUT_RING(chan, RING_3D_NI(reg, push));
+		while (push--) {
+			OUT_RING(chan, ((0x100 - 1) << 24) | start);
+			start += 0x100;
+		}
+	}
+}
+
+static void
+emit_ib_ranges(void* priv, unsigned start, unsigned vc)
+{
+	emit_ranges(priv, start, vc, NV34TCL_VB_INDEX_BATCH);
+}
+
+static void
+emit_vb_ranges(void* priv, unsigned start, unsigned vc)
+{
+	emit_ranges(priv, start, vc, NV34TCL_VB_VERTEX_BATCH);
+}
+
+static INLINE void
+emit_elt8(void* priv, unsigned start, unsigned vc)
+{
+	struct push_context* ctx = priv;
+	struct nouveau_channel *chan = ctx->chan;
+	uint8_t *elts = (uint8_t *)ctx->idxbuf + start;
+	int idxbias = ctx->idxbias;
+
+	if (vc & 1) {
+		OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1));
+		OUT_RING  (chan, elts[0]);
+		elts++; vc--;
+	}
+
+	while (vc) {
+		unsigned i;
+		unsigned push = MIN2(vc, 2047 * 2);
+
+		OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1));
+		for (i = 0; i < push; i+=2)
+			OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias));
+
+		vc -= push;
+		elts += push;
+	}
+}
+
+static INLINE void
+emit_elt16(void* priv, unsigned start, unsigned vc)
+{
+	struct push_context* ctx = priv;
+	struct nouveau_channel *chan = ctx->chan;
+	uint16_t *elts = (uint16_t *)ctx->idxbuf + start;
+	int idxbias = ctx->idxbias;
+
+	if (vc & 1) {
+		OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1));
+		OUT_RING  (chan, elts[0]);
+		elts++; vc--;
+	}
+
+	while (vc) {
+		unsigned i;
+		unsigned push = MIN2(vc, 2047 * 2);
+
+		OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1));
+		for (i = 0; i < push; i+=2)
+			OUT_RING(chan, ((elts[i+1] + idxbias) << 16) | (elts[i] + idxbias));
+
+		vc -= push;
+		elts += push;
+	}
+}
+
+static INLINE void
+emit_elt32(void* priv, unsigned start, unsigned vc)
+{
+	struct push_context* ctx = priv;
+	struct nouveau_channel *chan = ctx->chan;
+	uint32_t *elts = (uint32_t *)ctx->idxbuf + start;
+	int idxbias = ctx->idxbias;
+
+	while (vc) {
+		unsigned push = MIN2(vc, 2047);
+
+		OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U32, push));
+		assert(AVAIL_RING(chan) >= push);
+		if(idxbias)
+		{
+			for(unsigned i = 0; i < push; ++i)
+				OUT_RING(chan, elts[i] + idxbias);
+		}
+		else
+			OUT_RINGp(chan, elts, push);
+
+		vc -= push;
+		elts += push;
+	}
+}
+
+void
+nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+	struct nouveau_channel *chan = nvfx->screen->base.channel;
+	struct push_context ctx;
+	struct util_split_prim s;
+	unsigned instances_left = info->instance_count;
+	int vtx_value;
+	unsigned hw_mode = nvgl_primitive(info->mode);
+	int i;
+	struct
+	{
+		uint8_t* map;
+		unsigned step;
+	} per_instance[16];
+	unsigned p_overhead = 0
+			+ 4 /* begin/end */
+			+ 4; /* potential edgeflag enable/disable */
+
+	ctx.chan = nvfx->screen->base.channel;
+	ctx.translate = nvfx->vtxelt->translate;
+	ctx.idxbuf = NULL;
+	ctx.vertex_length = nvfx->vtxelt->vertex_length;
+	ctx.max_vertices_per_packet = nvfx->vtxelt->max_vertices_per_packet;
+	ctx.edgeflag = 0.5f;
+	// TODO: figure out if we really want to handle this, and do so in that case
+	ctx.edgeflag_attr = 0xff; // nvfx->vertprog->cfg.edgeflag_in;
+
+	if(!nvfx->use_vertex_buffers)
+	{
+		for(i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; ++i)
+		{
+			struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
+			struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
+			uint8_t* data = nvfx_buffer(vb->buffer)->data + vb->buffer_offset;
+			if(info->indexed)
+				data += info->index_bias * vb->stride;
+			ctx.translate->set_buffer(ctx.translate, i, data, vb->stride, ~0);
+		}
+
+		if(ctx.edgeflag_attr < 16)
+			vtx_value = -(ctx.vertex_length + 3);  /* vertex data and edgeflag header and value */
+		else
+		{
+			p_overhead += 1; /* initial vertex_data header */
+			vtx_value = -ctx.vertex_length;  /* vertex data and edgeflag header and value */
+		}
+
+		if (info->indexed) {
+			// XXX: this case and is broken and probably need a new VTX_ATTR push path
+			if (nvfx->idxbuf.index_size == 1)
+				s.emit = emit_vertices_lookup8;
+			else if (nvfx->idxbuf.index_size == 2)
+				s.emit = emit_vertices_lookup16;
+			else
+				s.emit = emit_vertices_lookup32;
+		} else
+			s.emit = emit_vertices;
+	}
+	else
+	{
+		if(!info->indexed || nvfx->use_index_buffer)
+		{
+			s.emit = info->indexed ? emit_ib_ranges : emit_vb_ranges;
+			p_overhead += 3;
+			vtx_value = 0;
+		}
+		else if (nvfx->idxbuf.index_size == 4)
+		{
+			s.emit = emit_elt32;
+			p_overhead += 1;
+			vtx_value = 8;
+		}
+		else
+		{
+			s.emit = (nvfx->idxbuf.index_size == 2) ? emit_elt16 : emit_elt8;
+			p_overhead += 3;
+			vtx_value = 7;
+		}
+	}
+
+	ctx.idxbias = info->index_bias;
+	if(nvfx->use_vertex_buffers)
+		ctx.idxbias -= nvfx->base_vertex;
+
+	/* map index buffer, if present */
+	if (info->indexed && !nvfx->use_index_buffer)
+		ctx.idxbuf = nvfx_buffer(nvfx->idxbuf.buffer)->data + nvfx->idxbuf.offset;
+
+	s.priv = &ctx;
+	s.edge = emit_edgeflag;
+
+	for (i = 0; i < nvfx->vtxelt->num_per_instance; ++i)
+	{
+		struct nvfx_per_instance_element *ve = &nvfx->vtxelt->per_instance[i];
+		struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->base.vertex_buffer_index];
+		float v[4];
+		per_instance[i].step = info->start_instance % ve->instance_divisor;
+		per_instance[i].map = nvfx_buffer(vb->buffer)->data + vb->buffer_offset + ve->base.src_offset;
+
+		nvfx->vtxelt->per_instance[i].base.fetch_rgba_float(v, per_instance[i].map, 0, 0);
+
+		WAIT_RING(chan, 5);
+		nvfx_emit_vtx_attr(chan, nvfx->vtxelt->per_instance[i].base.idx, v, nvfx->vtxelt->per_instance[i].base.ncomp);
+	}
+
+	/* per-instance loop */
+	while (instances_left--) {
+		int max_verts;
+		boolean done;
+
+		util_split_prim_init(&s, info->mode, info->start, info->count);
+		nvfx_state_emit(nvfx);
+		for(;;) {
+			max_verts  = AVAIL_RING(chan);
+			max_verts -= p_overhead;
+
+			/* if vtx_value < 0, each vertex is -vtx_value words long
+			 * otherwise, each vertex is 2^(vtx_value) / 255 words long (this is an approximation)
+			 */
+			if(vtx_value < 0)
+			{
+				max_verts /= -vtx_value;
+				max_verts -= (max_verts >> 10); /* vertex data headers */
+			}
+			else
+			{
+				if(max_verts >= (1 << 23)) /* avoid overflow here */
+					max_verts = (1 << 23);
+				max_verts = (max_verts * 255) >> vtx_value;
+			}
+
+			//printf("avail %u max_verts %u\n", AVAIL_RING(chan), max_verts);
+
+			if(max_verts >= 16)
+			{
+				OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
+				OUT_RING(chan, hw_mode);
+				done = util_split_prim_next(&s, max_verts);
+				OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
+				OUT_RING(chan, 0);
+
+				if(done)
+					break;
+			}
+
+			FIRE_RING(chan);
+			nvfx_state_emit(nvfx);
+		}
+
+		/* set data for the next instance, if any changed */
+		for (i = 0; i < nvfx->vtxelt->num_per_instance; ++i)
+		{
+			struct nvfx_per_instance_element *ve = &nvfx->vtxelt->per_instance[i];
+			struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->base.vertex_buffer_index];
+
+			if(++per_instance[i].step == ve->instance_divisor)
+			{
+				float v[4];
+				per_instance[i].map += vb->stride;
+				per_instance[i].step = 0;
+
+				nvfx->vtxelt->per_instance[i].base.fetch_rgba_float(v, per_instance[i].map, 0, 0);
+				WAIT_RING(chan, 5);
+				nvfx_emit_vtx_attr(chan, nvfx->vtxelt->per_instance[i].base.idx, v, nvfx->vtxelt->per_instance[i].base.ncomp);
+			}
+		}
+	}
+}
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.c b/src/gallium/drivers/nvfx/nvfx_resource.c
index 1c921b4710..3a46e0a7a5 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.c
+++ b/src/gallium/drivers/nvfx/nvfx_resource.c
@@ -59,12 +59,6 @@ nvfx_resource_get_handle(struct pipe_screen *pscreen,
 void
 nvfx_init_resource_functions(struct pipe_context *pipe)
 {
-	pipe->get_transfer = nvfx_transfer_new;
-	pipe->transfer_map = nvfx_transfer_map;
-	pipe->transfer_flush_region = u_default_transfer_flush_region;
-	pipe->transfer_unmap = nvfx_transfer_unmap;
-	pipe->transfer_destroy = util_staging_transfer_destroy;
-	pipe->transfer_inline_write = u_default_transfer_inline_write;
 	pipe->is_resource_referenced = nvfx_resource_is_referenced;
 }
 
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.h b/src/gallium/drivers/nvfx/nvfx_resource.h
index ff86f6d9cb..583be4de2a 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.h
+++ b/src/gallium/drivers/nvfx/nvfx_resource.h
@@ -17,8 +17,23 @@ struct nvfx_resource {
 	struct nouveau_bo *bo;
 };
 
+static INLINE
+struct nvfx_resource *nvfx_resource(struct pipe_resource *resource)
+{
+	return (struct nvfx_resource *)resource;
+}
+
 #define NVFX_RESOURCE_FLAG_LINEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
+#define NVFX_RESOURCE_FLAG_USER (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
+
+/* is resource mapped into the GPU's address space (i.e. VRAM or GART) ? */
+static INLINE boolean
+nvfx_resource_mapped_by_gpu(struct pipe_resource *resource)
+{
+   return nvfx_resource(resource)->bo->handle;
+}
 
+/* is resource in VRAM? */
 static inline int
 nvfx_resource_on_gpu(struct pipe_resource* pr)
 {
@@ -63,12 +78,6 @@ struct nvfx_surface {
 	struct nvfx_miptree* temp;
 };
 
-static INLINE 
-struct nvfx_resource *nvfx_resource(struct pipe_resource *resource)
-{
-	return (struct nvfx_resource *)resource;
-}
-
 static INLINE struct nouveau_bo *
 nvfx_surface_buffer(struct pipe_surface *surf)
 {
@@ -106,22 +115,6 @@ nvfx_miptree_from_handle(struct pipe_screen *pscreen,
 			 const struct pipe_resource *template,
 			 struct winsys_handle *whandle);
 
-struct pipe_resource *
-nvfx_buffer_create(struct pipe_screen *pscreen,
-		   const struct pipe_resource *template);
-
-void
-nvfx_buffer_destroy(struct pipe_screen *pscreen,
-                    struct pipe_resource *presource);
-
-struct pipe_resource *
-nvfx_user_buffer_create(struct pipe_screen *screen,
-			void *ptr,
-			unsigned bytes,
-			unsigned usage);
-
-
-
 void
 nvfx_miptree_surface_del(struct pipe_surface *ps);
 
@@ -173,4 +166,58 @@ nvfx_surface_create_temp(struct pipe_context* pipe, struct pipe_surface* surf);
 void
 nvfx_surface_flush(struct pipe_context* pipe, struct pipe_surface* surf);
 
+struct nvfx_buffer
+{
+	struct nvfx_resource base;
+	uint8_t* data;
+	unsigned size;
+
+	/* the range of data not yet uploaded to the GPU bo */
+	unsigned dirty_begin;
+	unsigned dirty_end;
+
+	/* whether all transfers were unsynchronized */
+	boolean dirty_unsynchronized;
+
+	/* whether it would have been profitable to upload
+	 * the latest updated data to the GPU immediately */
+	boolean last_update_static;
+
+	/* how many bytes we need to draw before we deem
+	 * the buffer to be static
+	 */
+	long long bytes_to_draw_until_static;
+};
+
+static inline struct nvfx_buffer* nvfx_buffer(struct pipe_resource* pr)
+{
+	return (struct nvfx_buffer*)pr;
+}
+
+/* this is an heuristic to determine whether we are better off uploading the
+ * buffer to the GPU, or just continuing pushing it on the FIFO
+ */
+static inline boolean nvfx_buffer_seems_static(struct nvfx_buffer* buffer)
+{
+	return buffer->last_update_static
+		|| buffer->bytes_to_draw_until_static < 0;
+}
+
+struct pipe_resource *
+nvfx_buffer_create(struct pipe_screen *pscreen,
+		   const struct pipe_resource *template);
+
+void
+nvfx_buffer_destroy(struct pipe_screen *pscreen,
+                    struct pipe_resource *presource);
+
+struct pipe_resource *
+nvfx_user_buffer_create(struct pipe_screen *screen,
+			void *ptr,
+			unsigned bytes,
+			unsigned usage);
+
+void
+nvfx_buffer_upload(struct nvfx_buffer* buffer);
+
 #endif
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index a1b8361a9a..7e3caf8d2e 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -163,11 +163,11 @@ nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 }
 
 static boolean
-nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
+nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 				     enum pipe_format format,
 				     enum pipe_texture_target target,
 				     unsigned sample_count,
-				     unsigned tex_usage, unsigned geom_flags)
+				     unsigned bind, unsigned geom_flags)
 {
 	struct nvfx_screen *screen = nvfx_screen(pscreen);
 	struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
@@ -175,7 +175,7 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 	 if (sample_count > 1)
 		return FALSE;
 
-	if (tex_usage & PIPE_BIND_RENDER_TARGET) {
+	if (bind & PIPE_BIND_RENDER_TARGET) {
 		switch (format) {
 		case PIPE_FORMAT_B8G8R8A8_UNORM:
 		case PIPE_FORMAT_B8G8R8X8_UNORM:
@@ -186,7 +186,7 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 		}
 	}
 
-	if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
+	if (bind & PIPE_BIND_DEPTH_STENCIL) {
 		switch (format) {
 		case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 		case PIPE_FORMAT_X8Z24_UNORM:
@@ -201,7 +201,7 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 		}
 	}
 
-	if (tex_usage & PIPE_BIND_SAMPLER_VIEW) {
+	if (bind & PIPE_BIND_SAMPLER_VIEW) {
 		struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 		if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 			return FALSE;
@@ -218,6 +218,22 @@ nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 		}
 	}
 
+	// note that we do actually support everything through translate
+	if (bind & PIPE_BIND_VERTEX_BUFFER) {
+		unsigned type = nvfx_vertex_formats[format];
+		if(!type)
+			return FALSE;
+	}
+
+	if (bind & PIPE_BIND_INDEX_BUFFER) {
+		// 8-bit indices supported, but not in hardware index buffer
+		if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
+			return FALSE;
+	}
+
+	if(bind & PIPE_BIND_STREAM_OUTPUT)
+		return FALSE;
+
 	return TRUE;
 }
 
@@ -387,7 +403,7 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	pscreen->destroy = nvfx_screen_destroy;
 	pscreen->get_param = nvfx_screen_get_param;
 	pscreen->get_paramf = nvfx_screen_get_paramf;
-	pscreen->is_format_supported = nvfx_screen_surface_format_supported;
+	pscreen->is_format_supported = nvfx_screen_is_format_supported;
 	pscreen->context_create = nvfx_create;
 
 	switch (dev->chipset & 0xf0) {
@@ -419,6 +435,11 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 	}
 
 	screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE);
+	screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
+
+	screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
+	screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
+	screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 
 	screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.h b/src/gallium/drivers/nvfx/nvfx_screen.h
index 4dedbe9cb4..473a112775 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.h
+++ b/src/gallium/drivers/nvfx/nvfx_screen.h
@@ -16,6 +16,7 @@ struct nvfx_screen {
 
 	unsigned is_nv4x; /* either 0 or ~0 */
 	boolean force_swtnl;
+	boolean trace_draw;
 	unsigned vertex_buffer_reloc_flags;
 	unsigned index_buffer_reloc_flags;
 
@@ -33,6 +34,18 @@ struct nvfx_screen {
 	struct nouveau_resource *vp_data_heap;
 
 	struct nv04_2d_context* eng2d;
+
+	/* Once the amount of bytes drawn from the buffer reaches the updated size times this value,
+	 * we will assume that the buffer will be drawn an huge number of times before the
+	 * next modification
+	 */
+	float static_reuse_threshold;
+
+	/* Cost of allocating a buffer in terms of the cost of copying a byte to an hardware buffer */
+	unsigned buffer_allocation_cost;
+
+	/* inline_cost/hardware_cost conversion ration */
+	float inline_cost_per_hardware_cost;
 };
 
 static INLINE struct nvfx_screen *
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index d459f9a880..25d29720a8 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -441,83 +441,6 @@ nvfx_set_viewport_state(struct pipe_context *pipe,
 	nvfx->draw_dirty |= NVFX_NEW_VIEWPORT;
 }
 
-static void
-nvfx_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
-			const struct pipe_vertex_buffer *vb)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-
-	for(unsigned i = 0; i < count; ++i)
-	{
-		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, vb[i].buffer);
-		nvfx->vtxbuf[i].buffer_offset = vb[i].buffer_offset;
-		nvfx->vtxbuf[i].max_index = vb[i].max_index;
-		nvfx->vtxbuf[i].stride = vb[i].stride;
-	}
-
-	for(unsigned i = count; i < nvfx->vtxbuf_nr; ++i)
-		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, 0);
-
-	nvfx->vtxbuf_nr = count;
-
-	nvfx->dirty |= NVFX_NEW_ARRAYS;
-	nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
-}
-
-static void
-nvfx_set_index_buffer(struct pipe_context *pipe,
-		      const struct pipe_index_buffer *ib)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-
-	/* TODO make this more like a state */
-
-	if(ib)
-	{
-		pipe_resource_reference(&nvfx->idxbuf.buffer, ib->buffer);
-		nvfx->idxbuf.index_size = ib->index_size;
-		nvfx->idxbuf.offset = ib->offset;
-	}
-	else
-	{
-		pipe_resource_reference(&nvfx->idxbuf.buffer, 0);
-		nvfx->idxbuf.index_size = 0;
-		nvfx->idxbuf.offset = 0;
-	}
-}
-
-static void *
-nvfx_vtxelts_state_create(struct pipe_context *pipe,
-			  unsigned num_elements,
-			  const struct pipe_vertex_element *elements)
-{
-	struct nvfx_vtxelt_state *cso = CALLOC_STRUCT(nvfx_vtxelt_state);
-
-	assert(num_elements < 16); /* not doing fallbacks yet */
-	cso->num_elements = num_elements;
-	memcpy(cso->pipe, elements, num_elements * sizeof(*elements));
-
-/*	nvfx_vtxelt_construct(cso);*/
-
-	return (void *)cso;
-}
-
-static void
-nvfx_vtxelts_state_delete(struct pipe_context *pipe, void *hwcso)
-{
-	FREE(hwcso);
-}
-
-static void
-nvfx_vtxelts_state_bind(struct pipe_context *pipe, void *hwcso)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-
-	nvfx->vtxelt = hwcso;
-	nvfx->dirty |= NVFX_NEW_ARRAYS;
-	/*nvfx->draw_dirty |= NVFX_NEW_ARRAYS;*/
-}
-
 void
 nvfx_init_state_functions(struct nvfx_context *nvfx)
 {
@@ -553,11 +476,4 @@ nvfx_init_state_functions(struct nvfx_context *nvfx)
 	nvfx->pipe.set_polygon_stipple = nvfx_set_polygon_stipple;
 	nvfx->pipe.set_scissor_state = nvfx_set_scissor_state;
 	nvfx->pipe.set_viewport_state = nvfx_set_viewport_state;
-
-	nvfx->pipe.create_vertex_elements_state = nvfx_vtxelts_state_create;
-	nvfx->pipe.delete_vertex_elements_state = nvfx_vtxelts_state_delete;
-	nvfx->pipe.bind_vertex_elements_state = nvfx_vtxelts_state_bind;
-
-	nvfx->pipe.set_vertex_buffers = nvfx_set_vertex_buffers;
-	nvfx->pipe.set_index_buffer = nvfx_set_index_buffer;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index dc70f3de87..b9d1897791 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -8,6 +8,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	unsigned dirty;
+	unsigned still_dirty = 0;
 	int all_swizzled = -1;
 	boolean flush_tex_cache = FALSE;
 
@@ -52,11 +53,19 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 				return FALSE;
 		}
 
-		if(dirty & (NVFX_NEW_ARRAYS))
+		if(dirty & NVFX_NEW_ARRAYS)
 		{
 			if(!nvfx_vbo_validate(nvfx))
 				return FALSE;
 		}
+
+		if(dirty & NVFX_NEW_INDEX)
+		{
+			if(nvfx->use_index_buffer)
+				nvfx_idxbuf_validate(nvfx);
+			else
+				still_dirty = NVFX_NEW_INDEX;
+		}
 	}
 	else
 	{
@@ -64,7 +73,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 		if(dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
 			nvfx_vertprog_validate(nvfx);
 
-		if(dirty & (NVFX_NEW_ARRAYS | NVFX_NEW_FRAGPROG))
+		if(dirty & (NVFX_NEW_ARRAYS | NVFX_NEW_INDEX | NVFX_NEW_FRAGPROG))
 			nvfx_vtxfmt_validate(nvfx);
 	}
 
@@ -118,7 +127,24 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 			OUT_RING(chan, 1);
 		}
 	}
-	nvfx->dirty = 0;
+
+	nvfx->dirty = dirty & still_dirty;
+
+	unsigned render_temps = nvfx->state.render_temps;
+	if(render_temps)
+	{
+		for(int i = 0; i < nvfx->framebuffer.nr_cbufs; ++i)
+		{
+			if(render_temps & (1 << i))
+				util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.cbufs[i]),
+						(struct util_dirty_surface*)nvfx->framebuffer.cbufs[i]);
+		}
+
+		if(render_temps & 0x80)
+			util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.zsbuf),
+					(struct util_dirty_surface*)nvfx->framebuffer.zsbuf);
+	}
+
 	return TRUE;
 }
 
@@ -137,21 +163,6 @@ nvfx_state_emit(struct nvfx_context *nvfx)
 	      ;
 	MARK_RING(chan, max_relocs * 2, max_relocs * 2);
 	nvfx_state_relocate(nvfx);
-
-	unsigned render_temps = nvfx->state.render_temps;
-	if(render_temps)
-	{
-		for(int i = 0; i < nvfx->framebuffer.nr_cbufs; ++i)
-		{
-			if(render_temps & (1 << i))
-				util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.cbufs[i]),
-						(struct util_dirty_surface*)nvfx->framebuffer.cbufs[i]);
-		}
-
-		if(render_temps & 0x80)
-			util_dirty_surface_set_dirty(nvfx_surface_get_dirty_surfaces(nvfx->framebuffer.zsbuf),
-					(struct util_dirty_surface*)nvfx->framebuffer.zsbuf);
-	}
 }
 
 void
@@ -161,7 +172,11 @@ nvfx_state_relocate(struct nvfx_context *nvfx)
 	nvfx_fragtex_relocate(nvfx);
 	nvfx_fragprog_relocate(nvfx);
 	if (nvfx->render_mode == HW)
+	{
 		nvfx_vbo_relocate(nvfx);
+		if(nvfx->use_index_buffer)
+			nvfx_idxbuf_relocate(nvfx);
+	}
 }
 
 boolean
diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c
index 80b0f21575..28bbd36c2e 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_fb.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c
@@ -1,6 +1,5 @@
 #include "nvfx_context.h"
 #include "nvfx_resource.h"
-#include "nouveau/nouveau_util.h"
 #include "util/u_format.h"
 
 static inline boolean
@@ -125,8 +124,8 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
 		assert(!(fb->width & (fb->width - 1)) && !(fb->height & (fb->height - 1)));
 
 		rt_format = NV34TCL_RT_FORMAT_TYPE_SWIZZLED |
-			(log2i(fb->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
-			(log2i(fb->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
+			(util_logbase2(fb->width) << NV34TCL_RT_FORMAT_LOG2_WIDTH_SHIFT) |
+			(util_logbase2(fb->height) << NV34TCL_RT_FORMAT_LOG2_HEIGHT_SHIFT);
 	} else
 		rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
 
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
index 7efdd954b4..135978ad27 100644
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ b/src/gallium/drivers/nvfx/nvfx_surface.c
@@ -36,7 +36,6 @@
 #include "util/u_blitter.h"
 
 #include "nouveau/nouveau_winsys.h"
-#include "nouveau/nouveau_util.h"
 #include "nouveau/nouveau_screen.h"
 #include "nvfx_context.h"
 #include "nvfx_screen.h"
@@ -62,7 +61,7 @@ nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format)
 		break;
 	default:
 		assert(util_is_pot(bits));
-		int shift = log2i(bits) - 3;
+		int shift = util_logbase2(bits) - 3;
 		assert(shift >= 2);
 		rgn->bpps = 2;
 		shift -= 2;
@@ -365,25 +364,29 @@ nvfx_surface_copy_temp(struct pipe_context* pipe, struct pipe_surface* surf, int
 {
 	struct nvfx_surface* ns = (struct nvfx_surface*)surf;
 	struct pipe_subresource tempsr, surfsr;
-	struct pipe_resource *idxbuf_buffer;
-	unsigned idxbuf_format;
+	struct nvfx_context* nvfx = nvfx_context(pipe);
+
+	// TODO: we really should do this validation before setting these variable in draw calls
+	unsigned use_vertex_buffers = nvfx->use_vertex_buffers;
+	boolean use_index_buffer = nvfx->use_index_buffer;
+	unsigned base_vertex = nvfx->base_vertex;
 
 	tempsr.face = 0;
 	tempsr.level = 0;
 	surfsr.face = surf->face;
 	surfsr.level = surf->level;
 
-	// TODO: do this properly, in blitter save
-	idxbuf_buffer = ((struct nvfx_context*)pipe)->idxbuf_buffer;
-	idxbuf_format = ((struct nvfx_context*)pipe)->idxbuf_format;
-
 	if(to_temp)
 		nvfx_resource_copy_region(pipe, &ns->temp->base.base, tempsr, 0, 0, 0, surf->texture, surfsr, 0, 0, surf->zslice, surf->width, surf->height);
 	else
 		nvfx_resource_copy_region(pipe, surf->texture, surfsr, 0, 0, surf->zslice, &ns->temp->base.base, tempsr, 0, 0, 0, surf->width, surf->height);
 
-	((struct nvfx_context*)pipe)->idxbuf_buffer = idxbuf_buffer;
-	((struct nvfx_context*)pipe)->idxbuf_format = idxbuf_format;
+	nvfx->use_vertex_buffers = use_vertex_buffers;
+	nvfx->use_index_buffer = use_index_buffer;
+        nvfx->base_vertex = base_vertex;
+
+	nvfx->dirty |= NVFX_NEW_ARRAYS;
+	nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
 }
 
 void
diff --git a/src/gallium/drivers/nvfx/nvfx_transfer.c b/src/gallium/drivers/nvfx/nvfx_transfer.c
index e9c3dd7e55..ca4462ef9d 100644
--- a/src/gallium/drivers/nvfx/nvfx_transfer.c
+++ b/src/gallium/drivers/nvfx/nvfx_transfer.c
@@ -26,25 +26,44 @@ nvfx_transfer_new(struct pipe_context *pipe,
 			  unsigned usage,
 			  const struct pipe_box *box)
 {
-	struct nvfx_staging_transfer* tx;
-	bool direct = !nvfx_resource_on_gpu(pt) && pt->flags & NVFX_RESOURCE_FLAG_LINEAR;
-
-	tx = CALLOC_STRUCT(nvfx_staging_transfer);
-	if(!tx)
-		return NULL;
-
-	util_staging_transfer_init(pipe, pt, sr, usage, box, direct, tx);
+        if((usage & (PIPE_TRANSFER_UNSYNCHRONIZED | PIPE_TRANSFER_DONTBLOCK)) == PIPE_TRANSFER_DONTBLOCK)
+        {
+                struct nouveau_bo* bo = ((struct nvfx_resource*)pt)->bo;
+                if(bo && nouveau_bo_busy(bo, NOUVEAU_BO_WR))
+                        return NULL;
+        }
 
 	if(pt->target == PIPE_BUFFER)
 	{
-		tx->base.base.slice_stride = tx->base.base.stride = ((struct nvfx_resource*)tx->base.staging_resource)->bo->size;
-		if(direct)
-			tx->offset = util_format_get_stride(pt->format, box->x);
-		else
-			tx->offset = 0;
+		// it would be nice if we could avoid all this ridiculous overhead...
+		struct pipe_transfer* tx;
+		struct nvfx_buffer* buffer = nvfx_buffer(pt);
+
+		tx = CALLOC_STRUCT(pipe_transfer);
+		if (!tx)
+			return NULL;
+
+		pipe_resource_reference(&tx->resource, pt);
+		tx->sr = sr;
+		tx->usage = usage;
+		tx->box = *box;
+
+		tx->slice_stride = tx->stride = util_format_get_stride(pt->format, box->width);
+		tx->data = buffer->data + util_format_get_stride(pt->format, box->x);
+
+		return tx;
 	}
 	else
 	{
+	        struct nvfx_staging_transfer* tx;
+	        bool direct = !nvfx_resource_on_gpu(pt) && pt->flags & NVFX_RESOURCE_FLAG_LINEAR;
+
+	        tx = CALLOC_STRUCT(nvfx_staging_transfer);
+	        if(!tx)
+	        	return NULL;
+
+	        util_staging_transfer_init(pipe, pt, sr, usage, box, direct, &tx->base);
+
 		if(direct)
 		{
 			tx->base.base.stride = nvfx_subresource_pitch(pt, sr.level);
@@ -66,26 +85,132 @@ nvfx_transfer_new(struct pipe_context *pipe,
 	}
 }
 
+static void nvfx_buffer_dirty_interval(struct nvfx_buffer* buffer, unsigned begin, unsigned size, boolean unsynchronized)
+{
+	struct nvfx_screen* screen = nvfx_screen(buffer->base.base.screen);
+	buffer->last_update_static = buffer->bytes_to_draw_until_static < 0;
+	if(buffer->dirty_begin == buffer->dirty_end)
+	{
+		buffer->dirty_begin = begin;
+		buffer->dirty_end = begin + size;
+		buffer->dirty_unsynchronized = unsynchronized;
+	}
+	else
+	{
+		buffer->dirty_begin = MIN2(buffer->dirty_begin, begin);
+		buffer->dirty_end = MAX2(buffer->dirty_end, begin + size);
+		buffer->dirty_unsynchronized &= unsynchronized;
+	}
+
+	if(unsynchronized)
+	{
+		// TODO: revisit this, it doesn't seem quite right
+		//printf("UNSYNC UPDATE %p %u %u\n", buffer, begin, size);
+		buffer->bytes_to_draw_until_static += size * screen->static_reuse_threshold;
+	}
+	else
+		buffer->bytes_to_draw_until_static = buffer->size * screen->static_reuse_threshold;
+}
+
+static void nvfx_transfer_flush_region( struct pipe_context *pipe,
+				      struct pipe_transfer *ptx,
+				      const struct pipe_box *box)
+{
+	if(ptx->resource->target == PIPE_BUFFER && (ptx->usage & PIPE_TRANSFER_FLUSH_EXPLICIT))
+	{
+		struct nvfx_buffer* buffer = nvfx_buffer(ptx->resource);
+		nvfx_buffer_dirty_interval(buffer,
+				(uint8_t*)ptx->data - buffer->data + util_format_get_stride(buffer->base.base.format, box->x),
+				util_format_get_stride(buffer->base.base.format, box->width),
+				!!(ptx->usage & PIPE_TRANSFER_UNSYNCHRONIZED));
+	}
+}
+
+static void
+nvfx_transfer_destroy(struct pipe_context *pipe, struct pipe_transfer *ptx)
+{
+	if(ptx->resource->target == PIPE_BUFFER)
+	{
+		struct nvfx_buffer* buffer = nvfx_buffer(ptx->resource);
+		if((ptx->usage & (PIPE_TRANSFER_WRITE | PIPE_TRANSFER_FLUSH_EXPLICIT)) == PIPE_TRANSFER_WRITE)
+			nvfx_buffer_dirty_interval(buffer,
+				(uint8_t*)ptx->data - buffer->data,
+				ptx->stride,
+				!!(ptx->usage & PIPE_TRANSFER_UNSYNCHRONIZED));
+		pipe_resource_reference(&ptx->resource, 0);
+		FREE(ptx);
+	}
+	else
+		util_staging_transfer_destroy(pipe, ptx);
+}
+
 void *
 nvfx_transfer_map(struct pipe_context *pipe, struct pipe_transfer *ptx)
 {
-	struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
-	if(!ptx->data)
+	if(ptx->resource->target == PIPE_BUFFER)
+		return ptx->data;
+	else
 	{
-		struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
-		uint8_t *map = nouveau_screen_bo_map(pipe->screen, mt->base.bo, nouveau_screen_transfer_flags(ptx->usage));
-		ptx->data = map + tx->offset;
+		struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
+		if(!ptx->data)
+		{
+			struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
+			uint8_t *map = nouveau_screen_bo_map(pipe->screen, mt->base.bo, nouveau_screen_transfer_flags(ptx->usage));
+			ptx->data = map + tx->offset;
+		}
+
+		++tx->map_count;
+		return ptx->data;
 	}
-	++tx->map_count;
-	return ptx->data;
 }
 
 void
 nvfx_transfer_unmap(struct pipe_context *pipe, struct pipe_transfer *ptx)
 {
-	struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
-	struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
+	if(ptx->resource->target != PIPE_BUFFER)
+	{
+		struct nvfx_staging_transfer *tx = (struct nvfx_staging_transfer *)ptx;
+		struct nvfx_miptree *mt = (struct nvfx_miptree *)tx->base.staging_resource;
+
+		if(!--tx->map_count)
+		{
+			nouveau_screen_bo_unmap(pipe->screen, mt->base.bo);
+			ptx->data = 0;
+		}
+	}
+}
+
+static void nvfx_transfer_inline_write( struct pipe_context *pipe,
+				      struct pipe_resource *pr,
+				      struct pipe_subresource sr,
+				      unsigned usage,
+				      const struct pipe_box *box,
+				      const void *data,
+				      unsigned stride,
+				      unsigned slice_stride)
+{
+	if(pr->target != PIPE_BUFFER)
+	{
+		u_default_transfer_inline_write(pipe, pr, sr, usage, box, data, stride, slice_stride);
+	}
+	else
+	{
+		struct nvfx_buffer* buffer = nvfx_buffer(pr);
+		unsigned begin = util_format_get_stride(pr->format, box->x);
+		unsigned size = util_format_get_stride(pr->format, box->width);
+		memcpy(buffer->data + begin, data, size);
+		nvfx_buffer_dirty_interval(buffer, begin, size,
+				!!(pr->flags & PIPE_TRANSFER_UNSYNCHRONIZED));
+	}
+}
 
-	if(!--tx->map_count)
-		nouveau_screen_bo_unmap(pipe->screen, mt->base.bo);
+void
+nvfx_init_transfer_functions(struct pipe_context *pipe)
+{
+	pipe->get_transfer = nvfx_transfer_new;
+	pipe->transfer_map = nvfx_transfer_map;
+	pipe->transfer_flush_region = nvfx_transfer_flush_region;
+	pipe->transfer_unmap = nvfx_transfer_unmap;
+	pipe->transfer_destroy = nvfx_transfer_destroy;
+	pipe->transfer_inline_write = nvfx_transfer_inline_write;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index 4aa3793842..a6cd125635 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -2,6 +2,7 @@
 #include "pipe/p_state.h"
 #include "util/u_inlines.h"
 #include "util/u_format.h"
+#include "translate/translate.h"
 
 #include "nvfx_context.h"
 #include "nvfx_state.h"
@@ -10,646 +11,583 @@
 #include "nouveau/nouveau_channel.h"
 #include "nouveau/nouveau_class.h"
 #include "nouveau/nouveau_pushbuf.h"
-#include "nouveau/nouveau_util.h"
 
-static INLINE int
-nvfx_vbo_format_to_hw(enum pipe_format pipe, unsigned *fmt, unsigned *ncomp)
+static inline unsigned
+util_guess_unique_indices_count(unsigned mode, unsigned indices)
 {
-	switch (pipe) {
-	case PIPE_FORMAT_R32_FLOAT:
-	case PIPE_FORMAT_R32G32_FLOAT:
-	case PIPE_FORMAT_R32G32B32_FLOAT:
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-		*fmt = NV34TCL_VTXFMT_TYPE_FLOAT;
-		break;
-	case PIPE_FORMAT_R16_FLOAT:
-	case PIPE_FORMAT_R16G16_FLOAT:
-	case PIPE_FORMAT_R16G16B16_FLOAT:
-	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-		*fmt = NV34TCL_VTXFMT_TYPE_HALF;
-		break;
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R8G8_UNORM:
-	case PIPE_FORMAT_R8G8B8_UNORM:
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-		*fmt = NV34TCL_VTXFMT_TYPE_UBYTE;
-		break;
-	case PIPE_FORMAT_R16_SSCALED:
-	case PIPE_FORMAT_R16G16_SSCALED:
-	case PIPE_FORMAT_R16G16B16_SSCALED:
-	case PIPE_FORMAT_R16G16B16A16_SSCALED:
-		*fmt = NV34TCL_VTXFMT_TYPE_USHORT;
-		break;
-	default:
-		NOUVEAU_ERR("Unknown format %s\n", util_format_name(pipe));
-		return 1;
+	/* Euler's formula gives V =
+	 * = E - F + 2 =
+	 * = F * (polygon_edges / 2 - 1) + 2 =
+	 * =  F * (polygon_edges - 2) / 2 + 2 =
+	 * =  indices * (polygon_edges - 2) / (2 * indices_per_face) + 2
+	 * =  indices * (1 / 2 - 1 / polygon_edges) + 2
+	 */
+	switch(mode)
+	{
+	case PIPE_PRIM_LINES:
+		return indices >> 1;
+	case PIPE_PRIM_TRIANGLES:
+	{
+		// avoid an expensive division by 3 using the multiplicative inverse mod 2^32
+		unsigned q;
+		unsigned inv3 = 2863311531;
+		indices >>= 1;
+		q = indices * inv3;
+		if(unlikely(q >= indices))
+		{
+			q += inv3;
+			if(q >= indices)
+				q += inv3;
+		}
+		return indices + 2;
+		//return indices / 6 + 2;
 	}
-
-	switch (pipe) {
-	case PIPE_FORMAT_R8_UNORM:
-	case PIPE_FORMAT_R32_FLOAT:
-	case PIPE_FORMAT_R16_FLOAT:
-	case PIPE_FORMAT_R16_SSCALED:
-		*ncomp = 1;
-		break;
-	case PIPE_FORMAT_R8G8_UNORM:
-	case PIPE_FORMAT_R32G32_FLOAT:
-	case PIPE_FORMAT_R16G16_FLOAT:
-	case PIPE_FORMAT_R16G16_SSCALED:
-		*ncomp = 2;
-		break;
-	case PIPE_FORMAT_R8G8B8_UNORM:
-	case PIPE_FORMAT_R32G32B32_FLOAT:
-	case PIPE_FORMAT_R16G16B16_FLOAT:
-	case PIPE_FORMAT_R16G16B16_SSCALED:
-		*ncomp = 3;
-		break;
-	case PIPE_FORMAT_R8G8B8A8_UNORM:
-	case PIPE_FORMAT_R32G32B32A32_FLOAT:
-	case PIPE_FORMAT_R16G16B16A16_FLOAT:
-	case PIPE_FORMAT_R16G16B16A16_SSCALED:
-		*ncomp = 4;
-		break;
+	// guess that indexed quads are created by successive connections, since a closed mesh seems unlikely
+	case PIPE_PRIM_QUADS:
+		return (indices >> 1) + 2;
+	//	return (indices >> 2) + 2; // if it is a closed mesh
 	default:
-		NOUVEAU_ERR("Unknown format %s\n", util_format_name(pipe));
-		return 1;
+		return indices;
 	}
-
-	return 0;
 }
 
-static boolean
-nvfx_vbo_set_idxbuf(struct nvfx_context *nvfx, struct pipe_resource *ib,
-		    unsigned ib_size)
+static unsigned nvfx_decide_upload_mode(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
-	unsigned type;
-
-	if (!ib) {
-		nvfx->idxbuf_buffer = NULL;
-		nvfx->idxbuf_format = 0xdeadbeef;
-		return FALSE;
+	struct nvfx_context* nvfx = nvfx_context(pipe);
+	unsigned hardware_cost = 0;
+	unsigned inline_cost = 0;
+	unsigned unique_vertices;
+	unsigned upload_mode;
+	if (info->indexed)
+		unique_vertices = util_guess_unique_indices_count(info->mode, info->count);
+	else
+		unique_vertices = info->count;
+
+	/* Here we try to figure out if we are better off writing vertex data directly on the FIFO,
+	 * or create hardware buffer objects and pointing the hardware to them.
+	 *
+	 * This is done by computing the total memcpy cost of each option, ignoring uploads
+	 * if we think that the buffer is static and thus the upload cost will be amortized over
+	 * future draw calls.
+	 *
+	 * For instance, if everything looks static, we will always create buffer objects, while if
+	 * everything is a user buffer and we are not doing indexed drawing, we never do.
+	 *
+	 * Other interesting cases are where a small user vertex buffer, but a huge user index buffer,
+	 * where we will upload the vertex buffer, so that we can use hardware index lookup, and
+	 * the opposite case, where we instead do index lookup in software to avoid uploading
+	 * a huge amount of vertex data that is not going to be used.
+	 *
+	 * Otherwise, we generally move to the GPU the after it has been pushed
+	 * NVFX_STATIC_BUFFER_MIN_REUSE_TIMES times to the GPU without having
+	 * been updated with a transfer (or just the buffer having been destroyed).
+	 *
+	 * There is no special handling for user buffers, since applications can use
+	 * OpenGL VBOs in a one-shot fashion. OpenGL 3/4 core profile forces this
+	 * by the way.
+	 *
+	 * Note that currently we don't support only putting some data on the FIFO, and
+	 * some on vertex buffers (constant and instanced data is independent from this).
+	 *
+	 * nVidia doesn't seem to do this either, even though it should be at least
+	 * doable with VTX_ATTR and possibly with VERTEX_DATA too if not indexed.
+	 */
+
+	for (unsigned i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; i++)
+	{
+		struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
+		struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
+		struct nvfx_buffer* buffer = nvfx_buffer(vb->buffer);
+		buffer->bytes_to_draw_until_static -= vbi->per_vertex_size * unique_vertices;
+		if (!nvfx_buffer_seems_static(buffer))
+		{
+			hardware_cost += buffer->dirty_end - buffer->dirty_begin;
+			if (!buffer->base.bo)
+				hardware_cost += nvfx->screen->buffer_allocation_cost;
+		}
+		inline_cost += vbi->per_vertex_size * info->count;
 	}
 
-	if (!nvfx->screen->index_buffer_reloc_flags || ib_size == 1)
-		return FALSE;
+	float best_index_cost_for_hardware_vertices_as_inline_cost = 0.0f;
+	boolean prefer_hardware_indices = FALSE;
+	unsigned index_inline_cost = 0;
+	unsigned index_hardware_cost = 0;
 
-	switch (ib_size) {
-	case 2:
-		type = NV34TCL_IDXBUF_FORMAT_TYPE_U16;
-		break;
-	case 4:
-		type = NV34TCL_IDXBUF_FORMAT_TYPE_U32;
-		break;
-	default:
-		return FALSE;
-	}
+	if (info->indexed)
+	{
+		index_inline_cost = nvfx->idxbuf.index_size * info->count;
+		if (nvfx->screen->index_buffer_reloc_flags
+			&& (nvfx->idxbuf.index_size == 2 || nvfx->idxbuf.index_size == 4)
+			&& !(nvfx->idxbuf.offset & (nvfx->idxbuf.index_size - 1)))
+		{
+			struct nvfx_buffer* buffer = nvfx_buffer(nvfx->idxbuf.buffer);
+			buffer->bytes_to_draw_until_static -= index_inline_cost;
 
-	if (ib != nvfx->idxbuf_buffer ||
-	    type != nvfx->idxbuf_format) {
-		nvfx->dirty |= NVFX_NEW_ARRAYS;
-		nvfx->idxbuf_buffer = ib;
-		nvfx->idxbuf_format = type;
-	}
+			prefer_hardware_indices = TRUE;
 
-	return TRUE;
-}
+			if (!nvfx_buffer_seems_static(buffer))
+			{
+				index_hardware_cost = buffer->dirty_end - buffer->dirty_begin;
+				if (!buffer->base.bo)
+					index_hardware_cost += nvfx->screen->buffer_allocation_cost;
+			}
 
-// type must be floating point
-static inline void
-nvfx_vbo_static_attrib(struct nvfx_context *nvfx,
-		       int attrib, struct pipe_vertex_element *ve,
-		       struct pipe_vertex_buffer *vb, unsigned ncomp)
-{
-	struct pipe_transfer *transfer;
-	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	void *map;
-	float *v;
-
-	map  = pipe_buffer_map(&nvfx->pipe, vb->buffer, PIPE_TRANSFER_READ, &transfer);
-	map = (uint8_t *) map + vb->buffer_offset + ve->src_offset;
-
-	v = map;
-
-	switch (ncomp) {
-	case 4:
-		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_4F_X(attrib), 4));
-		OUT_RING(chan, fui(v[0]));
-		OUT_RING(chan, fui(v[1]));
-		OUT_RING(chan,  fui(v[2]));
-		OUT_RING(chan,  fui(v[3]));
-		break;
-	case 3:
-		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_3F_X(attrib), 3));
-		OUT_RING(chan,  fui(v[0]));
-		OUT_RING(chan,  fui(v[1]));
-		OUT_RING(chan,  fui(v[2]));
-		break;
-	case 2:
-		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_2F_X(attrib), 2));
-		OUT_RING(chan,  fui(v[0]));
-		OUT_RING(chan,  fui(v[1]));
-		break;
-	case 1:
-		OUT_RING(chan, RING_3D(NV34TCL_VTX_ATTR_1F(attrib), 1));
-		OUT_RING(chan,  fui(v[0]));
-		break;
+			if ((float) index_inline_cost < (float) index_hardware_cost * nvfx->screen->inline_cost_per_hardware_cost)
+			{
+				best_index_cost_for_hardware_vertices_as_inline_cost = (float) index_inline_cost;
+			}
+			else
+			{
+				best_index_cost_for_hardware_vertices_as_inline_cost = (float) index_hardware_cost * nvfx->screen->inline_cost_per_hardware_cost;
+				prefer_hardware_indices = TRUE;
+			}
+		}
 	}
 
-	pipe_buffer_unmap(&nvfx->pipe, vb->buffer, transfer);
+	/* let's finally figure out which of the 3 paths we want to take */
+	if ((float) (inline_cost + index_inline_cost) > ((float) hardware_cost * nvfx->screen->inline_cost_per_hardware_cost + best_index_cost_for_hardware_vertices_as_inline_cost))
+		upload_mode = 1 + prefer_hardware_indices;
+	else
+		upload_mode = 0;
+
+#ifdef DEBUG
+        if (unlikely(nvfx->screen->trace_draw))
+          {
+                  fprintf(stderr, "DRAW");
+                  if (info->indexed)
+                  {
+                          fprintf(stderr, "_IDX%u", nvfx->idxbuf.index_size);
+                          if (info->index_bias)
+                                  fprintf(stderr, " biased %u", info->index_bias);
+                          fprintf(stderr, " idxrange %u -> %u", info->min_index, info->max_index);
+                  }
+                  if (info->instance_count > 1)
+                          fprintf(stderr, " %u instances from %u", info->instance_count, info->indexed);
+                  fprintf(stderr, " start %u count %u prim %u", info->start, info->count, info->mode);
+                  if (!upload_mode)
+                          fprintf(stderr, " -> inline vertex data");
+                  else if (upload_mode == 2 || !info->indexed)
+                          fprintf(stderr, " -> buffer range");
+                  else
+                          fprintf(stderr, " -> inline indices");
+                  fprintf(stderr, " [ivtx %u hvtx %u iidx %u hidx %u bidx %f] <", inline_cost, hardware_cost, index_inline_cost, index_hardware_cost, best_index_cost_for_hardware_vertices_as_inline_cost);
+                  for (unsigned i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; ++i)
+                  {
+                          struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
+                          struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
+                          struct nvfx_buffer* buffer = nvfx_buffer(vb->buffer);
+                          if (i)
+                                  fprintf(stderr, ", ");
+                          fprintf(stderr, "%p%s left %Li", buffer, buffer->last_update_static ? " static" : "", buffer->bytes_to_draw_until_static);
+                  }
+                  fprintf(stderr, ">\n");
+          }
+#endif
+
+	return upload_mode;
 }
 
-static void
-nvfx_draw_arrays(struct pipe_context *pipe,
-		 unsigned mode, unsigned start, unsigned count)
+void nvfx_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nvfx_screen *screen = nvfx->screen;
-	struct nouveau_channel *chan = screen->base.channel;
-	unsigned restart = 0;
-
-	nvfx_vbo_set_idxbuf(nvfx, NULL, 0);
-	if (nvfx->screen->force_swtnl || !nvfx_state_validate(nvfx)) {
-		nvfx_draw_elements_swtnl(pipe, NULL, 0, 0,
-                                           mode, start, count);
-                return;
-	}
+	unsigned upload_mode = 0;
 
-	while (count) {
-		unsigned vc, nr, avail;
+	if (!nvfx->vtxelt->needs_translate)
+		upload_mode = nvfx_decide_upload_mode(pipe, info);
 
-		nvfx_state_emit(nvfx);
+	nvfx->use_index_buffer = upload_mode > 1;
 
-		avail = AVAIL_RING(chan);
-		avail -= 16 + (avail >> 10); /* for the BEGIN_RING_NIs, conservatively assuming one every 1024, plus 16 for safety */
+	if ((upload_mode > 0) != nvfx->use_vertex_buffers)
+	{
+		nvfx->use_vertex_buffers = (upload_mode > 0);
+		nvfx->dirty |= NVFX_NEW_ARRAYS;
+		nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
+	}
 
-		vc = nouveau_vbuf_split(avail, 6, 256,
-					mode, start, count, &restart);
-		if (!vc) {
-			FIRE_RING(chan);
-			continue;
+	if (upload_mode > 0)
+	{
+		for (unsigned i = 0; i < nvfx->vtxelt->num_per_vertex_buffer_infos; i++)
+		{
+			struct nvfx_per_vertex_buffer_info* vbi = &nvfx->vtxelt->per_vertex_buffer_info[i];
+			struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[vbi->vertex_buffer_index];
+			nvfx_buffer_upload(nvfx_buffer(vb->buffer));
 		}
 
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, nvgl_primitive(mode));
+		if (upload_mode > 1)
+		{
+			nvfx_buffer_upload(nvfx_buffer(nvfx->idxbuf.buffer));
 
-		nr = (vc & 0xff);
-		if (nr) {
-			OUT_RING(chan, RING_3D(NV34TCL_VB_VERTEX_BATCH, 1));
-			OUT_RING  (chan, ((nr - 1) << 24) | start);
-			start += nr;
+			if (unlikely(info->index_bias != nvfx->base_vertex))
+			{
+				nvfx->base_vertex = info->index_bias;
+				nvfx->dirty |= NVFX_NEW_ARRAYS;
+			}
 		}
-
-		nr = vc >> 8;
-		while (nr) {
-			unsigned push = nr > 2047 ? 2047 : nr;
-
-			nr -= push;
-
-			OUT_RING(chan, RING_3D_NI(NV34TCL_VB_VERTEX_BATCH, push));
-			while (push--) {
-				OUT_RING(chan, ((0x100 - 1) << 24) | start);
-				start += 0x100;
+		else
+		{
+			if (unlikely(info->start < nvfx->base_vertex && nvfx->base_vertex))
+			{
+				nvfx->base_vertex = 0;
+				nvfx->dirty |= NVFX_NEW_ARRAYS;
 			}
 		}
-
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, 0);
-
-		count -= vc;
-		start = restart;
 	}
 
-	pipe->flush(pipe, 0, NULL);
+	if (nvfx->screen->force_swtnl || !nvfx_state_validate(nvfx))
+		nvfx_draw_vbo_swtnl(pipe, info);
+	else
+		nvfx_push_vbo(pipe, info);
 }
 
-static INLINE void
-nvfx_draw_elements_u08(struct nvfx_context *nvfx, void *ib,
-		       unsigned mode, unsigned start, unsigned count)
+boolean
+nvfx_vbo_validate(struct nvfx_context *nvfx)
 {
-	struct nvfx_screen *screen = nvfx->screen;
-	struct nouveau_channel *chan = screen->base.channel;
+	struct nouveau_channel* chan = nvfx->screen->base.channel;
+	int i;
+	int elements = MAX2(nvfx->vtxelt->num_elements, nvfx->hw_vtxelt_nr);
+	unsigned vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD;
 
-	while (count) {
-		uint8_t *elts = (uint8_t *)ib + start;
-		unsigned vc, push, restart = 0, avail;
+	if (!elements)
+		return TRUE;
 
-		nvfx_state_emit(nvfx);
+	MARK_RING(chan, (5 + 2) * 16 + 2 + 11, 16 + 2);
+	for(unsigned i = 0; i < nvfx->vtxelt->num_constant; ++i)
+	{
+		struct nvfx_low_frequency_element *ve = &nvfx->vtxelt->constant[i];
+		struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
+		struct nvfx_buffer* buffer = nvfx_buffer(vb->buffer);
+		float v[4];
+		ve->fetch_rgba_float(v, buffer->data + vb->buffer_offset + ve->src_offset, 0, 0);
+		nvfx_emit_vtx_attr(chan, ve->idx, v, ve->ncomp);
+	}
 
-		avail = AVAIL_RING(chan);
-		avail -= 16 + (avail >> 10); /* for the BEGIN_RING_NIs, conservatively assuming one every 1024, plus 16 for safety */
 
-		vc = nouveau_vbuf_split(avail, 6, 2,
-					mode, start, count, &restart);
-		if (vc == 0) {
-			FIRE_RING(chan);
-			continue;
-		}
-		count -= vc;
+	OUT_RING(chan, RING_3D(NV34TCL_VTXFMT(0), elements));
+	if(nvfx->use_vertex_buffers)
+	{
+		unsigned idx = 0;
+		for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) {
+			struct nvfx_per_vertex_element *ve = &nvfx->vtxelt->per_vertex[i];
+			struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
 
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, nvgl_primitive(mode));
+			if(idx != ve->idx)
+			{
+				assert(idx < ve->idx);
+				OUT_RINGp(chan, &nvfx->vtxelt->vtxfmt[idx], ve->idx - idx);
+				idx = ve->idx;
+			}
 
-		if (vc & 1) {
-			OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1));
-			OUT_RING  (chan, elts[0]);
-			elts++; vc--;
+			OUT_RING(chan, nvfx->vtxelt->vtxfmt[idx] | (vb->stride << NV34TCL_VTXFMT_STRIDE_SHIFT));
+			++idx;
 		}
+		if(idx != nvfx->vtxelt->num_elements)
+			OUT_RINGp(chan, &nvfx->vtxelt->vtxfmt[idx], nvfx->vtxelt->num_elements - idx);
+	}
+	else
+		OUT_RINGp(chan, nvfx->vtxelt->vtxfmt, nvfx->vtxelt->num_elements);
 
-		while (vc) {
-			unsigned i;
-
-			push = MIN2(vc, 2047 * 2);
-
-			OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1));
-			for (i = 0; i < push; i+=2)
-				OUT_RING(chan, (elts[i+1] << 16) | elts[i]);
+	for(i = nvfx->vtxelt->num_elements; i < elements; ++i)
+		OUT_RING(chan, NV34TCL_VTXFMT_TYPE_32_FLOAT);
 
-			vc -= push;
-			elts += push;
+	if(nvfx->is_nv4x) {
+		unsigned i;
+		/* seems to be some kind of cache flushing */
+		for(i = 0; i < 3; ++i) {
+			OUT_RING(chan, RING_3D(0x1718, 1));
+			OUT_RING(chan, 0);
 		}
-
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, 0);
-
-		start = restart;
 	}
-}
-
-static INLINE void
-nvfx_draw_elements_u16(struct nvfx_context *nvfx, void *ib,
-		       unsigned mode, unsigned start, unsigned count)
-{
-	struct nvfx_screen *screen = nvfx->screen;
-	struct nouveau_channel *chan = screen->base.channel;
-
-	while (count) {
-		uint16_t *elts = (uint16_t *)ib + start;
-		unsigned vc, push, restart = 0, avail;
 
-		nvfx_state_emit(nvfx);
-
-		avail = AVAIL_RING(chan);
-		avail -= 16 + (avail >> 10); /* for the BEGIN_RING_NIs, conservatively assuming one every 1024, plus 16 for safety */
-
-		vc = nouveau_vbuf_split(avail, 6, 2,
-					mode, start, count, &restart);
-		if (vc == 0) {
-			FIRE_RING(chan);
-			continue;
-		}
-		count -= vc;
+	OUT_RING(chan, RING_3D(NV34TCL_VTXBUF_ADDRESS(0), elements));
+	if(nvfx->use_vertex_buffers)
+	{
+		unsigned idx = 0;
+		for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) {
+			struct nvfx_per_vertex_element *ve = &nvfx->vtxelt->per_vertex[i];
+			struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
+			struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
 
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, nvgl_primitive(mode));
+			for(; idx < ve->idx; ++idx)
+				OUT_RING(chan, 0);
 
-		if (vc & 1) {
-			OUT_RING(chan, RING_3D(NV34TCL_VB_ELEMENT_U32, 1));
-			OUT_RING  (chan, elts[0]);
-			elts++; vc--;
+			OUT_RELOC(chan, bo,
+					vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
+					vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
+					0, NV34TCL_VTXBUF_ADDRESS_DMA1);
+			++idx;
 		}
 
-		while (vc) {
-			unsigned i;
-
-			push = MIN2(vc, 2047 * 2);
-
-			OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U16, push >> 1));
-			for (i = 0; i < push; i+=2)
-				OUT_RING(chan, (elts[i+1] << 16) | elts[i]);
-
-			vc -= push;
-			elts += push;
-		}
+		for(; idx < elements; ++idx)
+			OUT_RING(chan, 0);
+	}
+	else
+	{
+		for (i = 0; i < elements; i++)
+			OUT_RING(chan, 0);
+	}
 
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, 0);
+	OUT_RING(chan, RING_3D(0x1710, 1));
+	OUT_RING(chan, 0);
 
-		start = restart;
-	}
+	nvfx->hw_vtxelt_nr = nvfx->vtxelt->num_elements;
+	return TRUE;
 }
 
-static INLINE void
-nvfx_draw_elements_u32(struct nvfx_context *nvfx, void *ib,
-		       unsigned mode, unsigned start, unsigned count)
+void
+nvfx_vbo_relocate(struct nvfx_context *nvfx)
 {
-	struct nvfx_screen *screen = nvfx->screen;
-	struct nouveau_channel *chan = screen->base.channel;
-
-	while (count) {
-		uint32_t *elts = (uint32_t *)ib + start;
-		unsigned vc, push, restart = 0, avail;
-
-		nvfx_state_emit(nvfx);
-
-		avail = AVAIL_RING(chan);
-		avail -= 16 + (avail >> 10); /* for the BEGIN_RING_NIs, conservatively assuming one every 1024, plus 16 for safety */
-
-		vc = nouveau_vbuf_split(avail, 5, 1,
-					mode, start, count, &restart);
-		if (vc == 0) {
-			FIRE_RING(chan);
-			continue;
-		}
-		count -= vc;
-
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, nvgl_primitive(mode));
-
-		while (vc) {
-			push = MIN2(vc, 2047);
-
-			OUT_RING(chan, RING_3D_NI(NV34TCL_VB_ELEMENT_U32, push));
-			OUT_RINGp    (chan, elts, push);
-
-			vc -= push;
-			elts += push;
-		}
+        if(!nvfx->use_vertex_buffers)
+                return;
 
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, 0);
+	struct nouveau_channel* chan = nvfx->screen->base.channel;
+	unsigned vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
+	int i;
 
-		start = restart;
+	MARK_RING(chan, 2 * 16 + 3, 2 * 16 + 3);
+        for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) {
+                struct nvfx_per_vertex_element *ve = &nvfx->vtxelt->per_vertex[i];
+                struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
+                struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
+
+                OUT_RELOC(chan, bo, RING_3D(NV34TCL_VTXBUF_ADDRESS(ve->idx), 1),
+				vb_flags, 0, 0);
+                OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset + nvfx->base_vertex * vb->stride,
+				vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
+				0, NV34TCL_VTXBUF_ADDRESS_DMA1);
 	}
 }
 
 static void
-nvfx_draw_elements_inline(struct pipe_context *pipe,
-			  struct pipe_resource *ib,
-			  unsigned ib_size, int ib_bias,
-			  unsigned mode, unsigned start, unsigned count)
+nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags)
 {
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct pipe_transfer *transfer;
-	void *map;
-
-	map = pipe_buffer_map(pipe, ib, PIPE_TRANSFER_READ, &transfer);
-	if (!ib) {
-		NOUVEAU_ERR("failed mapping ib\n");
-		return;
-	}
+	struct nouveau_channel* chan = nvfx->screen->base.channel;
+	unsigned ib_format = (nvfx->idxbuf.index_size == 2) ? NV34TCL_IDXBUF_FORMAT_TYPE_U16 : NV34TCL_IDXBUF_FORMAT_TYPE_U32;
+	struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf.buffer)->bo;
+	ib_flags |= nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD;
 
-	assert(ib_bias == 0);
-
-	switch (ib_size) {
-	case 1:
-		nvfx_draw_elements_u08(nvfx, map, mode, start, count);
-		break;
-	case 2:
-		nvfx_draw_elements_u16(nvfx, map, mode, start, count);
-		break;
-	case 4:
-		nvfx_draw_elements_u32(nvfx, map, mode, start, count);
-		break;
-	default:
-		NOUVEAU_ERR("invalid idxbuf fmt %d\n", ib_size);
-		break;
-	}
+	assert(nvfx->screen->index_buffer_reloc_flags);
 
-	pipe_buffer_unmap(pipe, ib, transfer);
+	MARK_RING(chan, 3, 3);
+	if(ib_flags & NOUVEAU_BO_DUMMY)
+		OUT_RELOC(chan, bo, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2), ib_flags, 0, 0);
+	else
+		OUT_RING(chan, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2));
+	OUT_RELOC(chan, bo, nvfx->idxbuf.offset + 1, ib_flags | NOUVEAU_BO_LOW, 0, 0);
+	OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR,
+			0, NV34TCL_IDXBUF_FORMAT_DMA1);
 }
 
-static void
-nvfx_draw_elements_vbo(struct pipe_context *pipe,
-		       unsigned mode, unsigned start, unsigned count)
+void
+nvfx_idxbuf_validate(struct nvfx_context* nvfx)
 {
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nvfx_screen *screen = nvfx->screen;
-	struct nouveau_channel *chan = screen->base.channel;
-	unsigned restart = 0;
-
-	while (count) {
-		unsigned nr, vc, avail;
-
-		nvfx_state_emit(nvfx);
+	nvfx_idxbuf_emit(nvfx, 0);
+}
 
-		avail = AVAIL_RING(chan);
-		avail -= 16 + (avail >> 10); /* for the BEGIN_RING_NIs, conservatively assuming one every 1024, plus 16 for safety */
+void
+nvfx_idxbuf_relocate(struct nvfx_context* nvfx)
+{
+	nvfx_idxbuf_emit(nvfx, NOUVEAU_BO_DUMMY);
+}
 
-		vc = nouveau_vbuf_split(avail, 6, 256,
-					mode, start, count, &restart);
-		if (!vc) {
-			FIRE_RING(chan);
-			continue;
-		}
+unsigned nvfx_vertex_formats[PIPE_FORMAT_COUNT] =
+{
+	[PIPE_FORMAT_R32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
+	[PIPE_FORMAT_R32G32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
+	[PIPE_FORMAT_R32G32B32A32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
+	[PIPE_FORMAT_R32G32B32_FLOAT] = NV34TCL_VTXFMT_TYPE_32_FLOAT,
+	[PIPE_FORMAT_R16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
+	[PIPE_FORMAT_R16G16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
+	[PIPE_FORMAT_R16G16B16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
+	[PIPE_FORMAT_R16G16B16A16_FLOAT] = NV34TCL_VTXFMT_TYPE_16_FLOAT,
+	[PIPE_FORMAT_R8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
+	[PIPE_FORMAT_R8G8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
+	[PIPE_FORMAT_R8G8B8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
+	[PIPE_FORMAT_R8G8B8A8_UNORM] = NV34TCL_VTXFMT_TYPE_8_UNORM,
+	[PIPE_FORMAT_R8G8B8A8_USCALED] = NV34TCL_VTXFMT_TYPE_8_USCALED,
+	[PIPE_FORMAT_R16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
+	[PIPE_FORMAT_R16G16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
+	[PIPE_FORMAT_R16G16B16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
+	[PIPE_FORMAT_R16G16B16A16_SNORM] = NV34TCL_VTXFMT_TYPE_16_SNORM,
+	[PIPE_FORMAT_R16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
+	[PIPE_FORMAT_R16G16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
+	[PIPE_FORMAT_R16G16B16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
+	[PIPE_FORMAT_R16G16B16A16_SSCALED] = NV34TCL_VTXFMT_TYPE_16_SSCALED,
+};
+
+static void *
+nvfx_vtxelts_state_create(struct pipe_context *pipe,
+			  unsigned num_elements,
+			  const struct pipe_vertex_element *elements)
+{
+	struct nvfx_context* nvfx = nvfx_context(pipe);
+	struct nvfx_vtxelt_state *cso = CALLOC_STRUCT(nvfx_vtxelt_state);
+        struct translate_key transkey;
+        unsigned per_vertex_size[16];
+        memset(per_vertex_size, 0, sizeof(per_vertex_size));
+
+        unsigned vb_compacted_index[16];
+
+	assert(num_elements < 16); /* not doing fallbacks yet */
+
+	memcpy(cso->pipe, elements, num_elements * sizeof(elements[0]));
+	cso->num_elements = num_elements;
+	cso->needs_translate = FALSE;
+
+	transkey.nr_elements = 0;
+	transkey.output_stride = 0;
+
+	for(unsigned i = 0; i < num_elements; ++i)
+        {
+		const struct pipe_vertex_element* ve = &elements[i];
+		if(!ve->instance_divisor)
+                        per_vertex_size[ve->vertex_buffer_index] += util_format_get_stride(ve->src_format, 1);
+        }
+
+        for(unsigned i = 0; i < 16; ++i)
+        {
+                if(per_vertex_size[i])
+                {
+                        unsigned idx = cso->num_per_vertex_buffer_infos++;
+                        cso->per_vertex_buffer_info[idx].vertex_buffer_index = i;
+                        cso->per_vertex_buffer_info[idx].per_vertex_size = per_vertex_size[i];
+                        vb_compacted_index[i] = idx;
+                }
+        }
+
+	for(unsigned i = 0; i < num_elements; ++i)
+	{
+		const struct pipe_vertex_element* ve = &elements[i];
+		unsigned type = nvfx_vertex_formats[ve->src_format];
+		unsigned ncomp = util_format_get_nr_components(ve->src_format);
 
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, nvgl_primitive(mode));
+		//if(ve->frequency != PIPE_ELEMENT_FREQUENCY_PER_VERTEX)
+		if(ve->instance_divisor)
+		{
+			struct nvfx_low_frequency_element* lfve;
+			cso->vtxfmt[i] = NV34TCL_VTXFMT_TYPE_32_FLOAT;
+
+			//if(ve->frequency == PIPE_ELEMENT_FREQUENCY_CONSTANT)
+			if(0)
+				lfve = &cso->constant[cso->num_constant++];
+			else
+			{
+				lfve = &cso->per_instance[cso->num_per_instance++].base;
+				((struct nvfx_per_instance_element*)lfve)->instance_divisor = ve->instance_divisor;
+			}
 
-		nr = (vc & 0xff);
-		if (nr) {
-			OUT_RING(chan, RING_3D(NV34TCL_VB_INDEX_BATCH, 1));
-			OUT_RING  (chan, ((nr - 1) << 24) | start);
-			start += nr;
+                        lfve->idx = i;
+                        lfve->vertex_buffer_index = ve->vertex_buffer_index;
+                        lfve->src_offset = ve->src_offset;
+                        lfve->fetch_rgba_float = util_format_description(ve->src_format)->fetch_rgba_float;
+                        lfve->ncomp = ncomp;
 		}
-
-		nr = vc >> 8;
-		while (nr) {
-			unsigned push = nr > 2047 ? 2047 : nr;
-
-			nr -= push;
-
-			OUT_RING(chan, RING_3D_NI(NV34TCL_VB_INDEX_BATCH, push));
-			while (push--) {
-				OUT_RING(chan, ((0x100 - 1) << 24) | start);
-				start += 0x100;
+		else
+		{
+			unsigned idx;
+
+			idx = cso->num_per_vertex++;
+			cso->per_vertex[idx].idx = i;
+			cso->per_vertex[idx].vertex_buffer_index = ve->vertex_buffer_index;
+			cso->per_vertex[idx].src_offset = ve->src_offset;
+
+			idx = transkey.nr_elements++;
+			transkey.element[idx].input_format = ve->src_format;
+			transkey.element[idx].input_buffer = vb_compacted_index[ve->vertex_buffer_index];
+			transkey.element[idx].input_offset = ve->src_offset;
+			transkey.element[idx].instance_divisor = 0;
+			transkey.element[idx].type = TRANSLATE_ELEMENT_NORMAL;
+			if(type)
+			{
+				transkey.element[idx].output_format = ve->src_format;
+				cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | type;
+			}
+			else
+			{
+				unsigned float32[4] = {PIPE_FORMAT_R32_FLOAT, PIPE_FORMAT_R32G32_FLOAT, PIPE_FORMAT_R32G32B32_FLOAT, PIPE_FORMAT_R32G32B32A32_FLOAT};
+				transkey.element[idx].output_format = float32[ncomp - 1];
+				cso->needs_translate = TRUE;
+				cso->vtxfmt[i] = (ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | NV34TCL_VTXFMT_TYPE_32_FLOAT;
 			}
+			transkey.element[idx].output_offset = transkey.output_stride;
+			transkey.output_stride += (util_format_get_stride(transkey.element[idx].output_format, 1) + 3) & ~3;
 		}
+	}
 
-		OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-		OUT_RING  (chan, 0);
+	cso->translate = translate_generic_create(&transkey);
+	cso->vertex_length = transkey.output_stride >> 2;
+	cso->max_vertices_per_packet = 2047 / cso->vertex_length;
 
-		count -= vc;
-		start = restart;
-	}
+	return (void *)cso;
 }
 
 static void
-nvfx_draw_elements(struct pipe_context *pipe,
-		   struct pipe_resource *indexBuffer,
-		   unsigned indexSize, int indexBias,
-		   unsigned mode, unsigned start, unsigned count)
+nvfx_vtxelts_state_delete(struct pipe_context *pipe, void *hwcso)
 {
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	boolean idxbuf;
-
-	idxbuf = nvfx_vbo_set_idxbuf(nvfx, indexBuffer, indexSize);
-	if (nvfx->screen->force_swtnl || !nvfx_state_validate(nvfx)) {
-		nvfx_draw_elements_swtnl(pipe,
-		                         indexBuffer, indexSize, indexBias,
-		                         mode, start, count);
-		return;
-	}
-
-	if (idxbuf) {
-		nvfx_draw_elements_vbo(pipe, mode, start, count);
-	} else {
-		nvfx_draw_elements_inline(pipe,
-		                          indexBuffer, indexSize, indexBias,
-					  mode, start, count);
-	}
-
-	pipe->flush(pipe, 0, NULL);
+	FREE(hwcso);
 }
 
-void
-nvfx_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
+static void
+nvfx_vtxelts_state_bind(struct pipe_context *pipe, void *hwcso)
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
 
-	if (info->indexed && nvfx->idxbuf.buffer) {
-		unsigned offset;
-
-		assert(nvfx->idxbuf.offset % nvfx->idxbuf.index_size == 0);
-		offset = nvfx->idxbuf.offset / nvfx->idxbuf.index_size;
-
-		nvfx_draw_elements(pipe,
-				   nvfx->idxbuf.buffer,
-				   nvfx->idxbuf.index_size,
-				   info->index_bias,
-				   info->mode,
-				   info->start + offset,
-				   info->count);
-	}
-	else {
-		nvfx_draw_arrays(pipe,
-				info->mode,
-				info->start,
-				info->count);
-	}
+	nvfx->vtxelt = hwcso;
+	nvfx->use_vertex_buffers = -1;
+	nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
 }
 
-boolean
-nvfx_vbo_validate(struct nvfx_context *nvfx)
+static void
+nvfx_set_vertex_buffers(struct pipe_context *pipe, unsigned count,
+			const struct pipe_vertex_buffer *vb)
 {
-	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	struct pipe_resource *ib = nvfx->idxbuf_buffer;
-	unsigned ib_format = nvfx->idxbuf_format;
-	int i;
-	int elements = MAX2(nvfx->vtxelt->num_elements, nvfx->hw_vtxelt_nr);
-	uint32_t vtxfmt[16];
-	unsigned vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD;
-
-	if (!elements)
-		return TRUE;
-
-	nvfx->vbo_bo = 0;
-
-	MARK_RING(chan, (5 + 2) * 16 + 2 + 11, 16 + 2);
-	for (i = 0; i < nvfx->vtxelt->num_elements; i++) {
-		struct pipe_vertex_element *ve;
-		struct pipe_vertex_buffer *vb;
-		unsigned type, ncomp;
-
-		ve = &nvfx->vtxelt->pipe[i];
-		vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
-
-		if (nvfx_vbo_format_to_hw(ve->src_format, &type, &ncomp)) {
-			MARK_UNDO(chan);
-			nvfx->fallback_swtnl |= NVFX_NEW_ARRAYS;
-			return FALSE;
-		}
+	struct nvfx_context *nvfx = nvfx_context(pipe);
 
-		if (!vb->stride && type == NV34TCL_VTXFMT_TYPE_FLOAT) {
-			nvfx_vbo_static_attrib(nvfx, i, ve, vb, ncomp);
-			vtxfmt[i] = type;
-		} else {
-			vtxfmt[i] = ((vb->stride << NV34TCL_VTXFMT_STRIDE_SHIFT) |
-				(ncomp << NV34TCL_VTXFMT_SIZE_SHIFT) | type);
-			nvfx->vbo_bo |= (1 << i);
-		}
+	for(unsigned i = 0; i < count; ++i)
+	{
+		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, vb[i].buffer);
+		nvfx->vtxbuf[i].buffer_offset = vb[i].buffer_offset;
+		nvfx->vtxbuf[i].max_index = vb[i].max_index;
+		nvfx->vtxbuf[i].stride = vb[i].stride;
 	}
 
-	for(; i < elements; ++i)
-		vtxfmt[i] = NV34TCL_VTXFMT_TYPE_FLOAT;
-
-	OUT_RING(chan, RING_3D(NV34TCL_VTXFMT(0), elements));
-	OUT_RINGp(chan, vtxfmt, elements);
-
-	if(nvfx->is_nv4x) {
-		unsigned i;
-		/* seems to be some kind of cache flushing */
-		for(i = 0; i < 3; ++i) {
-			OUT_RING(chan, RING_3D(0x1718, 1));
-			OUT_RING(chan, 0);
-		}
-	}
+	for(unsigned i = count; i < nvfx->vtxbuf_nr; ++i)
+		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, 0);
 
-	OUT_RING(chan, RING_3D(NV34TCL_VTXBUF_ADDRESS(0), elements));
-	for (i = 0; i < nvfx->vtxelt->num_elements; i++) {
-		struct pipe_vertex_element *ve;
-		struct pipe_vertex_buffer *vb;
+	nvfx->vtxbuf_nr = count;
+	nvfx->use_vertex_buffers = -1;
+	nvfx->draw_dirty |= NVFX_NEW_ARRAYS;
+}
 
-		ve = &nvfx->vtxelt->pipe[i];
-		vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
+static void
+nvfx_set_index_buffer(struct pipe_context *pipe,
+		      const struct pipe_index_buffer *ib)
+{
+	struct nvfx_context *nvfx = nvfx_context(pipe);
 
-		if (!(nvfx->vbo_bo & (1 << i)))
-			OUT_RING(chan, 0);
-		else
-		{
-			struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
-			OUT_RELOC(chan, bo,
-				 vb->buffer_offset + ve->src_offset,
-				 vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
-				 0, NV34TCL_VTXBUF_ADDRESS_DMA1);
-		}
+	if(ib)
+	{
+		pipe_resource_reference(&nvfx->idxbuf.buffer, ib->buffer);
+		nvfx->idxbuf.index_size = ib->index_size;
+		nvfx->idxbuf.offset = ib->offset;
 	}
-
-        for (; i < elements; i++)
-		OUT_RING(chan, 0);
-
-	OUT_RING(chan, RING_3D(0x1710, 1));
-	OUT_RING(chan, 0);
-
-	if (ib) {
-		unsigned ib_flags = nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD;
-		struct nouveau_bo* bo = nvfx_resource(ib)->bo;
-
-		assert(nvfx->screen->index_buffer_reloc_flags);
-
-		OUT_RING(chan, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2));
-		OUT_RELOC(chan, bo, 0, ib_flags | NOUVEAU_BO_LOW, 0, 0);
-		OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR,
-				  0, NV34TCL_IDXBUF_FORMAT_DMA1);
+	else
+	{
+		pipe_resource_reference(&nvfx->idxbuf.buffer, 0);
+		nvfx->idxbuf.index_size = 0;
+		nvfx->idxbuf.offset = 0;
 	}
 
-	nvfx->hw_vtxelt_nr = nvfx->vtxelt->num_elements;
-	return TRUE;
+	nvfx->dirty |= NVFX_NEW_INDEX;
+	nvfx->draw_dirty |= NVFX_NEW_INDEX;
 }
 
 void
-nvfx_vbo_relocate(struct nvfx_context *nvfx)
+nvfx_init_vbo_functions(struct nvfx_context *nvfx)
 {
-	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	unsigned vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
-	int i;
+	nvfx->pipe.set_vertex_buffers = nvfx_set_vertex_buffers;
+	nvfx->pipe.set_index_buffer = nvfx_set_index_buffer;
 
-	MARK_RING(chan, 2 * 16 + 3, 2 * 16 + 3);
-	for(i = 0; i < nvfx->vtxelt->num_elements; ++i) {
-		if(nvfx->vbo_bo & (1 << i)) {
-			struct pipe_vertex_element *ve = &nvfx->vtxelt->pipe[i];
-			struct pipe_vertex_buffer *vb = &nvfx->vtxbuf[ve->vertex_buffer_index];
-			struct nouveau_bo* bo = nvfx_resource(vb->buffer)->bo;
-			OUT_RELOC(chan, bo, RING_3D(NV34TCL_VTXBUF_ADDRESS(i), 1),
-					vb_flags, 0, 0);
-			OUT_RELOC(chan, bo, vb->buffer_offset + ve->src_offset,
-					vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
-					0, NV34TCL_VTXBUF_ADDRESS_DMA1);
-		}
-	}
-
-	if(nvfx->idxbuf_buffer)
-	{
-		unsigned ib_flags = nvfx->screen->index_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
-		struct nouveau_bo* bo = nvfx_resource(nvfx->idxbuf_buffer)->bo;
-
-		assert(nvfx->screen->index_buffer_reloc_flags);
-
-		OUT_RELOC(chan, bo, RING_3D(NV34TCL_IDXBUF_ADDRESS, 2),
-				ib_flags, 0, 0);
-		OUT_RELOC(chan, bo, 0,
-				ib_flags | NOUVEAU_BO_LOW, 0, 0);
-		OUT_RELOC(chan, bo, nvfx->idxbuf_format,
-				ib_flags | NOUVEAU_BO_OR,
-				0, NV34TCL_IDXBUF_FORMAT_DMA1);
-	}
+	nvfx->pipe.create_vertex_elements_state = nvfx_vtxelts_state_create;
+	nvfx->pipe.delete_vertex_elements_state = nvfx_vtxelts_state_delete;
+	nvfx->pipe.bind_vertex_elements_state = nvfx_vtxelts_state_bind;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 24d9846310..939d2b83ae 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -10,6 +10,7 @@
 
 #include "nvfx_context.h"
 #include "nvfx_state.h"
+#include "nvfx_resource.h"
 
 /* TODO (at least...):
  *  1. Indexed consts  + ARL
@@ -874,7 +875,6 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 	struct nouveau_grobj *eng3d = screen->eng3d;
 	struct nvfx_vertex_program *vp;
 	struct pipe_resource *constbuf;
-	struct pipe_transfer *transfer = NULL;
 	boolean upload_code = FALSE, upload_data = FALSE;
 	int i;
 
@@ -983,11 +983,8 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 	if (vp->nr_consts) {
 		float *map = NULL;
 
-		if (constbuf) {
-			map = pipe_buffer_map(pipe, constbuf,
-					      PIPE_TRANSFER_READ,
-					      &transfer);
-		}
+		if (constbuf)
+			map = nvfx_buffer(constbuf)->data;
 
 		for (i = 0; i < vp->nr_consts; i++) {
 			struct nvfx_vertex_program_data *vpd = &vp->consts[i];
@@ -1005,9 +1002,6 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 			OUT_RING  (chan, i + vp->data->start);
 			OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
 		}
-
-		if (constbuf)
-			pipe_buffer_unmap(pipe, constbuf, transfer);
 	}
 
 	/* Upload vtxprog */
-- 
cgit v1.2.3


From 4d765f7fa3751eae00bbf2b6ee9710bf5bdf95d0 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 10 Aug 2010 23:09:53 +0200
Subject: nvfx: support proper shader linkage - adds glsl support

---
 src/gallium/drivers/nvfx/nvfx_context.h    |   1 +
 src/gallium/drivers/nvfx/nvfx_fragprog.c   | 204 ++++++++++++++++++++---------
 src/gallium/drivers/nvfx/nvfx_shader.h     |   1 +
 src/gallium/drivers/nvfx/nvfx_state.c      |  25 ++--
 src/gallium/drivers/nvfx/nvfx_state.h      |  24 ++++
 src/gallium/drivers/nvfx/nvfx_state_emit.c |   3 +-
 src/gallium/drivers/nvfx/nvfx_vertprog.c   |  41 ++++--
 7 files changed, 211 insertions(+), 88 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 8899bf991e..7ec6a4f412 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -45,6 +45,7 @@
 #define NVFX_NEW_VERTCONST	(1 << 14)
 #define NVFX_NEW_FRAGCONST	(1 << 15)
 #define NVFX_NEW_INDEX	(1 << 16)
+#define NVFX_NEW_SPRITE  (1 << 17)
 
 struct nvfx_rasterizer_state {
 	struct pipe_rasterizer_state pipe;
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index ae4fe3aa26..0a599c62a7 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -16,8 +16,6 @@
 struct nvfx_fpc {
 	struct nvfx_fragment_program *fp;
 
-	uint attrib_map[PIPE_MAX_SHADER_INPUTS];
-
 	unsigned r_temps;
 	unsigned r_temps_discard;
 	struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
@@ -36,6 +34,8 @@ struct nvfx_fpc {
 
 	struct nvfx_sreg imm[MAX_IMM];
 	unsigned nr_imm;
+
+	unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
 };
 
 static INLINE struct nvfx_sreg
@@ -111,6 +111,11 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
 		sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
 		sr |= (src.index << NVFX_FP_REG_SRC_SHIFT);
 		break;
+	case NVFXSR_RELOCATED:
+		sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
+		//printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
+		util_dynarray_append(&fpc->fp->slot_relocations[src.index], unsigned, fpc->inst_offset);
+		break;
 	case NVFXSR_CONST:
 		if (!fpc->have_const) {
 			grow_insns(fpc, 4);
@@ -241,8 +246,28 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
 
 	switch (fsrc->Register.File) {
 	case TGSI_FILE_INPUT:
-		src = nvfx_sr(NVFXSR_INPUT,
-			      fpc->attrib_map[fsrc->Register.Index]);
+		if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
+			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
+			src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
+		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
+			if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0)
+				src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
+			else if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 1)
+				src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
+			else
+				assert(0);
+		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
+			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
+			src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
+		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
+			/* TODO: check this has the correct values */
+			/* XXX: what do we do for nv30 here (assuming it lacks facing)?!  */
+			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
+			src = nvfx_sr(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
+		} else {
+			assert(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
+			src = nvfx_sr(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
+		}
 		break;
 	case TGSI_FILE_CONSTANT:
 		src = constant(fpc, fsrc->Register.Index, NULL);
@@ -610,48 +635,6 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 	return TRUE;
 }
 
-static boolean
-nvfx_fragprog_parse_decl_attrib(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
-				const struct tgsi_full_declaration *fdec)
-{
-	int hw;
-
-	switch (fdec->Semantic.Name) {
-	case TGSI_SEMANTIC_POSITION:
-		hw = NVFX_FP_OP_INPUT_SRC_POSITION;
-		break;
-	case TGSI_SEMANTIC_COLOR:
-		if (fdec->Semantic.Index == 0) {
-			hw = NVFX_FP_OP_INPUT_SRC_COL0;
-		} else
-		if (fdec->Semantic.Index == 1) {
-			hw = NVFX_FP_OP_INPUT_SRC_COL1;
-		} else {
-			NOUVEAU_ERR("bad colour semantic index\n");
-			return FALSE;
-		}
-		break;
-	case TGSI_SEMANTIC_FOG:
-		hw = NVFX_FP_OP_INPUT_SRC_FOGC;
-		break;
-	case TGSI_SEMANTIC_GENERIC:
-		if (fdec->Semantic.Index <= 7) {
-			hw = NVFX_FP_OP_INPUT_SRC_TC(fdec->Semantic.
-						     Index);
-		} else {
-			NOUVEAU_ERR("bad generic semantic index\n");
-			return FALSE;
-		}
-		break;
-	default:
-		NOUVEAU_ERR("bad input semantic\n");
-		return FALSE;
-	}
-
-	fpc->attrib_map[fdec->Range.First] = hw;
-	return TRUE;
-}
-
 static boolean
 nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 				const struct tgsi_full_declaration *fdec)
@@ -691,6 +674,15 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 {
 	struct tgsi_parse_context p;
 	int high_temp = -1, i;
+	struct util_semantic_set set;
+
+	fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->fp->pipe.tokens, TGSI_FILE_INPUT);
+	if(fpc->fp->num_slots > 8)
+		return FALSE;
+	util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, 8);
+	util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, 8);
+
+	memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
 
 	tgsi_parse_init(&p, fpc->fp->pipe.tokens);
 	while (!tgsi_parse_end_of_tokens(&p)) {
@@ -703,10 +695,6 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 			const struct tgsi_full_declaration *fdec;
 			fdec = &p.FullToken.FullDeclaration;
 			switch (fdec->Declaration.File) {
-			case TGSI_FILE_INPUT:
-				if (!nvfx_fragprog_parse_decl_attrib(nvfx, fpc, fdec))
-					goto out_err;
-				break;
 			case TGSI_FILE_OUTPUT:
 				if (!nvfx_fragprog_parse_decl_output(nvfx, fpc, fdec))
 					goto out_err;
@@ -805,7 +793,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 
 	/* Terminate final instruction */
 	if(fp->insn)
-                fp->insn[fpc->inst_offset] |= 0x00000001;
+		fp->insn[fpc->inst_offset] |= 0x00000001;
 
 	/* Append NOP + END instruction, may or may not be necessary. */
 	fpc->inst_offset = fp->insn_len;
@@ -881,9 +869,70 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG))
 		update = TRUE;
 
-	if(update) {
-		int offset;
+	struct nvfx_vertex_program* vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
+	if (fp->last_vp_id != vp->id) {
+		char* vp_sem_table = vp->generic_to_fp_input;
+		unsigned char* fp_semantics = fp->slot_to_generic;
+		unsigned diff = 0;
+		fp->last_vp_id = nvfx->vertprog->id;
+		unsigned char* cur_slots = fp->slot_to_fp_input;
+		for(unsigned i = 0; i < fp->num_slots; ++i) {
+			unsigned char slot_mask = vp_sem_table[fp_semantics[i]];
+			diff |= (slot_mask >> 4) & (slot_mask ^ cur_slots[i]);
+		}
+
+		if(diff)
+		{
+			for(unsigned i = 0; i < fp->num_slots; ++i) {
+				/* if 0xff, then this will write to the dummy value at fp->last_layout_mask[0] */
+				fp->slot_to_fp_input[i] = vp_sem_table[fp_semantics[i]] & 0xf;
+				//printf("fp: GENERIC[%i] from fpreg %i\n", fp_semantics[i], fp->slot_to_fp_input[i]);
+			}
+
+			fp->progs_left_with_obsolete_slot_assignments = fp->progs;
+			update = TRUE;
+		}
+	}
+
+	// last_sprite_coord_enable
+	unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
+	if(fp->last_sprite_coord_enable != sprite_coord_enable)
+	{
+		unsigned texcoord_mask = vp->texcoord_ouput_mask;
+		fp->last_sprite_coord_enable = sprite_coord_enable;
+		fp->point_sprite_control = 0;
+		for(unsigned i = 0; i < fp->num_slots; ++i) {
+			if((1 << fp->slot_to_generic[i]) & sprite_coord_enable)
+			{
+				unsigned fpin = fp->slot_to_fp_input[i];
+				//printf("sprite: slot %i generic %i had texcoord %i\n", i, fp->slot_to_generic[i], fpin - NVFX_FP_OP_INPUT_SRC_TC0);
+				if(fpin >= 0x0f)
+				{
+					unsigned tc = __builtin_ctz(~texcoord_mask);
+					texcoord_mask |= (1 << tc);
+					fp->slot_to_fp_input[i] = fpin = NVFX_FP_OP_INPUT_SRC_TC(tc);
+
+					fp->progs_left_with_obsolete_slot_assignments = fp->progs;
+					update = TRUE;
+				}
+				//printf("sprite: slot %i texcoord %i\n", i, fpin - NVFX_FP_OP_INPUT_SRC_TC0);
+				fp->point_sprite_control |= (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
+			}
+			else
+			{
+				unsigned fpin = fp->slot_to_fp_input[i];
+				if(!(vp->texcoord_ouput_mask & (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0))))
+				{
+					fp->slot_to_fp_input[i] = 0x0f;
 
+					fp->progs_left_with_obsolete_slot_assignments = fp->progs;
+					update = TRUE;
+				}
+			}
+		}
+	}
+
+	if(update) {
 		++fp->bo_prog_idx;
 		if(fp->bo_prog_idx >= fp->progs_per_bo)
 		{
@@ -893,10 +942,9 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			}
 			else
 			{
-				struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + fp->prog_size * fp->progs_per_bo, 16);
-				char *map, *buf;
-				int i;
-
+				struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
+				fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
+				memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
 				if(fp->fpbo)
 				{
 					fpbo->next = fp->fpbo->next;
@@ -906,12 +954,14 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 					fpbo->next = fpbo;
 				fp->fpbo = fpbo;
 				fpbo->bo = 0;
+				fp->progs += fp->progs_per_bo;
+				fp->progs_left_with_obsolete_slot_assignments += fp->progs_per_bo;
 				nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
 				nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
 
-				map = fpbo->bo->map;
-				buf = fpbo->insn;
-				for(i = 0; i < fp->progs_per_bo; ++i)
+				uint8_t* map = fpbo->bo->map;
+				uint8_t* buf = (uint8_t*)fpbo->insn;
+				for(unsigned i = 0; i < fp->progs_per_bo; ++i)
 				{
 					memcpy(buf, fp->insn, fp->insn_len * 4);
 					nvfx_fp_memcpy(map, fp->insn, fp->insn_len * 4);
@@ -922,7 +972,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			fp->bo_prog_idx = 0;
 		}
 
-		offset = fp->bo_prog_idx * fp->prog_size;
+		int offset = fp->bo_prog_idx * fp->prog_size;
+		uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
 
 		if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
 			struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
@@ -941,6 +992,25 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 				}
 			}
 		}
+
+		if(fp->progs_left_with_obsolete_slot_assignments) {
+			unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
+			for(unsigned i = 0; i < fp->num_slots; ++i) {
+				unsigned value = fp->slot_to_fp_input[i];;
+				if(value != fpbo_slots[i]) {
+					unsigned* p = (unsigned*)fp->slot_relocations[i].data;
+					unsigned* pend = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
+					for(; p != pend; ++p) {
+						unsigned off = *p;
+						unsigned dw = fp->insn[off];
+						dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
+						nvfx_fp_memcpy(&fpmap[*p], &dw, sizeof(dw));
+					}
+					fpbo_slots[i] = value;
+				}
+			}
+			--fp->progs_left_with_obsolete_slot_assignments;
+		}
 	}
 
 	if(update || (nvfx->dirty & NVFX_NEW_FRAGPROG)) {
@@ -960,6 +1030,13 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			OUT_RING(chan, fp->samplers);
 		}
 	}
+
+	if(nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_SPRITE))
+	{
+		WAIT_RING(chan, 2);
+		OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
+		OUT_RING(chan, fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization);
+	}
 }
 
 void
@@ -982,6 +1059,7 @@ void
 nvfx_fragprog_destroy(struct nvfx_context *nvfx,
 		      struct nvfx_fragment_program *fp)
 {
+	unsigned i;
 	struct nvfx_fragment_program_bo* fpbo = fp->fpbo;
 	if(fpbo)
 	{
@@ -996,7 +1074,9 @@ nvfx_fragprog_destroy(struct nvfx_context *nvfx,
 		while(fpbo != fp->fpbo);
 	}
 
+	for(i = 0; i < 8; ++i)
+		util_dynarray_fini(&fp->slot_relocations[i]);
+
 	if (fp->insn_len)
 		FREE(fp->insn);
 }
-
diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h
index 50830b3916..88cf91b95f 100644
--- a/src/gallium/drivers/nvfx/nvfx_shader.h
+++ b/src/gallium/drivers/nvfx/nvfx_shader.h
@@ -323,6 +323,7 @@
 #define NVFXSR_INPUT	2
 #define NVFXSR_TEMP	3
 #define NVFXSR_CONST	4
+#define NVFXSR_RELOCATED	5
 
 #define NVFX_COND_FL  0
 #define NVFX_COND_LT  1
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index 25d29720a8..c3addf1114 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -91,6 +91,7 @@ nvfx_rasterizer_state_create(struct pipe_context *pipe,
 	/*XXX: ignored:
 	 * 	point_smooth -nohw
 	 * 	multisample
+	 *     sprite_coord_origin
 	 */
 
 	sb_method(sb, NV34TCL_SHADE_MODEL, 1);
@@ -150,20 +151,6 @@ nvfx_rasterizer_state_create(struct pipe_context *pipe,
 		sb_data(sb, fui(cso->offset_units * 2));
 	}
 
-	sb_method(sb, NV34TCL_POINT_SPRITE, 1);
-	if (cso->point_quad_rasterization) {
-		unsigned psctl = (1 << 0), i;
-
-		for (i = 0; i < 8; i++) {
-			if ((cso->sprite_coord_enable >> i) & 1)
-				psctl |= (1 << (8 + i));
-		}
-
-		sb_data(sb, psctl);
-	} else {
-		sb_data(sb, 0);
-	}
-
 	rsso->pipe = *cso;
 	rsso->sb_len = sb_len(sb, rsso->sb);
 	return (void *)rsso;
@@ -189,6 +176,12 @@ nvfx_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
 			nvfx->dirty |= NVFX_NEW_STIPPLE;
 			nvfx->draw_dirty |= NVFX_NEW_STIPPLE;
 		}
+
+		if(((struct nvfx_rasterizer_state*)hwcso)->pipe.point_quad_rasterization != nvfx->rasterizer->pipe.point_quad_rasterization
+				|| ((struct nvfx_rasterizer_state*)hwcso)->pipe.sprite_coord_enable != nvfx->rasterizer->pipe.sprite_coord_enable)
+		{
+			nvfx->dirty |= NVFX_NEW_SPRITE;
+		}
 	}
 
 	nvfx->rasterizer = hwcso;
@@ -280,9 +273,13 @@ nvfx_vp_state_create(struct pipe_context *pipe,
 	struct nvfx_context *nvfx = nvfx_context(pipe);
 	struct nvfx_vertex_program *vp;
 
+	// TODO: use a 64-bit atomic here!
+	static unsigned long long id = 0;
+
 	vp = CALLOC(1, sizeof(struct nvfx_vertex_program));
 	vp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
 	vp->draw = draw_create_vertex_shader(nvfx->draw, &vp->pipe);
+	vp->id = ++id;
 
 	return (void *)vp;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
index 9ceb2577ec..e1fa3c7e04 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ b/src/gallium/drivers/nvfx/nvfx_state.h
@@ -4,6 +4,8 @@
 #include "pipe/p_state.h"
 #include "tgsi/tgsi_scan.h"
 #include "nouveau/nouveau_statebuf.h"
+#include "util/u_dynarray.h"
+#include "util/u_linkage.h"
 
 struct nvfx_vertex_program_exec {
 	uint32_t data[4];
@@ -18,6 +20,7 @@ struct nvfx_vertex_program_data {
 
 struct nvfx_vertex_program {
 	struct pipe_shader_state pipe;
+	unsigned long long id;
 
 	struct draw_vertex_shader *draw;
 
@@ -30,6 +33,9 @@ struct nvfx_vertex_program {
 	struct nvfx_vertex_program_data *consts;
 	unsigned nr_consts;
 
+	char generic_to_fp_input[256];
+	unsigned texcoord_ouput_mask;
+
 	struct nouveau_resource *exec;
 	unsigned exec_start;
 	struct nouveau_resource *data;
@@ -49,6 +55,7 @@ struct nvfx_fragment_program_data {
 struct nvfx_fragment_program_bo {
 	struct nvfx_fragment_program_bo* next;
 	struct nouveau_bo* bo;
+	unsigned char* slots;
 	char insn[] __attribute__((aligned(16)));
 };
 
@@ -58,6 +65,7 @@ struct nvfx_fragment_program {
 
 	boolean translated;
 	unsigned samplers;
+	unsigned point_sprite_control;
 
 	uint32_t *insn;
 	int       insn_len;
@@ -65,11 +73,27 @@ struct nvfx_fragment_program {
 	struct nvfx_fragment_program_data *consts;
 	unsigned nr_consts;
 
+	unsigned num_slots; /* how many input semantics? */
+	unsigned char slot_to_generic[8]; /* semantics */
+	unsigned char slot_to_fp_input[8]; /* current assignment of slots for each used semantic */
+	struct util_dynarray slot_relocations[8];
+
+	/* This is reset to progs on any relocation update, and decreases every time we
+	 * move to a new prog due to a constant update
+	 * When this is the same as progs, applying relocations is no longer necessary.
+	 */
+	unsigned progs_left_with_obsolete_slot_assignments;
+
+	unsigned long long last_vp_id;
+	unsigned last_sprite_coord_enable;
+
 	uint32_t fp_control;
 
 	unsigned bo_prog_idx;
 	unsigned prog_size;
 	unsigned progs_per_bo;
+	unsigned progs;
+
 	struct nvfx_fragment_program_bo* fpbo;
 };
 
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index b9d1897791..2e0e366ca3 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -15,6 +15,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	if(nvfx != nvfx->screen->cur_ctx)
 	{
 		nvfx->dirty = ~0;
+		nvfx->hw_vtxelt_nr = 16;
 		nvfx->screen->cur_ctx = nvfx;
 	}
 
@@ -86,7 +87,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	if(dirty & NVFX_NEW_STIPPLE)
 		nvfx_state_stipple_validate(nvfx);
 
-	if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST))
+	if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST | NVFX_NEW_VERTPROG | NVFX_NEW_SPRITE))
 	{
 		nvfx_fragprog_validate(nvfx);
 		if(dirty & NVFX_NEW_FRAGPROG)
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 939d2b83ae..3d2f2b9fba 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -1,7 +1,7 @@
 #include "pipe/p_context.h"
 #include "pipe/p_defines.h"
 #include "pipe/p_state.h"
-#include "util/u_inlines.h"
+#include "util/u_linkage.h"
 
 #include "pipe/p_shader_tokens.h"
 #include "tgsi/tgsi_parse.h"
@@ -61,7 +61,7 @@ temp(struct nvfx_vpc *vpc)
 	return nvfx_sr(NVFXSR_TEMP, idx);
 }
 
-static INLINE void
+static inline void
 release_temps(struct nvfx_vpc *vpc)
 {
 	vpc->r_temps &= ~vpc->r_temps_discard;
@@ -339,7 +339,7 @@ nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
 	emit_src(nvfx, vpc, hw, 2, s2);
 }
 
-static INLINE struct nvfx_sreg
+static inline struct nvfx_sreg
 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
 	struct nvfx_sreg src = { 0 };
 
@@ -385,14 +385,14 @@ tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
 		dst = vpc->r_address[fdst->Register.Index];
 		break;
 	default:
-		NOUVEAU_ERR("bad dst file\n");
+		NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
 		break;
 	}
 
 	return dst;
 }
 
-static INLINE int
+static inline int
 tgsi_mask(uint tgsi)
 {
 	int mask = 0;
@@ -650,12 +650,8 @@ nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 		hw = NVFX_VP(INST_DEST_PSZ);
 		break;
 	case TGSI_SEMANTIC_GENERIC:
-		if (fdec->Semantic.Index <= 7) {
-			hw = NVFX_VP(INST_DEST_TC(fdec->Semantic.Index));
-		} else {
-			NOUVEAU_ERR("bad generic semantic index\n");
-			return FALSE;
-		}
+		hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf)
+			+ NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0);
 		break;
 	case TGSI_SEMANTIC_EDGEFLAG:
 		/* not really an error just a fallback */
@@ -675,6 +671,29 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
 {
 	struct tgsi_parse_context p;
 	int high_temp = -1, high_addr = -1, nr_imm = 0, i;
+	struct util_semantic_set set;
+	unsigned char sem_layout[8];
+	unsigned sem_layout_size;
+	unsigned num_outputs;
+
+	num_outputs = util_semantic_set_from_program_file(&set, vpc->vp->pipe.tokens, TGSI_FILE_OUTPUT);
+
+	if(num_outputs > 8) {
+		NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs);
+		return FALSE;
+	}
+	util_semantic_layout_from_set(sem_layout, &set, 8, 8);
+
+	/* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
+	memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input));
+	vpc->vp->texcoord_ouput_mask = 0;
+	for(int i = 0; i < 8; ++i) {
+		if(sem_layout[i] == 0xff)
+			continue;
+		vpc->vp->texcoord_ouput_mask |= (1 << i);
+		//printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
+		vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | (NVFX_FP_OP_INPUT_SRC_TC(0) + i);
+	}
 
 	tgsi_parse_init(&p, vpc->vp->pipe.tokens);
 	while (!tgsi_parse_end_of_tokens(&p)) {
-- 
cgit v1.2.3


From 0184e298636370865bb8d511ca890acd70c1c4c6 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 13 Mar 2010 02:28:59 +0100
Subject: nvfx: expose GLSL

Still no control flow support, but basic stuff works.
---
 src/gallium/drivers/nvfx/nvfx_screen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index 7e3caf8d2e..72cb5239b5 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -44,7 +44,7 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 	case PIPE_CAP_TWO_SIDED_STENCIL:
 		return 1;
 	case PIPE_CAP_GLSL:
-		return 0;
+		return 1;
 	case PIPE_CAP_ANISOTROPIC_FILTER:
 		return 1;
 	case PIPE_CAP_POINT_SPRITE:
-- 
cgit v1.2.3


From 0d74956a1f895303a44bddc6f92c246ecce40023 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 15 Aug 2010 10:15:40 +0200
Subject: nvfx: support flatshade_first

---
 src/gallium/drivers/nouveau/nouveau_class.h | 1 +
 src/gallium/drivers/nvfx/nvfx_context.h     | 2 +-
 src/gallium/drivers/nvfx/nvfx_state.c       | 3 +++
 3 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nouveau/nouveau_class.h b/src/gallium/drivers/nouveau/nouveau_class.h
index 14c11b278a..20941f379c 100644
--- a/src/gallium/drivers/nouveau/nouveau_class.h
+++ b/src/gallium/drivers/nouveau/nouveau_class.h
@@ -6149,6 +6149,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define   NV34TCL_FP_REG_CONTROL_UNK1_MASK						0xffff0000
 #define   NV34TCL_FP_REG_CONTROL_UNK0_SHIFT						0
 #define   NV34TCL_FP_REG_CONTROL_UNK0_MASK						0x0000ffff
+#define  NV34TCL_FLATSHADE_FIRST							0x00001454
 #define  NV34TCL_EDGEFLAG_ENABLE							0x0000145c
 #define  NV34TCL_VP_CLIP_PLANES_ENABLE							0x00001478
 #define   NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0						(1 <<  1)
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 7ec6a4f412..2eec5a11a6 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -50,7 +50,7 @@
 struct nvfx_rasterizer_state {
 	struct pipe_rasterizer_state pipe;
 	unsigned sb_len;
-	uint32_t sb[32];
+	uint32_t sb[34];
 };
 
 struct nvfx_zsa_state {
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index c3addf1114..f529fb2a27 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -151,6 +151,9 @@ nvfx_rasterizer_state_create(struct pipe_context *pipe,
 		sb_data(sb, fui(cso->offset_units * 2));
 	}
 
+	sb_method(sb, NV34TCL_FLATSHADE_FIRST, 1);
+	sb_data(sb, cso->flatshade_first);
+
 	rsso->pipe = *cso;
 	rsso->sb_len = sb_len(sb, rsso->sb);
 	return (void *)rsso;
-- 
cgit v1.2.3


From 07b6fde4102bfa5097b3c16cf23a6d60357e5463 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 16 Aug 2010 16:55:00 +0200
Subject: nv30: band-aid viewport issues

For some reason nv30 seems to like to reset the viewport, even though
attempts to isolate where exactly it does that have currently been
inconclusive.
---
 src/gallium/drivers/nvfx/nvfx_state_emit.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index 2e0e366ca3..7a706ea6d7 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -109,12 +109,14 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	if(dirty & NVFX_NEW_SR)
 		nvfx_state_sr_validate(nvfx);
 
-/* Having this depend on FB looks wrong, but it seems
-   necessary to make this work on nv3x
+/* All these dependencies are wrong, but otherwise
+   etracer, neverball, foobillard, glest totally misrender
    TODO: find the right fix
 */
-	if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_FB))
+	if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA) || (all_swizzled > 0))
+	{
 		nvfx_state_viewport_validate(nvfx);
+	}
 
 	if(flush_tex_cache)
 	{
-- 
cgit v1.2.3


From 6931a01222beab107cb65067270770e3406425e2 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 17 Aug 2010 01:01:42 +0200
Subject: nvfx: fire ring after transfers

Might reduce the risk of running out of memory
---
 src/gallium/drivers/nvfx/nvfx_transfer.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_transfer.c b/src/gallium/drivers/nvfx/nvfx_transfer.c
index ca4462ef9d..7cb47a20f6 100644
--- a/src/gallium/drivers/nvfx/nvfx_transfer.c
+++ b/src/gallium/drivers/nvfx/nvfx_transfer.c
@@ -141,7 +141,12 @@ nvfx_transfer_destroy(struct pipe_context *pipe, struct pipe_transfer *ptx)
 		FREE(ptx);
 	}
 	else
+	{
+		struct nouveau_channel* chan = nvfx_context(pipe)->screen->base.channel;
 		util_staging_transfer_destroy(pipe, ptx);
+
+		FIRE_RING(chan);
+	}
 }
 
 void *
-- 
cgit v1.2.3


From ed232adc80867a424978396e047f146cb94a1cc5 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Thu, 19 Aug 2010 12:58:14 +0200
Subject: nvfx: fix GPU hardlocks when depth buffer is absent

---
 src/gallium/drivers/nvfx/nvfx_context.h    |  2 +-
 src/gallium/drivers/nvfx/nvfx_state.c      |  4 +---
 src/gallium/drivers/nvfx/nvfx_state_emit.c | 10 +++++++++-
 src/gallium/drivers/nvfx/nvfx_state_fb.c   |  4 ++++
 4 files changed, 15 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 2eec5a11a6..04447da3e1 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -56,7 +56,7 @@ struct nvfx_rasterizer_state {
 struct nvfx_zsa_state {
 	struct pipe_depth_stencil_alpha_state pipe;
 	unsigned sb_len;
-	uint32_t sb[26];
+	uint32_t sb[24];
 };
 
 struct nvfx_blend_state {
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index f529fb2a27..c8431641d3 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -207,10 +207,8 @@ nvfx_depth_stencil_alpha_state_create(struct pipe_context *pipe,
 	struct nvfx_zsa_state *zsaso = CALLOC(1, sizeof(*zsaso));
 	struct nouveau_statebuf_builder sb = sb_init(zsaso->sb);
 
-	sb_method(sb, NV34TCL_DEPTH_FUNC, 3);
+	sb_method(sb, NV34TCL_DEPTH_FUNC, 1);
 	sb_data  (sb, nvgl_comparison_op(cso->depth.func));
-	sb_data  (sb, cso->depth.writemask ? 1 : 0);
-	sb_data  (sb, cso->depth.enabled ? 1 : 0);
 
 	sb_method(sb, NV34TCL_ALPHA_FUNC_ENABLE, 3);
 	sb_data  (sb, cso->alpha.enabled ? 1 : 0);
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index 7a706ea6d7..19512194be 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -113,11 +113,19 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
    etracer, neverball, foobillard, glest totally misrender
    TODO: find the right fix
 */
-	if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA) || (all_swizzled > 0))
+	if(dirty & (NVFX_NEW_VIEWPORT | NVFX_NEW_RAST | NVFX_NEW_ZSA) || (all_swizzled >= 0))
 	{
 		nvfx_state_viewport_validate(nvfx);
 	}
 
+	if(dirty & NVFX_NEW_ZSA || (all_swizzled >= 0))
+	{
+		WAIT_RING(chan, 3);
+		OUT_RING(chan, RING_3D(NV34TCL_DEPTH_WRITE_ENABLE, 2));
+		OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.writemask);
+	        OUT_RING(chan, nvfx->framebuffer.zsbuf && nvfx->zsa->pipe.depth.enabled);
+	}
+
 	if(flush_tex_cache)
 	{
 		// TODO: what about nv30?
diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c
index 28bbd36c2e..3db9cec905 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_fb.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c
@@ -252,6 +252,10 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
 			OUT_RING(chan, nvfx->hw_zeta.pitch);
 		}
 	}
+	else if(nvfx->is_nv4x) {
+		OUT_RING(chan, RING_3D(NV40TCL_ZETA_PITCH, 1));
+		OUT_RING(chan, 64);
+	}
 
 	OUT_RING(chan, RING_3D(NV34TCL_RT_ENABLE, 1));
 	OUT_RING(chan, rt_enable);
-- 
cgit v1.2.3


From 1dea9bc369dea1215c9e10bf6d52507e618d11ca Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Thu, 19 Aug 2010 22:36:00 +0200
Subject: nvfx: mostly fix inline corruption magically

Not sure why this mostly works.
---
 src/gallium/drivers/nvfx/nvfx_push.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_push.c b/src/gallium/drivers/nvfx/nvfx_push.c
index 52e891c667..49d518e2eb 100644
--- a/src/gallium/drivers/nvfx/nvfx_push.c
+++ b/src/gallium/drivers/nvfx/nvfx_push.c
@@ -246,7 +246,7 @@ nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 		uint8_t* map;
 		unsigned step;
 	} per_instance[16];
-	unsigned p_overhead = 0
+	unsigned p_overhead = 64 /* magic fix */
 			+ 4 /* begin/end */
 			+ 4; /* potential edgeflag enable/disable */
 
@@ -367,6 +367,14 @@ nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 
 			if(max_verts >= 16)
 			{
+				/* XXX: any command a lot of times seems to (mostly) fix corruption that would otherwise happen */
+				int i;
+				for(i = 0; i < 32; ++i)
+				{
+					OUT_RING(chan, RING_3D(0x1dac, 1));
+					OUT_RING(chan, 0);
+				}
+
 				OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
 				OUT_RING(chan, hw_mode);
 				done = util_split_prim_next(&s, max_verts);
-- 
cgit v1.2.3


From 928cce672a613b2f7bfa5563eca828327b16dc27 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Thu, 19 Aug 2010 22:47:03 +0200
Subject: nvfx: fix lodbias

---
 src/gallium/drivers/nvfx/nv30_fragtex.c | 2 +-
 src/gallium/drivers/nvfx/nv40_fragtex.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv30_fragtex.c b/src/gallium/drivers/nvfx/nv30_fragtex.c
index db8a8fc4b0..0c3d43fd57 100644
--- a/src/gallium/drivers/nvfx/nv30_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv30_fragtex.c
@@ -21,7 +21,7 @@ nv30_sampler_state_init(struct pipe_context *pipe,
 			ps->en |= NV34TCL_TX_ENABLE_ANISO_2X;
 	}
 
-	limit = CLAMP(cso->lod_bias, -16.0, 15.0);
+	limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0));
 	ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
 
 	ps->max_lod = (int)CLAMP(cso->max_lod, 0.0, 15.0);
diff --git a/src/gallium/drivers/nvfx/nv40_fragtex.c b/src/gallium/drivers/nvfx/nv40_fragtex.c
index 5fe742f260..106ce71a07 100644
--- a/src/gallium/drivers/nvfx/nv40_fragtex.c
+++ b/src/gallium/drivers/nvfx/nv40_fragtex.c
@@ -29,11 +29,11 @@ nv40_sampler_state_init(struct pipe_context *pipe,
 			ps->en |= NV40TCL_TEX_ENABLE_ANISO_2X;
 	}
 
-	limit = CLAMP(cso->lod_bias, -16.0, 15.0);
+	limit = CLAMP(cso->lod_bias, -16.0, 15.0 + (255.0 / 256.0));
 	ps->filt |= (int)(cso->lod_bias * 256.0) & 0x1fff;
 
-	ps->max_lod = (int)(CLAMP(cso->max_lod, 0.0, 15.0) * 256.0);
-	ps->min_lod = (int)(CLAMP(cso->min_lod, 0.0, 15.0) * 256.0);
+	ps->max_lod = (int)(CLAMP(cso->max_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0);
+	ps->min_lod = (int)(CLAMP(cso->min_lod, 0.0, 15.0 + (255.0 / 256.0)) * 256.0);
 
 	ps->en |= NV40TCL_TEX_ENABLE_ENABLE;
 }
-- 
cgit v1.2.3


From b2bad53478b6033038b51982db09094337f1f379 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Thu, 25 Feb 2010 17:46:37 +0100
Subject: nvfx: improve and correct nvfx_shader.h

---
 src/gallium/drivers/nvfx/nvfx_shader.h | 78 ++++++++++++++++++++++++++++------
 1 file changed, 65 insertions(+), 13 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h
index 88cf91b95f..59a439fc60 100644
--- a/src/gallium/drivers/nvfx/nvfx_shader.h
+++ b/src/gallium/drivers/nvfx/nvfx_shader.h
@@ -1,6 +1,8 @@
 #ifndef __NVFX_SHADER_H__
 #define __NVFX_SHADER_H__
 
+#define NVFX_SWZ_IDENTITY ((3 << 6) | (2 << 4) | (1 << 2) | (0 << 0))
+
 /* this will resolve to either the NV30 or the NV40 version
  * depending on the current hardware */
 /* unusual, but very fast and compact method */
@@ -71,11 +73,58 @@
 /*
  * Each fragment program opcode appears to be comprised of 4 32-bit values.
  *
- *   0 - Opcode, output reg/mask, ATTRIB source
- *   1 - Source 0
- *   2 - Source 1
- *   3 - Source 2
+ * 0: OPDEST
+ * 	0: program end
+ * 	1-6: destination register
+ * 	7: destination register is fp16?? (use for outputs)
+ * 	8: set condition code
+ * 	9: writemask x
+ *  	10: writemask y
+ *  	11: writemask z
+ *  	12: writemask w
+ *  	13-16: source attribute register number (e.g. COL0)
+ *  	17-20: texture unit number
+ *  	21: expand value on texture operation (x -> 2x - 1)
+ *  	22-23: precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = s0.8 fixed (nv40-only))
+ * 	24-29: opcode
+ * 	30: no destination
+ * 	31: saturate
+ * 1 - SRC0
+ * 	0-17: see common source fields
+ * 	18: execute if condition code less
+ * 	19: execute if condition code equal
+ * 	20: execute if condition code greater
+ * 	21-22: condition code swizzle x source component
+ * 	23-24: condition code swizzle y source component
+ * 	25-26: condition code swizzle z source component
+ * 	27-28: condition code swizzle w source component
+ * 	29: source 0 absolute
+ * 	30: always 0 in renouveau tests
+ * 	31: always 0 in renouveau tests
+ * 2 - SRC1
+ * 	0-17: see common source fields
+ * 	18: source 1 absolute
+ * 	19-20: input precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = ???
+ * 	21-27: always 0 in renouveau tests
+ * 	28-30: scale (0 = 1x, 1 = 2x, 2 = 4x, 3 = 8x, 4 = ???, 5, = 1/2, 6 = 1/4, 7 = 1/8)
+ * 	31: opcode is branch
+ * 3 - SRC2
+ * 	0-17: see common source fields
+ * 	18: source 2 absolute
+ * 	19-29: address register displacement
+ * 	30: use index register
+ * 	31: disable perspective-correct interpolation?
  *
+* Common fields of 0, 1, 2 - SRC
+ * 	0-1: source register type (0 = temp, 1 = input, 2 = immediate, 3 = ???)
+ * 	2-7: source temp register index
+ * 	8: source register is fp16??
+ * 	9-10: source swizzle x source component
+ * 	11-12: source swizzle y source component
+ * 	13-14: source swizzle z source component
+ * 	15-16: source swizzle w source component
+ *	17: negate
+
  * There appears to be no special difference between result regs and temp regs.
  *     result.color == R0.xyzw
  *     result.depth == R1.z
@@ -210,6 +259,7 @@
 
 /* NV40 only fragment program opcodes */
 #define NVFX_FP_OP_OPCODE_TXL_NV40 0x2F
+
 /* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
 #define NV40_FP_OP_BRA_OPCODE_BRK                                    0x0
 #define NV40_FP_OP_BRA_OPCODE_CAL                                    0x1
@@ -218,10 +268,11 @@
 #define NV40_FP_OP_BRA_OPCODE_REP                                    0x4
 #define NV40_FP_OP_BRA_OPCODE_RET                                    0x5
 
+#define NV40_FP_OP_OUT_NONE         (1 << 30)
 #define NVFX_FP_OP_OUT_SAT          (1 << 31)
 
 /* high order bits of SRC0 */
-#define NVFX_FP_OP_OUT_ABS          (1 << 29)
+#define NVFX_FP_OP_SRC0_ABS          (1 << 29)
 #define NVFX_FP_OP_COND_SWZ_W_SHIFT        27
 #define NVFX_FP_OP_COND_SWZ_W_MASK        (3 << 27)
 #define NVFX_FP_OP_COND_SWZ_Z_SHIFT        25
@@ -254,6 +305,7 @@
 #define NVFX_FP_OP_DST_SCALE_INV_2X                                            5
 #define NVFX_FP_OP_DST_SCALE_INV_4X                                            6
 #define NVFX_FP_OP_DST_SCALE_INV_8X                                            7
+#define NVFX_FP_OP_SRC1_ABS          (1 << 18)
 
 /* SRC1 LOOP */
 #define NV40_FP_OP_LOOP_INCR_SHIFT                                            19
@@ -263,13 +315,13 @@
 #define NV40_FP_OP_LOOP_COUNT_SHIFT                                            2
 #define NV40_FP_OP_LOOP_COUNT_MASK                                   (0xFF << 2)
 
-/* SRC1 IF */
-#define NV40_FP_OP_ELSE_ID_SHIFT                                               2
-#define NV40_FP_OP_ELSE_ID_MASK                                      (0xFF << 2)
+/* SRC1 IF: absolute offset in dwords */
+#define NV40_FP_OP_ELSE_OFFSET_SHIFT                                           0
+#define NV40_FP_OP_ELSE_OFFSET_MASK                             (0x7FFFFFFF << 0)
 
 /* SRC1 CAL */
-#define NV40_FP_OP_IADDR_SHIFT                                                 2
-#define NV40_FP_OP_IADDR_MASK                                        (0xFF << 2)
+#define NV40_FP_OP_SUB_OFFSET_SHIFT                                                 0
+#define NV40_FP_OP_SUB_OFFSET_MASK                                   (0x7FFFFFFF << 0)
 
 /* SRC1 REP
  *   I have no idea why there are 3 count values here..  but they
@@ -283,9 +335,9 @@
 #define NV40_FP_OP_REP_COUNT3_SHIFT                                           19
 #define NV40_FP_OP_REP_COUNT3_MASK                                  (0xFF << 19)
 
-/* SRC2 REP/IF */
-#define NV40_FP_OP_END_ID_SHIFT                                                2
-#define NV40_FP_OP_END_ID_MASK                                       (0xFF << 2)
+/* SRC2 REP/IF: absolute offset in dwords */
+#define NV40_FP_OP_END_OFFSET_SHIFT                                            0
+#define NV40_FP_OP_END_OFFSET_MASK                              (0x7FFFFFFF << 0)
 
 /* high order bits of SRC2 */
 #define NVFX_FP_OP_INDEX_INPUT          (1 << 30)
-- 
cgit v1.2.3


From 28fa9451e1b3fe251923b0de352e34f84dbd6f4a Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 13:28:38 +0200
Subject: nvfx: add option to dump shaders in TGSI and native code

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 15 +++++++++++++++
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 23 +++++++++++++++--------
 2 files changed, 30 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 0a599c62a7..6d2957c82b 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -2,10 +2,12 @@
 #include "pipe/p_defines.h"
 #include "pipe/p_state.h"
 #include "util/u_inlines.h"
+#include "util/u_debug.h"
 
 #include "pipe/p_shader_tokens.h"
 #include "tgsi/tgsi_parse.h"
 #include "tgsi/tgsi_util.h"
+#include "tgsi/tgsi_dump.h"
 
 #include "nvfx_context.h"
 #include "nvfx_shader.h"
@@ -748,6 +750,8 @@ out_err:
 	return FALSE;
 }
 
+DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
+
 static void
 nvfx_fragprog_translate(struct nvfx_context *nvfx,
 			struct nvfx_fragment_program *fp)
@@ -803,6 +807,17 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 	fp->insn[fpc->inst_offset + 2] = 0x00000000;
 	fp->insn[fpc->inst_offset + 3] = 0x00000000;
 
+	if(debug_get_option_nvfx_dump_fp())
+	{
+		debug_printf("\n");
+		tgsi_dump(fp->pipe.tokens, 0);
+
+		debug_printf("\n%s fragment program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
+		for (unsigned i = 0; i < fp->insn_len; i += 4)
+			debug_printf("%3u: %08x %08x %08x %08x\n", i >> 2, fp->insn[i], fp->insn[i + 1], fp->insn[i + 2], fp->insn[i + 3]);
+		debug_printf("\n");
+	}
+
 	fp->translated = TRUE;
 out_err:
 	tgsi_parse_free(&parse);
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 3d2f2b9fba..359bc01341 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -2,6 +2,7 @@
 #include "pipe/p_defines.h"
 #include "pipe/p_state.h"
 #include "util/u_linkage.h"
+#include "util/u_debug.h"
 
 #include "pipe/p_shader_tokens.h"
 #include "tgsi/tgsi_parse.h"
@@ -777,6 +778,8 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
 	return TRUE;
 }
 
+DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE)
+
 static void
 nvfx_vertprog_translate(struct nvfx_context *nvfx,
 			struct nvfx_vertex_program *vp)
@@ -873,6 +876,18 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 	}
 
 	vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
+
+	if(debug_get_option_nvfx_dump_vp())
+	{
+		debug_printf("\n");
+		tgsi_dump(vp->pipe.tokens, 0);
+
+		debug_printf("\n%s vertex program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
+		for (i = 0; i < vp->nr_insns; i++)
+			debug_printf("%3u: %08x %08x %08x %08x\n", i, vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
+		debug_printf("\n");
+	}
+
 	vp->translated = TRUE;
 out_err:
 	tgsi_parse_free(&parse);
@@ -1025,14 +1040,6 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 
 	/* Upload vtxprog */
 	if (upload_code) {
-#if 0
-		for (i = 0; i < vp->nr_insns; i++) {
-			NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[0]);
-			NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[1]);
-			NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[2]);
-			NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
-		}
-#endif
 		BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
 		OUT_RING  (chan, vp->exec->start);
 		for (i = 0; i < vp->nr_insns; i++) {
-- 
cgit v1.2.3


From cf0d15642289f0a4b8d40e61266c89fe09d6601b Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 12:32:59 +0200
Subject: nvfx: refactor shader assembler

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 364 +++++++++++++++----------------
 src/gallium/drivers/nvfx/nvfx_shader.h   | 116 ++++++----
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 237 ++++++++++----------
 3 files changed, 357 insertions(+), 360 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 6d2957c82b..f8c4eae387 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -20,8 +20,8 @@ struct nvfx_fpc {
 
 	unsigned r_temps;
 	unsigned r_temps_discard;
-	struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
-	struct nvfx_sreg *r_temp;
+	struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
+	struct nvfx_reg *r_temp;
 
 	int num_regs;
 
@@ -34,13 +34,13 @@ struct nvfx_fpc {
 	} consts[MAX_CONSTS];
 	int nr_consts;
 
-	struct nvfx_sreg imm[MAX_IMM];
+	struct nvfx_reg imm[MAX_IMM];
 	unsigned nr_imm;
 
 	unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
 };
 
-static INLINE struct nvfx_sreg
+static INLINE struct nvfx_reg
 temp(struct nvfx_fpc *fpc)
 {
 	int idx = ffs(~fpc->r_temps) - 1;
@@ -48,12 +48,12 @@ temp(struct nvfx_fpc *fpc)
 	if (idx < 0) {
 		NOUVEAU_ERR("out of temps!!\n");
 		assert(0);
-		return nvfx_sr(NVFXSR_TEMP, 0);
+		return nvfx_reg(NVFXSR_TEMP, 0);
 	}
 
 	fpc->r_temps |= (1 << idx);
 	fpc->r_temps_discard |= (1 << idx);
-	return nvfx_sr(NVFXSR_TEMP, idx);
+	return nvfx_reg(NVFXSR_TEMP, idx);
 }
 
 static INLINE void
@@ -63,7 +63,7 @@ release_temps(struct nvfx_fpc *fpc)
 	fpc->r_temps_discard = 0;
 }
 
-static INLINE struct nvfx_sreg
+static INLINE struct nvfx_reg
 constant(struct nvfx_fpc *fpc, int pipe, float vals[4])
 {
 	int idx;
@@ -75,16 +75,9 @@ constant(struct nvfx_fpc *fpc, int pipe, float vals[4])
 	fpc->consts[idx].pipe = pipe;
 	if (pipe == -1)
 		memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
-	return nvfx_sr(NVFXSR_CONST, idx);
+	return nvfx_reg(NVFXSR_CONST, idx);
 }
 
-#define arith(cc,s,o,d,m,s0,s1,s2) \
-	nvfx_fp_arith((cc), (s), NVFX_FP_OP_OPCODE_##o, \
-			(d), (m), (s0), (s1), (s2))
-#define tex(cc,s,o,u,d,m,s0,s1,s2) \
-	nvfx_fp_tex((cc), (s), NVFX_FP_OP_OPCODE_##o, (u), \
-		    (d), (m), (s0), none, none)
-
 static void
 grow_insns(struct nvfx_fpc *fpc, int size)
 {
@@ -95,28 +88,28 @@ grow_insns(struct nvfx_fpc *fpc, int size)
 }
 
 static void
-emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
+emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
 {
 	struct nvfx_fragment_program *fp = fpc->fp;
 	uint32_t *hw = &fp->insn[fpc->inst_offset];
 	uint32_t sr = 0;
 
-	switch (src.type) {
+	switch (src.reg.type) {
 	case NVFXSR_INPUT:
 		sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
-		hw[0] |= (src.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
+		hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
 		break;
 	case NVFXSR_OUTPUT:
 		sr |= NVFX_FP_REG_SRC_HALF;
 		/* fall-through */
 	case NVFXSR_TEMP:
 		sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
-		sr |= (src.index << NVFX_FP_REG_SRC_SHIFT);
+		sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
 		break;
 	case NVFXSR_RELOCATED:
 		sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
 		//printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
-		util_dynarray_append(&fpc->fp->slot_relocations[src.index], unsigned, fpc->inst_offset);
+		util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset);
 		break;
 	case NVFXSR_CONST:
 		if (!fpc->have_const) {
@@ -125,18 +118,18 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
 		}
 
 		hw = &fp->insn[fpc->inst_offset];
-		if (fpc->consts[src.index].pipe >= 0) {
+		if (fpc->consts[src.reg.index].pipe >= 0) {
 			struct nvfx_fragment_program_data *fpd;
 
 			fp->consts = realloc(fp->consts, ++fp->nr_consts *
 					     sizeof(*fpd));
 			fpd = &fp->consts[fp->nr_consts - 1];
 			fpd->offset = fpc->inst_offset + 4;
-			fpd->index = fpc->consts[src.index].pipe;
+			fpd->index = fpc->consts[src.reg.index].pipe;
 			memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
 		} else {
 			memcpy(&fp->insn[fpc->inst_offset + 4],
-				fpc->consts[src.index].vals,
+				fpc->consts[src.reg.index].vals,
 				sizeof(uint32_t) * 4);
 		}
 
@@ -164,7 +157,7 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
 }
 
 static void
-emit_dst(struct nvfx_fpc *fpc, struct nvfx_sreg dst)
+emit_dst(struct nvfx_fpc *fpc, struct nvfx_reg dst)
 {
 	struct nvfx_fragment_program *fp = fpc->fp;
 	uint32_t *hw = &fp->insn[fpc->inst_offset];
@@ -192,9 +185,7 @@ emit_dst(struct nvfx_fpc *fpc, struct nvfx_sreg dst)
 }
 
 static void
-nvfx_fp_arith(struct nvfx_fpc *fpc, int sat, int op,
-	      struct nvfx_sreg dst, int mask,
-	      struct nvfx_sreg s0, struct nvfx_sreg s1, struct nvfx_sreg s2)
+nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
 {
 	struct nvfx_fragment_program *fp = fpc->fp;
 	uint32_t *hw;
@@ -205,85 +196,86 @@ nvfx_fp_arith(struct nvfx_fpc *fpc, int sat, int op,
 	hw = &fp->insn[fpc->inst_offset];
 	memset(hw, 0, sizeof(uint32_t) * 4);
 
-	if (op == NVFX_FP_OP_OPCODE_KIL)
+	if (insn.op == NVFX_FP_OP_OPCODE_KIL)
 		fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
-	hw[0] |= (op << NVFX_FP_OP_OPCODE_SHIFT);
-	hw[0] |= (mask << NVFX_FP_OP_OUTMASK_SHIFT);
-	hw[2] |= (dst.dst_scale << NVFX_FP_OP_DST_SCALE_SHIFT);
+	hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
+	hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
+	hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
 
-	if (sat)
+	if (insn.sat)
 		hw[0] |= NVFX_FP_OP_OUT_SAT;
 
-	if (dst.cc_update)
+	if (insn.cc_update)
 		hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
-	hw[1] |= (dst.cc_test << NVFX_FP_OP_COND_SHIFT);
-	hw[1] |= ((dst.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
-		  (dst.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
-		  (dst.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
-		  (dst.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
-
-	emit_dst(fpc, dst);
-	emit_src(fpc, 0, s0);
-	emit_src(fpc, 1, s1);
-	emit_src(fpc, 2, s2);
-}
+	hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
+	hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
+		  (insn.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
+		  (insn.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
+		  (insn.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
 
-static void
-nvfx_fp_tex(struct nvfx_fpc *fpc, int sat, int op, int unit,
-	    struct nvfx_sreg dst, int mask,
-	    struct nvfx_sreg s0, struct nvfx_sreg s1, struct nvfx_sreg s2)
-{
-	struct nvfx_fragment_program *fp = fpc->fp;
-
-	nvfx_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
+	if(insn.unit >= 0)
+	{
+		hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
+		fp->samplers |= (1 << insn.unit);
+	}
 
-	fp->insn[fpc->inst_offset] |= (unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
-	fp->samplers |= (1 << unit);
+	emit_dst(fpc, insn.dst);
+	emit_src(fpc, 0, insn.src[0]);
+	emit_src(fpc, 1, insn.src[1]);
+	emit_src(fpc, 2, insn.src[2]);
 }
 
-static INLINE struct nvfx_sreg
+#define arith(s,o,d,m,s0,s1,s2) \
+       nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
+                       (d), (m), (s0), (s1), (s2))
+
+#define tex(s,o,u,d,m,s0,s1,s2) \
+	nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
+                   (d), (m), (s0), none, none)
+
+static INLINE struct nvfx_src
 tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
 {
-	struct nvfx_sreg src = { 0 };
+	struct nvfx_src src;
 
 	switch (fsrc->Register.File) {
 	case TGSI_FILE_INPUT:
 		if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
 			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
-			src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
+			src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
 		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
 			if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0)
-				src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
+				src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
 			else if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 1)
-				src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
+				src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
 			else
 				assert(0);
 		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
 			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
-			src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
+			src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
 		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
 			/* TODO: check this has the correct values */
 			/* XXX: what do we do for nv30 here (assuming it lacks facing)?!  */
 			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
-			src = nvfx_sr(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
+			src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
 		} else {
 			assert(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
-			src = nvfx_sr(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
+			src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
 		}
 		break;
 	case TGSI_FILE_CONSTANT:
-		src = constant(fpc, fsrc->Register.Index, NULL);
+		src.reg = constant(fpc, fsrc->Register.Index, NULL);
 		break;
 	case TGSI_FILE_IMMEDIATE:
 		assert(fsrc->Register.Index < fpc->nr_imm);
-		src = fpc->imm[fsrc->Register.Index];
+		src.reg = fpc->imm[fsrc->Register.Index];
 		break;
 	case TGSI_FILE_TEMPORARY:
-		src = fpc->r_temp[fsrc->Register.Index];
+		src.reg = fpc->r_temp[fsrc->Register.Index];
 		break;
 	/* NV40 fragprog result regs are just temps, so this is simple */
 	case TGSI_FILE_OUTPUT:
-		src = fpc->r_result[fsrc->Register.Index];
+		src.reg = fpc->r_result[fsrc->Register.Index];
 		break;
 	default:
 		NOUVEAU_ERR("bad src file\n");
@@ -299,7 +291,7 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
 	return src;
 }
 
-static INLINE struct nvfx_sreg
+static INLINE struct nvfx_reg
 tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
 	switch (fdst->Register.File) {
 	case TGSI_FILE_OUTPUT:
@@ -307,10 +299,10 @@ tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
 	case TGSI_FILE_TEMPORARY:
 		return fpc->r_temp[fdst->Register.Index];
 	case TGSI_FILE_NULL:
-		return nvfx_sr(NVFXSR_NONE, 0);
+		return nvfx_reg(NVFXSR_NONE, 0);
 	default:
 		NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
-		return nvfx_sr(NVFXSR_NONE, 0);
+		return nvfx_reg(NVFXSR_NONE, 0);
 	}
 }
 
@@ -330,8 +322,10 @@ static boolean
 nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 				const struct tgsi_full_instruction *finst)
 {
-	const struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
-	struct nvfx_sreg src[3], dst, tmp;
+	const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
+	struct nvfx_insn insn;
+	struct nvfx_src src[3], tmp;
+	struct nvfx_reg dst;
 	int mask, sat, unit = 0;
 	int ai = -1, ci = -1, ii = -1;
 	int i;
@@ -359,9 +353,8 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 				ai = fsrc->Register.Index;
 				src[i] = tgsi_src(fpc, fsrc);
 			} else {
-				src[i] = temp(fpc);
-				arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
-				      tgsi_src(fpc, fsrc), none, none);
+				src[i] = nvfx_src(temp(fpc));
+				nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
 			}
 			break;
 		case TGSI_FILE_CONSTANT:
@@ -370,9 +363,8 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 				ci = fsrc->Register.Index;
 				src[i] = tgsi_src(fpc, fsrc);
 			} else {
-				src[i] = temp(fpc);
-				arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
-				      tgsi_src(fpc, fsrc), none, none);
+				src[i] = nvfx_src(temp(fpc));
+				nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
 			}
 			break;
 		case TGSI_FILE_IMMEDIATE:
@@ -381,9 +373,8 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 				ii = fsrc->Register.Index;
 				src[i] = tgsi_src(fpc, fsrc);
 			} else {
-				src[i] = temp(fpc);
-				arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
-				      tgsi_src(fpc, fsrc), none, none);
+				src[i] = nvfx_src(temp(fpc));
+				nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
 			}
 			break;
 		case TGSI_FILE_TEMPORARY:
@@ -406,227 +397,212 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 
 	switch (finst->Instruction.Opcode) {
 	case TGSI_OPCODE_ABS:
-		arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
+		nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
 		break;
 	case TGSI_OPCODE_ADD:
-		arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_CMP:
-		tmp = nvfx_sr(NVFXSR_NONE, 0);
-		tmp.cc_update = 1;
-		arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
-		dst.cc_test = NVFX_COND_GE;
-		arith(fpc, sat, MOV, dst, mask, src[2], none, none);
-		dst.cc_test = NVFX_COND_LT;
-		arith(fpc, sat, MOV, dst, mask, src[1], none, none);
+		insn = arith(0, MOV, none.reg, 0xf, src[0], none, none);
+		insn.cc_update = 1;
+		nvfx_fp_emit(fpc, insn);
+
+		insn = arith(sat, MOV, dst, mask, src[2], none, none);
+		insn.cc_test = NVFX_COND_GE;
+		nvfx_fp_emit(fpc, insn);
+
+		insn = arith(sat, MOV, dst, mask, src[1], none, none);
+		insn.cc_test = NVFX_COND_LT;
+		nvfx_fp_emit(fpc, insn);
 		break;
 	case TGSI_OPCODE_COS:
-		arith(fpc, sat, COS, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_DDX:
 		if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
-			tmp = temp(fpc);
-			arith(fpc, sat, DDX, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y,
-			      swz(src[0], Z, W, Z, W), none, none);
-			arith(fpc, 0, MOV, tmp, NVFX_FP_MASK_Z | NVFX_FP_MASK_W,
-			      swz(tmp, X, Y, X, Y), none, none);
-			arith(fpc, sat, DDX, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0],
-			      none, none);
-			arith(fpc, 0, MOV, dst, mask, tmp, none, none);
+			tmp = nvfx_src(temp(fpc));
+			nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
+			nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
+			nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
+			nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
 		} else {
-			arith(fpc, sat, DDX, dst, mask, src[0], none, none);
+			nvfx_fp_emit(fpc, arith(sat, DDX, dst, mask, src[0], none, none));
 		}
 		break;
 	case TGSI_OPCODE_DDY:
 		if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
-			tmp = temp(fpc);
-			arith(fpc, sat, DDY, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y,
-			      swz(src[0], Z, W, Z, W), none, none);
-			arith(fpc, 0, MOV, tmp, NVFX_FP_MASK_Z | NVFX_FP_MASK_W,
-			      swz(tmp, X, Y, X, Y), none, none);
-			arith(fpc, sat, DDY, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0],
-			      none, none);
-			arith(fpc, 0, MOV, dst, mask, tmp, none, none);
+			tmp = nvfx_src(temp(fpc));
+			nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
+			nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
+			nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
+			nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
 		} else {
-			arith(fpc, sat, DDY, dst, mask, src[0], none, none);
+			nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
 		}
 		break;
 	case TGSI_OPCODE_DP3:
-		arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_DP4:
-		arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, DP4, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_DPH:
-		tmp = temp(fpc);
-		arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_X, src[0], src[1], none);
-		arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
-		      swz(src[1], W, W, W, W), none);
+		tmp = nvfx_src(temp(fpc));
+		nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[1], none));
+		nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
 		break;
 	case TGSI_OPCODE_DST:
-		arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, DST, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_EX2:
-		arith(fpc, sat, EX2, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_FLR:
-		arith(fpc, sat, FLR, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_FRC:
-		arith(fpc, sat, FRC, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_KILP:
-		arith(fpc, 0, KIL, none, 0, none, none, none);
+		nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
 		break;
 	case TGSI_OPCODE_KIL:
-		dst = nvfx_sr(NVFXSR_NONE, 0);
-		dst.cc_update = 1;
-		arith(fpc, 0, MOV, dst, NVFX_FP_MASK_ALL, src[0], none, none);
-		dst.cc_update = 0; dst.cc_test = NVFX_COND_LT;
-		arith(fpc, 0, KIL, dst, 0, none, none, none);
+		insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none, none);
+		insn.cc_update = 1;
+		nvfx_fp_emit(fpc, insn);
+
+		insn = arith(0, KIL, none.reg, 0, none, none, none);
+		insn.cc_test = NVFX_COND_LT;
+		nvfx_fp_emit(fpc, insn);
 		break;
 	case TGSI_OPCODE_LG2:
-		arith(fpc, sat, LG2, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none));
 		break;
 //	case TGSI_OPCODE_LIT:
 	case TGSI_OPCODE_LRP:
 		if(!nvfx->is_nv4x)
-			arith(fpc, sat, LRP_NV30, dst, mask, src[0], src[1], src[2]);
+			nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2]));
 		else {
-			tmp = temp(fpc);
-			arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
-			arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
+			tmp = nvfx_src(temp(fpc));
+			nvfx_fp_emit(fpc, arith(0, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
+			nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], tmp));
 		}
 		break;
 	case TGSI_OPCODE_MAD:
-		arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
+		nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], src[2]));
 		break;
 	case TGSI_OPCODE_MAX:
-		arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, MAX, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_MIN:
-		arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, MIN, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_MOV:
-		arith(fpc, sat, MOV, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_MUL:
-		arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_POW:
 		if(!nvfx->is_nv4x)
-			arith(fpc, sat, POW_NV30, dst, mask, src[0], src[1], none);
+			nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
 		else {
-			tmp = temp(fpc);
-			arith(fpc, 0, LG2, tmp, NVFX_FP_MASK_X,
-			      swz(src[0], X, X, X, X), none, none);
-			arith(fpc, 0, MUL, tmp, NVFX_FP_MASK_X, swz(tmp, X, X, X, X),
-			      swz(src[1], X, X, X, X), none);
-			arith(fpc, sat, EX2, dst, mask,
-			      swz(tmp, X, X, X, X), none, none);
+			tmp = nvfx_src(temp(fpc));
+			nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
+			nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
+			nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none));
 		}
 		break;
 	case TGSI_OPCODE_RCP:
-		arith(fpc, sat, RCP, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_RET:
 		assert(0);
 		break;
 	case TGSI_OPCODE_RFL:
 		if(!nvfx->is_nv4x)
-			arith(fpc, 0, RFL_NV30, dst, mask, src[0], src[1], none);
+			nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
 		else {
-			tmp = temp(fpc);
-			arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_X, src[0], src[0], none);
-			arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_Y, src[0], src[1], none);
-			arith(fpc, 0, DIV, scale(tmp, 2X), NVFX_FP_MASK_Z,
-			      swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
-			arith(fpc, sat, MAD, dst, mask,
-			      swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
+			tmp = nvfx_src(temp(fpc));
+			nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
+			nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
+			insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
+			insn.scale = NVFX_FP_OP_DST_SCALE_2X;
+			nvfx_fp_emit(fpc, insn);
+			nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
 		}
 		break;
 	case TGSI_OPCODE_RSQ:
 		if(!nvfx->is_nv4x)
-			arith(fpc, sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none);
+			nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));
 		else {
-			tmp = temp(fpc);
-			arith(fpc, 0, LG2, scale(tmp, INV_2X), NVFX_FP_MASK_X,
-			      abs(swz(src[0], X, X, X, X)), none, none);
-			arith(fpc, sat, EX2, dst, mask,
-			      neg(swz(tmp, X, X, X, X)), none, none);
+			tmp = nvfx_src(temp(fpc));
+			insn = arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, abs(swz(src[0], X, X, X, X)), none, none);
+			insn.scale = NVFX_FP_OP_DST_SCALE_INV_2X;
+			nvfx_fp_emit(fpc, insn);
+			nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none));
 		}
 		break;
 	case TGSI_OPCODE_SCS:
 		/* avoid overwriting the source */
 		if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
 		{
-			if (mask & NVFX_FP_MASK_X) {
-				arith(fpc, sat, COS, dst, NVFX_FP_MASK_X,
-				      swz(src[0], X, X, X, X), none, none);
-			}
-			if (mask & NVFX_FP_MASK_Y) {
-				arith(fpc, sat, SIN, dst, NVFX_FP_MASK_Y,
-				      swz(src[0], X, X, X, X), none, none);
-			}
+			if (mask & NVFX_FP_MASK_X)
+				nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
+			if (mask & NVFX_FP_MASK_Y)
+				nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
 		}
 		else
 		{
-			if (mask & NVFX_FP_MASK_Y) {
-				arith(fpc, sat, SIN, dst, NVFX_FP_MASK_Y,
-				      swz(src[0], X, X, X, X), none, none);
-			}
-			if (mask & NVFX_FP_MASK_X) {
-				arith(fpc, sat, COS, dst, NVFX_FP_MASK_X,
-				      swz(src[0], X, X, X, X), none, none);
-			}
+			if (mask & NVFX_FP_MASK_Y)
+				nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
+			if (mask & NVFX_FP_MASK_X)
+				nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
 		}
 		break;
 	case TGSI_OPCODE_SEQ:
-		arith(fpc, sat, SEQ, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SFL:
-		arith(fpc, sat, SFL, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SGE:
-		arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SGT:
-		arith(fpc, sat, SGT, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, SGT, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SIN:
-		arith(fpc, sat, SIN, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, arith(sat, SIN, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_SLE:
-		arith(fpc, sat, SLE, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, SLE, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SLT:
-		arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, SLT, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SNE:
-		arith(fpc, sat, SNE, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_STR:
-		arith(fpc, sat, STR, dst, mask, src[0], src[1], none);
+		nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SUB:
-		arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
+		nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
 		break;
 	case TGSI_OPCODE_TEX:
-		tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_TXB:
-		tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_TXP:
-		tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
+		nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_XPD:
-		tmp = temp(fpc);
-		arith(fpc, 0, MUL, tmp, mask,
-		      swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
-		arith(fpc, sat, MAD, dst, (mask & ~NVFX_FP_MASK_W),
-		      swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
-		      neg(tmp));
+		tmp = nvfx_src(temp(fpc));
+		nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
+		nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
 		break;
 	default:
 		NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
@@ -666,7 +642,7 @@ nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 		return FALSE;
 	}
 
-	fpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
+	fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
 	fpc->r_temps |= (1 << hw);
 	return TRUE;
 }
@@ -735,7 +711,7 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 	tgsi_parse_free(&p);
 
 	if (++high_temp) {
-		fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
+		fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
 		for (i = 0; i < high_temp; i++)
 			fpc->r_temp[i] = temp(fpc);
 		fpc->r_temps_discard = 0;
diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h
index 59a439fc60..fcf577ca74 100644
--- a/src/gallium/drivers/nvfx/nvfx_shader.h
+++ b/src/gallium/drivers/nvfx/nvfx_shader.h
@@ -405,51 +405,88 @@
 #define NVFX_SWZ_Z 2
 #define NVFX_SWZ_W 3
 
-#define swz(s,x,y,z,w) nvfx_sr_swz((s), NVFX_SWZ_##x, NVFX_SWZ_##y, NVFX_SWZ_##z, NVFX_SWZ_##w)
-#define neg(s) nvfx_sr_neg((s))
-#define abs(s) nvfx_sr_abs((s))
-#define scale(s,v) nvfx_sr_scale((s), NVFX_FP_OP_DST_SCALE_##v)
-
-struct nvfx_sreg {
-	int type;
-	int index;
-
-	int dst_scale;
-
-	int negate;
-	int abs;
-	int swz[4];
-
-	int cc_update;
-	int cc_update_reg;
-	int cc_test;
-	int cc_test_reg;
-	int cc_swz[4];
+#define swz(s,x,y,z,w) nvfx_src_swz((s), NVFX_SWZ_##x, NVFX_SWZ_##y, NVFX_SWZ_##z, NVFX_SWZ_##w)
+#define neg(s) nvfx_src_neg((s))
+#define abs(s) nvfx_src_abs((s))
+
+struct nvfx_reg {
+	uint8_t type;
+	uint32_t index;
+};
+
+struct nvfx_src {
+	struct nvfx_reg reg;
+
+	/* src only */
+	uint8_t negate : 1;
+	uint8_t abs : 1;
+	uint8_t swz[4];
 };
 
-static INLINE struct nvfx_sreg
-nvfx_sr(int type, int index)
+struct nvfx_insn
 {
-	struct nvfx_sreg temp = {
-		.type = type,
-		.index = index,
-		.dst_scale = 0,
-		.abs = 0,
-		.negate = 0,
-		.swz = { 0, 1, 2, 3 },
+	uint8_t op;
+	char scale;
+	int8_t unit;
+	uint8_t mask;
+	uint8_t cc_swz[4];
+
+	uint8_t sat : 1;
+	uint8_t cc_update : 1;
+	uint8_t cc_update_reg : 1;
+	uint8_t cc_test : 3;
+	uint8_t cc_test_reg : 1;
+
+	struct nvfx_reg dst;
+	struct nvfx_src src[3];
+};
+
+static INLINE struct nvfx_insn
+nvfx_insn(boolean sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask, struct nvfx_src s0, struct nvfx_src s1, struct nvfx_src s2)
+{
+	struct nvfx_insn insn = {
+		.op = op,
+		.scale = 0,
+		.unit = unit,
+		.sat = sat,
+		.mask = mask,
 		.cc_update = 0,
 		.cc_update_reg = 0,
 		.cc_test = NVFX_COND_TR,
 		.cc_test_reg = 0,
 		.cc_swz = { 0, 1, 2, 3 },
+		.dst = dst,
+		.src = {s0, s1, s2}
+	};
+	return insn;
+}
+
+static INLINE struct nvfx_reg
+nvfx_reg(int type, int index)
+{
+	struct nvfx_reg temp = {
+		.type = type,
+		.index = index,
 	};
 	return temp;
 }
 
-static INLINE struct nvfx_sreg
-nvfx_sr_swz(struct nvfx_sreg src, int x, int y, int z, int w)
+static INLINE struct nvfx_src
+nvfx_src(struct nvfx_reg reg)
 {
-	struct nvfx_sreg dst = src;
+	struct nvfx_src temp = {
+		.reg = reg,
+		.abs = 0,
+		.negate = 0,
+		.swz = { 0, 1, 2, 3 },
+	};
+	return temp;
+}
+
+static INLINE struct nvfx_src
+nvfx_src_swz(struct nvfx_src src, int x, int y, int z, int w)
+{
+	struct nvfx_src dst = src;
 
 	dst.swz[NVFX_SWZ_X] = src.swz[x];
 	dst.swz[NVFX_SWZ_Y] = src.swz[y];
@@ -458,25 +495,18 @@ nvfx_sr_swz(struct nvfx_sreg src, int x, int y, int z, int w)
 	return dst;
 }
 
-static INLINE struct nvfx_sreg
-nvfx_sr_neg(struct nvfx_sreg src)
+static INLINE struct nvfx_src
+nvfx_src_neg(struct nvfx_src src)
 {
 	src.negate = !src.negate;
 	return src;
 }
 
-static INLINE struct nvfx_sreg
-nvfx_sr_abs(struct nvfx_sreg src)
+static INLINE struct nvfx_src
+nvfx_src_abs(struct nvfx_src src)
 {
 	src.abs = 1;
 	return src;
 }
 
-static INLINE struct nvfx_sreg
-nvfx_sr_scale(struct nvfx_sreg src, int scale)
-{
-	src.dst_scale = scale;
-	return src;
-}
-
 #endif
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 359bc01341..416e1b4d45 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -30,23 +30,24 @@
 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
 
 struct nvfx_vpc {
+	struct nvfx_context* nvfx;
 	struct nvfx_vertex_program *vp;
 
 	struct nvfx_vertex_program_exec *vpi;
 
 	unsigned r_temps;
 	unsigned r_temps_discard;
-	struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
-	struct nvfx_sreg *r_address;
-	struct nvfx_sreg *r_temp;
+	struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
+	struct nvfx_reg *r_address;
+	struct nvfx_reg *r_temp;
 
-	struct nvfx_sreg *imm;
+	struct nvfx_reg *imm;
 	unsigned nr_imm;
 
 	unsigned hpos_idx;
 };
 
-static struct nvfx_sreg
+static struct nvfx_reg
 temp(struct nvfx_vpc *vpc)
 {
 	int idx = ffs(~vpc->r_temps) - 1;
@@ -54,12 +55,12 @@ temp(struct nvfx_vpc *vpc)
 	if (idx < 0) {
 		NOUVEAU_ERR("out of temps!!\n");
 		assert(0);
-		return nvfx_sr(NVFXSR_TEMP, 0);
+		return nvfx_reg(NVFXSR_TEMP, 0);
 	}
 
 	vpc->r_temps |= (1 << idx);
 	vpc->r_temps_discard |= (1 << idx);
-	return nvfx_sr(NVFXSR_TEMP, idx);
+	return nvfx_reg(NVFXSR_TEMP, idx);
 }
 
 static inline void
@@ -69,7 +70,7 @@ release_temps(struct nvfx_vpc *vpc)
 	vpc->r_temps_discard = 0;
 }
 
-static struct nvfx_sreg
+static struct nvfx_reg
 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
 {
 	struct nvfx_vertex_program *vp = vpc->vp;
@@ -79,7 +80,7 @@ constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
 	if (pipe >= 0) {
 		for (idx = 0; idx < vp->nr_consts; idx++) {
 			if (vp->consts[idx].index == pipe)
-				return nvfx_sr(NVFXSR_CONST, idx);
+				return nvfx_reg(NVFXSR_CONST, idx);
 		}
 	}
 
@@ -92,35 +93,35 @@ constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
 	vpd->value[1] = y;
 	vpd->value[2] = z;
 	vpd->value[3] = w;
-	return nvfx_sr(NVFXSR_CONST, idx);
+	return nvfx_reg(NVFXSR_CONST, idx);
 }
 
-#define arith(cc,s,o,d,m,s0,s1,s2) \
-	nvfx_vp_arith(nvfx, (cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
+#define arith(s,o,d,m,s0,s1,s2) \
+	nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
 
 static void
-emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_sreg src)
+emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src)
 {
 	struct nvfx_vertex_program *vp = vpc->vp;
 	uint32_t sr = 0;
 
-	switch (src.type) {
+	switch (src.reg.type) {
 	case NVFXSR_TEMP:
 		sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
-		sr |= (src.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
+		sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
 		break;
 	case NVFXSR_INPUT:
 		sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
 		       NVFX_VP(SRC_REG_TYPE_SHIFT));
-		vp->ir |= (1 << src.index);
-		hw[1] |= (src.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
+		vp->ir |= (1 << src.reg.index);
+		hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
 		break;
 	case NVFXSR_CONST:
 		sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
 		       NVFX_VP(SRC_REG_TYPE_SHIFT));
 		assert(vpc->vpi->const_index == -1 ||
-		       vpc->vpi->const_index == src.index);
-		vpc->vpi->const_index = src.index;
+		       vpc->vpi->const_index == src.reg.index);
+		vpc->vpi->const_index = src.reg.index;
 		break;
 	case NVFXSR_NONE:
 		sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
@@ -163,7 +164,7 @@ emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos,
 }
 
 static void
-emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_sreg dst)
+emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst)
 {
 	struct nvfx_vertex_program *vp = vpc->vp;
 
@@ -173,13 +174,10 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 			hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
 		else {
 			hw[3] |= NV40_VP_INST_DEST_MASK;
-			if (slot == 0) {
-				hw[0] |= (dst.index <<
-					  NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
-			} else {
-				hw[3] |= (dst.index <<
-					  NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
-			}
+			if (slot == 0)
+				hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
+			else
+				hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
 		}
 		break;
 	case NVFXSR_OUTPUT:
@@ -279,12 +277,12 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 }
 
 static void
-nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
-	      struct nvfx_sreg dst, int mask,
-	      struct nvfx_sreg s0, struct nvfx_sreg s1,
-	      struct nvfx_sreg s2)
+nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
 {
+	struct nvfx_context* nvfx = vpc->nvfx;
 	struct nvfx_vertex_program *vp = vpc->vp;
+	unsigned slot = insn.op >> 7;
+	unsigned op = insn.op & 0x7f;
 	uint32_t *hw;
 
 	vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
@@ -311,51 +309,51 @@ nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
 //		hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
 //		hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
 
-		if (dst.type == NVFXSR_OUTPUT) {
+		if (insn.dst.type == NVFXSR_OUTPUT) {
 			if (slot)
-				hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
+				hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
 			else
-				hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
+				hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
 		} else {
 			if (slot)
-				hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
+				hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
 			else
-				hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
+				hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
 		}
 	 } else {
 		if (slot == 0) {
 			hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
 			hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
-			hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
+			hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
 	    } else {
 			hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
 			hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
-			hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
+			hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
 		}
 	}
 
-	emit_dst(nvfx, vpc, hw, slot, dst);
-	emit_src(nvfx, vpc, hw, 0, s0);
-	emit_src(nvfx, vpc, hw, 1, s1);
-	emit_src(nvfx, vpc, hw, 2, s2);
+	emit_dst(nvfx, vpc, hw, slot, insn.dst);
+	emit_src(nvfx, vpc, hw, 0, insn.src[0]);
+	emit_src(nvfx, vpc, hw, 1, insn.src[1]);
+	emit_src(nvfx, vpc, hw, 2, insn.src[2]);
 }
 
-static inline struct nvfx_sreg
+static inline struct nvfx_src
 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
-	struct nvfx_sreg src = { 0 };
+	struct nvfx_src src;
 
 	switch (fsrc->Register.File) {
 	case TGSI_FILE_INPUT:
-		src = nvfx_sr(NVFXSR_INPUT, fsrc->Register.Index);
+		src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index);
 		break;
 	case TGSI_FILE_CONSTANT:
-		src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
+		src.reg = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
 		break;
 	case TGSI_FILE_IMMEDIATE:
-		src = vpc->imm[fsrc->Register.Index];
+		src.reg = vpc->imm[fsrc->Register.Index];
 		break;
 	case TGSI_FILE_TEMPORARY:
-		src = vpc->r_temp[fsrc->Register.Index];
+		src.reg = vpc->r_temp[fsrc->Register.Index];
 		break;
 	default:
 		NOUVEAU_ERR("bad src file\n");
@@ -371,9 +369,9 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
 	return src;
 }
 
-static INLINE struct nvfx_sreg
+static INLINE struct nvfx_reg
 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
-	struct nvfx_sreg dst = { 0 };
+	struct nvfx_reg dst;
 
 	switch (fdst->Register.File) {
 	case TGSI_FILE_OUTPUT:
@@ -409,8 +407,9 @@ static boolean
 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 				const struct tgsi_full_instruction *finst)
 {
-	struct nvfx_sreg src[3], dst, tmp;
-	struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
+	struct nvfx_src src[3], tmp;
+	struct nvfx_reg dst;
+	struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
 	int mask;
 	int ai = -1, ci = -1, ii = -1;
 	int i;
@@ -438,9 +437,8 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 				ai = fsrc->Register.Index;
 				src[i] = tgsi_src(vpc, fsrc);
 			} else {
-				src[i] = temp(vpc);
-				arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
-				      tgsi_src(vpc, fsrc), none, none);
+				src[i] = nvfx_src(temp(vpc));
+				nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
 			}
 			break;
 		case TGSI_FILE_CONSTANT:
@@ -449,9 +447,8 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 				ci = fsrc->Register.Index;
 				src[i] = tgsi_src(vpc, fsrc);
 			} else {
-				src[i] = temp(vpc);
-				arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
-				      tgsi_src(vpc, fsrc), none, none);
+				src[i] = nvfx_src(temp(vpc));
+				nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
 			}
 			break;
 		case TGSI_FILE_IMMEDIATE:
@@ -460,9 +457,8 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 				ii = fsrc->Register.Index;
 				src[i] = tgsi_src(vpc, fsrc);
 			} else {
-				src[i] = temp(vpc);
-				arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
-				      tgsi_src(vpc, fsrc), none, none);
+				src[i] = nvfx_src(temp(vpc));
+				nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
 			}
 			break;
 		case TGSI_FILE_TEMPORARY:
@@ -479,127 +475,121 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 
 	switch (finst->Instruction.Opcode) {
 	case TGSI_OPCODE_ABS:
-		arith(vpc, VEC, MOV, dst, mask, abs(src[0]), none, none);
+		nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, abs(src[0]), none, none));
 		break;
 	case TGSI_OPCODE_ADD:
-		arith(vpc, VEC, ADD, dst, mask, src[0], none, src[1]);
+		nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, src[1]));
 		break;
 	case TGSI_OPCODE_ARL:
-		arith(vpc, VEC, ARL, dst, mask, src[0], none, none);
+		nvfx_vp_emit(vpc, arith(VEC, ARL, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_COS:
-		arith(vpc, SCA, COS, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_DP3:
-		arith(vpc, VEC, DP3, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, DP3, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_DP4:
-		arith(vpc, VEC, DP4, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, DP4, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_DPH:
-		arith(vpc, VEC, DPH, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, DPH, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_DST:
-		arith(vpc, VEC, DST, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, DST, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_EX2:
-		arith(vpc, SCA, EX2, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_EXP:
-		arith(vpc, SCA, EXP, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, EXP, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_FLR:
-		arith(vpc, VEC, FLR, dst, mask, src[0], none, none);
+		nvfx_vp_emit(vpc, arith(VEC, FLR, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_FRC:
-		arith(vpc, VEC, FRC, dst, mask, src[0], none, none);
+		nvfx_vp_emit(vpc, arith(VEC, FRC, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_LG2:
-		arith(vpc, SCA, LG2, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, LG2, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_LIT:
-		arith(vpc, SCA, LIT, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, LIT, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_LOG:
-		arith(vpc, SCA, LOG, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, LOG, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_LRP:
-		tmp = temp(vpc);
-		arith(vpc, VEC, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
-		arith(vpc, VEC, MAD, dst, mask, src[0], src[1], tmp);
+		tmp = nvfx_src(temp(vpc));
+		nvfx_vp_emit(vpc, arith(VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
+		nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], tmp));
 		break;
 	case TGSI_OPCODE_MAD:
-		arith(vpc, VEC, MAD, dst, mask, src[0], src[1], src[2]);
+		nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], src[2]));
 		break;
 	case TGSI_OPCODE_MAX:
-		arith(vpc, VEC, MAX, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, MAX, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_MIN:
-		arith(vpc, VEC, MIN, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, MIN, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_MOV:
-		arith(vpc, VEC, MOV, dst, mask, src[0], none, none);
+		nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, src[0], none, none));
 		break;
 	case TGSI_OPCODE_MUL:
-		arith(vpc, VEC, MUL, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, MUL, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_POW:
-		tmp = temp(vpc);
-		arith(vpc, SCA, LG2, tmp, NVFX_VP_MASK_X, none, none,
-		      swz(src[0], X, X, X, X));
-		arith(vpc, VEC, MUL, tmp, NVFX_VP_MASK_X, swz(tmp, X, X, X, X),
-		      swz(src[1], X, X, X, X), none);
-		arith(vpc, SCA, EX2, dst, mask, none, none,
-		      swz(tmp, X, X, X, X));
+		tmp = nvfx_src(temp(vpc));
+		nvfx_vp_emit(vpc, arith(SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
+		nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
+		nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X)));
 		break;
 	case TGSI_OPCODE_RCP:
-		arith(vpc, SCA, RCP, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, RCP, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_RET:
 		break;
 	case TGSI_OPCODE_RSQ:
-		arith(vpc, SCA, RSQ, dst, mask, none, none, abs(src[0]));
+		nvfx_vp_emit(vpc, arith(SCA, RSQ, dst, mask, none, none, abs(src[0])));
 		break;
 	case TGSI_OPCODE_SEQ:
-		arith(vpc, VEC, SEQ, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SEQ, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SFL:
-		arith(vpc, VEC, SFL, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SFL, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SGE:
-		arith(vpc, VEC, SGE, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SGE, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SGT:
-		arith(vpc, VEC, SGT, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SGT, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SIN:
-		arith(vpc, SCA, SIN, dst, mask, none, none, src[0]);
+		nvfx_vp_emit(vpc, arith(SCA, SIN, dst, mask, none, none, src[0]));
 		break;
 	case TGSI_OPCODE_SLE:
-		arith(vpc, VEC, SLE, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SLE, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SLT:
-		arith(vpc, VEC, SLT, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SLT, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SNE:
-		arith(vpc, VEC, SNE, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SNE, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SSG:
-		arith(vpc, VEC, SSG, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, SSG, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_STR:
-		arith(vpc, VEC, STR, dst, mask, src[0], src[1], none);
+		nvfx_vp_emit(vpc, arith(VEC, STR, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_SUB:
-		arith(vpc, VEC, ADD, dst, mask, src[0], none, neg(src[1]));
+		nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, neg(src[1])));
 		break;
 	case TGSI_OPCODE_XPD:
-		tmp = temp(vpc);
-		arith(vpc, VEC, MUL, tmp, mask,
-		      swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
-		arith(vpc, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W),
-		      swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
-		      neg(tmp));
+		tmp = nvfx_src(temp(vpc));
+		nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
+		nvfx_vp_emit(vpc, arith(VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
 		break;
 	default:
 		NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
@@ -663,7 +653,7 @@ nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 		return FALSE;
 	}
 
-	vpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
+	vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
 	return TRUE;
 }
 
@@ -758,18 +748,18 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
 	tgsi_parse_free(&p);
 
 	if (nr_imm) {
-		vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_sreg));
+		vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_reg));
 		assert(vpc->imm);
 	}
 
 	if (++high_temp) {
-		vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
+		vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
 		for (i = 0; i < high_temp; i++)
 			vpc->r_temp[i] = temp(vpc);
 	}
 
 	if (++high_addr) {
-		vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_sreg));
+		vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg));
 		for (i = 0; i < high_addr; i++)
 			vpc->r_address[i] = temp(vpc);
 	}
@@ -786,12 +776,13 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 {
 	struct tgsi_parse_context parse;
 	struct nvfx_vpc *vpc = NULL;
-	struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
+	struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
 	int i;
 
 	vpc = CALLOC(1, sizeof(struct nvfx_vpc));
 	if (!vpc)
 		return;
+	vpc->nvfx = nvfx;
 	vpc->vp = vp;
 
 	if (!nvfx_vertprog_prepare(nvfx, vpc)) {
@@ -844,23 +835,23 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 
 	/* Write out HPOS if it was redirected to a temp earlier */
 	if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
-		struct nvfx_sreg hpos = nvfx_sr(NVFXSR_OUTPUT,
+		struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
 						NVFX_VP(INST_DEST_POS));
-		struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
+		struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
 
-		arith(vpc, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none);
+		nvfx_vp_emit(vpc, arith(VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none));
 	}
 
 	/* Insert code to handle user clip planes */
 	for (i = 0; i < vp->ucp.nr; i++) {
-		struct nvfx_sreg cdst = nvfx_sr(NVFXSR_OUTPUT,
+		struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT,
 						NVFX_VP_INST_DEST_CLIP(i));
-		struct nvfx_sreg ceqn = constant(vpc, -1,
+		struct nvfx_src ceqn = nvfx_src(constant(vpc, -1,
 						 nvfx->clip.ucp[i][0],
 						 nvfx->clip.ucp[i][1],
 						 nvfx->clip.ucp[i][2],
-						 nvfx->clip.ucp[i][3]);
-		struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
+						 nvfx->clip.ucp[i][3]));
+		struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
 		unsigned mask;
 
 		switch (i) {
@@ -872,7 +863,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 			goto out_err;
 		}
 
-		arith(vpc, VEC, DP4, cdst, mask, htmp, ceqn, none);
+		nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none));
 	}
 
 	vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
-- 
cgit v1.2.3


From af4a6eba55ad81e343db788a97f3eaa3cf184369 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Fri, 20 Aug 2010 21:16:49 +0200
Subject: nv40: add fragment program control flow

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 247 ++++++++++++++++++++++++++++++-
 src/gallium/drivers/nvfx/nvfx_shader.h   |   5 +
 2 files changed, 247 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index f8c4eae387..91776371e4 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -15,6 +15,7 @@
 
 #define MAX_CONSTS 128
 #define MAX_IMM 32
+
 struct nvfx_fpc {
 	struct nvfx_fragment_program *fp;
 
@@ -38,6 +39,10 @@ struct nvfx_fpc {
 	unsigned nr_imm;
 
 	unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
+
+	struct util_dynarray if_stack;
+	//struct util_dynarray loop_stack;
+	struct util_dynarray label_relocs;
 };
 
 static INLINE struct nvfx_reg
@@ -233,6 +238,134 @@ nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
 	nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
                    (d), (m), (s0), none, none)
 
+/* IF src.x != 0, as TGSI specifies */
+static void
+nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
+{
+	const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
+	struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none);
+	insn.cc_update = 1;
+	nvfx_fp_emit(fpc, insn);
+
+	fpc->inst_offset = fpc->fp->insn_len;
+	grow_insns(fpc, 4);
+	uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+	/* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
+	hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
+		NV40_FP_OP_OUT_NONE |
+		(NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
+	/* Use .xxxx swizzle so that we check only src[0].x*/
+	hw[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
+			(0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
+			(0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
+			(0 << NVFX_FP_OP_COND_SWZ_W_SHIFT) |
+			(NVFX_FP_OP_COND_NE << NVFX_FP_OP_COND_SHIFT);
+	hw[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
+	hw[3] = 0; /* | endif_offset */
+	util_dynarray_append(&fpc->if_stack, unsigned, fpc->inst_offset);
+}
+
+/* IF src.x != 0, as TGSI specifies */
+static void
+nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
+{
+        struct nvfx_label_relocation reloc;
+        fpc->inst_offset = fpc->fp->insn_len;
+        grow_insns(fpc, 4);
+        uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+        /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
+        hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
+        /* Use .xxxx swizzle so that we check only src[0].x*/
+        hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
+                        (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
+        hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
+        hw[3] = 0;
+        reloc.target = target;
+        reloc.location = fpc->inst_offset + 2;
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+}
+
+static void
+nv40_fp_ret(struct nvfx_fpc *fpc)
+{
+	fpc->inst_offset = fpc->fp->insn_len;
+	grow_insns(fpc, 4);
+	uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+	/* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
+	hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
+	/* Use .xxxx swizzle so that we check only src[0].x*/
+	hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
+			(NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
+	hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
+	hw[3] = 0;
+}
+
+static void
+nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
+{
+        struct nvfx_label_relocation reloc;
+        fpc->inst_offset = fpc->fp->insn_len;
+        grow_insns(fpc, 4);
+        uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+        /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
+        hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
+                        NV40_FP_OP_OUT_NONE |
+                        (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
+        /* Use .xxxx swizzle so that we check only src[0].x*/
+        hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
+                        (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
+        hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH |
+                        (count << NV40_FP_OP_REP_COUNT1_SHIFT) |
+                        (count << NV40_FP_OP_REP_COUNT2_SHIFT) |
+                        (count << NV40_FP_OP_REP_COUNT3_SHIFT);
+        hw[3] = 0; /* | end_offset */
+        reloc.target = target;
+        reloc.location = fpc->inst_offset + 3;
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+        //util_dynarray_append(&fpc->loop_stack, unsigned, target);
+}
+
+/* warning: this only works forward, and probably only if not inside any IF */
+static void
+nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
+{
+        struct nvfx_label_relocation reloc;
+        fpc->inst_offset = fpc->fp->insn_len;
+        grow_insns(fpc, 4);
+        uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+        /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
+        hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
+                NV40_FP_OP_OUT_NONE |
+                (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
+        /* Use .xxxx swizzle so that we check only src[0].x*/
+        hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
+                        (NVFX_FP_OP_COND_FL << NVFX_FP_OP_COND_SHIFT);
+        hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | else_offset */
+        hw[3] = 0; /* | endif_offset */
+        reloc.target = target;
+        reloc.location = fpc->inst_offset + 2;
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+        reloc.target = target;
+        reloc.location = fpc->inst_offset + 3;
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+}
+
+static void
+nv40_fp_brk(struct nvfx_fpc *fpc)
+{
+	fpc->inst_offset = fpc->fp->insn_len;
+	grow_insns(fpc, 4);
+	uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+	/* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
+	hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
+		NV40_FP_OP_OUT_NONE;
+	/* Use .xxxx swizzle so that we check only src[0].x*/
+	hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
+			(NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
+	hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH;
+	hw[3] = 0;
+}
+
 static INLINE struct nvfx_src
 tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
 {
@@ -516,9 +649,6 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 	case TGSI_OPCODE_RCP:
 		nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
 		break;
-	case TGSI_OPCODE_RET:
-		assert(0);
-		break;
 	case TGSI_OPCODE_RFL:
 		if(!nvfx->is_nv4x)
 			nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
@@ -604,13 +734,106 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 		nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
 		nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
 		break;
-	default:
+
+	case TGSI_OPCODE_IF:
+		// MOVRC0 R31 (TR0.xyzw), R<src>:
+		// IF (NE.xxxx) ELSE <else> END <end>
+		if(!nvfx->is_nv4x)
+			goto nv3x_cflow;
+		nv40_fp_if(fpc, src[0]);
+		break;
+
+	case TGSI_OPCODE_ELSE:
+	{
+		if(!nvfx->is_nv4x)
+			goto nv3x_cflow;
+		assert(util_dynarray_contains(&fpc->if_stack, unsigned));
+		uint32_t *hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
+		hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
+		break;
+	}
+
+	case TGSI_OPCODE_ENDIF:
+	{
+		if(!nvfx->is_nv4x)
+			goto nv3x_cflow;
+		assert(util_dynarray_contains(&fpc->if_stack, unsigned));
+		uint32_t *hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
+		if(!hw[2])
+			hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
+		hw[3] = fpc->fp->insn_len;
+		break;
+	}
+
+	case TGSI_OPCODE_BRA:
+		/* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
+		/* no state tracker uses this, so don't implement this for now */
+		assert(0);
+		nv40_fp_bra(fpc, finst->Label.Label);
+		break;
+
+	case TGSI_OPCODE_BGNSUB:
+	case TGSI_OPCODE_ENDSUB:
+		/* nothing to do here */
+		break;
+
+	case TGSI_OPCODE_CAL:
+		if(!nvfx->is_nv4x)
+			goto nv3x_cflow;
+		nv40_fp_cal(fpc, finst->Label.Label);
+		break;
+
+	case TGSI_OPCODE_RET:
+		if(!nvfx->is_nv4x)
+			goto nv3x_cflow;
+		nv40_fp_ret(fpc);
+		break;
+
+	case TGSI_OPCODE_BGNLOOP:
+		if(!nvfx->is_nv4x)
+			goto nv3x_cflow;
+		/* TODO: we should support using two nested REPs to allow a > 255 iteration count */
+		nv40_fp_rep(fpc, 255, finst->Label.Label);
+		break;
+
+	case TGSI_OPCODE_ENDLOOP:
+		break;
+
+	case TGSI_OPCODE_BRK:
+		if(!nvfx->is_nv4x)
+			goto nv3x_cflow;
+		nv40_fp_brk(fpc);
+		break;
+
+	case TGSI_OPCODE_CONT:
+	{
+		static int warned = 0;
+		if(!warned) {
+			NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
+			warned = 1;
+		}
+		break;
+	}
+
+        default:
 		NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
 		return FALSE;
 	}
 
+out:
 	release_temps(fpc);
 	return TRUE;
+nv3x_cflow:
+	{
+		static int warned = 0;
+		if(!warned) {
+			NOUVEAU_ERR(
+					"Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
+					"If rendering is incorrect, try to disable GLSL support in the application.\n");
+			warned = 1;
+		}
+	}
+	goto out;
 }
 
 static boolean
@@ -734,6 +957,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 {
 	struct tgsi_parse_context parse;
 	struct nvfx_fpc *fpc = NULL;
+	struct util_dynarray insns;
 
 	fpc = CALLOC(1, sizeof(struct nvfx_fpc));
 	if (!fpc)
@@ -748,6 +972,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 
 	tgsi_parse_init(&parse, fp->pipe.tokens);
 
+	util_dynarray_init(&insns);
 	while (!tgsi_parse_end_of_tokens(&parse)) {
 		tgsi_parse_token(&parse);
 
@@ -756,6 +981,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 		{
 			const struct tgsi_full_instruction *finst;
 
+			util_dynarray_append(&insns, unsigned, fp->insn_len);
 			finst = &parse.FullToken.FullInstruction;
 			if (!nvfx_fragprog_parse_instruction(nvfx, fpc, finst))
 				goto out_err;
@@ -765,6 +991,14 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 			break;
 		}
 	}
+	util_dynarray_append(&insns, unsigned, fp->insn_len);
+
+	for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_label_relocation))
+	{
+		struct nvfx_label_relocation* label_reloc = (struct nvfx_label_relocation*)((char*)fpc->label_relocs.data + i);
+		fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
+	}
+	util_dynarray_fini(&insns);
 
 	if(!nvfx->is_nv4x)
 		fp->fp_control |= (fpc->num_regs-1)/2;
@@ -775,7 +1009,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 	if(fp->insn)
 		fp->insn[fpc->inst_offset] |= 0x00000001;
 
-	/* Append NOP + END instruction, may or may not be necessary. */
+	/* Append NOP + END instruction for branches to the end of the program */
 	fpc->inst_offset = fp->insn_len;
 	grow_insns(fpc, 4);
 	fp->insn[fpc->inst_offset + 0] = 0x00000001;
@@ -799,6 +1033,9 @@ out_err:
 	tgsi_parse_free(&parse);
 	if (fpc->r_temp)
 		FREE(fpc->r_temp);
+	util_dynarray_fini(&fpc->if_stack);
+	util_dynarray_fini(&fpc->label_relocs);
+	//util_dynarray_fini(&fpc->loop_stack);
 	FREE(fpc);
 }
 
diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h
index fcf577ca74..52e684aec3 100644
--- a/src/gallium/drivers/nvfx/nvfx_shader.h
+++ b/src/gallium/drivers/nvfx/nvfx_shader.h
@@ -509,4 +509,9 @@ nvfx_src_abs(struct nvfx_src src)
 	return src;
 }
 
+struct nvfx_label_relocation {
+        unsigned location;
+        unsigned target;
+};
+
 #endif
-- 
cgit v1.2.3


From 5287d86a0b818fd0a7cba6d7728b701663ea78a5 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 18:37:01 +0200
Subject: nvfx: fix vertex shader headers

---
 src/gallium/drivers/nvfx/nv30_vertprog.h | 4 ++--
 src/gallium/drivers/nvfx/nv40_vertprog.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv30_vertprog.h b/src/gallium/drivers/nvfx/nv30_vertprog.h
index ec0444c07f..df92469078 100644
--- a/src/gallium/drivers/nvfx/nv30_vertprog.h
+++ b/src/gallium/drivers/nvfx/nv30_vertprog.h
@@ -68,7 +68,7 @@
 #define NV30_VP_INST_DEST_TEMP_ID_SHIFT        16
 #define NV30_VP_INST_DEST_TEMP_ID_MASK        (0x0F << 16)
 #define NV30_VP_INST_COND_UPDATE_ENABLE        (1<<15)
-#define NV30_VP_INST_VEC_DEST_TEMP_MASK      (0xF << 16)
+#define NV30_VP_INST_VEC_DEST_TEMP_MASK      (0x1F << 16)
 #define NV30_VP_INST_COND_TEST_ENABLE        (1<<14)
 #define NV30_VP_INST_COND_SHIFT          11
 #define NV30_VP_INST_COND_MASK          (0x07 << 11)
@@ -111,7 +111,7 @@
 #define NV30_VP_INST_SRC2H_SHIFT        0    /*NV20*/
 #define NV30_VP_INST_SRC2H_MASK          (0x7FF << 0)  /* NV30_VP_SRC2_HIGH_MASK >> 4*/
 #define NV30_VP_INST_IADDR_SHIFT        2
-#define NV30_VP_INST_IADDR_MASK          (0xF <<  28)   /* NV30_VP_SRC2_LOW_MASK << 28 */
+#define NV30_VP_INST_IADDR_MASK          (0x1FF <<  2)   /* NV30_VP_SRC2_LOW_MASK << 28 */
 
 /* DWORD 3 */
 #define NV30_VP_INST_SRC2L_SHIFT        28    /*NV20*/
diff --git a/src/gallium/drivers/nvfx/nv40_vertprog.h b/src/gallium/drivers/nvfx/nv40_vertprog.h
index 7337293bab..3d0a1fe3d1 100644
--- a/src/gallium/drivers/nvfx/nv40_vertprog.h
+++ b/src/gallium/drivers/nvfx/nv40_vertprog.h
@@ -44,7 +44,7 @@
 #define NV40_VP_INST_SRC1_ABS                                          (1 << 22)
 #define NV40_VP_INST_SRC0_ABS                                          (1 << 21)
 #define NV40_VP_INST_VEC_DEST_TEMP_SHIFT                                      15
-#define NV40_VP_INST_VEC_DEST_TEMP_MASK                             (0x1F << 15)
+#define NV40_VP_INST_VEC_DEST_TEMP_MASK                             (0x3F << 15)
 #define NV40_VP_INST_COND_TEST_ENABLE                                  (1 << 13)
 #define NV40_VP_INST_COND_SHIFT                                               10
 #define NV40_VP_INST_COND_MASK                                       (0x7 << 10)
@@ -100,7 +100,7 @@
 #define NV40_VP_INST_SRC2H_SHIFT                                               0
 #define NV40_VP_INST_SRC2H_MASK                                      (0x3F << 0)
 #define NV40_VP_INST_IADDRH_SHIFT                                              0
-#define NV40_VP_INST_IADDRH_MASK                                     (0x1F << 0)
+#define NV40_VP_INST_IADDRH_MASK                                     (0x3F << 0)
 
 /* ---- OPCODE BITS 31:0 / data DWORD 3 --- */
 #define NV40_VP_INST_IADDRL_SHIFT                                             29
-- 
cgit v1.2.3


From fe3c62dd7728f1cab64978d634fd0be4237d3b23 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 18:37:21 +0200
Subject: nvfx: add vertex program control flow

---
 src/gallium/drivers/nvfx/nvfx_state.h    |   3 +-
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 184 ++++++++++++++++++++++++++++---
 2 files changed, 169 insertions(+), 18 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
index e1fa3c7e04..6d589af5f3 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ b/src/gallium/drivers/nvfx/nvfx_state.h
@@ -9,7 +9,6 @@
 
 struct nvfx_vertex_program_exec {
 	uint32_t data[4];
-	boolean has_branch_offset;
 	int const_index;
 };
 
@@ -45,6 +44,8 @@ struct nvfx_vertex_program {
 	uint32_t ir;
 	uint32_t or;
 	uint32_t clip_ctrl;
+
+	struct util_dynarray branch_relocs;
 };
 
 struct nvfx_fragment_program_data {
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 416e1b4d45..98fcc92898 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -29,6 +29,12 @@
 
 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
 
+struct nvfx_loop_entry
+{
+	unsigned brk_target;
+	unsigned cont_target;
+};
+
 struct nvfx_vpc {
 	struct nvfx_context* nvfx;
 	struct nvfx_vertex_program *vp;
@@ -45,6 +51,9 @@ struct nvfx_vpc {
 	unsigned nr_imm;
 
 	unsigned hpos_idx;
+
+	struct util_dynarray label_relocs;
+	struct util_dynarray loop_stack;
 };
 
 static struct nvfx_reg
@@ -169,6 +178,17 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 	struct nvfx_vertex_program *vp = vpc->vp;
 
 	switch (dst.type) {
+	case NVFXSR_NONE:
+		if(!nvfx->is_nv4x)
+			hw[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK;
+		else {
+			hw[3] |= NV40_VP_INST_DEST_MASK;
+			if (slot == 0)
+				hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
+			else
+				hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
+		}
+		break;
 	case NVFXSR_TEMP:
 		if(!nvfx->is_nv4x)
 			hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
@@ -254,7 +274,7 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 
 		if(!nvfx->is_nv4x) {
 			hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
-			hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
+			hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK;
 
 			/*XXX: no way this is entirely correct, someone needs to
 			 *     figure out what exactly it is.
@@ -264,7 +284,7 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 			hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
 			if (slot == 0) {
 				hw[0] |= NV40_VP_INST_VEC_RESULT;
-				hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
+				hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
 			} else {
 				hw[3] |= NV40_VP_INST_SCA_RESULT;
 				hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
@@ -292,11 +312,13 @@ nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
 
 	hw = vpc->vpi->data;
 
-	hw[0] |= (NVFX_COND_TR << NVFX_VP(INST_COND_SHIFT));
-	hw[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
-		  (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
-		  (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
-		  (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
+	hw[0] |= (insn.cc_test << NVFX_VP(INST_COND_SHIFT));
+	hw[0] |= ((insn.cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
+		  (insn.cc_swz[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
+		  (insn.cc_swz[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
+		  (insn.cc_swz[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
+	if(insn.cc_update)
+		hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE);
 
 	if(!nvfx->is_nv4x) {
 		if(slot == 0)
@@ -327,7 +349,7 @@ nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
 			hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
 	    } else {
 			hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
-			hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
+			hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK ;
 			hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
 		}
 	}
@@ -374,6 +396,9 @@ tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
 	struct nvfx_reg dst;
 
 	switch (fdst->Register.File) {
+	case TGSI_FILE_NULL:
+		dst = nvfx_reg(NVFXSR_NONE, 0);
+		break;
 	case TGSI_FILE_OUTPUT:
 		dst = vpc->r_result[fdst->Register.Index];
 		break;
@@ -405,11 +430,14 @@ tgsi_mask(uint tgsi)
 
 static boolean
 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
-				const struct tgsi_full_instruction *finst)
+				unsigned idx, const struct tgsi_full_instruction *finst)
 {
 	struct nvfx_src src[3], tmp;
 	struct nvfx_reg dst;
 	struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
+	struct nvfx_insn insn;
+	struct nvfx_label_relocation reloc;
+	struct nvfx_loop_entry loop;
 	int mask;
 	int ai = -1, ci = -1, ii = -1;
 	int i;
@@ -548,8 +576,6 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 	case TGSI_OPCODE_RCP:
 		nvfx_vp_emit(vpc, arith(SCA, RCP, dst, mask, none, none, src[0]));
 		break;
-	case TGSI_OPCODE_RET:
-		break;
 	case TGSI_OPCODE_RSQ:
 		nvfx_vp_emit(vpc, arith(SCA, RSQ, dst, mask, none, none, abs(src[0])));
 		break;
@@ -591,6 +617,84 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 		nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
 		nvfx_vp_emit(vpc, arith(VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
 		break;
+
+	case TGSI_OPCODE_IF:
+		insn = arith(VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none);
+		insn.cc_update = 1;
+		nvfx_vp_emit(vpc, insn);
+
+		reloc.location = vpc->vp->nr_insns;
+		reloc.target = finst->Label.Label + 1;
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+
+		insn = arith(SCA, BRA, none.reg, 0, none, none, none);
+		insn.cc_test = NVFX_COND_EQ;
+		insn.cc_swz[0] = insn.cc_swz[1] = insn.cc_swz[2] = insn.cc_swz[3] = 0;
+		nvfx_vp_emit(vpc, insn);
+		break;
+
+	case TGSI_OPCODE_ELSE:
+	case TGSI_OPCODE_BRA:
+	case TGSI_OPCODE_CAL:
+		reloc.location = vpc->vp->nr_insns;
+		reloc.target = finst->Label.Label;
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+
+		if(finst->Instruction.Opcode == TGSI_OPCODE_CAL)
+			insn = arith(SCA, CAL, none.reg, 0, none, none, none);
+		else
+			insn = arith(SCA, BRA, none.reg, 0, none, none, none);
+		nvfx_vp_emit(vpc, insn);
+		break;
+
+	case TGSI_OPCODE_RET:
+		tmp = none;
+		tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0;
+		nvfx_vp_emit(vpc, arith(SCA, RET, none.reg, 0, none, none, tmp));
+		break;
+
+	case TGSI_OPCODE_BGNSUB:
+	case TGSI_OPCODE_ENDSUB:
+	case TGSI_OPCODE_ENDIF:
+		/* nothing to do here */
+		break;
+
+	case TGSI_OPCODE_BGNLOOP:
+		loop.cont_target = idx;
+		loop.brk_target = finst->Label.Label + 1;
+		util_dynarray_append(&vpc->loop_stack, struct nvfx_loop_entry, loop);
+		break;
+
+	case TGSI_OPCODE_ENDLOOP:
+		loop = util_dynarray_pop(&vpc->loop_stack, struct nvfx_loop_entry);
+
+		reloc.location = vpc->vp->nr_insns;
+		reloc.target = loop.cont_target;
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+
+		nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
+		break;
+
+	case TGSI_OPCODE_CONT:
+		loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
+
+		reloc.location = vpc->vp->nr_insns;
+		reloc.target = loop.cont_target;
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+
+		nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
+		break;
+
+	case TGSI_OPCODE_BRK:
+		loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
+
+		reloc.location = vpc->vp->nr_insns;
+		reloc.target = loop.brk_target;
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+
+		nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
+		break;
+
 	default:
 		NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
 		return FALSE;
@@ -777,6 +881,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 	struct tgsi_parse_context parse;
 	struct nvfx_vpc *vpc = NULL;
 	struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
+	struct util_dynarray insns;
 	int i;
 
 	vpc = CALLOC(1, sizeof(struct nvfx_vpc));
@@ -801,6 +906,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 
 	tgsi_parse_init(&parse, vp->pipe.tokens);
 
+	util_dynarray_init(&insns);
 	while (!tgsi_parse_end_of_tokens(&parse)) {
 		tgsi_parse_token(&parse);
 
@@ -823,8 +929,10 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 		case TGSI_TOKEN_TYPE_INSTRUCTION:
 		{
 			const struct tgsi_full_instruction *finst;
+			unsigned idx = insns.size >> 2;
+			util_dynarray_append(&insns, unsigned, vp->nr_insns);
 			finst = &parse.FullToken.FullInstruction;
-			if (!nvfx_vertprog_parse_instruction(nvfx, vpc, finst))
+			if (!nvfx_vertprog_parse_instruction(nvfx, vpc, idx, finst))
 				goto out_err;
 		}
 			break;
@@ -833,6 +941,25 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 		}
 	}
 
+	util_dynarray_append(&insns, unsigned, vp->nr_insns);
+
+	for(unsigned i = 0; i < vpc->label_relocs.size; i += sizeof(struct nvfx_label_relocation))
+	{
+		struct nvfx_label_relocation* label_reloc = (struct nvfx_label_relocation*)((char*)vpc->label_relocs.data + i);
+		struct nvfx_label_relocation hw_reloc;
+
+		hw_reloc.location = label_reloc->location;
+		hw_reloc.target = ((unsigned*)insns.data)[label_reloc->target];
+
+		//debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
+
+		util_dynarray_append(&vp->branch_relocs, struct nvfx_label_relocation, hw_reloc);
+	}
+	util_dynarray_fini(&insns);
+	util_dynarray_trim(&vp->branch_relocs);
+
+	/* XXX: what if we add a RET before?!  make sure we jump here...*/
+
 	/* Write out HPOS if it was redirected to a temp earlier */
 	if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
 		struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
@@ -866,7 +993,11 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 		nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none));
 	}
 
-	vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
+	//vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
+
+	/* Append NOP + END instruction for branches to the end of the program */
+	nvfx_vp_emit(vpc, arith(VEC, NOP, none.reg, 0, none, none, none));
+        vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST | 0x1000;
 
 	if(debug_get_option_nvfx_dump_vp())
 	{
@@ -879,9 +1010,12 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 		debug_printf("\n");
 	}
 
+	vp->exec_start = -1;
 	vp->translated = TRUE;
 out_err:
 	tgsi_parse_free(&parse);
+	util_dynarray_fini(&vpc->label_relocs);
+	util_dynarray_fini(&vpc->loop_stack);
 	if (vpc->r_temp)
 		FREE(vpc->r_temp);
 	if (vpc->r_address)
@@ -977,11 +1111,27 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 	 * fixup offsets and register IDs.
 	 */
 	if (vp->exec_start != vp->exec->start) {
-		for (i = 0; i < vp->nr_insns; i++) {
-			struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
+		//printf("vp_relocs %u -> %u\n", vp->exec_start, vp->exec->start);
+		for(unsigned i = 0; i < vp->branch_relocs.size; i += sizeof(struct nvfx_label_relocation))
+		{
+			struct nvfx_label_relocation* reloc = (struct nvfx_label_relocation*)((char*)vp->branch_relocs.data + i);
+			uint32_t* hw = vp->insns[reloc->location].data;
+			unsigned target = vp->exec->start + reloc->target;
 
-			if (vpi->has_branch_offset) {
-				assert(0);
+			//debug_printf("vp_reloc hw %u -> hw %u\n", reloc->location, target);
+
+			if(!nvfx->is_nv4x)
+			{
+				hw[2] &=~ NV30_VP_INST_IADDR_MASK;
+				hw[2] |= (target & 0x1ff) << NV30_VP_INST_IADDR_SHIFT;
+			}
+			else
+			{
+				hw[3] &=~ NV40_VP_INST_IADDRL_MASK;
+				hw[3] |= (target & 7) << NV40_VP_INST_IADDRL_SHIFT;
+
+				hw[2] &=~ NV40_VP_INST_IADDRH_MASK;
+				hw[2] |= ((target >> 3) & 0x3f) << NV40_VP_INST_IADDRH_SHIFT;
 			}
 		}
 
-- 
cgit v1.2.3


From 587d26fdf9c58503333e4e7603a115881a80260b Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 19:45:06 +0200
Subject: nvfx: implement NOP

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 2 ++
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 2 ++
 2 files changed, 4 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 91776371e4..2b749efece 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -636,6 +636,8 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 	case TGSI_OPCODE_MUL:
 		nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
 		break;
+	case TGSI_OPCODE_NOP:
+		break;
 	case TGSI_OPCODE_POW:
 		if(!nvfx->is_nv4x)
 			nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 98fcc92898..2894532bd1 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -567,6 +567,8 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 	case TGSI_OPCODE_MUL:
 		nvfx_vp_emit(vpc, arith(VEC, MUL, dst, mask, src[0], src[1], none));
 		break;
+	case TGSI_OPCODE_NOP:
+		break;
 	case TGSI_OPCODE_POW:
 		tmp = nvfx_src(temp(vpc));
 		nvfx_vp_emit(vpc, arith(SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
-- 
cgit v1.2.3


From 4aec8aa2e33b0bf9d5e8c292d604fe988e439bca Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 19:35:06 +0200
Subject: nvfx: implement TRUNC in vp and fp

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 25 +++++++++++++++++++------
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 13 +++++++++++++
 2 files changed, 32 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 2b749efece..2c24d523c4 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -725,12 +725,25 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 	case TGSI_OPCODE_TEX:
 		nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
 		break;
-	case TGSI_OPCODE_TXB:
-		nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
-		break;
-	case TGSI_OPCODE_TXP:
-		nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
-		break;
+        case TGSI_OPCODE_TRUNC:
+                tmp = nvfx_src(temp(fpc));
+                insn = arith(0, MOV, none.reg, mask, src[0], none, none);
+                insn.cc_update = 1;
+                nvfx_fp_emit(fpc, insn);
+
+                nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, abs(src[0]), none, none));
+                nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, tmp, none, none));
+
+                insn = arith(sat, MOV, dst, mask, neg(tmp), none, none);
+                insn.cc_test = NVFX_COND_LT;
+                nvfx_fp_emit(fpc, insn);
+                break;
+        case TGSI_OPCODE_TXB:
+                nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
+                break;
+        case TGSI_OPCODE_TXP:
+                nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
+                break;
 	case TGSI_OPCODE_XPD:
 		tmp = nvfx_src(temp(fpc));
 		nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 2894532bd1..d68224ce7a 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -614,6 +614,19 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 	case TGSI_OPCODE_SUB:
 		nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, neg(src[1])));
 		break;
+        case TGSI_OPCODE_TRUNC:
+                tmp = nvfx_src(temp(vpc));
+                insn = arith(VEC, MOV, none.reg, mask, src[0], none, none);
+                insn.cc_update = 1;
+                nvfx_vp_emit(vpc, insn);
+
+                nvfx_vp_emit(vpc, arith(VEC, FLR, tmp.reg, mask, abs(src[0]), none, none));
+                nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, tmp, none, none));
+
+                insn = arith(VEC, MOV, dst, mask, neg(tmp), none, none);
+                insn.cc_test = NVFX_COND_LT;
+                nvfx_vp_emit(vpc, insn);
+                break;
 	case TGSI_OPCODE_XPD:
 		tmp = nvfx_src(temp(vpc));
 		nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
-- 
cgit v1.2.3


From 32d2525d645e4a06a116a1c0433bda0dd3bc245f Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 19:43:46 +0200
Subject: nvfx: implement DP2 in vp and fp

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 5 +++++
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 5 +++++
 2 files changed, 10 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 2c24d523c4..40cd410e9b 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -573,6 +573,11 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 			nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
 		}
 		break;
+	case TGSI_OPCODE_DP2:
+		tmp = nvfx_src(temp(fpc));
+		nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], src[1], none));
+		nvfx_fp_emit(fpc, arith(0, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
+		break;
 	case TGSI_OPCODE_DP3:
 		nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
 		break;
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index d68224ce7a..6b19d86a18 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -514,6 +514,11 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 	case TGSI_OPCODE_COS:
 		nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0]));
 		break;
+        case TGSI_OPCODE_DP2:
+                tmp = nvfx_src(temp(vpc));
+                nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none));
+                nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
+                break;
 	case TGSI_OPCODE_DP3:
 		nvfx_vp_emit(vpc, arith(VEC, DP3, dst, mask, src[0], src[1], none));
 		break;
-- 
cgit v1.2.3


From 847ac88671ce4315eb03fcd1d746d20ee03379af Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 20:05:04 +0200
Subject: nvfx: implement SSG in fp

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 40cd410e9b..ebd3eb88c1 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -457,7 +457,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 {
 	const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
 	struct nvfx_insn insn;
-	struct nvfx_src src[3], tmp;
+	struct nvfx_src src[3], tmp, tmp2;
 	struct nvfx_reg dst;
 	int mask, sat, unit = 0;
 	int ai = -1, ci = -1, ii = -1;
@@ -721,6 +721,13 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 	case TGSI_OPCODE_SNE:
 		nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
 		break;
+	case TGSI_OPCODE_SSG:
+		tmp = nvfx_src(temp(fpc));
+		tmp2 = nvfx_src(temp(fpc));
+		nvfx_fp_emit(fpc, arith(0, SGT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none));
+		nvfx_fp_emit(fpc, arith(0, SLT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none));
+		nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, tmp, neg(tmp2), none));
+		break;
 	case TGSI_OPCODE_STR:
 		nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
 		break;
@@ -896,6 +903,8 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 	struct tgsi_parse_context p;
 	int high_temp = -1, i;
 	struct util_semantic_set set;
+	float const0v[4] = {0, 0, 0, 0};
+	struct nvfx_reg const0;
 
 	fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->fp->pipe.tokens, TGSI_FILE_INPUT);
 	if(fpc->fp->num_slots > 8)
@@ -905,6 +914,9 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 
 	memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
 
+	const0 = constant(fpc, -1, const0v);
+	assert(const0.index == 0);
+
 	tgsi_parse_init(&p, fpc->fp->pipe.tokens);
 	while (!tgsi_parse_end_of_tokens(&p)) {
 		const union tgsi_full_token *tok = &p.FullToken;
-- 
cgit v1.2.3


From 923f5c97b14c107ba647c1c3eb81d81000c301f3 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 20:07:48 +0200
Subject: nvfx: implement TXL in fp

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index ebd3eb88c1..f9b3e075a0 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -753,6 +753,12 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
         case TGSI_OPCODE_TXB:
                 nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
                 break;
+        case TGSI_OPCODE_TXL:
+                if(nvfx->is_nv4x)
+                        nvfx_fp_emit(fpc, tex(sat, TXL_NV40, unit, dst, mask, src[0], none, none));
+                else /* unsupported on nv30, use TEX and hope they like it */
+                        nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
+                break;
         case TGSI_OPCODE_TXP:
                 nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
                 break;
-- 
cgit v1.2.3


From 8983621c6b39d74e0f30fa97fb8b4b362eddc87c Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 20:14:16 +0200
Subject: nvfx: implement CMP in vp

---
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 6b19d86a18..8ca7cfef74 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -511,6 +511,19 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 	case TGSI_OPCODE_ARL:
 		nvfx_vp_emit(vpc, arith(VEC, ARL, dst, mask, src[0], none, none));
 		break;
+	case TGSI_OPCODE_CMP:
+		insn = arith(VEC, MOV, none.reg, mask, src[0], none, none);
+		insn.cc_update = 1;
+		nvfx_vp_emit(vpc, insn);
+
+		insn = arith(VEC, MOV, dst, mask, src[2], none, none);
+		insn.cc_test = NVFX_COND_GE;
+		nvfx_vp_emit(vpc, insn);
+
+		insn = arith(VEC, MOV, dst, mask, src[1], none, none);
+		insn.cc_test = NVFX_COND_LT;
+		nvfx_vp_emit(vpc, insn);
+		break;
 	case TGSI_OPCODE_COS:
 		nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0]));
 		break;
-- 
cgit v1.2.3


From 5eddf95be992d1d6cafe567068ca4c12b0ee2b4a Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 20:14:35 +0200
Subject: nvfx: tweak CMP in fp

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index f9b3e075a0..dc681f4d4d 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -536,7 +536,7 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 		nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
 		break;
 	case TGSI_OPCODE_CMP:
-		insn = arith(0, MOV, none.reg, 0xf, src[0], none, none);
+		insn = arith(0, MOV, none.reg, mask, src[0], none, none);
 		insn.cc_update = 1;
 		nvfx_fp_emit(fpc, insn);
 
-- 
cgit v1.2.3


From d8e210eb111324482450c8bdbb19e29a805b088e Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 20:23:41 +0200
Subject: nvfx: slightly improve handling of overlong vps

---
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 8ca7cfef74..7cccffe0ff 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -1110,7 +1110,11 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 			}
 
 			if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
-				assert(0);
+			{
+				debug_printf("Vertex shader too long: %u instructions\n", vplen);
+				nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
+				return FALSE;
+			}
 		}
 
 		upload_code = TRUE;
@@ -1129,7 +1133,11 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 			}
 
 			if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
-				assert(0);
+                        {
+                                debug_printf("Vertex shader uses too many constants: %u constants\n", vp->nr_consts);
+                                nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
+                                return FALSE;
+                        }
 		}
 
 		/*XXX: handle this some day */
-- 
cgit v1.2.3


From 1badd3c43fdb21d30a14763c681b26d9dc5924fb Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 12:00:57 -0700
Subject: scons: Fix nvfx build.

---
 src/gallium/drivers/nvfx/SConscript | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/SConscript b/src/gallium/drivers/nvfx/SConscript
index 02d931b10e..80e3ef2257 100644
--- a/src/gallium/drivers/nvfx/SConscript
+++ b/src/gallium/drivers/nvfx/SConscript
@@ -9,7 +9,7 @@ env.PrependUnique(delete_existing=1, CPPPATH = [
 nvfx = env.ConvenienceLibrary(
     target = 'nvfx',
     source = [
-        'nv04_surface_2d.c',
+        'nv04_2d.c',
         'nvfx_buffer.c',
         'nvfx_context.c',
         'nvfx_clear.c',
@@ -19,6 +19,7 @@ nvfx = env.ConvenienceLibrary(
         'nv30_fragtex.c',
         'nv40_fragtex.c',
         'nvfx_miptree.c',
+        'nvfx_push.c',
         'nvfx_query.c',
         'nvfx_resource.c',
         'nvfx_screen.c',
-- 
cgit v1.2.3


From 42210f44645c154983705a2caea6af8fbdafbc12 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 21:29:18 +0200
Subject: nvfx: enable translate_sse

---
 src/gallium/drivers/nvfx/nvfx_vbo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index a6cd125635..abd7706512 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -513,7 +513,7 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe,
 		}
 	}
 
-	cso->translate = translate_generic_create(&transkey);
+	cso->translate = translate_create(&transkey);
 	cso->vertex_length = transkey.output_stride >> 2;
 	cso->max_vertices_per_packet = 2047 / cso->vertex_length;
 
-- 
cgit v1.2.3


From 11d27871a79fb7ffcf0e139a8c04d90991969023 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 22:48:29 +0200
Subject: nvfx: fix warnings

---
 src/gallium/drivers/nvfx/nvfx_context.h  | 2 +-
 src/gallium/drivers/nvfx/nvfx_vbo.c      | 1 -
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 4 +---
 3 files changed, 2 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 04447da3e1..83c44ef477 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -312,7 +312,7 @@ extern void nvfx_vertprog_destroy(struct nvfx_context *,
 extern void nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info);
 
 /* must WAIT_RING(chan, ncomp + 1) or equivalent beforehand! */
-static inline void nvfx_emit_vtx_attr(struct nouveau_channel* chan, unsigned attrib, float* v, unsigned ncomp)
+static inline void nvfx_emit_vtx_attr(struct nouveau_channel* chan, unsigned attrib, const float* v, unsigned ncomp)
 {
 	switch (ncomp) {
 	case 4:
diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index abd7706512..d1e7199287 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -419,7 +419,6 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe,
 			  unsigned num_elements,
 			  const struct pipe_vertex_element *elements)
 {
-	struct nvfx_context* nvfx = nvfx_context(pipe);
 	struct nvfx_vtxelt_state *cso = CALLOC_STRUCT(nvfx_vtxelt_state);
         struct translate_key transkey;
         unsigned per_vertex_size[16];
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 7cccffe0ff..b5dde2592e 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -801,7 +801,6 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
 	int high_temp = -1, high_addr = -1, nr_imm = 0, i;
 	struct util_semantic_set set;
 	unsigned char sem_layout[8];
-	unsigned sem_layout_size;
 	unsigned num_outputs;
 
 	num_outputs = util_semantic_set_from_program_file(&set, vpc->vp->pipe.tokens, TGSI_FILE_OUTPUT);
@@ -1061,7 +1060,6 @@ out_err:
 boolean
 nvfx_vertprog_validate(struct nvfx_context *nvfx)
 {
-	struct pipe_context *pipe = &nvfx->pipe;
 	struct nvfx_screen *screen = nvfx->screen;
 	struct nouveau_channel *chan = screen->base.channel;
 	struct nouveau_grobj *eng3d = screen->eng3d;
@@ -1200,7 +1198,7 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 		float *map = NULL;
 
 		if (constbuf)
-			map = nvfx_buffer(constbuf)->data;
+			map = (float*)nvfx_buffer(constbuf)->data;
 
 		for (i = 0; i < vp->nr_consts; i++) {
 			struct nvfx_vertex_program_data *vpd = &vp->consts[i];
-- 
cgit v1.2.3


From 489c787b80064b590016eecf2b8157760b0bc8a2 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 14:29:50 -0700
Subject: nvfx: Fix SCons build.

Move declarations before code.
Fix void pointer arithmetic.
---
 src/gallium/drivers/nvfx/nv04_2d.c         | 44 +++++++++++++++++++---------
 src/gallium/drivers/nvfx/nvfx_buffer.c     |  2 +-
 src/gallium/drivers/nvfx/nvfx_fragprog.c   | 47 ++++++++++++++++++++----------
 src/gallium/drivers/nvfx/nvfx_miptree.c    |  5 ++--
 src/gallium/drivers/nvfx/nvfx_state_emit.c |  3 +-
 src/gallium/drivers/nvfx/nvfx_surface.c    | 35 +++++++++++++---------
 src/gallium/drivers/nvfx/nvfx_vbo.c        | 25 ++++++++++------
 7 files changed, 105 insertions(+), 56 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c
index b2f2ae79e1..46d5f5c08d 100644
--- a/src/gallium/drivers/nvfx/nv04_2d.c
+++ b/src/gallium/drivers/nvfx/nv04_2d.c
@@ -257,6 +257,9 @@ nv04_region_assert(struct nv04_region* rgn, unsigned w, unsigned h)
 static inline int
 nv04_region_is_contiguous(struct nv04_region* rgn, int w, int h)
 {
+	int surf_min;
+	int rect_min;
+
 	if(rgn->pitch)
 		return rgn->pitch == w << rgn->bpps;
 
@@ -275,8 +278,8 @@ nv04_region_is_contiguous(struct nv04_region* rgn, int w, int h)
 	if(rgn->d > 1)
 		return 0;
 
-	int surf_min = MIN2(rgn->w, rgn->h);
-	int rect_min = MIN2(w, h);
+	surf_min = MIN2(rgn->w, rgn->h);
+	rect_min = MIN2(w, h);
 
 	if((rect_min == surf_min) || (w == h) || (w == 2 * h))
 		return 1;
@@ -361,8 +364,10 @@ nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int
 {
 	if(rgn->pitch > 0)
 	{
+		int delta;
+
 		assert(!(rgn->offset & ((1 << rgn->bpps) - 1))); // fatal!
-		int delta = rgn->offset & ((1 << shift) - 1);
+		delta = rgn->offset & ((1 << shift) - 1);
 
 		if(h <= 1)
 		{
@@ -388,19 +393,22 @@ nv04_region_do_align_offset(struct nv04_region* rgn, unsigned w, unsigned h, int
 	}
 	else
 	{
+		int size;
+		int min;
+		int v;
+
 		// we don't care about the alignment of 3D surfaces since the 2D engine can't use them
 		if(rgn->d < 0)
 			return -1;
 
-		int size;
-		int min = MIN2(rgn->w, rgn->h);
+		min = MIN2(rgn->w, rgn->h);
 		size = min * min << rgn->bpps;
 
 		// this is unfixable, and should not be happening
 		if(rgn->offset & (size - 1))
 			return -1;
 
-		int v = (rgn->offset & ((1 << shift) - 1)) / size;
+		v = (rgn->offset & ((1 << shift) - 1)) / size;
 		rgn->offset -= v * size;
 
 		if(rgn->h == min)
@@ -457,6 +465,10 @@ nv04_region_align(struct nv04_region* rgn, unsigned w, unsigned h, int shift)
 void
 nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, int h)
 {
+	uint8_t* mdst;
+	uint8_t* msrc;
+	int size;
+
 	if(dst->bo != src->bo)
 	{
 		nouveau_bo_map(dst->bo, NOUVEAU_BO_WR);
@@ -465,10 +477,10 @@ nv04_region_copy_cpu(struct nv04_region* dst, struct nv04_region* src, int w, in
 	else
 		nouveau_bo_map(dst->bo, NOUVEAU_BO_WR | NOUVEAU_BO_RD);
 
-	uint8_t* mdst = dst->bo->map + dst->offset;
-	uint8_t* msrc = src->bo->map + src->offset;
+	mdst = (uint8_t*)dst->bo->map + dst->offset;
+	msrc = (uint8_t*)src->bo->map + src->offset;
 
-	int size = w << dst->bpps;
+	size = w << dst->bpps;
 
 	nv04_region_assert(dst, w, h);
 	nv04_region_assert(src, w, h);
@@ -548,6 +560,7 @@ simple:
 		int* dswy;
 		int* sswx;
 		int* sswy;
+		int dir;
 
 		if(!dst->pitch)
 		{
@@ -569,7 +582,7 @@ simple:
 				sswy[iy] = nv04_swizzle_bits(0, src->y + iy, src->z, src->w, src->h, src->d);
 		}
 
-		int dir = 1;
+		dir = 1;
 		/* do backwards copies for overlapping swizzled surfaces */
 		if(dst->pitch == src->pitch && dst->offset == src->offset)
 		{
@@ -611,7 +624,7 @@ simple:
 void
 nv04_region_fill_cpu(struct nv04_region* dst, int w, int h, unsigned value)
 {
-	uint8_t* mdst = (nouveau_bo_map(dst->bo, NOUVEAU_BO_WR), dst->bo->map + dst->offset);
+	uint8_t* mdst = (nouveau_bo_map(dst->bo, NOUVEAU_BO_WR), (uint8_t*)dst->bo->map + dst->offset);
 
 #ifdef NV04_REGION_DEBUG
 	fprintf(stderr, "\tRGN_FILL_CPU ");
@@ -727,11 +740,12 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx,
 	unsigned ex = (dst->x + w - 1) >> max_shift;
 	unsigned ey = (dst->y + h - 1) >> max_shift;
 	unsigned chunks = (ex - sx + 1) * (ey - sy + 1);
+	unsigned chunk_size;
 	if(dst->w < cw)
 		cw = dst->w;
 	if(dst->h < ch)
 		ch = dst->h;
-	unsigned chunk_size = cw * ch << dst->bpps;
+	chunk_size = cw * ch << dst->bpps;
 
 #ifdef NV04_REGION_DEBUG
 	fprintf(stderr, "\tRGN_COPY_SWIZZLE [%i, %i: %i] ", w, h, dst->bpps);
@@ -770,10 +784,12 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx,
 	  for (int cx = sx; cx <= ex; ++cx) {
 	    int rx = MAX2(0, (int)(dst->x - cw * cx));
 	    int rw = MIN2((int)cw, (int)(dst->x - cw * cx + w)) - rx;
+	    unsigned dst_offset;
+	    unsigned src_offset;
 
 	    BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
 
-	    unsigned dst_offset = dst->offset + (nv04_swizzle_bits_2d(cx * cw, cy * ch, dst->w, dst->h) << dst->bpps);
+	    dst_offset = dst->offset + (nv04_swizzle_bits_2d(cx * cw, cy * ch, dst->w, dst->h) << dst->bpps);
 	    assert(dst_offset <= dst->bo->size);
 	    assert(dst_offset + chunk_size <= dst->bo->size);
 	    OUT_RELOCl(chan, dst->bo, dst_offset,
@@ -795,7 +811,7 @@ nv04_region_copy_swizzle(struct nv04_2d_context *ctx,
 	    OUT_RING  (chan, src->pitch |
 			     NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
 			     NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
-	    unsigned src_offset = src->offset + (cy * ch + ry + src->y - dst->y) * src->pitch + ((cx * cw + rx + src->x - dst->x) << src->bpps);
+	    src_offset = src->offset + (cy * ch + ry + src->y - dst->y) * src->pitch + ((cx * cw + rx + src->x - dst->x) << src->bpps);
 	    assert(src_offset <= src->bo->size);
 	    assert(src_offset + (src->pitch * (rh - 1)) + (rw << src->bpps) <= src->bo->size);
 	    OUT_RELOCl(chan, src->bo, src_offset,
diff --git a/src/gallium/drivers/nvfx/nvfx_buffer.c b/src/gallium/drivers/nvfx/nvfx_buffer.c
index 89bb8570ef..041099e0e5 100644
--- a/src/gallium/drivers/nvfx/nvfx_buffer.c
+++ b/src/gallium/drivers/nvfx/nvfx_buffer.c
@@ -89,7 +89,7 @@ void nvfx_buffer_upload(struct nvfx_buffer* buffer)
 		// TODO: may want to use a temporary in some cases
 		nouveau_bo_map(buffer->base.bo, NOUVEAU_BO_WR
 				| (buffer->dirty_unsynchronized ? NOUVEAU_BO_NOSYNC : 0));
-		memcpy(buffer->base.bo->map + buffer->dirty_begin, buffer->data + buffer->dirty_begin, dirty);
+		memcpy((uint8_t*)buffer->base.bo->map + buffer->dirty_begin, buffer->data + buffer->dirty_begin, dirty);
 		nouveau_bo_unmap(buffer->base.bo);
 		buffer->dirty_begin = buffer->dirty_end = 0;
 	}
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index dc681f4d4d..6c8f5c4708 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -244,12 +244,13 @@ nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
 {
 	const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
 	struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none);
+	uint32_t *hw;
 	insn.cc_update = 1;
 	nvfx_fp_emit(fpc, insn);
 
 	fpc->inst_offset = fpc->fp->insn_len;
 	grow_insns(fpc, 4);
-	uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+	hw = &fpc->fp->insn[fpc->inst_offset];
 	/* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
 	hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
 		NV40_FP_OP_OUT_NONE |
@@ -270,9 +271,10 @@ static void
 nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
 {
         struct nvfx_label_relocation reloc;
+        uint32_t *hw;
         fpc->inst_offset = fpc->fp->insn_len;
         grow_insns(fpc, 4);
-        uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+        hw = &fpc->fp->insn[fpc->inst_offset];
         /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
         hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
         /* Use .xxxx swizzle so that we check only src[0].x*/
@@ -288,9 +290,10 @@ nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
 static void
 nv40_fp_ret(struct nvfx_fpc *fpc)
 {
+	uint32_t *hw;
 	fpc->inst_offset = fpc->fp->insn_len;
 	grow_insns(fpc, 4);
-	uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+	hw = &fpc->fp->insn[fpc->inst_offset];
 	/* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
 	hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
 	/* Use .xxxx swizzle so that we check only src[0].x*/
@@ -304,9 +307,10 @@ static void
 nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
 {
         struct nvfx_label_relocation reloc;
+        uint32_t *hw;
         fpc->inst_offset = fpc->fp->insn_len;
         grow_insns(fpc, 4);
-        uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+        hw = &fpc->fp->insn[fpc->inst_offset];
         /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
         hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
                         NV40_FP_OP_OUT_NONE |
@@ -330,9 +334,10 @@ static void
 nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
 {
         struct nvfx_label_relocation reloc;
+        uint32_t *hw;
         fpc->inst_offset = fpc->fp->insn_len;
         grow_insns(fpc, 4);
-        uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+        hw = &fpc->fp->insn[fpc->inst_offset];
         /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
         hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
                 NV40_FP_OP_OUT_NONE |
@@ -353,9 +358,10 @@ nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
 static void
 nv40_fp_brk(struct nvfx_fpc *fpc)
 {
+	uint32_t *hw;
 	fpc->inst_offset = fpc->fp->insn_len;
 	grow_insns(fpc, 4);
-	uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
+	hw = &fpc->fp->insn[fpc->inst_offset];
 	/* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
 	hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
 		NV40_FP_OP_OUT_NONE;
@@ -778,20 +784,22 @@ nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 
 	case TGSI_OPCODE_ELSE:
 	{
+		uint32_t *hw;
 		if(!nvfx->is_nv4x)
 			goto nv3x_cflow;
 		assert(util_dynarray_contains(&fpc->if_stack, unsigned));
-		uint32_t *hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
+		hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
 		hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
 		break;
 	}
 
 	case TGSI_OPCODE_ENDIF:
 	{
+		uint32_t *hw;
 		if(!nvfx->is_nv4x)
 			goto nv3x_cflow;
 		assert(util_dynarray_contains(&fpc->if_stack, unsigned));
-		uint32_t *hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
+		hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
 		if(!hw[2])
 			hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
 		hw[3] = fpc->fp->insn_len;
@@ -1097,6 +1105,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	struct nvfx_fragment_program *fp = nvfx->fragprog;
 	int update = 0;
+	struct nvfx_vertex_program* vp;
+	unsigned sprite_coord_enable;
 
 	if (!fp->translated)
 	{
@@ -1135,13 +1145,14 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG))
 		update = TRUE;
 
-	struct nvfx_vertex_program* vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
+	vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
 	if (fp->last_vp_id != vp->id) {
 		char* vp_sem_table = vp->generic_to_fp_input;
 		unsigned char* fp_semantics = fp->slot_to_generic;
 		unsigned diff = 0;
+		unsigned char* cur_slots;
 		fp->last_vp_id = nvfx->vertprog->id;
-		unsigned char* cur_slots = fp->slot_to_fp_input;
+		cur_slots = fp->slot_to_fp_input;
 		for(unsigned i = 0; i < fp->num_slots; ++i) {
 			unsigned char slot_mask = vp_sem_table[fp_semantics[i]];
 			diff |= (slot_mask >> 4) & (slot_mask ^ cur_slots[i]);
@@ -1161,7 +1172,7 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	}
 
 	// last_sprite_coord_enable
-	unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
+	sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
 	if(fp->last_sprite_coord_enable != sprite_coord_enable)
 	{
 		unsigned texcoord_mask = vp->texcoord_ouput_mask;
@@ -1199,6 +1210,9 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	}
 
 	if(update) {
+		int offset;
+		uint32_t* fpmap;
+
 		++fp->bo_prog_idx;
 		if(fp->bo_prog_idx >= fp->progs_per_bo)
 		{
@@ -1209,6 +1223,9 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			else
 			{
 				struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
+				uint8_t* map;
+				uint8_t* buf;
+
 				fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
 				memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
 				if(fp->fpbo)
@@ -1225,8 +1242,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 				nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
 				nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
 
-				uint8_t* map = fpbo->bo->map;
-				uint8_t* buf = (uint8_t*)fpbo->insn;
+				map = fpbo->bo->map;
+				buf = (uint8_t*)fpbo->insn;
 				for(unsigned i = 0; i < fp->progs_per_bo; ++i)
 				{
 					memcpy(buf, fp->insn, fp->insn_len * 4);
@@ -1238,8 +1255,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			fp->bo_prog_idx = 0;
 		}
 
-		int offset = fp->bo_prog_idx * fp->prog_size;
-		uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
+		offset = fp->bo_prog_idx * fp->prog_size;
+		fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
 
 		if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
 			struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 559e832109..0532b43ef0 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -155,9 +155,10 @@ struct pipe_resource *
 nvfx_miptree_create(struct pipe_screen *pscreen, const struct pipe_resource *pt)
 {
 	struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, pt);
+        unsigned size;
 	nvfx_miptree_choose_format(mt);
 
-        unsigned size = nvfx_miptree_layout(mt);
+        size = nvfx_miptree_layout(mt);
 
 	mt->base.bo = nouveau_screen_bo_new(pscreen, 256, pt->usage, pt->bind, size);
 
@@ -173,6 +174,7 @@ struct pipe_resource *
 nvfx_miptree_from_handle(struct pipe_screen *pscreen, const struct pipe_resource *template, struct winsys_handle *whandle)
 {
         struct nvfx_miptree* mt = nvfx_miptree_create_skeleton(pscreen, template);
+        unsigned stride;
         if(whandle->stride) {
 		mt->linear_pitch = whandle->stride;
 		mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
@@ -181,7 +183,6 @@ nvfx_miptree_from_handle(struct pipe_screen *pscreen, const struct pipe_resource
 
         nvfx_miptree_layout(mt);
 
-        unsigned stride;
         mt->base.bo = nouveau_screen_bo_from_handle(pscreen, whandle, &stride);
         if (mt->base.bo == NULL) {
                 FREE(mt);
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index 19512194be..8e3c342179 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -11,6 +11,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	unsigned still_dirty = 0;
 	int all_swizzled = -1;
 	boolean flush_tex_cache = FALSE;
+	unsigned render_temps;
 
 	if(nvfx != nvfx->screen->cur_ctx)
 	{
@@ -141,7 +142,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 
 	nvfx->dirty = dirty & still_dirty;
 
-	unsigned render_temps = nvfx->state.render_temps;
+	render_temps = nvfx->state.render_temps;
 	if(render_temps)
 	{
 		for(int i = 0; i < nvfx->framebuffer.nr_cbufs; ++i)
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
index 135978ad27..806f1a22e6 100644
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ b/src/gallium/drivers/nvfx/nvfx_surface.c
@@ -60,14 +60,17 @@ nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format)
 		rgn->bpps = 2;
 		break;
 	default:
-		assert(util_is_pot(bits));
-		int shift = util_logbase2(bits) - 3;
-		assert(shift >= 2);
-		rgn->bpps = 2;
-		shift -= 2;
-
-		rgn->x = util_format_get_nblocksx(format, rgn->x) << shift;
-		rgn->y = util_format_get_nblocksy(format, rgn->y);
+		{
+			int shift;
+			assert(util_is_pot(bits));
+			shift = util_logbase2(bits) - 3;
+			assert(shift >= 2);
+			rgn->bpps = 2;
+			shift -= 2;
+
+			rgn->x = util_format_get_nblocksx(format, rgn->x) << shift;
+			rgn->y = util_format_get_nblocksy(format, rgn->y);
+		}
 	}
 }
 
@@ -241,26 +244,29 @@ nvfx_resource_copy_region(struct pipe_context *pipe,
 		  unsigned srcx, unsigned srcy, unsigned srcz,
 		  unsigned w, unsigned h)
 {
+	static int copy_threshold = -1;
 	struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
 	struct nv04_region dst, src;
+	int dst_to_gpu;
+	int src_on_gpu;
+	boolean small;
+	int ret;
 
 	if(!w || !h)
 		return;
 
-	static int copy_threshold = -1;
 	if(copy_threshold < 0)
 		copy_threshold = debug_get_num_option("NOUVEAU_COPY_THRESHOLD", 4);
 
-	int dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING;
-	int src_on_gpu = nvfx_resource_on_gpu(srcr);
+	dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING;
+	src_on_gpu = nvfx_resource_on_gpu(srcr);
 
 	nvfx_region_init_for_subresource(&dst, dstr, subdst, dstx, dsty, dstz, TRUE);
 	nvfx_region_init_for_subresource(&src, srcr, subsrc, srcx, srcy, srcz, FALSE);
 	w = util_format_get_stride(dstr->format, w) >> dst.bpps;
 	h = util_format_get_nblocksy(dstr->format, h);
 
-	int ret;
-	boolean small = (w * h <= copy_threshold);
+	small = (w * h <= copy_threshold);
 	if((!dst_to_gpu || !src_on_gpu) && small)
 		ret = -1; /* use the CPU */
 	else
@@ -309,6 +315,7 @@ nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts,
 {
 	struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
 	struct nv04_region dst;
+	int ret;
 	/* Always try to use the GPU right now, if possible
 	 * If the user wanted the surface data on the CPU, he would have cleared with memset (hopefully) */
 
@@ -318,7 +325,7 @@ nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts,
 	w = util_format_get_stride(dsts->format, w) >> dst.bpps;
 	h = util_format_get_nblocksy(dsts->format, h);
 
-	int ret = nv04_region_fill_2d(ctx, &dst, w, h, value);
+	ret = nv04_region_fill_2d(ctx, &dst, w, h, value);
 	if(ret > 0 && dsts->texture->bind & PIPE_BIND_RENDER_TARGET)
 		return 1;
 	else if(ret)
diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index d1e7199287..5d3fb6fb6c 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -58,6 +58,10 @@ static unsigned nvfx_decide_upload_mode(struct pipe_context *pipe, const struct
 	unsigned inline_cost = 0;
 	unsigned unique_vertices;
 	unsigned upload_mode;
+	float best_index_cost_for_hardware_vertices_as_inline_cost;
+	boolean prefer_hardware_indices;
+	unsigned index_inline_cost;
+	unsigned index_hardware_cost;
 	if (info->indexed)
 		unique_vertices = util_guess_unique_indices_count(info->mode, info->count);
 	else
@@ -108,10 +112,10 @@ static unsigned nvfx_decide_upload_mode(struct pipe_context *pipe, const struct
 		inline_cost += vbi->per_vertex_size * info->count;
 	}
 
-	float best_index_cost_for_hardware_vertices_as_inline_cost = 0.0f;
-	boolean prefer_hardware_indices = FALSE;
-	unsigned index_inline_cost = 0;
-	unsigned index_hardware_cost = 0;
+	best_index_cost_for_hardware_vertices_as_inline_cost = 0.0f;
+	prefer_hardware_indices = FALSE;
+	index_inline_cost = 0;
+	index_hardware_cost = 0;
 
 	if (info->indexed)
 	{
@@ -336,12 +340,15 @@ nvfx_vbo_validate(struct nvfx_context *nvfx)
 void
 nvfx_vbo_relocate(struct nvfx_context *nvfx)
 {
+	struct nouveau_channel* chan;
+	unsigned vb_flags;
+	int i;
+
         if(!nvfx->use_vertex_buffers)
                 return;
 
-	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	unsigned vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
-	int i;
+	chan = nvfx->screen->base.channel;
+	vb_flags = nvfx->screen->vertex_buffer_reloc_flags | NOUVEAU_BO_RD | NOUVEAU_BO_DUMMY;
 
 	MARK_RING(chan, 2 * 16 + 3, 2 * 16 + 3);
         for (i = 0; i < nvfx->vtxelt->num_per_vertex; i++) {
@@ -422,10 +429,10 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe,
 	struct nvfx_vtxelt_state *cso = CALLOC_STRUCT(nvfx_vtxelt_state);
         struct translate_key transkey;
         unsigned per_vertex_size[16];
-        memset(per_vertex_size, 0, sizeof(per_vertex_size));
-
         unsigned vb_compacted_index[16];
 
+        memset(per_vertex_size, 0, sizeof(per_vertex_size));
+
 	assert(num_elements < 16); /* not doing fallbacks yet */
 
 	memcpy(cso->pipe, elements, num_elements * sizeof(elements[0]));
-- 
cgit v1.2.3


From 251e48c64a37c4b05f26c96c5a1799c24da6474b Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 23:33:51 +0200
Subject: nvfx: fix incorrect assert

---
 src/gallium/drivers/nvfx/nvfx_vbo.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index 5d3fb6fb6c..b1a06654b6 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -427,14 +427,17 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe,
 			  const struct pipe_vertex_element *elements)
 {
 	struct nvfx_vtxelt_state *cso = CALLOC_STRUCT(nvfx_vtxelt_state);
-        struct translate_key transkey;
-        unsigned per_vertex_size[16];
-        unsigned vb_compacted_index[16];
+	struct translate_key transkey;
+	unsigned per_vertex_size[16];
+	unsigned vb_compacted_index[16];
 
-        memset(per_vertex_size, 0, sizeof(per_vertex_size));
-
-	assert(num_elements < 16); /* not doing fallbacks yet */
+	if(num_elements > 16)
+	{
+		_debug_printf("Error: application attempted to use %u vertex elements, but only 16 are supported: ignoring the rest\n");
+		num_elements = 16;
+	}
 
+	memset(per_vertex_size, 0, sizeof(per_vertex_size));
 	memcpy(cso->pipe, elements, num_elements * sizeof(elements[0]));
 	cso->num_elements = num_elements;
 	cso->needs_translate = FALSE;
-- 
cgit v1.2.3


From 4edeeaf71564582d5afebc9cb59f4b3f7fb40a7e Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sat, 21 Aug 2010 23:53:39 +0200
Subject: nvfx: actually fix it properly

---
 src/gallium/drivers/nvfx/nvfx_vbo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index b1a06654b6..21d6e0e6f8 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -433,7 +433,7 @@ nvfx_vtxelts_state_create(struct pipe_context *pipe,
 
 	if(num_elements > 16)
 	{
-		_debug_printf("Error: application attempted to use %u vertex elements, but only 16 are supported: ignoring the rest\n");
+		_debug_printf("Error: application attempted to use %u vertex elements, but only 16 are supported: ignoring the rest\n", num_elements);
 		num_elements = 16;
 	}
 
-- 
cgit v1.2.3


From 36efb86c0570d86d8dfce87fd2416125e0e91b40 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Sat, 21 Aug 2010 22:49:22 -0400
Subject: r600g: partialy fix texturing from depth buffer + initial support for
 untiling

Partialy fix texturing from depth buffer, depth buffer is tiled
following different tile organisation that color buffer. This
properly set the tile type & array mode field of texture sampler
when sampling from db resource.

Add initial support to untiling buffer when transfering them,
it's kind of broken by corruption the vertex buffer of previous
draw.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c     |  27 ++++-
 src/gallium/drivers/r600/r600_context.c  |   8 +-
 src/gallium/drivers/r600/r600_resource.h |   3 +
 src/gallium/drivers/r600/r600_screen.h   |   1 +
 src/gallium/drivers/r600/r600_shader.c   |   6 +-
 src/gallium/drivers/r600/r600_state.c    |   7 +-
 src/gallium/drivers/r600/r600_texture.c  | 179 +++++++++++++++++++++----------
 7 files changed, 165 insertions(+), 66 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index aef4fbd9af..dc57b333a0 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -120,7 +120,8 @@ static void r600_clear_depth_stencil(struct pipe_context *ctx,
 	r600_queries_resume(ctx);
 }
 
-static void r600_resource_copy_region(struct pipe_context *pipe,
+
+static void r600_resource_copy_region(struct pipe_context *ctx,
 				      struct pipe_resource *dst,
 				      struct pipe_subresource subdst,
 				      unsigned dstx, unsigned dsty, unsigned dstz,
@@ -129,8 +130,28 @@ static void r600_resource_copy_region(struct pipe_context *pipe,
 				      unsigned srcx, unsigned srcy, unsigned srcz,
 				      unsigned width, unsigned height)
 {
-	util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
-				  src, subsrc, srcx, srcy, srcz, width, height);
+	struct r600_context *rctx = r600_context(ctx);
+	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
+	struct pipe_sampler_state *samplers[PIPE_MAX_ATTRIBS];
+	struct pipe_sampler_view_state *sampler_views[PIPE_MAX_ATTRIBS];
+	unsigned i;
+
+	for (i = 0; i < rctx->ps_nsampler_view; i++) {
+		sampler_views[i] = &rctx->ps_sampler_view[i]->state.sampler_view;
+	}
+	for (i = 0; i < rctx->ps_nsampler; i++) {
+		samplers[i] = &rctx->ps_sampler[i]->state.sampler;
+	}
+	r600_blitter_save_states(ctx);
+	util_blitter_save_framebuffer(rctx->blitter, fb);
+	util_blitter_save_fragment_sampler_states(rctx->blitter, rctx->ps_nsampler, samplers);
+	util_blitter_save_fragment_sampler_views(rctx->blitter, rctx->ps_nsampler_view, sampler_views);
+
+	util_blitter_copy_region(rctx->blitter, dst, subdst, dstx, dsty, dstz,
+			src, subsrc, srcx, srcy, srcz, width, height,
+			TRUE);
+	/* resume queries */
+	r600_queries_resume(ctx);
 }
 
 void r600_init_blit_functions(struct r600_context *rctx)
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 2f59a550f5..9af28356c5 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -52,7 +52,7 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	char dname[256];
 
 	/* suspend queries */
-	r600_queries_suspend(rctx);
+	r600_queries_suspend(ctx);
 	if (radeon_ctx_pm4(rctx->ctx))
 		goto out;
 	/* FIXME dumping should be removed once shader support instructions
@@ -61,8 +61,10 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	if (!rctx->ctx->cpm4)
 		goto out;
 	sprintf(dname, "gallium-%08d.bof", dc);
-	if (dc < 10)
+	if (dc < 2) {
 		radeon_ctx_dump_bof(rctx->ctx, dname);
+		R600_ERR("dumped %s\n", dname);
+	}
 #if 1
 	radeon_ctx_submit(rctx->ctx);
 #endif
@@ -74,7 +76,7 @@ out:
 	rctx->ctx = radeon_ctx_decref(rctx->ctx);
 	rctx->ctx = radeon_ctx(rscreen->rw);
 	/* resume queries */
-	r600_queries_resume(rctx);
+	r600_queries_resume(ctx);
 }
 
 static void r600_init_config(struct r600_context *rctx)
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index bb90e76fb7..5ebda027e9 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -48,6 +48,9 @@ struct r600_resource_texture {
 	unsigned long			pitch_override;
 	unsigned long			bpt;
 	unsigned long			size;
+	unsigned			tilled;
+	unsigned			array_mode;
+	unsigned			tile_type;
 };
 
 void r600_init_context_resource_functions(struct r600_context *r600);
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 53b560c617..147be3c4ac 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -38,6 +38,7 @@ struct r600_transfer {
 	/* Buffer transfer. */
 	struct pipe_transfer		*buffer_transfer;
 	unsigned			offset;
+	struct pipe_resource		*linear_texture;
 };
 
 struct r600_screen {
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index da1af6702c..79fc04a9fe 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -105,8 +105,8 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	int r;
 
-fprintf(stderr, "--------------------------------------------------------------\n");
-tgsi_dump(tokens, 0);
+//fprintf(stderr, "--------------------------------------------------------------\n");
+//tgsi_dump(tokens, 0);
 	if (rpshader == NULL)
 		return -ENOMEM;
 	rpshader->shader.family = radeon_get_family(rscreen->rw);
@@ -120,7 +120,7 @@ tgsi_dump(tokens, 0);
 		R600_ERR("building bytecode failed !\n");
 		return r;
 	}
-fprintf(stderr, "______________________________________________________________\n");
+//fprintf(stderr, "______________________________________________________________\n");
 	return 0;
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 93fc68e42e..e9b03f571a 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -773,6 +773,9 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 		return NULL;
 
 	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rtex->tilled = 1;
+	rtex->array_mode = 2;
+	rtex->tile_type = 1;
 	rbuffer = &rtex->resource;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->nbo = 1;
@@ -1258,7 +1261,9 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	/* FIXME properly handle first level != 0 */
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
-	                S_038000_PITCH((pitch / 8) - 1) |
+			S_038000_TILE_MODE(tmp->array_mode) |
+			S_038000_TILE_TYPE(tmp->tile_type) |
+			S_038000_PITCH((pitch / 8) - 1) |
 			S_038000_TEX_WIDTH(view->texture->width0 - 1);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
 			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 8a6b5f8764..92b4f430c5 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -37,6 +37,21 @@
 
 extern struct u_resource_vtbl r600_texture_vtbl;
 
+/* Copy from a tiled texture to a detiled one. */
+static void r600_copy_from_tiled_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+{
+	struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
+	struct pipe_resource *texture = transfer->resource;
+	struct pipe_subresource subdst;
+
+	subdst.face = 0;
+	subdst.level = 0;
+	ctx->resource_copy_region(ctx, rtransfer->linear_texture,
+				subdst, 0, 0, 0, texture, transfer->sr,
+				transfer->box.x, transfer->box.y, transfer->box.z,
+				transfer->box.width, transfer->box.height);
+}
+
 static unsigned long r600_texture_get_offset(struct r600_resource_texture *rtex,
 					unsigned level, unsigned zslice,
 					unsigned face)
@@ -106,7 +121,6 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 		FREE(rtex);
 		return NULL;
 	}
-
 	return &resource->base.b;
 }
 
@@ -208,6 +222,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 						const struct pipe_box *box)
 {
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+	struct pipe_resource resource;
 	struct r600_transfer *trans;
 
 	trans = CALLOC_STRUCT(r600_transfer);
@@ -219,14 +234,56 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	trans->transfer.box = *box;
 	trans->transfer.stride = rtex->pitch[sr.level];
 	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
+	if (rtex->tilled) {
+		resource.target = PIPE_TEXTURE_2D;
+		resource.format = texture->format;
+		resource.width0 = box->width;
+		resource.height0 = box->height;
+		resource.depth0 = 0;
+		resource.last_level = 0;
+		resource.nr_samples = 0;
+		resource.usage = PIPE_USAGE_DYNAMIC;
+		resource.bind = 0;
+		resource.flags = 0;
+		/* For texture reading, the temporary (detiled) texture is used as
+		 * a render target when blitting from a tiled texture. */
+		if (usage & PIPE_TRANSFER_READ) {
+			resource.bind |= PIPE_BIND_RENDER_TARGET;
+		}
+		/* For texture writing, the temporary texture is used as a sampler
+		 * when blitting into a tiled texture. */
+		if (usage & PIPE_TRANSFER_WRITE) {
+			resource.bind |= PIPE_BIND_SAMPLER_VIEW;
+		}
+		/* Create the temporary texture. */
+		trans->linear_texture = ctx->screen->resource_create(ctx->screen, &resource);
+		if (trans->linear_texture == NULL) {
+			R600_ERR("failed to create temporary texture to hold untiled copy\n");
+			pipe_resource_reference(&trans->transfer.resource, NULL);
+			FREE(trans);
+			return NULL;
+		}
+		if (usage & PIPE_TRANSFER_READ) {
+			/* We cannot map a tiled texture directly because the data is
+			 * in a different order, therefore we do detiling using a blit. */
+			r600_copy_from_tiled_texture(ctx, trans);
+			/* Always referenced in the blit. */
+			ctx->flush(ctx, 0, NULL);
+		}
+	}
 	return &trans->transfer;
 }
 
 void r600_texture_transfer_destroy(struct pipe_context *ctx,
-				   struct pipe_transfer *trans)
+				   struct pipe_transfer *transfer)
 {
-	pipe_resource_reference(&trans->resource, NULL);
-	FREE(trans);
+	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+
+	if (rtransfer->linear_texture) {
+		pipe_resource_reference(&rtransfer->linear_texture, NULL);
+	}
+	pipe_resource_reference(&transfer->resource, NULL);
+	FREE(transfer);
 }
 
 void* r600_texture_transfer_map(struct pipe_context *ctx,
@@ -239,14 +296,20 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 	char *map;
 
 	r600_flush(ctx, 0, NULL);
-
-	resource = (struct r600_resource *)transfer->resource;
+	if (rtransfer->linear_texture) {
+		resource = (struct r600_resource *)rtransfer->linear_texture;
+	} else {
+		resource = (struct r600_resource *)transfer->resource;
+	}
 	if (radeon_bo_map(rscreen->rw, resource->bo)) {
 		return NULL;
 	}
 	radeon_bo_wait(rscreen->rw, resource->bo);
 
 	map = resource->bo->data;
+	if (rtransfer->linear_texture) {
+		return map;
+	}
 
 	return map + rtransfer->offset +
 		transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
@@ -256,10 +319,15 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 				 struct pipe_transfer* transfer)
 {
+	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_resource *resource;
 
-	resource = (struct r600_resource *)transfer->resource;
+	if (rtransfer->linear_texture) {
+		resource = (struct r600_resource *)rtransfer->linear_texture;
+	} else {
+		resource = (struct r600_resource *)transfer->resource;
+	}
 	radeon_bo_unmap(rscreen->rw, resource->bo);
 }
 
@@ -283,51 +351,51 @@ void r600_init_screen_texture_functions(struct pipe_screen *screen)
 }
 
 static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
-					  const unsigned char *swizzle_view)
+		const unsigned char *swizzle_view)
 {
-    unsigned i;
-    unsigned char swizzle[4];
-    unsigned result = 0;
-    const uint32_t swizzle_shift[4] = {
-	    16, 19, 22, 25,
-    };
-    const uint32_t swizzle_bit[4] = {
-	    0, 1, 2, 3,
-    };
-
-    if (swizzle_view) {
-        /* Combine two sets of swizzles. */
-        for (i = 0; i < 4; i++) {
-            swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
-                         swizzle_format[swizzle_view[i]] : swizzle_view[i];
-        }
-    } else {
-        memcpy(swizzle, swizzle_format, 4);
-    }
-
-    /* Get swizzle. */
-    for (i = 0; i < 4; i++) {
-        switch (swizzle[i]) {
-            case UTIL_FORMAT_SWIZZLE_Y:
-                result |= swizzle_bit[1] << swizzle_shift[i];
-                break;
-            case UTIL_FORMAT_SWIZZLE_Z:
-                result |= swizzle_bit[2] << swizzle_shift[i];
-                break;
-            case UTIL_FORMAT_SWIZZLE_W:
-                result |= swizzle_bit[3] << swizzle_shift[i];
-                break;
-            case UTIL_FORMAT_SWIZZLE_0:
-                result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
-                break;
-            case UTIL_FORMAT_SWIZZLE_1:
-                result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
-                break;
-            default: /* UTIL_FORMAT_SWIZZLE_X */
-                result |= swizzle_bit[0] << swizzle_shift[i];
-        }
-    }
-    return result;
+	unsigned i;
+	unsigned char swizzle[4];
+	unsigned result = 0;
+	const uint32_t swizzle_shift[4] = {
+		16, 19, 22, 25,
+	};
+	const uint32_t swizzle_bit[4] = {
+		0, 1, 2, 3,
+	};
+
+	if (swizzle_view) {
+		/* Combine two sets of swizzles. */
+		for (i = 0; i < 4; i++) {
+			swizzle[i] = swizzle_view[i] <= UTIL_FORMAT_SWIZZLE_W ?
+				swizzle_format[swizzle_view[i]] : swizzle_view[i];
+		}
+	} else {
+		memcpy(swizzle, swizzle_format, 4);
+	}
+
+	/* Get swizzle. */
+	for (i = 0; i < 4; i++) {
+		switch (swizzle[i]) {
+		case UTIL_FORMAT_SWIZZLE_Y:
+			result |= swizzle_bit[1] << swizzle_shift[i];
+			break;
+		case UTIL_FORMAT_SWIZZLE_Z:
+			result |= swizzle_bit[2] << swizzle_shift[i];
+			break;
+		case UTIL_FORMAT_SWIZZLE_W:
+			result |= swizzle_bit[3] << swizzle_shift[i];
+			break;
+		case UTIL_FORMAT_SWIZZLE_0:
+			result |= V_038010_SQ_SEL_0 << swizzle_shift[i];
+			break;
+		case UTIL_FORMAT_SWIZZLE_1:
+			result |= V_038010_SQ_SEL_1 << swizzle_shift[i];
+			break;
+		default: /* UTIL_FORMAT_SWIZZLE_X */
+			result |= swizzle_bit[0] << swizzle_shift[i];
+		}
+	}
+	return result;
 }
 
 /* texture format translate */
@@ -353,13 +421,13 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 	case UTIL_FORMAT_COLORSPACE_ZS:
 		switch (format) {
 		case PIPE_FORMAT_Z16_UNORM:
-			result = V_028010_DEPTH_16;
+			result = V_0280A0_COLOR_16;
 			goto out_word4;
 		case PIPE_FORMAT_Z24X8_UNORM:
-			result = V_028010_DEPTH_X8_24;
+			result = V_0280A0_COLOR_8_24;
 			goto out_word4;
 		case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-			result = V_028010_DEPTH_8_24;
+			result = V_0280A0_COLOR_8_24;
 			goto out_word4;
 		default:
 			goto out_unknown;
@@ -522,9 +590,8 @@ out_word4:
 		*word4_p = word4;
 	if (yuv_format_p)
 		*yuv_format_p = yuv_format;
-//	fprintf(stderr,"returning %08x %08x %08x\n", result, word4, yuv_format);
 	return result;
 out_unknown:
-//	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
+	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
 	return ~0;
 }
-- 
cgit v1.2.3


From 973c065abef2ab4066cd3c1cf12652c1da289210 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 21:27:43 -0700
Subject: i965g: Fix printf format warning on 32-bit platforms.

Fixes the following GCC warning on 32-bit platforms.
warning: format '%li' expects type 'long int', but argument 4 has type 'int'
---
 src/gallium/drivers/i965/brw_batchbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/i965/brw_batchbuffer.c b/src/gallium/drivers/i965/brw_batchbuffer.c
index 8b3f46f2c1..e80067f3b1 100644
--- a/src/gallium/drivers/i965/brw_batchbuffer.c
+++ b/src/gallium/drivers/i965/brw_batchbuffer.c
@@ -162,7 +162,7 @@ brw_batchbuffer_emit_reloc(struct brw_batchbuffer *batch,
 
    if (batch->ptr - batch->map > batch->buf->size) {
       debug_printf("bad relocation ptr %p map %p offset %li size %i\n",
-		   batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
+		   batch->ptr, batch->map, (long) (batch->ptr - batch->map), batch->buf->size);
 
       return PIPE_ERROR_OUT_OF_MEMORY;
    }
-- 
cgit v1.2.3


From 2506b32eecbaacf5609f0c4654a9f90c72ce0c81 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 21:42:17 -0700
Subject: nv50: Disable unused code.

Disable release_hw and emit_mov_from_pred functions as they are
currently not being used.
---
 src/gallium/drivers/nv50/nv50_program.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nv50/nv50_program.c b/src/gallium/drivers/nv50/nv50_program.c
index 8cb1639013..cec2290481 100644
--- a/src/gallium/drivers/nv50/nv50_program.c
+++ b/src/gallium/drivers/nv50/nv50_program.c
@@ -306,6 +306,7 @@ alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst)
 	return NULL;
 }
 
+#if 0
 /* release the hardware resource held by r */
 static void
 release_hw(struct nv50_pc *pc, struct nv50_reg *r)
@@ -321,6 +322,7 @@ release_hw(struct nv50_pc *pc, struct nv50_reg *r)
 	if (r->index == -1)
 		FREE(r);
 }
+#endif
 
 static void
 free_temp(struct nv50_pc *pc, struct nv50_reg *r)
@@ -885,6 +887,7 @@ set_half_src(struct nv50_pc *pc, struct nv50_reg *src, int lh,
 	e->inst[pos / 32] |= ((src->hw * 2) + lh) << (pos % 32);
 }
 
+#if 0
 static void
 emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
 {
@@ -897,6 +900,7 @@ emit_mov_from_pred(struct nv50_pc *pc, struct nv50_reg *dst, int pred)
 
 	emit(pc, e);
 }
+#endif
 
 static void
 emit_mov_to_pred(struct nv50_pc *pc, int pred, struct nv50_reg *src)
-- 
cgit v1.2.3


From 4a06525737c17126243a48741c87298ad1ffd076 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 22:01:04 -0700
Subject: nv50: Silence incompatible pointer type initialization warning.

Silence the following GCC warning.
warning: initialization from incompatible pointer type
---
 src/gallium/drivers/nv50/nv50_push.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nv50/nv50_push.c b/src/gallium/drivers/nv50/nv50_push.c
index 6a2ffd5a3c..57c0010bf4 100644
--- a/src/gallium/drivers/nv50/nv50_push.c
+++ b/src/gallium/drivers/nv50/nv50_push.c
@@ -108,8 +108,9 @@ emit_vertex(struct push_context *ctx, unsigned n)
    int i;
 
    if (ctx->edgeflag_attr < 16) {
-      float *edgeflag = (uint8_t *)ctx->attr[ctx->edgeflag_attr].map +
-                        ctx->attr[ctx->edgeflag_attr].stride * n;
+      float *edgeflag = (float *)
+         ((uint8_t *)ctx->attr[ctx->edgeflag_attr].map +
+          ctx->attr[ctx->edgeflag_attr].stride * n);
 
       if (*edgeflag != ctx->edgeflag) {
          BEGIN_RING(chan, tesla, NV50TCL_EDGEFLAG_ENABLE, 1);
-- 
cgit v1.2.3


From 68d34f2979f4f4e0dfa5695742bb8ccdb6feb54a Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 22:09:47 -0700
Subject: nvfx: Silence uninitialized variable warnings.

Silence the following i686-apple-darwin10-gcc-4.2.1 warnings.
nv04_2d.c: In function 'nv04_region_copy_cpu':
nv04_2d.c:560: warning: 'dswy' may be used uninitialized in this function
nv04_2d.c:559: warning: 'dswx' may be used uninitialized in this function
nv04_2d.c:562: warning: 'sswy' may be used uninitialized in this function
nv04_2d.c:561: warning: 'sswx' may be used uninitialized in this function
---
 src/gallium/drivers/nvfx/nv04_2d.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c
index 46d5f5c08d..c7d53a786f 100644
--- a/src/gallium/drivers/nvfx/nv04_2d.c
+++ b/src/gallium/drivers/nvfx/nv04_2d.c
@@ -556,10 +556,10 @@ simple:
 	}
 	else
 	{
-		int* dswx;
-		int* dswy;
-		int* sswx;
-		int* sswy;
+		int* dswx = NULL;
+		int* dswy = NULL;
+		int* sswx = NULL;
+		int* sswy = NULL;
 		int dir;
 
 		if(!dst->pitch)
-- 
cgit v1.2.3


From fdedff2dba64ce25e8a572c1001f2b9e8eed00d2 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 22:45:09 -0700
Subject: i965g: Silence printf format warnings on 64-bit builds.

---
 src/gallium/drivers/i965/brw_wm_debug.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/i965/brw_wm_debug.c b/src/gallium/drivers/i965/brw_wm_debug.c
index e2767264e7..1b2aa93bef 100644
--- a/src/gallium/drivers/i965/brw_wm_debug.c
+++ b/src/gallium/drivers/i965/brw_wm_debug.c
@@ -101,16 +101,16 @@ void brw_wm_print_value( struct brw_wm_compile *c,
       debug_printf("undef");
    else if( value - c->vreg >= 0 &&
 	    value - c->vreg < BRW_WM_MAX_VREG)
-      debug_printf("r%d", value - c->vreg);
+      debug_printf("r%ld", (long) (value - c->vreg));
    else if (value - c->creg >= 0 &&
 	    value - c->creg < BRW_WM_MAX_PARAM)
-      debug_printf("c%d", value - c->creg);
+      debug_printf("c%ld", (long) (value - c->creg));
    else if (value - c->payload.input_interp >= 0 &&
 	    value - c->payload.input_interp < PIPE_MAX_SHADER_INPUTS)
-      debug_printf("i%d", value - c->payload.input_interp);
+      debug_printf("i%ld", (long) (value - c->payload.input_interp));
    else if (value - c->payload.depth >= 0 &&
 	    value - c->payload.depth < PIPE_MAX_SHADER_INPUTS)
-      debug_printf("d%d", value - c->payload.depth);
+      debug_printf("d%ld", (long) (value - c->payload.depth));
    else 
       debug_printf("?");
 }
-- 
cgit v1.2.3


From 172953ef3a481612aa3bc9894941c2f9d34f509e Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 21 Aug 2010 22:59:46 -0700
Subject: nvfx: Silence uninitialized variable warnings.

Variables weren't initialized on the error paths.
---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 2 ++
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 4 ++++
 2 files changed, 6 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 6c8f5c4708..db33ecd78c 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -418,6 +418,8 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
 		break;
 	default:
 		NOUVEAU_ERR("bad src file\n");
+		src.reg.index = 0;
+		src.reg.type = 0;
 		break;
 	}
 
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index b5dde2592e..38f37168a1 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -379,6 +379,8 @@ tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
 		break;
 	default:
 		NOUVEAU_ERR("bad src file\n");
+		src.reg.index = 0;
+		src.reg.type = 0;
 		break;
 	}
 
@@ -410,6 +412,8 @@ tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
 		break;
 	default:
 		NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
+		dst.index = 0;
+		dst.type = 0;
 		break;
 	}
 
-- 
cgit v1.2.3


From 928830606f267aa828ede92cf0a643eb5901c3e2 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sun, 22 Aug 2010 00:16:54 -0700
Subject: nvfx: Silence unused variable warning.

The variable is used but only in the body of an assert.
---
 src/gallium/drivers/nvfx/nv04_2d.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c
index c7d53a786f..3761002bcb 100644
--- a/src/gallium/drivers/nvfx/nv04_2d.c
+++ b/src/gallium/drivers/nvfx/nv04_2d.c
@@ -247,6 +247,7 @@ nv04_region_assert(struct nv04_region* rgn, unsigned w, unsigned h)
 
 	assert(rgn->offset <= (int)rgn->bo->size);
 	assert(end <= rgn->bo->size);
+	(void) end;
 	if(!rgn->pitch) {
 		assert(util_is_pot(rgn->w));
 		assert(util_is_pot(rgn->h));
-- 
cgit v1.2.3


From 04094b2da2030a82ff49e647fc8658502f02cea8 Mon Sep 17 00:00:00 2001
From: José Fonseca <jfonseca@vmware.com>
Date: Sun, 15 Aug 2010 13:36:02 +0100
Subject: svga: Do not shortcut NULL surface relocations with
 SVGA3D_INVALID_ID.

How to cope with NULL surface relocations should be entirely at winsys'
discretion.
---
 src/gallium/drivers/svga/svga_cmd.c       |  2 +-
 src/gallium/drivers/svga/svga_state_tss.c | 13 ++++++++-----
 2 files changed, 9 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/svga/svga_cmd.c b/src/gallium/drivers/svga/svga_cmd.c
index 7b2dfe2549..e975f3b02f 100644
--- a/src/gallium/drivers/svga/svga_cmd.c
+++ b/src/gallium/drivers/svga/svga_cmd.c
@@ -67,7 +67,7 @@ void surface_to_surfaceid(struct svga_winsys_context *swc, // IN
       id->mipmap = s->real_level;
    }
    else {
-      id->sid = SVGA3D_INVALID_ID;
+      swc->surface_relocation(swc, &id->sid, NULL, flags);
       id->face = 0;
       id->mipmap = 0;
    }
diff --git a/src/gallium/drivers/svga/svga_state_tss.c b/src/gallium/drivers/svga/svga_state_tss.c
index 76a2dae143..e42c4f7fce 100644
--- a/src/gallium/drivers/svga/svga_state_tss.c
+++ b/src/gallium/drivers/svga/svga_state_tss.c
@@ -128,18 +128,21 @@ update_tss_binding(struct svga_context *svga,
          goto fail;
 
       for (i = 0; i < queue.bind_count; i++) {
+         struct svga_winsys_surface *handle;
+
          ts[i].stage = queue.bind[i].unit;
          ts[i].name = SVGA3D_TS_BIND_TEXTURE;
 
          if (queue.bind[i].view->v) {
-            svga->swc->surface_relocation(svga->swc,
-                                          &ts[i].value,
-                                          queue.bind[i].view->v->handle,
-                                          SVGA_RELOC_READ);
+            handle = queue.bind[i].view->v->handle;
          }
          else {
-            ts[i].value = SVGA3D_INVALID_ID;
+            handle = NULL;
          }
+         svga->swc->surface_relocation(svga->swc,
+                                       &ts[i].value,
+                                       handle,
+                                       SVGA_RELOC_READ);
          
          queue.bind[i].view->dirty = FALSE;
       }
-- 
cgit v1.2.3


From a0c45eabf961905ea7bd48b2750fce41c8ba542b Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 00:21:55 +0200
Subject: nvfx: use relocations array for vp constants

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 18 ++++++------
 src/gallium/drivers/nvfx/nvfx_shader.h   |  2 +-
 src/gallium/drivers/nvfx/nvfx_state.h    |  2 +-
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 47 ++++++++++++++++----------------
 4 files changed, 34 insertions(+), 35 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index db33ecd78c..025989ac5b 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -270,7 +270,7 @@ nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
 static void
 nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
 {
-        struct nvfx_label_relocation reloc;
+        struct nvfx_relocation reloc;
         uint32_t *hw;
         fpc->inst_offset = fpc->fp->insn_len;
         grow_insns(fpc, 4);
@@ -284,7 +284,7 @@ nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
         hw[3] = 0;
         reloc.target = target;
         reloc.location = fpc->inst_offset + 2;
-        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
 }
 
 static void
@@ -306,7 +306,7 @@ nv40_fp_ret(struct nvfx_fpc *fpc)
 static void
 nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
 {
-        struct nvfx_label_relocation reloc;
+        struct nvfx_relocation reloc;
         uint32_t *hw;
         fpc->inst_offset = fpc->fp->insn_len;
         grow_insns(fpc, 4);
@@ -325,7 +325,7 @@ nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
         hw[3] = 0; /* | end_offset */
         reloc.target = target;
         reloc.location = fpc->inst_offset + 3;
-        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
         //util_dynarray_append(&fpc->loop_stack, unsigned, target);
 }
 
@@ -333,7 +333,7 @@ nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
 static void
 nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
 {
-        struct nvfx_label_relocation reloc;
+        struct nvfx_relocation reloc;
         uint32_t *hw;
         fpc->inst_offset = fpc->fp->insn_len;
         grow_insns(fpc, 4);
@@ -349,10 +349,10 @@ nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
         hw[3] = 0; /* | endif_offset */
         reloc.target = target;
         reloc.location = fpc->inst_offset + 2;
-        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
         reloc.target = target;
         reloc.location = fpc->inst_offset + 3;
-        util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
+        util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
 }
 
 static void
@@ -1041,9 +1041,9 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 	}
 	util_dynarray_append(&insns, unsigned, fp->insn_len);
 
-	for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_label_relocation))
+	for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
 	{
-		struct nvfx_label_relocation* label_reloc = (struct nvfx_label_relocation*)((char*)fpc->label_relocs.data + i);
+		struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)fpc->label_relocs.data + i);
 		fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
 	}
 	util_dynarray_fini(&insns);
diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h
index 52e684aec3..c711484ee2 100644
--- a/src/gallium/drivers/nvfx/nvfx_shader.h
+++ b/src/gallium/drivers/nvfx/nvfx_shader.h
@@ -509,7 +509,7 @@ nvfx_src_abs(struct nvfx_src src)
 	return src;
 }
 
-struct nvfx_label_relocation {
+struct nvfx_relocation {
         unsigned location;
         unsigned target;
 };
diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
index 6d589af5f3..1247abcfa2 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ b/src/gallium/drivers/nvfx/nvfx_state.h
@@ -9,7 +9,6 @@
 
 struct nvfx_vertex_program_exec {
 	uint32_t data[4];
-	int const_index;
 };
 
 struct nvfx_vertex_program_data {
@@ -46,6 +45,7 @@ struct nvfx_vertex_program {
 	uint32_t clip_ctrl;
 
 	struct util_dynarray branch_relocs;
+	struct util_dynarray const_relocs;
 };
 
 struct nvfx_fragment_program_data {
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 38f37168a1..996680e32c 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -113,6 +113,7 @@ emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos,
 {
 	struct nvfx_vertex_program *vp = vpc->vp;
 	uint32_t sr = 0;
+	struct nvfx_relocation reloc;
 
 	switch (src.reg.type) {
 	case NVFXSR_TEMP:
@@ -128,9 +129,9 @@ emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos,
 	case NVFXSR_CONST:
 		sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
 		       NVFX_VP(SRC_REG_TYPE_SHIFT));
-		assert(vpc->vpi->const_index == -1 ||
-		       vpc->vpi->const_index == src.reg.index);
-		vpc->vpi->const_index = src.reg.index;
+		reloc.location = vp->nr_insns - 1;
+		reloc.target = src.reg.index;
+		util_dynarray_append(&vp->const_relocs, struct nvfx_relocation, reloc);
 		break;
 	case NVFXSR_NONE:
 		sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
@@ -308,7 +309,6 @@ nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
 	vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
 	vpc->vpi = &vp->insns[vp->nr_insns - 1];
 	memset(vpc->vpi, 0, sizeof(*vpc->vpi));
-	vpc->vpi->const_index = -1;
 
 	hw = vpc->vpi->data;
 
@@ -440,7 +440,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 	struct nvfx_reg dst;
 	struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
 	struct nvfx_insn insn;
-	struct nvfx_label_relocation reloc;
+	struct nvfx_relocation reloc;
 	struct nvfx_loop_entry loop;
 	int mask;
 	int ai = -1, ci = -1, ii = -1;
@@ -662,7 +662,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 
 		reloc.location = vpc->vp->nr_insns;
 		reloc.target = finst->Label.Label + 1;
-		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
 
 		insn = arith(SCA, BRA, none.reg, 0, none, none, none);
 		insn.cc_test = NVFX_COND_EQ;
@@ -675,7 +675,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 	case TGSI_OPCODE_CAL:
 		reloc.location = vpc->vp->nr_insns;
 		reloc.target = finst->Label.Label;
-		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
 
 		if(finst->Instruction.Opcode == TGSI_OPCODE_CAL)
 			insn = arith(SCA, CAL, none.reg, 0, none, none, none);
@@ -707,7 +707,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 
 		reloc.location = vpc->vp->nr_insns;
 		reloc.target = loop.cont_target;
-		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
 
 		nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
 		break;
@@ -717,7 +717,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 
 		reloc.location = vpc->vp->nr_insns;
 		reloc.target = loop.cont_target;
-		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
 
 		nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
 		break;
@@ -727,7 +727,7 @@ nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
 
 		reloc.location = vpc->vp->nr_insns;
 		reloc.target = loop.brk_target;
-		util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
+		util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
 
 		nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
 		break;
@@ -979,17 +979,17 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 
 	util_dynarray_append(&insns, unsigned, vp->nr_insns);
 
-	for(unsigned i = 0; i < vpc->label_relocs.size; i += sizeof(struct nvfx_label_relocation))
+	for(unsigned i = 0; i < vpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
 	{
-		struct nvfx_label_relocation* label_reloc = (struct nvfx_label_relocation*)((char*)vpc->label_relocs.data + i);
-		struct nvfx_label_relocation hw_reloc;
+		struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)vpc->label_relocs.data + i);
+		struct nvfx_relocation hw_reloc;
 
 		hw_reloc.location = label_reloc->location;
 		hw_reloc.target = ((unsigned*)insns.data)[label_reloc->target];
 
 		//debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
 
-		util_dynarray_append(&vp->branch_relocs, struct nvfx_label_relocation, hw_reloc);
+		util_dynarray_append(&vp->branch_relocs, struct nvfx_relocation, hw_reloc);
 	}
 	util_dynarray_fini(&insns);
 	util_dynarray_trim(&vp->branch_relocs);
@@ -1155,9 +1155,9 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 	 */
 	if (vp->exec_start != vp->exec->start) {
 		//printf("vp_relocs %u -> %u\n", vp->exec_start, vp->exec->start);
-		for(unsigned i = 0; i < vp->branch_relocs.size; i += sizeof(struct nvfx_label_relocation))
+		for(unsigned i = 0; i < vp->branch_relocs.size; i += sizeof(struct nvfx_relocation))
 		{
-			struct nvfx_label_relocation* reloc = (struct nvfx_label_relocation*)((char*)vp->branch_relocs.data + i);
+			struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->branch_relocs.data + i);
 			uint32_t* hw = vp->insns[reloc->location].data;
 			unsigned target = vp->exec->start + reloc->target;
 
@@ -1182,16 +1182,15 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 	}
 
 	if (vp->nr_consts && vp->data_start != vp->data->start) {
-		for (i = 0; i < vp->nr_insns; i++) {
-			struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
+		for(unsigned i = 0; i < vp->const_relocs.size; i += sizeof(struct nvfx_relocation))
+		{
+			struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->const_relocs.data + i);
+			struct nvfx_vertex_program_exec *vpi = &vp->insns[reloc->location];
 
-			if (vpi->const_index >= 0) {
-				vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
-				vpi->data[1] |=
-					(vpi->const_index + vp->data->start) <<
+			vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
+			vpi->data[1] |=
+					(reloc->target + vp->data->start) <<
 					NVFX_VP(INST_CONST_SRC_SHIFT);
-
-			}
 		}
 
 		vp->data_start = vp->data->start;
-- 
cgit v1.2.3


From 793e398681ac9ef9da6f6a453a5665bdfd0270e8 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 14:53:49 +0200
Subject: nvfx: fix vertex programs

---
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 996680e32c..3c3521e162 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -1272,4 +1272,6 @@ nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
 	vp->data_start_min = 0;
 
 	vp->ir = vp->or = vp->clip_ctrl = 0;
+	util_dynarray_fini(&vp->branch_relocs);
+	util_dynarray_fini(&vp->const_relocs);
 }
-- 
cgit v1.2.3


From 9fefab340f59519efc5c5690347a54e437d9407a Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 11:58:54 +0200
Subject: nvfx: make stipple setting independent of enable

---
 src/gallium/drivers/nvfx/nvfx_context.c       |  1 -
 src/gallium/drivers/nvfx/nvfx_context.h       |  1 -
 src/gallium/drivers/nvfx/nvfx_state.c         |  7 -------
 src/gallium/drivers/nvfx/nvfx_state_stipple.c | 21 +++------------------
 4 files changed, 3 insertions(+), 27 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 94c854b22b..8e852010f5 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -90,7 +90,6 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 
 	/* set these to that we init them on first validation */
 	nvfx->state.scissor_enabled = ~0;
-	nvfx->state.stipple_enabled = ~0;
 	nvfx->use_vertex_buffers = -1;
 
 	LIST_INITHEAD(&nvfx->render_cache);
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 83c44ef477..63fbce87b5 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -68,7 +68,6 @@ struct nvfx_blend_state {
 
 struct nvfx_state {
 	unsigned scissor_enabled;
-	unsigned stipple_enabled;
 	unsigned fp_samplers;
 	unsigned render_temps;
 };
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index c8431641d3..e3c3fcb7d5 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -173,13 +173,6 @@ nvfx_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
 			nvfx->draw_dirty |= NVFX_NEW_SCISSOR;
 		}
 
-		if(((struct nvfx_rasterizer_state*)hwcso)->pipe.poly_stipple_enable
-					!= nvfx->rasterizer->pipe.poly_stipple_enable)
-		{
-			nvfx->dirty |= NVFX_NEW_STIPPLE;
-			nvfx->draw_dirty |= NVFX_NEW_STIPPLE;
-		}
-
 		if(((struct nvfx_rasterizer_state*)hwcso)->pipe.point_quad_rasterization != nvfx->rasterizer->pipe.point_quad_rasterization
 				|| ((struct nvfx_rasterizer_state*)hwcso)->pipe.sprite_coord_enable != nvfx->rasterizer->pipe.sprite_coord_enable)
 		{
diff --git a/src/gallium/drivers/nvfx/nvfx_state_stipple.c b/src/gallium/drivers/nvfx/nvfx_state_stipple.c
index 4da968f093..b76e9dd382 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_stipple.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_stipple.c
@@ -4,23 +4,8 @@ void
 nvfx_state_stipple_validate(struct nvfx_context *nvfx)
 {
 	struct nouveau_channel *chan = nvfx->screen->base.channel;
-	struct pipe_rasterizer_state *rast = &nvfx->rasterizer->pipe;
 
-	if ((rast->poly_stipple_enable == 0 && nvfx->state.stipple_enabled == 0))
-		return;
-
-	if (rast->poly_stipple_enable) {
-		unsigned i;
-
-		WAIT_RING(chan, 35);
-		OUT_RING(chan, RING_3D(NV34TCL_POLYGON_STIPPLE_ENABLE, 1));
-		OUT_RING(chan, 1);
-		OUT_RING(chan, RING_3D(NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32));
-		for (i = 0; i < 32; i++)
-			OUT_RING(chan, nvfx->stipple[i]);
-	} else {
-		WAIT_RING(chan, 2);
-		OUT_RING(chan, RING_3D(NV34TCL_POLYGON_STIPPLE_ENABLE, 1));
-		OUT_RING(chan, 0);
-	}
+	WAIT_RING(chan, 33);
+	OUT_RING(chan, RING_3D(NV34TCL_POLYGON_STIPPLE_PATTERN(0), 32));
+	OUT_RINGp(chan, nvfx->stipple, 32);
 }
-- 
cgit v1.2.3


From 7de1f86c49716eeadb443507d16ead933288059c Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 12:02:41 +0200
Subject: nvfx: simplify and correct fragment program update logic

This version should hopefully be much clearer and thus less likely
to be subtly broken.

Also fixes point sprites on nv40 and possibly some other bugs too.
---
 src/gallium/drivers/nvfx/nvfx_context.c    |   2 +
 src/gallium/drivers/nvfx/nvfx_context.h    |   2 +
 src/gallium/drivers/nvfx/nvfx_fragprog.c   | 185 +++++++++++++++++++----------
 src/gallium/drivers/nvfx/nvfx_state.h      |   3 +-
 src/gallium/drivers/nvfx/nvfx_state_emit.c |   2 +
 src/gallium/drivers/nvfx/nvfx_vertprog.c   |  49 +++-----
 6 files changed, 149 insertions(+), 94 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 8e852010f5..e78fc14da4 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -90,6 +90,8 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 
 	/* set these to that we init them on first validation */
 	nvfx->state.scissor_enabled = ~0;
+	nvfx->hw_pointsprite_control = -1;
+	nvfx->hw_vp_output = -1;
 	nvfx->use_vertex_buffers = -1;
 
 	LIST_INITHEAD(&nvfx->render_cache);
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 63fbce87b5..fb4a9da579 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -193,6 +193,8 @@ struct nvfx_context {
 	uint32_t hw_txf[8];
 	struct nvfx_render_target hw_rt[4];
 	struct nvfx_render_target hw_zeta;
+	int hw_pointsprite_control;
+	int hw_vp_output;
 };
 
 static INLINE struct nvfx_context *
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 025989ac5b..e40a814e18 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -1101,6 +1101,35 @@ nvfx_fp_memcpy(void* dst, const void* src, size_t len)
 #endif
 }
 
+/* The hardware only supports immediate constants inside the fragment program,
+ * and at least on nv30 doesn't support an indirect linkage table.
+ *
+ * Hence, we need to patch the fragment program itself both to update constants
+ * and update linkage.
+ *
+ * Using a single fragment program would entail unacceptable stalls if the GPU is
+ * already rendering with that fragment program.
+ * Thus, we instead use a "rotating queue" of buffer objects, each of which is
+ * packed with multiple versions of the same program.
+ *
+ * Whenever we need to patch something, we move to the next program and
+ * patch it. If all buffer objects are in use by the GPU, we allocate another one,
+ * expanding the queue.
+ *
+ * As an additional optimization, we record when all the programs have the
+ * current input slot configuration, and at that point we stop patching inputs.
+ * This happens, for instance, if a given fragment program is always used with
+ * the same vertex program (i.e. always with GLSL), or if the layouts match
+ * enough (non-GLSL).
+ *
+ * Note that instead of using multiple programs, we could push commands
+ * on the FIFO to patch a single program: it's not fully clear which option is
+ * faster, but my guess is that the current way is faster.
+ *
+ * We also track the previous slot assignments for each version and don't
+ * patch if they are the same (this could perhaps be removed).
+ */
+
 void
 nvfx_fragprog_validate(struct nvfx_context *nvfx)
 {
@@ -1109,6 +1138,7 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	int update = 0;
 	struct nvfx_vertex_program* vp;
 	unsigned sprite_coord_enable;
+	boolean update_pointsprite = !!(nvfx->dirty & NVFX_NEW_FRAGPROG);
 
 	if (!fp->translated)
 	{
@@ -1141,80 +1171,96 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 		fp->bo_prog_idx = fp->progs_per_bo - 1;
 	}
 
-	/* we must update constants even on "just" fragprog changes, because
-	   we don't check whether the current constant buffer matches the latest
-	   one bound to this fragment program */
-	if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG))
-		update = TRUE;
-
 	vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
-	if (fp->last_vp_id != vp->id) {
-		char* vp_sem_table = vp->generic_to_fp_input;
-		unsigned char* fp_semantics = fp->slot_to_generic;
-		unsigned diff = 0;
-		unsigned char* cur_slots;
-		fp->last_vp_id = nvfx->vertprog->id;
-		cur_slots = fp->slot_to_fp_input;
-		for(unsigned i = 0; i < fp->num_slots; ++i) {
-			unsigned char slot_mask = vp_sem_table[fp_semantics[i]];
-			diff |= (slot_mask >> 4) & (slot_mask ^ cur_slots[i]);
-		}
+        sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
+
+	if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) {
+		int sprite_input = -1;
+		unsigned i;
+		fp->last_vp_id = vp->id;
+		fp->last_sprite_coord_enable = sprite_coord_enable;
 
-		if(diff)
+		if(sprite_coord_enable)
 		{
-			for(unsigned i = 0; i < fp->num_slots; ++i) {
-				/* if 0xff, then this will write to the dummy value at fp->last_layout_mask[0] */
-				fp->slot_to_fp_input[i] = vp_sem_table[fp_semantics[i]] & 0xf;
-				//printf("fp: GENERIC[%i] from fpreg %i\n", fp_semantics[i], fp->slot_to_fp_input[i]);
+			sprite_input = vp->sprite_fp_input;
+			if(sprite_input < 0)
+			{
+				unsigned used_texcoords = 0;
+				for(unsigned i = 0; i < fp->num_slots; ++i) {
+					unsigned generic = fp->slot_to_generic[i];
+					if(!((1 << generic) & sprite_coord_enable))
+					{
+						unsigned char slot_mask = vp->generic_to_fp_input[generic];
+						if(slot_mask >= 0xf0)
+							used_texcoords |= 1 << ((slot_mask & 0xf) - NVFX_FP_OP_INPUT_SRC_TC0);
+					}
+				}
+
+				sprite_input = NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords));
 			}
 
-			fp->progs_left_with_obsolete_slot_assignments = fp->progs;
-			update = TRUE;
+			fp->point_sprite_control |= (1 << (sprite_input - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
 		}
-	}
+		else
+			fp->point_sprite_control = 0;
 
-	// last_sprite_coord_enable
-	sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
-	if(fp->last_sprite_coord_enable != sprite_coord_enable)
-	{
-		unsigned texcoord_mask = vp->texcoord_ouput_mask;
-		fp->last_sprite_coord_enable = sprite_coord_enable;
-		fp->point_sprite_control = 0;
-		for(unsigned i = 0; i < fp->num_slots; ++i) {
-			if((1 << fp->slot_to_generic[i]) & sprite_coord_enable)
+		for(i = 0; i < fp->num_slots; ++i) {
+			unsigned generic = fp->slot_to_generic[i];
+			if((1 << generic) & sprite_coord_enable)
 			{
-				unsigned fpin = fp->slot_to_fp_input[i];
-				//printf("sprite: slot %i generic %i had texcoord %i\n", i, fp->slot_to_generic[i], fpin - NVFX_FP_OP_INPUT_SRC_TC0);
-				if(fpin >= 0x0f)
-				{
-					unsigned tc = __builtin_ctz(~texcoord_mask);
-					texcoord_mask |= (1 << tc);
-					fp->slot_to_fp_input[i] = fpin = NVFX_FP_OP_INPUT_SRC_TC(tc);
-
-					fp->progs_left_with_obsolete_slot_assignments = fp->progs;
-					update = TRUE;
-				}
-				//printf("sprite: slot %i texcoord %i\n", i, fpin - NVFX_FP_OP_INPUT_SRC_TC0);
-				fp->point_sprite_control |= (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
+				if(fp->slot_to_fp_input[i] != sprite_input)
+					goto update_slots;
 			}
 			else
 			{
-				unsigned fpin = fp->slot_to_fp_input[i];
-				if(!(vp->texcoord_ouput_mask & (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0))))
-				{
-					fp->slot_to_fp_input[i] = 0x0f;
+				unsigned char slot_mask = vp->generic_to_fp_input[generic];
+				if((slot_mask >> 4) & (slot_mask ^ fp->slot_to_fp_input[i]))
+					goto update_slots;
+			}
+		}
+
+		if(0)
+		{
+update_slots:
+			/* optimization: we start updating from the slot we found the first difference in */
+			for(; i < fp->num_slots; ++i)
+			{
+				unsigned generic = fp->slot_to_generic[i];
+				if((1 << generic) & sprite_coord_enable)
+					fp->slot_to_fp_input[i] = sprite_input;
+				else
+					fp->slot_to_fp_input[i] = vp->generic_to_fp_input[generic] & 0xf;
+			}
 
-					fp->progs_left_with_obsolete_slot_assignments = fp->progs;
-					update = TRUE;
+			if(nvfx->is_nv4x)
+			{
+				fp->or = 0;
+				for(i = 0; i < fp->num_slots; ++i) {
+					unsigned fp_input = fp->slot_to_fp_input[i];
+					if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(8))
+						fp->or |= (1 << 12);
+					else if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(9))
+						fp->or |= (1 << 13);
+					else if(fp_input != 0xf)
+						fp->or |= (1 << (fp_input - NVFX_FP_OP_INPUT_SRC_TC0 + 14));
 				}
 			}
+
+			fp->progs_left_with_obsolete_slot_assignments = fp->progs;
+			goto update;
 		}
 	}
 
-	if(update) {
+	/* We must update constants even on "just" fragprog changes, because
+	  * we don't check whether the current constant buffer matches the latest
+	  * one bound to this fragment program.
+	  * Doing such a check would likely be a pessimization.
+	  */
+	if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG)) {
 		int offset;
 		uint32_t* fpmap;
 
+update:
 		++fp->bo_prog_idx;
 		if(fp->bo_prog_idx >= fp->progs_per_bo)
 		{
@@ -1278,6 +1324,9 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			}
 		}
 
+		/* we only do this if we aren't sure that all program versions have the
+		 * current slot assignments, otherwise we just update constants for speed
+		 */
 		if(fp->progs_left_with_obsolete_slot_assignments) {
 			unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
 			for(unsigned i = 0; i < fp->num_slots; ++i) {
@@ -1296,10 +1345,7 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			}
 			--fp->progs_left_with_obsolete_slot_assignments;
 		}
-	}
 
-	if(update || (nvfx->dirty & NVFX_NEW_FRAGPROG)) {
-		int offset = fp->bo_prog_idx * fp->prog_size;
 		MARK_RING(chan, 8, 1);
 		OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1));
 		OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
@@ -1316,11 +1362,28 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 		}
 	}
 
-	if(nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_SPRITE))
 	{
-		WAIT_RING(chan, 2);
-		OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
-		OUT_RING(chan, fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization);
+		unsigned pointsprite_control = fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization;
+		if(pointsprite_control != nvfx->hw_pointsprite_control)
+		{
+			WAIT_RING(chan, 2);
+			OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
+			OUT_RING(chan, pointsprite_control);
+			nvfx->hw_pointsprite_control = pointsprite_control;
+		}
+	}
+
+	if(nvfx->is_nv4x)
+	{
+		unsigned vp_output = vp->or | fp->or;
+
+		if(vp_output != nvfx->hw_vp_output)
+		{
+			WAIT_RING(chan, 2);
+			OUT_RING(chan, RING_3D(NV40TCL_VP_RESULT_EN, 1));
+			OUT_RING(chan, vp_output);
+			nvfx->hw_vp_output = vp_output;
+		}
 	}
 }
 
diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
index 1247abcfa2..05d41cfc8d 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ b/src/gallium/drivers/nvfx/nvfx_state.h
@@ -32,7 +32,7 @@ struct nvfx_vertex_program {
 	unsigned nr_consts;
 
 	char generic_to_fp_input[256];
-	unsigned texcoord_ouput_mask;
+	int sprite_fp_input;
 
 	struct nouveau_resource *exec;
 	unsigned exec_start;
@@ -67,6 +67,7 @@ struct nvfx_fragment_program {
 	boolean translated;
 	unsigned samplers;
 	unsigned point_sprite_control;
+	unsigned or;
 
 	uint32_t *insn;
 	int       insn_len;
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index 8e3c342179..bd89a385d7 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -17,6 +17,8 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	{
 		nvfx->dirty = ~0;
 		nvfx->hw_vtxelt_nr = 16;
+		nvfx->hw_pointsprite_control = -1;
+		nvfx->hw_vp_output = -1;
 		nvfx->screen->cur_ctx = nvfx;
 	}
 
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 3c3521e162..806f263dcf 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -235,24 +235,10 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 			dst.index = NVFX_VP(INST_DEST_PSZ);
 			break;
 		default:
-			if(!nvfx->is_nv4x) {
-				switch (dst.index) {
-				case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
-				case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
-				case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
-				case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
-				case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
-				case NV30_VP_INST_DEST_PSZ  : vp->or |= (1 << 5); break;
-				case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
-				case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
-				case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
-				case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
-				case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
-				case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
-				case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
-				case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
-				}
-			} else {
+			if(nvfx->is_nv4x) {
+				/* we don't need vp->or on nv3x
+				 * texcoords are handled by fragment program
+				 */
 				switch (dst.index) {
 				case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
 				case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
@@ -260,14 +246,6 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 				case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
 				case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
 				case NV40_VP_INST_DEST_PSZ  : vp->or |= (1 << 5); break;
-				case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
-				case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
-				case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
-				case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
-				case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
-				case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
-				case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
-				case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
 				}
 			}
 			break;
@@ -817,13 +795,21 @@ nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
 
 	/* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
 	memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input));
-	vpc->vp->texcoord_ouput_mask = 0;
 	for(int i = 0; i < 8; ++i) {
 		if(sem_layout[i] == 0xff)
 			continue;
-		vpc->vp->texcoord_ouput_mask |= (1 << i);
 		//printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
-		vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | (NVFX_FP_OP_INPUT_SRC_TC(0) + i);
+		vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | NVFX_FP_OP_INPUT_SRC_TC(i);
+	}
+
+	vpc->vp->sprite_fp_input = -1;
+	for(int i = 0; i < 8; ++i)
+	{
+		if(sem_layout[i] == 0xff)
+		{
+			vpc->vp->sprite_fp_input = NVFX_FP_OP_INPUT_SRC_TC(i);
+			break;
+		}
 	}
 
 	tgsi_parse_init(&p, vpc->vp->pipe.tokens);
@@ -1233,13 +1219,12 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 
 	if(nvfx->dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
 	{
-		WAIT_RING(chan, 7);
+		WAIT_RING(chan, 6);
 		OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
 		OUT_RING(chan, vp->exec->start);
 		if(nvfx->is_nv4x) {
-			OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 2));
+			OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 1));
 			OUT_RING(chan, vp->ir);
-			OUT_RING(chan, vp->or);
 		}
 		OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
 		OUT_RING(chan, vp->clip_ctrl);
-- 
cgit v1.2.3


From 0ad82b8d28cbb8d7224bf96c43c80fed45321597 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Sun, 22 Aug 2010 11:43:01 +0100
Subject: llvmpipe: don't clear unused bins

If bins outside the current scene bounds are being corrupted, we'll
need to fix that separately.  Currently seems ok though.
---
 src/gallium/drivers/llvmpipe/lp_scene.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_scene.c b/src/gallium/drivers/llvmpipe/lp_scene.c
index f88a759fe7..15a09b7100 100644
--- a/src/gallium/drivers/llvmpipe/lp_scene.c
+++ b/src/gallium/drivers/llvmpipe/lp_scene.c
@@ -163,12 +163,15 @@ lp_scene_reset(struct lp_scene *scene )
 
    /* Free all but last binner command lists:
     */
-   for (i = 0; i < TILES_X; i++) {
-      for (j = 0; j < TILES_Y; j++) {
+   for (i = 0; i < scene->tiles_x; i++) {
+      for (j = 0; j < scene->tiles_y; j++) {
          lp_scene_bin_reset(scene, i, j);
       }
    }
 
+   /* If there are any bins which weren't cleared by the loop above,
+    * they will be caught (on debug builds at least) by this assert:
+    */
    assert(lp_scene_is_empty(scene));
 
    /* Free all but last binned data block:
-- 
cgit v1.2.3


From 49a2ea082b16732959b1e8e793d9c3293d8332c0 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Sun, 22 Aug 2010 12:16:45 +0100
Subject: llvmpipe: remove unused member from lp_fragment_shader_variant_key

---
 src/gallium/drivers/llvmpipe/lp_state_fs.h | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.h b/src/gallium/drivers/llvmpipe/lp_state_fs.h
index 37900fc544..78c5b1aee2 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_fs.h
+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.h
@@ -56,10 +56,6 @@ struct lp_fragment_shader_variant_key
    unsigned flatshade:1;
    unsigned occlusion_count:1;
 
-   struct {
-      ubyte colormask;
-   } cbuf_blend[PIPE_MAX_COLOR_BUFS];
-
    struct lp_sampler_static_state sampler[PIPE_MAX_SAMPLERS];
 };
 
-- 
cgit v1.2.3


From 3d4b60f1f7be3dc54951c9c414601062e73ca674 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Sun, 22 Aug 2010 12:31:18 +0100
Subject: llvmpipe: reduce size of fragment shader variant key

Don't spend as much time comparing them.
---
 src/gallium/drivers/llvmpipe/lp_state_fs.c | 26 ++++++++++++++++++++------
 src/gallium/drivers/llvmpipe/lp_state_fs.h |  2 ++
 2 files changed, 22 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
index dbca49a2ef..35ef63389c 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
@@ -808,7 +808,7 @@ generate_variant(struct llvmpipe_context *lp,
    variant->list_item_local.base = variant;
    variant->no = shader->variants_created++;
 
-   memcpy(&variant->key, key, sizeof *key);
+   memcpy(&variant->key, key, shader->variant_key_size);
 
    if (gallivm_debug & GALLIVM_DEBUG_IR) {
       debug_printf("llvmpipe: Creating fragment shader #%u variant #%u:\n", 
@@ -840,6 +840,7 @@ llvmpipe_create_fs_state(struct pipe_context *pipe,
                          const struct pipe_shader_state *templ)
 {
    struct lp_fragment_shader *shader;
+   int nr_samplers;
 
    shader = CALLOC_STRUCT(lp_fragment_shader);
    if (!shader)
@@ -854,6 +855,11 @@ llvmpipe_create_fs_state(struct pipe_context *pipe,
    /* we need to keep a local copy of the tokens */
    shader->base.tokens = tgsi_dup_tokens(templ->tokens);
 
+   nr_samplers = shader->info.file_max[TGSI_FILE_SAMPLER] + 1;
+
+   shader->variant_key_size = Offset(struct lp_fragment_shader_variant_key,
+				     sampler[nr_samplers]);
+
    if (LP_DEBUG & DEBUG_TGSI) {
       unsigned attrib;
       debug_printf("llvmpipe: Create fragment shader #%u %p:\n", shader->no, (void *) shader);
@@ -1027,7 +1033,7 @@ make_variant_key(struct llvmpipe_context *lp,
 {
    unsigned i;
 
-   memset(key, 0, sizeof *key);
+   memset(key, 0, shader->variant_key_size);
 
    if (lp->framebuffer.zsbuf) {
       if (lp->depth_stencil->depth.enabled) {
@@ -1097,9 +1103,17 @@ make_variant_key(struct llvmpipe_context *lp,
       }
    }
 
-   for(i = 0; i < PIPE_MAX_SAMPLERS; ++i)
-      if(shader->info.file_mask[TGSI_FILE_SAMPLER] & (1 << i))
-         lp_sampler_static_state(&key->sampler[i], lp->fragment_sampler_views[i], lp->sampler[i]);
+   /* This value will be the same for all the variants of a given shader:
+    */
+   key->nr_samplers = shader->info.file_max[TGSI_FILE_SAMPLER] + 1;
+
+   for(i = 0; i < key->nr_samplers; ++i) {
+      if(shader->info.file_mask[TGSI_FILE_SAMPLER] & (1 << i)) {
+         lp_sampler_static_state(&key->sampler[i],
+				 lp->fragment_sampler_views[i],
+				 lp->sampler[i]);
+      }
+   }
 }
 
 /**
@@ -1118,7 +1132,7 @@ llvmpipe_update_fs(struct llvmpipe_context *lp)
 
    li = first_elem(&shader->variants);
    while(!at_end(&shader->variants, li)) {
-      if(memcmp(&li->base->key, &key, sizeof key) == 0) {
+      if(memcmp(&li->base->key, &key, shader->variant_key_size) == 0) {
          variant = li->base;
          break;
       }
diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.h b/src/gallium/drivers/llvmpipe/lp_state_fs.h
index 78c5b1aee2..33c480010d 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_fs.h
+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.h
@@ -53,6 +53,7 @@ struct lp_fragment_shader_variant_key
    struct pipe_blend_state blend;
    enum pipe_format zsbuf_format;
    unsigned nr_cbufs:8;
+   unsigned nr_samplers:8;	/* actually derivable from just the shader */
    unsigned flatshade:1;
    unsigned occlusion_count:1;
 
@@ -93,6 +94,7 @@ struct lp_fragment_shader
    struct lp_fs_variant_list_item variants;
 
    /* For debugging/profiling purposes */
+   unsigned variant_key_size;
    unsigned no;
    unsigned variants_created;
    unsigned variants_cached;
-- 
cgit v1.2.3


From ed99c28d12579bb8ee79eb9cfa55452785be7b6e Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Sun, 22 Aug 2010 14:22:00 -0400
Subject: r600g: depth buffer likely needs decompression when used as texture

Before using depth buffer as texture, it needs to be decompressed
(tile pattern of db are different from one used for colorbuffer
like texture)

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c     | 665 ++++++++++++++++++++++++++++++-
 src/gallium/drivers/r600/r600_context.h  |   2 +-
 src/gallium/drivers/r600/r600_draw.c     |   2 +-
 src/gallium/drivers/r600/r600_resource.h |   8 +
 src/gallium/drivers/r600/r600_screen.h   |   9 +-
 src/gallium/drivers/r600/r600_shader.c   |   1 +
 src/gallium/drivers/r600/r600_state.c    |  38 +-
 src/gallium/drivers/r600/r600_texture.c  | 228 +++++++++++
 8 files changed, 919 insertions(+), 34 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index dc57b333a0..8cb2795d2b 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -24,6 +24,7 @@
  *      Jerome Glisse
  *      Marek Olšák
  */
+#include <errno.h>
 #include <pipe/p_screen.h>
 #include <util/u_blitter.h>
 #include <util/u_inlines.h>
@@ -31,6 +32,7 @@
 #include "util/u_surface.h"
 #include "r600_screen.h"
 #include "r600_context.h"
+#include "r600d.h"
 
 static void r600_blitter_save_states(struct pipe_context *ctx)
 {
@@ -130,28 +132,8 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 				      unsigned srcx, unsigned srcy, unsigned srcz,
 				      unsigned width, unsigned height)
 {
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-	struct pipe_sampler_state *samplers[PIPE_MAX_ATTRIBS];
-	struct pipe_sampler_view_state *sampler_views[PIPE_MAX_ATTRIBS];
-	unsigned i;
-
-	for (i = 0; i < rctx->ps_nsampler_view; i++) {
-		sampler_views[i] = &rctx->ps_sampler_view[i]->state.sampler_view;
-	}
-	for (i = 0; i < rctx->ps_nsampler; i++) {
-		samplers[i] = &rctx->ps_sampler[i]->state.sampler;
-	}
-	r600_blitter_save_states(ctx);
-	util_blitter_save_framebuffer(rctx->blitter, fb);
-	util_blitter_save_fragment_sampler_states(rctx->blitter, rctx->ps_nsampler, samplers);
-	util_blitter_save_fragment_sampler_views(rctx->blitter, rctx->ps_nsampler_view, sampler_views);
-
-	util_blitter_copy_region(rctx->blitter, dst, subdst, dstx, dsty, dstz,
-			src, subsrc, srcx, srcy, srcz, width, height,
-			TRUE);
-	/* resume queries */
-	r600_queries_resume(ctx);
+	util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
+				  src, subsrc, srcx, srcy, srcz, width, height);
 }
 
 void r600_init_blit_functions(struct r600_context *rctx)
@@ -161,3 +143,642 @@ void r600_init_blit_functions(struct r600_context *rctx)
 	rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
 	rctx->context.resource_copy_region = r600_resource_copy_region;
 }
+
+
+struct r600_blit_states {
+	struct radeon_state	*rasterizer;
+	struct radeon_state	*dsa;
+	struct radeon_state	*blend;
+	struct radeon_state	*viewport;
+	struct radeon_state	*cb_cntl;
+	struct radeon_state	*config;
+	struct radeon_state	*vgt;
+	struct radeon_state	*draw;
+	struct radeon_state	*vs_constant0;
+	struct radeon_state	*vs_constant1;
+	struct radeon_state	*vs_constant2;
+	struct radeon_state	*vs_constant3;
+	struct radeon_state	*ps_shader;
+	struct radeon_state	*vs_shader;
+	struct radeon_state	*vs_resource0;
+	struct radeon_state	*vs_resource1;
+};
+
+static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates)
+{
+	struct radeon_state *rstate;
+	struct radeon_bo *bo;
+	u32 vbo[] = {
+		0xBF800000, 0xBF800000, 0x3F800000, 0x3F800000,
+		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
+		0x3F800000, 0xBF800000, 0x3F800000, 0x3F800000,
+		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
+		0x3F800000, 0x3F800000, 0x3F800000, 0x3F800000,
+		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000,
+		0xBF800000, 0x3F800000, 0x3F800000, 0x3F800000,
+		0x3F000000, 0x3F000000, 0x3F000000, 0x00000000
+	};
+
+	/* simple shader */
+	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
+	if (bo == NULL) {
+		return -ENOMEM;
+	}
+	if (radeon_bo_map(rscreen->rw, bo)) {
+		radeon_bo_decref(rscreen->rw, bo);
+		return -ENOMEM;
+	}
+	memcpy(bo->data, vbo, 128);
+	radeon_bo_unmap(rscreen->rw, bo);
+
+	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
+	if (rstate == NULL) {
+		radeon_bo_decref(rscreen->rw, bo);
+		return -ENOMEM;
+	}
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
+	rstate->bo[0] = bo;
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return -ENOMEM;
+	}
+	bstates->vs_resource0 = rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
+	if (rstate == NULL) {
+		return -ENOMEM;
+	}
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return -ENOMEM;
+	}
+	bstates->vs_resource1 = rstate;
+
+	return 0;
+}
+
+static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+	struct radeon_bo *bo;
+	u32 shader_bc[] = {
+		0x00000004, 0x81000400,
+		0x00000008, 0xA01C0000,
+		0xC001A03C, 0x94000688,
+		0xC0024000, 0x94200688,
+		0x7C000000, 0x002D1001,
+		0x00080000, 0x00000000,
+		0x7C000100, 0x002D1002,
+		0x00080000, 0x00000000,
+		0x00000001, 0x00601910,
+		0x00000401, 0x20601910,
+		0x00000801, 0x40601910,
+		0x80000C01, 0x60601910,
+		0x00000002, 0x00801910,
+		0x00000402, 0x20801910,
+		0x00000802, 0x40801910,
+		0x80000C02, 0x60801910
+	};
+
+	/* simple shader */
+	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
+	if (bo == NULL) {
+		return NULL;
+	}
+	if (radeon_bo_map(rscreen->rw, bo)) {
+		radeon_bo_decref(rscreen->rw, bo);
+		return NULL;
+	}
+	memcpy(bo->data, shader_bc, 128);
+	radeon_bo_unmap(rscreen->rw, bo);
+
+	rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
+	if (rstate == NULL) {
+		radeon_bo_decref(rscreen->rw, bo);
+		return NULL;
+	}
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_0] = 0x03020100;
+	rstate->states[R600_VS_SHADER__SPI_VS_OUT_ID_1] = 0x07060504;
+	rstate->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = 0x00000005;
+
+	rstate->bo[0] = bo;
+	rstate->bo[1] = radeon_bo_incref(rscreen->rw, bo);
+	rstate->nbo = 2;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+	struct radeon_bo *bo;
+	u32 shader_bc[] = {
+		0x00000002, 0xA00C0000,
+		0xC0008000, 0x94200688,
+		0x00000000, 0x00201910,
+		0x00000400, 0x20201910,
+		0x00000800, 0x40201910,
+		0x80000C00, 0x60201910
+	};
+
+	/* simple shader */
+	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
+	if (bo == NULL) {
+		radeon_bo_decref(rscreen->rw, bo);
+		return NULL;
+	}
+	if (radeon_bo_map(rscreen->rw, bo)) {
+		return NULL;
+	}
+	memcpy(bo->data, shader_bc, 48);
+	radeon_bo_unmap(rscreen->rw, bo);
+
+	rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
+	if (rstate == NULL) {
+		radeon_bo_decref(rscreen->rw, bo);
+		return NULL;
+	}
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_PS_SHADER__SPI_PS_INPUT_CNTL_0] = 0x00000C00;
+	rstate->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = 0x10000001;
+	rstate->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = 0x00000002;
+	rstate->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = 0x00000002;
+
+	rstate->bo[0] = bo;
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+	rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002;
+	rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscreen,
+					unsigned id, float c0, float c1,
+					float c2, float c3)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256] = fui(c0);
+	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256] = fui(c1);
+	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2);
+	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3);
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ] = 0x3F800000;
+	rstate->states[R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ] = 0x3F800000;
+	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ] = 0x3F800000;
+	rstate->states[R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ] = 0x3F800000;
+	rstate->states[R600_RASTERIZER__PA_SC_LINE_CNTL] = 0x00000400;
+	rstate->states[R600_RASTERIZER__PA_SC_LINE_STIPPLE] = 0x00000005;
+	rstate->states[R600_RASTERIZER__PA_SU_LINE_CNTL] = 0x00000008;
+	rstate->states[R600_RASTERIZER__PA_SU_POINT_MINMAX] = 0x80000000;
+	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004;
+	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
+	rstate->states[R600_DSA__DB_DEPTH_CLEAR] = 0x3F800000;
+	rstate->states[R600_DSA__DB_RENDER_CONTROL] = 0x00000060;
+	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
+	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_viewport(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = 0x42FA0000;
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = 0x42FA0000;
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = 0x42FA0000;
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = 0xC2FA0000;
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
+	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
+	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
+	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = 0x00CC0080;
+	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
+	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
+	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	int r;
+
+	bstates->ps_shader = r600_blit_state_ps_shader(rscreen);
+	if (bstates->ps_shader == NULL) {
+		R600_ERR("failed creating ps_shader state\n");
+		return -ENOMEM;
+	}
+	bstates->vs_shader = r600_blit_state_vs_shader(rscreen);
+	if (bstates->vs_shader == NULL) {
+		R600_ERR("failed creating vs_shader state\n");
+		return -ENOMEM;
+	}
+	bstates->vgt = r600_blit_state_vgt(rscreen);
+	if (bstates->vgt == NULL) {
+		R600_ERR("failed creating vgt state\n");
+		return -ENOMEM;
+	}
+	bstates->draw = r600_blit_state_draw(rscreen);
+	if (bstates->draw == NULL) {
+		R600_ERR("failed creating draw state\n");
+		return -ENOMEM;
+	}
+	bstates->vs_constant0 = r600_blit_state_vs_constant(rscreen, 0, 1.0, 0.0, 0.0, 0.0);
+	if (bstates->vs_constant0 == NULL) {
+		R600_ERR("failed creating vs_constant0 state\n");
+		return -ENOMEM;
+	}
+	bstates->vs_constant1 = r600_blit_state_vs_constant(rscreen, 1, 0.0, 1.0, 0.0, 0.0);
+	if (bstates->vs_constant1 == NULL) {
+		R600_ERR("failed creating vs_constant1 state\n");
+		return -ENOMEM;
+	}
+	bstates->vs_constant2 = r600_blit_state_vs_constant(rscreen, 2, 0.0, 0.0, -0.00199900055, 0.0);
+	if (bstates->vs_constant2 == NULL) {
+		R600_ERR("failed creating vs_constant2 state\n");
+		return -ENOMEM;
+	}
+	bstates->vs_constant3 = r600_blit_state_vs_constant(rscreen, 3, 0.0, 0.0, -0.99900049, 1.0);
+	if (bstates->vs_constant3 == NULL) {
+		R600_ERR("failed creating vs_constant3 state\n");
+		return -ENOMEM;
+	}
+	bstates->rasterizer = r600_blit_state_rasterizer(rscreen);
+	if (bstates->rasterizer == NULL) {
+		R600_ERR("failed creating rasterizer state\n");
+		return -ENOMEM;
+	}
+	bstates->dsa = r600_blit_state_dsa(rscreen);
+	if (bstates->dsa == NULL) {
+		R600_ERR("failed creating dsa state\n");
+		return -ENOMEM;
+	}
+	bstates->blend = r600_blit_state_blend(rscreen);
+	if (bstates->blend == NULL) {
+		R600_ERR("failed creating blend state\n");
+		return -ENOMEM;
+	}
+	bstates->viewport = r600_blit_state_viewport(rscreen);
+	if (bstates->viewport == NULL) {
+		R600_ERR("failed creating viewport state\n");
+		return -ENOMEM;
+	}
+	bstates->cb_cntl = r600_blit_state_cb_cntl(rscreen);
+	if (bstates->cb_cntl == NULL) {
+		R600_ERR("failed creating cb_cntl state\n");
+		return -ENOMEM;
+	}
+	r = r600_blit_state_vs_resources(rscreen, bstates);
+	if (r) {
+		R600_ERR("failed creating vs_resource state\n");
+		return r;
+	}
+	bstates->config = radeon_state_incref(rctx->hw_states.config);
+	return 0;
+}
+
+static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates)
+{
+	radeon_state_decref(bstates->rasterizer);
+	radeon_state_decref(bstates->dsa);
+	radeon_state_decref(bstates->blend);
+	radeon_state_decref(bstates->viewport);
+	radeon_state_decref(bstates->cb_cntl);
+	radeon_state_decref(bstates->config);
+	radeon_state_decref(bstates->vgt);
+	radeon_state_decref(bstates->draw);
+	radeon_state_decref(bstates->vs_constant0);
+	radeon_state_decref(bstates->vs_constant1);
+	radeon_state_decref(bstates->vs_constant2);
+	radeon_state_decref(bstates->vs_constant3);
+	radeon_state_decref(bstates->ps_shader);
+	radeon_state_decref(bstates->vs_shader);
+	radeon_state_decref(bstates->vs_resource0);
+	radeon_state_decref(bstates->vs_resource1);
+}
+
+int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_context *rctx = r600_context(ctx);
+	struct radeon_draw *draw = NULL;
+	struct r600_blit_states bstates;
+	int r;
+
+	r = r600_texture_scissor(ctx, rtexture, level);
+	if (r) {
+		return r;
+	}
+	r = r600_texture_cb0(ctx, rtexture, level);
+	if (r) {
+		return r;
+	}
+	r = r600_texture_db(ctx, rtexture, level);
+	if (r) {
+		return r;
+	}
+
+	r = r600_blit_states_init(ctx, &bstates);
+	if (r) {
+		return r;
+	}
+	bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x000000EC;
+	bstates.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
+	/* force rebuild */
+	bstates.dsa->cpm4 = bstates.cb_cntl->cpm4 = 0;
+	if (radeon_state_pm4(bstates.dsa)) {
+		goto out;
+	}
+	if (radeon_state_pm4(bstates.cb_cntl)) {
+		goto out;
+	}
+
+	draw = radeon_draw(rscreen->rw);
+	if (draw == NULL) {
+		R600_ERR("failed creating draw for uncompressing textures\n");
+		goto out;
+	}
+
+	r = radeon_draw_set(draw, bstates.vs_shader);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.ps_shader);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.rasterizer);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.dsa);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.blend);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.viewport);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.cb_cntl);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.config);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.vgt);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.draw);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.vs_resource0);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.vs_resource1);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.vs_constant0);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.vs_constant1);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.vs_constant2);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, bstates.vs_constant3);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, rtexture->scissor[level]);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, rtexture->cb0[level]);
+	if (r) {
+		goto out;
+	}
+	r = radeon_draw_set(draw, rtexture->db[level]);
+	if (r) {
+		goto out;
+	}
+
+	/* suspend queries */
+	r600_queries_suspend(ctx);
+
+	/* schedule draw*/
+	r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+	if (r == -EBUSY) {
+		r600_flush(ctx, 0, NULL);
+		r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+	}
+	if (r) {
+		goto out;
+	}
+
+	/* resume queries */
+	r600_queries_resume(ctx);
+
+out:
+	r600_blit_states_destroy(ctx, &bstates);
+	return r;
+}
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index 900aa9fd0c..d96d5b513f 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -186,7 +186,7 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state *
 void r600_flush(struct pipe_context *ctx, unsigned flags,
 			struct pipe_fence_handle **fence);
 
-int r600_context_hw_states(struct r600_context *rctx);
+int r600_context_hw_states(struct pipe_context *ctx);
 
 void r600_draw_vbo(struct pipe_context *ctx,
                    const struct pipe_draw_info *info);
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index f058455162..1eb868c4c7 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -58,7 +58,7 @@ static int r600_draw_common(struct r600_draw *draw)
 	struct pipe_vertex_buffer *vertex_buffer;
 	int r;
 
-	r = r600_context_hw_states(rctx);
+	r = r600_context_hw_states(draw->ctx);
 	if (r)
 		return r;
 	switch (draw->index_size) {
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 5ebda027e9..5b3a7027a7 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -44,6 +44,8 @@ struct r600_resource_texture {
 	struct r600_resource		resource;
 	unsigned long			offset[PIPE_MAX_TEXTURE_LEVELS];
 	unsigned long			pitch[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			width[PIPE_MAX_TEXTURE_LEVELS];
+	unsigned long			height[PIPE_MAX_TEXTURE_LEVELS];
 	unsigned long			layer_size[PIPE_MAX_TEXTURE_LEVELS];
 	unsigned long			pitch_override;
 	unsigned long			bpt;
@@ -51,6 +53,12 @@ struct r600_resource_texture {
 	unsigned			tilled;
 	unsigned			array_mode;
 	unsigned			tile_type;
+	unsigned			depth;
+	unsigned			dirty;
+	struct radeon_bo		*uncompressed;
+	struct radeon_state		*scissor[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		*cb0[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		*db[PIPE_MAX_TEXTURE_LEVELS];
 };
 
 void r600_init_context_resource_functions(struct r600_context *r600);
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 147be3c4ac..4b2aac73ac 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -30,6 +30,7 @@
 #include <radeon_drm.h>
 #include "radeon.h"
 #include "util/u_transfer.h"
+#include "r600_resource.h"
 
 /* Texture transfer. */
 struct r600_transfer {
@@ -63,7 +64,7 @@ unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
 struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
 					      struct winsys_handle *whandle);
 
-/* Texture transfer functions. */
+/* r600_texture.c texture transfer functions. */
 struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 						struct pipe_resource *texture,
 						struct pipe_subresource sr,
@@ -75,7 +76,13 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 				struct pipe_transfer* transfer);
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 				 struct pipe_transfer* transfer);
+int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
+int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
+int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
+int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 
+/* r600_blit.c */
+int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 
 /* helpers */
 int r600_conv_pipe_format(unsigned pformat, unsigned *format);
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 79fc04a9fe..5cdbe2bfe8 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -150,6 +150,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
 	rpshader->rstate->nbo = 2;
 	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e9b03f571a..58df32818e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -776,7 +776,9 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	rtex->tilled = 1;
 	rtex->array_mode = 2;
 	rtex->tile_type = 1;
+	rtex->depth = 1;
 	rbuffer = &rtex->resource;
+R600_ERR("DB handle %d   %p  %d\n", rbuffer->bo->handle, rtex, state->zsbuf->texture->format);
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
@@ -785,7 +787,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
 	format = r600_translate_dbformat(state->zsbuf->texture->format);
 	rstate->states[R600_DB__DB_DEPTH_BASE] = rtex->offset[level] >> 8;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = 0x00010000 |
+	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
 					S_028010_FORMAT(format);
 	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
 	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
@@ -1214,10 +1216,11 @@ static inline unsigned r600_tex_dim(unsigned dim)
 	}
 }
 
-static struct radeon_state *r600_resource(struct r600_context *rctx,
+static struct radeon_state *r600_resource(struct pipe_context *ctx,
 					const struct pipe_sampler_view *view,
 					unsigned id)
 {
+	struct r600_context *rctx = r600_context(ctx);
 	struct r600_screen *rscreen = rctx->screen;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
@@ -1225,7 +1228,8 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	struct radeon_state *rstate;
 	unsigned format;
 	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
-	unsigned char swizzle[4];
+	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
+	int r;
 
 	swizzle[0] = view->swizzle_r;
 	swizzle[1] = view->swizzle_g;
@@ -1247,8 +1251,23 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	}
 	tmp = (struct r600_resource_texture*)view->texture;
 	rbuffer = &tmp->resource;
-	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	if (tmp->depth) {
+		r = r600_texture_from_depth(ctx, tmp, view->first_level);
+		if (r) {
+			return NULL;
+		}
+format = r600_translate_colorformat(view->texture->format);
+R600_ERR("DEPTH TEXTURE %d rtex %p %d 0x%02X\n", tmp->uncompressed->handle, tmp, view->texture->format, format);
+format = 17;
+		rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+		rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
+//		array_mode = tmp->array_mode;
+//		tile_type = tmp->tile_type;
+	} else {
+R600_ERR("NOT DEPTH TEXTURE\n");
+		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	}
 	rstate->nbo = 2;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
@@ -1261,8 +1280,8 @@ static struct radeon_state *r600_resource(struct r600_context *rctx,
 	/* FIXME properly handle first level != 0 */
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
-			S_038000_TILE_MODE(tmp->array_mode) |
-			S_038000_TILE_TYPE(tmp->tile_type) |
+			S_038000_TILE_MODE(array_mode) |
+			S_038000_TILE_TYPE(tile_type) |
 			S_038000_PITCH((pitch / 8) - 1) |
 			S_038000_TEX_WIDTH(view->texture->width0 - 1);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
@@ -1347,8 +1366,9 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	return rstate;
 }
 
-int r600_context_hw_states(struct r600_context *rctx)
+int r600_context_hw_states(struct pipe_context *ctx)
 {
+	struct r600_context *rctx = r600_context(ctx);
 	unsigned i;
 	int r;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
@@ -1410,7 +1430,7 @@ int r600_context_hw_states(struct r600_context *rctx)
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			rctx->hw_states.ps_resource[i] = r600_resource(rctx,
+			rctx->hw_states.ps_resource[i] = r600_resource(ctx,
 							&rctx->ps_sampler_view[i]->state.sampler_view,
 							R600_PS_RESOURCE + i);
 		}
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 92b4f430c5..c79dd34f09 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -24,6 +24,7 @@
  *      Jerome Glisse
  *      Corbin Simpson
  */
+#include <errno.h>
 #include <pipe/p_screen.h>
 #include <util/u_format.h>
 #include <util/u_math.h>
@@ -33,6 +34,7 @@
 #include "r600_screen.h"
 #include "r600_context.h"
 #include "r600_resource.h"
+#include "r600_state_inlines.h"
 #include "r600d.h"
 
 extern struct u_resource_vtbl r600_texture_vtbl;
@@ -91,6 +93,8 @@ static void r600_setup_miptree(struct r600_screen *rscreen, struct r600_resource
 		rtex->offset[i] = offset;
 		rtex->layer_size[i] = layer_size;
 		rtex->pitch[i] = pitch;
+		rtex->width[i] = w;
+		rtex->height[i] = h;
 		offset += size;
 	}
 	rtex->size = offset;
@@ -130,10 +134,19 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
 	struct r600_screen *rscreen = r600_screen(screen);
+	unsigned i;
 
 	if (resource->bo) {
 		radeon_bo_decref(rscreen->rw, resource->bo);
 	}
+	if (rtex->uncompressed) {
+		radeon_bo_decref(rscreen->rw, rtex->uncompressed);
+	}
+	for (i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
+		radeon_state_decref(rtex->scissor[i]);
+		radeon_state_decref(rtex->cb0[i]);
+		radeon_state_decref(rtex->db[i]);
+	}
 	FREE(rtex);
 }
 
@@ -595,3 +608,218 @@ out_unknown:
 	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
 	return ~0;
 }
+
+int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	int r;
+
+	if (!rtexture->depth) {
+		/* This shouldn't happen maybe print a warning */
+		return 0;
+	}
+	if (rtexture->uncompressed && !rtexture->dirty) {
+		/* Uncompressed bo already in good state */
+		return 0;
+	}
+
+	/* allocate uncompressed texture */
+	if (rtexture->uncompressed == NULL) {
+		rtexture->uncompressed = radeon_bo(rscreen->rw, 0, rtexture->size, 4096, NULL);
+		if (rtexture->uncompressed == NULL) {
+			return -ENOMEM;
+		}
+	}
+
+	/* render a rectangle covering whole buffer to uncompress depth */
+	r = r600_blit_uncompress_depth(ctx, rtexture, level);
+R600_ERR("---step0 %d\n", r);
+	if (r) {
+		return r;
+	}
+
+	rtexture->dirty = 0;
+	return 0;
+}
+
+static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscreen,
+					struct r600_resource_texture *rtexture,
+					unsigned level)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_0_TL] = 0x80000000;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_1_TL] = 0x80000000;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_2_TL] = 0x80000000;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_3_TL] = 0x80000000;
+	rstate->states[R600_SCISSOR__PA_SC_CLIPRECT_RULE] = 0x0000FFFF;
+	rstate->states[R600_SCISSOR__PA_SC_EDGERULE] = 0xAAAAAAAA;
+	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL] = 0x80000000;
+	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = 0x80000000;
+	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = 0x80000000;
+	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
+	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
+				struct r600_resource_texture *rtexture,
+				unsigned level)
+{
+	struct radeon_state *rstate;
+	struct r600_resource *rbuffer;
+	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+
+	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
+	if (rstate == NULL)
+		return NULL;
+	rbuffer = &rtexture->resource;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
+	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
+	ntype = 0;
+	desc = util_format_description(rbuffer->base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_0280A0_NUMBER_SRGB;
+	format = r600_translate_colorformat(rtexture->resource.base.b.format);
+	swap = r600_translate_colorswap(rtexture->resource.base.b.format);
+	color_info = S_0280A0_FORMAT(format) |
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
+R600_ERR("CB0 uncompressed texture %p (handle)%d %d 0x%02X\n", rtexture, rtexture->uncompressed->handle, rtexture->resource.base.b.format, format);
+format = 17;
+		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+		rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
+		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+		rstate->nbo = 3;
+	} else {
+		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+		rstate->nbo = 3;
+		color_info |= S_0280A0_SOURCE_FORMAT(1);
+	}
+	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
+	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+						S_028060_SLICE_TILE_MAX(slice);
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
+				struct r600_resource_texture *rtexture,
+				unsigned level)
+{
+	struct radeon_state *rstate;
+	struct r600_resource *rbuffer;
+	unsigned pitch, slice, format;
+
+	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	if (rstate == NULL)
+		return NULL;
+	rbuffer = &rtexture->resource;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	pitch = (rtexture->pitch[level] / rtexture->bpt) / 8 - 1;
+	slice = (rtexture->pitch[level] / rtexture->bpt) * rtexture->height[level] / 64 - 1;
+	format = r600_translate_dbformat(rbuffer->base.b.format);
+	rstate->states[R600_DB__DB_DEPTH_BASE] = rtexture->offset[level] >> 8;
+	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtexture->array_mode) |
+					S_028010_FORMAT(format);
+	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
+	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
+	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
+						S_028000_SLICE_TILE_MAX(slice);
+R600_ERR("DB handle %d  %p %d\n", rbuffer->bo->handle, rtexture, rbuffer->base.b.format);
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->nbo = 1;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
+int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+
+	if (rtexture->scissor[level] == NULL) {
+		rtexture->scissor[level] = r600_texture_state_scissor(rscreen, rtexture, level);
+		if (rtexture->scissor[level] == NULL) {
+			R600_ERR("failed to create scissor for uncompressing depth\n");
+			return -ENOMEM;
+		}
+	}
+	return 0;
+}
+
+int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+
+	if (rtexture->cb0[level] == NULL) {
+		rtexture->cb0[level] = r600_texture_state_cb0(rscreen, rtexture, level);
+		if (rtexture->cb0[level] == NULL) {
+			R600_ERR("failed to create cb0 state for texture\n");
+			return -ENOMEM;
+		}
+	}
+	return 0;
+}
+
+int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+
+	if (rtexture->db[level] == NULL) {
+		rtexture->db[level] = r600_texture_state_db(rscreen, rtexture, level);
+		if (rtexture->db[level] == NULL) {
+			R600_ERR("failed to create db state for texture\n");
+			return -ENOMEM;
+		}
+	}
+	return 0;
+}
-- 
cgit v1.2.3


From 47537a4557c8a264f1e0eb308aff07464c81e0ca Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 15:48:41 +0200
Subject: nvfx: move stuff around

---
 src/gallium/drivers/nvfx/nvfx_context.c  |  2 +
 src/gallium/drivers/nvfx/nvfx_context.h  |  5 +-
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 42 ++++++++++++++++
 src/gallium/drivers/nvfx/nvfx_state.c    | 82 --------------------------------
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 48 +++++++++++++++++++
 5 files changed, 95 insertions(+), 84 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index e78fc14da4..99ad7bfacf 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -77,6 +77,8 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	nvfx_init_state_functions(nvfx);
 	nvfx_init_sampling_functions(nvfx);
 	nvfx_init_vbo_functions(nvfx);
+	nvfx_init_fragprog_functions(nvfx);
+	nvfx_init_vertprog_functions(nvfx);
 	nvfx_init_resource_functions(&nvfx->pipe);
 	nvfx_init_transfer_functions(&nvfx->pipe);
 
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index fb4a9da579..02e8ed0178 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -244,8 +244,8 @@ nvfx_framebuffer_relocate(struct nvfx_context *nvfx);
 extern void nvfx_fragprog_destroy(struct nvfx_context *,
 				    struct nvfx_fragment_program *);
 extern void nvfx_fragprog_validate(struct nvfx_context *nvfx);
-extern void
-nvfx_fragprog_relocate(struct nvfx_context *nvfx);
+extern void nvfx_fragprog_relocate(struct nvfx_context *nvfx);
+extern void nvfx_init_fragprog_functions(struct nvfx_context *nvfx);
 
 /* nvfx_fragtex.c */
 extern void nvfx_init_sampling_functions(struct nvfx_context *nvfx);
@@ -308,6 +308,7 @@ extern unsigned nvfx_vertex_formats[];
 extern boolean nvfx_vertprog_validate(struct nvfx_context *nvfx);
 extern void nvfx_vertprog_destroy(struct nvfx_context *,
 				  struct nvfx_vertex_program *);
+extern void nvfx_init_vertprog_functions(struct nvfx_context *nvfx);
 
 /* nvfx_push.c */
 extern void nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info);
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index e40a814e18..e0e31e4689 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -1428,3 +1428,45 @@ nvfx_fragprog_destroy(struct nvfx_context *nvfx,
 	if (fp->insn_len)
 		FREE(fp->insn);
 }
+
+static void *
+nvfx_fp_state_create(struct pipe_context *pipe,
+                     const struct pipe_shader_state *cso)
+{
+        struct nvfx_fragment_program *fp;
+
+        fp = CALLOC(1, sizeof(struct nvfx_fragment_program));
+        fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
+
+        tgsi_scan_shader(fp->pipe.tokens, &fp->info);
+
+        return (void *)fp;
+}
+
+static void
+nvfx_fp_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+        struct nvfx_context *nvfx = nvfx_context(pipe);
+
+        nvfx->fragprog = hwcso;
+        nvfx->dirty |= NVFX_NEW_FRAGPROG;
+}
+
+static void
+nvfx_fp_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+        struct nvfx_context *nvfx = nvfx_context(pipe);
+        struct nvfx_fragment_program *fp = hwcso;
+
+        nvfx_fragprog_destroy(nvfx, fp);
+        FREE((void*)fp->pipe.tokens);
+        FREE(fp);
+}
+
+void
+nvfx_init_fragprog_functions(struct nvfx_context *nvfx)
+{
+        nvfx->pipe.create_fs_state = nvfx_fp_state_create;
+        nvfx->pipe.bind_fs_state = nvfx_fp_state_bind;
+        nvfx->pipe.delete_fs_state = nvfx_fp_state_delete;
+}
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index e3c3fcb7d5..cb32e503c8 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -260,80 +260,6 @@ nvfx_depth_stencil_alpha_state_delete(struct pipe_context *pipe, void *hwcso)
 	FREE(zsaso);
 }
 
-static void *
-nvfx_vp_state_create(struct pipe_context *pipe,
-		     const struct pipe_shader_state *cso)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nvfx_vertex_program *vp;
-
-	// TODO: use a 64-bit atomic here!
-	static unsigned long long id = 0;
-
-	vp = CALLOC(1, sizeof(struct nvfx_vertex_program));
-	vp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
-	vp->draw = draw_create_vertex_shader(nvfx->draw, &vp->pipe);
-	vp->id = ++id;
-
-	return (void *)vp;
-}
-
-static void
-nvfx_vp_state_bind(struct pipe_context *pipe, void *hwcso)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-
-	nvfx->vertprog = hwcso;
-	nvfx->dirty |= NVFX_NEW_VERTPROG;
-	nvfx->draw_dirty |= NVFX_NEW_VERTPROG;
-}
-
-static void
-nvfx_vp_state_delete(struct pipe_context *pipe, void *hwcso)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nvfx_vertex_program *vp = hwcso;
-
-	draw_delete_vertex_shader(nvfx->draw, vp->draw);
-	nvfx_vertprog_destroy(nvfx, vp);
-	FREE((void*)vp->pipe.tokens);
-	FREE(vp);
-}
-
-static void *
-nvfx_fp_state_create(struct pipe_context *pipe,
-		     const struct pipe_shader_state *cso)
-{
-	struct nvfx_fragment_program *fp;
-
-	fp = CALLOC(1, sizeof(struct nvfx_fragment_program));
-	fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
-
-	tgsi_scan_shader(fp->pipe.tokens, &fp->info);
-
-	return (void *)fp;
-}
-
-static void
-nvfx_fp_state_bind(struct pipe_context *pipe, void *hwcso)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-
-	nvfx->fragprog = hwcso;
-	nvfx->dirty |= NVFX_NEW_FRAGPROG;
-}
-
-static void
-nvfx_fp_state_delete(struct pipe_context *pipe, void *hwcso)
-{
-	struct nvfx_context *nvfx = nvfx_context(pipe);
-	struct nvfx_fragment_program *fp = hwcso;
-
-	nvfx_fragprog_destroy(nvfx, fp);
-	FREE((void*)fp->pipe.tokens);
-	FREE(fp);
-}
-
 static void
 nvfx_set_blend_color(struct pipe_context *pipe,
 		     const struct pipe_blend_color *bcol)
@@ -450,14 +376,6 @@ nvfx_init_state_functions(struct nvfx_context *nvfx)
 	nvfx->pipe.delete_depth_stencil_alpha_state =
 		nvfx_depth_stencil_alpha_state_delete;
 
-	nvfx->pipe.create_vs_state = nvfx_vp_state_create;
-	nvfx->pipe.bind_vs_state = nvfx_vp_state_bind;
-	nvfx->pipe.delete_vs_state = nvfx_vp_state_delete;
-
-	nvfx->pipe.create_fs_state = nvfx_fp_state_create;
-	nvfx->pipe.bind_fs_state = nvfx_fp_state_bind;
-	nvfx->pipe.delete_fs_state = nvfx_fp_state_delete;
-
 	nvfx->pipe.set_blend_color = nvfx_set_blend_color;
         nvfx->pipe.set_stencil_ref = nvfx_set_stencil_ref;
 	nvfx->pipe.set_clip_state = nvfx_set_clip_state;
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 806f263dcf..f8f1af9816 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -1260,3 +1260,51 @@ nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
 	util_dynarray_fini(&vp->branch_relocs);
 	util_dynarray_fini(&vp->const_relocs);
 }
+
+static void *
+nvfx_vp_state_create(struct pipe_context *pipe,
+                     const struct pipe_shader_state *cso)
+{
+        struct nvfx_context *nvfx = nvfx_context(pipe);
+        struct nvfx_vertex_program *vp;
+
+        // TODO: use a 64-bit atomic here!
+        static unsigned long long id = 0;
+
+        vp = CALLOC(1, sizeof(struct nvfx_vertex_program));
+        vp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
+        vp->draw = draw_create_vertex_shader(nvfx->draw, &vp->pipe);
+        vp->id = ++id;
+
+        return (void *)vp;
+}
+
+static void
+nvfx_vp_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+        struct nvfx_context *nvfx = nvfx_context(pipe);
+
+        nvfx->vertprog = hwcso;
+        nvfx->dirty |= NVFX_NEW_VERTPROG;
+        nvfx->draw_dirty |= NVFX_NEW_VERTPROG;
+}
+
+static void
+nvfx_vp_state_delete(struct pipe_context *pipe, void *hwcso)
+{
+        struct nvfx_context *nvfx = nvfx_context(pipe);
+        struct nvfx_vertex_program *vp = hwcso;
+
+        draw_delete_vertex_shader(nvfx->draw, vp->draw);
+        nvfx_vertprog_destroy(nvfx, vp);
+        FREE((void*)vp->pipe.tokens);
+        FREE(vp);
+}
+
+void
+nvfx_init_vertprog_functions(struct nvfx_context *nvfx)
+{
+        nvfx->pipe.create_vs_state = nvfx_vp_state_create;
+        nvfx->pipe.bind_vs_state = nvfx_vp_state_bind;
+        nvfx->pipe.delete_vs_state = nvfx_vp_state_delete;
+}
-- 
cgit v1.2.3


From df86f1e7d50e01b92e03dc25fa9e9258d2d4fa2f Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 16:15:51 +0200
Subject: nvfx: refactor to support multiple fragment program versions

---
 src/gallium/drivers/nvfx/nvfx_context.c  |   4 +
 src/gallium/drivers/nvfx/nvfx_context.h  |   5 +-
 src/gallium/drivers/nvfx/nvfx_draw.c     |  10 +-
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 174 +++++++++++++++++++------------
 src/gallium/drivers/nvfx/nvfx_state.h    |  10 +-
 5 files changed, 127 insertions(+), 76 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 99ad7bfacf..80b36fb7b9 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -33,6 +33,9 @@ nvfx_destroy(struct pipe_context *pipe)
 {
 	struct nvfx_context *nvfx = nvfx_context(pipe);
 
+	if(nvfx->dummy_fs)
+		pipe->delete_fs_state(pipe, nvfx->dummy_fs);
+
 	for(unsigned i = 0; i < nvfx->vtxbuf_nr; ++i)
 		pipe_resource_reference(&nvfx->vtxbuf[i].buffer, 0);
 	pipe_resource_reference(&nvfx->idxbuf.buffer, 0);
@@ -42,6 +45,7 @@ nvfx_destroy(struct pipe_context *pipe)
 
 	if (nvfx->draw)
 		draw_destroy(nvfx->draw);
+
 	FREE(nvfx);
 }
 
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 02e8ed0178..2134f3c386 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -161,7 +161,7 @@ struct nvfx_context {
 	unsigned stipple[32];
 	struct pipe_clip_state clip;
 	struct nvfx_vertex_program *vertprog;
-	struct nvfx_fragment_program *fragprog;
+	struct nvfx_pipe_fragment_program *fragprog;
 	struct pipe_resource *constbuf[PIPE_SHADER_TYPES];
 	unsigned constbuf_nr[PIPE_SHADER_TYPES];
 	struct nvfx_rasterizer_state *rasterizer;
@@ -174,6 +174,8 @@ struct nvfx_context {
 	struct pipe_index_buffer idxbuf;
 	struct nvfx_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
 	struct pipe_sampler_view *fragment_sampler_views[PIPE_MAX_SAMPLERS];
+	struct nvfx_pipe_fragment_program* dummy_fs;
+
 	unsigned nr_samplers;
 	unsigned nr_textures;
 	unsigned dirty_samplers;
@@ -195,6 +197,7 @@ struct nvfx_context {
 	struct nvfx_render_target hw_zeta;
 	int hw_pointsprite_control;
 	int hw_vp_output;
+	struct nvfx_fragment_program* hw_fragprog;
 };
 
 static INLINE struct nvfx_context *
diff --git a/src/gallium/drivers/nvfx/nvfx_draw.c b/src/gallium/drivers/nvfx/nvfx_draw.c
index 331e28418a..0b17921295 100644
--- a/src/gallium/drivers/nvfx/nvfx_draw.c
+++ b/src/gallium/drivers/nvfx/nvfx_draw.c
@@ -274,19 +274,19 @@ emit_attrib(struct nvfx_context *nvfx, unsigned hw, unsigned emit,
 void
 nvfx_vtxfmt_validate(struct nvfx_context *nvfx)
 {
-	struct nvfx_fragment_program *fp = nvfx->fragprog;
+	struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
 	unsigned colour = 0, texcoords = 0, fog = 0, i;
 
 	/* Determine needed fragprog inputs */
-	for (i = 0; i < fp->info.num_inputs; i++) {
-		switch (fp->info.input_semantic_name[i]) {
+	for (i = 0; i < pfp->info.num_inputs; i++) {
+		switch (pfp->info.input_semantic_name[i]) {
 		case TGSI_SEMANTIC_POSITION:
 			break;
 		case TGSI_SEMANTIC_COLOR:
-			colour |= (1 << fp->info.input_semantic_index[i]);
+			colour |= (1 << pfp->info.input_semantic_index[i]);
 			break;
 		case TGSI_SEMANTIC_GENERIC:
-			texcoords |= (1 << fp->info.input_semantic_index[i]);
+			texcoords |= (1 << pfp->info.input_semantic_index[i]);
 			break;
 		case TGSI_SEMANTIC_FOG:
 			fog = 1;
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index e0e31e4689..c4394b25f3 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -8,6 +8,7 @@
 #include "tgsi/tgsi_parse.h"
 #include "tgsi/tgsi_util.h"
 #include "tgsi/tgsi_dump.h"
+#include "tgsi/tgsi_ureg.h"
 
 #include "nvfx_context.h"
 #include "nvfx_shader.h"
@@ -17,6 +18,7 @@
 #define MAX_IMM 32
 
 struct nvfx_fpc {
+	struct nvfx_pipe_fragment_program* pfp;
 	struct nvfx_fragment_program *fp;
 
 	unsigned r_temps;
@@ -379,27 +381,27 @@ tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
 
 	switch (fsrc->Register.File) {
 	case TGSI_FILE_INPUT:
-		if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
-			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
+		if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
+			assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
 			src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
-		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
-			if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0)
+		} else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
+			if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0)
 				src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
-			else if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 1)
+			else if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 1)
 				src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
 			else
 				assert(0);
-		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
-			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
+		} else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
+			assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
 			src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
-		} else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
+		} else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
 			/* TODO: check this has the correct values */
 			/* XXX: what do we do for nv30 here (assuming it lacks facing)?!  */
-			assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
+			assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
 			src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
 		} else {
-			assert(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
-			src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
+			assert(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
+			src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->pfp->info.input_semantic_index[fsrc->Register.Index]]);
 		}
 		break;
 	case TGSI_FILE_CONSTANT:
@@ -922,7 +924,7 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 	float const0v[4] = {0, 0, 0, 0};
 	struct nvfx_reg const0;
 
-	fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->fp->pipe.tokens, TGSI_FILE_INPUT);
+	fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->pfp->pipe.tokens, TGSI_FILE_INPUT);
 	if(fpc->fp->num_slots > 8)
 		return FALSE;
 	util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, 8);
@@ -933,7 +935,7 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 	const0 = constant(fpc, -1, const0v);
 	assert(const0.index == 0);
 
-	tgsi_parse_init(&p, fpc->fp->pipe.tokens);
+	tgsi_parse_init(&p, fpc->pfp->pipe.tokens);
 	while (!tgsi_parse_end_of_tokens(&p)) {
 		const union tgsi_full_token *tok = &p.FullToken;
 
@@ -999,26 +1001,32 @@ out_err:
 
 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
 
-static void
+static struct nvfx_fragment_program*
 nvfx_fragprog_translate(struct nvfx_context *nvfx,
-			struct nvfx_fragment_program *fp)
+			struct nvfx_pipe_fragment_program *pfp)
 {
 	struct tgsi_parse_context parse;
 	struct nvfx_fpc *fpc = NULL;
 	struct util_dynarray insns;
+	struct nvfx_fragment_program* fp = NULL;
+        const int min_size = 4096;
+
+	fp = CALLOC_STRUCT(nvfx_fragment_program);
+	if(!fp)
+		goto out_err;
 
-	fpc = CALLOC(1, sizeof(struct nvfx_fpc));
+	fpc = CALLOC_STRUCT(nvfx_fpc);
 	if (!fpc)
-		return;
+		goto out_err;
+
+	fpc->pfp = pfp;
 	fpc->fp = fp;
 	fpc->num_regs = 2;
 
-	if (!nvfx_fragprog_prepare(nvfx, fpc)) {
-		FREE(fpc);
-		return;
-	}
+	if (!nvfx_fragprog_prepare(nvfx, fpc))
+		goto out_err;
 
-	tgsi_parse_init(&parse, fp->pipe.tokens);
+	tgsi_parse_init(&parse, pfp->pipe.tokens);
 
 	util_dynarray_init(&insns);
 	while (!tgsi_parse_end_of_tokens(&parse)) {
@@ -1068,7 +1076,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 	if(debug_get_option_nvfx_dump_fp())
 	{
 		debug_printf("\n");
-		tgsi_dump(fp->pipe.tokens, 0);
+		tgsi_dump(pfp->pipe.tokens, 0);
 
 		debug_printf("\n%s fragment program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
 		for (unsigned i = 0; i < fp->insn_len; i += 4)
@@ -1076,15 +1084,37 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 		debug_printf("\n");
 	}
 
-	fp->translated = TRUE;
-out_err:
+        fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
+
+        if(fp->prog_size >= min_size)
+                fp->progs_per_bo = 1;
+        else
+                fp->progs_per_bo = min_size / fp->prog_size;
+        fp->bo_prog_idx = fp->progs_per_bo - 1;
+
+out:
 	tgsi_parse_free(&parse);
-	if (fpc->r_temp)
-		FREE(fpc->r_temp);
-	util_dynarray_fini(&fpc->if_stack);
-	util_dynarray_fini(&fpc->label_relocs);
-	//util_dynarray_fini(&fpc->loop_stack);
-	FREE(fpc);
+	if(fpc)
+	{
+		if (fpc->r_temp)
+			FREE(fpc->r_temp);
+		util_dynarray_fini(&fpc->if_stack);
+		util_dynarray_fini(&fpc->label_relocs);
+		//util_dynarray_fini(&fpc->loop_stack);
+		FREE(fpc);
+	}
+	return fp;
+
+out_err:
+	_debug_printf("Error: failed to compile this fragment program:\n");
+	tgsi_dump(pfp->pipe.tokens, 0);
+
+	if(fp)
+	{
+		FREE(fp);
+		fp = NULL;
+	}
+	goto out;
 }
 
 static inline void
@@ -1134,43 +1164,49 @@ void
 nvfx_fragprog_validate(struct nvfx_context *nvfx)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	struct nvfx_fragment_program *fp = nvfx->fragprog;
-	int update = 0;
+	struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
 	struct nvfx_vertex_program* vp;
 	unsigned sprite_coord_enable;
-	boolean update_pointsprite = !!(nvfx->dirty & NVFX_NEW_FRAGPROG);
+	unsigned key = 0;
+	struct nvfx_fragment_program* fp;
 
-	if (!fp->translated)
+	fp = pfp->fps[key];
+	if (!fp)
 	{
-		const int min_size = 4096;
+		fp = nvfx_fragprog_translate(nvfx, pfp);
 
-		nvfx_fragprog_translate(nvfx, fp);
-		if (!fp->translated) {
-			static unsigned dummy[8] = {1, 0, 0, 0, 1, 0, 0, 0};
-			static int warned = 0;
-			if(!warned)
+		if(!fp)
+		{
+			if(!nvfx->dummy_fs)
 			{
-				fprintf(stderr, "nvfx: failed to translate fragment program!\n");
-				warned = 1;
+				struct ureg_program *ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT );
+				if (ureg)
+				{
+					ureg_END( ureg );
+					nvfx->dummy_fs = ureg_create_shader_and_destroy( ureg, &nvfx->pipe );
+				}
+
+				if(!nvfx->dummy_fs)
+				{
+					_debug_printf("Error: unable to create a dummy fragment shader: aborting.");
+					abort();
+				}
 			}
 
-			/* use dummy program: we cannot fail here */
-			fp->translated = TRUE;
-			fp->insn = malloc(sizeof(dummy));
-			memcpy(fp->insn, dummy, sizeof(dummy));
-			fp->insn_len = sizeof(dummy) / sizeof(dummy[0]);
-		}
-		update = TRUE;
+			fp = nvfx_fragprog_translate(nvfx, nvfx->dummy_fs);
 
-		fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
+			if(!fp)
+			{
+				_debug_printf("Error: unable to compile even a dummy fragment shader: aborting.");
+				abort();
+			}
+		}
 
-		if(fp->prog_size >= min_size)
-			fp->progs_per_bo = 1;
-		else
-			fp->progs_per_bo = min_size / fp->prog_size;
-		fp->bo_prog_idx = fp->progs_per_bo - 1;
+		pfp->fps[key] = fp;
 	}
 
+	nvfx->hw_fragprog = fp;
+
 	vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
         sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
 
@@ -1391,7 +1427,7 @@ void
 nvfx_fragprog_relocate(struct nvfx_context *nvfx)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
-	struct nvfx_fragment_program *fp = nvfx->fragprog;
+	struct nvfx_fragment_program *fp = nvfx->hw_fragprog;
 	struct nouveau_bo* bo = fp->fpbo->bo;
 	int offset = fp->bo_prog_idx * fp->prog_size;
 	unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
@@ -1433,14 +1469,14 @@ static void *
 nvfx_fp_state_create(struct pipe_context *pipe,
                      const struct pipe_shader_state *cso)
 {
-        struct nvfx_fragment_program *fp;
+        struct nvfx_pipe_fragment_program *pfp;
 
-        fp = CALLOC(1, sizeof(struct nvfx_fragment_program));
-        fp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
+        pfp = CALLOC(1, sizeof(struct nvfx_pipe_fragment_program));
+        pfp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
 
-        tgsi_scan_shader(fp->pipe.tokens, &fp->info);
+        tgsi_scan_shader(pfp->pipe.tokens, &pfp->info);
 
-        return (void *)fp;
+        return (void *)pfp;
 }
 
 static void
@@ -1456,11 +1492,17 @@ static void
 nvfx_fp_state_delete(struct pipe_context *pipe, void *hwcso)
 {
         struct nvfx_context *nvfx = nvfx_context(pipe);
-        struct nvfx_fragment_program *fp = hwcso;
+        struct nvfx_pipe_fragment_program *pfp = hwcso;
+        unsigned i;
+
+        for(i = 0; i < Elements(pfp->fps); ++i)
+        {
+        	nvfx_fragprog_destroy(nvfx, pfp->fps[i]);
+        	FREE(pfp->fps[i]);
+        }
 
-        nvfx_fragprog_destroy(nvfx, fp);
-        FREE((void*)fp->pipe.tokens);
-        FREE(fp);
+        FREE((void*)pfp->pipe.tokens);
+        FREE(pfp);
 }
 
 void
diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
index 05d41cfc8d..fd2174ed69 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ b/src/gallium/drivers/nvfx/nvfx_state.h
@@ -61,10 +61,6 @@ struct nvfx_fragment_program_bo {
 };
 
 struct nvfx_fragment_program {
-	struct pipe_shader_state pipe;
-	struct tgsi_shader_info info;
-
-	boolean translated;
 	unsigned samplers;
 	unsigned point_sprite_control;
 	unsigned or;
@@ -99,5 +95,11 @@ struct nvfx_fragment_program {
 	struct nvfx_fragment_program_bo* fpbo;
 };
 
+struct nvfx_pipe_fragment_program {
+        struct pipe_shader_state pipe;
+        struct tgsi_shader_info info;
+
+        struct nvfx_fragment_program* fps[1];
+};
 
 #endif
-- 
cgit v1.2.3


From d324fcea67f8e3f3c371ec089c5d5106be06e160 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sun, 22 Aug 2010 12:45:04 -0700
Subject: nvfx: Include missing header in nvfx_vertprog.c.

Include draw_context.h for draw_*_vertex_shader symbols.

Fixes the following GCC warning.
nvfx_vertprog.c: In function 'nvfx_vp_state_create':
nvfx_vertprog.c:1276: warning: implicit declaration of function 'draw_create_vertex_shader'
nvfx_vertprog.c:1276: warning: assignment makes pointer from integer without a cast
nvfx_vertprog.c: In function 'nvfx_vp_state_delete':
nvfx_vertprog.c:1298: warning: implicit declaration of function 'draw_delete_vertex_shader'
---
 src/gallium/drivers/nvfx/nvfx_vertprog.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index f8f1af9816..3b8d3853b7 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -9,6 +9,8 @@
 #include "tgsi/tgsi_dump.h"
 #include "tgsi/tgsi_util.h"
 
+#include "draw/draw_context.h"
+
 #include "nvfx_context.h"
 #include "nvfx_state.h"
 #include "nvfx_resource.h"
-- 
cgit v1.2.3


From d843bbfd3f92d5afea665c3ff16bcca0628f2e7b Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Sun, 22 Aug 2010 17:13:58 -0400
Subject: r600g: fix DB decompression

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c          |  48 +++--------
 src/gallium/drivers/r600/r600_resource.h      |   1 +
 src/gallium/drivers/r600/r600_screen.h        |   1 +
 src/gallium/drivers/r600/r600_state.c         |  10 +--
 src/gallium/drivers/r600/r600_state_inlines.h |   2 +-
 src/gallium/drivers/r600/r600_texture.c       | 110 +++++++++++++++++++-------
 6 files changed, 97 insertions(+), 75 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 8cb2795d2b..1a975da4bd 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -149,7 +149,6 @@ struct r600_blit_states {
 	struct radeon_state	*rasterizer;
 	struct radeon_state	*dsa;
 	struct radeon_state	*blend;
-	struct radeon_state	*viewport;
 	struct radeon_state	*cb_cntl;
 	struct radeon_state	*config;
 	struct radeon_state	*vgt;
@@ -490,33 +489,6 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
 	return rstate;
 }
 
-static struct radeon_state *r600_blit_state_viewport(struct r600_screen *rscreen)
-{
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
-	if (rstate == NULL)
-		return NULL;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = 0x42FA0000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = 0x42FA0000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = 0x42FA0000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = 0xC2FA0000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
-	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
-	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
-
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
-}
-
 static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
@@ -604,11 +576,6 @@ static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_stat
 		R600_ERR("failed creating blend state\n");
 		return -ENOMEM;
 	}
-	bstates->viewport = r600_blit_state_viewport(rscreen);
-	if (bstates->viewport == NULL) {
-		R600_ERR("failed creating viewport state\n");
-		return -ENOMEM;
-	}
 	bstates->cb_cntl = r600_blit_state_cb_cntl(rscreen);
 	if (bstates->cb_cntl == NULL) {
 		R600_ERR("failed creating cb_cntl state\n");
@@ -628,7 +595,6 @@ static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_
 	radeon_state_decref(bstates->rasterizer);
 	radeon_state_decref(bstates->dsa);
 	radeon_state_decref(bstates->blend);
-	radeon_state_decref(bstates->viewport);
 	radeon_state_decref(bstates->cb_cntl);
 	radeon_state_decref(bstates->config);
 	radeon_state_decref(bstates->vgt);
@@ -663,12 +629,16 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		return r;
 	}
+	r = r600_texture_viewport(ctx, rtexture, level);
+	if (r) {
+		return r;
+	}
 
 	r = r600_blit_states_init(ctx, &bstates);
 	if (r) {
 		return r;
 	}
-	bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x000000EC;
+	bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
 	bstates.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
 	/* force rebuild */
 	bstates.dsa->cpm4 = bstates.cb_cntl->cpm4 = 0;
@@ -705,10 +675,6 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		goto out;
 	}
-	r = radeon_draw_set(draw, bstates.viewport);
-	if (r) {
-		goto out;
-	}
 	r = radeon_draw_set(draw, bstates.cb_cntl);
 	if (r) {
 		goto out;
@@ -749,6 +715,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		goto out;
 	}
+	r = radeon_draw_set(draw, rtexture->viewport[level]);
+	if (r) {
+		goto out;
+	}
 	r = radeon_draw_set(draw, rtexture->scissor[level]);
 	if (r) {
 		goto out;
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 5b3a7027a7..b880f9369c 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -59,6 +59,7 @@ struct r600_resource_texture {
 	struct radeon_state		*scissor[PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*cb0[PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*db[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		*viewport[PIPE_MAX_TEXTURE_LEVELS];
 };
 
 void r600_init_context_resource_functions(struct r600_context *r600);
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 4b2aac73ac..5e82ac8e23 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -80,6 +80,7 @@ int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture
 int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
+int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 
 /* r600_blit.c */
 int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 58df32818e..c3ef6267b2 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -775,10 +775,10 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 	rtex->tilled = 1;
 	rtex->array_mode = 2;
-	rtex->tile_type = 1;
+	rtex->tile_type = 0;
 	rtex->depth = 1;
 	rbuffer = &rtex->resource;
-R600_ERR("DB handle %d   %p  %d\n", rbuffer->bo->handle, rtex, state->zsbuf->texture->format);
+
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
@@ -1256,15 +1256,9 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 		if (r) {
 			return NULL;
 		}
-format = r600_translate_colorformat(view->texture->format);
-R600_ERR("DEPTH TEXTURE %d rtex %p %d 0x%02X\n", tmp->uncompressed->handle, tmp, view->texture->format, format);
-format = 17;
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
 		rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
-//		array_mode = tmp->array_mode;
-//		tile_type = tmp->tile_type;
 	} else {
-R600_ERR("NOT DEPTH TEXTURE\n");
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	}
diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index f93c20da35..927c342bb5 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -262,7 +262,7 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 
 	case PIPE_FORMAT_Z24X8_UNORM:
 	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
-		return V_0280A0_COLOR_24_8;
+		return V_0280A0_COLOR_8_24;
 
 		/* 64-bit buffers. */
 	case PIPE_FORMAT_R16G16B16A16_UNORM:
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index c79dd34f09..fb84ed9cfe 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -247,7 +247,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	trans->transfer.box = *box;
 	trans->transfer.stride = rtex->pitch[sr.level];
 	trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
-	if (rtex->tilled) {
+	if (rtex->tilled && !rtex->depth) {
 		resource.target = PIPE_TEXTURE_2D;
 		resource.format = texture->format;
 		resource.width0 = box->width;
@@ -303,30 +303,40 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 				struct pipe_transfer* transfer)
 {
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
-	struct r600_resource *resource;
+	struct radeon_bo *bo;
 	enum pipe_format format = transfer->resource->format;
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
+	struct r600_resource_texture *rtex;
+	unsigned long offset = 0;
 	char *map;
+	int r;
 
 	r600_flush(ctx, 0, NULL);
 	if (rtransfer->linear_texture) {
-		resource = (struct r600_resource *)rtransfer->linear_texture;
+		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
-		resource = (struct r600_resource *)transfer->resource;
+		rtex = (struct r600_resource_texture*)transfer->resource;
+		if (rtex->depth) {
+			r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
+			if (r) {
+				return NULL;
+			}
+			r600_flush(ctx, 0, NULL);
+			bo = rtex->uncompressed;
+		} else {
+			bo = ((struct r600_resource *)transfer->resource)->bo;
+		}
+		offset = rtransfer->offset +
+			transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
+			transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
 	}
-	if (radeon_bo_map(rscreen->rw, resource->bo)) {
+	if (radeon_bo_map(rscreen->rw, bo)) {
 		return NULL;
 	}
-	radeon_bo_wait(rscreen->rw, resource->bo);
-
-	map = resource->bo->data;
-	if (rtransfer->linear_texture) {
-		return map;
-	}
+	radeon_bo_wait(rscreen->rw, bo);
 
-	return map + rtransfer->offset +
-		transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
-		transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
+	map = bo->data;
+	return map + offset;
 }
 
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
@@ -334,14 +344,20 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
 {
 	struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_resource *resource;
+	struct r600_resource_texture *rtex;
+	struct radeon_bo *bo;
 
 	if (rtransfer->linear_texture) {
-		resource = (struct r600_resource *)rtransfer->linear_texture;
+		bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
 	} else {
-		resource = (struct r600_resource *)transfer->resource;
+		rtex = (struct r600_resource_texture*)transfer->resource;
+		if (rtex->depth) {
+			bo = rtex->uncompressed;
+		} else {
+			bo = ((struct r600_resource *)transfer->resource)->bo;
+		}
 	}
-	radeon_bo_unmap(rscreen->rw, resource->bo);
+	radeon_bo_unmap(rscreen->rw, bo);
 }
 
 struct u_resource_vtbl r600_texture_vtbl =
@@ -633,7 +649,6 @@ int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_textu
 
 	/* render a rectangle covering whole buffer to uncompress depth */
 	r = r600_blit_uncompress_depth(ctx, rtexture, level);
-R600_ERR("---step0 %d\n", r);
 	if (r) {
 		return r;
 	}
@@ -708,13 +723,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 		ntype = V_0280A0_NUMBER_SRGB;
 	format = r600_translate_colorformat(rtexture->resource.base.b.format);
 	swap = r600_translate_colorswap(rtexture->resource.base.b.format);
-	color_info = S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
 	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
-R600_ERR("CB0 uncompressed texture %p (handle)%d %d 0x%02X\n", rtexture, rtexture->uncompressed->handle, rtexture->resource.base.b.format, format);
-format = 17;
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
 		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
 		rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
@@ -722,6 +731,7 @@ format = 17;
 		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 		rstate->nbo = 3;
+		color_info = 0;
 	} else {
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -730,8 +740,12 @@ format = 17;
 		rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 		rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
 		rstate->nbo = 3;
-		color_info |= S_0280A0_SOURCE_FORMAT(1);
+		color_info = S_0280A0_SOURCE_FORMAT(1);
 	}
+	color_info |= S_0280A0_FORMAT(format) |
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
 	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
 	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
@@ -770,7 +784,6 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
 	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
 						S_028000_SLICE_TILE_MAX(slice);
-R600_ERR("DB handle %d  %p %d\n", rbuffer->bo->handle, rtexture, rbuffer->base.b.format);
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 1;
@@ -796,6 +809,35 @@ int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture
 	return 0;
 }
 
+static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscreen,
+					struct r600_resource_texture *rtexture,
+					unsigned level)
+{
+	struct radeon_state *rstate;
+
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	if (rstate == NULL)
+		return NULL;
+
+	/* set states (most default value are 0 and struct already
+	 * initialized to 0, thus avoid resetting them)
+	 */
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
+	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
+	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
+	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
+}
+
 int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
@@ -823,3 +865,17 @@ int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtex
 	}
 	return 0;
 }
+
+int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+{
+	struct r600_screen *rscreen = r600_screen(ctx->screen);
+
+	if (rtexture->viewport[level] == NULL) {
+		rtexture->viewport[level] = r600_texture_state_viewport(rscreen, rtexture, level);
+		if (rtexture->viewport[level] == NULL) {
+			R600_ERR("failed to create viewport state for texture\n");
+			return -ENOMEM;
+		}
+	}
+	return 0;
+}
-- 
cgit v1.2.3


From d21be6ee2cae2daeb83583a5d3798f5104c00d73 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 21:41:49 +0200
Subject: nvfx: use 64-bit bitmasks for temps

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index c4394b25f3..47df71f232 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -21,8 +21,8 @@ struct nvfx_fpc {
 	struct nvfx_pipe_fragment_program* pfp;
 	struct nvfx_fragment_program *fp;
 
-	unsigned r_temps;
-	unsigned r_temps_discard;
+	unsigned long long r_temps;
+	unsigned long long r_temps_discard;
 	struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
 	struct nvfx_reg *r_temp;
 
@@ -50,7 +50,7 @@ struct nvfx_fpc {
 static INLINE struct nvfx_reg
 temp(struct nvfx_fpc *fpc)
 {
-	int idx = ffs(~fpc->r_temps) - 1;
+	int idx = ffsll(~fpc->r_temps) - 1;
 
 	if (idx < 0) {
 		NOUVEAU_ERR("out of temps!!\n");
@@ -58,8 +58,8 @@ temp(struct nvfx_fpc *fpc)
 		return nvfx_reg(NVFXSR_TEMP, 0);
 	}
 
-	fpc->r_temps |= (1 << idx);
-	fpc->r_temps_discard |= (1 << idx);
+	fpc->r_temps |= (1ULL << idx);
+	fpc->r_temps_discard |= (1ULL << idx);
 	return nvfx_reg(NVFXSR_TEMP, idx);
 }
 
@@ -67,7 +67,7 @@ static INLINE void
 release_temps(struct nvfx_fpc *fpc)
 {
 	fpc->r_temps &= ~fpc->r_temps_discard;
-	fpc->r_temps_discard = 0;
+	fpc->r_temps_discard = 0ULL;
 }
 
 static INLINE struct nvfx_reg
@@ -911,7 +911,7 @@ nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
 	}
 
 	fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
-	fpc->r_temps |= (1 << hw);
+	fpc->r_temps |= (1ULL << hw);
 	return TRUE;
 }
 
@@ -987,7 +987,7 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 		fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
 		for (i = 0; i < high_temp; i++)
 			fpc->r_temp[i] = temp(fpc);
-		fpc->r_temps_discard = 0;
+		fpc->r_temps_discard = 0ULL;
 	}
 
 	return TRUE;
-- 
cgit v1.2.3


From d507c0812d5a01d29f1f9f6942ec5cfd91ea0375 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Sun, 22 Aug 2010 23:29:34 +0200
Subject: nvfx: support both sprite coord origins

Now we lie less when claiming OpenGL 2 support.

Also, first piglit result group is now all green, except for
fdo25614-genmipmap, which seems mesa/st's fault.
---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 139 ++++++++++++++++++++++---------
 src/gallium/drivers/nvfx/nvfx_state.c    |   3 +-
 src/gallium/drivers/nvfx/nvfx_state.h    |   9 +-
 3 files changed, 108 insertions(+), 43 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 47df71f232..12b002a819 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -25,6 +25,7 @@ struct nvfx_fpc {
 	unsigned long long r_temps_discard;
 	struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
 	struct nvfx_reg *r_temp;
+	unsigned sprite_coord_temp;
 
 	int num_regs;
 
@@ -114,9 +115,10 @@ emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
 		sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
 		break;
 	case NVFXSR_RELOCATED:
-		sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
+		sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
+		sr |= (fpc->sprite_coord_temp << NVFX_FP_REG_SRC_SHIFT);
 		//printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
-		util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset);
+		util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset + pos + 1);
 		break;
 	case NVFXSR_CONST:
 		if (!fpc->have_const) {
@@ -1003,7 +1005,8 @@ DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
 
 static struct nvfx_fragment_program*
 nvfx_fragprog_translate(struct nvfx_context *nvfx,
-			struct nvfx_pipe_fragment_program *pfp)
+			struct nvfx_pipe_fragment_program *pfp,
+			boolean emulate_sprite_flipping)
 {
 	struct tgsi_parse_context parse;
 	struct nvfx_fpc *fpc = NULL;
@@ -1027,8 +1030,20 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 		goto out_err;
 
 	tgsi_parse_init(&parse, pfp->pipe.tokens);
-
 	util_dynarray_init(&insns);
+
+	if(emulate_sprite_flipping)
+	{
+		struct nvfx_reg reg = temp(fpc);
+		struct nvfx_src sprite_input = nvfx_src(nvfx_reg(NVFXSR_RELOCATED, fp->num_slots));
+		float v[4] = {1, -1, 0, 0};
+		struct nvfx_src imm = nvfx_src(constant(fpc, -1, v));
+
+		fpc->sprite_coord_temp = reg.index;
+		fpc->r_temps_discard = 0ULL;
+		nvfx_fp_emit(fpc, arith(0, MAD, reg, NVFX_FP_MASK_ALL, sprite_input, swz(imm, X, Y, X, X), swz(imm, Z, X, Z, Z)));
+	}
+
 	while (!tgsi_parse_end_of_tokens(&parse)) {
 		tgsi_parse_token(&parse);
 
@@ -1166,14 +1181,16 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
 	struct nvfx_vertex_program* vp;
-	unsigned sprite_coord_enable;
-	unsigned key = 0;
+	unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
+	// TODO: correct or flipped?
+	boolean emulate_sprite_flipping = sprite_coord_enable && nvfx->rasterizer->pipe.sprite_coord_mode;
+	unsigned key = emulate_sprite_flipping;
 	struct nvfx_fragment_program* fp;
 
 	fp = pfp->fps[key];
 	if (!fp)
 	{
-		fp = nvfx_fragprog_translate(nvfx, pfp);
+		fp = nvfx_fragprog_translate(nvfx, pfp, emulate_sprite_flipping);
 
 		if(!fp)
 		{
@@ -1193,7 +1210,8 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 				}
 			}
 
-			fp = nvfx_fragprog_translate(nvfx, nvfx->dummy_fs);
+			fp = nvfx_fragprog_translate(nvfx, nvfx->dummy_fs, FALSE);
+			emulate_sprite_flipping = FALSE;
 
 			if(!fp)
 			{
@@ -1205,21 +1223,19 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 		pfp->fps[key] = fp;
 	}
 
-	nvfx->hw_fragprog = fp;
-
 	vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
-        sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
 
 	if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) {
-		int sprite_input = -1;
+		int sprite_real_input = -1;
+		int sprite_reloc_input;
 		unsigned i;
 		fp->last_vp_id = vp->id;
 		fp->last_sprite_coord_enable = sprite_coord_enable;
 
 		if(sprite_coord_enable)
 		{
-			sprite_input = vp->sprite_fp_input;
-			if(sprite_input < 0)
+			sprite_real_input = vp->sprite_fp_input;
+			if(sprite_real_input < 0)
 			{
 				unsigned used_texcoords = 0;
 				for(unsigned i = 0; i < fp->num_slots; ++i) {
@@ -1232,19 +1248,24 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 					}
 				}
 
-				sprite_input = NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords));
+				sprite_real_input = NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords));
 			}
 
-			fp->point_sprite_control |= (1 << (sprite_input - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
+			fp->point_sprite_control |= (1 << (sprite_real_input - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
 		}
 		else
 			fp->point_sprite_control = 0;
 
+		if(emulate_sprite_flipping)
+		   sprite_reloc_input = 0;
+		else
+		   sprite_reloc_input = sprite_real_input;
+
 		for(i = 0; i < fp->num_slots; ++i) {
 			unsigned generic = fp->slot_to_generic[i];
 			if((1 << generic) & sprite_coord_enable)
 			{
-				if(fp->slot_to_fp_input[i] != sprite_input)
+				if(fp->slot_to_fp_input[i] != sprite_reloc_input)
 					goto update_slots;
 			}
 			else
@@ -1255,6 +1276,12 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 			}
 		}
 
+		if(emulate_sprite_flipping)
+		{
+			if(fp->slot_to_fp_input[fp->num_slots] != sprite_real_input)
+				goto update_slots;
+		}
+
 		if(0)
 		{
 update_slots:
@@ -1263,21 +1290,23 @@ update_slots:
 			{
 				unsigned generic = fp->slot_to_generic[i];
 				if((1 << generic) & sprite_coord_enable)
-					fp->slot_to_fp_input[i] = sprite_input;
+					fp->slot_to_fp_input[i] = sprite_reloc_input;
 				else
 					fp->slot_to_fp_input[i] = vp->generic_to_fp_input[generic] & 0xf;
 			}
 
+			fp->slot_to_fp_input[fp->num_slots] = sprite_real_input;
+
 			if(nvfx->is_nv4x)
 			{
 				fp->or = 0;
-				for(i = 0; i < fp->num_slots; ++i) {
+				for(i = 0; i <= fp->num_slots; ++i) {
 					unsigned fp_input = fp->slot_to_fp_input[i];
 					if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(8))
 						fp->or |= (1 << 12);
 					else if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(9))
 						fp->or |= (1 << 13);
-					else if(fp_input != 0xf)
+					else if(fp_input >= NVFX_FP_OP_INPUT_SRC_TC(0) && fp_input <= NVFX_FP_OP_INPUT_SRC_TC(7))
 						fp->or |= (1 << (fp_input - NVFX_FP_OP_INPUT_SRC_TC0 + 14));
 				}
 			}
@@ -1292,7 +1321,7 @@ update_slots:
 	  * one bound to this fragment program.
 	  * Doing such a check would likely be a pessimization.
 	  */
-	if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG)) {
+	if ((nvfx->hw_fragprog != fp) || (nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST))) {
 		int offset;
 		uint32_t* fpmap;
 
@@ -1365,16 +1394,45 @@ update:
 		 */
 		if(fp->progs_left_with_obsolete_slot_assignments) {
 			unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
-			for(unsigned i = 0; i < fp->num_slots; ++i) {
+			/* also relocate sprite coord slot, if any */
+			for(unsigned i = 0; i <= fp->num_slots; ++i) {
 				unsigned value = fp->slot_to_fp_input[i];;
 				if(value != fpbo_slots[i]) {
-					unsigned* p = (unsigned*)fp->slot_relocations[i].data;
-					unsigned* pend = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
-					for(; p != pend; ++p) {
-						unsigned off = *p;
-						unsigned dw = fp->insn[off];
-						dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
-						nvfx_fp_memcpy(&fpmap[*p], &dw, sizeof(dw));
+					unsigned* p;
+					unsigned* begin = (unsigned*)fp->slot_relocations[i].data;
+					unsigned* end = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
+					//printf("fp %p reloc slot %u/%u: %u -> %u\n", fp, i, fp->num_slots, fpbo_slots[i], value);
+					if(value == 0)
+					{
+						/* was relocated to an input, switch type to temporary */
+						for(p = begin; p != end; ++p) {
+							unsigned off = *p;
+							unsigned dw = fp->insn[off];
+							dw &=~ NVFX_FP_REG_TYPE_MASK;
+							//printf("reloc_tmp at %x\n", off);
+							nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
+						}
+					} else {
+						if(!fpbo_slots[i])
+						{
+							/* was relocated to a temporary, switch type to input */
+							for(p= begin; p != end; ++p) {
+								unsigned off = *p;
+								unsigned dw = fp->insn[off];
+								//printf("reloc_in at %x\n", off);
+								dw |= NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT;
+								nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
+							}
+						}
+
+						/* set the correct input index */
+						for(p = begin; p != end; ++p) {
+							unsigned off = *p & ~3;
+							unsigned dw = fp->insn[off];
+							//printf("reloc&~3 at %x\n", off);
+							dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
+							nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
+						}
 					}
 					fpbo_slots[i] = value;
 				}
@@ -1382,6 +1440,8 @@ update:
 			--fp->progs_left_with_obsolete_slot_assignments;
 		}
 
+		nvfx->hw_fragprog = fp;
+
 		MARK_RING(chan, 8, 1);
 		OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1));
 		OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
@@ -1491,15 +1551,18 @@ nvfx_fp_state_bind(struct pipe_context *pipe, void *hwcso)
 static void
 nvfx_fp_state_delete(struct pipe_context *pipe, void *hwcso)
 {
-        struct nvfx_context *nvfx = nvfx_context(pipe);
-        struct nvfx_pipe_fragment_program *pfp = hwcso;
-        unsigned i;
-
-        for(i = 0; i < Elements(pfp->fps); ++i)
-        {
-        	nvfx_fragprog_destroy(nvfx, pfp->fps[i]);
-        	FREE(pfp->fps[i]);
-        }
+	struct nvfx_context *nvfx = nvfx_context(pipe);
+	struct nvfx_pipe_fragment_program *pfp = hwcso;
+	unsigned i;
+
+	for(i = 0; i < Elements(pfp->fps); ++i)
+	{
+		if(pfp->fps[i])
+		{
+			nvfx_fragprog_destroy(nvfx, pfp->fps[i]);
+			FREE(pfp->fps[i]);
+		}
+	}
 
         FREE((void*)pfp->pipe.tokens);
         FREE(pfp);
diff --git a/src/gallium/drivers/nvfx/nvfx_state.c b/src/gallium/drivers/nvfx/nvfx_state.c
index cb32e503c8..5bd7dc07f0 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.c
+++ b/src/gallium/drivers/nvfx/nvfx_state.c
@@ -174,7 +174,8 @@ nvfx_rasterizer_state_bind(struct pipe_context *pipe, void *hwcso)
 		}
 
 		if(((struct nvfx_rasterizer_state*)hwcso)->pipe.point_quad_rasterization != nvfx->rasterizer->pipe.point_quad_rasterization
-				|| ((struct nvfx_rasterizer_state*)hwcso)->pipe.sprite_coord_enable != nvfx->rasterizer->pipe.sprite_coord_enable)
+				|| ((struct nvfx_rasterizer_state*)hwcso)->pipe.sprite_coord_enable != nvfx->rasterizer->pipe.sprite_coord_enable
+				|| ((struct nvfx_rasterizer_state*)hwcso)->pipe.sprite_coord_mode != nvfx->rasterizer->pipe.sprite_coord_mode)
 		{
 			nvfx->dirty |= NVFX_NEW_SPRITE;
 		}
diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
index fd2174ed69..3795191918 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ b/src/gallium/drivers/nvfx/nvfx_state.h
@@ -71,10 +71,11 @@ struct nvfx_fragment_program {
 	struct nvfx_fragment_program_data *consts;
 	unsigned nr_consts;
 
+	/* the slot at num_slots is for the sprite coordinate, if any */
 	unsigned num_slots; /* how many input semantics? */
-	unsigned char slot_to_generic[8]; /* semantics */
-	unsigned char slot_to_fp_input[8]; /* current assignment of slots for each used semantic */
-	struct util_dynarray slot_relocations[8];
+	unsigned char slot_to_generic[10]; /* semantics */
+	unsigned char slot_to_fp_input[11]; /* current assignment of slots for each used semantic */
+	struct util_dynarray slot_relocations[11];
 
 	/* This is reset to progs on any relocation update, and decreases every time we
 	 * move to a new prog due to a constant update
@@ -99,7 +100,7 @@ struct nvfx_pipe_fragment_program {
         struct pipe_shader_state pipe;
         struct tgsi_shader_info info;
 
-        struct nvfx_fragment_program* fps[1];
+        struct nvfx_fragment_program* fps[2];
 };
 
 #endif
-- 
cgit v1.2.3


From 8ffc3572281c24d1f97b3c119117918dca80f53e Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 23 Aug 2010 00:16:23 +0200
Subject: nvfx: fix minor memory leak

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 12b002a819..a7e43b1513 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -1518,7 +1518,7 @@ nvfx_fragprog_destroy(struct nvfx_context *nvfx,
 		while(fpbo != fp->fpbo);
 	}
 
-	for(i = 0; i < 8; ++i)
+	for(i = 0; i < Elements(fp->slot_relocations); ++i)
 		util_dynarray_fini(&fp->slot_relocations[i]);
 
 	if (fp->insn_len)
-- 
cgit v1.2.3


From eb430b0e948caf02b9f4095d0e1435880073c2aa Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 23 Aug 2010 20:28:02 +1000
Subject: r300g: avoid stall in no-tcl drawing when mapping vbo

the current code reuses the same vbo over and over, however after a flush
we'd stall and wait for mapping on the vbo when we should just fire and forget.

On a gears test this brings me from ~620 to ~750 on my rv530 in swtcl mode.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r300/r300_context.h |  4 ++++
 src/gallium/drivers/r300/r300_flush.c   |  2 ++
 src/gallium/drivers/r300/r300_render.c  | 35 +++++++++++++++++++--------------
 3 files changed, 26 insertions(+), 15 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
index 6fa7f470f9..030bb2314f 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -449,6 +449,7 @@ struct r300_context {
     struct r300_screen *screen;
     /* Draw module. Used mostly for SW TCL. */
     struct draw_context* draw;
+    size_t draw_vbo_size;
     /* Accelerated blit support. */
     struct blitter_context* blitter;
     /* Stencil two-sided reference value fallback. */
@@ -649,6 +650,9 @@ void r300_translate_index_buffer(struct r300_context *r300,
 /* r300_render_stencilref.c */
 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
 
+/* r300 render */
+void r300_draw_flush_vbuf(struct r300_context *r300);
+
 /* r300_state.c */
 enum r300_fb_state_change {
     R300_CHANGED_FB_STATE = 0,
diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c
index fe182b6615..f00707b066 100644
--- a/src/gallium/drivers/r300/r300_flush.c
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -43,6 +43,8 @@ static void r300_flush(struct pipe_context* pipe,
     u_upload_flush(r300->upload_vb);
     u_upload_flush(r300->upload_ib);
 
+    if (r300->draw)
+	r300_draw_flush_vbuf(r300);
     if (r300->dirty_hw) {
         r300_emit_hyperz_end(r300);
         r300_emit_query_end(r300);
diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c
index 86b11ca045..73447057bb 100644
--- a/src/gallium/drivers/r300/r300_render.c
+++ b/src/gallium/drivers/r300/r300_render.c
@@ -726,8 +726,6 @@ struct r300_render {
     unsigned hwprim;
 
     /* VBO */
-    struct pipe_resource* vbo;
-    size_t vbo_size;
     size_t vbo_offset;
     size_t vbo_max_used;
     void * vbo_ptr;
@@ -759,31 +757,31 @@ static boolean r300_render_allocate_vertices(struct vbuf_render* render,
     struct pipe_screen* screen = r300->context.screen;
     size_t size = (size_t)vertex_size * (size_t)count;
 
-    if (size + r300render->vbo_offset > r300render->vbo_size)
+    if (size + r300render->vbo_offset > r300->draw_vbo_size)
     {
-        pipe_resource_reference(&r300->vbo, NULL);
-        r300render->vbo = pipe_buffer_create(screen,
-                                             PIPE_BIND_VERTEX_BUFFER,
-                                             R300_MAX_DRAW_VBO_SIZE);
+	pipe_resource_reference(&r300->vbo, NULL);
+        r300->vbo = pipe_buffer_create(screen,
+				       PIPE_BIND_VERTEX_BUFFER,
+				       R300_MAX_DRAW_VBO_SIZE);
         r300render->vbo_offset = 0;
-        r300render->vbo_size = R300_MAX_DRAW_VBO_SIZE;
+        r300->draw_vbo_size = R300_MAX_DRAW_VBO_SIZE;
     }
 
     r300render->vertex_size = vertex_size;
-    r300->vbo = r300render->vbo;
     r300->vbo_offset = r300render->vbo_offset;
 
-    return (r300render->vbo) ? TRUE : FALSE;
+    return (r300->vbo) ? TRUE : FALSE;
 }
 
 static void* r300_render_map_vertices(struct vbuf_render* render)
 {
     struct r300_render* r300render = r300_render(render);
+    struct r300_context* r300 = r300render->r300;
 
     assert(!r300render->vbo_transfer);
 
     r300render->vbo_ptr = pipe_buffer_map(&r300render->r300->context,
-					  r300render->vbo,
+					  r300->vbo,
                                           PIPE_TRANSFER_WRITE,
 					  &r300render->vbo_transfer);
 
@@ -798,12 +796,13 @@ static void r300_render_unmap_vertices(struct vbuf_render* render,
 {
     struct r300_render* r300render = r300_render(render);
     struct pipe_context* context = &r300render->r300->context;
+    struct r300_context* r300 = r300render->r300;
 
     assert(r300render->vbo_transfer);
 
     r300render->vbo_max_used = MAX2(r300render->vbo_max_used,
                                     r300render->vertex_size * (max + 1));
-    pipe_buffer_unmap(context, r300render->vbo, r300render->vbo_transfer);
+    pipe_buffer_unmap(context, r300->vbo, r300render->vbo_transfer);
 
     r300render->vbo_transfer = NULL;
 }
@@ -880,7 +879,7 @@ static void r300_render_draw_elements(struct vbuf_render* render,
     struct r300_context* r300 = r300render->r300;
     int i;
     unsigned end_cs_dwords;
-    unsigned max_index = (r300render->vbo_size - r300render->vbo_offset) /
+    unsigned max_index = (r300->draw_vbo_size - r300render->vbo_offset) /
                          (r300render->r300->vertex_info.size * 4) - 1;
     unsigned short_count;
     unsigned free_dwords;
@@ -956,8 +955,6 @@ static struct vbuf_render* r300_render_create(struct r300_context* r300)
     r300render->base.release_vertices = r300_render_release_vertices;
     r300render->base.destroy = r300_render_destroy;
 
-    r300render->vbo = NULL;
-    r300render->vbo_size = 0;
     r300render->vbo_offset = 0;
 
     return &r300render->base;
@@ -986,6 +983,14 @@ struct draw_stage* r300_draw_stage(struct r300_context* r300)
     return stage;
 }
 
+void r300_draw_flush_vbuf(struct r300_context *r300)
+{
+    struct r300_render *r300render;
+
+    pipe_resource_reference(&r300->vbo, NULL);
+    r300->draw_vbo_size = 0;
+}
+
 /****************************************************************************
  *                         End of SW TCL functions                          *
  ***************************************************************************/
-- 
cgit v1.2.3


From bfaa2577c6474222c79341c0d90685ed579f3414 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 23 Aug 2010 00:31:08 +0200
Subject: nvfx: support clip planes sensibly and fix them on nv30

Before, we were discarding the compiled vertex program on each
vertex program change.

Now we compile the program as if there were 6 clip planes and
dynamically patch in an "end program" bit at the right place.

Also, nv30 should now work.
---
 src/gallium/auxiliary/util/u_dynarray.h    |   3 +
 src/gallium/drivers/nvfx/nv30_vertprog.h   |   5 +-
 src/gallium/drivers/nvfx/nvfx_context.c    |   4 +
 src/gallium/drivers/nvfx/nvfx_context.h    |   1 +
 src/gallium/drivers/nvfx/nvfx_fragprog.c   |  13 ---
 src/gallium/drivers/nvfx/nvfx_state.h      |   4 +-
 src/gallium/drivers/nvfx/nvfx_state_emit.c |  82 ++++++++++++++
 src/gallium/drivers/nvfx/nvfx_vertprog.c   | 170 ++++++++++++-----------------
 8 files changed, 166 insertions(+), 116 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/auxiliary/util/u_dynarray.h b/src/gallium/auxiliary/util/u_dynarray.h
index 9d1c1713a7..980cadf22d 100644
--- a/src/gallium/auxiliary/util/u_dynarray.h
+++ b/src/gallium/auxiliary/util/u_dynarray.h
@@ -106,6 +106,9 @@ util_dynarray_trim(struct util_dynarray *buf)
 #define util_dynarray_pop_ptr(buf, type) (type*)((char*)(buf)->data + ((buf)->size -= sizeof(type)))
 #define util_dynarray_pop(buf, type) *util_dynarray_pop_ptr(buf, type)
 #define util_dynarray_contains(buf, type) ((buf)->size >= sizeof(type))
+#define util_dynarray_element(buf, type, idx) ((type*)(buf)->data + (idx))
+#define util_dynarray_begin(buf) ((buf)->data)
+#define util_dynarray_end(buf) ((void*)util_dynarray_element((buf), char, (buf)->size))
 
 #endif /* U_DYNARRAY_H */
 
diff --git a/src/gallium/drivers/nvfx/nv30_vertprog.h b/src/gallium/drivers/nvfx/nv30_vertprog.h
index df92469078..9a68f5c1fb 100644
--- a/src/gallium/drivers/nvfx/nv30_vertprog.h
+++ b/src/gallium/drivers/nvfx/nv30_vertprog.h
@@ -125,7 +125,7 @@
 #define NV30_VP_INST_VDEST_WRITEMASK_SHIFT      12    /*NV20*/
 #define NV30_VP_INST_VDEST_WRITEMASK_MASK      (0x0F << 12)  /*NV20*/
 #define NV30_VP_INST_DEST_SHIFT        2
-#define NV30_VP_INST_DEST_MASK        (0x0F <<  2)
+#define NV30_VP_INST_DEST_MASK        (0x1F <<  2)
 #  define NV30_VP_INST_DEST_POS  0
 #  define NV30_VP_INST_DEST_BFC0  1
 #  define NV30_VP_INST_DEST_BFC1  2
@@ -133,7 +133,8 @@
 #  define NV30_VP_INST_DEST_COL1  4
 #  define NV30_VP_INST_DEST_FOGC  5
 #  define NV30_VP_INST_DEST_PSZ   6
-#  define NV30_VP_INST_DEST_TC(n)  (8+n)
+#  define NV30_VP_INST_DEST_TC(n)  (8+(n))
+#  define NV30_VP_INST_DEST_CLP(n) (17 + (n))
 
 /* Useful to split the source selection regs into their pieces */
 #define NV30_VP_SRC0_HIGH_SHIFT                                                6
diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 80b36fb7b9..2f775f92cf 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -75,6 +75,10 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	screen->base.channel->user_private = nvfx;
 
 	nvfx->is_nv4x = screen->is_nv4x;
+	/* TODO: it seems that nv30 might have fixed function clipping usable with vertex programs
+	 * However, my code for that doesn't work, so use vp clipping for all cards, which works.
+	 */
+	nvfx->use_vp_clipping = TRUE;
 
 	nvfx_init_query_functions(nvfx);
 	nvfx_init_surface_functions(nvfx);
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 2134f3c386..680f4c6ce0 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -134,6 +134,7 @@ struct nvfx_context {
 	struct nvfx_screen *screen;
 
 	unsigned is_nv4x; /* either 0 or ~0 */
+	boolean use_vp_clipping;
 
 	struct draw_context *draw;
 	struct blitter_context* blitter;
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index a7e43b1513..23a85c9342 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -1468,19 +1468,6 @@ update:
 			nvfx->hw_pointsprite_control = pointsprite_control;
 		}
 	}
-
-	if(nvfx->is_nv4x)
-	{
-		unsigned vp_output = vp->or | fp->or;
-
-		if(vp_output != nvfx->hw_vp_output)
-		{
-			WAIT_RING(chan, 2);
-			OUT_RING(chan, RING_3D(NV40TCL_VP_RESULT_EN, 1));
-			OUT_RING(chan, vp_output);
-			nvfx->hw_vp_output = vp_output;
-		}
-	}
 }
 
 void
diff --git a/src/gallium/drivers/nvfx/nvfx_state.h b/src/gallium/drivers/nvfx/nvfx_state.h
index 3795191918..e9c1f2c26d 100644
--- a/src/gallium/drivers/nvfx/nvfx_state.h
+++ b/src/gallium/drivers/nvfx/nvfx_state.h
@@ -24,8 +24,6 @@ struct nvfx_vertex_program {
 
 	boolean translated;
 
-	struct pipe_clip_state ucp;
-
 	struct nvfx_vertex_program_exec *insns;
 	unsigned nr_insns;
 	struct nvfx_vertex_program_data *consts;
@@ -42,7 +40,7 @@ struct nvfx_vertex_program {
 
 	uint32_t ir;
 	uint32_t or;
-	uint32_t clip_ctrl;
+	int clip_nr;
 
 	struct util_dynarray branch_relocs;
 	struct util_dynarray const_relocs;
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index bd89a385d7..c43a75aaa2 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -90,6 +90,74 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	if(dirty & NVFX_NEW_STIPPLE)
 		nvfx_state_stipple_validate(nvfx);
 
+       if(nvfx->dirty & NVFX_NEW_UCP)
+	{
+		unsigned enables[7] =
+		{
+				0,
+				NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0,
+				NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1,
+				NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2,
+				NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3,
+				NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4,
+				NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4 | NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5,
+		};
+
+		if(!nvfx->use_vp_clipping)
+		{
+			WAIT_RING(chan, 2);
+			OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
+			OUT_RING(chan, 0);
+
+			WAIT_RING(chan, 6 * 4 + 1);
+			OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANE_A(0), nvfx->clip.nr * 4));
+			OUT_RINGp(chan, &nvfx->clip.ucp[0][0], nvfx->clip.nr * 4);
+		}
+
+		WAIT_RING(chan, 2);
+		OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
+		OUT_RING(chan, enables[nvfx->clip.nr]);
+	}
+
+	if(nvfx->use_vp_clipping && (nvfx->dirty & (NVFX_NEW_UCP | NVFX_NEW_VERTPROG)))
+	{
+		unsigned i;
+		struct nvfx_vertex_program* vp = nvfx->vertprog;
+		if(nvfx->clip.nr != vp->clip_nr)
+		{
+			unsigned idx;
+			WAIT_RING(chan, 14);
+
+			/* remove last instruction bit */
+			if(vp->clip_nr >= 0)
+			{
+				idx = vp->nr_insns - 7 + vp->clip_nr;
+				OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1));
+				OUT_RING(chan,  vp->exec->start + idx);
+				OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4));
+				OUT_RINGp (chan, vp->insns[idx].data, 4);
+			}
+
+			 /* set last instruction bit */
+			idx = vp->nr_insns - 7 + nvfx->clip.nr;
+			OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_FROM_ID, 1));
+			OUT_RING(chan,  vp->exec->start + idx);
+			OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_INST(0), 4));
+			OUT_RINGp(chan, vp->insns[idx].data, 3);
+			OUT_RING(chan, vp->insns[idx].data[3] | 1);
+			vp->clip_nr = nvfx->clip.nr;
+		}
+
+		// TODO: only do this for the ones changed
+		WAIT_RING(chan, 6 * 6);
+		for(i = 0; i < nvfx->clip.nr; ++i)
+		{
+			OUT_RING(chan, RING_3D(NV34TCL_VP_UPLOAD_CONST_ID, 5));
+			OUT_RING(chan, vp->data->start + i);
+			OUT_RINGp (chan, nvfx->clip.ucp[i], 4);
+		}
+	}
+
 	if(dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST | NVFX_NEW_VERTPROG | NVFX_NEW_SPRITE))
 	{
 		nvfx_fragprog_validate(nvfx);
@@ -97,6 +165,20 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 			flush_tex_cache = TRUE; // TODO: do we need this?
 	}
 
+	if(nvfx->is_nv4x)
+	{
+		unsigned vp_output = nvfx->vertprog->or | nvfx->hw_fragprog->or;
+		vp_output |= (1 << (nvfx->clip.nr + 6)) - (1 << 6);
+
+		if(vp_output != nvfx->hw_vp_output)
+		{
+			WAIT_RING(chan, 2);
+			OUT_RING(chan, RING_3D(NV40TCL_VP_RESULT_EN, 1));
+			OUT_RING(chan, vp_output);
+			nvfx->hw_vp_output = vp_output;
+		}
+	}
+
 	if(all_swizzled >= 0)
 		nvfx_framebuffer_validate(nvfx, all_swizzled);
 
diff --git a/src/gallium/drivers/nvfx/nvfx_vertprog.c b/src/gallium/drivers/nvfx/nvfx_vertprog.c
index 3b8d3853b7..ea7e88c561 100644
--- a/src/gallium/drivers/nvfx/nvfx_vertprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_vertprog.c
@@ -29,8 +29,6 @@
 #include "nv30_vertprog.h"
 #include "nv40_vertprog.h"
 
-#define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
-
 struct nvfx_loop_entry
 {
 	unsigned brk_target;
@@ -205,52 +203,33 @@ emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot
 		break;
 	case NVFXSR_OUTPUT:
 		/* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
-		switch (dst.index) {
-		case NVFX_VP_INST_DEST_CLIP(0):
-			vp->or |= (1 << 6);
-			vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
-			dst.index = NVFX_VP(INST_DEST_FOGC);
-			break;
-		case NVFX_VP_INST_DEST_CLIP(1):
-			vp->or |= (1 << 7);
-			vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
-			dst.index = NVFX_VP(INST_DEST_FOGC);
-			break;
-		case NVFX_VP_INST_DEST_CLIP(2):
-			vp->or |= (1 << 8);
-			vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
-			dst.index = NVFX_VP(INST_DEST_FOGC);
-			break;
-		case NVFX_VP_INST_DEST_CLIP(3):
-			vp->or |= (1 << 9);
-			vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
-			dst.index = NVFX_VP(INST_DEST_PSZ);
-			break;
-		case NVFX_VP_INST_DEST_CLIP(4):
-			vp->or |= (1 << 10);
-			vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
-			dst.index = NVFX_VP(INST_DEST_PSZ);
-			break;
-		case NVFX_VP_INST_DEST_CLIP(5):
-			vp->or |= (1 << 11);
-			vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
-			dst.index = NVFX_VP(INST_DEST_PSZ);
-			break;
-		default:
-			if(nvfx->is_nv4x) {
-				/* we don't need vp->or on nv3x
-				 * texcoords are handled by fragment program
-				 */
-				switch (dst.index) {
-				case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
-				case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
-				case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
-				case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
-				case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
-				case NV40_VP_INST_DEST_PSZ  : vp->or |= (1 << 5); break;
-				}
+		if(nvfx->is_nv4x) {
+			switch (dst.index) {
+			case NV30_VP_INST_DEST_CLP(0):
+				dst.index = NVFX_VP(INST_DEST_FOGC);
+				break;
+			case NV30_VP_INST_DEST_CLP(1):
+				dst.index = NVFX_VP(INST_DEST_FOGC);
+				break;
+			case NV30_VP_INST_DEST_CLP(2):
+				dst.index = NVFX_VP(INST_DEST_FOGC);
+				break;
+			case NV30_VP_INST_DEST_CLP(3):
+				dst.index = NVFX_VP(INST_DEST_PSZ);
+				break;
+			case NV30_VP_INST_DEST_CLP(4):
+				dst.index = NVFX_VP(INST_DEST_PSZ);
+				break;
+			case NV30_VP_INST_DEST_CLP(5):
+				dst.index = NVFX_VP(INST_DEST_PSZ);
+				break;
+			case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
+			case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
+			case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
+			case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
+			case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
+			case NV40_VP_INST_DEST_PSZ  : vp->or |= (1 << 5); break;
 			}
-			break;
 		}
 
 		if(!nvfx->is_nv4x) {
@@ -914,6 +893,13 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 	vpc->nvfx = nvfx;
 	vpc->vp = vp;
 
+	/* reserve space for ucps */
+	if(nvfx->use_vp_clipping)
+	{
+		for(i = 0; i < 6; ++i)
+			constant(vpc, -1, 0, 0, 0, 0);
+	}
+
 	if (!nvfx_vertprog_prepare(nvfx, vpc)) {
 		FREE(vpc);
 		return;
@@ -923,7 +909,8 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 	 * planes are enabled.  We need to append code to the vtxprog
 	 * to handle clip planes later.
 	 */
-	if (vp->ucp.nr)  {
+	/* TODO: maybe support patching this depending on whether there are ucps: not sure if it is really matters much */
+	if (nvfx->use_vp_clipping)  {
 		vpc->r_result[vpc->hpos_idx] = temp(vpc);
 		vpc->r_temps_discard = 0;
 	}
@@ -994,34 +981,39 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 	}
 
 	/* Insert code to handle user clip planes */
-	for (i = 0; i < vp->ucp.nr; i++) {
-		struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT,
-						NVFX_VP_INST_DEST_CLIP(i));
-		struct nvfx_src ceqn = nvfx_src(constant(vpc, -1,
-						 nvfx->clip.ucp[i][0],
-						 nvfx->clip.ucp[i][1],
-						 nvfx->clip.ucp[i][2],
-						 nvfx->clip.ucp[i][3]));
-		struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
-		unsigned mask;
+	if(nvfx->use_vp_clipping)
+	{
+		for (i = 0; i < 6; i++) {
+			struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT, NV30_VP_INST_DEST_CLP(i));
+			struct nvfx_src ceqn = nvfx_src(nvfx_reg(NVFXSR_CONST, i));
+			struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
+			unsigned mask;
 
-		switch (i) {
-		case 0: case 3: mask = NVFX_VP_MASK_Y; break;
-		case 1: case 4: mask = NVFX_VP_MASK_Z; break;
-		case 2: case 5: mask = NVFX_VP_MASK_W; break;
-		default:
-			NOUVEAU_ERR("invalid clip dist #%d\n", i);
-			goto out_err;
-		}
+			if(nvfx->is_nv4x)
+			{
+				switch (i) {
+				case 0: case 3: mask = NVFX_VP_MASK_Y; break;
+				case 1: case 4: mask = NVFX_VP_MASK_Z; break;
+				case 2: case 5: mask = NVFX_VP_MASK_W; break;
+				default:
+					NOUVEAU_ERR("invalid clip dist #%d\n", i);
+					goto out_err;
+				}
+			}
+			else
+				mask = NVFX_VP_MASK_X;
 
-		nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none));
+			nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none));
+		}
 	}
+	else
+	{
+		if(vp->nr_insns)
+			vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
 
-	//vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
-
-	/* Append NOP + END instruction for branches to the end of the program */
-	nvfx_vp_emit(vpc, arith(VEC, NOP, none.reg, 0, none, none, none));
-        vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST | 0x1000;
+		nvfx_vp_emit(vpc, arith(VEC, NOP, none.reg, 0, none, none, none));
+		vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
+	}
 
 	if(debug_get_option_nvfx_dump_vp())
 	{
@@ -1034,6 +1026,7 @@ nvfx_vertprog_translate(struct nvfx_context *nvfx,
 		debug_printf("\n");
 	}
 
+	vp->clip_nr = -1;
 	vp->exec_start = -1;
 	vp->translated = TRUE;
 out_err:
@@ -1063,13 +1056,6 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 	if (nvfx->render_mode == HW) {
 		vp = nvfx->vertprog;
 		constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
-
-		// TODO: ouch! can't we just use constant slots for these?!
-		if ((nvfx->dirty & NVFX_NEW_UCP) ||
-		    memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
-			nvfx_vertprog_destroy(nvfx, vp);
-			memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
-		}
 	} else {
 		vp = nvfx->swtnl.vertprog;
 		constbuf = NULL;
@@ -1169,7 +1155,7 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 		vp->exec_start = vp->exec->start;
 	}
 
-	if (vp->nr_consts && vp->data_start != vp->data->start) {
+	if (vp->data_start != vp->data->start) {
 		for(unsigned i = 0; i < vp->const_relocs.size; i += sizeof(struct nvfx_relocation))
 		{
 			struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->const_relocs.data + i);
@@ -1182,6 +1168,7 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 		}
 
 		vp->data_start = vp->data->start;
+		upload_code = TRUE;
 	}
 
 	/* Update + Upload constant values */
@@ -1191,7 +1178,7 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 		if (constbuf)
 			map = (float*)nvfx_buffer(constbuf)->data;
 
-		for (i = 0; i < vp->nr_consts; i++) {
+		for (i = nvfx->use_vp_clipping ? 6 : 0; i < vp->nr_consts; i++) {
 			struct nvfx_vertex_program_data *vpd = &vp->consts[i];
 
 			if (vpd->index >= 0) {
@@ -1217,9 +1204,10 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 			BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
 			OUT_RINGp (chan, vp->insns[i].data, 4);
 		}
+		vp->clip_nr = -1;
 	}
 
-	if(nvfx->dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
+	if(nvfx->dirty & (NVFX_NEW_VERTPROG))
 	{
 		WAIT_RING(chan, 6);
 		OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
@@ -1228,8 +1216,6 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 			OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 1));
 			OUT_RING(chan, vp->ir);
 		}
-		OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
-		OUT_RING(chan, vp->clip_ctrl);
 	}
 
 	return TRUE;
@@ -1238,27 +1224,15 @@ nvfx_vertprog_validate(struct nvfx_context *nvfx)
 void
 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
 {
-	vp->translated = FALSE;
-
-	if (vp->nr_insns) {
+	if (vp->nr_insns)
 		FREE(vp->insns);
-		vp->insns = NULL;
-		vp->nr_insns = 0;
-	}
 
-	if (vp->nr_consts) {
+	if (vp->nr_consts)
 		FREE(vp->consts);
-		vp->consts = NULL;
-		vp->nr_consts = 0;
-	}
 
 	nouveau_resource_free(&vp->exec);
-	vp->exec_start = 0;
 	nouveau_resource_free(&vp->data);
-	vp->data_start = 0;
-	vp->data_start_min = 0;
 
-	vp->ir = vp->or = vp->clip_ctrl = 0;
 	util_dynarray_fini(&vp->branch_relocs);
 	util_dynarray_fini(&vp->const_relocs);
 }
-- 
cgit v1.2.3


From 2e215bc28f71d6b556ba65e6c4e26654782e1844 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 23 Aug 2010 15:20:31 +0200
Subject: nvfx: match Gallium's gl_PointCoord brokenness

Gallium always puts gl_PointCoord in GENERIC[0] if
point_quad_rasterization is enabled.

This is silly, but for now it makes mesa-demos/glsl/pointcoord work.
---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 23a85c9342..049b814d49 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -1181,8 +1181,11 @@ nvfx_fragprog_validate(struct nvfx_context *nvfx)
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
 	struct nvfx_vertex_program* vp;
-	unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
-	// TODO: correct or flipped?
+	/* Gallium always puts the point coord in GENERIC[0]
+	 * TODO: this is wrong, Gallium needs to be fixed
+	 */
+	unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * (nvfx->rasterizer->pipe.sprite_coord_enable | 1);
+
 	boolean emulate_sprite_flipping = sprite_coord_enable && nvfx->rasterizer->pipe.sprite_coord_mode;
 	unsigned key = emulate_sprite_flipping;
 	struct nvfx_fragment_program* fp;
-- 
cgit v1.2.3


From c907b947130c884de09e48e1ecbeecc9afc9f75b Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 23 Aug 2010 16:43:04 +0200
Subject: nvfx: emit bo relocations only when needed

Should improve performance, possibly significantly.
---
 src/gallium/drivers/nvfx/nvfx_context.c    |  6 ++++--
 src/gallium/drivers/nvfx/nvfx_context.h    | 28 ++++++++++++++++++++++++++--
 src/gallium/drivers/nvfx/nvfx_fragprog.c   |  3 +++
 src/gallium/drivers/nvfx/nvfx_fragtex.c    |  2 ++
 src/gallium/drivers/nvfx/nvfx_screen.c     | 11 +++++++++++
 src/gallium/drivers/nvfx/nvfx_state_emit.c | 30 ++++++++++++++----------------
 src/gallium/drivers/nvfx/nvfx_state_fb.c   |  2 ++
 src/gallium/drivers/nvfx/nvfx_vbo.c        |  3 +++
 8 files changed, 65 insertions(+), 20 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_context.c b/src/gallium/drivers/nvfx/nvfx_context.c
index 2f775f92cf..5a2fa14c88 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.c
+++ b/src/gallium/drivers/nvfx/nvfx_context.c
@@ -46,6 +46,9 @@ nvfx_destroy(struct pipe_context *pipe)
 	if (nvfx->draw)
 		draw_destroy(nvfx->draw);
 
+	if(nvfx->screen->cur_ctx == nvfx)
+		nvfx->screen->cur_ctx = NULL;
+
 	FREE(nvfx);
 }
 
@@ -72,8 +75,6 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	nvfx->pipe.clear = nvfx_clear;
 	nvfx->pipe.flush = nvfx_flush;
 
-	screen->base.channel->user_private = nvfx;
-
 	nvfx->is_nv4x = screen->is_nv4x;
 	/* TODO: it seems that nv30 might have fixed function clipping usable with vertex programs
 	 * However, my code for that doesn't work, so use vp clipping for all cards, which works.
@@ -103,6 +104,7 @@ nvfx_create(struct pipe_screen *pscreen, void *priv)
 	nvfx->hw_pointsprite_control = -1;
 	nvfx->hw_vp_output = -1;
 	nvfx->use_vertex_buffers = -1;
+	nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 
 	LIST_INITHEAD(&nvfx->render_cache);
 
diff --git a/src/gallium/drivers/nvfx/nvfx_context.h b/src/gallium/drivers/nvfx/nvfx_context.h
index 680f4c6ce0..4c654bfa8b 100644
--- a/src/gallium/drivers/nvfx/nvfx_context.h
+++ b/src/gallium/drivers/nvfx/nvfx_context.h
@@ -47,6 +47,13 @@
 #define NVFX_NEW_INDEX	(1 << 16)
 #define NVFX_NEW_SPRITE  (1 << 17)
 
+#define NVFX_RELOCATE_FRAMEBUFFER (1 << 0)
+#define NVFX_RELOCATE_FRAGTEX (1 << 1)
+#define NVFX_RELOCATE_FRAGPROG (1 << 2)
+#define NVFX_RELOCATE_VTXBUF (1 << 3)
+#define NVFX_RELOCATE_IDXBUF (1 << 4)
+#define NVFX_RELOCATE_ALL 0x1f
+
 struct nvfx_rasterizer_state {
 	struct pipe_rasterizer_state pipe;
 	unsigned sb_len;
@@ -199,6 +206,8 @@ struct nvfx_context {
 	int hw_pointsprite_control;
 	int hw_vp_output;
 	struct nvfx_fragment_program* hw_fragprog;
+
+	unsigned relocs_needed;
 };
 
 static INLINE struct nvfx_context *
@@ -290,10 +299,25 @@ extern void nvfx_state_sr_validate(struct nvfx_context *nvfx);
 extern void nvfx_state_zsa_validate(struct nvfx_context *nvfx);
 
 /* nvfx_state_emit.c */
-extern void nvfx_state_relocate(struct nvfx_context *nvfx);
+extern void nvfx_state_relocate(struct nvfx_context *nvfx, unsigned relocs);
 extern boolean nvfx_state_validate(struct nvfx_context *nvfx);
 extern boolean nvfx_state_validate_swtnl(struct nvfx_context *nvfx);
-extern void nvfx_state_emit(struct nvfx_context *nvfx);
+
+static inline void
+nvfx_state_emit(struct nvfx_context *nvfx)
+{
+        unsigned relocs = NVFX_RELOCATE_FRAMEBUFFER | NVFX_RELOCATE_FRAGTEX | NVFX_RELOCATE_FRAGPROG;
+        if (nvfx->render_mode == HW)
+        {
+                relocs |= NVFX_RELOCATE_VTXBUF;
+                if(nvfx->use_index_buffer)
+                        relocs |= NVFX_RELOCATE_IDXBUF;
+        }
+
+        relocs &= nvfx->relocs_needed;
+        if(relocs)
+                nvfx_state_relocate(nvfx, relocs);
+}
 
 /* nvfx_transfer.c */
 extern void nvfx_init_transfer_functions(struct pipe_context *pipe);
diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 049b814d49..7caddfab70 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -1471,6 +1471,8 @@ update:
 			nvfx->hw_pointsprite_control = pointsprite_control;
 		}
 	}
+
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
 }
 
 void
@@ -1487,6 +1489,7 @@ nvfx_fragprog_relocate(struct nvfx_context *nvfx)
 	OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
 		      NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
 		      NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
 }
 
 void
diff --git a/src/gallium/drivers/nvfx/nvfx_fragtex.c b/src/gallium/drivers/nvfx/nvfx_fragtex.c
index 00c47be76a..6503c7afcb 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragtex.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragtex.c
@@ -205,6 +205,7 @@ nvfx_fragtex_validate(struct nvfx_context *nvfx)
 		}
 	}
 	nvfx->dirty_samplers = 0;
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGTEX;
 }
 
 void
@@ -231,6 +232,7 @@ nvfx_fragtex_relocate(struct nvfx_context *nvfx)
 		OUT_RELOC(chan, bo, nvfx->hw_txf[unit], tex_flags | NOUVEAU_BO_OR | NOUVEAU_BO_DUMMY,
 				NV34TCL_TX_FORMAT_DMA0, NV34TCL_TX_FORMAT_DMA1);
 	}
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGTEX;
 }
 
 void
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index 72cb5239b5..99b4d8b58c 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -377,6 +377,14 @@ nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 	return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 }
 
+static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
+{
+	struct nvfx_screen* screen = chan->user_private;
+	struct nvfx_context* nvfx = screen->cur_ctx;
+	if(nvfx)
+		nvfx->relocs_needed = NVFX_RELOCATE_ALL;
+}
+
 struct pipe_screen *
 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 {
@@ -398,6 +406,9 @@ nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 		return NULL;
 	}
 	chan = screen->base.channel;
+	screen->cur_ctx = NULL;
+	chan->user_private = screen;
+	chan->flush_notify = nvfx_channel_flush_notify;
 
 	pscreen->winsys = ws;
 	pscreen->destroy = nvfx_screen_destroy;
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index c43a75aaa2..cfcb0f7ef6 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -20,6 +20,7 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 		nvfx->hw_pointsprite_control = -1;
 		nvfx->hw_vp_output = -1;
 		nvfx->screen->cur_ctx = nvfx;
+		nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 	}
 
 	/* These can trigger use the of 3D engine to copy temporaries.
@@ -244,12 +245,12 @@ nvfx_state_validate_common(struct nvfx_context *nvfx)
 	return TRUE;
 }
 
-void
-nvfx_state_emit(struct nvfx_context *nvfx)
+inline void
+nvfx_state_relocate(struct nvfx_context *nvfx, unsigned relocs)
 {
 	struct nouveau_channel* chan = nvfx->screen->base.channel;
 	/* we need to ensure there is enough space to output relocations in one go */
-	unsigned max_relocs = 0
+	const unsigned max_relocs = 0
 	      + 16 /* vertex buffers, incl. dma flag */
 	      + 2 /* index buffer plus format+dma flag */
 	      + 2 * 5 /* 4 cbufs + zsbuf, plus dma objects */
@@ -257,22 +258,19 @@ nvfx_state_emit(struct nvfx_context *nvfx)
 	      + 2 * 4 /* vertex textures plus format+dma flag */
 	      + 1 /* fragprog incl dma flag */
 	      ;
+
 	MARK_RING(chan, max_relocs * 2, max_relocs * 2);
-	nvfx_state_relocate(nvfx);
-}
 
-void
-nvfx_state_relocate(struct nvfx_context *nvfx)
-{
-	nvfx_framebuffer_relocate(nvfx);
-	nvfx_fragtex_relocate(nvfx);
-	nvfx_fragprog_relocate(nvfx);
-	if (nvfx->render_mode == HW)
-	{
+	if(relocs & NVFX_RELOCATE_FRAMEBUFFER)
+		nvfx_framebuffer_relocate(nvfx);
+	if(relocs & NVFX_RELOCATE_FRAGTEX)
+		nvfx_fragtex_relocate(nvfx);
+	if(relocs & NVFX_RELOCATE_FRAGPROG)
+		nvfx_fragprog_relocate(nvfx);
+	if(relocs & NVFX_RELOCATE_VTXBUF)
 		nvfx_vbo_relocate(nvfx);
-		if(nvfx->use_index_buffer)
-			nvfx_idxbuf_relocate(nvfx);
-	}
+	if(relocs & NVFX_RELOCATE_IDXBUF)
+		nvfx_idxbuf_relocate(nvfx);
 }
 
 boolean
diff --git a/src/gallium/drivers/nvfx/nvfx_state_fb.c b/src/gallium/drivers/nvfx/nvfx_state_fb.c
index 3db9cec905..3b869d43a1 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_fb.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_fb.c
@@ -278,6 +278,7 @@ nvfx_framebuffer_validate(struct nvfx_context *nvfx, unsigned prepare_result)
 		OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_TX_ORIGIN, 1));
 		OUT_RING(chan, 0);
 	}
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER;
 }
 
 void
@@ -307,4 +308,5 @@ nvfx_framebuffer_relocate(struct nvfx_context *nvfx)
 	DO(NV40, 3);
 
 	DO_(nvfx->hw_zeta, NV34, ZETA);
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAMEBUFFER;
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_vbo.c b/src/gallium/drivers/nvfx/nvfx_vbo.c
index 21d6e0e6f8..e6e9a8f2e4 100644
--- a/src/gallium/drivers/nvfx/nvfx_vbo.c
+++ b/src/gallium/drivers/nvfx/nvfx_vbo.c
@@ -334,6 +334,7 @@ nvfx_vbo_validate(struct nvfx_context *nvfx)
 	OUT_RING(chan, 0);
 
 	nvfx->hw_vtxelt_nr = nvfx->vtxelt->num_elements;
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
 	return TRUE;
 }
 
@@ -362,6 +363,7 @@ nvfx_vbo_relocate(struct nvfx_context *nvfx)
 				vb_flags | NOUVEAU_BO_LOW | NOUVEAU_BO_OR,
 				0, NV34TCL_VTXBUF_ADDRESS_DMA1);
 	}
+        nvfx->relocs_needed &=~ NVFX_RELOCATE_VTXBUF;
 }
 
 static void
@@ -382,6 +384,7 @@ nvfx_idxbuf_emit(struct nvfx_context* nvfx, unsigned ib_flags)
 	OUT_RELOC(chan, bo, nvfx->idxbuf.offset + 1, ib_flags | NOUVEAU_BO_LOW, 0, 0);
 	OUT_RELOC(chan, bo, ib_format, ib_flags | NOUVEAU_BO_OR,
 			0, NV34TCL_IDXBUF_FORMAT_DMA1);
+	nvfx->relocs_needed &=~ NVFX_RELOCATE_IDXBUF;
 }
 
 void
-- 
cgit v1.2.3


From 4ab1001ac28b5716e1b103df44d04b8a8ddd2375 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Mon, 23 Aug 2010 20:27:40 +0200
Subject: nvfx: improve fp temp accounting

---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 7caddfab70..7f6b3f6599 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -21,6 +21,7 @@ struct nvfx_fpc {
 	struct nvfx_pipe_fragment_program* pfp;
 	struct nvfx_fragment_program *fp;
 
+	unsigned max_temps;
 	unsigned long long r_temps;
 	unsigned long long r_temps_discard;
 	struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
@@ -51,9 +52,9 @@ struct nvfx_fpc {
 static INLINE struct nvfx_reg
 temp(struct nvfx_fpc *fpc)
 {
-	int idx = ffsll(~fpc->r_temps) - 1;
+	int idx = __builtin_ctzll(~fpc->r_temps);
 
-	if (idx < 0) {
+	if (idx >= fpc->max_temps) {
 		NOUVEAU_ERR("out of temps!!\n");
 		assert(0);
 		return nvfx_reg(NVFXSR_TEMP, 0);
@@ -1022,6 +1023,7 @@ nvfx_fragprog_translate(struct nvfx_context *nvfx,
 	if (!fpc)
 		goto out_err;
 
+	fpc->max_temps = nvfx->is_nv4x ? 48 : 32;
 	fpc->pfp = pfp;
 	fpc->fp = fp;
 	fpc->num_regs = 2;
-- 
cgit v1.2.3


From bcf7f66a934ebd9c91da90d6e1f9b169c33c746c Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Mon, 23 Aug 2010 15:39:39 -0400
Subject: r600g: export one component per pixel + r7xx uncompression shader

We need to always at least export one component (wether it's depth
or color. Add valid r7xx shader program for depth decompression.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c   | 58 +++++++++++++++++++++++++++++++---
 src/gallium/drivers/r600/r600_screen.c | 23 ++++++++++++++
 src/gallium/drivers/r600/r600_screen.h |  7 ++++
 src/gallium/drivers/r600/r600_shader.c |  4 +++
 src/gallium/drivers/r600/r600_state.c  |  2 +-
 5 files changed, 89 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 1a975da4bd..72175fbbd5 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -242,7 +242,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 {
 	struct radeon_state *rstate;
 	struct radeon_bo *bo;
-	u32 shader_bc[] = {
+	u32 shader_bc_r600[] = {
 		0x00000004, 0x81000400,
 		0x00000008, 0xA01C0000,
 		0xC001A03C, 0x94000688,
@@ -260,6 +260,24 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 		0x00000802, 0x40801910,
 		0x80000C02, 0x60801910
 	};
+	u32 shader_bc_r700[] = {
+		0x00000004, 0x81000400,
+		0x00000008, 0xA01C0000,
+		0xC001A03C, 0x94000688,
+		0xC0024000, 0x94200688,
+		0x7C000000, 0x002D1001,
+		0x00080000, 0x00000000,
+		0x7C000100, 0x002D1002,
+		0x00080000, 0x00000000,
+		0x00000001, 0x00600C90,
+		0x00000401, 0x20600C90,
+		0x00000801, 0x40600C90,
+		0x80000C01, 0x60600C90,
+		0x00000002, 0x00800C90,
+		0x00000402, 0x20800C90,
+		0x00000802, 0x40800C90,
+		0x80000C02, 0x60800C90
+	};
 
 	/* simple shader */
 	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
@@ -270,7 +288,19 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 		radeon_bo_decref(rscreen->rw, bo);
 		return NULL;
 	}
-	memcpy(bo->data, shader_bc, 128);
+	switch (rscreen->chip_class) {
+	case R600:
+		memcpy(bo->data, shader_bc_r600, 128);
+		break;
+	case R700:
+		memcpy(bo->data, shader_bc_r700, 128);
+		break;
+	default:
+		R600_ERR("unsupported chip family\n");
+		radeon_bo_unmap(rscreen->rw, bo);
+		radeon_bo_decref(rscreen->rw, bo);
+		return NULL;
+	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
 	rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
@@ -303,7 +333,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 {
 	struct radeon_state *rstate;
 	struct radeon_bo *bo;
-	u32 shader_bc[] = {
+	u32 shader_bc_r600[] = {
 		0x00000002, 0xA00C0000,
 		0xC0008000, 0x94200688,
 		0x00000000, 0x00201910,
@@ -311,6 +341,14 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 		0x00000800, 0x40201910,
 		0x80000C00, 0x60201910
 	};
+	u32 shader_bc_r700[] = {
+		0x00000002, 0xA00C0000,
+		0xC0008000, 0x94200688,
+		0x00000000, 0x00200C90,
+		0x00000400, 0x20200C90,
+		0x00000800, 0x40200C90,
+		0x80000C00, 0x60200C90
+	};
 
 	/* simple shader */
 	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
@@ -321,7 +359,19 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	if (radeon_bo_map(rscreen->rw, bo)) {
 		return NULL;
 	}
-	memcpy(bo->data, shader_bc, 48);
+	switch (rscreen->chip_class) {
+	case R600:
+		memcpy(bo->data, shader_bc_r600, 48);
+		break;
+	case R700:
+		memcpy(bo->data, shader_bc_r700, 48);
+		break;
+	default:
+		R600_ERR("unsupported chip family\n");
+		radeon_bo_unmap(rscreen->rw, bo);
+		radeon_bo_decref(rscreen->rw, bo);
+		return NULL;
+	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
 	rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index cdaca9ed7d..1358432957 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -234,11 +234,34 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
 struct pipe_screen *r600_screen_create(struct radeon *rw)
 {
 	struct r600_screen* rscreen;
+	enum radeon_family family = radeon_get_family(rw);
 
 	rscreen = CALLOC_STRUCT(r600_screen);
 	if (rscreen == NULL) {
 		return NULL;
 	}
+
+	switch (family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+		rscreen->chip_class = R600;
+		break;
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		rscreen->chip_class = R700;
+		break;
+	default:
+		FREE(rscreen);
+		return NULL;
+	}
 	rscreen->rw = rw;
 	rscreen->screen.winsys = (struct pipe_winsys*)rw;
 	rscreen->screen.destroy = r600_destroy_screen;
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 5e82ac8e23..438976f654 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -42,9 +42,16 @@ struct r600_transfer {
 	struct pipe_resource		*linear_texture;
 };
 
+enum chip_class {
+	R600,
+	R700,
+	EVERGREEN,
+};
+
 struct r600_screen {
 	struct pipe_screen		screen;
 	struct radeon			*rw;
+	enum chip_class			chip_class;
 };
 
 static INLINE struct r600_screen *r600_screen(struct pipe_screen *screen)
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 5cdbe2bfe8..b20a5a11be 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -191,6 +191,10 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 			num_cout++;
 		}
 	}
+	if (!exports_ps) {
+		/* always at least export 1 component per pixel */
+		exports_ps = 2;
+	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
 							S_0286CC_PERSP_GRADIENT_ENA(1);
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index c3ef6267b2..12a61cacda 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -775,7 +775,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
 	rtex->tilled = 1;
 	rtex->array_mode = 2;
-	rtex->tile_type = 0;
+	rtex->tile_type = 1;
 	rtex->depth = 1;
 	rbuffer = &rtex->resource;
 
-- 
cgit v1.2.3


From 6fb39f0fa2cad668fd6c49d0b739c33954a6946c Mon Sep 17 00:00:00 2001
From: Henri Verbeet <hverbeet@gmail.com>
Date: Mon, 23 Aug 2010 21:13:59 +0200
Subject: r600g: Add support for PIPE_CAP_DEPTH_CLAMP.

---
 src/gallium/drivers/r600/r600_screen.c | 2 +-
 src/gallium/drivers/r600/r600_state.c  | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_screen.c b/src/gallium/drivers/r600/r600_screen.c
index 1358432957..a047a49a6c 100644
--- a/src/gallium/drivers/r600/r600_screen.c
+++ b/src/gallium/drivers/r600/r600_screen.c
@@ -69,6 +69,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_TEXTURE_SWIZZLE:
 	case PIPE_CAP_INDEP_BLEND_ENABLE:
 	case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
+	case PIPE_CAP_DEPTH_CLAMP:
 		return 1;
 
 	/* Unsupported features (boolean caps). */
@@ -77,7 +78,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_STREAM_OUTPUT:
 	case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
 	case PIPE_CAP_GEOMETRY_SHADER4:
-	case PIPE_CAP_DEPTH_CLAMP: /* FIXME allow this */
 		return 0;
 
 	/* Texturing. */
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 12a61cacda..b5e5346163 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -861,9 +861,10 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		}
 	}
 	rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = 0;
-	if (clip && clip->nr) {
+	if (clip) {
 		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] = S_028810_PS_UCP_MODE(3) | ((1 << clip->nr) - 1);
-		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_CLIP_DISABLE(clip->depth_clamp);
+		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_NEAR_DISABLE(clip->depth_clamp);
+		rstate->states[R600_RASTERIZER__PA_CL_CLIP_CNTL] |= S_028810_ZCLIP_FAR_DISABLE(clip->depth_clamp);
 	}
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] =
 		S_028814_PROVOKING_VTX_LAST(prov_vtx) |
-- 
cgit v1.2.3


From c60c2d3a64a54ff28dd772e51b1848aca6b42316 Mon Sep 17 00:00:00 2001
From: Luca Barbieri <luca@luca-barbieri.com>
Date: Tue, 24 Aug 2010 00:03:28 +0200
Subject: nvfx: don't emit dummy commands on nv30

Should fix errors on the original nv30, reported by pmdata.
---
 src/gallium/drivers/nvfx/nvfx_push.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_push.c b/src/gallium/drivers/nvfx/nvfx_push.c
index 49d518e2eb..ffe7e98357 100644
--- a/src/gallium/drivers/nvfx/nvfx_push.c
+++ b/src/gallium/drivers/nvfx/nvfx_push.c
@@ -368,11 +368,15 @@ nvfx_push_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 			if(max_verts >= 16)
 			{
 				/* XXX: any command a lot of times seems to (mostly) fix corruption that would otherwise happen */
-				int i;
-				for(i = 0; i < 32; ++i)
+				/* this seems to cause issues on nv3x, and also be unneeded there */
+				if(nvfx->is_nv4x)
 				{
-					OUT_RING(chan, RING_3D(0x1dac, 1));
-					OUT_RING(chan, 0);
+					int i;
+					for(i = 0; i < 32; ++i)
+					{
+						OUT_RING(chan, RING_3D(0x1dac, 1));
+						OUT_RING(chan, 0);
+					}
 				}
 
 				OUT_RING(chan, RING_3D(NV34TCL_VERTEX_BEGIN_END, 1));
-- 
cgit v1.2.3


From 87f44d5723ebb3a2efe0dddc1a6edb6536adea4d Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 24 Aug 2010 09:18:32 +1000
Subject: r600g: add CMP support.

ported from r600c, fixes fp-cmp, glsl1-sqrt*
---
 src/gallium/drivers/r600/r600_shader.c | 51 +++++++++++++++++++++++++++++++++-
 1 file changed, 50 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index b20a5a11be..e8f7e09d96 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1446,6 +1446,55 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
 	return tgsi_helper_copy(ctx, inst);
 }
 
+static int tgsi_cmp(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
+	struct r600_bc_alu alu;
+	int use_temp = 0;
+	int i, r;
+
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+
+	if (inst->Dst[0].Register.WriteMask != 0xf)
+		use_temp = 1;
+
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGE;
+		alu.src[0] = r600_src[0];
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
+
+		alu.src[1] = r600_src[2];
+		alu.src[1].chan = tgsi_chan(&inst->Src[2], i);
+
+		alu.src[2] = r600_src[1];
+		alu.src[2].chan = tgsi_chan(&inst->Src[1], i);
+
+		if (use_temp)
+			alu.dst.sel = ctx->temp_reg;
+		else {
+			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+			if (r)
+				return r;
+		}
+		alu.dst.chan = i;
+		alu.dst.write = 1;
+		alu.is_op3 = 1;
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}       
+	if (use_temp)
+		return tgsi_helper_copy(ctx, inst);
+	return 0;
+}
+
+
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_MOV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
@@ -1516,7 +1565,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_CAL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_RET,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SSG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
-	{TGSI_OPCODE_CMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
 	{TGSI_OPCODE_SCS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
 	{TGSI_OPCODE_NRM,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-- 
cgit v1.2.3


From 0e6a02d29915db2ca460206656ab517ddaf0b455 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 24 Aug 2010 09:56:22 +1000
Subject: r600g: add XPD support

ported from r600c.
---
 src/gallium/drivers/r600/r600_shader.c | 125 ++++++++++++++++++++++++++++++++-
 1 file changed, 124 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index e8f7e09d96..b2d1a1bf01 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1494,6 +1494,129 @@ static int tgsi_cmp(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_xpd(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
+	struct r600_bc_alu alu;
+	uint32_t use_temp = 0;
+	int i, r;
+
+	if (inst->Dst[0].Register.WriteMask != 0xf)
+		use_temp = 1;
+
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+	
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+
+		alu.src[0] = r600_src[0];
+		switch (i) {
+		case 0:
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
+			break;
+		case 1:
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+			break;
+		case 2:
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
+			break;
+		case 3:
+			alu.src[0].sel = V_SQ_ALU_SRC_0;
+			alu.src[0].chan = i;
+		}
+
+		alu.src[1] = r600_src[1];
+		switch (i) {
+		case 0:
+			alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
+			break;
+		case 1:
+			alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
+			break;
+		case 2:
+			alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
+			break;
+		case 3:
+			alu.src[1].sel = V_SQ_ALU_SRC_0;
+			alu.src[1].chan = i;
+		}
+
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = i;
+		alu.dst.write = 1;
+
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
+
+		alu.src[0] = r600_src[0];
+		switch (i) {
+		case 0:
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
+			break;
+		case 1:
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], 2);
+			break;
+		case 2:
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+			break;
+		case 3:
+			alu.src[0].sel = V_SQ_ALU_SRC_0;
+			alu.src[0].chan = i;
+		}
+
+		alu.src[1] = r600_src[1];
+		switch (i) {
+		case 0:
+			alu.src[1].chan = tgsi_chan(&inst->Src[1], 2);
+			break;
+		case 1:
+			alu.src[1].chan = tgsi_chan(&inst->Src[1], 0);
+			break;
+		case 2:
+			alu.src[1].chan = tgsi_chan(&inst->Src[1], 1);
+			break;
+		case 3:
+			alu.src[1].sel = V_SQ_ALU_SRC_0;
+			alu.src[1].chan = i;
+		}
+
+		alu.src[2].sel = ctx->temp_reg;
+		alu.src[2].neg = 1;
+		alu.src[2].chan = i;
+
+		if (use_temp)
+			alu.dst.sel = ctx->temp_reg;
+		else {
+			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+			if (r)
+				return r;
+		}
+		alu.dst.chan = i;
+		alu.dst.write = 1;
+		alu.is_op3 = 1;
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	if (use_temp)
+		return tgsi_helper_copy(ctx, inst);
+	return 0;
+}
+
 
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -1529,7 +1652,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
-	{TGSI_OPCODE_XPD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_XPD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_xpd},
 	/* gap */
 	{32,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
-- 
cgit v1.2.3


From b48f20dab8a93fe187f6e6d9d7544f07ed8148db Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Mon, 23 Aug 2010 22:15:24 -0700
Subject: r300g: Remove unused variable.

Fixes this GCC warning.
r300_render.c: In function 'r300_draw_flush_vbuf':
r300_render.c:988: warning: unused variable 'r300_render'
---
 src/gallium/drivers/r300/r300_render.c | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c
index 73447057bb..fc3844f788 100644
--- a/src/gallium/drivers/r300/r300_render.c
+++ b/src/gallium/drivers/r300/r300_render.c
@@ -985,8 +985,6 @@ struct draw_stage* r300_draw_stage(struct r300_context* r300)
 
 void r300_draw_flush_vbuf(struct r300_context *r300)
 {
-    struct r300_render *r300render;
-
     pipe_resource_reference(&r300->vbo, NULL);
     r300->draw_vbo_size = 0;
 }
-- 
cgit v1.2.3


From b018ea19a39cb0e5326e92c88a55ff220e463404 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Mon, 23 Aug 2010 23:58:57 -0700
Subject: nvfx: Remove unnecessary headers.

---
 src/gallium/drivers/nvfx/nvfx_miptree.c  | 2 --
 src/gallium/drivers/nvfx/nvfx_resource.c | 1 -
 src/gallium/drivers/nvfx/nvfx_surface.c  | 1 -
 3 files changed, 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 0532b43ef0..46e1f9e4f4 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -10,8 +10,6 @@
 #include "nouveau/nouveau_screen.h"
 #include "nvfx_screen.h"
 #include "nvfx_resource.h"
-#include "nvfx_transfer.h"
-#include "nv04_2d.h"
 
 static void
 nvfx_miptree_choose_format(struct nvfx_miptree *mt)
diff --git a/src/gallium/drivers/nvfx/nvfx_resource.c b/src/gallium/drivers/nvfx/nvfx_resource.c
index 3a46e0a7a5..39ae893f1b 100644
--- a/src/gallium/drivers/nvfx/nvfx_resource.c
+++ b/src/gallium/drivers/nvfx/nvfx_resource.c
@@ -2,7 +2,6 @@
 #include "pipe/p_context.h"
 #include "util/u_staging.h"
 #include "nvfx_resource.h"
-#include "nvfx_transfer.h"
 #include "nouveau/nouveau_screen.h"
 
 static unsigned int
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
index 806f1a22e6..f6cc985673 100644
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ b/src/gallium/drivers/nvfx/nvfx_surface.c
@@ -32,7 +32,6 @@
 #include "util/u_math.h"
 #include "util/u_memory.h"
 #include "util/u_pack_color.h"
-#include "util/u_rect.h"
 #include "util/u_blitter.h"
 
 #include "nouveau/nouveau_winsys.h"
-- 
cgit v1.2.3


From 547e8675583053f15dc62a073b52f4722e7d0f5f Mon Sep 17 00:00:00 2001
From: Henri Verbeet <hverbeet@gmail.com>
Date: Tue, 24 Aug 2010 20:51:20 +0200
Subject: r600g: Add support for PIPE_FORMAT_R32_FLOAT.

---
 src/gallium/drivers/r600/r600_state_inlines.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index 927c342bb5..d67d4be6f8 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -264,6 +264,9 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 	case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 		return V_0280A0_COLOR_8_24;
 
+	case PIPE_FORMAT_R32_FLOAT:
+		return V_0280A0_COLOR_32_FLOAT;
+
 		/* 64-bit buffers. */
 	case PIPE_FORMAT_R16G16B16A16_UNORM:
 	case PIPE_FORMAT_R16G16B16A16_SNORM:
-- 
cgit v1.2.3


From 57e66ed9b1f6128dc8225477dcb2faa54a4960ac Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Tue, 24 Aug 2010 17:40:50 -0700
Subject: nvfx: Initialize variables on error path.

---
 src/gallium/drivers/nvfx/nv04_2d.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nv04_2d.c b/src/gallium/drivers/nvfx/nv04_2d.c
index 3761002bcb..c05312219b 100644
--- a/src/gallium/drivers/nvfx/nv04_2d.c
+++ b/src/gallium/drivers/nvfx/nv04_2d.c
@@ -1126,7 +1126,11 @@ nv04_region_fill_gdirect(struct nv04_2d_context *ctx, struct nv04_region* dst, i
 		cs2d_format = NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
 	}
 	else
+	{
 		assert(0);
+		gdirect_format = 0;
+		cs2d_format = 0;
+	}
 
 	MARK_RING (chan, 15, 4);
 	BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
-- 
cgit v1.2.3


From cb925970eeade17016f59497d2123e4e8a447164 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Tue, 24 Aug 2010 17:16:44 +0200
Subject: r300g: reset the index bias to 0 at the end of CS

---
 src/gallium/drivers/r300/r300_context.h | 4 +++-
 src/gallium/drivers/r300/r300_emit.c    | 2 ++
 src/gallium/drivers/r300/r300_flush.c   | 3 +++
 src/gallium/drivers/r300/r300_render.c  | 8 ++++----
 4 files changed, 12 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
index 030bb2314f..2b665ba2b5 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -650,8 +650,10 @@ void r300_translate_index_buffer(struct r300_context *r300,
 /* r300_render_stencilref.c */
 void r300_plug_in_stencil_ref_fallback(struct r300_context *r300);
 
-/* r300 render */
+/* r300_render.c */
 void r300_draw_flush_vbuf(struct r300_context *r300);
+boolean r500_index_bias_supported(struct r300_context *r300);
+void r500_emit_index_bias(struct r300_context *r300, int index_bias);
 
 /* r300_state.c */
 enum r300_fb_state_change {
diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index d0fd45349e..87d995010e 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -1219,6 +1219,8 @@ unsigned r300_get_num_cs_end_dwords(struct r300_context *r300)
     /* Emitted in flush. */
     dwords += 26; /* emit_query_end */
     dwords += r300->hyperz_state.size + 2; /* emit_hyperz_end + zcache flush */
+    if (r500_index_bias_supported(r300))
+        dwords += 2;
 
     return dwords;
 }
diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c
index f00707b066..2b5d2e42ba 100644
--- a/src/gallium/drivers/r300/r300_flush.c
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -45,9 +45,12 @@ static void r300_flush(struct pipe_context* pipe,
 
     if (r300->draw)
 	r300_draw_flush_vbuf(r300);
+
     if (r300->dirty_hw) {
         r300_emit_hyperz_end(r300);
         r300_emit_query_end(r300);
+        if (r500_index_bias_supported(r300))
+            r500_emit_index_bias(r300, 0);
 
         r300->flush_counter++;
         r300->rws->cs_flush(r300->cs);
diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c
index fc3844f788..e08335a105 100644
--- a/src/gallium/drivers/r300/r300_render.c
+++ b/src/gallium/drivers/r300/r300_render.c
@@ -118,13 +118,13 @@ static uint32_t r300_provoking_vertex_fixes(struct r300_context *r300,
     return color_control;
 }
 
-static boolean index_bias_supported(struct r300_context *r300)
+boolean r500_index_bias_supported(struct r300_context *r300)
 {
     return r300->screen->caps.is_r500 &&
            r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0);
 }
 
-static void r500_emit_index_bias(struct r300_context *r300, int index_bias)
+void r500_emit_index_bias(struct r300_context *r300, int index_bias)
 {
     CS_LOCALS(r300);
 
@@ -199,7 +199,7 @@ static void r300_prepare_for_rendering(struct r300_context *r300,
     boolean emit_aos       = flags & PREP_EMIT_AOS;
     boolean emit_aos_swtcl = flags & PREP_EMIT_AOS_SWTCL;
     boolean indexed        = flags & PREP_INDEXED;
-    boolean hw_index_bias  = index_bias_supported(r300);
+    boolean hw_index_bias  = r500_index_bias_supported(r300);
 
     /* Add dirty state, index offset, and AOS. */
     if (first_draw) {
@@ -506,7 +506,7 @@ static void r300_draw_range_elements(struct pipe_context* pipe,
         translate = TRUE;
     }
 
-    if (indexBias && !index_bias_supported(r300)) {
+    if (indexBias && !r500_index_bias_supported(r300)) {
         r300_split_index_bias(r300, indexBias, &buffer_offset, &index_offset);
     }
 
-- 
cgit v1.2.3


From 2eeaf773fdd58c176f7cdbcd05b75ad3a5ecab4c Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Mon, 23 Aug 2010 05:58:08 +0200
Subject: r300g: fix indentation

---
 src/gallium/drivers/r300/r300_fs.c    | 10 +++++-----
 src/gallium/drivers/r300/r300_state.c |  6 +++---
 2 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_fs.c b/src/gallium/drivers/r300/r300_fs.c
index 2a0c30620a..315d5b85f7 100644
--- a/src/gallium/drivers/r300/r300_fs.c
+++ b/src/gallium/drivers/r300/r300_fs.c
@@ -257,17 +257,17 @@ static void r300_emit_fs_code_to_buffer(
         shader->cb_code_size = 19 +
                                ((code->inst_end + 1) * 6) +
                                imm_count * 7 +
-			       code->int_constant_count * 2;
+                               code->int_constant_count * 2;
 
         NEW_CB(shader->cb_code, shader->cb_code_size);
         OUT_CB_REG(R500_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
         OUT_CB_REG(R500_US_PIXSIZE, code->max_temp_idx);
         OUT_CB_REG(R500_US_FC_CTRL, code->us_fc_ctrl);
         for(i = 0; i < code->int_constant_count; i++){
-		OUT_CB_REG(R500_US_FC_INT_CONST_0 + (i * 4),
-						code->int_constants[i]);
-	}
-	OUT_CB_REG(R500_US_CODE_RANGE,
+                OUT_CB_REG(R500_US_FC_INT_CONST_0 + (i * 4),
+                                                code->int_constants[i]);
+        }
+        OUT_CB_REG(R500_US_CODE_RANGE,
                    R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(code->inst_end));
         OUT_CB_REG(R500_US_CODE_OFFSET, 0);
         OUT_CB_REG(R500_US_CODE_ADDR,
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 239edd98e3..dc0d0415cb 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -1050,11 +1050,11 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
     stuffing_enable = 0;
     if (state->sprite_coord_enable) {
         stuffing_enable = R300_GB_POINT_STUFF_ENABLE;
-	for (i = 0; i < 8; i++) {
-	    if (state->sprite_coord_enable & (1 << i))
+        for (i = 0; i < 8; i++) {
+            if (state->sprite_coord_enable & (1 << i))
                 stuffing_enable |=
                     R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (i*2));
-	}
+        }
 
         point_texcoord_left = 0.0f;
         point_texcoord_right = 1.0f;
-- 
cgit v1.2.3


From 62eb9eda1d15acc180b4e144cc14427980419d07 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Tue, 24 Aug 2010 23:05:09 +0200
Subject: r300g: clean up some mess in set_constant_buffer

---
 src/gallium/drivers/r300/r300_context.h |  2 --
 src/gallium/drivers/r300/r300_state.c   | 21 +--------------------
 2 files changed, 1 insertion(+), 22 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
index 2b665ba2b5..c596d1cba2 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -254,8 +254,6 @@ struct r300_ztop_state {
 struct r300_constant_buffer {
     /* Buffer of constants */
     uint32_t *ptr;
-    /* Total number of vec4s */
-    unsigned count;
 };
 
 /* Query object.
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index dc0d0415cb..c4e270b444 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -1795,47 +1795,28 @@ static void r300_set_constant_buffer(struct pipe_context *pipe,
     struct r300_context* r300 = r300_context(pipe);
     struct r300_constant_buffer *cbuf;
     uint32_t *mapped = r300_buffer(buf)->user_buffer;
-    int max_size = 0, max_size_bytes = 0, clamped_size = 0;
 
     switch (shader) {
         case PIPE_SHADER_VERTEX:
             cbuf = (struct r300_constant_buffer*)r300->vs_constants.state;
-            max_size = 256;
             break;
         case PIPE_SHADER_FRAGMENT:
             cbuf = (struct r300_constant_buffer*)r300->fs_constants.state;
-            if (r300->screen->caps.is_r500) {
-                max_size = 256;
-            } else {
-                max_size = 32;
-            }
             break;
         default:
             assert(0);
             return;
     }
-    max_size_bytes = max_size * 4 * sizeof(float);
 
     if (buf == NULL || buf->width0 == 0 ||
         (mapped = r300_buffer(buf)->constant_buffer) == NULL) {
-        cbuf->count = 0;
         return;
     }
 
     if (shader == PIPE_SHADER_FRAGMENT ||
         (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) {
         assert((buf->width0 % (4 * sizeof(float))) == 0);
-
-        /* Check the size of the constant buffer. */
-        /* XXX Subtract immediates and RC_STATE_* variables. */
-        if (buf->width0 > max_size_bytes) {
-            fprintf(stderr, "r300: Max size of the constant buffer is "
-                          "%i*4 floats.\n", max_size);
-        }
-
-        clamped_size = MIN2(buf->width0, max_size_bytes);
-        cbuf->count = clamped_size / (4 * sizeof(float));
-        cbuf->ptr = mapped;
+        cbuf->ptr = mapped + index*4;
     }
 
     if (shader == PIPE_SHADER_VERTEX) {
-- 
cgit v1.2.3


From abae06ac85349a30996257f29f9c52c3f687d35d Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Mon, 23 Aug 2010 05:56:48 +0200
Subject: r300g: eliminate unused constants in VS

---
 src/gallium/drivers/r300/r300_context.h |  2 ++
 src/gallium/drivers/r300/r300_emit.c    | 10 +++++++++-
 src/gallium/drivers/r300/r300_fs.c      |  5 ++---
 src/gallium/drivers/r300/r300_state.c   |  5 +++++
 src/gallium/drivers/r300/r300_vs.c      | 17 +++++++++++++----
 5 files changed, 31 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_context.h b/src/gallium/drivers/r300/r300_context.h
index c596d1cba2..8f0e86fd37 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -254,6 +254,8 @@ struct r300_ztop_state {
 struct r300_constant_buffer {
     /* Buffer of constants */
     uint32_t *ptr;
+    /* Remapping table. */
+    unsigned *remap_table;
 };
 
 /* Query object.
diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index 87d995010e..d3ca23211e 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -961,6 +961,7 @@ void r300_emit_vs_constants(struct r300_context* r300,
     unsigned count =
         ((struct r300_vertex_shader*)r300->vs_state.state)->externals_count;
     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
+    unsigned i;
     CS_LOCALS(r300);
 
     if (!count)
@@ -971,7 +972,14 @@ void r300_emit_vs_constants(struct r300_context* r300,
                (r300->screen->caps.is_r500 ?
                R500_PVS_CONST_START : R300_PVS_CONST_START));
     OUT_CS_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, count * 4);
-    OUT_CS_TABLE(buf->ptr, count * 4);
+    if (buf->remap_table){
+        for (i = 0; i < count; i++) {
+            uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
+            OUT_CS_TABLE(data, 4);
+        }
+    } else {
+        OUT_CS_TABLE(buf->ptr, count * 4);
+    }
     END_CS;
 }
 
diff --git a/src/gallium/drivers/r300/r300_fs.c b/src/gallium/drivers/r300/r300_fs.c
index 315d5b85f7..d95587b381 100644
--- a/src/gallium/drivers/r300/r300_fs.c
+++ b/src/gallium/drivers/r300/r300_fs.c
@@ -431,9 +431,8 @@ static void r300_translate_fragment_shader(
     }
 
     if (compiler.Base.Error) {
-        DBG(r300, DBG_FP, "r300 FP: Compiler Error:\n%sUsing a dummy shader"
-                " instead.\nIf there's an 'unknown opcode' message, please"
-                " file a bug report and attach this log.\n", compiler.Base.ErrorMsg);
+        fprintf(stderr, "r300 FP: Compiler Error:\n%sUsing a dummy shader"
+                " instead.\n", compiler.Base.ErrorMsg);
 
         if (shader->dummy) {
             fprintf(stderr, "r300 FP: Cannot compile the dummy shader! "
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index c4e270b444..ed39c575ce 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -1765,6 +1765,9 @@ static void r300_bind_vs_state(struct pipe_context* pipe, void* shader)
             r300->vs_constants.size = 0;
         }
 
+        ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table =
+                vs->code.constants_remap_table;
+
         r300->pvs_flush.dirty = TRUE;
     } else {
         draw_bind_vertex_shader(r300->draw,
@@ -1779,6 +1782,8 @@ static void r300_delete_vs_state(struct pipe_context* pipe, void* shader)
 
     if (r300->screen->caps.has_tcl) {
         rc_constants_destroy(&vs->code.constants);
+        if (vs->code.constants_remap_table)
+            FREE(vs->code.constants_remap_table);
     } else {
         draw_delete_vertex_shader(r300->draw,
                 (struct draw_vertex_shader*)vs->draw_vs);
diff --git a/src/gallium/drivers/r300/r300_vs.c b/src/gallium/drivers/r300/r300_vs.c
index 54c8de1241..5f8dbb28d0 100644
--- a/src/gallium/drivers/r300/r300_vs.c
+++ b/src/gallium/drivers/r300/r300_vs.c
@@ -196,6 +196,7 @@ void r300_translate_vertex_shader(struct r300_context *r300,
 {
     struct r300_vertex_program_compiler compiler;
     struct tgsi_to_rc ttr;
+    unsigned i;
 
     /* Setup the compiler */
     rc_init(&compiler.Base);
@@ -205,6 +206,7 @@ void r300_translate_vertex_shader(struct r300_context *r300,
     compiler.UserData = vs;
     compiler.Base.is_r500 = r300->screen->caps.is_r500;
     compiler.Base.max_temp_regs = 32;
+    compiler.Base.remove_unused_constants = TRUE;
 
     if (compiler.Base.Debug) {
         DBG(r300, DBG_VP, "r300: Initial vertex program\n");
@@ -227,9 +229,8 @@ void r300_translate_vertex_shader(struct r300_context *r300,
     /* Invoke the compiler */
     r3xx_compile_vertex_program(&compiler);
     if (compiler.Base.Error) {
-        DBG(r300, DBG_VP, "r300 VP: Compiler error:\n%sUsing a dummy shader"
-                " instead.\nIf there's an 'unknown opcode' message, please"
-                " file a bug report and attach this log.\n", compiler.Base.ErrorMsg);
+        fprintf(stderr, "r300 VP: Compiler error:\n%sUsing a dummy shader"
+                " instead.\n", compiler.Base.ErrorMsg);
 
         if (vs->dummy) {
             fprintf(stderr, "r300 VP: Cannot compile the dummy shader! "
@@ -243,7 +244,15 @@ void r300_translate_vertex_shader(struct r300_context *r300,
     }
 
     /* Initialize numbers of constants for each type. */
-    vs->externals_count = ttr.immediate_offset;
+    vs->externals_count = 0;
+    for (i = 0;
+         i < vs->code.constants.Count &&
+         vs->code.constants.Constants[i].Type == RC_CONSTANT_EXTERNAL; i++) {
+        vs->externals_count = i+1;
+    }
+    for (; i < vs->code.constants.Count; i++) {
+        assert(vs->code.constants.Constants[i].Type == RC_CONSTANT_IMMEDIATE);
+    }
     vs->immediates_count = vs->code.constants.Count - vs->externals_count;
 
     /* And, finally... */
-- 
cgit v1.2.3


From 0a21938de92a1f1e74be7c4559b03179bd657fcd Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Tue, 24 Aug 2010 02:51:20 +0200
Subject: r300g: eliminate unused constants in FS

---
 src/gallium/drivers/r300/r300_emit.c  | 28 ++++++++++++++++++++++------
 src/gallium/drivers/r300/r300_fs.c    |  8 +++++++-
 src/gallium/drivers/r300/r300_state.c |  3 +++
 3 files changed, 32 insertions(+), 7 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index d3ca23211e..90bc9c56d3 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -180,9 +180,18 @@ void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *stat
 
     BEGIN_CS(size);
     OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
-    for (i = 0; i < count; i++)
-        for (j = 0; j < 4; j++)
-            OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
+    if (buf->remap_table){
+        for (i = 0; i < count; i++) {
+            uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
+            for (j = 0; j < 4; j++)
+                OUT_CS(pack_float24(data[j]));
+        }
+    } else {
+        for (i = 0; i < count; i++)
+            for (j = 0; j < 4; j++)
+                OUT_CS(pack_float24(*(float*)&buf->ptr[i*4+j]));
+    }
+
     END_CS;
 }
 
@@ -226,7 +235,7 @@ void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *stat
 {
     struct r300_fragment_shader *fs = r300_fs(r300);
     struct r300_constant_buffer *buf = (struct r300_constant_buffer*)state;
-    unsigned count = fs->shader->externals_count * 4;
+    unsigned count = fs->shader->externals_count;
     CS_LOCALS(r300);
 
     if (count == 0)
@@ -234,8 +243,15 @@ void r500_emit_fs_constants(struct r300_context* r300, unsigned size, void *stat
 
     BEGIN_CS(size);
     OUT_CS_REG(R500_GA_US_VECTOR_INDEX, R500_GA_US_VECTOR_INDEX_TYPE_CONST);
-    OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count);
-    OUT_CS_TABLE(buf->ptr, count);
+    OUT_CS_ONE_REG(R500_GA_US_VECTOR_DATA, count * 4);
+    if (buf->remap_table){
+        for (unsigned i = 0; i < count; i++) {
+            uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
+            OUT_CS_TABLE(data, 4);
+        }
+    } else {
+        OUT_CS_TABLE(buf->ptr, count * 4);
+    }
     END_CS;
 }
 
diff --git a/src/gallium/drivers/r300/r300_fs.c b/src/gallium/drivers/r300/r300_fs.c
index d95587b381..9845e54610 100644
--- a/src/gallium/drivers/r300/r300_fs.c
+++ b/src/gallium/drivers/r300/r300_fs.c
@@ -386,6 +386,7 @@ static void r300_translate_fragment_shader(
     compiler.state = shader->compare_state;
     compiler.Base.is_r500 = r300->screen->caps.is_r500;
     compiler.Base.max_temp_regs = compiler.Base.is_r500 ? 128 : 32;
+    compiler.Base.remove_unused_constants = TRUE;
     compiler.AllocateHwInputs = &allocate_hardware_inputs;
     compiler.UserData = &shader->inputs;
 
@@ -446,7 +447,12 @@ static void r300_translate_fragment_shader(
     }
 
     /* Initialize numbers of constants for each type. */
-    shader->externals_count = ttr.immediate_offset;
+    shader->externals_count = 0;
+    for (i = 0;
+         i < shader->code.constants.Count &&
+         shader->code.constants.Constants[i].Type == RC_CONSTANT_EXTERNAL; i++) {
+        shader->externals_count = i+1;
+    }
     shader->immediates_count = 0;
     shader->rc_state_count = 0;
 
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index ed39c575ce..3e35d7ab28 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -865,6 +865,9 @@ void r300_mark_fs_code_dirty(struct r300_context *r300)
         r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5;
         r300->fs_constants.size = fs->shader->externals_count * 4 + 1;
     }
+
+    ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table =
+            fs->shader->code.constants_remap_table;
 }
 
 /* Bind fragment shader state. */
-- 
cgit v1.2.3


From 879a73023189eed488db2840b829aa5c78e5ba3f Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Wed, 25 Aug 2010 04:55:01 +0200
Subject: r300g: fix gl_PointCoord

Is this hackish or is this the correct way to use point_quad_rasterization?
Copied from nvfx.
---
 src/gallium/drivers/r300/r300_state.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 3e35d7ab28..47e359cd5f 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -950,6 +950,11 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
     rs->rs = *state;
     rs->rs_draw = *state;
 
+    /* Generate point sprite texture coordinates in GENERIC0
+     * if point_quad_rasterization is TRUE. */
+    rs->rs.sprite_coord_enable = state->point_quad_rasterization *
+                                 (state->sprite_coord_enable | 1);
+
     /* Override some states for Draw. */
     rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */
 
@@ -1051,10 +1056,10 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
 
     /* Point sprites */
     stuffing_enable = 0;
-    if (state->sprite_coord_enable) {
+    if (rs->rs.sprite_coord_enable) {
         stuffing_enable = R300_GB_POINT_STUFF_ENABLE;
         for (i = 0; i < 8; i++) {
-            if (state->sprite_coord_enable & (1 << i))
+            if (rs->rs.sprite_coord_enable & (1 << i))
                 stuffing_enable |=
                     R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (i*2));
         }
-- 
cgit v1.2.3


From fbc3a911e1cbbc39da4c3b0e3dc9f1b964bf7fbc Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Wed, 25 Aug 2010 00:44:28 -0700
Subject: nvfx: Include missing headers in nvfx_shader.h.

Include stdint.h for uint8_t symbol.
Include p_compiler.h for INLINE symbol.
---
 src/gallium/drivers/nvfx/nvfx_shader.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_shader.h b/src/gallium/drivers/nvfx/nvfx_shader.h
index c711484ee2..35006eec3d 100644
--- a/src/gallium/drivers/nvfx/nvfx_shader.h
+++ b/src/gallium/drivers/nvfx/nvfx_shader.h
@@ -1,6 +1,10 @@
 #ifndef __NVFX_SHADER_H__
 #define __NVFX_SHADER_H__
 
+#include <stdint.h>
+
+#include "pipe/p_compiler.h"
+
 #define NVFX_SWZ_IDENTITY ((3 << 6) | (2 << 4) | (1 << 2) | (0 << 0))
 
 /* this will resolve to either the NV30 or the NV40 version
-- 
cgit v1.2.3


From 4e823197332604ca652ae6be21583725313f9f3d Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Wed, 25 Aug 2010 00:52:34 -0700
Subject: nvfx: Clean up header file inclusion in nvfx_screen.h.

Remove nvfx_context.h.
Include p_compiler.h for INLINE symbol.

Fixes nvfx_context.h -> nvfx_screen.h -> nvfx_context.h include recursion.
---
 src/gallium/drivers/nvfx/nvfx_screen.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_screen.h b/src/gallium/drivers/nvfx/nvfx_screen.h
index 473a112775..1b79235ae0 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.h
+++ b/src/gallium/drivers/nvfx/nvfx_screen.h
@@ -1,11 +1,11 @@
 #ifndef __NVFX_SCREEN_H__
 #define __NVFX_SCREEN_H__
 
+#include "pipe/p_compiler.h"
 #include "util/u_double_list.h"
 #include "nouveau/nouveau_screen.h"
-#include "nvfx_context.h"
 
-struct nv04_2d_context;
+struct pipe_screen;
 
 struct nvfx_screen {
 	struct nouveau_screen base;
-- 
cgit v1.2.3


From 94e8d4171d9647db84cd53334a2b14fab062640d Mon Sep 17 00:00:00 2001
From: Chia-I Wu <olv@lunarg.com>
Date: Sun, 1 Aug 2010 14:27:56 +0800
Subject: svga: Remove redundant svga_draw_range_elements.

That is, implement draw_vbo directly.  As a result,
svga_swtnl_draw_range_elements is also replaced by svga_swtnl_draw_vbo.

This commit should not have any functional change.
---
 src/gallium/drivers/svga/svga_pipe_draw.c  | 82 +++++++++---------------------
 src/gallium/drivers/svga/svga_swtnl.h      | 11 +---
 src/gallium/drivers/svga/svga_swtnl_draw.c | 39 +++++++-------
 3 files changed, 45 insertions(+), 87 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/svga/svga_pipe_draw.c b/src/gallium/drivers/svga/svga_pipe_draw.c
index de08bc5e56..001ec3616c 100644
--- a/src/gallium/drivers/svga/svga_pipe_draw.c
+++ b/src/gallium/drivers/svga/svga_pipe_draw.c
@@ -146,23 +146,15 @@ retry:
 }
 
 
-
-
-
 static void
-svga_draw_range_elements( struct pipe_context *pipe,
-                          struct pipe_resource *index_buffer,
-                          unsigned index_size,
-                          int index_bias,
-                          unsigned min_index,
-                          unsigned max_index,
-                          unsigned prim, unsigned start, unsigned count)
+svga_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
 {
    struct svga_context *svga = svga_context( pipe );
-   unsigned reduced_prim = u_reduced_prim(prim);
+   unsigned reduced_prim = u_reduced_prim( info->mode );
+   unsigned count = info->count;
    enum pipe_error ret = 0;
 
-   if (!u_trim_pipe_prim( prim, &count ))
+   if (!u_trim_pipe_prim( info->mode, &count ))
       return;
 
    /*
@@ -187,34 +179,32 @@ svga_draw_range_elements( struct pipe_context *pipe,
       return;
 #endif
 
-   if (svga->state.sw.need_swtnl)
-   {
-      ret = svga_swtnl_draw_range_elements( svga, 
-                                            index_buffer, 
-                                            index_size,
-                                            index_bias,
-                                            min_index, max_index,
-                                            prim,
-                                            start, count );
+   if (svga->state.sw.need_swtnl) {
+      ret = svga_swtnl_draw_vbo( svga, info );
    }
    else {
-      if (index_buffer) {
+      if (info->indexed && svga->curr.ib.buffer) {
+         unsigned offset;
+
+         assert(svga->curr.ib.offset % svga->curr.ib.index_size == 0);
+         offset = svga->curr.ib.offset / svga->curr.ib.index_size;
+
          ret = retry_draw_range_elements( svga,
-                                          index_buffer,
-                                          index_size,
-                                          index_bias,
-                                          min_index,
-                                          max_index,
-                                          prim,
-                                          start,
-                                          count,
+                                          svga->curr.ib.buffer,
+                                          svga->curr.ib.index_size,
+                                          info->index_bias,
+                                          info->min_index,
+                                          info->max_index,
+                                          info->mode,
+                                          info->start + offset,
+                                          info->count,
                                           TRUE );
       }
       else {
-         ret = retry_draw_arrays( svga, 
-                                  prim, 
-                                  start, 
-                                  count,
+         ret = retry_draw_arrays( svga,
+                                  info->mode,
+                                  info->start,
+                                  info->count,
                                   TRUE );
       }
    }
@@ -226,30 +216,6 @@ svga_draw_range_elements( struct pipe_context *pipe,
 }
 
 
-static void
-svga_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
-{
-   struct svga_context *svga = svga_context(pipe);
-
-   if (info->indexed && svga->curr.ib.buffer) {
-      unsigned offset;
-
-      assert(svga->curr.ib.offset % svga->curr.ib.index_size == 0);
-      offset = svga->curr.ib.offset / svga->curr.ib.index_size;
-
-      svga_draw_range_elements(pipe, svga->curr.ib.buffer,
-                               svga->curr.ib.index_size, info->index_bias,
-                               info->min_index, info->max_index,
-                               info->mode, info->start + offset, info->count);
-   }
-   else {
-      svga_draw_range_elements(pipe, NULL, 0, 0,
-                               info->min_index, info->max_index,
-                               info->mode, info->start, info->count);
-   }
-}
-
-
 void svga_init_draw_functions( struct svga_context *svga )
 {
    svga->pipe.draw_vbo = svga_draw_vbo;
diff --git a/src/gallium/drivers/svga/svga_swtnl.h b/src/gallium/drivers/svga/svga_swtnl.h
index 65c675f99c..fc094e5142 100644
--- a/src/gallium/drivers/svga/svga_swtnl.h
+++ b/src/gallium/drivers/svga/svga_swtnl.h
@@ -38,15 +38,8 @@ void svga_destroy_swtnl( struct svga_context *svga );
 
 
 enum pipe_error
-svga_swtnl_draw_range_elements(struct svga_context *svga,
-                               struct pipe_resource *indexBuffer,
-                               unsigned indexSize,
-                               int indexBias,
-                               unsigned min_index,
-                               unsigned max_index,
-                               unsigned prim, 
-                               unsigned start, 
-                               unsigned count);
+svga_swtnl_draw_vbo(struct svga_context *svga,
+                    const struct pipe_draw_info *info);
 
 
 #endif
diff --git a/src/gallium/drivers/svga/svga_swtnl_draw.c b/src/gallium/drivers/svga/svga_swtnl_draw.c
index eb71c23195..4f83822b5c 100644
--- a/src/gallium/drivers/svga/svga_swtnl_draw.c
+++ b/src/gallium/drivers/svga/svga_swtnl_draw.c
@@ -36,13 +36,8 @@
 
 
 enum pipe_error
-svga_swtnl_draw_range_elements(struct svga_context *svga,
-                               struct pipe_resource *indexBuffer,
-                               unsigned indexSize,
-                               int indexBias,
-                               unsigned min_index,
-                               unsigned max_index,
-                               unsigned prim, unsigned start, unsigned count)
+svga_swtnl_draw_vbo(struct svga_context *svga,
+                    const struct pipe_draw_info *info)
 {
    struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
    struct pipe_transfer *ib_transfer = NULL;
@@ -77,18 +72,22 @@ svga_swtnl_draw_range_elements(struct svga_context *svga,
    }
 
    /* Map index buffer, if present */
-   if (indexBuffer) {
-      map = pipe_buffer_map(&svga->pipe, indexBuffer,
+   map = NULL;
+   if (info->indexed && svga->curr.ib.buffer) {
+      map = pipe_buffer_map(&svga->pipe, svga->curr.ib.buffer,
                             PIPE_TRANSFER_READ,
-			    &ib_transfer);
-
-      draw_set_mapped_element_buffer_range(draw, 
-                                           indexSize, indexBias,
-                                           min_index,
-                                           max_index,
-                                           map);
+                            &ib_transfer);
+      if (map)
+         map = (const void *) ((const char *) map + svga->curr.ib.offset);
    }
-   
+
+   draw_set_mapped_element_buffer_range(draw, (map) ?
+                                        svga->curr.ib.index_size : 0,
+                                        info->index_bias,
+                                        info->min_index,
+                                        info->max_index,
+                                        map);
+
    if (svga->curr.cb[PIPE_SHADER_VERTEX]) {
       map = pipe_buffer_map(&svga->pipe,
                             svga->curr.cb[PIPE_SHADER_VERTEX],
@@ -101,7 +100,7 @@ svga_swtnl_draw_range_elements(struct svga_context *svga,
          svga->curr.cb[PIPE_SHADER_VERTEX]->width0);
    }
 
-   draw_arrays(svga->swtnl.draw, prim, start, count);
+   draw_arrays(draw, info->mode, info->start, info->count);
 
    draw_flush(svga->swtnl.draw);
 
@@ -117,8 +116,8 @@ svga_swtnl_draw_range_elements(struct svga_context *svga,
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
 
-   if (indexBuffer) {
-      pipe_buffer_unmap(&svga->pipe, indexBuffer, ib_transfer);
+   if (ib_transfer) {
+      pipe_buffer_unmap(&svga->pipe, svga->curr.ib.buffer, ib_transfer);
       draw_set_mapped_element_buffer(draw, 0, 0, NULL);
    }
 
-- 
cgit v1.2.3


From 22f6026324f63c142925244ff575fefc29a90389 Mon Sep 17 00:00:00 2001
From: Chia-I Wu <olv@lunarg.com>
Date: Wed, 25 Aug 2010 15:11:03 +0800
Subject: gallium: Use draw_set_index_buffer and others.

Update all drivers to use draw_set_index_buffer,
draw_set_mapped_index_buffer, and draw_vbo.  Remove
draw_set_mapped_element_buffer and draw_set_mapped_element_buffer_range.
---
 src/gallium/auxiliary/draw/draw_context.c        | 42 ----------------------
 src/gallium/auxiliary/draw/draw_context.h        | 13 -------
 src/gallium/auxiliary/draw/draw_pt.c             |  8 ++---
 src/gallium/drivers/cell/ppu/cell_draw_arrays.c  | 15 +++-----
 src/gallium/drivers/cell/ppu/cell_state_vertex.c |  2 +-
 src/gallium/drivers/i915/i915_context.c          | 22 ++++--------
 src/gallium/drivers/i915/i915_state.c            |  3 +-
 src/gallium/drivers/llvmpipe/lp_draw_arrays.c    | 18 +++-------
 src/gallium/drivers/llvmpipe/lp_state_vertex.c   |  2 +-
 src/gallium/drivers/nvfx/nvfx_draw.c             | 12 +++----
 src/gallium/drivers/nvfx/nvfx_state_emit.c       |  3 ++
 src/gallium/drivers/r300/r300_render.c           | 14 ++------
 src/gallium/drivers/r300/r300_state.c            |  7 +++-
 src/gallium/drivers/softpipe/sp_draw_arrays.c    | 26 ++++----------
 src/gallium/drivers/softpipe/sp_state_vertex.c   |  2 +-
 src/gallium/drivers/svga/svga_swtnl_draw.c       | 17 ++++-----
 src/mesa/state_tracker/st_draw_feedback.c        | 46 +++++++++++++-----------
 17 files changed, 80 insertions(+), 172 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/auxiliary/draw/draw_context.c b/src/gallium/auxiliary/draw/draw_context.c
index c2b7a441bd..b39b835f05 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -518,48 +518,6 @@ draw_set_mapped_index_buffer(struct draw_context *draw,
 }
 
 
-/**
- * Tell the drawing context about the index/element buffer to use
- * (ala glDrawElements)
- * If no element buffer is to be used (i.e. glDrawArrays) then this
- * should be called with eltSize=0 and elements=NULL.
- *
- * \param draw  the drawing context
- * \param eltSize  size of each element (1, 2 or 4 bytes)
- * \param elements  the element buffer ptr
- */
-void
-draw_set_mapped_element_buffer_range( struct draw_context *draw,
-                                      unsigned eltSize,
-                                      int eltBias,
-                                      unsigned min_index,
-                                      unsigned max_index,
-                                      const void *elements )
-{
-   struct pipe_index_buffer ib;
-
-   memset(&ib, 0, sizeof(ib));
-   ib.index_size = eltSize;
-   draw_set_index_buffer(draw, &ib);
-
-   draw->pt.user.elts = elements;
-   draw->pt.user.eltBias = eltBias;
-   draw->pt.user.min_index = min_index;
-   draw->pt.user.max_index = max_index;
-}
-
-
-void
-draw_set_mapped_element_buffer( struct draw_context *draw,
-                                unsigned eltSize,
-                                int eltBias,
-                                const void *elements )
-{
-   draw_set_mapped_element_buffer_range(draw,
-         eltSize, eltBias, 0, 0xffffffff, elements);
-}
-
- 
 /* Revamp me please:
  */
 void draw_do_flush( struct draw_context *draw, unsigned flags )
diff --git a/src/gallium/auxiliary/draw/draw_context.h b/src/gallium/auxiliary/draw/draw_context.h
index e9f3237dda..ea55320c42 100644
--- a/src/gallium/auxiliary/draw/draw_context.h
+++ b/src/gallium/auxiliary/draw/draw_context.h
@@ -166,19 +166,6 @@ void draw_set_index_buffer(struct draw_context *draw,
 void draw_set_mapped_index_buffer(struct draw_context *draw,
                                   const void *elements);
 
-void
-draw_set_mapped_element_buffer_range( struct draw_context *draw,
-                                      unsigned eltSize,
-                                      int eltBias,
-                                      unsigned min_index,
-                                      unsigned max_index,
-                                      const void *elements );
-
-void draw_set_mapped_element_buffer( struct draw_context *draw,
-                                     unsigned eltSize, 
-                                     int eltBias,
-                                     const void *elements );
-
 void draw_set_mapped_vertex_buffer(struct draw_context *draw,
                                    unsigned attr, const void *buffer);
 
diff --git a/src/gallium/auxiliary/draw/draw_pt.c b/src/gallium/auxiliary/draw/draw_pt.c
index 8db0d73662..f81714d6b4 100644
--- a/src/gallium/auxiliary/draw/draw_pt.c
+++ b/src/gallium/auxiliary/draw/draw_pt.c
@@ -299,7 +299,6 @@ draw_arrays(struct draw_context *draw, unsigned prim,
 
 /**
  * Instanced drawing.
- * draw_set_mapped_element_buffer must be called before calling this function.
  * \sa draw_vbo
  */
 void
@@ -321,9 +320,10 @@ draw_arrays_instanced(struct draw_context *draw,
    info.instance_count = instanceCount;
 
    info.indexed = (draw->pt.user.elts != NULL);
-   info.index_bias = draw->pt.user.eltBias;
-   info.min_index = draw->pt.user.min_index;
-   info.max_index = draw->pt.user.max_index;
+   if (!info.indexed) {
+      info.min_index = start;
+      info.max_index = start + count - 1;
+   }
 
    draw_vbo(draw, &info);
 }
diff --git a/src/gallium/drivers/cell/ppu/cell_draw_arrays.c b/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
index 4adef5b8c0..a367fa3fe1 100644
--- a/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
+++ b/src/gallium/drivers/cell/ppu/cell_draw_arrays.c
@@ -78,20 +78,13 @@ cell_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
       draw_set_mapped_vertex_buffer(draw, i, buf);
    }
    /* Map index buffer, if present */
-   if (info->indexed && cell->index_buffer.buffer) {
+   if (info->indexed && cell->index_buffer.buffer)
       mapped_indices = cell_resource(cell->index_buffer.buffer)->data;
-      mapped_indices += cell->index_buffer.offset;
-   }
 
-   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
-                                        lp->index_buffer.index_size : 0,
-                                        info->index_bias,
-                                        info->min_index,
-                                        info->max_index,
-                                        mapped_indices);
+   draw_set_mapped_index_buffer(draw, mapped_indices);
 
    /* draw! */
-   draw_arrays(draw, info->mode, info->start, info->count);
+   draw_vbo(draw, info);
 
    /*
     * unmap vertex/index buffers - will cause draw module to flush
@@ -100,7 +93,7 @@ cell_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
    if (mapped_indices) {
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
+      draw_set_mapped_index_buffer(draw, NULL);
    }
 
    /*
diff --git a/src/gallium/drivers/cell/ppu/cell_state_vertex.c b/src/gallium/drivers/cell/ppu/cell_state_vertex.c
index 4e3701cd0a..a065d68b5a 100644
--- a/src/gallium/drivers/cell/ppu/cell_state_vertex.c
+++ b/src/gallium/drivers/cell/ppu/cell_state_vertex.c
@@ -102,7 +102,7 @@ cell_set_index_buffer(struct pipe_context *pipe,
    else
       memset(&cell->index_buffer, 0, sizeof(cell->index_buffer));
 
-   /* TODO make this more like a state */
+   draw_set_index_buffer(cell->draw, ib);
 }
 
 
diff --git a/src/gallium/drivers/i915/i915_context.c b/src/gallium/drivers/i915/i915_context.c
index 2beb9e3091..847dd6dd47 100644
--- a/src/gallium/drivers/i915/i915_context.c
+++ b/src/gallium/drivers/i915/i915_context.c
@@ -66,18 +66,9 @@ i915_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
    /*
     * Map index buffer, if present
     */
-   if (info->indexed && i915->index_buffer.buffer) {
-      char *indices = (char *) i915_buffer(i915->index_buffer.buffer)->data;
-      mapped_indices = (void *) (indices + i915->index_buffer.offset);
-   }
-
-   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
-                                        i915->index_buffer.index_size : 0,
-                                        info->index_bias,
-                                        info->min_index,
-                                        info->max_index,
-                                        mapped_indices);
-
+   if (info->indexed && i915->index_buffer.buffer)
+      mapped_indices = i915_buffer(i915->index_buffer.buffer)->data;
+   draw_set_mapped_index_buffer(draw, mapped_indices);
 
    draw_set_mapped_constant_buffer(draw, PIPE_SHADER_VERTEX, 0,
                                    i915->current.constants[PIPE_SHADER_VERTEX],
@@ -87,7 +78,7 @@ i915_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
    /*
     * Do the drawing
     */
-   draw_arrays(i915->draw, info->mode, info->start, info->count);
+   draw_vbo(i915->draw, info);
 
    /*
     * unmap vertex/index buffers
@@ -96,9 +87,8 @@ i915_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
 
-   if (mapped_indices) {
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
-   }
+   if (mapped_indices)
+      draw_set_mapped_index_buffer(draw, NULL);
 }
 
 
diff --git a/src/gallium/drivers/i915/i915_state.c b/src/gallium/drivers/i915/i915_state.c
index 8c53b06931..bbfcff6bc4 100644
--- a/src/gallium/drivers/i915/i915_state.c
+++ b/src/gallium/drivers/i915/i915_state.c
@@ -817,7 +817,8 @@ static void i915_set_index_buffer(struct pipe_context *pipe,
    else
       memset(&i915->index_buffer, 0, sizeof(i915->index_buffer));
 
-   /* TODO make this more like a state */
+   /* pass-through to draw module */
+   draw_set_index_buffer(i915->draw, ib);
 }
 
 static void
diff --git a/src/gallium/drivers/llvmpipe/lp_draw_arrays.c b/src/gallium/drivers/llvmpipe/lp_draw_arrays.c
index e73b431cb4..3af5c8d5c5 100644
--- a/src/gallium/drivers/llvmpipe/lp_draw_arrays.c
+++ b/src/gallium/drivers/llvmpipe/lp_draw_arrays.c
@@ -68,25 +68,17 @@ llvmpipe_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
    }
 
    /* Map index buffer, if present */
-   if (info->indexed && lp->index_buffer.buffer) {
-      char *indices = (char *) llvmpipe_resource_data(lp->index_buffer.buffer);
-      mapped_indices = (void *) (indices + lp->index_buffer.offset);
-   }
+   if (info->indexed && lp->index_buffer.buffer)
+      mapped_indices = llvmpipe_resource_data(lp->index_buffer.buffer);
 
-   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
-                                        lp->index_buffer.index_size : 0,
-                                        info->index_bias,
-                                        info->min_index,
-                                        info->max_index,
-                                        mapped_indices);
+   draw_set_mapped_index_buffer(draw, mapped_indices);
 
    llvmpipe_prepare_vertex_sampling(lp,
                                     lp->num_vertex_sampler_views,
                                     lp->vertex_sampler_views);
 
    /* draw! */
-   draw_arrays_instanced(draw, info->mode, info->start, info->count,
-         info->start_instance, info->instance_count);
+   draw_vbo(draw, info);
 
    /*
     * unmap vertex/index buffers
@@ -95,7 +87,7 @@ llvmpipe_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
    if (mapped_indices) {
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
+      draw_set_mapped_index_buffer(draw, NULL);
    }
    llvmpipe_cleanup_vertex_sampling(lp);
 
diff --git a/src/gallium/drivers/llvmpipe/lp_state_vertex.c b/src/gallium/drivers/llvmpipe/lp_state_vertex.c
index d86e66b4fb..fb29423dd3 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_vertex.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_vertex.c
@@ -100,7 +100,7 @@ llvmpipe_set_index_buffer(struct pipe_context *pipe,
    else
       memset(&llvmpipe->index_buffer, 0, sizeof(llvmpipe->index_buffer));
 
-   /* TODO make this more like a state */
+   draw_set_index_buffer(llvmpipe->draw, ib);
 }
 
 void
diff --git a/src/gallium/drivers/nvfx/nvfx_draw.c b/src/gallium/drivers/nvfx/nvfx_draw.c
index 0b17921295..2601d5b8e2 100644
--- a/src/gallium/drivers/nvfx/nvfx_draw.c
+++ b/src/gallium/drivers/nvfx/nvfx_draw.c
@@ -239,12 +239,10 @@ nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info
 		draw_set_mapped_vertex_buffer(nvfx->draw, i, map);
 	}
 
-	if (info->indexed) {
-		map = nvfx_buffer(nvfx->idxbuf.buffer)->data + nvfx->idxbuf.offset;
-		draw_set_mapped_element_buffer_range(nvfx->draw, nvfx->idxbuf.index_size, info->index_bias, info->min_index, info->max_index, map);
-	} else {
-		draw_set_mapped_element_buffer(nvfx->draw, 0, 0, NULL);
-	}
+	map = NULL;
+	if (info->indexed && nvfx->idxbuf.buffer)
+		map = nvfx_buffer(nvfx->idxbuf.buffer)->data;
+	draw_set_mapped_index_buffer(nvfx->draw, map);
 
 	if (nvfx->constbuf[PIPE_SHADER_VERTEX]) {
 		const unsigned nr = nvfx->constbuf_nr[PIPE_SHADER_VERTEX];
@@ -254,7 +252,7 @@ nvfx_draw_vbo_swtnl(struct pipe_context *pipe, const struct pipe_draw_info* info
                                                 map, nr);
 	}
 
-	draw_arrays_instanced(nvfx->draw, info->mode, info->start, info->count, info->start_instance, info->instance_count);
+	draw_vbo(nvfx->draw, info);
 
 	draw_flush(nvfx->draw);
 }
diff --git a/src/gallium/drivers/nvfx/nvfx_state_emit.c b/src/gallium/drivers/nvfx/nvfx_state_emit.c
index cfcb0f7ef6..390bca8cdb 100644
--- a/src/gallium/drivers/nvfx/nvfx_state_emit.c
+++ b/src/gallium/drivers/nvfx/nvfx_state_emit.c
@@ -335,6 +335,9 @@ nvfx_state_validate_swtnl(struct nvfx_context *nvfx)
 		draw_set_vertex_elements(draw, nvfx->vtxelt->num_elements, nvfx->vtxelt->pipe);
 	}
 
+	if (nvfx->draw_dirty & NVFX_NEW_INDEX)
+		draw_set_index_buffer(draw, &nvfx->idxbuf);
+
 	nvfx_state_validate_common(nvfx);
 
 	nvfx->draw_dirty = 0;
diff --git a/src/gallium/drivers/r300/r300_render.c b/src/gallium/drivers/r300/r300_render.c
index e08335a105..20bad2c56f 100644
--- a/src/gallium/drivers/r300/r300_render.c
+++ b/src/gallium/drivers/r300/r300_render.c
@@ -680,18 +680,11 @@ static void r300_swtcl_draw_vbo(struct pipe_context* pipe,
     if (info->indexed && r300->index_buffer.buffer) {
         indices = pipe_buffer_map(pipe, r300->index_buffer.buffer,
                                   PIPE_TRANSFER_READ, &ib_transfer);
-        if (indices)
-            indices = (void *) ((char *) indices + r300->index_buffer.offset);
     }
 
-    draw_set_mapped_element_buffer_range(r300->draw, (indices) ?
-                                         r300->index_buffer.index_size : 0,
-                                         info->index_bias,
-                                         info->min_index,
-                                         info->max_index,
-                                         indices);
+    draw_set_mapped_index_buffer(r300->draw, indices);
 
-    draw_arrays(r300->draw, info->mode, info->start, count);
+    draw_vbo(r300->draw, info);
 
     /* XXX Not sure whether this is the best fix.
      * It prevents CS from being rejected and weird assertion failures. */
@@ -707,8 +700,7 @@ static void r300_swtcl_draw_vbo(struct pipe_context* pipe,
 
     if (ib_transfer) {
         pipe_buffer_unmap(pipe, r300->index_buffer.buffer, ib_transfer);
-        draw_set_mapped_element_buffer_range(r300->draw, 0, 0, info->start,
-                info->start + count - 1, NULL);
+        draw_set_mapped_index_buffer(r300->draw, NULL);
     }
 }
 
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 47e359cd5f..5c225e24f9 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -1556,7 +1556,12 @@ static void r300_set_index_buffer(struct pipe_context* pipe,
         memset(&r300->index_buffer, 0, sizeof(r300->index_buffer));
     }
 
-    /* TODO make this more like a state */
+    if (r300->screen->caps.has_tcl) {
+       /* TODO make this more like a state */
+    }
+    else {
+       draw_set_index_buffer(r300->draw, ib);
+    }
 }
 
 /* Initialize the PSC tables. */
diff --git a/src/gallium/drivers/softpipe/sp_draw_arrays.c b/src/gallium/drivers/softpipe/sp_draw_arrays.c
index 386c8acb8c..01b4ca985d 100644
--- a/src/gallium/drivers/softpipe/sp_draw_arrays.c
+++ b/src/gallium/drivers/softpipe/sp_draw_arrays.c
@@ -75,14 +75,10 @@ softpipe_draw_stream_output(struct pipe_context *pipe, unsigned mode)
    buf = (void*)((int32_t*)buf + offset);
    draw_set_mapped_vertex_buffer(draw, 0, buf);
 
-   draw_set_mapped_element_buffer_range(draw,
-                                        0, 0,
-                                        start,
-                                        start + count - 1,
-                                        NULL);
+   draw_set_mapped_index_buffer(draw, NULL);
 
    /* draw! */
-   draw_arrays_instanced(draw, mode, start, count, 0, 1);
+   draw_arrays(draw, mode, start, count);
 
    /* unmap vertex/index buffers - will cause draw module to flush */
    draw_set_mapped_vertex_buffer(draw, 0, NULL);
@@ -138,28 +134,20 @@ softpipe_draw_vbo(struct pipe_context *pipe,
    }
 
    /* Map index buffer, if present */
-   if (info->indexed && sp->index_buffer.buffer) {
-      char *indices = (char *) softpipe_resource(sp->index_buffer.buffer)->data;
-      mapped_indices = (void *) (indices + sp->index_buffer.offset);
-   }
+   if (info->indexed && sp->index_buffer.buffer)
+      mapped_indices = softpipe_resource(sp->index_buffer.buffer)->data;
 
-   draw_set_mapped_element_buffer_range(draw, (mapped_indices) ?
-                                        sp->index_buffer.index_size : 0,
-                                        info->index_bias,
-                                        info->min_index,
-                                        info->max_index,
-                                        mapped_indices);
+   draw_set_mapped_index_buffer(draw, mapped_indices);
 
    /* draw! */
-   draw_arrays_instanced(draw, info->mode, info->start, info->count,
-         info->start_instance, info->instance_count);
+   draw_vbo(draw, info);
 
    /* unmap vertex/index buffers - will cause draw module to flush */
    for (i = 0; i < sp->num_vertex_buffers; i++) {
       draw_set_mapped_vertex_buffer(draw, i, NULL);
    }
    if (mapped_indices) {
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
+      draw_set_mapped_index_buffer(draw, NULL);
    }
 
    /*
diff --git a/src/gallium/drivers/softpipe/sp_state_vertex.c b/src/gallium/drivers/softpipe/sp_state_vertex.c
index 880a7c7cd2..b650fcaea5 100644
--- a/src/gallium/drivers/softpipe/sp_state_vertex.c
+++ b/src/gallium/drivers/softpipe/sp_state_vertex.c
@@ -100,5 +100,5 @@ softpipe_set_index_buffer(struct pipe_context *pipe,
    else
       memset(&softpipe->index_buffer, 0, sizeof(softpipe->index_buffer));
 
-   /* TODO make this more like a state */
+   draw_set_index_buffer(softpipe->draw, ib);
 }
diff --git a/src/gallium/drivers/svga/svga_swtnl_draw.c b/src/gallium/drivers/svga/svga_swtnl_draw.c
index 4f83822b5c..e9eba3b422 100644
--- a/src/gallium/drivers/svga/svga_swtnl_draw.c
+++ b/src/gallium/drivers/svga/svga_swtnl_draw.c
@@ -71,22 +71,17 @@ svga_swtnl_draw_vbo(struct svga_context *svga,
       draw_set_mapped_vertex_buffer(draw, i, map);
    }
 
+   /* TODO move this to update_swtnl_draw */
+   draw_set_index_buffer(draw, &svga->curr.ib);
+
    /* Map index buffer, if present */
    map = NULL;
    if (info->indexed && svga->curr.ib.buffer) {
       map = pipe_buffer_map(&svga->pipe, svga->curr.ib.buffer,
                             PIPE_TRANSFER_READ,
                             &ib_transfer);
-      if (map)
-         map = (const void *) ((const char *) map + svga->curr.ib.offset);
    }
-
-   draw_set_mapped_element_buffer_range(draw, (map) ?
-                                        svga->curr.ib.index_size : 0,
-                                        info->index_bias,
-                                        info->min_index,
-                                        info->max_index,
-                                        map);
+   draw_set_mapped_index_buffer(draw, map);
 
    if (svga->curr.cb[PIPE_SHADER_VERTEX]) {
       map = pipe_buffer_map(&svga->pipe,
@@ -100,7 +95,7 @@ svga_swtnl_draw_vbo(struct svga_context *svga,
          svga->curr.cb[PIPE_SHADER_VERTEX]->width0);
    }
 
-   draw_arrays(draw, info->mode, info->start, info->count);
+   draw_vbo(draw, info);
 
    draw_flush(svga->swtnl.draw);
 
@@ -118,7 +113,7 @@ svga_swtnl_draw_vbo(struct svga_context *svga,
 
    if (ib_transfer) {
       pipe_buffer_unmap(&svga->pipe, svga->curr.ib.buffer, ib_transfer);
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
+      draw_set_mapped_index_buffer(draw, NULL);
    }
 
    if (svga->curr.cb[PIPE_SHADER_VERTEX]) {
diff --git a/src/mesa/state_tracker/st_draw_feedback.c b/src/mesa/state_tracker/st_draw_feedback.c
index 5cf2666334..e0995f8318 100644
--- a/src/mesa/state_tracker/st_draw_feedback.c
+++ b/src/mesa/state_tracker/st_draw_feedback.c
@@ -40,6 +40,7 @@
 #include "pipe/p_context.h"
 #include "pipe/p_defines.h"
 #include "util/u_inlines.h"
+#include "util/u_draw.h"
 
 #include "draw/draw_private.h"
 #include "draw/draw_context.h"
@@ -104,14 +105,15 @@ st_feedback_draw_vbo(GLcontext *ctx,
    struct draw_context *draw = st->draw;
    const struct st_vertex_program *vp;
    const struct pipe_shader_state *vs;
-   struct pipe_resource *index_buffer_handle = 0;
    struct pipe_vertex_buffer vbuffers[PIPE_MAX_SHADER_INPUTS];
    struct pipe_vertex_element velements[PIPE_MAX_ATTRIBS];
+   struct pipe_index_buffer ibuffer;
    struct pipe_transfer *vb_transfer[PIPE_MAX_ATTRIBS];
    struct pipe_transfer *ib_transfer = NULL;
    struct pipe_transfer *cb_transfer;
    GLuint attr, i;
    ubyte *mapped_constants;
+   const void *mapped_indices = NULL;
 
    assert(draw);
 
@@ -204,17 +206,19 @@ st_feedback_draw_vbo(GLcontext *ctx,
    draw_set_vertex_buffers(draw, vp->num_inputs, vbuffers);
    draw_set_vertex_elements(draw, vp->num_inputs, velements);
 
+   memset(&ibuffer, 0, sizeof(ibuffer));
    if (ib) {
       struct gl_buffer_object *bufobj = ib->obj;
-      unsigned indexSize;
-      void *map;
 
       switch (ib->type) {
       case GL_UNSIGNED_INT:
-         indexSize = 4;
+         ibuffer.index_size = 4;
          break;
       case GL_UNSIGNED_SHORT:
-         indexSize = 2;
+         ibuffer.index_size = 2;
+         break;
+      case GL_UNSIGNED_BYTE:
+         ibuffer.index_size = 1;
          break;
       default:
          assert(0);
@@ -224,23 +228,20 @@ st_feedback_draw_vbo(GLcontext *ctx,
       if (bufobj && bufobj->Name) {
          struct st_buffer_object *stobj = st_buffer_object(bufobj);
 
-         index_buffer_handle = stobj->buffer;
-
-         map = pipe_buffer_map(pipe, index_buffer_handle,
-                               PIPE_TRANSFER_READ, &ib_transfer);
+         pipe_resource_reference(&ibuffer.buffer, stobj->buffer);
+         ibuffer.offset = pointer_to_offset(ib->ptr);
 
-         draw_set_mapped_element_buffer(draw, indexSize, 0, map);
+         mapped_indices = pipe_buffer_map(pipe, stobj->buffer,
+                                          PIPE_TRANSFER_READ, &ib_transfer);
       }
       else {
-         draw_set_mapped_element_buffer(draw, indexSize, 0, (void *) ib->ptr);
-	 ib_transfer = NULL;
+         /* skip setting ibuffer.buffer as the draw module does not use it */
+         mapped_indices = ib->ptr;
       }
-   }
-   else {
-      /* no index/element buffer */
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
-   }
 
+      draw_set_index_buffer(draw, &ibuffer);
+      draw_set_mapped_index_buffer(draw, mapped_indices);
+   }
 
    /* map constant buffers */
    mapped_constants = pipe_buffer_map(pipe,
@@ -273,9 +274,14 @@ st_feedback_draw_vbo(GLcontext *ctx,
          draw_set_mapped_vertex_buffer(draw, i, NULL);
       }
    }
-   if (index_buffer_handle) {
-      pipe_buffer_unmap(pipe, index_buffer_handle, ib_transfer);
-      draw_set_mapped_element_buffer(draw, 0, 0, NULL);
+
+   if (ib) {
+      draw_set_mapped_index_buffer(draw, NULL);
+      draw_set_index_buffer(draw, NULL);
+
+      if (ib_transfer)
+         pipe_buffer_unmap(pipe, ibuffer.buffer, ib_transfer);
+      pipe_resource_reference(&ibuffer.buffer, NULL);
    }
 }
 
-- 
cgit v1.2.3


From f77daaa88290388ec817e1a4756405fddce1e696 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 20 Aug 2010 11:36:53 +0100
Subject: llvmpipe: remove dead code

---
 src/gallium/drivers/llvmpipe/lp_rast.c | 37 ----------------------------------
 1 file changed, 37 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_rast.c b/src/gallium/drivers/llvmpipe/lp_rast.c
index 3215d0f652..b1c306bbe9 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast.c
@@ -316,43 +316,6 @@ lp_rast_clear_zstencil(struct lp_rasterizer_task *task,
 }
 
 
-/**
- * Load tile color from the framebuffer surface.
- * This is a bin command called during bin processing.
- */
-#if 0
-void
-lp_rast_load_color(struct lp_rasterizer_task *task,
-                   const union lp_rast_cmd_arg arg)
-{
-   struct lp_rasterizer *rast = task->rast;
-   unsigned buf;
-   enum lp_texture_usage usage;
-
-   LP_DBG(DEBUG_RAST, "%s at %u, %u\n", __FUNCTION__, x, y);
-
-   if (scene->has_color_clear)
-      usage = LP_TEX_USAGE_WRITE_ALL;
-   else
-      usage = LP_TEX_USAGE_READ_WRITE;
-
-   /* Get pointers to color tile(s).
-    * This will convert linear data to tiled if needed.
-    */
-   for (buf = 0; buf < rast->state.nr_cbufs; buf++) {
-      struct pipe_surface *cbuf = rast->curr_scene->fb.cbufs[buf];
-      struct llvmpipe_texture *lpt;
-      assert(cbuf);
-      lpt = llvmpipe_texture(cbuf->texture);
-      task->color_tiles[buf] = llvmpipe_get_texture_tile(lpt,
-                                                         cbuf->face + cbuf->zslice,
-                                                         cbuf->level,
-                                                         usage,
-                                                         task->x, task->y);
-      assert(task->color_tiles[buf]);
-   }
-}
-#endif
 
 
 /**
-- 
cgit v1.2.3


From 6c0dc4bafbdbdc0cb4b6e5934fe064226dbd47ec Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 20 Aug 2010 15:52:58 +0100
Subject: draw: specialized cliptesting routines

---
 src/gallium/auxiliary/draw/draw_cliptest_tmp.h     | 114 ++++++++
 src/gallium/auxiliary/draw/draw_context.c          |  31 ++-
 src/gallium/auxiliary/draw/draw_context.h          |   3 +-
 src/gallium/auxiliary/draw/draw_pipe_validate.c    |   2 +-
 src/gallium/auxiliary/draw/draw_private.h          |  12 +-
 src/gallium/auxiliary/draw/draw_pt.c               |   4 +-
 src/gallium/auxiliary/draw/draw_pt.h               |   4 +-
 .../auxiliary/draw/draw_pt_fetch_shade_emit.c      |   2 +-
 .../auxiliary/draw/draw_pt_fetch_shade_pipeline.c  |   6 +-
 .../draw/draw_pt_fetch_shade_pipeline_llvm.c       |   6 +-
 src/gallium/auxiliary/draw/draw_pt_post_vs.c       | 288 ++++++++-------------
 src/gallium/drivers/r300/r300_context.c            |   2 -
 src/gallium/drivers/svga/svga_swtnl_draw.c         |   3 +-
 13 files changed, 269 insertions(+), 208 deletions(-)
 create mode 100644 src/gallium/auxiliary/draw/draw_cliptest_tmp.h

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/auxiliary/draw/draw_cliptest_tmp.h b/src/gallium/auxiliary/draw/draw_cliptest_tmp.h
new file mode 100644
index 0000000000..958ed20dc8
--- /dev/null
+++ b/src/gallium/auxiliary/draw/draw_cliptest_tmp.h
@@ -0,0 +1,114 @@
+/**************************************************************************
+ * 
+ * Copyright 2010, VMware, inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ * 
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * 
+ **************************************************************************/
+
+
+
+static boolean TAG(do_cliptest)( struct pt_post_vs *pvs,
+                                 struct draw_vertex_info *info )
+{
+   struct vertex_header *out = info->verts;
+   const float *scale = pvs->draw->viewport.scale;
+   const float *trans = pvs->draw->viewport.translate;
+   /* const */ float (*plane)[4] = pvs->draw->plane;
+   const unsigned pos = draw_current_shader_position_output(pvs->draw);
+   const unsigned ef = pvs->draw->vs.edgeflag_output;
+   const unsigned nr = pvs->draw->nr_planes;
+   const unsigned flags = (FLAGS);
+   unsigned need_pipeline = 0;
+   unsigned j;
+
+   for (j = 0; j < info->count; j++) {
+      float *position = out->data[pos];
+      unsigned mask = 0x0;
+  
+      initialize_vertex_header(out);
+
+      if (flags & (DO_CLIP_XY | DO_CLIP_FULL_Z | DO_CLIP_HALF_Z | DO_CLIP_USER)) {
+         out->clip[0] = position[0];
+         out->clip[1] = position[1];
+         out->clip[2] = position[2];
+         out->clip[3] = position[3];
+
+         /* Do the hardwired planes first:
+          */
+         if (flags & DO_CLIP_XY) {
+            if (-position[0] + position[3] < 0) mask |= (1<<0);
+            if ( position[0] + position[3] < 0) mask |= (1<<1);
+            if (-position[1] + position[3] < 0) mask |= (1<<2);
+            if ( position[1] + position[3] < 0) mask |= (1<<3);
+         }
+
+         /* Clip Z planes according to full cube, half cube or none.
+          */
+         if (flags & DO_CLIP_FULL_Z) {
+            if ( position[2] + position[3] < 0) mask |= (1<<4);
+            if (-position[2] + position[3] < 0) mask |= (1<<5);
+         }
+         else if (flags & DO_CLIP_HALF_Z) {
+            if ( position[2]               < 0) mask |= (1<<4);
+            if (-position[2] + position[3] < 0) mask |= (1<<5);
+         }
+
+         if (flags & DO_CLIP_USER) {
+            unsigned i;
+            for (i = 6; i < nr; i++) {
+               if (dot4(position, plane[i]) < 0) 
+                  mask |= (1<<i);
+            }
+         }
+
+         out->clipmask = mask;
+         need_pipeline |= out->clipmask;
+      }
+
+      if ((flags & DO_VIEWPORT) && mask == 0)
+      {
+	 /* divide by w */
+	 float w = 1.0f / position[3];
+
+	 /* Viewport mapping */
+	 position[0] = position[0] * w * scale[0] + trans[0];
+	 position[1] = position[1] * w * scale[1] + trans[1];
+	 position[2] = position[2] * w * scale[2] + trans[2];
+	 position[3] = w;
+      }
+
+      if ((flags & DO_EDGEFLAG) && ef) {
+         const float *edgeflag = out->data[ef];
+         out->edgeflag = !(edgeflag[0] != 1.0f);
+         need_pipeline |= !out->edgeflag;
+      }
+
+      out = (struct vertex_header *)( (char *)out + info->stride );
+   }
+
+   return need_pipeline != 0;
+}
+
+
+#undef FLAGS
+#undef TAG
diff --git a/src/gallium/auxiliary/draw/draw_context.c b/src/gallium/auxiliary/draw/draw_context.c
index b39b835f05..937b093479 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -106,6 +106,8 @@ boolean draw_init(struct draw_context *draw)
    ASSIGN_4V( draw->plane[4],  0,  0,  1, 1 ); /* yes these are correct */
    ASSIGN_4V( draw->plane[5],  0,  0, -1, 1 ); /* mesa's a bit wonky */
    draw->nr_planes = 6;
+   draw->clip_xy = 1;
+   draw->clip_z = 1;
 
 
    draw->reduced_prim = ~0; /* != any of PIPE_PRIM_x */
@@ -186,6 +188,14 @@ void draw_set_mrd(struct draw_context *draw, double mrd)
 }
 
 
+static void update_clip_flags( struct draw_context *draw )
+{
+   draw->clip_xy = !draw->driver.bypass_clip_xy;
+   draw->clip_z = (!draw->driver.bypass_clip_z &&
+                   !draw->depth_clamp);
+   draw->clip_user = (draw->nr_planes > 6);
+}
+
 /**
  * Register new primitive rasterization/rendering state.
  * This causes the drawing pipeline to be rebuilt.
@@ -200,18 +210,25 @@ void draw_set_rasterizer_state( struct draw_context *draw,
       draw->rasterizer = raster;
       draw->rast_handle = rast_handle;
 
-      draw->bypass_clipping = draw->driver.bypass_clipping;
-   }
+  }
 }
 
-
+/* With a little more work, llvmpipe will be able to turn this off and
+ * do its own x/y clipping.  
+ *
+ * Some hardware can turn off clipping altogether - in particular any
+ * hardware with a TNL unit can do its own clipping, even if it is
+ * relying on the draw module for some other reason.
+ */
 void draw_set_driver_clipping( struct draw_context *draw,
-                               boolean bypass_clipping )
+                               boolean bypass_clip_xy,
+                               boolean bypass_clip_z )
 {
    draw_do_flush( draw, DRAW_FLUSH_STATE_CHANGE );
 
-   draw->driver.bypass_clipping = bypass_clipping;
-   draw->bypass_clipping = draw->driver.bypass_clipping;
+   draw->driver.bypass_clip_xy = bypass_clip_xy;
+   draw->driver.bypass_clip_z = bypass_clip_z;
+   update_clip_flags(draw);
 }
 
 
@@ -241,6 +258,8 @@ void draw_set_clip_state( struct draw_context *draw,
    memcpy(&draw->plane[6], clip->ucp, clip->nr * sizeof(clip->ucp[0]));
    draw->nr_planes = 6 + clip->nr;
    draw->depth_clamp = clip->depth_clamp;
+
+   update_clip_flags(draw);
 }
 
 
diff --git a/src/gallium/auxiliary/draw/draw_context.h b/src/gallium/auxiliary/draw/draw_context.h
index ea55320c42..4c780e4dcb 100644
--- a/src/gallium/auxiliary/draw/draw_context.h
+++ b/src/gallium/auxiliary/draw/draw_context.h
@@ -212,7 +212,8 @@ void draw_set_render( struct draw_context *draw,
 		      struct vbuf_render *render );
 
 void draw_set_driver_clipping( struct draw_context *draw,
-                               boolean bypass_clipping );
+                               boolean bypass_clip_xy,
+                               boolean bypass_clip_z );
 
 void draw_set_force_passthrough( struct draw_context *draw, 
                                  boolean enable );
diff --git a/src/gallium/auxiliary/draw/draw_pipe_validate.c b/src/gallium/auxiliary/draw/draw_pipe_validate.c
index eafa29276f..8b92543987 100644
--- a/src/gallium/auxiliary/draw/draw_pipe_validate.c
+++ b/src/gallium/auxiliary/draw/draw_pipe_validate.c
@@ -265,7 +265,7 @@ static struct draw_stage *validate_pipeline( struct draw_stage *stage )
 
    /* Clip stage
     */
-   if (!draw->bypass_clipping)
+   if (draw->clip_xy || draw->clip_z || draw->clip_user)
    {
       draw->pipeline.clip->next = next;
       next = draw->pipeline.clip;
diff --git a/src/gallium/auxiliary/draw/draw_private.h b/src/gallium/auxiliary/draw/draw_private.h
index 7bc3923692..362f563ba6 100644
--- a/src/gallium/auxiliary/draw/draw_private.h
+++ b/src/gallium/auxiliary/draw/draw_private.h
@@ -176,13 +176,19 @@ struct draw_context
    } pt;
 
    struct {
-      boolean bypass_clipping;
-      boolean bypass_vs;
+      boolean bypass_clip_xy;
+      boolean bypass_clip_z;
    } driver;
 
    boolean flushing;         /**< debugging/sanity */
    boolean suspend_flushing; /**< internally set */
-   boolean bypass_clipping;  /**< set if either api or driver bypass_clipping true */
+
+   /* Flags set if API requires clipping in these planes and the
+    * driver doesn't indicate that it can do it for us.
+    */
+   boolean clip_xy;
+   boolean clip_z;
+   boolean clip_user;
 
    boolean force_passthrough; /**< never clip or shade */
 
diff --git a/src/gallium/auxiliary/draw/draw_pt.c b/src/gallium/auxiliary/draw/draw_pt.c
index f81714d6b4..f44bf2507c 100644
--- a/src/gallium/auxiliary/draw/draw_pt.c
+++ b/src/gallium/auxiliary/draw/draw_pt.c
@@ -86,7 +86,9 @@ draw_pt_arrays(struct draw_context *draw,
          opt |= PT_PIPELINE;
       }
 
-      if (!draw->bypass_clipping && !draw->pt.test_fse) {
+      if ((draw->clip_xy ||
+           draw->clip_z ||
+           draw->clip_user) && !draw->pt.test_fse) {
          opt |= PT_CLIPTEST;
       }
 
diff --git a/src/gallium/auxiliary/draw/draw_pt.h b/src/gallium/auxiliary/draw/draw_pt.h
index 0db5666529..5fbb424291 100644
--- a/src/gallium/auxiliary/draw/draw_pt.h
+++ b/src/gallium/auxiliary/draw/draw_pt.h
@@ -221,7 +221,9 @@ boolean draw_pt_post_vs_run( struct pt_post_vs *pvs,
 			     struct draw_vertex_info *info );
 
 void draw_pt_post_vs_prepare( struct pt_post_vs *pvs,
-			      boolean bypass_clipping,
+			      boolean clip_xy,
+			      boolean clip_z,
+			      boolean clip_user,
 			      boolean bypass_viewport,
 			      boolean opengl,
 			      boolean need_edgeflags );
diff --git a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_emit.c b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_emit.c
index 4fbf88844a..7c198c6026 100644
--- a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_emit.c
+++ b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_emit.c
@@ -102,7 +102,7 @@ static void fse_prepare( struct draw_pt_middle_end *middle,
                                fse->key.nr_inputs);     /* inputs - fetch from api format */
 
    fse->key.viewport = !draw->identity_viewport;
-   fse->key.clip = !draw->bypass_clipping;
+   fse->key.clip = draw->clip_xy || draw->clip_z || draw->clip_user;
    fse->key.const_vbuffers = 0;
 
    memset(fse->key.element, 0, 
diff --git a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c
index 96b40fb363..b72fd61245 100644
--- a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c
+++ b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline.c
@@ -100,8 +100,10 @@ static void fetch_pipeline_prepare( struct draw_pt_middle_end *middle,
     * but gl vs dx9 clip spaces.
     */
    draw_pt_post_vs_prepare( fpme->post_vs,
-			    (boolean)draw->bypass_clipping,
-			    (boolean)draw->identity_viewport,
+			    draw->clip_xy,
+			    draw->clip_z,
+			    draw->clip_user,
+			    draw->identity_viewport,
 			    (boolean)draw->rasterizer->gl_rasterization_rules,
 			    (draw->vs.edgeflag_output ? TRUE : FALSE) );
 
diff --git a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
index cc0b4e5232..77291e304e 100644
--- a/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
+++ b/src/gallium/auxiliary/draw/draw_pt_fetch_shade_pipeline_llvm.c
@@ -107,8 +107,10 @@ llvm_middle_end_prepare( struct draw_pt_middle_end *middle,
     * but gl vs dx9 clip spaces.
     */
    draw_pt_post_vs_prepare( fpme->post_vs,
-			    (boolean)draw->bypass_clipping,
-			    (boolean)(draw->identity_viewport),
+			    draw->clip_xy,
+			    draw->clip_z,
+			    draw->clip_user,
+			    draw->identity_viewport,
 			    (boolean)draw->rasterizer->gl_rasterization_rules,
 			    (draw->vs.edgeflag_output ? TRUE : FALSE) );
 
diff --git a/src/gallium/auxiliary/draw/draw_pt_post_vs.c b/src/gallium/auxiliary/draw/draw_pt_post_vs.c
index 308f927b77..769409cfd6 100644
--- a/src/gallium/auxiliary/draw/draw_pt_post_vs.c
+++ b/src/gallium/auxiliary/draw/draw_pt_post_vs.c
@@ -26,14 +26,26 @@
  **************************************************************************/
 
 #include "util/u_memory.h"
+#include "util/u_math.h"
 #include "pipe/p_context.h"
 #include "draw/draw_context.h"
 #include "draw/draw_private.h"
 #include "draw/draw_pt.h"
 
+
+#define DO_CLIP_XY           0x1
+#define DO_CLIP_FULL_Z       0x2
+#define DO_CLIP_HALF_Z       0x4
+#define DO_CLIP_USER         0x8
+#define DO_VIEWPORT          0x10
+#define DO_EDGEFLAG          0x20
+
+
 struct pt_post_vs {
    struct draw_context *draw;
 
+   unsigned flags;
+
    boolean (*run)( struct pt_post_vs *pvs,
                    struct draw_vertex_info *info );
 };
@@ -56,186 +68,47 @@ dot4(const float *a, const float *b)
            a[3]*b[3]);
 }
 
-static INLINE unsigned
-compute_clipmask_gl(const float *clip, /*const*/ float plane[][4], unsigned nr,
-                    boolean clip_depth)
-{
-   unsigned mask = 0x0;
-   unsigned i;
+#define FLAGS (0)
+#define TAG(x) x##_none
+#include "draw_cliptest_tmp.h"
 
-#if 0
-   debug_printf("compute clipmask %f %f %f %f\n",
-                clip[0], clip[1], clip[2], clip[3]);
-   assert(clip[3] != 0.0);
-#endif
+#define FLAGS (DO_CLIP_XY | DO_CLIP_FULL_Z | DO_VIEWPORT)
+#define TAG(x) x##_xy_fullz_viewport
+#include "draw_cliptest_tmp.h"
 
-   /* Do the hardwired planes first:
-    */
-   if (-clip[0] + clip[3] < 0) mask |= (1<<0);
-   if ( clip[0] + clip[3] < 0) mask |= (1<<1);
-   if (-clip[1] + clip[3] < 0) mask |= (1<<2);
-   if ( clip[1] + clip[3] < 0) mask |= (1<<3);
-   if (clip_depth) {
-      if ( clip[2] + clip[3] < 0) mask |= (1<<4); /* match mesa clipplane numbering - for now */
-      if (-clip[2] + clip[3] < 0) mask |= (1<<5); /* match mesa clipplane numbering - for now */
-   }
+#define FLAGS (DO_CLIP_XY | DO_CLIP_HALF_Z | DO_VIEWPORT)
+#define TAG(x) x##_xy_halfz_viewport
+#include "draw_cliptest_tmp.h"
 
-   /* Followed by any remaining ones:
-    */
-   for (i = 6; i < nr; i++) {
-      if (dot4(clip, plane[i]) < 0) 
-         mask |= (1<<i);
-   }
+#define FLAGS (DO_CLIP_FULL_Z | DO_VIEWPORT)
+#define TAG(x) x##_fullz_viewport
+#include "draw_cliptest_tmp.h"
 
-   return mask;
-}
+#define FLAGS (DO_CLIP_HALF_Z | DO_VIEWPORT)
+#define TAG(x) x##_halfz_viewport
+#include "draw_cliptest_tmp.h"
 
+#define FLAGS (DO_CLIP_XY | DO_CLIP_FULL_Z | DO_CLIP_USER | DO_VIEWPORT)
+#define TAG(x) x##_xy_fullz_user_viewport
+#include "draw_cliptest_tmp.h"
 
-/* The normal case - cliptest, rhw divide, viewport transform.
- *
- * Also handle identity viewport here at the expense of a few wasted
- * instructions
- */
-static boolean post_vs_cliptest_viewport_gl( struct pt_post_vs *pvs,
-                                             struct draw_vertex_info *info )
-{
-   struct vertex_header *out = info->verts;
-   const float *scale = pvs->draw->viewport.scale;
-   const float *trans = pvs->draw->viewport.translate;
-   const unsigned pos = draw_current_shader_position_output(pvs->draw);
-   unsigned clipped = 0;
-   unsigned j;
-
-   if (0) debug_printf("%s count, %d\n", __FUNCTION__, info->count);
-
-   for (j = 0; j < info->count; j++) {
-      float *position = out->data[pos];
-
-      initialize_vertex_header(out);
-#if 0
-      debug_printf("%d) io = %p, data = %p = [%f, %f, %f, %f]\n",
-                   j, out, position, position[0], position[1], position[2], position[3]);
-#endif
-
-      out->clip[0] = position[0];
-      out->clip[1] = position[1];
-      out->clip[2] = position[2];
-      out->clip[3] = position[3];
-
-      out->vertex_id = 0xffff;
-      /* Disable depth clipping if depth clamping is enabled. */
-      out->clipmask = compute_clipmask_gl(out->clip, 
-					  pvs->draw->plane,
-                                          pvs->draw->nr_planes,
-                                          !pvs->draw->depth_clamp);
-      clipped += out->clipmask;
-
-      if (out->clipmask == 0)
-      {
-	 /* divide by w */
-	 float w = 1.0f / position[3];
-
-	 /* Viewport mapping */
-	 position[0] = position[0] * w * scale[0] + trans[0];
-	 position[1] = position[1] * w * scale[1] + trans[1];
-	 position[2] = position[2] * w * scale[2] + trans[2];
-	 position[3] = w;
-#if 0
-         debug_printf("post viewport: %f %f %f %f\n",
-                      position[0],
-                      position[1],
-                      position[2],
-                      position[3]);
-#endif
-      }
-
-      out = (struct vertex_header *)( (char *)out + info->stride );
-   }
-
-   return clipped != 0;
-}
+#define FLAGS (DO_CLIP_XY | DO_CLIP_FULL_Z | DO_CLIP_USER | DO_VIEWPORT | DO_EDGEFLAG)
+#define TAG(x) x##_xy_fullz_user_viewport_edgeflag
+#include "draw_cliptest_tmp.h"
 
 
 
-/* As above plus edgeflags
+/* Don't want to create 64 versions of this function, so catch the
+ * less common ones here.  This is looking like something which should
+ * be code-generated, perhaps appended to the end of the vertex
+ * shader.
  */
-static boolean
-post_vs_cliptest_viewport_gl_edgeflag(struct pt_post_vs *pvs,
-                                      struct draw_vertex_info *info)
-{
-   unsigned j;
-   boolean needpipe;
-
-   needpipe = post_vs_cliptest_viewport_gl(pvs, info);
-
-   /* If present, copy edgeflag VS output into vertex header.
-    * Otherwise, leave header as is.
-    */
-   if (pvs->draw->vs.edgeflag_output) {
-      struct vertex_header *out = info->verts;
-      int ef = pvs->draw->vs.edgeflag_output;
-
-      for (j = 0; j < info->count; j++) {
-         const float *edgeflag = out->data[ef];
-         out->edgeflag = !(edgeflag[0] != 1.0f);
-         needpipe |= !out->edgeflag;
-         out = (struct vertex_header *)( (char *)out + info->stride );
-      }
-   }
-   return needpipe;
-}
-
+#define FLAGS (pvs->flags)
+#define TAG(x) x##_generic
+#include "draw_cliptest_tmp.h"
 
 
 
-/* If bypass_clipping is set, skip cliptest and rhw divide.
- */
-static boolean post_vs_viewport( struct pt_post_vs *pvs,
-                                 struct draw_vertex_info *info )
-{
-   struct vertex_header *out = info->verts;
-   const float *scale = pvs->draw->viewport.scale;
-   const float *trans = pvs->draw->viewport.translate;
-   const unsigned pos = draw_current_shader_position_output(pvs->draw);
-   unsigned j;
-
-   if (0) debug_printf("%s\n", __FUNCTION__);
-   for (j = 0; j < info->count; j++) {
-      float *position = out->data[pos];
-
-      initialize_vertex_header(out);
-      /* Viewport mapping only, no cliptest/rhw divide
-       */
-      position[0] = position[0] * scale[0] + trans[0];
-      position[1] = position[1] * scale[1] + trans[1];
-      position[2] = position[2] * scale[2] + trans[2];
-
-      out = (struct vertex_header *)((char *)out + info->stride);
-   }
-
-   return FALSE;
-}
-
-
-/* If bypass_clipping is set and we have an identity viewport, nothing
- * to do.
- */
-static boolean post_vs_none( struct pt_post_vs *pvs,
-			     struct draw_vertex_info *info )
-{
-   struct vertex_header *out = info->verts;
-   unsigned j;
-
-   if (0) debug_printf("%s\n", __FUNCTION__);
-   /* just initialize the vertex_id in all headers */
-   for (j = 0; j < info->count; j++) {
-      initialize_vertex_header(out);
-
-      out = (struct vertex_header *)((char *)out + info->stride);
-   }
-   return FALSE;
-}
-
 boolean draw_pt_post_vs_run( struct pt_post_vs *pvs,
 			     struct draw_vertex_info *info )
 {
@@ -244,31 +117,72 @@ boolean draw_pt_post_vs_run( struct pt_post_vs *pvs,
 
 
 void draw_pt_post_vs_prepare( struct pt_post_vs *pvs,
-			      boolean bypass_clipping,
+			      boolean clip_xy,
+			      boolean clip_z,
+                              boolean clip_user,
 			      boolean bypass_viewport,
 			      boolean opengl,
 			      boolean need_edgeflags )
 {
-   if (!need_edgeflags) {
-      if (bypass_clipping) {
-         if (bypass_viewport)
-            pvs->run = post_vs_none;
-         else
-            pvs->run = post_vs_viewport;
-      }
-      else {
-         /* if (opengl) */
-         pvs->run = post_vs_cliptest_viewport_gl;
-      }
+   pvs->flags = 0;
+
+   if (clip_xy)
+      pvs->flags |= DO_CLIP_XY;
+   
+   if (clip_z && opengl) {
+      pvs->flags |= DO_CLIP_FULL_Z;
+      ASSIGN_4V( pvs->draw->plane[4],  0,  0,  1, 1 );
+   }
+
+   if (clip_z && !opengl) {
+      pvs->flags |= DO_CLIP_HALF_Z;
+      ASSIGN_4V( pvs->draw->plane[4],  0,  0,  1, 0 );
    }
-   else {
-      /* If we need to copy edgeflags to the vertex header, it should
-       * mean we're running the primitive pipeline.  Hence the bypass
-       * flags should be false.
-       */
-      assert(!bypass_clipping);
-      assert(!bypass_viewport);
-      pvs->run = post_vs_cliptest_viewport_gl_edgeflag;
+
+   if (clip_user)
+      pvs->flags |= DO_CLIP_USER;
+
+   if (!bypass_viewport)
+      pvs->flags |= DO_VIEWPORT;
+
+   if (need_edgeflags)
+      pvs->flags |= DO_EDGEFLAG;
+
+   /* Now select the relevant function:
+    */
+   switch (pvs->flags) {
+   case 0:
+      pvs->run = do_cliptest_none;
+      break;
+
+   case DO_CLIP_XY | DO_CLIP_FULL_Z | DO_VIEWPORT:
+      pvs->run = do_cliptest_xy_fullz_viewport;
+      break;
+
+   case DO_CLIP_XY | DO_CLIP_HALF_Z | DO_VIEWPORT:
+      pvs->run = do_cliptest_xy_halfz_viewport;
+      break;
+
+   case DO_CLIP_FULL_Z | DO_VIEWPORT:
+      pvs->run = do_cliptest_fullz_viewport;
+      break;
+
+   case DO_CLIP_HALF_Z | DO_VIEWPORT:
+      pvs->run = do_cliptest_halfz_viewport;
+      break;
+
+   case DO_CLIP_XY | DO_CLIP_FULL_Z | DO_CLIP_USER | DO_VIEWPORT:
+      pvs->run = do_cliptest_xy_fullz_user_viewport;
+      break;
+
+   case (DO_CLIP_XY | DO_CLIP_FULL_Z | DO_CLIP_USER |
+         DO_VIEWPORT | DO_EDGEFLAG):
+      pvs->run = do_cliptest_xy_fullz_user_viewport_edgeflag;
+      break;
+      
+   default:
+      pvs->run = do_cliptest_generic;
+      break;
    }
 }
 
diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index 852d88af54..05f7d09316 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -431,8 +431,6 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
         r300->draw = draw_create(&r300->context);
         /* Enable our renderer. */
         draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
-        /* Enable Draw's clipping. */
-        draw_set_driver_clipping(r300->draw, FALSE);
         /* Disable converting points/lines to triangles. */
         draw_wide_line_threshold(r300->draw, 10000000.f);
         draw_wide_point_threshold(r300->draw, 10000000.f);
diff --git a/src/gallium/drivers/svga/svga_swtnl_draw.c b/src/gallium/drivers/svga/svga_swtnl_draw.c
index e9eba3b422..814e8edd70 100644
--- a/src/gallium/drivers/svga/svga_swtnl_draw.c
+++ b/src/gallium/drivers/svga/svga_swtnl_draw.c
@@ -151,7 +151,8 @@ boolean svga_init_swtnl( struct svga_context *svga )
    draw_install_aapoint_stage(svga->swtnl.draw, &svga->pipe);
    draw_install_pstipple_stage(svga->swtnl.draw, &svga->pipe);
 
-   draw_set_driver_clipping(svga->swtnl.draw, debug_get_bool_option("SVGA_SWTNL_FSE", FALSE));
+   if (debug_get_bool_option("SVGA_SWTNL_FSE", FALSE))
+      draw_set_driver_clipping(svga->swtnl.draw, TRUE, TRUE);
 
    return TRUE;
 
-- 
cgit v1.2.3


From b6e03eafe3311142445ca42c1574d3f6998eecc3 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 20 Aug 2010 15:14:19 +0100
Subject: llvmpipe: fence debugging, add llvmpipe_finish

---
 src/gallium/drivers/llvmpipe/lp_context.c  | 10 +++++++-
 src/gallium/drivers/llvmpipe/lp_debug.h    |  2 ++
 src/gallium/drivers/llvmpipe/lp_fence.c    | 16 +++++++++++--
 src/gallium/drivers/llvmpipe/lp_fence.h    |  1 +
 src/gallium/drivers/llvmpipe/lp_flush.c    | 38 ++++++++++++++----------------
 src/gallium/drivers/llvmpipe/lp_flush.h    | 13 +++++++---
 src/gallium/drivers/llvmpipe/lp_query.c    | 25 ++++----------------
 src/gallium/drivers/llvmpipe/lp_screen.c   |  2 ++
 src/gallium/drivers/llvmpipe/lp_setup.c    |  5 ++--
 src/gallium/drivers/llvmpipe/lp_setup.h    |  3 ++-
 src/gallium/drivers/llvmpipe/lp_state_fs.c | 15 ++----------
 src/gallium/drivers/llvmpipe/lp_surface.c  |  6 +++--
 src/gallium/drivers/llvmpipe/lp_texture.c  |  3 ++-
 13 files changed, 74 insertions(+), 65 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_context.c b/src/gallium/drivers/llvmpipe/lp_context.c
index 7543bd7b2b..086a2d5898 100644
--- a/src/gallium/drivers/llvmpipe/lp_context.c
+++ b/src/gallium/drivers/llvmpipe/lp_context.c
@@ -85,6 +85,14 @@ static void llvmpipe_destroy( struct pipe_context *pipe )
    align_free( llvmpipe );
 }
 
+static void
+do_flush( struct pipe_context *pipe,
+          unsigned flags,
+          struct pipe_fence_handle **fence)
+{
+   llvmpipe_flush(pipe, flags, fence, __FUNCTION__);
+}
+
 
 struct pipe_context *
 llvmpipe_create_context( struct pipe_screen *screen, void *priv )
@@ -109,7 +117,7 @@ llvmpipe_create_context( struct pipe_screen *screen, void *priv )
    llvmpipe->pipe.destroy = llvmpipe_destroy;
    llvmpipe->pipe.set_framebuffer_state = llvmpipe_set_framebuffer_state;
    llvmpipe->pipe.clear = llvmpipe_clear;
-   llvmpipe->pipe.flush = llvmpipe_flush;
+   llvmpipe->pipe.flush = do_flush;
 
    llvmpipe_init_blend_funcs(llvmpipe);
    llvmpipe_init_clip_funcs(llvmpipe);
diff --git a/src/gallium/drivers/llvmpipe/lp_debug.h b/src/gallium/drivers/llvmpipe/lp_debug.h
index 92fb2b3ee5..a928ee38be 100644
--- a/src/gallium/drivers/llvmpipe/lp_debug.h
+++ b/src/gallium/drivers/llvmpipe/lp_debug.h
@@ -46,6 +46,8 @@ st_print_current(void);
 #define DEBUG_SHOW_TILES    0x200
 #define DEBUG_SHOW_SUBTILES 0x400
 #define DEBUG_COUNTERS      0x800
+#define DEBUG_SCENE         0x1000
+#define DEBUG_FENCE         0x2000
 
 
 #ifdef DEBUG
diff --git a/src/gallium/drivers/llvmpipe/lp_fence.c b/src/gallium/drivers/llvmpipe/lp_fence.c
index f9805e5d68..4d549b0750 100644
--- a/src/gallium/drivers/llvmpipe/lp_fence.c
+++ b/src/gallium/drivers/llvmpipe/lp_fence.c
@@ -44,6 +44,7 @@
 struct lp_fence *
 lp_fence_create(unsigned rank)
 {
+   static int fence_id;
    struct lp_fence *fence = CALLOC_STRUCT(lp_fence);
 
    pipe_reference_init(&fence->reference, 1);
@@ -51,8 +52,12 @@ lp_fence_create(unsigned rank)
    pipe_mutex_init(fence->mutex);
    pipe_condvar_init(fence->signalled);
 
+   fence->id = fence_id++;
    fence->rank = rank;
 
+   if (LP_DEBUG & DEBUG_FENCE)
+      debug_printf("%s %d\n", __FUNCTION__, fence->id);
+
    return fence;
 }
 
@@ -61,6 +66,9 @@ lp_fence_create(unsigned rank)
 void
 lp_fence_destroy(struct lp_fence *fence)
 {
+   if (LP_DEBUG & DEBUG_FENCE)
+      debug_printf("%s %d\n", __FUNCTION__, fence->id);
+
    pipe_mutex_destroy(fence->mutex);
    pipe_condvar_destroy(fence->signalled);
    FREE(fence);
@@ -126,13 +134,17 @@ llvmpipe_fence_finish(struct pipe_screen *screen,
 void
 lp_fence_signal(struct lp_fence *fence)
 {
+   if (LP_DEBUG & DEBUG_FENCE)
+      debug_printf("%s %d\n", __FUNCTION__, fence->id);
+
    pipe_mutex_lock(fence->mutex);
 
    fence->count++;
    assert(fence->count <= fence->rank);
 
-   LP_DBG(DEBUG_RAST, "%s count=%u rank=%u\n", __FUNCTION__,
-          fence->count, fence->rank);
+   if (LP_DEBUG & DEBUG_FENCE)
+      debug_printf("%s count=%u rank=%u\n", __FUNCTION__,
+                   fence->count, fence->rank);
 
    pipe_condvar_signal(fence->signalled);
 
diff --git a/src/gallium/drivers/llvmpipe/lp_fence.h b/src/gallium/drivers/llvmpipe/lp_fence.h
index 13358fb99f..b80af5c654 100644
--- a/src/gallium/drivers/llvmpipe/lp_fence.h
+++ b/src/gallium/drivers/llvmpipe/lp_fence.h
@@ -41,6 +41,7 @@ struct pipe_screen;
 struct lp_fence
 {
    struct pipe_reference reference;
+   unsigned id;
 
    pipe_mutex mutex;
    pipe_condvar signalled;
diff --git a/src/gallium/drivers/llvmpipe/lp_flush.c b/src/gallium/drivers/llvmpipe/lp_flush.c
index 845292f4ab..040fe0ba9a 100644
--- a/src/gallium/drivers/llvmpipe/lp_flush.c
+++ b/src/gallium/drivers/llvmpipe/lp_flush.c
@@ -45,14 +45,15 @@
 void
 llvmpipe_flush( struct pipe_context *pipe,
                 unsigned flags,
-                struct pipe_fence_handle **fence )
+                struct pipe_fence_handle **fence,
+                const char *reason)
 {
    struct llvmpipe_context *llvmpipe = llvmpipe_context(pipe);
 
    draw_flush(llvmpipe->draw);
 
    /* ask the setup module to flush */
-   lp_setup_flush(llvmpipe->setup, flags, fence);
+   lp_setup_flush(llvmpipe->setup, flags, fence, reason);
 
    /* Enable to dump BMPs of the color/depth buffers each frame */
    if (0) {
@@ -76,6 +77,17 @@ llvmpipe_flush( struct pipe_context *pipe,
    }
 }
 
+void
+llvmpipe_finish( struct pipe_context *pipe,
+                 const char *reason )
+{
+   struct pipe_fence_handle *fence = NULL;
+   llvmpipe_flush(pipe, 0, &fence, reason);
+   if (fence) {
+      pipe->screen->fence_finish(pipe->screen, fence, 0);
+      pipe->screen->fence_reference(pipe->screen, &fence, NULL);
+   }
+}
 
 /**
  * Flush context if necessary.
@@ -93,7 +105,8 @@ llvmpipe_flush_resource(struct pipe_context *pipe,
                         unsigned flush_flags,
                         boolean read_only,
                         boolean cpu_access,
-                        boolean do_not_block)
+                        boolean do_not_block,
+                        const char *reason)
 {
    unsigned referenced;
 
@@ -106,31 +119,16 @@ llvmpipe_flush_resource(struct pipe_context *pipe,
          /*
           * Flush and wait.
           */
-
-         struct pipe_fence_handle *fence = NULL;
-
          if (do_not_block)
             return FALSE;
 
-         /*
-          * Do the unswizzling in parallel.
-          *
-          * XXX: Don't abuse the PIPE_FLUSH_FRAME flag for this.
-          */
-         flush_flags |= PIPE_FLUSH_FRAME;
-
-         llvmpipe_flush(pipe, flush_flags, &fence);
-
-         if (fence) {
-            pipe->screen->fence_finish(pipe->screen, fence, 0);
-            pipe->screen->fence_reference(pipe->screen, &fence, NULL);
-         }
+         llvmpipe_finish(pipe, reason);
       } else {
          /*
           * Just flush.
           */
 
-         llvmpipe_flush(pipe, flush_flags, NULL);
+         llvmpipe_flush(pipe, flush_flags, NULL, reason);
       }
    }
 
diff --git a/src/gallium/drivers/llvmpipe/lp_flush.h b/src/gallium/drivers/llvmpipe/lp_flush.h
index 7b605681a9..bb538b2bd8 100644
--- a/src/gallium/drivers/llvmpipe/lp_flush.h
+++ b/src/gallium/drivers/llvmpipe/lp_flush.h
@@ -34,8 +34,14 @@ struct pipe_context;
 struct pipe_fence_handle;
 
 void
-llvmpipe_flush(struct pipe_context *pipe, unsigned flags,
-               struct pipe_fence_handle **fence);
+llvmpipe_flush(struct pipe_context *pipe,
+               unsigned flags,
+               struct pipe_fence_handle **fence,
+               const char *reason);
+
+void
+llvmpipe_finish( struct pipe_context *pipe,
+                 const char *reason );
 
 boolean
 llvmpipe_flush_resource(struct pipe_context *pipe,
@@ -45,6 +51,7 @@ llvmpipe_flush_resource(struct pipe_context *pipe,
                         unsigned flush_flags,
                         boolean read_only,
                         boolean cpu_access,
-                        boolean do_not_block);
+                        boolean do_not_block,
+                        const char *reason);
 
 #endif
diff --git a/src/gallium/drivers/llvmpipe/lp_query.c b/src/gallium/drivers/llvmpipe/lp_query.c
index 02eeaf6487..540eea7fd1 100644
--- a/src/gallium/drivers/llvmpipe/lp_query.c
+++ b/src/gallium/drivers/llvmpipe/lp_query.c
@@ -35,9 +35,9 @@
 #include "util/u_memory.h"
 #include "lp_context.h"
 #include "lp_flush.h"
+#include "lp_fence.h"
 #include "lp_query.h"
 #include "lp_rast.h"
-#include "lp_rast_priv.h"
 #include "lp_state.h"
 
 
@@ -69,12 +69,7 @@ llvmpipe_destroy_query(struct pipe_context *pipe, struct pipe_query *q)
    struct llvmpipe_query *pq = llvmpipe_query(q);
    /* query might still be in process if we never waited for the result */
    if (!pq->done) {
-     struct pipe_fence_handle *fence = NULL;
-     llvmpipe_flush(pipe, 0, &fence);
-     if (fence) {
-         pipe->screen->fence_finish(pipe->screen, fence, 0);
-         pipe->screen->fence_reference(pipe->screen, &fence, NULL);
-      }
+      llvmpipe_finish(pipe, __FUNCTION__);
    }
 
    pipe_mutex_destroy(pq->mutex);
@@ -93,16 +88,11 @@ llvmpipe_get_query_result(struct pipe_context *pipe,
 
    if (!pq->done) {
       if (wait) {
-         struct pipe_fence_handle *fence = NULL;
-         llvmpipe_flush(pipe, 0, &fence);
-         if (fence) {
-            pipe->screen->fence_finish(pipe->screen, fence, 0);
-            pipe->screen->fence_reference(pipe->screen, &fence, NULL);
-         }
+         llvmpipe_finish(pipe, __FUNCTION__);
       }
       /* this is a bit inconsequent but should be ok */
       else {
-         llvmpipe_flush(pipe, 0, NULL);
+         llvmpipe_flush(pipe, 0, NULL, __FUNCTION__);
       }
    }
 
@@ -125,12 +115,7 @@ llvmpipe_begin_query(struct pipe_context *pipe, struct pipe_query *q)
     * frame of rendering.
     */
    if (pq->binned) {
-      struct pipe_fence_handle *fence;
-      llvmpipe_flush(pipe, 0, &fence);
-      if (fence) {
-         pipe->screen->fence_finish(pipe->screen, fence, 0);
-         pipe->screen->fence_reference(pipe->screen, &fence, NULL);
-      }
+      llvmpipe_finish(pipe, __FUNCTION__);
    }
 
    lp_setup_begin_query(llvmpipe->setup, pq);
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 6968cda629..14a156378a 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -61,6 +61,8 @@ static const struct debug_named_value lp_debug_flags[] = {
    { "show_tiles",    DEBUG_SHOW_TILES, NULL },
    { "show_subtiles", DEBUG_SHOW_SUBTILES, NULL },
    { "counters", DEBUG_COUNTERS, NULL },
+   { "scene", DEBUG_SCENE, NULL },
+   { "fence", DEBUG_FENCE, NULL },
    DEBUG_NAMED_VALUE_END
 };
 #endif
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c
index 556e571585..6eede83bfb 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup.c
@@ -275,9 +275,10 @@ set_scene_state( struct lp_setup_context *setup,
 void
 lp_setup_flush( struct lp_setup_context *setup,
                 unsigned flags,
-                struct pipe_fence_handle **fence)
+                struct pipe_fence_handle **fence,
+                const char *reason)
 {
-   LP_DBG(DEBUG_SETUP, "%s\n", __FUNCTION__);
+   LP_DBG(DEBUG_SETUP, "%s %s\n", __FUNCTION__, reason);
 
    if (setup->scene) {
       if (fence) {
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.h b/src/gallium/drivers/llvmpipe/lp_setup.h
index 73b1c85325..a41bb8863b 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup.h
@@ -85,7 +85,8 @@ lp_setup_fence( struct lp_setup_context *setup );
 void
 lp_setup_flush( struct lp_setup_context *setup,
                 unsigned flags,
-                struct pipe_fence_handle **fence);
+                struct pipe_fence_handle **fence,
+                const char *reason);
 
 
 void
diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c b/src/gallium/drivers/llvmpipe/lp_state_fs.c
index 35ef63389c..33c1a49efe 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
@@ -927,7 +927,6 @@ static void
 llvmpipe_delete_fs_state(struct pipe_context *pipe, void *fs)
 {
    struct llvmpipe_context *llvmpipe = llvmpipe_context(pipe);
-   struct pipe_fence_handle *fence = NULL;
    struct lp_fragment_shader *shader = fs;
    struct lp_fs_variant_list_item *li;
 
@@ -940,12 +939,7 @@ llvmpipe_delete_fs_state(struct pipe_context *pipe, void *fs)
     * Flushing alone might not sufficient we need to wait on it too.
     */
 
-   llvmpipe_flush(pipe, 0, &fence);
-
-   if (fence) {
-      pipe->screen->fence_finish(pipe->screen, fence, 0);
-      pipe->screen->fence_reference(pipe->screen, &fence, NULL);
-   }
+   llvmpipe_finish(pipe, __FUNCTION__);
 
    li = first_elem(&shader->variants);
    while(!at_end(&shader->variants, li)) {
@@ -1148,19 +1142,14 @@ llvmpipe_update_fs(struct llvmpipe_context *lp)
       unsigned i;
       if (lp->nr_fs_variants >= LP_MAX_SHADER_VARIANTS) {
          struct pipe_context *pipe = &lp->pipe;
-         struct pipe_fence_handle *fence = NULL;
 
          /*
           * XXX: we need to flush the context until we have some sort of reference
           * counting in fragment shaders as they may still be binned
           * Flushing alone might not be sufficient we need to wait on it too.
           */
-         llvmpipe_flush(pipe, 0, &fence);
+         llvmpipe_finish(pipe, __FUNCTION__);
 
-         if (fence) {
-            pipe->screen->fence_finish(pipe->screen, fence, 0);
-            pipe->screen->fence_reference(pipe->screen, &fence, NULL);
-         }
          for (i = 0; i < LP_MAX_SHADER_VARIANTS / 4; i++) {
             struct lp_fs_variant_list_item *item = last_elem(&lp->fs_variants_list);
             remove_shader_variant(lp, item->base);
diff --git a/src/gallium/drivers/llvmpipe/lp_surface.c b/src/gallium/drivers/llvmpipe/lp_surface.c
index f761e82850..63ddc669c2 100644
--- a/src/gallium/drivers/llvmpipe/lp_surface.c
+++ b/src/gallium/drivers/llvmpipe/lp_surface.c
@@ -68,14 +68,16 @@ lp_resource_copy(struct pipe_context *pipe,
                            0, /* flush_flags */
                            FALSE, /* read_only */
                            TRUE, /* cpu_access */
-                           FALSE); /* do_not_block */
+                           FALSE,
+                           "blit dst"); /* do_not_block */
 
    llvmpipe_flush_resource(pipe,
                            src, subsrc.face, subsrc.level,
                            0, /* flush_flags */
                            TRUE, /* read_only */
                            TRUE, /* cpu_access */
-                           FALSE); /* do_not_block */
+                           FALSE,
+                           "blit src"); /* do_not_block */
 
    /*
    printf("surface copy from %u to %u: %u,%u to %u,%u %u x %u\n",
diff --git a/src/gallium/drivers/llvmpipe/lp_texture.c b/src/gallium/drivers/llvmpipe/lp_texture.c
index ff4773fd7c..5832ea2744 100644
--- a/src/gallium/drivers/llvmpipe/lp_texture.c
+++ b/src/gallium/drivers/llvmpipe/lp_texture.c
@@ -584,7 +584,8 @@ llvmpipe_get_transfer(struct pipe_context *pipe,
                                    0, /* flush_flags */
                                    read_only,
                                    TRUE, /* cpu_access */
-                                   do_not_block)) {
+                                   do_not_block,
+                                   "transfer dest")) {
          /*
           * It would have blocked, but state tracker requested no to.
           */
-- 
cgit v1.2.3


From 1e926fe42a9780fd5e6574df2014a75d4af1101d Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 20 Aug 2010 15:15:36 +0100
Subject: llvmpipe: wake all threads waiting on a fence

---
 src/gallium/drivers/llvmpipe/lp_fence.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_fence.c b/src/gallium/drivers/llvmpipe/lp_fence.c
index 4d549b0750..1f96dcd81a 100644
--- a/src/gallium/drivers/llvmpipe/lp_fence.c
+++ b/src/gallium/drivers/llvmpipe/lp_fence.c
@@ -146,7 +146,9 @@ lp_fence_signal(struct lp_fence *fence)
       debug_printf("%s count=%u rank=%u\n", __FUNCTION__,
                    fence->count, fence->rank);
 
-   pipe_condvar_signal(fence->signalled);
+   /* Wakeup all threads waiting on the mutex:
+    */
+   pipe_condvar_broadcast(fence->signalled);
 
    pipe_mutex_unlock(fence->mutex);
 }
-- 
cgit v1.2.3


From 5a45e53df4419fde1fe7696f3a9459893363f7c5 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 20 Aug 2010 15:25:27 +0100
Subject: llvmpipe: move some fence functions into lp_screen.c

---
 src/gallium/drivers/llvmpipe/lp_fence.c  | 73 ++++++++------------------------
 src/gallium/drivers/llvmpipe/lp_fence.h  | 12 ++++++
 src/gallium/drivers/llvmpipe/lp_screen.c | 49 ++++++++++++++++++++-
 src/gallium/drivers/llvmpipe/lp_setup.c  |  2 +
 4 files changed, 79 insertions(+), 57 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_fence.c b/src/gallium/drivers/llvmpipe/lp_fence.c
index 1f96dcd81a..3a55e76bc3 100644
--- a/src/gallium/drivers/llvmpipe/lp_fence.c
+++ b/src/gallium/drivers/llvmpipe/lp_fence.c
@@ -75,58 +75,6 @@ lp_fence_destroy(struct lp_fence *fence)
 }
 
 
-/**
- * For reference counting.
- * This is a Gallium API function.
- */
-static void
-llvmpipe_fence_reference(struct pipe_screen *screen,
-                         struct pipe_fence_handle **ptr,
-                         struct pipe_fence_handle *fence)
-{
-   struct lp_fence **old = (struct lp_fence **) ptr;
-   struct lp_fence *f = (struct lp_fence *) fence;
-
-   lp_fence_reference(old, f);
-}
-
-
-/**
- * Has the fence been executed/finished?
- * This is a Gallium API function.
- */
-static int
-llvmpipe_fence_signalled(struct pipe_screen *screen,
-                         struct pipe_fence_handle *fence,
-                         unsigned flag)
-{
-   struct lp_fence *f = (struct lp_fence *) fence;
-
-   return f->count == f->rank;
-}
-
-
-/**
- * Wait for the fence to finish.
- * This is a Gallium API function.
- */
-static int
-llvmpipe_fence_finish(struct pipe_screen *screen,
-                      struct pipe_fence_handle *fence_handle,
-                      unsigned flag)
-{
-   struct lp_fence *fence = (struct lp_fence *) fence_handle;
-
-   pipe_mutex_lock(fence->mutex);
-   while (fence->count < fence->rank) {
-      pipe_condvar_wait(fence->signalled, fence->mutex);
-   }
-   pipe_mutex_unlock(fence->mutex);
-
-   return 0;
-}
-
-
 /**
  * Called by the rendering threads to increment the fence counter.
  * When the counter == the rank, the fence is finished.
@@ -153,11 +101,24 @@ lp_fence_signal(struct lp_fence *fence)
    pipe_mutex_unlock(fence->mutex);
 }
 
+boolean
+lp_fence_signalled(struct lp_fence *f)
+{
+   return f->count == f->rank;
+}
 
 void
-llvmpipe_init_screen_fence_funcs(struct pipe_screen *screen)
+lp_fence_wait(struct lp_fence *f)
 {
-   screen->fence_reference = llvmpipe_fence_reference;
-   screen->fence_signalled = llvmpipe_fence_signalled;
-   screen->fence_finish = llvmpipe_fence_finish;
+   if (LP_DEBUG & DEBUG_FENCE)
+      debug_printf("%s %d\n", __FUNCTION__, f->id);
+
+   pipe_mutex_lock(f->mutex);
+   assert(f->issued);
+   while (f->count < f->rank) {
+      pipe_condvar_wait(f->signalled, f->mutex);
+   }
+   pipe_mutex_unlock(f->mutex);
 }
+
+
diff --git a/src/gallium/drivers/llvmpipe/lp_fence.h b/src/gallium/drivers/llvmpipe/lp_fence.h
index b80af5c654..3c59118780 100644
--- a/src/gallium/drivers/llvmpipe/lp_fence.h
+++ b/src/gallium/drivers/llvmpipe/lp_fence.h
@@ -46,6 +46,7 @@ struct lp_fence
    pipe_mutex mutex;
    pipe_condvar signalled;
 
+   boolean issued;
    unsigned rank;
    unsigned count;
 };
@@ -58,6 +59,11 @@ lp_fence_create(unsigned rank);
 void
 lp_fence_signal(struct lp_fence *fence);
 
+boolean
+lp_fence_signalled(struct lp_fence *fence);
+
+void
+lp_fence_wait(struct lp_fence *fence);
 
 void
 llvmpipe_init_screen_fence_funcs(struct pipe_screen *screen);
@@ -79,5 +85,11 @@ lp_fence_reference(struct lp_fence **ptr,
    *ptr = f;
 }
 
+static INLINE boolean
+lp_fence_issued(const struct lp_fence *fence)
+{
+   return fence->issued;
+}
+
 
 #endif /* LP_FENCE_H */
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 14a156378a..9b7e0d51cd 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -317,6 +317,51 @@ llvmpipe_destroy_screen( struct pipe_screen *_screen )
 
 
 
+
+/**
+ * Fence reference counting.
+ */
+static void
+llvmpipe_fence_reference(struct pipe_screen *screen,
+                         struct pipe_fence_handle **ptr,
+                         struct pipe_fence_handle *fence)
+{
+   struct lp_fence **old = (struct lp_fence **) ptr;
+   struct lp_fence *f = (struct lp_fence *) fence;
+
+   lp_fence_reference(old, f);
+}
+
+
+/**
+ * Has the fence been executed/finished?
+ */
+static int
+llvmpipe_fence_signalled(struct pipe_screen *screen,
+                         struct pipe_fence_handle *fence,
+                         unsigned flag)
+{
+   struct lp_fence *f = (struct lp_fence *) fence;
+   return lp_fence_signalled(f);
+}
+
+
+/**
+ * Wait for the fence to finish.
+ */
+static int
+llvmpipe_fence_finish(struct pipe_screen *screen,
+                      struct pipe_fence_handle *fence_handle,
+                      unsigned flag)
+{
+   struct lp_fence *f = (struct lp_fence *) fence_handle;
+
+   lp_fence_wait(f);
+   return 0;
+}
+
+
+
 /**
  * Create a new pipe_screen object
  * Note: we're not presently subclassing pipe_screen (no llvmpipe_screen).
@@ -354,9 +399,11 @@ llvmpipe_create_screen(struct sw_winsys *winsys)
 
    screen->base.context_create = llvmpipe_create_context;
    screen->base.flush_frontbuffer = llvmpipe_flush_frontbuffer;
+   screen->base.fence_reference = llvmpipe_fence_reference;
+   screen->base.fence_signalled = llvmpipe_fence_signalled;
+   screen->base.fence_finish = llvmpipe_fence_finish;
 
    llvmpipe_init_screen_resource_funcs(&screen->base);
-   llvmpipe_init_screen_fence_funcs(&screen->base);
 
    lp_jit_screen_init(screen);
 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c
index 6eede83bfb..5389de8b63 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup.c
@@ -288,6 +288,8 @@ lp_setup_flush( struct lp_setup_context *setup,
          *fence = lp_setup_fence( setup );
       }
 
+      if (setup->scene->fence)
+         setup->scene->fence->issued = TRUE;
    }
 
    set_scene_state( setup, SETUP_FLUSHED );
-- 
cgit v1.2.3


From 98f3ff8f4a761d579ee9b42ee3090635519213a5 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 20 Aug 2010 15:45:25 +0100
Subject: llvmpipe: more rasterization counters

---
 src/gallium/drivers/llvmpipe/lp_perf.c         | 21 +++++++++++++++------
 src/gallium/drivers/llvmpipe/lp_perf.h         |  7 +++++++
 src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h |  7 +++++++
 3 files changed, 29 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_perf.c b/src/gallium/drivers/llvmpipe/lp_perf.c
index 083e7e30a5..e22532f25c 100644
--- a/src/gallium/drivers/llvmpipe/lp_perf.c
+++ b/src/gallium/drivers/llvmpipe/lp_perf.c
@@ -46,7 +46,7 @@ lp_print_counters(void)
 {
    if (LP_DEBUG & DEBUG_COUNTERS) {
       unsigned total_64, total_16, total_4;
-      float p1, p2, p3, p4;
+      float p1, p2, p3, p5, p6;
 
       debug_printf("llvmpipe: nr_triangles:                 %9u\n", lp_count.nr_tris);
       debug_printf("llvmpipe: nr_culled_triangles:          %9u\n", lp_count.nr_culled_tris);
@@ -58,11 +58,15 @@ lp_print_counters(void)
       p1 = 100.0 * (float) lp_count.nr_empty_64 / (float) total_64;
       p2 = 100.0 * (float) lp_count.nr_fully_covered_64 / (float) total_64;
       p3 = 100.0 * (float) lp_count.nr_partially_covered_64 / (float) total_64;
-      p4 = 100.0 * (float) lp_count.nr_shade_opaque_64 / (float) total_64;
+      p5 = 100.0 * (float) lp_count.nr_shade_opaque_64 / (float) total_64;
+      p6 = 100.0 * (float) lp_count.nr_shade_64 / (float) total_64;
 
       debug_printf("llvmpipe: nr_64x64:                     %9u\n", total_64);
       debug_printf("llvmpipe:   nr_fully_covered_64x64:     %9u (%3.0f%% of %u)\n", lp_count.nr_fully_covered_64, p2, total_64);
-      debug_printf("llvmpipe:     nr_shade_opaque_64x64:    %9u (%3.0f%% of %u)\n", lp_count.nr_shade_opaque_64, p4, total_64);
+      debug_printf("llvmpipe:     nr_shade_opaque_64x64:    %9u (%3.0f%% of %u)\n", lp_count.nr_shade_opaque_64, p5, total_64);
+      debug_printf("llvmpipe:        nr_pure_shade_opaque:  %9u (%3.0f%% of %u)\n", lp_count.nr_pure_shade_opaque_64, 0.0, lp_count.nr_shade_opaque_64);
+      debug_printf("llvmpipe:     nr_shade_64x64:           %9u (%3.0f%% of %u)\n", lp_count.nr_shade_64, p6, total_64);
+      debug_printf("llvmpipe:        nr_pure_shade:         %9u (%3.0f%% of %u)\n", lp_count.nr_pure_shade_64, 0.0, lp_count.nr_shade_64);
       debug_printf("llvmpipe:   nr_partially_covered_64x64: %9u (%3.0f%% of %u)\n", lp_count.nr_partially_covered_64, p3, total_64);
       debug_printf("llvmpipe:   nr_empty_64x64:             %9u (%3.0f%% of %u)\n", lp_count.nr_empty_64, p1, total_64);
 
@@ -79,12 +83,17 @@ lp_print_counters(void)
       debug_printf("llvmpipe:   nr_partially_covered_16x16: %9u (%3.0f%% of %u)\n", lp_count.nr_partially_covered_16, p3, total_16);
       debug_printf("llvmpipe:   nr_empty_16x16:             %9u (%3.0f%% of %u)\n", lp_count.nr_empty_16, p1, total_16);
 
-      total_4 = (lp_count.nr_empty_4 + lp_count.nr_non_empty_4);
+      total_4 = (lp_count.nr_empty_4 +
+                 lp_count.nr_fully_covered_4 +
+                 lp_count.nr_partially_covered_4);
 
       p1 = 100.0 * (float) lp_count.nr_empty_4 / (float) total_4;
-      p2 = 100.0 * (float) lp_count.nr_non_empty_4 / (float) total_4;
+      p2 = 100.0 * (float) lp_count.nr_fully_covered_4 / (float) total_4;
+      p3 = 100.0 * (float) lp_count.nr_partially_covered_4 / (float) total_4;
 
-      debug_printf("llvmpipe: nr_4x4:                       %9u\n", total_4);
+      debug_printf("llvmpipe: nr_tri_4x4:                   %9u\n", total_4);
+      debug_printf("llvmpipe:   nr_fully_covered_4x4:       %9u (%3.0f%% of %u)\n", lp_count.nr_fully_covered_4, p2, total_4);
+      debug_printf("llvmpipe:   nr_partially_covered_4x4:   %9u (%3.0f%% of %u)\n", lp_count.nr_partially_covered_4, p3, total_4);
       debug_printf("llvmpipe:   nr_empty_4x4:               %9u (%3.0f%% of %u)\n", lp_count.nr_empty_4, p1, total_4);
       debug_printf("llvmpipe:   nr_non_empty_4x4:           %9u (%3.0f%% of %u)\n", lp_count.nr_non_empty_4, p2, total_4);
 
diff --git a/src/gallium/drivers/llvmpipe/lp_perf.h b/src/gallium/drivers/llvmpipe/lp_perf.h
index 4774f64550..c28652fc30 100644
--- a/src/gallium/drivers/llvmpipe/lp_perf.h
+++ b/src/gallium/drivers/llvmpipe/lp_perf.h
@@ -44,11 +44,16 @@ struct lp_counters
    unsigned nr_empty_64;
    unsigned nr_fully_covered_64;
    unsigned nr_partially_covered_64;
+   unsigned nr_pure_shade_opaque_64;
+   unsigned nr_pure_shade_64;
+   unsigned nr_shade_64;
    unsigned nr_shade_opaque_64;
    unsigned nr_empty_16;
    unsigned nr_fully_covered_16;
    unsigned nr_partially_covered_16;
    unsigned nr_empty_4;
+   unsigned nr_fully_covered_4;
+   unsigned nr_partially_covered_4;
    unsigned nr_non_empty_4;
    unsigned nr_llvm_compiles;
    int64_t llvm_compile_time;  /**< total, in microseconds */
@@ -66,9 +71,11 @@ extern struct lp_counters lp_count;
 #ifdef DEBUG
 #define LP_COUNT(counter) lp_count.counter++
 #define LP_COUNT_ADD(counter, incr)  lp_count.counter += (incr)
+#define LP_COUNT_GET(counter) (lp_count.counter)
 #else
 #define LP_COUNT(counter)
 #define LP_COUNT_ADD(counter, incr) (void) incr
+#define LP_COUNT_GET(counter) 0
 #endif
 
 
diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
index 43f72d8ca8..70a4b64c8d 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
@@ -102,6 +102,8 @@ TAG(do_block_16)(struct lp_rasterizer_task *task,
 
    assert((partial_mask & inmask) == 0);
 
+   LP_COUNT_ADD(nr_empty_4, util_bitcount(0xffff & ~(partial_mask | inmask)));
+
    /* Iterate over partials:
     */
    while (partial_mask) {
@@ -114,6 +116,8 @@ TAG(do_block_16)(struct lp_rasterizer_task *task,
 
       partial_mask &= ~(1 << i);
 
+      LP_COUNT(nr_partially_covered_4);
+
       for (j = 0; j < NR_PLANES; j++)
          cx[j] = (c[j] 
 		  - plane[j].dcdx * ix
@@ -133,6 +137,7 @@ TAG(do_block_16)(struct lp_rasterizer_task *task,
 
       inmask &= ~(1 << i);
 
+      LP_COUNT(nr_fully_covered_4);
       block_full_4(task, tri, px, py);
    }
 }
@@ -190,6 +195,8 @@ TAG(lp_rast_triangle)(struct lp_rasterizer_task *task,
 
    assert((partial_mask & inmask) == 0);
 
+   LP_COUNT_ADD(nr_empty_16, util_bitcount(0xffff & ~(partial_mask | inmask)));
+
    /* Iterate over partials:
     */
    while (partial_mask) {
-- 
cgit v1.2.3


From c25151dd6a06acd93c8bf0d9e79fdcf134ffe818 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 20 Aug 2010 16:18:23 +0100
Subject: llvmpipe: cull zero-area triangles early

---
 src/gallium/drivers/llvmpipe/lp_setup_tri.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index 614a6372b4..b4325390fe 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -819,9 +819,10 @@ static void triangle_both( struct lp_setup_context *setup,
    const float fy = v1[0][1] - v2[0][1];
 
    /* det = cross(e,f).z */
-   if (ex * fy - ey * fx < 0.0f) 
+   const float det = ex * fy - ey * fx;
+   if (det < 0.0f) 
       triangle_ccw( setup, v0, v1, v2 );
-   else
+   else if (det > 0.0f)
       triangle_cw( setup, v0, v1, v2 );
 }
 
-- 
cgit v1.2.3


From d808f7b53ec71a7684bac7e6b536911fc27d5238 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Tue, 24 Aug 2010 19:58:54 +0100
Subject: llvmpipe: better triangle debugging

---
 src/gallium/drivers/llvmpipe/lp_setup_context.h | 12 ++++
 src/gallium/drivers/llvmpipe/lp_setup_tri.c     | 74 ++++++++++++++++++-------
 2 files changed, 67 insertions(+), 19 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup_context.h b/src/gallium/drivers/llvmpipe/lp_setup_context.h
index a0606f5034..102361cca3 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup_context.h
@@ -158,4 +158,16 @@ void lp_setup_update_state( struct lp_setup_context *setup );
 
 void lp_setup_destroy( struct lp_setup_context *setup );
 
+void
+lp_setup_print_triangle(struct lp_setup_context *setup,
+                        const float (*v0)[4],
+                        const float (*v1)[4],
+                        const float (*v2)[4]);
+
+void
+lp_setup_print_vertex(struct lp_setup_context *setup,
+                      const char *name,
+                      const float (*v)[4]);
+
 #endif
+
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index b4325390fe..d6c837d8d4 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -357,31 +357,67 @@ alloc_triangle(struct lp_scene *scene,
    return tri;
 }
 
+void
+lp_setup_print_vertex(struct lp_setup_context *setup,
+                      const char *name,
+                      const float (*v)[4])
+{
+   int i, j;
+
+   debug_printf("   wpos (%s[0]) xyzw %f %f %f %f\n",
+                name,
+                v[0][0], v[0][1], v[0][2], v[0][3]);
+
+   for (i = 0; i < setup->fs.nr_inputs; i++) {
+      const float *in = v[setup->fs.input[i].src_index];
+
+      debug_printf("  in[%d] (%s[%d]) %s%s%s%s ",
+                   i, 
+                   name, setup->fs.input[i].src_index,
+                   (setup->fs.input[i].usage_mask & 0x1) ? "x" : " ",
+                   (setup->fs.input[i].usage_mask & 0x2) ? "y" : " ",
+                   (setup->fs.input[i].usage_mask & 0x4) ? "z" : " ",
+                   (setup->fs.input[i].usage_mask & 0x8) ? "w" : " ");
+
+      for (j = 0; j < 4; j++)
+         if (setup->fs.input[i].usage_mask & (1<<j))
+            debug_printf("%.5f ", in[j]);
+
+      debug_printf("\n");
+   }
+}
+
 
 /**
  * Print triangle vertex attribs (for debug).
  */
-static void
-print_triangle(struct lp_setup_context *setup,
-               const float (*v1)[4],
-               const float (*v2)[4],
-               const float (*v3)[4])
+void
+lp_setup_print_triangle(struct lp_setup_context *setup,
+                        const float (*v0)[4],
+                        const float (*v1)[4],
+                        const float (*v2)[4])
 {
-   uint i;
+   debug_printf("triangle\n");
 
-   debug_printf("llvmpipe triangle\n");
-   for (i = 0; i < 1 + setup->fs.nr_inputs; i++) {
-      debug_printf("  v1[%d]:  %f %f %f %f\n", i,
-                   v1[i][0], v1[i][1], v1[i][2], v1[i][3]);
-   }
-   for (i = 0; i < 1 + setup->fs.nr_inputs; i++) {
-      debug_printf("  v2[%d]:  %f %f %f %f\n", i,
-                   v2[i][0], v2[i][1], v2[i][2], v2[i][3]);
-   }
-   for (i = 0; i < 1 + setup->fs.nr_inputs; i++) {
-      debug_printf("  v3[%d]:  %f %f %f %f\n", i,
-                   v3[i][0], v3[i][1], v3[i][2], v3[i][3]);
+   {
+      const float ex = v0[0][0] - v2[0][0];
+      const float ey = v0[0][1] - v2[0][1];
+      const float fx = v1[0][0] - v2[0][0];
+      const float fy = v1[0][1] - v2[0][1];
+
+      /* det = cross(e,f).z */
+      const float det = ex * fy - ey * fx;
+      if (det < 0.0f) 
+         debug_printf("   - ccw\n");
+      else if (det > 0.0f)
+         debug_printf("   - cw\n");
+      else
+         debug_printf("   - zero area\n");
    }
+
+   lp_setup_print_vertex(setup, "v0", v0);
+   lp_setup_print_vertex(setup, "v1", v1);
+   lp_setup_print_vertex(setup, "v2", v2);
 }
 
 
@@ -421,7 +457,7 @@ do_triangle_ccw(struct lp_setup_context *setup,
    int nr_planes = 3;
       
    if (0)
-      print_triangle(setup, v1, v2, v3);
+      lp_setup_print_triangle(setup, v1, v2, v3);
 
    if (setup->scissor_test) {
       nr_planes = 7;
-- 
cgit v1.2.3


From 29bcbf5e797a18430285c75abb8a9300c8defe1d Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Tue, 24 Aug 2010 20:04:08 +0100
Subject: llvmpipe: track drawing region as a single u_rect

---
 src/gallium/drivers/llvmpipe/lp_setup.c         |  29 ++++--
 src/gallium/drivers/llvmpipe/lp_setup_context.h |   7 +-
 src/gallium/drivers/llvmpipe/lp_setup_tri.c     | 113 ++++++++++++------------
 3 files changed, 86 insertions(+), 63 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c
index 5389de8b63..0c6d2de193 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup.c
@@ -315,6 +315,11 @@ lp_setup_bind_framebuffer( struct lp_setup_context *setup,
     * scene.
     */
    util_copy_framebuffer_state(&setup->fb, fb);
+   setup->framebuffer.x0 = 0;
+   setup->framebuffer.y0 = 0;
+   setup->framebuffer.x1 = fb->width-1;
+   setup->framebuffer.y1 = fb->height-1;
+   setup->dirty |= LP_SETUP_NEW_SCISSOR;
 }
 
 
@@ -472,8 +477,12 @@ lp_setup_set_triangle_state( struct lp_setup_context *setup,
    setup->ccw_is_frontface = ccw_is_frontface;
    setup->cullmode = cull_mode;
    setup->triangle = first_triangle;
-   setup->scissor_test = scissor;
    setup->pixel_offset = gl_rasterization_rules ? 0.5f : 0.0f;
+
+   if (setup->scissor_test != scissor) {
+      setup->dirty |= LP_SETUP_NEW_SCISSOR;
+      setup->scissor_test = scissor;
+   }
 }
 
 
@@ -562,10 +571,11 @@ lp_setup_set_scissor( struct lp_setup_context *setup,
 
    assert(scissor);
 
-   if (memcmp(&setup->scissor.current, scissor, sizeof(*scissor)) != 0) {
-      setup->scissor.current = *scissor; /* struct copy */
-      setup->dirty |= LP_SETUP_NEW_SCISSOR;
-   }
+   setup->scissor.x0 = scissor->minx;
+   setup->scissor.x1 = scissor->maxx-1;
+   setup->scissor.y0 = scissor->miny;
+   setup->scissor.y1 = scissor->maxy-1;
+   setup->dirty |= LP_SETUP_NEW_SCISSOR;
 }
 
 
@@ -805,6 +815,15 @@ lp_setup_update_state( struct lp_setup_context *setup )
          for (i = 0; i < Elements(setup->fs.current_tex); i++) {
             if (setup->fs.current_tex[i])
                lp_scene_add_resource_reference(scene, setup->fs.current_tex[i]);
+   if (setup->dirty & LP_SETUP_NEW_SCISSOR) {
+      setup->draw_region = setup->framebuffer;
+      if (setup->scissor_test) {
+         u_rect_possible_intersection(&setup->scissor,
+                                      &setup->draw_region);
+      }
+   }
+                                      
+
          }
       }
    }
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_context.h b/src/gallium/drivers/llvmpipe/lp_setup_context.h
index 102361cca3..1a147e0353 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup_context.h
@@ -41,6 +41,7 @@
 #include "lp_scene.h"
 
 #include "draw/draw_vbuf.h"
+#include "util/u_rect.h"
 
 #define LP_SETUP_NEW_FS          0x01
 #define LP_SETUP_NEW_CONSTANTS   0x02
@@ -92,6 +93,9 @@ struct lp_setup_context
    float pixel_offset;
 
    struct pipe_framebuffer_state fb;
+   struct u_rect framebuffer;
+   struct u_rect scissor;
+   struct u_rect draw_region;   /* intersection of fb & scissor */
 
    struct {
       unsigned flags;
@@ -127,9 +131,6 @@ struct lp_setup_context
       uint8_t *stored;
    } blend_color;
 
-   struct {
-      struct pipe_scissor_state current;
-   } scissor;
 
    unsigned dirty;   /**< bitmask of LP_SETUP_NEW_x bits */
 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index d6c837d8d4..fe5c9358dd 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -31,6 +31,7 @@
 
 #include "util/u_math.h"
 #include "util/u_memory.h"
+#include "util/u_rect.h"
 #include "lp_perf.h"
 #include "lp_setup_context.h"
 #include "lp_rast.h"
@@ -450,7 +451,7 @@ do_triangle_ccw(struct lp_setup_context *setup,
    struct lp_rast_triangle *tri;
    struct tri_info info;
    int area;
-   int minx, maxx, miny, maxy;
+   struct u_rect bbox;
    int ix0, ix1, iy0, iy1;
    unsigned tri_bytes;
    int i;
@@ -466,6 +467,50 @@ do_triangle_ccw(struct lp_setup_context *setup,
       nr_planes = 3;
    }
 
+   /* x/y positions in fixed point */
+   info.x[0] = subpixel_snap(v1[0][0] - setup->pixel_offset);
+   info.x[1] = subpixel_snap(v2[0][0] - setup->pixel_offset);
+   info.x[2] = subpixel_snap(v3[0][0] - setup->pixel_offset);
+   info.y[0] = subpixel_snap(v1[0][1] - setup->pixel_offset);
+   info.y[1] = subpixel_snap(v2[0][1] - setup->pixel_offset);
+   info.y[2] = subpixel_snap(v3[0][1] - setup->pixel_offset);
+
+
+
+   /* Bounding rectangle (in pixels) */
+   {
+      /* Yes this is necessary to accurately calculate bounding boxes
+       * with the two fill-conventions we support.  GL (normally) ends
+       * up needing a bottom-left fill convention, which requires
+       * slightly different rounding.
+       */
+      int adj = (setup->pixel_offset != 0) ? 1 : 0;
+
+      bbox.x0 = (MIN3(info.x[0], info.x[1], info.x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.x1 = (MAX3(info.x[0], info.x[1], info.x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.y0 = (MIN3(info.y[0], info.y[1], info.y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.y1 = (MAX3(info.y[0], info.y[1], info.y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+
+      /* Inclusive coordinates:
+       */
+      bbox.x1--;
+      bbox.y1--;
+   }
+
+   if (bbox.x1 < bbox.x0 ||
+       bbox.y1 < bbox.y0) {
+      if (0) debug_printf("empty bounding box\n");
+      LP_COUNT(nr_culled_tris);
+      return;
+   }
+
+   if (!u_rect_test_intersection(&setup->draw_region, &bbox)) {
+      if (0) debug_printf("offscreen\n");
+      LP_COUNT(nr_culled_tris);
+      return;
+   }
+
+   u_rect_find_intersection(&setup->draw_region, &bbox);
 
    tri = alloc_triangle(scene,
                         setup->fs.nr_inputs,
@@ -483,14 +528,6 @@ do_triangle_ccw(struct lp_setup_context *setup,
    tri->v[2][1] = v3[0][1];
 #endif
 
-   /* x/y positions in fixed point */
-   info.x[0] = subpixel_snap(v1[0][0] - setup->pixel_offset);
-   info.x[1] = subpixel_snap(v2[0][0] - setup->pixel_offset);
-   info.x[2] = subpixel_snap(v3[0][0] - setup->pixel_offset);
-   info.y[0] = subpixel_snap(v1[0][1] - setup->pixel_offset);
-   info.y[1] = subpixel_snap(v2[0][1] - setup->pixel_offset);
-   info.y[2] = subpixel_snap(v3[0][1] - setup->pixel_offset);
-
    tri->plane[0].dcdy = info.x[0] - info.x[1];
    tri->plane[1].dcdy = info.x[1] - info.x[2];
    tri->plane[2].dcdy = info.x[2] - info.x[0];
@@ -514,40 +551,6 @@ do_triangle_ccw(struct lp_setup_context *setup,
       return;
    }
 
-   /* Bounding rectangle (in pixels) */
-   {
-      /* Yes this is necessary to accurately calculate bounding boxes
-       * with the two fill-conventions we support.  GL (normally) ends
-       * up needing a bottom-left fill convention, which requires
-       * slightly different rounding.
-       */
-      int adj = (setup->pixel_offset != 0) ? 1 : 0;
-
-      minx = (MIN3(info.x[0], info.x[1], info.x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      maxx = (MAX3(info.x[0], info.x[1], info.x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      miny = (MIN3(info.y[0], info.y[1], info.y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
-      maxy = (MAX3(info.y[0], info.y[1], info.y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
-   }
-
-   if (setup->scissor_test) {
-      minx = MAX2(minx, setup->scissor.current.minx);
-      maxx = MIN2(maxx, setup->scissor.current.maxx);
-      miny = MAX2(miny, setup->scissor.current.miny);
-      maxy = MIN2(maxy, setup->scissor.current.maxy);
-   }
-   else {
-      minx = MAX2(minx, 0);
-      miny = MAX2(miny, 0);
-      maxx = MIN2(maxx, scene->fb.width);
-      maxy = MIN2(maxy, scene->fb.height);
-   }
-
-
-   if (miny >= maxy || minx >= maxx) {
-      lp_scene_putback_data( scene, tri_bytes );
-      LP_COUNT(nr_culled_tris);
-      return;
-   }
 
    /* 
     */
@@ -648,25 +651,25 @@ do_triangle_ccw(struct lp_setup_context *setup,
    if (nr_planes == 7) {
       tri->plane[3].dcdx = -1;
       tri->plane[3].dcdy = 0;
-      tri->plane[3].c = 1-minx;
+      tri->plane[3].c = 1-bbox.x0;
       tri->plane[3].ei = 0;
       tri->plane[3].eo = 1;
 
       tri->plane[4].dcdx = 1;
       tri->plane[4].dcdy = 0;
-      tri->plane[4].c = maxx;
+      tri->plane[4].c = bbox.x1+1;
       tri->plane[4].ei = -1;
       tri->plane[4].eo = 0;
 
       tri->plane[5].dcdx = 0;
       tri->plane[5].dcdy = 1;
-      tri->plane[5].c = 1-miny;
+      tri->plane[5].c = 1-bbox.y0;
       tri->plane[5].ei = 0;
       tri->plane[5].eo = 1;
 
       tri->plane[6].dcdx = 0;
       tri->plane[6].dcdy = -1;
-      tri->plane[6].c = maxy;
+      tri->plane[6].c = bbox.y1+1;
       tri->plane[6].ei = -1;
       tri->plane[6].eo = 0;
    }
@@ -680,10 +683,10 @@ do_triangle_ccw(struct lp_setup_context *setup,
    /* Convert to tile coordinates, and inclusive ranges:
     */
    if (nr_planes == 3) {
-      int ix0 = minx / 16;
-      int iy0 = miny / 16;
-      int ix1 = (maxx-1) / 16;
-      int iy1 = (maxy-1) / 16;
+      int ix0 = bbox.x0 / 16;
+      int iy0 = bbox.y0 / 16;
+      int ix1 = bbox.x1 / 16;
+      int iy1 = bbox.y1 / 16;
       
       if (iy0 == iy1 && ix0 == ix1)
       {
@@ -699,10 +702,10 @@ do_triangle_ccw(struct lp_setup_context *setup,
       }
    }
 
-   ix0 = minx / TILE_SIZE;
-   iy0 = miny / TILE_SIZE;
-   ix1 = (maxx-1) / TILE_SIZE;
-   iy1 = (maxy-1) / TILE_SIZE;
+   ix0 = bbox.x0 / TILE_SIZE;
+   iy0 = bbox.y0 / TILE_SIZE;
+   ix1 = bbox.x1 / TILE_SIZE;
+   iy1 = bbox.y1 / TILE_SIZE;
 
    /*
     * Clamp to framebuffer size
-- 
cgit v1.2.3


From 14ac294e1a67577d3f2b63e77272ec472a93c224 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Wed, 25 Aug 2010 09:55:07 -0700
Subject: llvmpipe: Remove unnecessary header.

---
 src/gallium/drivers/llvmpipe/lp_query.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_query.c b/src/gallium/drivers/llvmpipe/lp_query.c
index 540eea7fd1..67fd797af2 100644
--- a/src/gallium/drivers/llvmpipe/lp_query.c
+++ b/src/gallium/drivers/llvmpipe/lp_query.c
@@ -37,7 +37,6 @@
 #include "lp_flush.h"
 #include "lp_fence.h"
 #include "lp_query.h"
-#include "lp_rast.h"
 #include "lp_state.h"
 
 
-- 
cgit v1.2.3


From d4bfd8a24a4c2b246b55888d4983ddcf665b6976 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Wed, 25 Aug 2010 18:01:51 +0100
Subject: llvmpipe: fix bad patch application

---
 src/gallium/drivers/llvmpipe/lp_setup.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c
index 0c6d2de193..9aa6c4bf38 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup.c
@@ -815,6 +815,10 @@ lp_setup_update_state( struct lp_setup_context *setup )
          for (i = 0; i < Elements(setup->fs.current_tex); i++) {
             if (setup->fs.current_tex[i])
                lp_scene_add_resource_reference(scene, setup->fs.current_tex[i]);
+         }
+      }
+   }
+
    if (setup->dirty & LP_SETUP_NEW_SCISSOR) {
       setup->draw_region = setup->framebuffer;
       if (setup->scissor_test) {
@@ -823,11 +827,6 @@ lp_setup_update_state( struct lp_setup_context *setup )
       }
    }
                                       
-
-         }
-      }
-   }
-
    setup->dirty = 0;
 
    assert(setup->fs.stored);
-- 
cgit v1.2.3


From dc27515780d5e1b3a7b3f9ab7119d3e35b22294c Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Wed, 25 Aug 2010 20:02:24 +0200
Subject: r300g: fix potentially uninitialized variables in create_rs_state

It had no impact on correctness, though.

Reported by Vinson Lee.
---
 src/gallium/drivers/r300/r300_state.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 5c225e24f9..2240011368 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -940,9 +940,9 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
     uint32_t stuffing_enable;       /* R300_GB_ENABLE: 0x4008 */
 
     /* Point sprites texture coordinates, 0: lower left, 1: upper right */
-    float point_texcoord_left;      /* R300_GA_POINT_S0: 0x4200 */
+    float point_texcoord_left = 0;  /* R300_GA_POINT_S0: 0x4200 */
     float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */
-    float point_texcoord_right;     /* R300_GA_POINT_S1: 0x4208 */
+    float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */
     float point_texcoord_top = 0;   /* R300_GA_POINT_T1: 0x420c */
     CB_LOCALS;
 
@@ -1064,9 +1064,6 @@ static void* r300_create_rs_state(struct pipe_context* pipe,
                     R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (i*2));
         }
 
-        point_texcoord_left = 0.0f;
-        point_texcoord_right = 1.0f;
-
         switch (state->sprite_coord_mode) {
             case PIPE_SPRITE_COORD_UPPER_LEFT:
                 point_texcoord_top = 0.0f;
-- 
cgit v1.2.3


From 721954c334787bbddd8726348a4c95465f89677b Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Wed, 25 Aug 2010 11:22:55 -0700
Subject: nvfx: Set pointer to NULL after free.

Guard against potential use after free.
---
 src/gallium/drivers/nvfx/nvfx_fragprog.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_fragprog.c b/src/gallium/drivers/nvfx/nvfx_fragprog.c
index 7f6b3f6599..275672a31f 100644
--- a/src/gallium/drivers/nvfx/nvfx_fragprog.c
+++ b/src/gallium/drivers/nvfx/nvfx_fragprog.c
@@ -996,8 +996,10 @@ nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
 	return TRUE;
 
 out_err:
-	if (fpc->r_temp)
+	if (fpc->r_temp) {
 		FREE(fpc->r_temp);
+		fpc->r_temp = NULL;
+	}
 	tgsi_parse_free(&p);
 	return FALSE;
 }
-- 
cgit v1.2.3


From bd25e23bf3740f59ce8859848c715daeb9e9821f Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Tue, 24 Aug 2010 17:46:31 -0400
Subject: r600g: simplify states

Directly build PM4 packet, avoid using malloc (no states are
bigger than 128 dwords), remove unecessary informations,
remove pm4 building in favor of prebuild pm4 packet.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c       |   61 +-
 src/gallium/drivers/r600/r600_context.c    |    9 +-
 src/gallium/drivers/r600/r600_draw.c       |   46 +-
 src/gallium/drivers/r600/r600_query.c      |    6 +-
 src/gallium/drivers/r600/r600_shader.c     |    7 +-
 src/gallium/drivers/r600/r600_state.c      |   78 +-
 src/gallium/drivers/r600/r600_texture.c    |   18 +-
 src/gallium/drivers/r600/radeon.h          |  669 +--
 src/gallium/winsys/r600/drm/r600_state.c   | 8091 ++++++++++++++++++++++++++--
 src/gallium/winsys/r600/drm/r600_states.h  |  562 --
 src/gallium/winsys/r600/drm/radeon.c       |   44 -
 src/gallium/winsys/r600/drm/radeon_ctx.c   |  313 +-
 src/gallium/winsys/r600/drm/radeon_draw.c  |    3 +-
 src/gallium/winsys/r600/drm/radeon_priv.h  |   34 +-
 src/gallium/winsys/r600/drm/radeon_state.c |   56 +-
 15 files changed, 8277 insertions(+), 1720 deletions(-)
 delete mode 100644 src/gallium/winsys/r600/drm/r600_states.h

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 72175fbbd5..d3b722c82f 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 				      unsigned srcx, unsigned srcy, unsigned srcz,
 				      unsigned width, unsigned height)
 {
-	util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
+	util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
 				  src, subsrc, srcx, srcy, srcz, width, height);
 }
 
@@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	memcpy(bo->data, vbo, 128);
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
+	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return -ENOMEM;
@@ -199,33 +199,35 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
 	 */
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
 	rstate->bo[0] = bo;
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
+	rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return -ENOMEM;
 	}
 	bstates->vs_resource0 = rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
+	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1);
 	if (rstate == NULL) {
 		return -ENOMEM;
 	}
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
-	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -303,7 +305,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
+	rstate = radeon_state(rscreen->rw, R600_VS_SHADER);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return NULL;
@@ -321,6 +323,8 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	rstate->nbo = 2;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
+	rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
 
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -374,7 +378,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
+	rstate = radeon_state(rscreen->rw, R600_PS_SHADER);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return NULL;
@@ -391,6 +395,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	rstate->bo[0] = bo;
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
 
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -403,7 +408,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
+	rstate = radeon_state(rscreen->rw, R600_VGT);
 	if (rstate == NULL)
 		return NULL;
 
@@ -425,7 +430,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	rstate = radeon_state(rscreen->rw, R600_DRAW);
 	if (rstate == NULL)
 		return NULL;
 
@@ -448,7 +453,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
+	rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id);
 	if (rstate == NULL)
 		return NULL;
 
@@ -471,7 +476,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
+	rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
 	if (rstate == NULL)
 		return NULL;
 
@@ -500,7 +505,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	rstate = radeon_state(rscreen->rw, R600_DSA);
 	if (rstate == NULL)
 		return NULL;
 
@@ -524,7 +529,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
+	rstate = radeon_state(rscreen->rw, R600_BLEND);
 	if (rstate == NULL)
 		return NULL;
 
@@ -543,7 +548,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
 	if (rstate == NULL)
 		return NULL;
 
@@ -786,10 +791,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	r600_queries_suspend(ctx);
 
 	/* schedule draw*/
-	r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+	r = radeon_ctx_set_draw(rctx->ctx, draw);
 	if (r == -EBUSY) {
 		r600_flush(ctx, 0, NULL);
-		r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+		r = radeon_ctx_set_draw(rctx->ctx, draw);
 	}
 	if (r) {
 		goto out;
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 9af28356c5..790a85110b 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -53,12 +53,10 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 
 	/* suspend queries */
 	r600_queries_suspend(ctx);
-	if (radeon_ctx_pm4(rctx->ctx))
-		goto out;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
-	if (!rctx->ctx->cpm4)
+	if (!rctx->ctx->id)
 		goto out;
 	sprintf(dname, "gallium-%08d.bof", dc);
 	if (dc < 2) {
@@ -73,8 +71,7 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	}
 	dc++;
 out:
-	rctx->ctx = radeon_ctx_decref(rctx->ctx);
-	rctx->ctx = radeon_ctx(rscreen->rw);
+	radeon_ctx_clear(rctx->ctx);
 	/* resume queries */
 	r600_queries_resume(ctx);
 }
@@ -218,7 +215,7 @@ static void r600_init_config(struct r600_context *rctx)
 		num_es_stack_entries = 0;
 		break;
 	}
-	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
+	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG);
 
 	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 1eb868c4c7..a1a392ad2b 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -101,19 +101,21 @@ static int r600_draw_common(struct r600_draw *draw)
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
+		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i);
 		if (vs_resource == NULL)
 			return -ENOMEM;
 		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		vs_resource->nbo = 1;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
+		vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
+		vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
+		vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset;
+		vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset;
+		vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 								S_038008_DATA_FORMAT(format);
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
+		vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
+		vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
+		vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
+		vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
 		vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
 		vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
 		r = radeon_draw_set_new(rctx->draw, vs_resource);
@@ -121,22 +123,29 @@ static int r600_draw_common(struct r600_draw *draw)
 			return r;
 	}
 	/* FIXME start need to change winsys */
-	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
-	if (draw->draw == NULL)
-		return -ENOMEM;
-	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	if (draw->index_buffer) {
+		draw->draw = radeon_state(rscreen->rw, R600_DRAW);
+		if (draw->draw == NULL)
+			return -ENOMEM;
+		draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+		draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 		rbuffer = (struct r600_resource*)draw->index_buffer;
 		draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
 		draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
 		draw->draw->nbo = 1;
+		draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID;
+	} else {
+		draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO);
+		if (draw->draw == NULL)
+			return -ENOMEM;
+		draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count;
+		draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	}
 	r = radeon_draw_set_new(rctx->draw, draw->draw);
 	if (r)
 		return r;
-	draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
+	draw->vgt = radeon_state(rscreen->rw, R600_VGT);
 	if (draw->vgt == NULL)
 		return -ENOMEM;
 	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
@@ -145,23 +154,18 @@ static int r600_draw_common(struct r600_draw *draw)
 	draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
 	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
 	draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
 	draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
 	r = radeon_draw_set_new(rctx->draw, draw->vgt);
 	if (r)
 		return r;
 	/* FIXME */
-	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+	r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
 	if (r == -EBUSY) {
 		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+		r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
 	}
 	if (r)
 		return r;
-	rctx->draw = radeon_draw_duplicate(rctx->draw);
 	return 0;
 }
 
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 5929606cd2..8b4fe8999f 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -36,10 +36,11 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
+	rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
+	rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -55,10 +56,11 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
+	rstate = radeon_state(rscreen->rw, R600_QUERY_END);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
+	rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index b2d1a1bf01..f0b7df5a6f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -132,7 +132,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	unsigned i, tmp;
 
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
+	state = radeon_state(rscreen->rw, R600_VS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < 10; i++) {
@@ -151,6 +151,8 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	rpshader->rstate->nbo = 2;
 	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
+	state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
 	return radeon_state_pm4(state);
 }
 
@@ -165,7 +167,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 
 	rasterizer = &rctx->rasterizer->state.rasterizer;
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
+	state = radeon_state(rscreen->rw, R600_PS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < rshader->ninput; i++) {
@@ -204,6 +206,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
 	rpshader->rstate->nbo = 1;
 	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
 	return radeon_state_pm4(state);
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b5e5346163..e75575da79 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -283,19 +283,17 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, i, type, id;
+	unsigned nconstant = 0, i, id;
 	struct radeon_state *rstate;
 	struct pipe_transfer *transfer;
 	u32 *ptr;
 
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
-		id = R600_VS_CONSTANT;
-		type = R600_VS_CONSTANT_TYPE;
+		id = R600_VS_CONSTANT0;
 		break;
 	case PIPE_SHADER_FRAGMENT:
-		id = R600_PS_CONSTANT;
-		type = R600_PS_CONSTANT_TYPE;
+		id = R600_PS_CONSTANT0;
 		break;
 	default:
 		R600_ERR("unsupported %d\n", shader);
@@ -307,7 +305,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		if (ptr == NULL)
 			return;
 		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state(rscreen->rw, type, id + i);
+			rstate = radeon_state(rscreen->rw, id + i);
 			if (rstate == NULL)
 				return;
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
@@ -622,7 +620,7 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
 
-	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
+	rstate = radeon_state(rscreen->rw, R600_BLEND);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
@@ -681,14 +679,14 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
 	struct radeon_state *rstate;
 	const struct pipe_clip_state *state = &rctx->clip->state.clip;
 
-	rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
+	rstate = radeon_state(rscreen->rw, R600_UCP0 + clip);
 	if (rstate == NULL)
 		return NULL;
 
-	rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
-	rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
-	rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
-	rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
+	rstate->states[R600_UCP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
+	rstate->states[R600_UCP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
+	rstate->states[R600_UCP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
+	rstate->states[R600_UCP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
 
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -711,7 +709,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
+	rstate = radeon_state(rscreen->rw, R600_CB0 + cb);
 	if (rstate == NULL)
 		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
@@ -722,6 +720,9 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+	rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
+	rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
+	rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
 	rstate->nbo = 3;
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
@@ -740,14 +741,14 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 		S_0280A0_SOURCE_FORMAT(1) |
 		S_0280A0_NUMBER_TYPE(ntype);
 
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+	rstate->states[R600_CB__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
+	rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
+	rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
-	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
+	rstate->states[R600_CB__CB_COLOR0_VIEW] = 0x00000000;
+	rstate->states[R600_CB__CB_COLOR0_FRAG] = 0x00000000;
+	rstate->states[R600_CB__CB_COLOR0_TILE] = 0x00000000;
+	rstate->states[R600_CB__CB_COLOR0_MASK] = 0x00000000;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
@@ -768,7 +769,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	if (state->zsbuf == NULL)
 		return NULL;
 
-	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	rstate = radeon_state(rscreen->rw, R600_DB);
 	if (rstate == NULL)
 		return NULL;
 
@@ -782,6 +783,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
 	level = state->zsbuf->level;
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
@@ -844,7 +846,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		prov_vtx = 0;
 
 	rctx->flat_shade = state->flatshade;
-	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
+	rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
@@ -925,7 +927,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	}
 	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	rstate = radeon_state(rscreen->rw, R600_SCISSOR);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
@@ -960,7 +962,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
@@ -993,7 +995,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	if (rctx->ps_shader == NULL) {
 		return NULL;
 	}
-	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	rstate = radeon_state(rscreen->rw, R600_DSA);
 	if (rstate == NULL)
 		return NULL;
 
@@ -1145,7 +1147,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
+	rstate = radeon_state(rscreen->rw, id);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
@@ -1246,7 +1248,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 		R600_ERR("unknow format %d\n", view->texture->format);
 		return NULL;
 	}
-	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
+	rstate = radeon_state(rscreen->rw, id);
 	if (rstate == NULL) {
 		return NULL;
 	}
@@ -1268,34 +1270,36 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
+	rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
+	rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
 
 	pitch = (tmp->pitch[0] / tmp->bpt);
 	pitch = (pitch + 0x7) & ~0x7;
 	
 	/* FIXME properly handle first level != 0 */
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
+	rstate->states[R600_RESOURCE__RESOURCE_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
 			S_038000_TILE_MODE(array_mode) |
 			S_038000_TILE_TYPE(tile_type) |
 			S_038000_PITCH((pitch / 8) - 1) |
 			S_038000_TEX_WIDTH(view->texture->width0 - 1);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
+	rstate->states[R600_RESOURCE__RESOURCE_WORD1] =
 			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
 			S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
 			S_038004_DATA_FORMAT(format);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
+	rstate->states[R600_RESOURCE__RESOURCE_WORD2] = tmp->offset[0] >> 8;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD3] = tmp->offset[1] >> 8;
+	rstate->states[R600_RESOURCE__RESOURCE_WORD4] =
 		        word4 | 
 			S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
 			S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
 			S_038010_REQUEST_SIZE(1) |
 			S_038010_BASE_LEVEL(view->first_level);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
+	rstate->states[R600_RESOURCE__RESOURCE_WORD5] =
 			S_038014_LAST_LEVEL(view->last_level) |
 			S_038014_BASE_ARRAY(0) |
 			S_038014_LAST_ARRAY(0);
-	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
+	rstate->states[R600_RESOURCE__RESOURCE_WORD6] =
 			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -1342,7 +1346,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
-	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1419,7 +1423,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 		if (rctx->ps_sampler[i]) {
 			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
 							&rctx->ps_sampler[i]->state.sampler,
-							R600_PS_SAMPLER + i);
+							R600_PS_SAMPLER0 + i);
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
@@ -1427,7 +1431,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 		if (rctx->ps_sampler_view[i]) {
 			rctx->hw_states.ps_resource[i] = r600_resource(ctx,
 							&rctx->ps_sampler_view[i]->state.sampler_view,
-							R600_PS_RESOURCE + i);
+							R600_PS_RESOURCE0 + i);
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index fb84ed9cfe..9dc0208eb1 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -663,7 +663,7 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	rstate = radeon_state(rscreen->rw, R600_SCISSOR);
 	if (rstate == NULL)
 		return NULL;
 
@@ -707,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
+	rstate = radeon_state(rscreen->rw, R600_CB0);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -742,13 +742,16 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 		rstate->nbo = 3;
 		color_info = S_0280A0_SOURCE_FORMAT(1);
 	}
+	rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
+	rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
+	rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
 	color_info |= S_0280A0_FORMAT(format) |
 		S_0280A0_COMP_SWAP(swap) |
 		S_0280A0_BLEND_CLAMP(1) |
 		S_0280A0_NUMBER_TYPE(ntype);
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+	rstate->states[R600_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
+	rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
+	rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
 
 	if (radeon_state_pm4(rstate)) {
@@ -766,7 +769,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	struct r600_resource *rbuffer;
 	unsigned pitch, slice, format;
 
-	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	rstate = radeon_state(rscreen->rw, R600_DB);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -784,6 +787,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
 	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
 						S_028000_SLICE_TILE_MAX(slice);
+	rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 1;
@@ -815,7 +819,7 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
 	if (rstate == NULL)
 		return NULL;
 
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index b2cc74f696..777fe3e792 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -104,26 +104,18 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
 struct radeon_state {
 	struct radeon			*radeon;
 	unsigned			refcount;
-	unsigned			type;
 	unsigned			id;
-	unsigned			nstates;
-	u32				*states;
-	unsigned			npm4;
 	unsigned			cpm4;
+	u32				states[128];
 	u32				pm4_crc;
-	u32				*pm4;
-	u32				nimmd;
-	u32				*immd;
 	unsigned			nbo;
 	struct radeon_bo		*bo[4];
-	unsigned			nreloc;
-	unsigned			reloc_pm4_id[8];
-	unsigned			reloc_bo_id[8];
+	unsigned			reloc_pm4_id[4];
 	u32				placement[8];
 	unsigned			bo_dirty[4];
 };
 
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
+struct radeon_state *radeon_state(struct radeon *radeon, u32 id);
 struct radeon_state *radeon_state_incref(struct radeon_state *state);
 struct radeon_state *radeon_state_decref(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
@@ -147,16 +139,6 @@ int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
 int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
 int radeon_draw_check(struct radeon_draw *draw);
 
-struct radeon_ctx *radeon_ctx(struct radeon *radeon);
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_pm4(struct radeon_ctx *ctx);
-int radeon_ctx_submit(struct radeon_ctx *ctx);
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
-
 /*
  * radeon context functions
  */
@@ -169,261 +151,216 @@ struct radeon_cs_reloc {
 };
 #pragma pack()
 
+struct radeon_ctx_bo {
+	struct radeon_bo		*bo;
+	u32				bo_flushed;
+	unsigned			state_id;
+};
+
 struct radeon_ctx {
 	int				refcount;
 	struct radeon			*radeon;
 	u32				*pm4;
-	u32				cpm4;
-	u32				draw_cpm4;
+	int				npm4;
 	unsigned			id;
-	unsigned			next_id;
 	unsigned			nreloc;
+	unsigned			max_reloc;
 	struct radeon_cs_reloc		*reloc;
 	unsigned			nbo;
-	struct radeon_bo		**bo;
-	unsigned			ndraw;
-	struct radeon_draw		*cdraw;
-	struct radeon_draw		**draw;
-	unsigned			nstate;
-	struct radeon_state		**state;
+	struct radeon_ctx_bo		*bo;
+	unsigned			max_bo;
+	u32				*state_crc32;
 };
 
+struct radeon_ctx *radeon_ctx(struct radeon *radeon);
+struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
+struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
+void radeon_ctx_clear(struct radeon_ctx *ctx);
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
+int radeon_ctx_pm4(struct radeon_ctx *ctx);
+int radeon_ctx_submit(struct radeon_ctx *ctx);
+void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
+
+
 /*
  * R600/R700
  */
-
-#define R600_NSTATE				1288
-#define R600_NTYPE				35
-
-#define R600_CONFIG				0
-#define R600_CONFIG_TYPE				0
-#define R600_CB_CNTL				1
-#define R600_CB_CNTL_TYPE				1
-#define R600_RASTERIZER				2
-#define R600_RASTERIZER_TYPE				2
-#define R600_VIEWPORT				3
-#define R600_VIEWPORT_TYPE				3
-#define R600_SCISSOR				4
-#define R600_SCISSOR_TYPE				4
-#define R600_BLEND				5
-#define R600_BLEND_TYPE				5
-#define R600_DSA				6
-#define R600_DSA_TYPE				6
-#define R600_VS_SHADER				7
-#define R600_VS_SHADER_TYPE				7
-#define R600_PS_SHADER				8
-#define R600_PS_SHADER_TYPE				8
-#define R600_PS_CONSTANT				9
-#define R600_PS_CONSTANT_TYPE				9
-#define R600_VS_CONSTANT				265
-#define R600_VS_CONSTANT_TYPE				10
-#define R600_PS_RESOURCE				521
-#define R600_PS_RESOURCE_TYPE				11
-#define R600_VS_RESOURCE				681
-#define R600_VS_RESOURCE_TYPE				12
-#define R600_FS_RESOURCE				841
-#define R600_FS_RESOURCE_TYPE				13
-#define R600_GS_RESOURCE				1001
-#define R600_GS_RESOURCE_TYPE				14
-#define R600_PS_SAMPLER				1161
-#define R600_PS_SAMPLER_TYPE				15
-#define R600_VS_SAMPLER				1179
-#define R600_VS_SAMPLER_TYPE				16
-#define R600_GS_SAMPLER				1197
-#define R600_GS_SAMPLER_TYPE				17
-#define R600_PS_SAMPLER_BORDER				1215
-#define R600_PS_SAMPLER_BORDER_TYPE				18
-#define R600_VS_SAMPLER_BORDER				1233
-#define R600_VS_SAMPLER_BORDER_TYPE				19
-#define R600_GS_SAMPLER_BORDER				1251
-#define R600_GS_SAMPLER_BORDER_TYPE				20
-#define R600_CB0				1269
-#define R600_CB0_TYPE				21
-#define R600_CB1				1270
-#define R600_CB1_TYPE				22
-#define R600_CB2				1271
-#define R600_CB2_TYPE				23
-#define R600_CB3				1272
-#define R600_CB3_TYPE				24
-#define R600_CB4				1273
-#define R600_CB4_TYPE				25
-#define R600_CB5				1274
-#define R600_CB5_TYPE				26
-#define R600_CB6				1275
-#define R600_CB6_TYPE				27
-#define R600_CB7				1276
-#define R600_CB7_TYPE				28
-#define R600_QUERY_BEGIN			1277
-#define R600_QUERY_BEGIN_TYPE			29
-#define R600_QUERY_END				1278
-#define R600_QUERY_END_TYPE			30
-#define R600_DB					1279
-#define R600_DB_TYPE				31
-#define R600_CLIP				1280
-#define R600_CLIP_TYPE				32
-#define R600_VGT				1286
-#define R600_VGT_TYPE				33
-#define R600_DRAW				1287
-#define R600_DRAW_TYPE				34
+#define R600_CONFIG		0
+#define R600_CB_CNTL		1
+#define R600_RASTERIZER		2
+#define R600_VIEWPORT		3
+#define R600_SCISSOR		4
+#define R600_BLEND		5
+#define R600_DSA		6
+#define R600_VGT		7
+#define R600_QUERY_BEGIN	8
+#define R600_QUERY_END		9
+#define R600_VS_SHADER		10
+#define R600_PS_SHADER		11
+#define R600_DB			12
+#define R600_CB0		13
+#define R600_UCP0		21
+#define R600_PS_RESOURCE0	27
+#define R600_VS_RESOURCE0	187
+#define R600_FS_RESOURCE0	347
+#define R600_GS_RESOURCE0	363
+#define R600_PS_CONSTANT0	523
+#define R600_VS_CONSTANT0	779
+#define R600_PS_SAMPLER0	1035
+#define R600_VS_SAMPLER0	1053
+#define R600_GS_SAMPLER0	1071
+#define R600_PS_SAMPLER_BORDER0	1089
+#define R600_VS_SAMPLER_BORDER0	1107
+#define R600_GS_SAMPLER_BORDER0	1125
+#define R600_DRAW_AUTO		1143
+#define R600_DRAW		1144
+#define R600_NSTATE		1145
 
 /* R600_CONFIG */
-#define R600_CONFIG__SQ_CONFIG			0
+#define R600_CONFIG__SQ_CONFIG					0
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			1
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2			2
 #define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT			3
 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1			4
 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2			5
-#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ			6
-#define R600_CONFIG__TA_CNTL_AUX			7
-#define R600_CONFIG__VC_ENHANCE			8
-#define R600_CONFIG__DB_DEBUG			9
-#define R600_CONFIG__DB_WATERMARKS			10
-#define R600_CONFIG__SX_MISC			11
-#define R600_CONFIG__SPI_THREAD_GROUPING			12
-#define R600_CONFIG__CB_SHADER_CONTROL			13
-#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE			14
-#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE			15
-#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE			16
-#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE			17
-#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE			18
-#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE			19
-#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE			20
-#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE			21
-#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE			22
-#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL			23
-#define R600_CONFIG__VGT_HOS_CNTL			24
-#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL			25
-#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL			26
-#define R600_CONFIG__VGT_HOS_REUSE_DEPTH			27
-#define R600_CONFIG__VGT_GROUP_PRIM_TYPE			28
-#define R600_CONFIG__VGT_GROUP_FIRST_DECR			29
-#define R600_CONFIG__VGT_GROUP_DECR			30
-#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL			31
-#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL			32
-#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL			33
-#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL			34
-#define R600_CONFIG__VGT_GS_MODE			35
-#define R600_CONFIG__PA_SC_MODE_CNTL			36
-#define R600_CONFIG__VGT_STRMOUT_EN			37
-#define R600_CONFIG__VGT_REUSE_OFF			38
-#define R600_CONFIG__VGT_VTX_CNT_EN			39
-#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN			40
-#define R600_CONFIG_SIZE				41
-#define R600_CONFIG_PM4				128
+#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ		8
+#define R600_CONFIG__TA_CNTL_AUX				11
+#define R600_CONFIG__VC_ENHANCE					14
+#define R600_CONFIG__DB_DEBUG					17
+#define R600_CONFIG__DB_WATERMARKS				20
+#define R600_CONFIG__SX_MISC					23
+#define R600_CONFIG__SPI_THREAD_GROUPING			26
+#define R600_CONFIG__CB_SHADER_CONTROL				29
+#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE			32
+#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE			33
+#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE			34
+#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE			35
+#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE			36
+#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE			37
+#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE			38
+#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE			39
+#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE			40
+#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL			43
+#define R600_CONFIG__VGT_HOS_CNTL				44
+#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL			45
+#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL			46
+#define R600_CONFIG__VGT_HOS_REUSE_DEPTH			47
+#define R600_CONFIG__VGT_GROUP_PRIM_TYPE			48
+#define R600_CONFIG__VGT_GROUP_FIRST_DECR			49
+#define R600_CONFIG__VGT_GROUP_DECR				50
+#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL			51
+#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL			52
+#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL			53
+#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL			54
+#define R600_CONFIG__VGT_GS_MODE				55
+#define R600_CONFIG__PA_SC_MODE_CNTL				58
+#define R600_CONFIG__VGT_STRMOUT_EN				61
+#define R600_CONFIG__VGT_REUSE_OFF				62
+#define R600_CONFIG__VGT_VTX_CNT_EN				63
+#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN			66
 /* R600_CB_CNTL */
-#define R600_CB_CNTL__CB_CLEAR_RED			0
-#define R600_CB_CNTL__CB_CLEAR_GREEN			1
-#define R600_CB_CNTL__CB_CLEAR_BLUE			2
-#define R600_CB_CNTL__CB_CLEAR_ALPHA			3
-#define R600_CB_CNTL__CB_SHADER_MASK			4
-#define R600_CB_CNTL__CB_TARGET_MASK			5
-#define R600_CB_CNTL__CB_FOG_RED			6
-#define R600_CB_CNTL__CB_FOG_GREEN			7
-#define R600_CB_CNTL__CB_FOG_BLUE			8
-#define R600_CB_CNTL__CB_COLOR_CONTROL			9
-#define R600_CB_CNTL__PA_SC_AA_CONFIG			10
-#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX			11
-#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX			12
-#define R600_CB_CNTL__CB_CLRCMP_CONTROL			13
-#define R600_CB_CNTL__CB_CLRCMP_SRC			14
-#define R600_CB_CNTL__CB_CLRCMP_DST			15
-#define R600_CB_CNTL__CB_CLRCMP_MSK			16
-#define R600_CB_CNTL__PA_SC_AA_MASK			17
-#define R600_CB_CNTL_SIZE				18
-#define R600_CB_CNTL_PM4				128
+#define R600_CB_CNTL__CB_CLEAR_RED				0
+#define R600_CB_CNTL__CB_CLEAR_GREEN				1
+#define R600_CB_CNTL__CB_CLEAR_BLUE				2
+#define R600_CB_CNTL__CB_CLEAR_ALPHA				3
+#define R600_CB_CNTL__CB_SHADER_MASK				6
+#define R600_CB_CNTL__CB_TARGET_MASK				7
+#define R600_CB_CNTL__CB_FOG_RED				10
+#define R600_CB_CNTL__CB_FOG_GREEN				11
+#define R600_CB_CNTL__CB_FOG_BLUE				12
+#define R600_CB_CNTL__CB_COLOR_CONTROL				15
+#define R600_CB_CNTL__PA_SC_AA_CONFIG				18
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX			21
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX		22
+#define R600_CB_CNTL__CB_CLRCMP_CONTROL				25
+#define R600_CB_CNTL__CB_CLRCMP_SRC				26
+#define R600_CB_CNTL__CB_CLRCMP_DST				27
+#define R600_CB_CNTL__CB_CLRCMP_MSK				28
+#define R600_CB_CNTL__PA_SC_AA_MASK				31
 /* R600_RASTERIZER */
 #define R600_RASTERIZER__SPI_INTERP_CONTROL_0			0
-#define R600_RASTERIZER__PA_CL_CLIP_CNTL			1
-#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL			2
-#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL			3
-#define R600_RASTERIZER__PA_CL_NANINF_CNTL			4
-#define R600_RASTERIZER__PA_SU_POINT_SIZE			5
-#define R600_RASTERIZER__PA_SU_POINT_MINMAX			6
-#define R600_RASTERIZER__PA_SU_LINE_CNTL			7
-#define R600_RASTERIZER__PA_SC_LINE_STIPPLE			8
-#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL			9
-#define R600_RASTERIZER__PA_SC_LINE_CNTL			10
-#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ			11
-#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ			12
-#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ			13
-#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ			14
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL			15
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP			16
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE			17
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET			18
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE			19
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET			20
-#define R600_RASTERIZER_SIZE				21
-#define R600_RASTERIZER_PM4				128
+#define R600_RASTERIZER__PA_CL_CLIP_CNTL			3
+#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL			4
+#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL			7
+#define R600_RASTERIZER__PA_CL_NANINF_CNTL			8
+#define R600_RASTERIZER__PA_SU_POINT_SIZE			11
+#define R600_RASTERIZER__PA_SU_POINT_MINMAX			12
+#define R600_RASTERIZER__PA_SU_LINE_CNTL			13
+#define R600_RASTERIZER__PA_SC_LINE_STIPPLE			14
+#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL			17
+#define R600_RASTERIZER__PA_SC_LINE_CNTL			20
+#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ			23
+#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ			24
+#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ			25
+#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ			26
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL		29
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP		30
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE		31
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET		32
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE		33
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET		34
 /* R600_VIEWPORT */
 #define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0			0
 #define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0			1
-#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0			2
-#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0			3
-#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0			4
-#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0			5
-#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0			6
-#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0			7
-#define R600_VIEWPORT__PA_CL_VTE_CNTL			8
-#define R600_VIEWPORT_SIZE				9
-#define R600_VIEWPORT_PM4				128
+#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0			4
+#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0			7
+#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0			10
+#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0			13
+#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0			16
+#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0			19
+#define R600_VIEWPORT__PA_CL_VTE_CNTL				22
 /* R600_SCISSOR */
 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL			0
 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR			1
-#define R600_SCISSOR__PA_SC_WINDOW_OFFSET			2
-#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL			3
-#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR			4
-#define R600_SCISSOR__PA_SC_CLIPRECT_RULE			5
-#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL			6
-#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR			7
-#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL			8
-#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR			9
-#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL			10
-#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR			11
-#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL			12
-#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR			13
-#define R600_SCISSOR__PA_SC_EDGERULE			14
-#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL			15
-#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR			16
-#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL			17
-#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR			18
-#define R600_SCISSOR_SIZE				19
-#define R600_SCISSOR_PM4				128
+#define R600_SCISSOR__PA_SC_WINDOW_OFFSET			4
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL			5
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR			6
+#define R600_SCISSOR__PA_SC_CLIPRECT_RULE			7
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL			8
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR			9
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL			10
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR			11
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL			12
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR			13
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL			14
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR			15
+#define R600_SCISSOR__PA_SC_EDGERULE				16
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL			19
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR			20
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL			23
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR			24
 /* R600_BLEND */
-#define R600_BLEND__CB_BLEND_RED			0
-#define R600_BLEND__CB_BLEND_GREEN			1
-#define R600_BLEND__CB_BLEND_BLUE			2
-#define R600_BLEND__CB_BLEND_ALPHA			3
-#define R600_BLEND__CB_BLEND0_CONTROL			4
-#define R600_BLEND__CB_BLEND1_CONTROL			5
-#define R600_BLEND__CB_BLEND2_CONTROL			6
-#define R600_BLEND__CB_BLEND3_CONTROL			7
-#define R600_BLEND__CB_BLEND4_CONTROL			8
-#define R600_BLEND__CB_BLEND5_CONTROL			9
-#define R600_BLEND__CB_BLEND6_CONTROL			10
-#define R600_BLEND__CB_BLEND7_CONTROL			11
-#define R600_BLEND__CB_BLEND_CONTROL			12
-#define R600_BLEND_SIZE				13
-#define R600_BLEND_PM4				128
+#define R600_BLEND__CB_BLEND_RED				0
+#define R600_BLEND__CB_BLEND_GREEN				1
+#define R600_BLEND__CB_BLEND_BLUE				2
+#define R600_BLEND__CB_BLEND_ALPHA				3
+#define R600_BLEND__CB_BLEND0_CONTROL				6
+#define R600_BLEND__CB_BLEND1_CONTROL				7
+#define R600_BLEND__CB_BLEND2_CONTROL				8
+#define R600_BLEND__CB_BLEND3_CONTROL				9
+#define R600_BLEND__CB_BLEND4_CONTROL				10
+#define R600_BLEND__CB_BLEND5_CONTROL				11
+#define R600_BLEND__CB_BLEND6_CONTROL				12
+#define R600_BLEND__CB_BLEND7_CONTROL				13
+#define R600_BLEND__CB_BLEND_CONTROL				16
 /* R600_DSA */
-#define R600_DSA__DB_STENCIL_CLEAR			0
-#define R600_DSA__DB_DEPTH_CLEAR			1
-#define R600_DSA__SX_ALPHA_TEST_CONTROL			2
-#define R600_DSA__DB_STENCILREFMASK			3
-#define R600_DSA__DB_STENCILREFMASK_BF			4
-#define R600_DSA__SX_ALPHA_REF			5
-#define R600_DSA__SPI_FOG_FUNC_SCALE			6
-#define R600_DSA__SPI_FOG_FUNC_BIAS			7
-#define R600_DSA__SPI_FOG_CNTL			8
-#define R600_DSA__DB_DEPTH_CONTROL			9
-#define R600_DSA__DB_SHADER_CONTROL			10
-#define R600_DSA__DB_RENDER_CONTROL			11
-#define R600_DSA__DB_RENDER_OVERRIDE			12
-#define R600_DSA__DB_SRESULTS_COMPARE_STATE1			13
-#define R600_DSA__DB_PRELOAD_CONTROL			14
-#define R600_DSA__DB_ALPHA_TO_MASK			15
-#define R600_DSA_SIZE				16
-#define R600_DSA_PM4				128
+#define R600_DSA__DB_STENCIL_CLEAR				0
+#define R600_DSA__DB_DEPTH_CLEAR				1
+#define R600_DSA__SX_ALPHA_TEST_CONTROL				4
+#define R600_DSA__DB_STENCILREFMASK				7
+#define R600_DSA__DB_STENCILREFMASK_BF				8
+#define R600_DSA__SX_ALPHA_REF					9
+#define R600_DSA__SPI_FOG_FUNC_SCALE				12
+#define R600_DSA__SPI_FOG_FUNC_BIAS				13
+#define R600_DSA__SPI_FOG_CNTL					16
+#define R600_DSA__DB_DEPTH_CONTROL				19
+#define R600_DSA__DB_SHADER_CONTROL				22
+#define R600_DSA__DB_RENDER_CONTROL				25
+#define R600_DSA__DB_RENDER_OVERRIDE				26
+#define R600_DSA__DB_SRESULTS_COMPARE_STATE1			29
+#define R600_DSA__DB_PRELOAD_CONTROL				30
+#define R600_DSA__DB_ALPHA_TO_MASK				33
 /* R600_VS_SHADER */
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_0			0
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_1			1
@@ -457,25 +394,25 @@ struct radeon_ctx {
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_29			29
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_30			30
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_31			31
-#define R600_VS_SHADER__SPI_VS_OUT_ID_0			32
-#define R600_VS_SHADER__SPI_VS_OUT_ID_1			33
-#define R600_VS_SHADER__SPI_VS_OUT_ID_2			34
-#define R600_VS_SHADER__SPI_VS_OUT_ID_3			35
-#define R600_VS_SHADER__SPI_VS_OUT_ID_4			36
-#define R600_VS_SHADER__SPI_VS_OUT_ID_5			37
-#define R600_VS_SHADER__SPI_VS_OUT_ID_6			38
-#define R600_VS_SHADER__SPI_VS_OUT_ID_7			39
-#define R600_VS_SHADER__SPI_VS_OUT_ID_8			40
-#define R600_VS_SHADER__SPI_VS_OUT_ID_9			41
-#define R600_VS_SHADER__SPI_VS_OUT_CONFIG			42
-#define R600_VS_SHADER__SQ_PGM_START_VS			43
-#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS			44
-#define R600_VS_SHADER__SQ_PGM_START_FS			45
-#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS			46
-#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS			47
-#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS			48
-#define R600_VS_SHADER_SIZE				49
-#define R600_VS_SHADER_PM4				128
+#define R600_VS_SHADER__SPI_VS_OUT_ID_0				34
+#define R600_VS_SHADER__SPI_VS_OUT_ID_1				35
+#define R600_VS_SHADER__SPI_VS_OUT_ID_2				36
+#define R600_VS_SHADER__SPI_VS_OUT_ID_3				37
+#define R600_VS_SHADER__SPI_VS_OUT_ID_4				38
+#define R600_VS_SHADER__SPI_VS_OUT_ID_5				39
+#define R600_VS_SHADER__SPI_VS_OUT_ID_6				40
+#define R600_VS_SHADER__SPI_VS_OUT_ID_7				41
+#define R600_VS_SHADER__SPI_VS_OUT_ID_8				42
+#define R600_VS_SHADER__SPI_VS_OUT_ID_9				43
+#define R600_VS_SHADER__SPI_VS_OUT_CONFIG			46
+#define R600_VS_SHADER__SQ_PGM_START_VS				49
+#define R600_VS_SHADER__SQ_PGM_START_VS_BO_ID			51
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS			54
+#define R600_VS_SHADER__SQ_PGM_START_FS				57
+#define R600_VS_SHADER__SQ_PGM_START_FS_BO_ID			59
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS			62
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS			65
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS			68
 /* R600_PS_SHADER */
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0			0
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1			1
@@ -509,158 +446,104 @@ struct radeon_ctx {
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29			29
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30			30
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31			31
-#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0			32
-#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1			33
-#define R600_PS_SHADER__SPI_INPUT_Z			34
-#define R600_PS_SHADER__SQ_PGM_START_PS			35
-#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS			36
-#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS			37
-#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS			38
-#define R600_PS_SHADER_SIZE				39
-#define R600_PS_SHADER_PM4				128
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0			34
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1			35
+#define R600_PS_SHADER__SPI_INPUT_Z				38
+#define R600_PS_SHADER__SQ_PGM_START_PS				41
+#define R600_PS_SHADER__SQ_PGM_START_PS_BO_ID			43
+#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS			46
+#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS			47
+#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS			50
 /* R600_PS_CONSTANT */
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0			0
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0			1
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0			2
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0			3
-#define R600_PS_CONSTANT_SIZE				4
-#define R600_PS_CONSTANT_PM4				128
 /* R600_VS_CONSTANT */
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256			0
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256			1
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256			2
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256			3
-#define R600_VS_CONSTANT_SIZE				4
-#define R600_VS_CONSTANT_PM4				128
 /* R600_PS_RESOURCE */
-#define R600_PS_RESOURCE__RESOURCE0_WORD0			0
-#define R600_PS_RESOURCE__RESOURCE0_WORD1			1
-#define R600_PS_RESOURCE__RESOURCE0_WORD2			2
-#define R600_PS_RESOURCE__RESOURCE0_WORD3			3
-#define R600_PS_RESOURCE__RESOURCE0_WORD4			4
-#define R600_PS_RESOURCE__RESOURCE0_WORD5			5
-#define R600_PS_RESOURCE__RESOURCE0_WORD6			6
-#define R600_PS_RESOURCE_SIZE				7
-#define R600_PS_RESOURCE_PM4				128
-/* R600_VS_RESOURCE */
-#define R600_VS_RESOURCE__RESOURCE160_WORD0			0
-#define R600_VS_RESOURCE__RESOURCE160_WORD1			1
-#define R600_VS_RESOURCE__RESOURCE160_WORD2			2
-#define R600_VS_RESOURCE__RESOURCE160_WORD3			3
-#define R600_VS_RESOURCE__RESOURCE160_WORD4			4
-#define R600_VS_RESOURCE__RESOURCE160_WORD5			5
-#define R600_VS_RESOURCE__RESOURCE160_WORD6			6
-#define R600_VS_RESOURCE_SIZE				7
-#define R600_VS_RESOURCE_PM4				128
-/* R600_FS_RESOURCE */
-#define R600_FS_RESOURCE__RESOURCE320_WORD0			0
-#define R600_FS_RESOURCE__RESOURCE320_WORD1			1
-#define R600_FS_RESOURCE__RESOURCE320_WORD2			2
-#define R600_FS_RESOURCE__RESOURCE320_WORD3			3
-#define R600_FS_RESOURCE__RESOURCE320_WORD4			4
-#define R600_FS_RESOURCE__RESOURCE320_WORD5			5
-#define R600_FS_RESOURCE__RESOURCE320_WORD6			6
-#define R600_FS_RESOURCE_SIZE				7
-#define R600_FS_RESOURCE_PM4				128
-/* R600_GS_RESOURCE */
-#define R600_GS_RESOURCE__RESOURCE336_WORD0			0
-#define R600_GS_RESOURCE__RESOURCE336_WORD1			1
-#define R600_GS_RESOURCE__RESOURCE336_WORD2			2
-#define R600_GS_RESOURCE__RESOURCE336_WORD3			3
-#define R600_GS_RESOURCE__RESOURCE336_WORD4			4
-#define R600_GS_RESOURCE__RESOURCE336_WORD5			5
-#define R600_GS_RESOURCE__RESOURCE336_WORD6			6
-#define R600_GS_RESOURCE_SIZE				7
-#define R600_GS_RESOURCE_PM4				128
+#define R600_RESOURCE__RESOURCE_WORD0				0
+#define R600_RESOURCE__RESOURCE_WORD1				1
+#define R600_RESOURCE__RESOURCE_WORD2				2
+#define R600_RESOURCE__RESOURCE_WORD3				3
+#define R600_RESOURCE__RESOURCE_WORD4				4
+#define R600_RESOURCE__RESOURCE_WORD5				5
+#define R600_RESOURCE__RESOURCE_WORD6				6
+#define R600_RESOURCE__RESOURCE_BO0_ID				8
+#define R600_RESOURCE__RESOURCE_BO1_ID				10
 /* R600_PS_SAMPLER */
 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0			0
 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0			1
 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0			2
-#define R600_PS_SAMPLER_SIZE				3
-#define R600_PS_SAMPLER_PM4				128
 /* R600_VS_SAMPLER */
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18			0
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18			1
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18			2
-#define R600_VS_SAMPLER_SIZE				3
-#define R600_VS_SAMPLER_PM4				128
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18		0
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18		1
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18		2
 /* R600_GS_SAMPLER */
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36			0
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36			1
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36			2
-#define R600_GS_SAMPLER_SIZE				3
-#define R600_GS_SAMPLER_PM4				128
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36		0
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36		1
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36		2
 /* R600_PS_SAMPLER_BORDER */
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED			0
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN			1
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE			2
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA			3
-#define R600_PS_SAMPLER_BORDER_SIZE				4
-#define R600_PS_SAMPLER_BORDER_PM4				128
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED	0
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN	1
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE	2
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA	3
 /* R600_VS_SAMPLER_BORDER */
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED			0
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN			1
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE			2
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA			3
-#define R600_VS_SAMPLER_BORDER_SIZE				4
-#define R600_VS_SAMPLER_BORDER_PM4				128
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED	0
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN	1
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE	2
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA	3
 /* R600_GS_SAMPLER_BORDER */
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED			0
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN			1
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE			2
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA			3
-#define R600_GS_SAMPLER_BORDER_SIZE				4
-#define R600_GS_SAMPLER_BORDER_PM4				128
-/* R600_CB0 */
-#define R600_CB0__CB_COLOR0_BASE			0
-#define R600_CB0__CB_COLOR0_INFO			1
-#define R600_CB0__CB_COLOR0_SIZE			2
-#define R600_CB0__CB_COLOR0_VIEW			3
-#define R600_CB0__CB_COLOR0_FRAG			4
-#define R600_CB0__CB_COLOR0_TILE			5
-#define R600_CB0__CB_COLOR0_MASK			6
-#define R600_CB0_SIZE				7
-#define R600_CB0_PM4				128
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED	0
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN	1
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE	2
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA	3
+/* R600_CB */
+#define R600_CB__CB_COLOR0_BASE					0
+#define R600_CB__CB_COLOR0_BASE_BO_ID				2
+#define R600_CB__CB_COLOR0_INFO					5
+#define R600_CB__CB_COLOR0_SIZE					8
+#define R600_CB__CB_COLOR0_VIEW					11
+#define R600_CB__CB_COLOR0_FRAG					14
+#define R600_CB__CB_COLOR0_FRAG_BO_ID				16
+#define R600_CB__CB_COLOR0_TILE					19
+#define R600_CB__CB_COLOR0_TILE_BO_ID				21
+#define R600_CB__CB_COLOR0_MASK					24
 /* R600_DB */
-#define R600_DB__DB_DEPTH_BASE			0
-#define R600_DB__DB_DEPTH_SIZE			1
-#define R600_DB__DB_DEPTH_VIEW			2
-#define R600_DB__DB_DEPTH_INFO			3
-#define R600_DB__DB_HTILE_SURFACE			4
-#define R600_DB__DB_PREFETCH_LIMIT			5
-#define R600_DB_SIZE				6
-#define R600_DB_PM4				128
+#define R600_DB__DB_DEPTH_BASE					0
+#define R600_DB__DB_DEPTH_BASE_BO_ID				2
+#define R600_DB__DB_DEPTH_SIZE					5
+#define R600_DB__DB_DEPTH_VIEW					6
+#define R600_DB__DB_DEPTH_INFO					9
+#define R600_DB__DB_HTILE_SURFACE				12
+#define R600_DB__DB_PREFETCH_LIMIT				15
 /* R600_VGT */
-#define R600_VGT__VGT_PRIMITIVE_TYPE			0
-#define R600_VGT__VGT_MAX_VTX_INDX			1
-#define R600_VGT__VGT_MIN_VTX_INDX			2
-#define R600_VGT__VGT_INDX_OFFSET			3
-#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX			4
-#define R600_VGT__VGT_DMA_INDEX_TYPE			5
-#define R600_VGT__VGT_PRIMITIVEID_EN			6
-#define R600_VGT__VGT_DMA_NUM_INSTANCES			7
-#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN			8
-#define R600_VGT__VGT_INSTANCE_STEP_RATE_0			9
-#define R600_VGT__VGT_INSTANCE_STEP_RATE_1			10
-#define R600_VGT_SIZE				11
-#define R600_VGT_PM4				128
+#define R600_VGT__VGT_MAX_VTX_INDX				0
+#define R600_VGT__VGT_MIN_VTX_INDX				1
+#define R600_VGT__VGT_INDX_OFFSET				2
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX			3
+#define R600_VGT__VGT_PRIMITIVE_TYPE				6
+#define R600_VGT__VGT_DMA_INDEX_TYPE				8
+#define R600_VGT__VGT_DMA_NUM_INSTANCES				10
+/* R600_DRAW_AUTO */
+#define R600_DRAW_AUTO__VGT_NUM_INDICES				0
+#define R600_DRAW_AUTO__VGT_DRAW_INITIATOR			1
 /* R600_DRAW */
-#define R600_DRAW__VGT_NUM_INDICES			0
-#define R600_DRAW__VGT_DMA_BASE_HI			1
-#define R600_DRAW__VGT_DMA_BASE			2
-#define R600_DRAW__VGT_DRAW_INITIATOR			3
-#define R600_DRAW_SIZE				4
-#define R600_DRAW_PM4				128
-/* R600_CLIP */
-#define R600_CLIP__PA_CL_UCP_X_0  0
-#define R600_CLIP__PA_CL_UCP_Y_0  1
-#define R600_CLIP__PA_CL_UCP_Z_0  2
-#define R600_CLIP__PA_CL_UCP_W_0  3
-#define R600_CLIP_SIZE  4
-#define R600_CLIP_PM4 128
+#define R600_DRAW__VGT_DMA_BASE					0
+#define R600_DRAW__VGT_DMA_BASE_HI				1
+#define R600_DRAW__VGT_NUM_INDICES				2
+#define R600_DRAW__VGT_DRAW_INITIATOR				3
+#define R600_DRAW__INDICES_BO_ID				5
+/* R600_UCP */
+#define R600_UCP__PA_CL_UCP_X_0					0
+#define R600_UCP__PA_CL_UCP_Y_0					1
+#define R600_UCP__PA_CL_UCP_Z_0					2
+#define R600_UCP__PA_CL_UCP_W_0					3
 /* R600 QUERY BEGIN/END */
-#define R600_QUERY__OFFSET			0
-#define R600_QUERY_SIZE				1
-#define R600_QUERY_PM4				128
+#define R600_QUERY__OFFSET					0
+#define R600_QUERY__BO_ID					3
 
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 9b7c11bdc0..7941563215 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -30,377 +30,41 @@
 #include "radeon_priv.h"
 #include "r600d.h"
 
-static int r600_state_pm4_resource(struct radeon_state *state);
-static int r600_state_pm4_cb0(struct radeon_state *state);
-static int r600_state_pm4_vgt(struct radeon_state *state);
-static int r600_state_pm4_db(struct radeon_state *state);
-static int r600_state_pm4_shader(struct radeon_state *state);
-static int r600_state_pm4_draw(struct radeon_state *state);
-static int r600_state_pm4_config(struct radeon_state *state);
-static int r600_state_pm4_generic(struct radeon_state *state);
-static int r600_state_pm4_query_begin(struct radeon_state *state);
-static int r600_state_pm4_query_end(struct radeon_state *state);
-static int r700_state_pm4_config(struct radeon_state *state);
-static int r700_state_pm4_cb0(struct radeon_state *state);
-static int r700_state_pm4_db(struct radeon_state *state);
+static const struct radeon_type R600_types[];
+static const struct radeon_type R700_types[];
+#define R600_FLUSH_RESOURCE	((~C_0085F0_TC_ACTION_ENA) | (~C_0085F0_VC_ACTION_ENA))
+#define R600_FLUSH_CB0		(~C_0085F0_CB0_DEST_BASE_ENA)
+#define R600_FLUSH_CB1		(~C_0085F0_CB1_DEST_BASE_ENA)
+#define R600_FLUSH_CB2		(~C_0085F0_CB2_DEST_BASE_ENA)
+#define R600_FLUSH_CB3		(~C_0085F0_CB3_DEST_BASE_ENA)
+#define R600_FLUSH_CB4		(~C_0085F0_CB4_DEST_BASE_ENA)
+#define R600_FLUSH_CB5		(~C_0085F0_CB5_DEST_BASE_ENA)
+#define R600_FLUSH_CB6		(~C_0085F0_CB6_DEST_BASE_ENA)
+#define R600_FLUSH_CB7		(~C_0085F0_CB7_DEST_BASE_ENA)
+#define R600_FLUSH_DB		(~C_0085F0_DB_DEST_BASE_ENA)
+#define R600_DIRTY_ALL		0xFFFFFFFF
+#define R600_DIRTY_ALL2		(R600_FLUSH_RESOURCE | R600_FLUSH_DB | R600_FLUSH_CB0\
+				R600_FLUSH_CB1 | R600_FLUSH_CB2 | R600_FLUSH_CB3\
+				R600_FLUSH_CB4 | R600_FLUSH_CB5 | R600_FLUSH_CB6\
+				R600_FLUSH_CB7)
 
-#include "r600_states.h"
-
-/*
- * r600/r700 state functions
- */
-static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
-{
-	const struct radeon_register *regs = state->radeon->type[state->type].regs;
-	unsigned i;
-	int r;
-
-	if (!offset) {
-		fprintf(stderr, "%s invalid register for state %d %d\n",
-			__func__, state->type, id);
-		return -EINVAL;
-	}
-	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		for (i = 0; i < nreg; i++) {
-			if (regs[id + i].need_reloc) {
-				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
-				if (r)
-					return r;
-				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
-			}
-		}
-		return 0;
-	}
-	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		for (i = 0; i < nreg; i++) {
-			if (regs[id + i].need_reloc) {
-				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
-				if (r)
-					return r;
-				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
-			}
-		}
-		return 0;
-	}
-	if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_ALU_CONST, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_ALU_CONST_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		return 0;
-	}
-	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		return 0;
-	}
-	fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset);
-	return -EINVAL;
-}
-
-static int r600_state_pm4_generic(struct radeon_state *state)
-{
-	struct radeon *radeon = state->radeon;
-	unsigned i, offset, nreg, type, coffset, loffset, soffset;
-	unsigned start;
-	int r;
-
-	if (!state->nstates)
-		return 0;
-	type = state->type;
-	soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride;
-	offset = loffset = radeon->type[type].regs[0].offset + soffset;
-	start = 0;
-	for (i = 1, nreg = 1; i < state->nstates; i++) {
-		coffset = radeon->type[type].regs[i].offset + soffset;
-		if (coffset == (loffset + 4)) {
-			nreg++;
-			loffset = coffset;
-		} else {
-			r = r600_state_pm4_bytecode(state, offset, start, nreg);
-			if (r) {
-				fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg);
-				return r;
-			}
-			offset = loffset = coffset;
-			nreg = 1;
-			start = i;
-		}
-	}
-	return r600_state_pm4_bytecode(state, offset, start, nreg);
-}
-
-static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags)
-{
-	unsigned i, j, add, size;
-
-	state->nreloc = 0;
-	for (i = 0; i < state->nbo; i++) {
-		for (j = 0, add = 1; j < state->nreloc; j++) {
-			if (state->bo[state->reloc_bo_id[j]] == state->bo[i]) {
-				add = 0;
-				break;
-			}
-		}
-		if (add) {
-			state->reloc_bo_id[state->nreloc++] = i;
-		}
-	}
-	for (i = 0; i < state->nreloc; i++) {
-		size = (state->bo[state->reloc_bo_id[i]]->size + 255) >> 8;
-		state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
-		state->pm4[state->cpm4++] = flags;
-		state->pm4[state->cpm4++] = size;
-		state->pm4[state->cpm4++] = 0x00000000;
-		state->pm4[state->cpm4++] = 0x0000000A;
-		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-		state->reloc_pm4_id[i] = state->cpm4;
-		state->pm4[state->cpm4++] = state->bo[state->reloc_bo_id[i]]->handle;
-	}
-}
-
-static int r600_state_pm4_cb0(struct radeon_state *state)
-{
-	int r;
-
-	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
-				S_0085F0_CB0_DEST_BASE_ENA(1));
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
-	state->pm4[state->cpm4++] = 0x00000002;
-	return 0;
-}
-
-static int r700_state_pm4_cb0(struct radeon_state *state)
-{
-	int r;
-
-	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
-				S_0085F0_CB0_DEST_BASE_ENA(1));
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-	return 0;
-}
-
-static int r600_state_pm4_db(struct radeon_state *state)
-{
-	int r;
-
-	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
-				S_0085F0_DB_DEST_BASE_ENA(1));
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
-	state->pm4[state->cpm4++] = 0x00000001;
-	return 0;
-}
-
-static int r700_state_pm4_db(struct radeon_state *state)
-{
-	int r;
-
-	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
-				S_0085F0_DB_DEST_BASE_ENA(1));
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-	return 0;
-}
-
-static int r600_state_pm4_config(struct radeon_state *state)
-{
-	state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0);
-	state->pm4[state->cpm4++] = 0x00000000;
-	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
-	state->pm4[state->cpm4++] = 0x00000010;
-	state->pm4[state->cpm4++] = 0x00028000;
-	return r600_state_pm4_generic(state);
-}
-
-static int r600_state_pm4_query_begin(struct radeon_state *state)
-{
-	int r;
-
-	state->cpm4 = 0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
-	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
-	state->pm4[state->cpm4++] = state->states[0];
-	state->pm4[state->cpm4++] = 0x0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-	r = radeon_state_reloc(state, state->cpm4, 0);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = state->bo[0]->handle;
-	return 0;
-}
-
-static int r600_state_pm4_query_end(struct radeon_state *state)
-{
-	int r;
-
-	state->cpm4 = 0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
-	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
-	state->pm4[state->cpm4++] = state->states[0];
-	state->pm4[state->cpm4++] = 0x0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-	r = radeon_state_reloc(state, state->cpm4, 0);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = state->bo[0]->handle;
-	return 0;
-}
-
-static int r700_state_pm4_config(struct radeon_state *state)
-{
-	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
-	state->pm4[state->cpm4++] = 0x00000010;
-	state->pm4[state->cpm4++] = 0x00028000;
-	return r600_state_pm4_generic(state);
-}
-
-static int r600_state_pm4_shader(struct radeon_state *state)
-{
-	r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1));
-	return r600_state_pm4_generic(state);
-}
-
-static int r600_state_pm4_vgt(struct radeon_state *state)
-{
-	int r;
-
-	r = r600_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, R600_VGT__VGT_MAX_VTX_INDX, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, R600_VGT__VGT_MIN_VTX_INDX, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, R600_VGT__VGT_INDX_OFFSET, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, R600_VGT__VGT_PRIMITIVE_TYPE, 1);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0);
-	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_INDEX_TYPE];
-	state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0);
-	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_NUM_INSTANCES];
-	return 0;
-}
-
-static int r600_state_pm4_draw(struct radeon_state *state)
+static int r600_ctx_bo_flush(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement)
 {
-	unsigned i;
-	int r;
+	unsigned size;
 
-	if (state->nbo) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX, 3);
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE_HI];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
-		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-		r = radeon_state_reloc(state, state->cpm4, 0);
-		if (r)
-			return r;
-		state->pm4[state->cpm4++] = state->bo[0]->handle;
-	} else if  (state->nimmd) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1);
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
-		for (i = 0; i < state->nimmd; i++) {
-			state->pm4[state->cpm4++] = state->immd[i];
-		}
-	} else {
-		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
+	if (7 > ctx->npm4) {
+		return -EBUSY;
 	}
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
-	return 0;
-}
-
-static int r600_state_pm4_resource(struct radeon_state *state)
-{
-	u32 flags, type, nbo, offset, soffset;
-	int r;
-
-	soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride;
-	type = G_038018_TYPE(state->states[6]);
-	switch (type) {
-	case 2:
-		flags = S_0085F0_TC_ACTION_ENA(1);
-		nbo = 2;
-		break;
-	case 3:
-		flags = S_0085F0_VC_ACTION_ENA(1);
-		nbo = 1;
-		break;
-	default:
-		return 0;
-	}
-	if (state->nbo != nbo) {
-		fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo);
-		return -EINVAL;
-	}
-	r600_state_pm4_with_flush(state, flags);
-	offset = state->radeon->type[state->type].regs[0].offset + soffset;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7);
-	state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
-	state->pm4[state->cpm4++] = state->states[0];
-	state->pm4[state->cpm4++] = state->states[1];
-	state->pm4[state->cpm4++] = state->states[2];
-	state->pm4[state->cpm4++] = state->states[3];
-	state->pm4[state->cpm4++] = state->states[4];
-	state->pm4[state->cpm4++] = state->states[5];
-	state->pm4[state->cpm4++] = state->states[6];
-	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-	r = radeon_state_reloc(state, state->cpm4, 0);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = state->bo[0]->handle;
-	if (type == 2) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-		r = radeon_state_reloc(state, state->cpm4, 1);
-		if (r)
-			return r;
-		state->pm4[state->cpm4++] = state->bo[1]->handle;
-	}
-	return 0;
+	size = (bo->size + 255) >> 8;
+	ctx->pm4[ctx->id++] = PKT3(PKT3_SURFACE_SYNC, 3);
+	ctx->pm4[ctx->id++] = flags;
+	ctx->pm4[ctx->id++] = size;
+	ctx->pm4[ctx->id++] = 0x00000000;
+	ctx->pm4[ctx->id++] = 0x0000000A;
+	ctx->pm4[ctx->id++] = PKT3(PKT3_NOP, 0);
+	ctx->pm4[ctx->id++] = 0x00000000;
+	ctx->npm4 -= 7;
+	return radeon_ctx_reloc(ctx, bo, ctx->id - 1, placement);
 }
 
 int r600_init(struct radeon *radeon)
@@ -414,7 +78,6 @@ int r600_init(struct radeon *radeon)
 	case CHIP_RV635:
 	case CHIP_RS780:
 	case CHIP_RS880:
-		radeon->ntype = R600_NTYPE;
 		radeon->nstate = R600_NSTATE;
 		radeon->type = R600_types;
 		break;
@@ -422,7 +85,6 @@ int r600_init(struct radeon *radeon)
 	case CHIP_RV730:
 	case CHIP_RV710:
 	case CHIP_RV740:
-		radeon->ntype = R600_NTYPE;
 		radeon->nstate = R600_NSTATE;
 		radeon->type = R700_types;
 		break;
@@ -431,5 +93,7696 @@ int r600_init(struct radeon *radeon)
 			__func__, radeon->device);
 		return -EINVAL;
 	}
+	radeon->bo_flush = &r600_ctx_bo_flush;
 	return 0;
 }
+
+/* CONFIG */
+#define R600_CONFIG_header_cpm4 12
+static const u32 R600_CONFIG_header_pm4[R600_CONFIG_header_cpm4] = {
+	0xC0002400,
+	0x00000000,
+	0xC0012800,
+	0x80000000,
+	0x80000000,
+	0xC0004600,
+	0x00000016,
+	0xC0016800,
+	0x00000010,
+	0x00028000,
+	0xC0066800,
+	0x00000300,
+};
+#define R700_CONFIG_header_cpm4 10
+u32 R700_CONFIG_header_pm4[R700_CONFIG_header_cpm4] = {
+	0xC0012800,
+	0x80000000,
+	0x80000000,
+	0xC0004600,
+	0x00000016,
+	0xC0016800,
+	0x00000010,
+	0x00028000,
+	0xC0066800,
+	0x00000300,
+};
+#define R600_CONFIG_state_cpm4 67
+u32 R600_CONFIG_state_pm4[R600_CONFIG_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016800,
+	0x00000363,
+	0x00000000,
+	0xC0016800,
+	0x00000542,
+	0x00000000,
+	0xC0016800,
+	0x000005C5,
+	0x00000000,
+	0xC0016800,
+	0x0000060C,
+	0x00000000,
+	0xC0016800,
+	0x0000060E,
+	0x00000000,
+	0xC0016900,
+	0x000000D4,
+	0x00000000,
+	0xC0016900,
+	0x000001B2,
+	0x00000000,
+	0xC0016900,
+	0x000001E8,
+	0x00000000,
+	0xC0096900,
+	0x0000022A,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC00D6900,
+	0x00000284,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000293,
+	0x00000000,
+	0xC0036900,
+	0x000002AC,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x000002C8,
+	0x00000000,
+};
+#define R600_CB_CNTL_header_cpm4 2
+u32 R600_CB_CNTL_header_pm4[R600_CB_CNTL_header_cpm4] = {
+	0xC0046900,
+	0x00000048,
+};
+#define R600_CB_CNTL_state_cpm4 32
+u32 R600_CB_CNTL_state_pm4[R600_CB_CNTL_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0026900,
+	0x0000008E,
+	0x00000000,
+	0x00000000,
+	0xC0036900,
+	0x00000109,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000202,
+	0x00000000,
+	0xC0016900,
+	0x00000301,
+	0x00000000,
+	0xC0026900,
+	0x00000307,
+	0x00000000,
+	0x00000000,
+	0xC0046900,
+	0x0000030C,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000312,
+	0x00000000,
+};
+#define R600_RASTERIZER_header_cpm4 2
+u32 R600_RASTERIZER_header_pm4[R600_RASTERIZER_header_cpm4] = {
+	0xC0016900,
+	0x000001B5,
+};
+#define R600_RASTERIZER_state_cpm4 35
+u32 R600_RASTERIZER_state_pm4[R600_RASTERIZER_state_cpm4] = {
+	0x00000000,
+	0xC0026900,
+	0x00000204,
+	0x00000000,
+	0x00000000,
+	0xC0026900,
+	0x00000207,
+	0x00000000,
+	0x00000000,
+	0xC0046900,
+	0x00000280,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000292,
+	0x00000000,
+	0xC0016900,
+	0x00000300,
+	0x00000000,
+	0xC0046900,
+	0x00000303,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0066900,
+	0x0000037E,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+/* R600_VIEWPORT */
+#define R600_VIEWPORT_header_cpm4 2
+u32 R600_VIEWPORT_header_pm4[R600_VIEWPORT_header_cpm4] = {
+	0xC0026900,
+	0x000000B4,
+};
+#define R600_VIEWPORT_state_cpm4 23
+u32 R600_VIEWPORT_state_pm4[R600_VIEWPORT_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x0000010F,
+	0x00000000,
+	0xC0016900,
+	0x00000111,
+	0x00000000,
+	0xC0016900,
+	0x00000113,
+	0x00000000,
+	0xC0016900,
+	0x00000110,
+	0x00000000,
+	0xC0016900,
+	0x00000112,
+	0x00000000,
+	0xC0016900,
+	0x00000114,
+	0x00000000,
+	0xC0016900,
+	0x00000206,
+	0x00000000,
+};
+#define R600_SCISSOR_header_cpm4 2
+u32 R600_SCISSOR_header_pm4[R600_SCISSOR_header_cpm4] = {
+	0xC0026900,
+	0x0000000C,
+};
+#define R600_SCISSOR_state_cpm4 25
+u32 R600_SCISSOR_state_pm4[R600_SCISSOR_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0xC00D6900,
+	0x00000080,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0026900,
+	0x00000090,
+	0x00000000,
+	0x00000000,
+	0xC0026900,
+	0x00000094,
+	0x00000000,
+	0x00000000,
+};
+
+/* R600_BLEND */
+#define R600_BLEND_header_cpm4 2
+u32 R600_BLEND_header_pm4[R600_BLEND_header_cpm4] = {
+	0xC0046900,
+	0x00000105,
+};
+#define R600_BLEND_state_cpm4 17
+u32 R600_BLEND_state_pm4[R600_BLEND_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0086900,
+	0x000001E0,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000201,
+	0x00000000,
+};
+
+/* R600_DSA */
+#define R600_DSA_header_cpm4 2
+u32 R600_DSA_header_pm4[R600_DSA_header_cpm4] = {
+	0xC0026900,
+	0x0000000A,
+};
+#define R600_DSA_state_cpm4 34
+u32 R600_DSA_state_pm4[R600_DSA_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000104,
+	0x00000000,
+	0xC0036900,
+	0x0000010C,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0026900,
+	0x000001B8,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x000001B7,
+	0x00000000,
+	0xC0016900,
+	0x00000200,
+	0x00000000,
+	0xC0016900,
+	0x00000203,
+	0x00000000,
+	0xC0026900,
+	0x00000343,
+	0x00000000,
+	0x00000000,
+	0xC0026900,
+	0x0000034B,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000351,
+	0x00000000,
+};
+
+/* R600_UCP */
+#define R600_UCP_header_cpm4 2
+u32 R600_UCP0_header_pm4[R600_UCP_header_cpm4] = {
+	0xC0046900,
+	0x00000388,
+};
+u32 R600_UCP1_header_pm4[R600_UCP_header_cpm4] = {
+	0xC0046900,
+	0x0000038C,
+};
+u32 R600_UCP2_header_pm4[R600_UCP_header_cpm4] = {
+	0xC0046900,
+	0x00000390,
+};
+u32 R600_UCP3_header_pm4[R600_UCP_header_cpm4] = {
+	0xC0046900,
+	0x00000394,
+};
+u32 R600_UCP4_header_pm4[R600_UCP_header_cpm4] = {
+	0xC0046900,
+	0x00000398,
+};
+u32 R600_UCP5_header_pm4[R600_UCP_header_cpm4] = {
+	0xC0046900,
+	0x0000039C,
+};
+#define R600_UCP_state_cpm4 4
+u32 R600_UCP_state_pm4[R600_UCP_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+/* R600_VGT */
+#define R600_VGT_header_cpm4 2
+u32 R600_VGT_header_pm4[R600_VGT_header_cpm4] = {
+	0xC0046900,
+	0x00000100,
+};
+#define R600_VGT_state_cpm4 11
+u32 R600_VGT_state_pm4[R600_VGT_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016800,
+	0x00000256,
+	0x00000000,
+	0xC0002A00,
+	0x00000000,
+	0xC0002F00,
+	0x00000000,
+};
+
+/* R600_QUERY */
+#define R600_QUERY_header_cpm4 2
+u32 R600_QUERY_header_pm4[R600_QUERY_header_cpm4] = {
+	0xC0024600,
+	0x00000015,
+};
+#define R600_QUERY_state_cpm4 4
+u32 R600_QUERY_state_pm4[R600_QUERY_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+};
+
+/* R600_DRAW_AUTO */
+#define R600_DRAW_AUTO_header_cpm4 1
+u32 R600_DRAW_AUTO_header_pm4[R600_DRAW_AUTO_header_cpm4] = {
+	0xC0012D00,
+};
+#define R600_DRAW_AUTO_state_cpm4 4
+u32 R600_DRAW_AUTO_state_pm4[R600_DRAW_AUTO_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0xC0004600,
+	0x00000016,
+};
+
+/* R600_DRAW */
+#define R600_DRAW_header_cpm4 1
+u32 R600_DRAW_header_pm4[R600_DRAW_header_cpm4] = {
+	0xC0032B00,
+};
+#define R600_DRAW_state_cpm4 8
+u32 R600_DRAW_state_pm4[R600_DRAW_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0004600,
+	0x00000016,
+};
+
+/* R600_VS_SHADER */
+#define R600_VS_SHADER_header_cpm4 2
+u32 R600_VS_SHADER_header_pm4[R600_VS_SHADER_header_cpm4] = {
+	0xC0206900,
+	0x000000E0,
+};
+#define R600_VS_SHADER_state_cpm4 69
+u32 R600_VS_SHADER_state_pm4[R600_VS_SHADER_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC00A6900,
+	0x00000185,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x000001B1,
+	0x00000000,
+	0xC0016900,
+	0x00000216,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x0000021A,
+	0x00000000,
+	0xC0016900,
+	0x00000225,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000229,
+	0x00000000,
+	0xC0016900,
+	0x00000234,
+	0x00000000,
+	0xC0016900,
+	0x00000237,
+	0x00000000,
+};
+
+/* R600_PS_SHADER */
+#define R600_PS_SHADER_header_cpm4 2
+u32 R600_PS_SHADER_header_pm4[R600_PS_SHADER_header_cpm4] = {
+	0xC0206900,
+	0x00000191,
+};
+#define R600_PS_SHADER_state_cpm4 51
+u32 R600_PS_SHADER_state_pm4[R600_PS_SHADER_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0026900,
+	0x000001B3,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x000001B6,
+	0x00000000,
+	0xC0016900,
+	0x00000210,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0026900,
+	0x00000214,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000233,
+	0x00000000,
+};
+
+/* R600_DB */
+#define R600_DB_header_cpm4 2
+u32 R600_DB_header_pm4[R600_DB_header_cpm4] = {
+	0xC0016900,
+	0x00000003,
+};
+#define R600_DB_state_cpm4 18
+u32 R600_DB_state_pm4[R600_DB_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0026900,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0xC0016900,
+	0x00000004,
+	0x00000000,
+	0xC0016900,
+	0x00000349,
+	0x00000000,
+	0xC0016900,
+	0x0000034D,
+	0x00000000,
+	0xC0007300,
+	0x00000001,
+};
+
+/* R600_CB0 */
+#define R600_CB0_header_cpm4 2
+u32 R600_CB0_header_pm4[R600_CB0_header_cpm4] = {
+	0xC0016900,
+	0x00000010,
+};
+#define R600_CB0_state_cpm4 27
+u32 R600_CB0_state_pm4[R600_CB0_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000028,
+	0x00000000,
+	0xC0016900,
+	0x00000018,
+	0x00000000,
+	0xC0016900,
+	0x00000020,
+	0x00000000,
+	0xC0016900,
+	0x00000038,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000030,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000040,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CB1 */
+#define R600_CB1_header_cpm4 2
+u32 R600_CB1_header_pm4[R600_CB1_header_cpm4] = {
+	0xC0016900,
+	0x00000011,
+};
+#define R600_CB1_state_cpm4 27
+u32 R600_CB1_state_pm4[R600_CB1_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000029,
+	0x00000000,
+	0xC0016900,
+	0x00000019,
+	0x00000000,
+	0xC0016900,
+	0x00000021,
+	0x00000000,
+	0xC0016900,
+	0x00000039,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000031,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000041,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CB2 */
+#define R600_CB2_header_cpm4 2
+u32 R600_CB2_header_pm4[R600_CB2_header_cpm4] = {
+	0xC0016900,
+	0x00000012,
+};
+#define R600_CB2_state_cpm4 27
+u32 R600_CB2_state_pm4[R600_CB2_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000004,
+	0xC0016900,
+	0x0000002A,
+	0x00000000,
+	0xC0016900,
+	0x0000001A,
+	0x00000000,
+	0xC0016900,
+	0x00000022,
+	0x00000000,
+	0xC0016900,
+	0x0000003A,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000032,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000042,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CB3 */
+#define R600_CB3_header_cpm4 2
+u32 R600_CB3_header_pm4[R600_CB3_header_cpm4] = {
+	0xC0016900,
+	0x00000013,
+};
+#define R600_CB3_state_cpm4 27
+u32 R600_CB3_state_pm4[R600_CB3_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000004,
+	0xC0016900,
+	0x0000002B,
+	0x00000000,
+	0xC0016900,
+	0x0000001B,
+	0x00000000,
+	0xC0016900,
+	0x00000023,
+	0x00000000,
+	0xC0016900,
+	0x0000003B,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000033,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000043,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CB4 */
+#define R600_CB4_header_cpm4 2
+u32 R600_CB4_header_pm4[R600_CB4_header_cpm4] = {
+	0xC0016900,
+	0x00000014,
+};
+#define R600_CB4_state_cpm4 27
+u32 R600_CB4_state_pm4[R600_CB4_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000004,
+	0xC0016900,
+	0x0000002C,
+	0x00000000,
+	0xC0016900,
+	0x0000001C,
+	0x00000000,
+	0xC0016900,
+	0x00000024,
+	0x00000000,
+	0xC0016900,
+	0x0000003C,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000034,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000044,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CB5 */
+#define R600_CB5_header_cpm4 2
+u32 R600_CB5_header_pm4[R600_CB5_header_cpm4] = {
+	0xC0016900,
+	0x00000015,
+};
+#define R600_CB5_state_cpm4 27
+u32 R600_CB5_state_pm4[R600_CB5_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000004,
+	0xC0016900,
+	0x0000002D,
+	0x00000000,
+	0xC0016900,
+	0x0000001D,
+	0x00000000,
+	0xC0016900,
+	0x00000025,
+	0x00000000,
+	0xC0016900,
+	0x0000003D,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000035,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000045,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CB6 */
+#define R600_CB6_header_cpm4 2
+u32 R600_CB6_header_pm4[R600_CB6_header_cpm4] = {
+	0xC0016900,
+	0x00000016,
+};
+#define R600_CB6_state_cpm4 27
+u32 R600_CB6_state_pm4[R600_CB6_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000004,
+	0xC0016900,
+	0x0000002E,
+	0x00000000,
+	0xC0016900,
+	0x0000001E,
+	0x00000000,
+	0xC0016900,
+	0x00000026,
+	0x00000000,
+	0xC0016900,
+	0x0000003E,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000036,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000046,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CB7 */
+#define R600_CB7_header_cpm4 2
+u32 R600_CB7_header_pm4[R600_CB7_header_cpm4] = {
+	0xC0016900,
+	0x00000017,
+};
+#define R600_CB7_state_cpm4 27
+u32 R600_CB7_state_pm4[R600_CB7_state_cpm4] = {
+	0x00000000,
+	0xC0001000,
+	0x00000004,
+	0xC0016900,
+	0x0000002F,
+	0x00000000,
+	0xC0016900,
+	0x0000001F,
+	0x00000000,
+	0xC0016900,
+	0x00000027,
+	0x00000000,
+	0xC0016900,
+	0x0000003F,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000037,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+	0xC0016900,
+	0x00000047,
+	0x00000000,
+	0xC0007300,
+	0x00000002,
+};
+
+/* R600_CONSTANT */
+#define R600_CONSTANT_header_cpm4 2
+u32 R600_PS_CONSTANT0_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000000,
+};
+u32 R600_PS_CONSTANT1_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000004,
+};
+u32 R600_PS_CONSTANT2_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000008,
+};
+u32 R600_PS_CONSTANT3_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000000C,
+};
+u32 R600_PS_CONSTANT4_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000010,
+};
+u32 R600_PS_CONSTANT5_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000014,
+};
+u32 R600_PS_CONSTANT6_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000018,
+};
+u32 R600_PS_CONSTANT7_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000001C,
+};
+u32 R600_PS_CONSTANT8_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000020,
+};
+u32 R600_PS_CONSTANT9_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000024,
+};
+u32 R600_PS_CONSTANT10_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000028,
+};
+u32 R600_PS_CONSTANT11_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000002C,
+};
+u32 R600_PS_CONSTANT12_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000030,
+};
+u32 R600_PS_CONSTANT13_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000034,
+};
+u32 R600_PS_CONSTANT14_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000038,
+};
+u32 R600_PS_CONSTANT15_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000003C,
+};
+u32 R600_PS_CONSTANT16_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000040,
+};
+u32 R600_PS_CONSTANT17_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000044,
+};
+u32 R600_PS_CONSTANT18_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000048,
+};
+u32 R600_PS_CONSTANT19_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000004C,
+};
+u32 R600_PS_CONSTANT20_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000050,
+};
+u32 R600_PS_CONSTANT21_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000054,
+};
+u32 R600_PS_CONSTANT22_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000058,
+};
+u32 R600_PS_CONSTANT23_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000005C,
+};
+u32 R600_PS_CONSTANT24_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000060,
+};
+u32 R600_PS_CONSTANT25_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000064,
+};
+u32 R600_PS_CONSTANT26_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000068,
+};
+u32 R600_PS_CONSTANT27_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000006C,
+};
+u32 R600_PS_CONSTANT28_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000070,
+};
+u32 R600_PS_CONSTANT29_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000074,
+};
+u32 R600_PS_CONSTANT30_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000078,
+};
+u32 R600_PS_CONSTANT31_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000007C,
+};
+u32 R600_PS_CONSTANT32_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000080,
+};
+u32 R600_PS_CONSTANT33_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000084,
+};
+u32 R600_PS_CONSTANT34_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000088,
+};
+u32 R600_PS_CONSTANT35_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000008C,
+};
+u32 R600_PS_CONSTANT36_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000090,
+};
+u32 R600_PS_CONSTANT37_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000094,
+};
+u32 R600_PS_CONSTANT38_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000098,
+};
+u32 R600_PS_CONSTANT39_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000009C,
+};
+u32 R600_PS_CONSTANT40_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000A0,
+};
+u32 R600_PS_CONSTANT41_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000A4,
+};
+u32 R600_PS_CONSTANT42_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000A8,
+};
+u32 R600_PS_CONSTANT43_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000AC,
+};
+u32 R600_PS_CONSTANT44_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000B0,
+};
+u32 R600_PS_CONSTANT45_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000B4,
+};
+u32 R600_PS_CONSTANT46_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000B8,
+};
+u32 R600_PS_CONSTANT47_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000BC,
+};
+u32 R600_PS_CONSTANT48_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000C0,
+};
+u32 R600_PS_CONSTANT49_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000C4,
+};
+u32 R600_PS_CONSTANT50_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000C8,
+};
+u32 R600_PS_CONSTANT51_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000CC,
+};
+u32 R600_PS_CONSTANT52_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000D0,
+};
+u32 R600_PS_CONSTANT53_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000D4,
+};
+u32 R600_PS_CONSTANT54_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000D8,
+};
+u32 R600_PS_CONSTANT55_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000DC,
+};
+u32 R600_PS_CONSTANT56_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000E0,
+};
+u32 R600_PS_CONSTANT57_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000E4,
+};
+u32 R600_PS_CONSTANT58_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000E8,
+};
+u32 R600_PS_CONSTANT59_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000EC,
+};
+u32 R600_PS_CONSTANT60_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000F0,
+};
+u32 R600_PS_CONSTANT61_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000F4,
+};
+u32 R600_PS_CONSTANT62_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000F8,
+};
+u32 R600_PS_CONSTANT63_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000000FC,
+};
+u32 R600_PS_CONSTANT64_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000100,
+};
+u32 R600_PS_CONSTANT65_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000104,
+};
+u32 R600_PS_CONSTANT66_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000108,
+};
+u32 R600_PS_CONSTANT67_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000010C,
+};
+u32 R600_PS_CONSTANT68_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000110,
+};
+u32 R600_PS_CONSTANT69_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000114,
+};
+u32 R600_PS_CONSTANT70_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000118,
+};
+u32 R600_PS_CONSTANT71_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000011C,
+};
+u32 R600_PS_CONSTANT72_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000120,
+};
+u32 R600_PS_CONSTANT73_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000124,
+};
+u32 R600_PS_CONSTANT74_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000128,
+};
+u32 R600_PS_CONSTANT75_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000012C,
+};
+u32 R600_PS_CONSTANT76_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000130,
+};
+u32 R600_PS_CONSTANT77_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000134,
+};
+u32 R600_PS_CONSTANT78_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000138,
+};
+u32 R600_PS_CONSTANT79_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000013C,
+};
+u32 R600_PS_CONSTANT80_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000140,
+};
+u32 R600_PS_CONSTANT81_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000144,
+};
+u32 R600_PS_CONSTANT82_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000148,
+};
+u32 R600_PS_CONSTANT83_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000014C,
+};
+u32 R600_PS_CONSTANT84_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000150,
+};
+u32 R600_PS_CONSTANT85_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000154,
+};
+u32 R600_PS_CONSTANT86_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000158,
+};
+u32 R600_PS_CONSTANT87_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000015C,
+};
+u32 R600_PS_CONSTANT88_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000160,
+};
+u32 R600_PS_CONSTANT89_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000164,
+};
+u32 R600_PS_CONSTANT90_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000168,
+};
+u32 R600_PS_CONSTANT91_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000016C,
+};
+u32 R600_PS_CONSTANT92_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000170,
+};
+u32 R600_PS_CONSTANT93_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000174,
+};
+u32 R600_PS_CONSTANT94_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000178,
+};
+u32 R600_PS_CONSTANT95_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000017C,
+};
+u32 R600_PS_CONSTANT96_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000180,
+};
+u32 R600_PS_CONSTANT97_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000184,
+};
+u32 R600_PS_CONSTANT98_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000188,
+};
+u32 R600_PS_CONSTANT99_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000018C,
+};
+u32 R600_PS_CONSTANT100_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000190,
+};
+u32 R600_PS_CONSTANT101_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000194,
+};
+u32 R600_PS_CONSTANT102_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000198,
+};
+u32 R600_PS_CONSTANT103_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000019C,
+};
+u32 R600_PS_CONSTANT104_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001A0,
+};
+u32 R600_PS_CONSTANT105_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001A4,
+};
+u32 R600_PS_CONSTANT106_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001A8,
+};
+u32 R600_PS_CONSTANT107_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001AC,
+};
+u32 R600_PS_CONSTANT108_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001B0,
+};
+u32 R600_PS_CONSTANT109_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001B4,
+};
+u32 R600_PS_CONSTANT110_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001B8,
+};
+u32 R600_PS_CONSTANT111_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001BC,
+};
+u32 R600_PS_CONSTANT112_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001C0,
+};
+u32 R600_PS_CONSTANT113_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001C4,
+};
+u32 R600_PS_CONSTANT114_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001C8,
+};
+u32 R600_PS_CONSTANT115_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001CC,
+};
+u32 R600_PS_CONSTANT116_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001D0,
+};
+u32 R600_PS_CONSTANT117_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001D4,
+};
+u32 R600_PS_CONSTANT118_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001D8,
+};
+u32 R600_PS_CONSTANT119_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001DC,
+};
+u32 R600_PS_CONSTANT120_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001E0,
+};
+u32 R600_PS_CONSTANT121_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001E4,
+};
+u32 R600_PS_CONSTANT122_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001E8,
+};
+u32 R600_PS_CONSTANT123_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001EC,
+};
+u32 R600_PS_CONSTANT124_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001F0,
+};
+u32 R600_PS_CONSTANT125_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001F4,
+};
+u32 R600_PS_CONSTANT126_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001F8,
+};
+u32 R600_PS_CONSTANT127_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000001FC,
+};
+u32 R600_PS_CONSTANT128_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000200,
+};
+u32 R600_PS_CONSTANT129_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000204,
+};
+u32 R600_PS_CONSTANT130_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000208,
+};
+u32 R600_PS_CONSTANT131_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000020C,
+};
+u32 R600_PS_CONSTANT132_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000210,
+};
+u32 R600_PS_CONSTANT133_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000214,
+};
+u32 R600_PS_CONSTANT134_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000218,
+};
+u32 R600_PS_CONSTANT135_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000021C,
+};
+u32 R600_PS_CONSTANT136_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000220,
+};
+u32 R600_PS_CONSTANT137_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000224,
+};
+u32 R600_PS_CONSTANT138_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000228,
+};
+u32 R600_PS_CONSTANT139_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000022C,
+};
+u32 R600_PS_CONSTANT140_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000230,
+};
+u32 R600_PS_CONSTANT141_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000234,
+};
+u32 R600_PS_CONSTANT142_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000238,
+};
+u32 R600_PS_CONSTANT143_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000023C,
+};
+u32 R600_PS_CONSTANT144_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000240,
+};
+u32 R600_PS_CONSTANT145_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000244,
+};
+u32 R600_PS_CONSTANT146_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000248,
+};
+u32 R600_PS_CONSTANT147_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000024C,
+};
+u32 R600_PS_CONSTANT148_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000250,
+};
+u32 R600_PS_CONSTANT149_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000254,
+};
+u32 R600_PS_CONSTANT150_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000258,
+};
+u32 R600_PS_CONSTANT151_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000025C,
+};
+u32 R600_PS_CONSTANT152_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000260,
+};
+u32 R600_PS_CONSTANT153_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000264,
+};
+u32 R600_PS_CONSTANT154_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000268,
+};
+u32 R600_PS_CONSTANT155_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000026C,
+};
+u32 R600_PS_CONSTANT156_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000270,
+};
+u32 R600_PS_CONSTANT157_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000274,
+};
+u32 R600_PS_CONSTANT158_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000278,
+};
+u32 R600_PS_CONSTANT159_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000027C,
+};
+u32 R600_PS_CONSTANT160_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000280,
+};
+u32 R600_PS_CONSTANT161_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000284,
+};
+u32 R600_PS_CONSTANT162_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000288,
+};
+u32 R600_PS_CONSTANT163_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000028C,
+};
+u32 R600_PS_CONSTANT164_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000290,
+};
+u32 R600_PS_CONSTANT165_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000294,
+};
+u32 R600_PS_CONSTANT166_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000298,
+};
+u32 R600_PS_CONSTANT167_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000029C,
+};
+u32 R600_PS_CONSTANT168_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002A0,
+};
+u32 R600_PS_CONSTANT169_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002A4,
+};
+u32 R600_PS_CONSTANT170_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002A8,
+};
+u32 R600_PS_CONSTANT171_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002AC,
+};
+u32 R600_PS_CONSTANT172_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002B0,
+};
+u32 R600_PS_CONSTANT173_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002B4,
+};
+u32 R600_PS_CONSTANT174_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002B8,
+};
+u32 R600_PS_CONSTANT175_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002BC,
+};
+u32 R600_PS_CONSTANT176_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002C0,
+};
+u32 R600_PS_CONSTANT177_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002C4,
+};
+u32 R600_PS_CONSTANT178_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002C8,
+};
+u32 R600_PS_CONSTANT179_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002CC,
+};
+u32 R600_PS_CONSTANT180_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002D0,
+};
+u32 R600_PS_CONSTANT181_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002D4,
+};
+u32 R600_PS_CONSTANT182_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002D8,
+};
+u32 R600_PS_CONSTANT183_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002DC,
+};
+u32 R600_PS_CONSTANT184_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002E0,
+};
+u32 R600_PS_CONSTANT185_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002E4,
+};
+u32 R600_PS_CONSTANT186_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002E8,
+};
+u32 R600_PS_CONSTANT187_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002EC,
+};
+u32 R600_PS_CONSTANT188_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002F0,
+};
+u32 R600_PS_CONSTANT189_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002F4,
+};
+u32 R600_PS_CONSTANT190_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002F8,
+};
+u32 R600_PS_CONSTANT191_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000002FC,
+};
+u32 R600_PS_CONSTANT192_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000300,
+};
+u32 R600_PS_CONSTANT193_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000304,
+};
+u32 R600_PS_CONSTANT194_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000308,
+};
+u32 R600_PS_CONSTANT195_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000030C,
+};
+u32 R600_PS_CONSTANT196_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000310,
+};
+u32 R600_PS_CONSTANT197_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000314,
+};
+u32 R600_PS_CONSTANT198_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000318,
+};
+u32 R600_PS_CONSTANT199_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000031C,
+};
+u32 R600_PS_CONSTANT200_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000320,
+};
+u32 R600_PS_CONSTANT201_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000324,
+};
+u32 R600_PS_CONSTANT202_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000328,
+};
+u32 R600_PS_CONSTANT203_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000032C,
+};
+u32 R600_PS_CONSTANT204_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000330,
+};
+u32 R600_PS_CONSTANT205_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000334,
+};
+u32 R600_PS_CONSTANT206_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000338,
+};
+u32 R600_PS_CONSTANT207_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000033C,
+};
+u32 R600_PS_CONSTANT208_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000340,
+};
+u32 R600_PS_CONSTANT209_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000344,
+};
+u32 R600_PS_CONSTANT210_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000348,
+};
+u32 R600_PS_CONSTANT211_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000034C,
+};
+u32 R600_PS_CONSTANT212_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000350,
+};
+u32 R600_PS_CONSTANT213_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000354,
+};
+u32 R600_PS_CONSTANT214_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000358,
+};
+u32 R600_PS_CONSTANT215_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000035C,
+};
+u32 R600_PS_CONSTANT216_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000360,
+};
+u32 R600_PS_CONSTANT217_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000364,
+};
+u32 R600_PS_CONSTANT218_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000368,
+};
+u32 R600_PS_CONSTANT219_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000036C,
+};
+u32 R600_PS_CONSTANT220_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000370,
+};
+u32 R600_PS_CONSTANT221_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000374,
+};
+u32 R600_PS_CONSTANT222_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000378,
+};
+u32 R600_PS_CONSTANT223_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000037C,
+};
+u32 R600_PS_CONSTANT224_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000380,
+};
+u32 R600_PS_CONSTANT225_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000384,
+};
+u32 R600_PS_CONSTANT226_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000388,
+};
+u32 R600_PS_CONSTANT227_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000038C,
+};
+u32 R600_PS_CONSTANT228_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000390,
+};
+u32 R600_PS_CONSTANT229_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000394,
+};
+u32 R600_PS_CONSTANT230_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000398,
+};
+u32 R600_PS_CONSTANT231_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000039C,
+};
+u32 R600_PS_CONSTANT232_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003A0,
+};
+u32 R600_PS_CONSTANT233_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003A4,
+};
+u32 R600_PS_CONSTANT234_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003A8,
+};
+u32 R600_PS_CONSTANT235_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003AC,
+};
+u32 R600_PS_CONSTANT236_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003B0,
+};
+u32 R600_PS_CONSTANT237_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003B4,
+};
+u32 R600_PS_CONSTANT238_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003B8,
+};
+u32 R600_PS_CONSTANT239_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003BC,
+};
+u32 R600_PS_CONSTANT240_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003C0,
+};
+u32 R600_PS_CONSTANT241_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003C4,
+};
+u32 R600_PS_CONSTANT242_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003C8,
+};
+u32 R600_PS_CONSTANT243_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003CC,
+};
+u32 R600_PS_CONSTANT244_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003D0,
+};
+u32 R600_PS_CONSTANT245_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003D4,
+};
+u32 R600_PS_CONSTANT246_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003D8,
+};
+u32 R600_PS_CONSTANT247_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003DC,
+};
+u32 R600_PS_CONSTANT248_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003E0,
+};
+u32 R600_PS_CONSTANT249_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003E4,
+};
+u32 R600_PS_CONSTANT250_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003E8,
+};
+u32 R600_PS_CONSTANT251_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003EC,
+};
+u32 R600_PS_CONSTANT252_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003F0,
+};
+u32 R600_PS_CONSTANT253_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003F4,
+};
+u32 R600_PS_CONSTANT254_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003F8,
+};
+u32 R600_PS_CONSTANT255_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000003FC,
+};
+u32 R600_VS_CONSTANT0_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000400,
+};
+u32 R600_VS_CONSTANT1_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000404,
+};
+u32 R600_VS_CONSTANT2_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000408,
+};
+u32 R600_VS_CONSTANT3_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000040C,
+};
+u32 R600_VS_CONSTANT4_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000410,
+};
+u32 R600_VS_CONSTANT5_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000414,
+};
+u32 R600_VS_CONSTANT6_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000418,
+};
+u32 R600_VS_CONSTANT7_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000041C,
+};
+u32 R600_VS_CONSTANT8_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000420,
+};
+u32 R600_VS_CONSTANT9_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000424,
+};
+u32 R600_VS_CONSTANT10_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000428,
+};
+u32 R600_VS_CONSTANT11_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000042C,
+};
+u32 R600_VS_CONSTANT12_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000430,
+};
+u32 R600_VS_CONSTANT13_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000434,
+};
+u32 R600_VS_CONSTANT14_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000438,
+};
+u32 R600_VS_CONSTANT15_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000043C,
+};
+u32 R600_VS_CONSTANT16_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000440,
+};
+u32 R600_VS_CONSTANT17_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000444,
+};
+u32 R600_VS_CONSTANT18_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000448,
+};
+u32 R600_VS_CONSTANT19_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000044C,
+};
+u32 R600_VS_CONSTANT20_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000450,
+};
+u32 R600_VS_CONSTANT21_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000454,
+};
+u32 R600_VS_CONSTANT22_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000458,
+};
+u32 R600_VS_CONSTANT23_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000045C,
+};
+u32 R600_VS_CONSTANT24_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000460,
+};
+u32 R600_VS_CONSTANT25_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000464,
+};
+u32 R600_VS_CONSTANT26_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000468,
+};
+u32 R600_VS_CONSTANT27_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000046C,
+};
+u32 R600_VS_CONSTANT28_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000470,
+};
+u32 R600_VS_CONSTANT29_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000474,
+};
+u32 R600_VS_CONSTANT30_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000478,
+};
+u32 R600_VS_CONSTANT31_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000047C,
+};
+u32 R600_VS_CONSTANT32_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000480,
+};
+u32 R600_VS_CONSTANT33_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000484,
+};
+u32 R600_VS_CONSTANT34_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000488,
+};
+u32 R600_VS_CONSTANT35_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000048C,
+};
+u32 R600_VS_CONSTANT36_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000490,
+};
+u32 R600_VS_CONSTANT37_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000494,
+};
+u32 R600_VS_CONSTANT38_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000498,
+};
+u32 R600_VS_CONSTANT39_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000049C,
+};
+u32 R600_VS_CONSTANT40_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004A0,
+};
+u32 R600_VS_CONSTANT41_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004A4,
+};
+u32 R600_VS_CONSTANT42_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004A8,
+};
+u32 R600_VS_CONSTANT43_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004AC,
+};
+u32 R600_VS_CONSTANT44_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004B0,
+};
+u32 R600_VS_CONSTANT45_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004B4,
+};
+u32 R600_VS_CONSTANT46_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004B8,
+};
+u32 R600_VS_CONSTANT47_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004BC,
+};
+u32 R600_VS_CONSTANT48_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004C0,
+};
+u32 R600_VS_CONSTANT49_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004C4,
+};
+u32 R600_VS_CONSTANT50_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004C8,
+};
+u32 R600_VS_CONSTANT51_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004CC,
+};
+u32 R600_VS_CONSTANT52_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004D0,
+};
+u32 R600_VS_CONSTANT53_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004D4,
+};
+u32 R600_VS_CONSTANT54_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004D8,
+};
+u32 R600_VS_CONSTANT55_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004DC,
+};
+u32 R600_VS_CONSTANT56_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004E0,
+};
+u32 R600_VS_CONSTANT57_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004E4,
+};
+u32 R600_VS_CONSTANT58_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004E8,
+};
+u32 R600_VS_CONSTANT59_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004EC,
+};
+u32 R600_VS_CONSTANT60_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004F0,
+};
+u32 R600_VS_CONSTANT61_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004F4,
+};
+u32 R600_VS_CONSTANT62_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004F8,
+};
+u32 R600_VS_CONSTANT63_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000004FC,
+};
+u32 R600_VS_CONSTANT64_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000500,
+};
+u32 R600_VS_CONSTANT65_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000504,
+};
+u32 R600_VS_CONSTANT66_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000508,
+};
+u32 R600_VS_CONSTANT67_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000050C,
+};
+u32 R600_VS_CONSTANT68_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000510,
+};
+u32 R600_VS_CONSTANT69_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000514,
+};
+u32 R600_VS_CONSTANT70_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000518,
+};
+u32 R600_VS_CONSTANT71_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000051C,
+};
+u32 R600_VS_CONSTANT72_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000520,
+};
+u32 R600_VS_CONSTANT73_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000524,
+};
+u32 R600_VS_CONSTANT74_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000528,
+};
+u32 R600_VS_CONSTANT75_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000052C,
+};
+u32 R600_VS_CONSTANT76_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000530,
+};
+u32 R600_VS_CONSTANT77_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000534,
+};
+u32 R600_VS_CONSTANT78_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000538,
+};
+u32 R600_VS_CONSTANT79_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000053C,
+};
+u32 R600_VS_CONSTANT80_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000540,
+};
+u32 R600_VS_CONSTANT81_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000544,
+};
+u32 R600_VS_CONSTANT82_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000548,
+};
+u32 R600_VS_CONSTANT83_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000054C,
+};
+u32 R600_VS_CONSTANT84_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000550,
+};
+u32 R600_VS_CONSTANT85_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000554,
+};
+u32 R600_VS_CONSTANT86_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000558,
+};
+u32 R600_VS_CONSTANT87_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000055C,
+};
+u32 R600_VS_CONSTANT88_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000560,
+};
+u32 R600_VS_CONSTANT89_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000564,
+};
+u32 R600_VS_CONSTANT90_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000568,
+};
+u32 R600_VS_CONSTANT91_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000056C,
+};
+u32 R600_VS_CONSTANT92_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000570,
+};
+u32 R600_VS_CONSTANT93_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000574,
+};
+u32 R600_VS_CONSTANT94_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000578,
+};
+u32 R600_VS_CONSTANT95_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000057C,
+};
+u32 R600_VS_CONSTANT96_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000580,
+};
+u32 R600_VS_CONSTANT97_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000584,
+};
+u32 R600_VS_CONSTANT98_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000588,
+};
+u32 R600_VS_CONSTANT99_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000058C,
+};
+u32 R600_VS_CONSTANT100_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000590,
+};
+u32 R600_VS_CONSTANT101_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000594,
+};
+u32 R600_VS_CONSTANT102_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000598,
+};
+u32 R600_VS_CONSTANT103_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000059C,
+};
+u32 R600_VS_CONSTANT104_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005A0,
+};
+u32 R600_VS_CONSTANT105_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005A4,
+};
+u32 R600_VS_CONSTANT106_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005A8,
+};
+u32 R600_VS_CONSTANT107_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005AC,
+};
+u32 R600_VS_CONSTANT108_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005B0,
+};
+u32 R600_VS_CONSTANT109_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005B4,
+};
+u32 R600_VS_CONSTANT110_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005B8,
+};
+u32 R600_VS_CONSTANT111_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005BC,
+};
+u32 R600_VS_CONSTANT112_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005C0,
+};
+u32 R600_VS_CONSTANT113_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005C4,
+};
+u32 R600_VS_CONSTANT114_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005C8,
+};
+u32 R600_VS_CONSTANT115_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005CC,
+};
+u32 R600_VS_CONSTANT116_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005D0,
+};
+u32 R600_VS_CONSTANT117_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005D4,
+};
+u32 R600_VS_CONSTANT118_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005D8,
+};
+u32 R600_VS_CONSTANT119_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005DC,
+};
+u32 R600_VS_CONSTANT120_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005E0,
+};
+u32 R600_VS_CONSTANT121_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005E4,
+};
+u32 R600_VS_CONSTANT122_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005E8,
+};
+u32 R600_VS_CONSTANT123_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005EC,
+};
+u32 R600_VS_CONSTANT124_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005F0,
+};
+u32 R600_VS_CONSTANT125_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005F4,
+};
+u32 R600_VS_CONSTANT126_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005F8,
+};
+u32 R600_VS_CONSTANT127_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000005FC,
+};
+u32 R600_VS_CONSTANT128_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000600,
+};
+u32 R600_VS_CONSTANT129_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000604,
+};
+u32 R600_VS_CONSTANT130_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000608,
+};
+u32 R600_VS_CONSTANT131_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000060C,
+};
+u32 R600_VS_CONSTANT132_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000610,
+};
+u32 R600_VS_CONSTANT133_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000614,
+};
+u32 R600_VS_CONSTANT134_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000618,
+};
+u32 R600_VS_CONSTANT135_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000061C,
+};
+u32 R600_VS_CONSTANT136_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000620,
+};
+u32 R600_VS_CONSTANT137_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000624,
+};
+u32 R600_VS_CONSTANT138_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000628,
+};
+u32 R600_VS_CONSTANT139_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000062C,
+};
+u32 R600_VS_CONSTANT140_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000630,
+};
+u32 R600_VS_CONSTANT141_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000634,
+};
+u32 R600_VS_CONSTANT142_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000638,
+};
+u32 R600_VS_CONSTANT143_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000063C,
+};
+u32 R600_VS_CONSTANT144_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000640,
+};
+u32 R600_VS_CONSTANT145_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000644,
+};
+u32 R600_VS_CONSTANT146_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000648,
+};
+u32 R600_VS_CONSTANT147_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000064C,
+};
+u32 R600_VS_CONSTANT148_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000650,
+};
+u32 R600_VS_CONSTANT149_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000654,
+};
+u32 R600_VS_CONSTANT150_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000658,
+};
+u32 R600_VS_CONSTANT151_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000065C,
+};
+u32 R600_VS_CONSTANT152_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000660,
+};
+u32 R600_VS_CONSTANT153_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000664,
+};
+u32 R600_VS_CONSTANT154_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000668,
+};
+u32 R600_VS_CONSTANT155_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000066C,
+};
+u32 R600_VS_CONSTANT156_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000670,
+};
+u32 R600_VS_CONSTANT157_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000674,
+};
+u32 R600_VS_CONSTANT158_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000678,
+};
+u32 R600_VS_CONSTANT159_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000067C,
+};
+u32 R600_VS_CONSTANT160_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000680,
+};
+u32 R600_VS_CONSTANT161_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000684,
+};
+u32 R600_VS_CONSTANT162_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000688,
+};
+u32 R600_VS_CONSTANT163_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000068C,
+};
+u32 R600_VS_CONSTANT164_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000690,
+};
+u32 R600_VS_CONSTANT165_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000694,
+};
+u32 R600_VS_CONSTANT166_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000698,
+};
+u32 R600_VS_CONSTANT167_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000069C,
+};
+u32 R600_VS_CONSTANT168_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006A0,
+};
+u32 R600_VS_CONSTANT169_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006A4,
+};
+u32 R600_VS_CONSTANT170_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006A8,
+};
+u32 R600_VS_CONSTANT171_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006AC,
+};
+u32 R600_VS_CONSTANT172_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006B0,
+};
+u32 R600_VS_CONSTANT173_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006B4,
+};
+u32 R600_VS_CONSTANT174_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006B8,
+};
+u32 R600_VS_CONSTANT175_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006BC,
+};
+u32 R600_VS_CONSTANT176_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006C0,
+};
+u32 R600_VS_CONSTANT177_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006C4,
+};
+u32 R600_VS_CONSTANT178_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006C8,
+};
+u32 R600_VS_CONSTANT179_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006CC,
+};
+u32 R600_VS_CONSTANT180_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006D0,
+};
+u32 R600_VS_CONSTANT181_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006D4,
+};
+u32 R600_VS_CONSTANT182_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006D8,
+};
+u32 R600_VS_CONSTANT183_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006DC,
+};
+u32 R600_VS_CONSTANT184_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006E0,
+};
+u32 R600_VS_CONSTANT185_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006E4,
+};
+u32 R600_VS_CONSTANT186_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006E8,
+};
+u32 R600_VS_CONSTANT187_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006EC,
+};
+u32 R600_VS_CONSTANT188_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006F0,
+};
+u32 R600_VS_CONSTANT189_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006F4,
+};
+u32 R600_VS_CONSTANT190_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006F8,
+};
+u32 R600_VS_CONSTANT191_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000006FC,
+};
+u32 R600_VS_CONSTANT192_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000700,
+};
+u32 R600_VS_CONSTANT193_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000704,
+};
+u32 R600_VS_CONSTANT194_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000708,
+};
+u32 R600_VS_CONSTANT195_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000070C,
+};
+u32 R600_VS_CONSTANT196_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000710,
+};
+u32 R600_VS_CONSTANT197_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000714,
+};
+u32 R600_VS_CONSTANT198_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000718,
+};
+u32 R600_VS_CONSTANT199_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000071C,
+};
+u32 R600_VS_CONSTANT200_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000720,
+};
+u32 R600_VS_CONSTANT201_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000724,
+};
+u32 R600_VS_CONSTANT202_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000728,
+};
+u32 R600_VS_CONSTANT203_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000072C,
+};
+u32 R600_VS_CONSTANT204_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000730,
+};
+u32 R600_VS_CONSTANT205_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000734,
+};
+u32 R600_VS_CONSTANT206_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000738,
+};
+u32 R600_VS_CONSTANT207_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000073C,
+};
+u32 R600_VS_CONSTANT208_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000740,
+};
+u32 R600_VS_CONSTANT209_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000744,
+};
+u32 R600_VS_CONSTANT210_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000748,
+};
+u32 R600_VS_CONSTANT211_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000074C,
+};
+u32 R600_VS_CONSTANT212_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000750,
+};
+u32 R600_VS_CONSTANT213_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000754,
+};
+u32 R600_VS_CONSTANT214_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000758,
+};
+u32 R600_VS_CONSTANT215_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000075C,
+};
+u32 R600_VS_CONSTANT216_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000760,
+};
+u32 R600_VS_CONSTANT217_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000764,
+};
+u32 R600_VS_CONSTANT218_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000768,
+};
+u32 R600_VS_CONSTANT219_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000076C,
+};
+u32 R600_VS_CONSTANT220_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000770,
+};
+u32 R600_VS_CONSTANT221_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000774,
+};
+u32 R600_VS_CONSTANT222_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000778,
+};
+u32 R600_VS_CONSTANT223_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000077C,
+};
+u32 R600_VS_CONSTANT224_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000780,
+};
+u32 R600_VS_CONSTANT225_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000784,
+};
+u32 R600_VS_CONSTANT226_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000788,
+};
+u32 R600_VS_CONSTANT227_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000078C,
+};
+u32 R600_VS_CONSTANT228_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000790,
+};
+u32 R600_VS_CONSTANT229_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000794,
+};
+u32 R600_VS_CONSTANT230_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x00000798,
+};
+u32 R600_VS_CONSTANT231_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x0000079C,
+};
+u32 R600_VS_CONSTANT232_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007A0,
+};
+u32 R600_VS_CONSTANT233_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007A4,
+};
+u32 R600_VS_CONSTANT234_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007A8,
+};
+u32 R600_VS_CONSTANT235_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007AC,
+};
+u32 R600_VS_CONSTANT236_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007B0,
+};
+u32 R600_VS_CONSTANT237_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007B4,
+};
+u32 R600_VS_CONSTANT238_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007B8,
+};
+u32 R600_VS_CONSTANT239_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007BC,
+};
+u32 R600_VS_CONSTANT240_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007C0,
+};
+u32 R600_VS_CONSTANT241_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007C4,
+};
+u32 R600_VS_CONSTANT242_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007C8,
+};
+u32 R600_VS_CONSTANT243_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007CC,
+};
+u32 R600_VS_CONSTANT244_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007D0,
+};
+u32 R600_VS_CONSTANT245_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007D4,
+};
+u32 R600_VS_CONSTANT246_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007D8,
+};
+u32 R600_VS_CONSTANT247_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007DC,
+};
+u32 R600_VS_CONSTANT248_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007E0,
+};
+u32 R600_VS_CONSTANT249_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007E4,
+};
+u32 R600_VS_CONSTANT250_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007E8,
+};
+u32 R600_VS_CONSTANT251_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007EC,
+};
+u32 R600_VS_CONSTANT252_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007F0,
+};
+u32 R600_VS_CONSTANT253_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007F4,
+};
+u32 R600_VS_CONSTANT254_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007F8,
+};
+u32 R600_VS_CONSTANT255_header_pm4[R600_CONSTANT_header_cpm4] = {
+	0xC0046A00,
+	0x000007FC,
+};
+#define R600_CONSTANT_state_cpm4 4
+u32 R600_CONSTANT_state_pm4[R600_CONSTANT_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+
+/* R600_RESOURCE */
+#define R600_RESOURCE_header_cpm4 2
+u32 R600_PS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000000,
+};
+u32 R600_PS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000007,
+};
+u32 R600_PS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000000E,
+};
+u32 R600_PS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000015,
+};
+u32 R600_PS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000001C,
+};
+u32 R600_PS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000023,
+};
+u32 R600_PS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000002A,
+};
+u32 R600_PS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000031,
+};
+u32 R600_PS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000038,
+};
+u32 R600_PS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000003F,
+};
+u32 R600_PS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000046,
+};
+u32 R600_PS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000004D,
+};
+u32 R600_PS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000054,
+};
+u32 R600_PS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000005B,
+};
+u32 R600_PS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000062,
+};
+u32 R600_PS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000069,
+};
+u32 R600_PS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000070,
+};
+u32 R600_PS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000077,
+};
+u32 R600_PS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000007E,
+};
+u32 R600_PS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000085,
+};
+u32 R600_PS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000008C,
+};
+u32 R600_PS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000093,
+};
+u32 R600_PS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000009A,
+};
+u32 R600_PS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000A1,
+};
+u32 R600_PS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000A8,
+};
+u32 R600_PS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000AF,
+};
+u32 R600_PS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000B6,
+};
+u32 R600_PS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000BD,
+};
+u32 R600_PS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000C4,
+};
+u32 R600_PS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000CB,
+};
+u32 R600_PS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000D2,
+};
+u32 R600_PS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000D9,
+};
+u32 R600_PS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000E0,
+};
+u32 R600_PS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000E7,
+};
+u32 R600_PS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000EE,
+};
+u32 R600_PS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000F5,
+};
+u32 R600_PS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000000FC,
+};
+u32 R600_PS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000103,
+};
+u32 R600_PS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000010A,
+};
+u32 R600_PS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000111,
+};
+u32 R600_PS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000118,
+};
+u32 R600_PS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000011F,
+};
+u32 R600_PS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000126,
+};
+u32 R600_PS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000012D,
+};
+u32 R600_PS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000134,
+};
+u32 R600_PS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000013B,
+};
+u32 R600_PS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000142,
+};
+u32 R600_PS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000149,
+};
+u32 R600_PS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000150,
+};
+u32 R600_PS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000157,
+};
+u32 R600_PS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000015E,
+};
+u32 R600_PS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000165,
+};
+u32 R600_PS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000016C,
+};
+u32 R600_PS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000173,
+};
+u32 R600_PS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000017A,
+};
+u32 R600_PS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000181,
+};
+u32 R600_PS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000188,
+};
+u32 R600_PS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000018F,
+};
+u32 R600_PS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000196,
+};
+u32 R600_PS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000019D,
+};
+u32 R600_PS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001A4,
+};
+u32 R600_PS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001AB,
+};
+u32 R600_PS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001B2,
+};
+u32 R600_PS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001B9,
+};
+u32 R600_PS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001C0,
+};
+u32 R600_PS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001C7,
+};
+u32 R600_PS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001CE,
+};
+u32 R600_PS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001D5,
+};
+u32 R600_PS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001DC,
+};
+u32 R600_PS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001E3,
+};
+u32 R600_PS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001EA,
+};
+u32 R600_PS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001F1,
+};
+u32 R600_PS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001F8,
+};
+u32 R600_PS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000001FF,
+};
+u32 R600_PS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000206,
+};
+u32 R600_PS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000020D,
+};
+u32 R600_PS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000214,
+};
+u32 R600_PS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000021B,
+};
+u32 R600_PS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000222,
+};
+u32 R600_PS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000229,
+};
+u32 R600_PS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000230,
+};
+u32 R600_PS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000237,
+};
+u32 R600_PS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000023E,
+};
+u32 R600_PS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000245,
+};
+u32 R600_PS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000024C,
+};
+u32 R600_PS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000253,
+};
+u32 R600_PS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000025A,
+};
+u32 R600_PS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000261,
+};
+u32 R600_PS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000268,
+};
+u32 R600_PS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000026F,
+};
+u32 R600_PS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000276,
+};
+u32 R600_PS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000027D,
+};
+u32 R600_PS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000284,
+};
+u32 R600_PS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000028B,
+};
+u32 R600_PS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000292,
+};
+u32 R600_PS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000299,
+};
+u32 R600_PS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002A0,
+};
+u32 R600_PS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002A7,
+};
+u32 R600_PS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002AE,
+};
+u32 R600_PS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002B5,
+};
+u32 R600_PS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002BC,
+};
+u32 R600_PS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002C3,
+};
+u32 R600_PS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002CA,
+};
+u32 R600_PS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002D1,
+};
+u32 R600_PS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002D8,
+};
+u32 R600_PS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002DF,
+};
+u32 R600_PS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002E6,
+};
+u32 R600_PS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002ED,
+};
+u32 R600_PS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002F4,
+};
+u32 R600_PS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000002FB,
+};
+u32 R600_PS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000302,
+};
+u32 R600_PS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000309,
+};
+u32 R600_PS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000310,
+};
+u32 R600_PS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000317,
+};
+u32 R600_PS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000031E,
+};
+u32 R600_PS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000325,
+};
+u32 R600_PS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000032C,
+};
+u32 R600_PS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000333,
+};
+u32 R600_PS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000033A,
+};
+u32 R600_PS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000341,
+};
+u32 R600_PS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000348,
+};
+u32 R600_PS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000034F,
+};
+u32 R600_PS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000356,
+};
+u32 R600_PS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000035D,
+};
+u32 R600_PS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000364,
+};
+u32 R600_PS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000036B,
+};
+u32 R600_PS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000372,
+};
+u32 R600_PS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000379,
+};
+u32 R600_PS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000380,
+};
+u32 R600_PS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000387,
+};
+u32 R600_PS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000038E,
+};
+u32 R600_PS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000395,
+};
+u32 R600_PS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000039C,
+};
+u32 R600_PS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003A3,
+};
+u32 R600_PS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003AA,
+};
+u32 R600_PS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003B1,
+};
+u32 R600_PS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003B8,
+};
+u32 R600_PS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003BF,
+};
+u32 R600_PS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003C6,
+};
+u32 R600_PS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003CD,
+};
+u32 R600_PS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003D4,
+};
+u32 R600_PS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003DB,
+};
+u32 R600_PS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003E2,
+};
+u32 R600_PS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003E9,
+};
+u32 R600_PS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003F0,
+};
+u32 R600_PS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003F7,
+};
+u32 R600_PS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000003FE,
+};
+u32 R600_PS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000405,
+};
+u32 R600_PS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000040C,
+};
+u32 R600_PS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000413,
+};
+u32 R600_PS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000041A,
+};
+u32 R600_PS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000421,
+};
+u32 R600_PS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000428,
+};
+u32 R600_PS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000042F,
+};
+u32 R600_PS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000436,
+};
+u32 R600_PS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000043D,
+};
+u32 R600_PS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000444,
+};
+u32 R600_PS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000044B,
+};
+u32 R600_PS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000452,
+};
+u32 R600_PS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000459,
+};
+u32 R600_VS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000460,
+};
+u32 R600_VS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000467,
+};
+u32 R600_VS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000046E,
+};
+u32 R600_VS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000475,
+};
+u32 R600_VS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000047C,
+};
+u32 R600_VS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000483,
+};
+u32 R600_VS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000048A,
+};
+u32 R600_VS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000491,
+};
+u32 R600_VS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000498,
+};
+u32 R600_VS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000049F,
+};
+u32 R600_VS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004A6,
+};
+u32 R600_VS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004AD,
+};
+u32 R600_VS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004B4,
+};
+u32 R600_VS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004BB,
+};
+u32 R600_VS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004C2,
+};
+u32 R600_VS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004C9,
+};
+u32 R600_VS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004D0,
+};
+u32 R600_VS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004D7,
+};
+u32 R600_VS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004DE,
+};
+u32 R600_VS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004E5,
+};
+u32 R600_VS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004EC,
+};
+u32 R600_VS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004F3,
+};
+u32 R600_VS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000004FA,
+};
+u32 R600_VS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000501,
+};
+u32 R600_VS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000508,
+};
+u32 R600_VS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000050F,
+};
+u32 R600_VS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000516,
+};
+u32 R600_VS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000051D,
+};
+u32 R600_VS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000524,
+};
+u32 R600_VS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000052B,
+};
+u32 R600_VS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000532,
+};
+u32 R600_VS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000539,
+};
+u32 R600_VS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000540,
+};
+u32 R600_VS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000547,
+};
+u32 R600_VS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000054E,
+};
+u32 R600_VS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000555,
+};
+u32 R600_VS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000055C,
+};
+u32 R600_VS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000563,
+};
+u32 R600_VS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000056A,
+};
+u32 R600_VS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000571,
+};
+u32 R600_VS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000578,
+};
+u32 R600_VS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000057F,
+};
+u32 R600_VS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000586,
+};
+u32 R600_VS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000058D,
+};
+u32 R600_VS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000594,
+};
+u32 R600_VS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000059B,
+};
+u32 R600_VS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005A2,
+};
+u32 R600_VS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005A9,
+};
+u32 R600_VS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005B0,
+};
+u32 R600_VS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005B7,
+};
+u32 R600_VS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005BE,
+};
+u32 R600_VS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005C5,
+};
+u32 R600_VS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005CC,
+};
+u32 R600_VS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005D3,
+};
+u32 R600_VS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005DA,
+};
+u32 R600_VS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005E1,
+};
+u32 R600_VS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005E8,
+};
+u32 R600_VS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005EF,
+};
+u32 R600_VS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005F6,
+};
+u32 R600_VS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000005FD,
+};
+u32 R600_VS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000604,
+};
+u32 R600_VS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000060B,
+};
+u32 R600_VS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000612,
+};
+u32 R600_VS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000619,
+};
+u32 R600_VS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000620,
+};
+u32 R600_VS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000627,
+};
+u32 R600_VS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000062E,
+};
+u32 R600_VS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000635,
+};
+u32 R600_VS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000063C,
+};
+u32 R600_VS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000643,
+};
+u32 R600_VS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000064A,
+};
+u32 R600_VS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000651,
+};
+u32 R600_VS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000658,
+};
+u32 R600_VS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000065F,
+};
+u32 R600_VS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000666,
+};
+u32 R600_VS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000066D,
+};
+u32 R600_VS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000674,
+};
+u32 R600_VS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000067B,
+};
+u32 R600_VS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000682,
+};
+u32 R600_VS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000689,
+};
+u32 R600_VS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000690,
+};
+u32 R600_VS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000697,
+};
+u32 R600_VS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000069E,
+};
+u32 R600_VS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006A5,
+};
+u32 R600_VS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006AC,
+};
+u32 R600_VS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006B3,
+};
+u32 R600_VS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006BA,
+};
+u32 R600_VS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006C1,
+};
+u32 R600_VS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006C8,
+};
+u32 R600_VS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006CF,
+};
+u32 R600_VS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006D6,
+};
+u32 R600_VS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006DD,
+};
+u32 R600_VS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006E4,
+};
+u32 R600_VS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006EB,
+};
+u32 R600_VS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006F2,
+};
+u32 R600_VS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000006F9,
+};
+u32 R600_VS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000700,
+};
+u32 R600_VS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000707,
+};
+u32 R600_VS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000070E,
+};
+u32 R600_VS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000715,
+};
+u32 R600_VS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000071C,
+};
+u32 R600_VS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000723,
+};
+u32 R600_VS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000072A,
+};
+u32 R600_VS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000731,
+};
+u32 R600_VS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000738,
+};
+u32 R600_VS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000073F,
+};
+u32 R600_VS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000746,
+};
+u32 R600_VS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000074D,
+};
+u32 R600_VS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000754,
+};
+u32 R600_VS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000075B,
+};
+u32 R600_VS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000762,
+};
+u32 R600_VS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000769,
+};
+u32 R600_VS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000770,
+};
+u32 R600_VS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000777,
+};
+u32 R600_VS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000077E,
+};
+u32 R600_VS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000785,
+};
+u32 R600_VS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000078C,
+};
+u32 R600_VS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000793,
+};
+u32 R600_VS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000079A,
+};
+u32 R600_VS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007A1,
+};
+u32 R600_VS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007A8,
+};
+u32 R600_VS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007AF,
+};
+u32 R600_VS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007B6,
+};
+u32 R600_VS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007BD,
+};
+u32 R600_VS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007C4,
+};
+u32 R600_VS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007CB,
+};
+u32 R600_VS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007D2,
+};
+u32 R600_VS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007D9,
+};
+u32 R600_VS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007E0,
+};
+u32 R600_VS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007E7,
+};
+u32 R600_VS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007EE,
+};
+u32 R600_VS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007F5,
+};
+u32 R600_VS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000007FC,
+};
+u32 R600_VS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000803,
+};
+u32 R600_VS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000080A,
+};
+u32 R600_VS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000811,
+};
+u32 R600_VS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000818,
+};
+u32 R600_VS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000081F,
+};
+u32 R600_VS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000826,
+};
+u32 R600_VS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000082D,
+};
+u32 R600_VS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000834,
+};
+u32 R600_VS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000083B,
+};
+u32 R600_VS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000842,
+};
+u32 R600_VS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000849,
+};
+u32 R600_VS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000850,
+};
+u32 R600_VS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000857,
+};
+u32 R600_VS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000085E,
+};
+u32 R600_VS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000865,
+};
+u32 R600_VS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000086C,
+};
+u32 R600_VS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000873,
+};
+u32 R600_VS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000087A,
+};
+u32 R600_VS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000881,
+};
+u32 R600_VS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000888,
+};
+u32 R600_VS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000088F,
+};
+u32 R600_VS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000896,
+};
+u32 R600_VS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000089D,
+};
+u32 R600_VS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008A4,
+};
+u32 R600_VS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008AB,
+};
+u32 R600_VS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008B2,
+};
+u32 R600_VS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008B9,
+};
+u32 R600_FS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008C0,
+};
+u32 R600_FS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008C7,
+};
+u32 R600_FS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008CE,
+};
+u32 R600_FS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008D5,
+};
+u32 R600_FS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008DC,
+};
+u32 R600_FS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008E3,
+};
+u32 R600_FS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008EA,
+};
+u32 R600_FS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008F1,
+};
+u32 R600_FS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008F8,
+};
+u32 R600_FS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000008FF,
+};
+u32 R600_FS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000906,
+};
+u32 R600_FS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000090D,
+};
+u32 R600_FS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000914,
+};
+u32 R600_FS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000091B,
+};
+u32 R600_FS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000922,
+};
+u32 R600_FS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000929,
+};
+u32 R600_GS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000930,
+};
+u32 R600_GS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000937,
+};
+u32 R600_GS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000093E,
+};
+u32 R600_GS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000945,
+};
+u32 R600_GS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000094C,
+};
+u32 R600_GS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000953,
+};
+u32 R600_GS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000095A,
+};
+u32 R600_GS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000961,
+};
+u32 R600_GS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000968,
+};
+u32 R600_GS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000096F,
+};
+u32 R600_GS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000976,
+};
+u32 R600_GS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000097D,
+};
+u32 R600_GS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000984,
+};
+u32 R600_GS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x0000098B,
+};
+u32 R600_GS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000992,
+};
+u32 R600_GS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000999,
+};
+u32 R600_GS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009A0,
+};
+u32 R600_GS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009A7,
+};
+u32 R600_GS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009AE,
+};
+u32 R600_GS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009B5,
+};
+u32 R600_GS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009BC,
+};
+u32 R600_GS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009C3,
+};
+u32 R600_GS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009CA,
+};
+u32 R600_GS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009D1,
+};
+u32 R600_GS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009D8,
+};
+u32 R600_GS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009DF,
+};
+u32 R600_GS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009E6,
+};
+u32 R600_GS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009ED,
+};
+u32 R600_GS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009F4,
+};
+u32 R600_GS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x000009FB,
+};
+u32 R600_GS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A02,
+};
+u32 R600_GS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A09,
+};
+u32 R600_GS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A10,
+};
+u32 R600_GS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A17,
+};
+u32 R600_GS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A1E,
+};
+u32 R600_GS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A25,
+};
+u32 R600_GS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A2C,
+};
+u32 R600_GS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A33,
+};
+u32 R600_GS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A3A,
+};
+u32 R600_GS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A41,
+};
+u32 R600_GS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A48,
+};
+u32 R600_GS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A4F,
+};
+u32 R600_GS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A56,
+};
+u32 R600_GS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A5D,
+};
+u32 R600_GS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A64,
+};
+u32 R600_GS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A6B,
+};
+u32 R600_GS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A72,
+};
+u32 R600_GS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A79,
+};
+u32 R600_GS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A80,
+};
+u32 R600_GS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A87,
+};
+u32 R600_GS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A8E,
+};
+u32 R600_GS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A95,
+};
+u32 R600_GS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000A9C,
+};
+u32 R600_GS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AA3,
+};
+u32 R600_GS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AAA,
+};
+u32 R600_GS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AB1,
+};
+u32 R600_GS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AB8,
+};
+u32 R600_GS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000ABF,
+};
+u32 R600_GS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AC6,
+};
+u32 R600_GS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000ACD,
+};
+u32 R600_GS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AD4,
+};
+u32 R600_GS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000ADB,
+};
+u32 R600_GS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AE2,
+};
+u32 R600_GS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AE9,
+};
+u32 R600_GS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AF0,
+};
+u32 R600_GS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AF7,
+};
+u32 R600_GS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000AFE,
+};
+u32 R600_GS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B05,
+};
+u32 R600_GS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B0C,
+};
+u32 R600_GS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B13,
+};
+u32 R600_GS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B1A,
+};
+u32 R600_GS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B21,
+};
+u32 R600_GS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B28,
+};
+u32 R600_GS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B2F,
+};
+u32 R600_GS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B36,
+};
+u32 R600_GS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B3D,
+};
+u32 R600_GS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B44,
+};
+u32 R600_GS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B4B,
+};
+u32 R600_GS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B52,
+};
+u32 R600_GS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B59,
+};
+u32 R600_GS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B60,
+};
+u32 R600_GS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B67,
+};
+u32 R600_GS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B6E,
+};
+u32 R600_GS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B75,
+};
+u32 R600_GS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B7C,
+};
+u32 R600_GS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B83,
+};
+u32 R600_GS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B8A,
+};
+u32 R600_GS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B91,
+};
+u32 R600_GS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B98,
+};
+u32 R600_GS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000B9F,
+};
+u32 R600_GS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BA6,
+};
+u32 R600_GS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BAD,
+};
+u32 R600_GS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BB4,
+};
+u32 R600_GS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BBB,
+};
+u32 R600_GS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BC2,
+};
+u32 R600_GS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BC9,
+};
+u32 R600_GS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BD0,
+};
+u32 R600_GS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BD7,
+};
+u32 R600_GS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BDE,
+};
+u32 R600_GS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BE5,
+};
+u32 R600_GS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BEC,
+};
+u32 R600_GS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BF3,
+};
+u32 R600_GS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000BFA,
+};
+u32 R600_GS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C01,
+};
+u32 R600_GS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C08,
+};
+u32 R600_GS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C0F,
+};
+u32 R600_GS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C16,
+};
+u32 R600_GS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C1D,
+};
+u32 R600_GS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C24,
+};
+u32 R600_GS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C2B,
+};
+u32 R600_GS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C32,
+};
+u32 R600_GS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C39,
+};
+u32 R600_GS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C40,
+};
+u32 R600_GS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C47,
+};
+u32 R600_GS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C4E,
+};
+u32 R600_GS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C55,
+};
+u32 R600_GS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C5C,
+};
+u32 R600_GS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C63,
+};
+u32 R600_GS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C6A,
+};
+u32 R600_GS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C71,
+};
+u32 R600_GS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C78,
+};
+u32 R600_GS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C7F,
+};
+u32 R600_GS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C86,
+};
+u32 R600_GS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C8D,
+};
+u32 R600_GS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C94,
+};
+u32 R600_GS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000C9B,
+};
+u32 R600_GS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CA2,
+};
+u32 R600_GS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CA9,
+};
+u32 R600_GS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CB0,
+};
+u32 R600_GS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CB7,
+};
+u32 R600_GS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CBE,
+};
+u32 R600_GS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CC5,
+};
+u32 R600_GS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CCC,
+};
+u32 R600_GS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CD3,
+};
+u32 R600_GS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CDA,
+};
+u32 R600_GS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CE1,
+};
+u32 R600_GS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CE8,
+};
+u32 R600_GS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CEF,
+};
+u32 R600_GS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CF6,
+};
+u32 R600_GS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000CFD,
+};
+u32 R600_GS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D04,
+};
+u32 R600_GS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D0B,
+};
+u32 R600_GS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D12,
+};
+u32 R600_GS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D19,
+};
+u32 R600_GS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D20,
+};
+u32 R600_GS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D27,
+};
+u32 R600_GS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D2E,
+};
+u32 R600_GS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D35,
+};
+u32 R600_GS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D3C,
+};
+u32 R600_GS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D43,
+};
+u32 R600_GS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D4A,
+};
+u32 R600_GS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D51,
+};
+u32 R600_GS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D58,
+};
+u32 R600_GS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D5F,
+};
+u32 R600_GS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D66,
+};
+u32 R600_GS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D6D,
+};
+u32 R600_GS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D74,
+};
+u32 R600_GS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D7B,
+};
+u32 R600_GS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D82,
+};
+u32 R600_GS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = {
+	0xC0076D00,
+	0x00000D89,
+};
+#define R600_RESOURCE_state_cpm4 11
+u32 R600_RESOURCE_state_pm4[R600_RESOURCE_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x80000000,
+	0xC0001000,
+	0x00000000,
+	0xC0001000,
+	0x00000000,
+};
+
+/* R600_SAMPLER */
+#define R600_SAMPLER_header_cpm4 2
+u32 R600_PS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000000,
+};
+u32 R600_PS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000003,
+};
+u32 R600_PS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000006,
+};
+u32 R600_PS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000009,
+};
+u32 R600_PS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000000C,
+};
+u32 R600_PS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000000F,
+};
+u32 R600_PS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000012,
+};
+u32 R600_PS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000015,
+};
+u32 R600_PS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000018,
+};
+u32 R600_PS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000001B,
+};
+u32 R600_PS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000001E,
+};
+u32 R600_PS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000021,
+};
+u32 R600_PS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000024,
+};
+u32 R600_PS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000027,
+};
+u32 R600_PS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000002A,
+};
+u32 R600_PS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000002D,
+};
+u32 R600_PS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000030,
+};
+u32 R600_PS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000033,
+};
+u32 R600_VS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000036,
+};
+u32 R600_VS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000039,
+};
+u32 R600_VS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000003C,
+};
+u32 R600_VS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000003F,
+};
+u32 R600_VS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000042,
+};
+u32 R600_VS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000045,
+};
+u32 R600_VS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000048,
+};
+u32 R600_VS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000004B,
+};
+u32 R600_VS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000004E,
+};
+u32 R600_VS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000051,
+};
+u32 R600_VS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000054,
+};
+u32 R600_VS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000057,
+};
+u32 R600_VS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000005A,
+};
+u32 R600_VS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000005D,
+};
+u32 R600_VS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000060,
+};
+u32 R600_VS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000063,
+};
+u32 R600_VS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000066,
+};
+u32 R600_VS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000069,
+};
+u32 R600_GS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000006C,
+};
+u32 R600_GS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000006F,
+};
+u32 R600_GS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000072,
+};
+u32 R600_GS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000075,
+};
+u32 R600_GS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000078,
+};
+u32 R600_GS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000007B,
+};
+u32 R600_GS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000007E,
+};
+u32 R600_GS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000081,
+};
+u32 R600_GS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000084,
+};
+u32 R600_GS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000087,
+};
+u32 R600_GS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000008A,
+};
+u32 R600_GS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000008D,
+};
+u32 R600_GS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000090,
+};
+u32 R600_GS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000093,
+};
+u32 R600_GS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000096,
+};
+u32 R600_GS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x00000099,
+};
+u32 R600_GS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000009C,
+};
+u32 R600_GS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = {
+	0xC0036E00,
+	0x0000009F,
+};
+#define R600_SAMPLER_state_cpm4 3
+u32 R600_SAMPLER_state_pm4[R600_SAMPLER_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+/* R600_SAMPLER_BORDER */
+#define R600_SAMPLER_BORDER_header_cpm4 2
+u32 R600_PS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000900,
+};
+u32 R600_PS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000904,
+};
+u32 R600_PS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000908,
+};
+u32 R600_PS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x0000090C,
+};
+u32 R600_PS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000910,
+};
+u32 R600_PS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000914,
+};
+u32 R600_PS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000918,
+};
+u32 R600_PS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x0000091C,
+};
+u32 R600_PS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000920,
+};
+u32 R600_PS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000924,
+};
+u32 R600_PS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000928,
+};
+u32 R600_PS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x0000092C,
+};
+u32 R600_PS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000930,
+};
+u32 R600_PS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000934,
+};
+u32 R600_PS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000938,
+};
+u32 R600_PS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x0000093C,
+};
+u32 R600_PS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000940,
+};
+u32 R600_PS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000944,
+};
+u32 R600_VS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000980,
+};
+u32 R600_VS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000984,
+};
+u32 R600_VS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000988,
+};
+u32 R600_VS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x0000098C,
+};
+u32 R600_VS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000990,
+};
+u32 R600_VS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000994,
+};
+u32 R600_VS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000998,
+};
+u32 R600_VS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x0000099C,
+};
+u32 R600_VS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009A0,
+};
+u32 R600_VS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009A4,
+};
+u32 R600_VS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009A8,
+};
+u32 R600_VS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009AC,
+};
+u32 R600_VS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009B0,
+};
+u32 R600_VS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009B4,
+};
+u32 R600_VS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009B8,
+};
+u32 R600_VS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009BC,
+};
+u32 R600_VS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009C0,
+};
+u32 R600_VS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x000009C4,
+};
+u32 R600_GS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A00,
+};
+u32 R600_GS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A04,
+};
+u32 R600_GS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A08,
+};
+u32 R600_GS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A0C,
+};
+u32 R600_GS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A10,
+};
+u32 R600_GS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A14,
+};
+u32 R600_GS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A18,
+};
+u32 R600_GS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A1C,
+};
+u32 R600_GS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A20,
+};
+u32 R600_GS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A24,
+};
+u32 R600_GS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A28,
+};
+u32 R600_GS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A2C,
+};
+u32 R600_GS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A30,
+};
+u32 R600_GS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A34,
+};
+u32 R600_GS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A38,
+};
+u32 R600_GS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A3C,
+};
+u32 R600_GS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A40,
+};
+u32 R600_GS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
+	0xC0046800,
+	0x00000A44,
+};
+#define R600_SAMPLER_BORDER_state_cpm4 4
+u32 R600_SAMPLER_BORDER_state_pm4[R600_SAMPLER_BORDER_state_cpm4] = {
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+};
+
+static const struct radeon_type R600_types[] = {
+	{R600_CONFIG_header_pm4, R600_CONFIG_header_cpm4, R600_CONFIG_state_pm4, R600_CONFIG_state_cpm4, 0, 0},
+	{R600_CB_CNTL_header_pm4, R600_CB_CNTL_header_cpm4, R600_CB_CNTL_state_pm4, R600_CB_CNTL_state_cpm4, 0, 0},
+	{R600_RASTERIZER_header_pm4, R600_RASTERIZER_header_cpm4, R600_RASTERIZER_state_pm4, R600_RASTERIZER_state_cpm4, 0, 0},
+	{R600_VIEWPORT_header_pm4, R600_VIEWPORT_header_cpm4, R600_VIEWPORT_state_pm4, R600_VIEWPORT_state_cpm4, 0, 0},
+	{R600_SCISSOR_header_pm4, R600_SCISSOR_header_cpm4, R600_SCISSOR_state_pm4, R600_SCISSOR_state_cpm4, 0, 0},
+	{R600_BLEND_header_pm4, R600_BLEND_header_cpm4, R600_BLEND_state_pm4, R600_BLEND_state_cpm4, 0, 0},
+	{R600_DSA_header_pm4, R600_DSA_header_cpm4, R600_DSA_state_pm4, R600_DSA_state_cpm4, 0, 0},
+	{R600_VGT_header_pm4, R600_VGT_header_cpm4, R600_VGT_state_pm4, R600_VGT_state_cpm4, 0, 0},
+	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
+	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
+	{R600_VS_SHADER_header_pm4, R600_VS_SHADER_header_cpm4, R600_VS_SHADER_state_pm4, R600_VS_SHADER_state_cpm4, 0, 0},
+	{R600_PS_SHADER_header_pm4, R600_PS_SHADER_header_cpm4, R600_PS_SHADER_state_pm4, R600_PS_SHADER_state_cpm4, 0, 0},
+	{R600_DB_header_pm4, R600_DB_header_cpm4, R600_DB_state_pm4, R600_DB_state_cpm4, R600_FLUSH_DB, R600_DIRTY_ALL},
+	{R600_CB0_header_pm4, R600_CB0_header_cpm4, R600_CB0_state_pm4, R600_CB0_state_cpm4, R600_FLUSH_CB0, R600_DIRTY_ALL},
+	{R600_CB1_header_pm4, R600_CB1_header_cpm4, R600_CB1_state_pm4, R600_CB1_state_cpm4, R600_FLUSH_CB1, R600_DIRTY_ALL},
+	{R600_CB2_header_pm4, R600_CB2_header_cpm4, R600_CB2_state_pm4, R600_CB2_state_cpm4, R600_FLUSH_CB2, R600_DIRTY_ALL},
+	{R600_CB3_header_pm4, R600_CB3_header_cpm4, R600_CB3_state_pm4, R600_CB3_state_cpm4, R600_FLUSH_CB3, R600_DIRTY_ALL},
+	{R600_CB4_header_pm4, R600_CB4_header_cpm4, R600_CB4_state_pm4, R600_CB4_state_cpm4, R600_FLUSH_CB4, R600_DIRTY_ALL},
+	{R600_CB5_header_pm4, R600_CB5_header_cpm4, R600_CB5_state_pm4, R600_CB5_state_cpm4, R600_FLUSH_CB5, R600_DIRTY_ALL},
+	{R600_CB6_header_pm4, R600_CB6_header_cpm4, R600_CB6_state_pm4, R600_CB6_state_cpm4, R600_FLUSH_CB6, R600_DIRTY_ALL},
+	{R600_CB7_header_pm4, R600_CB7_header_cpm4, R600_CB7_state_pm4, R600_CB7_state_cpm4, R600_FLUSH_CB7, R600_DIRTY_ALL},
+	{R600_UCP0_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP1_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP2_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP3_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP4_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP5_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_PS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_DRAW_AUTO_header_pm4, R600_DRAW_AUTO_header_cpm4, R600_DRAW_AUTO_state_pm4, R600_DRAW_AUTO_state_cpm4, 0, 0},
+	{R600_DRAW_header_pm4, R600_DRAW_header_cpm4, R600_DRAW_state_pm4, R600_DRAW_state_cpm4, 0, 0}
+};
+
+static const struct radeon_type R700_types[] = {
+	{R700_CONFIG_header_pm4, R700_CONFIG_header_cpm4, R600_CONFIG_state_pm4, R600_CONFIG_state_cpm4, 0, 0},
+	{R600_CB_CNTL_header_pm4, R600_CB_CNTL_header_cpm4, R600_CB_CNTL_state_pm4, R600_CB_CNTL_state_cpm4, 0, 0},
+	{R600_RASTERIZER_header_pm4, R600_RASTERIZER_header_cpm4, R600_RASTERIZER_state_pm4, R600_RASTERIZER_state_cpm4, 0, 0},
+	{R600_VIEWPORT_header_pm4, R600_VIEWPORT_header_cpm4, R600_VIEWPORT_state_pm4, R600_VIEWPORT_state_cpm4, 0, 0},
+	{R600_SCISSOR_header_pm4, R600_SCISSOR_header_cpm4, R600_SCISSOR_state_pm4, R600_SCISSOR_state_cpm4, 0, 0},
+	{R600_BLEND_header_pm4, R600_BLEND_header_cpm4, R600_BLEND_state_pm4, R600_BLEND_state_cpm4, 0, 0},
+	{R600_DSA_header_pm4, R600_DSA_header_cpm4, R600_DSA_state_pm4, R600_DSA_state_cpm4, 0, 0},
+	{R600_VGT_header_pm4, R600_VGT_header_cpm4, R600_VGT_state_pm4, R600_VGT_state_cpm4, 0, 0},
+	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
+	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
+	{R600_VS_SHADER_header_pm4, R600_VS_SHADER_header_cpm4, R600_VS_SHADER_state_pm4, R600_VS_SHADER_state_cpm4, 0, 0},
+	{R600_PS_SHADER_header_pm4, R600_PS_SHADER_header_cpm4, R600_PS_SHADER_state_pm4, R600_PS_SHADER_state_cpm4, 0, 0},
+	{R600_DB_header_pm4, R600_DB_header_cpm4, R600_DB_state_pm4, R600_DB_state_cpm4, R600_FLUSH_DB, R600_DIRTY_ALL},
+	{R600_CB0_header_pm4, R600_CB0_header_cpm4, R600_CB0_state_pm4, R600_CB0_state_cpm4, R600_FLUSH_CB0, R600_DIRTY_ALL},
+	{R600_CB1_header_pm4, R600_CB1_header_cpm4, R600_CB1_state_pm4, R600_CB1_state_cpm4, R600_FLUSH_CB1, R600_DIRTY_ALL},
+	{R600_CB2_header_pm4, R600_CB2_header_cpm4, R600_CB2_state_pm4, R600_CB2_state_cpm4, R600_FLUSH_CB2, R600_DIRTY_ALL},
+	{R600_CB3_header_pm4, R600_CB3_header_cpm4, R600_CB3_state_pm4, R600_CB3_state_cpm4, R600_FLUSH_CB3, R600_DIRTY_ALL},
+	{R600_CB4_header_pm4, R600_CB4_header_cpm4, R600_CB4_state_pm4, R600_CB4_state_cpm4, R600_FLUSH_CB4, R600_DIRTY_ALL},
+	{R600_CB5_header_pm4, R600_CB5_header_cpm4, R600_CB5_state_pm4, R600_CB5_state_cpm4, R600_FLUSH_CB5, R600_DIRTY_ALL},
+	{R600_CB6_header_pm4, R600_CB6_header_cpm4, R600_CB6_state_pm4, R600_CB6_state_cpm4, R600_FLUSH_CB6, R600_DIRTY_ALL},
+	{R600_CB7_header_pm4, R600_CB7_header_cpm4, R600_CB7_state_pm4, R600_CB7_state_cpm4, R600_FLUSH_CB7, R600_DIRTY_ALL},
+	{R600_UCP0_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP1_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP2_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP3_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP4_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_UCP5_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
+	{R600_PS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_VS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_FS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_GS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
+	{R600_PS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_VS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_PS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_VS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_GS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
+	{R600_DRAW_AUTO_header_pm4, R600_DRAW_AUTO_header_cpm4, R600_DRAW_AUTO_state_pm4, R600_DRAW_AUTO_state_cpm4, 0, 0},
+	{R600_DRAW_header_pm4, R600_DRAW_header_cpm4, R600_DRAW_state_pm4, R600_DRAW_state_cpm4, 0, 0}
+};
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
deleted file mode 100644
index b5365e4275..0000000000
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ /dev/null
@@ -1,562 +0,0 @@
-/*
- * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-#ifndef R600_STATES_H
-#define R600_STATES_H
-
-static const struct radeon_register R600_CONFIG_names[] = {
-	{0x00008C00, 0, 0, "SQ_CONFIG"},
-	{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
-	{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
-	{0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"},
-	{0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
-	{0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
-	{0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
-	{0x00009508, 0, 0, "TA_CNTL_AUX"},
-	{0x00009714, 0, 0, "VC_ENHANCE"},
-	{0x00009830, 0, 0, "DB_DEBUG"},
-	{0x00009838, 0, 0, "DB_WATERMARKS"},
-	{0x00028350, 0, 0, "SX_MISC"},
-	{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
-	{0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
-	{0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
-	{0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
-	{0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
-	{0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
-	{0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
-	{0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
-	{0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"},
-	{0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"},
-	{0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
-	{0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
-	{0x00028A14, 0, 0, "VGT_HOS_CNTL"},
-	{0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
-	{0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
-	{0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
-	{0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
-	{0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
-	{0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
-	{0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
-	{0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
-	{0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
-	{0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
-	{0x00028A40, 0, 0, "VGT_GS_MODE"},
-	{0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"},
-	{0x00028AB0, 0, 0, "VGT_STRMOUT_EN"},
-	{0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
-	{0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
-	{0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
-};
-
-static const struct radeon_register R600_CB_CNTL_names[] = {
-	{0x00028120, 0, 0, "CB_CLEAR_RED"},
-	{0x00028124, 0, 0, "CB_CLEAR_GREEN"},
-	{0x00028128, 0, 0, "CB_CLEAR_BLUE"},
-	{0x0002812C, 0, 0, "CB_CLEAR_ALPHA"},
-	{0x0002823C, 0, 0, "CB_SHADER_MASK"},
-	{0x00028238, 0, 0, "CB_TARGET_MASK"},
-	{0x00028424, 0, 0, "CB_FOG_RED"},
-	{0x00028428, 0, 0, "CB_FOG_GREEN"},
-	{0x0002842C, 0, 0, "CB_FOG_BLUE"},
-	{0x00028808, 0, 0, "CB_COLOR_CONTROL"},
-	{0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
-	{0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
-	{0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"},
-	{0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"},
-	{0x00028C34, 0, 0, "CB_CLRCMP_SRC"},
-	{0x00028C38, 0, 0, "CB_CLRCMP_DST"},
-	{0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
-	{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
-};
-
-static const struct radeon_register R600_RASTERIZER_names[] = {
-	{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
-	{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
-	{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
-	{0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
-	{0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
-	{0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
-	{0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
-	{0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
-	{0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"},
-	{0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
-	{0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
-	{0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
-	{0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
-	{0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
-	{0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
-	{0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
-	{0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
-	{0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
-	{0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
-	{0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
-	{0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
-};
-
-static const struct radeon_register R600_VIEWPORT_names[] = {
-	{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
-	{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
-	{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
-	{0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
-	{0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
-	{0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
-	{0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
-	{0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
-	{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
-};
-
-static const struct radeon_register R600_SCISSOR_names[] = {
-	{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
-	{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
-	{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
-	{0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
-	{0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
-	{0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
-	{0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
-	{0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
-	{0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
-	{0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
-	{0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
-	{0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
-	{0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
-	{0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
-	{0x00028230, 0, 0, "PA_SC_EDGERULE"},
-	{0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
-	{0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
-	{0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
-	{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
-};
-
-static const struct radeon_register R600_BLEND_names[] = {
-	{0x00028414, 0, 0, "CB_BLEND_RED"},
-	{0x00028418, 0, 0, "CB_BLEND_GREEN"},
-	{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
-	{0x00028420, 0, 0, "CB_BLEND_ALPHA"},
-	{0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
-	{0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
-	{0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
-	{0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
-	{0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
-	{0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
-	{0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
-	{0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
-	{0x00028804, 0, 0, "CB_BLEND_CONTROL"},
-};
-
-static const struct radeon_register R600_DSA_names[] = {
-	{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
-	{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
-	{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
-	{0x00028430, 0, 0, "DB_STENCILREFMASK"},
-	{0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
-	{0x00028438, 0, 0, "SX_ALPHA_REF"},
-	{0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"},
-	{0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"},
-	{0x000286DC, 0, 0, "SPI_FOG_CNTL"},
-	{0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
-	{0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
-	{0x00028D0C, 0, 0, "DB_RENDER_CONTROL"},
-	{0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"},
-	{0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
-	{0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"},
-	{0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
-};
-
-static const struct radeon_register R600_VS_SHADER_names[] = {
-	{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
-	{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
-	{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
-	{0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
-	{0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
-	{0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
-	{0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
-	{0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
-	{0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
-	{0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
-	{0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
-	{0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
-	{0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
-	{0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
-	{0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
-	{0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
-	{0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
-	{0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
-	{0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
-	{0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
-	{0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
-	{0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
-	{0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
-	{0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
-	{0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
-	{0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
-	{0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
-	{0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
-	{0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
-	{0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
-	{0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
-	{0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
-	{0x00028614, 0, 0, "SPI_VS_OUT_ID_0"},
-	{0x00028618, 0, 0, "SPI_VS_OUT_ID_1"},
-	{0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"},
-	{0x00028620, 0, 0, "SPI_VS_OUT_ID_3"},
-	{0x00028624, 0, 0, "SPI_VS_OUT_ID_4"},
-	{0x00028628, 0, 0, "SPI_VS_OUT_ID_5"},
-	{0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"},
-	{0x00028630, 0, 0, "SPI_VS_OUT_ID_7"},
-	{0x00028634, 0, 0, "SPI_VS_OUT_ID_8"},
-	{0x00028638, 0, 0, "SPI_VS_OUT_ID_9"},
-	{0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
-	{0x00028858, 1, 0, "SQ_PGM_START_VS"},
-	{0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"},
-	{0x00028894, 1, 1, "SQ_PGM_START_FS"},
-	{0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"},
-	{0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"},
-	{0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
-};
-
-static const struct radeon_register R600_PS_SHADER_names[] = {
-	{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
-	{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
-	{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
-	{0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
-	{0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
-	{0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
-	{0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
-	{0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
-	{0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
-	{0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
-	{0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
-	{0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
-	{0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
-	{0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
-	{0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
-	{0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
-	{0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
-	{0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
-	{0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
-	{0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
-	{0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
-	{0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
-	{0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
-	{0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
-	{0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
-	{0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
-	{0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
-	{0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
-	{0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
-	{0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
-	{0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
-	{0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
-	{0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
-	{0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
-	{0x000286D8, 0, 0, "SPI_INPUT_Z"},
-	{0x00028840, 1, 0, "SQ_PGM_START_PS"},
-	{0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"},
-	{0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"},
-	{0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
-};
-
-static const struct radeon_register R600_PS_CONSTANT_names[] = {
-	{0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
-	{0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
-	{0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
-	{0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
-};
-
-static const struct radeon_register R600_VS_CONSTANT_names[] = {
-	{0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
-	{0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
-	{0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
-	{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
-};
-
-static const struct radeon_register R600_UCP_names[] = {
-	{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
-	{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
-	{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
-	{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
-};
-
-static const struct radeon_register R600_PS_RESOURCE_names[] = {
-	{0x00038000, 0, 0, "RESOURCE0_WORD0"},
-	{0x00038004, 0, 0, "RESOURCE0_WORD1"},
-	{0x00038008, 0, 0, "RESOURCE0_WORD2"},
-	{0x0003800C, 0, 0, "RESOURCE0_WORD3"},
-	{0x00038010, 0, 0, "RESOURCE0_WORD4"},
-	{0x00038014, 0, 0, "RESOURCE0_WORD5"},
-	{0x00038018, 0, 0, "RESOURCE0_WORD6"},
-};
-
-static const struct radeon_register R600_VS_RESOURCE_names[] = {
-	{0x00039180, 0, 0, "RESOURCE160_WORD0"},
-	{0x00039184, 0, 0, "RESOURCE160_WORD1"},
-	{0x00039188, 0, 0, "RESOURCE160_WORD2"},
-	{0x0003918C, 0, 0, "RESOURCE160_WORD3"},
-	{0x00039190, 0, 0, "RESOURCE160_WORD4"},
-	{0x00039194, 0, 0, "RESOURCE160_WORD5"},
-	{0x00039198, 0, 0, "RESOURCE160_WORD6"},
-};
-
-static const struct radeon_register R600_FS_RESOURCE_names[] = {
-	{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
-	{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
-	{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
-	{0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
-	{0x0003A310, 0, 0, "RESOURCE320_WORD4"},
-	{0x0003A314, 0, 0, "RESOURCE320_WORD5"},
-	{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
-};
-
-static const struct radeon_register R600_GS_RESOURCE_names[] = {
-	{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
-	{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
-	{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
-	{0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
-	{0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
-	{0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
-	{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
-};
-
-static const struct radeon_register R600_PS_SAMPLER_names[] = {
-	{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
-	{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
-	{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
-};
-
-static const struct radeon_register R600_VS_SAMPLER_names[] = {
-	{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
-	{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
-	{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
-};
-
-static const struct radeon_register R600_GS_SAMPLER_names[] = {
-	{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
-	{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
-	{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
-};
-
-static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = {
-	{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
-	{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = {
-	{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
-	{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = {
-	{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
-	{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register R600_CB0_names[] = {
-	{0x00028040, 1, 0, "CB_COLOR0_BASE"},
-	{0x000280A0, 0, 0, "CB_COLOR0_INFO"},
-	{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
-	{0x00028080, 0, 0, "CB_COLOR0_VIEW"},
-	{0x000280E0, 1, 1, "CB_COLOR0_FRAG"},
-	{0x000280C0, 1, 2, "CB_COLOR0_TILE"},
-	{0x00028100, 0, 0, "CB_COLOR0_MASK"},
-};
-
-static const struct radeon_register R600_CB1_names[] = {
-	{0x00028044, 1, 0, "CB_COLOR1_BASE"},
-	{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
-	{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
-	{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
-	{0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
-	{0x000280C4, 1, 2, "CB_COLOR1_TILE"},
-	{0x00028104, 0, 0, "CB_COLOR1_MASK"},
-};
-
-static const struct radeon_register R600_CB2_names[] = {
-	{0x00028048, 1, 0, "CB_COLOR2_BASE"},
-	{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
-	{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
-	{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
-	{0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
-	{0x000280C8, 1, 2, "CB_COLOR2_TILE"},
-	{0x00028108, 0, 0, "CB_COLOR2_MASK"},
-};
-
-static const struct radeon_register R600_CB3_names[] = {
-	{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
-	{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
-	{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
-	{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
-	{0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
-	{0x000280CC, 1, 2, "CB_COLOR3_TILE"},
-	{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
-};
-
-static const struct radeon_register R600_CB4_names[] = {
-	{0x00028050, 1, 0, "CB_COLOR4_BASE"},
-	{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
-	{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
-	{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
-	{0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
-	{0x000280D0, 1, 2, "CB_COLOR4_TILE"},
-	{0x00028110, 0, 0, "CB_COLOR4_MASK"},
-};
-
-static const struct radeon_register R600_CB5_names[] = {
-	{0x00028054, 1, 0, "CB_COLOR5_BASE"},
-	{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
-	{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
-	{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
-	{0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
-	{0x000280D4, 1, 2, "CB_COLOR5_TILE"},
-	{0x00028114, 0, 0, "CB_COLOR5_MASK"},
-};
-
-static const struct radeon_register R600_CB6_names[] = {
-	{0x00028058, 1, 0, "CB_COLOR6_BASE"},
-	{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
-	{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
-	{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
-	{0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
-	{0x000280D8, 1, 2, "CB_COLOR6_TILE"},
-	{0x00028118, 0, 0, "CB_COLOR6_MASK"},
-};
-
-static const struct radeon_register R600_CB7_names[] = {
-	{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
-	{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
-	{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
-	{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
-	{0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
-	{0x000280DC, 1, 2, "CB_COLOR7_TILE"},
-	{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
-};
-
-static const struct radeon_register R600_DB_names[] = {
-	{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
-	{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
-	{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
-	{0x00028010, 0, 0, "DB_DEPTH_INFO"},
-	{0x00028D24, 0, 0, "DB_HTILE_SURFACE"},
-	{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
-};
-
-static const struct radeon_register R600_VGT_names[] = {
-	{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
-	{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
-	{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
-	{0x00028408, 0, 0, "VGT_INDX_OFFSET"},
-	{0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"},
-	{0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"},
-	{0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"},
-	{0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"},
-	{0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"},
-	{0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"},
-	{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
-};
-
-static const struct radeon_register R600_DRAW_names[] = {
-	{0x00008970, 0, 0, "VGT_NUM_INDICES"},
-	{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},
-	{0x000287E8, 1, 0, "VGT_DMA_BASE"},
-	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
-};
-
-static const struct radeon_register R600_VGT_EVENT_names[] = {
-	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
-};
-
-static struct radeon_type R600_types[] = {
-	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
-	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
-	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
-	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
-	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
-	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
-	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
-	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
-	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
-	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
-	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
-	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
-	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
-	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
-	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
-	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
-	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
-	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
-	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
-	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
-	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
-	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
-	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
-	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
-	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
-	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
-	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
-	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
-	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-};
-
-static struct radeon_type R700_types[] = {
-	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names},
-	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
-	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
-	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
-	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
-	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
-	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
-	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
-	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
-	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
-	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
-	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
-	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
-	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
-	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
-	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
-	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
-	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
-	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
-	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
-	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
-	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
-	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
-	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
-	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
-	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
-	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
-	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
-	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-};
-
-#endif
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 80b0a1d397..2b16e3ce88 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -153,47 +153,3 @@ struct radeon *radeon_decref(struct radeon *radeon)
 	free(radeon);
 	return NULL;
 }
-
-int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id)
-{
-	unsigned i, j;
-
-	for (i = 0; i < radeon->ntype; i++) {
-		if (radeon->type[i].range_start) {
-			if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) {
-				*typeid = i;
-				j = offset - radeon->type[i].range_start;
-				j /= radeon->type[i].stride;
-				*stateid = radeon->type[i].id + j;
-				*id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4;
-				return 0;
-			}
-		} else {
-			for (j = 0; j < radeon->type[i].nstates; j++) {
-				if (radeon->type[i].regs[j].offset == offset) {
-					*typeid = i;
-					*stateid = radeon->type[i].id;
-					*id = j;
-					return 0;
-				}
-			}
-		}
-	}
-	fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset);
-	return -EINVAL;
-}
-
-unsigned radeon_type_from_id(struct radeon *radeon, unsigned id)
-{
-	unsigned i;
-
-	for (i = 0; i < radeon->ntype - 1; i++) {
-		if (radeon->type[i].id == id)
-			return i;
-		if (id > radeon->type[i].id && id < radeon->type[i + 1].id)
-			return i;
-	}
-	if (radeon->type[i].id == id)
-		return i;
-	return -1;
-}
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index bd050c4cf9..b8ba9b552d 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -26,54 +26,40 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <unistd.h>
 #include "radeon_priv.h"
 #include "radeon_drm.h"
 #include "bof.h"
 
-int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo)
+static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo, unsigned state_id)
 {
-	void *ptr;
-
-	ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1));
-	if (ptr == NULL) {
-		return -ENOMEM;
-	}
-	ctx->bo = ptr;
-	ctx->bo[ctx->nbo] = bo;
+	ctx->bo[ctx->nbo].bo = bo;
+	ctx->bo[ctx->nbo].bo_flushed = 0;
+	ctx->bo[ctx->nbo].state_id = state_id;
 	ctx->nbo++;
 	return 0;
 }
 
-struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc)
+void radeon_ctx_clear(struct radeon_ctx *ctx)
 {
-	struct radeon_cs_reloc *greloc;
 	unsigned i;
 
-	greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4);
-	for (i = 0; i < ctx->nbo; i++) {
-		if (ctx->bo[i]->handle == greloc->handle) {
-			return radeon_bo_incref(ctx->radeon, ctx->bo[i]);
-		}
+	/* FIXME somethings is wrong, it should be safe to
+	 * delete bo here, kernel should postpone bo deletion
+	 * until bo is no longer referenced by cs (through the
+	 * fence association)
+	 */
+	for (i = 0; i < 50; i++) {
+		usleep(10);
 	}
-	fprintf(stderr, "%s no bo for reloc[%d 0x%08X] %d\n", __func__, reloc, greloc->handle, ctx->nbo);
-	return NULL;
-}
-
-void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement)
-{
-	struct radeon_cs_reloc *greloc;
-	unsigned i;
-
-	placement[0] = 0;
-	placement[1] = 0;
-	greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4);
 	for (i = 0; i < ctx->nbo; i++) {
-		if (ctx->bo[i]->handle == greloc->handle) {
-			placement[0] = greloc->read_domain | greloc->write_domain;
-			placement[1] = placement[0];
-			return;
-		}
+		ctx->bo[i].bo = radeon_bo_decref(ctx->radeon, ctx->bo[i].bo);
 	}
+	ctx->id = 0;
+	ctx->npm4 = RADEON_CTX_MAX_PM4;
+	ctx->nreloc = 0;
+	ctx->nbo = 0;
+	memset(ctx->state_crc32, 0, ctx->radeon->nstate * 4);
 }
 
 struct radeon_ctx *radeon_ctx(struct radeon *radeon)
@@ -86,6 +72,25 @@ struct radeon_ctx *radeon_ctx(struct radeon *radeon)
 	if (ctx == NULL)
 		return NULL;
 	ctx->radeon = radeon_incref(radeon);
+	ctx->max_bo = 4096;
+	ctx->max_reloc = 4096;
+	ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4);
+	if (ctx->pm4 == NULL) {
+		return radeon_ctx_decref(ctx);
+	}
+	ctx->state_crc32 = malloc(ctx->radeon->nstate * 4);
+	if (ctx->state_crc32 == NULL) {
+		return radeon_ctx_decref(ctx);
+	}
+	ctx->bo = malloc(ctx->max_bo * sizeof(struct radeon_ctx_bo));
+	if (ctx->bo == NULL) {
+		return radeon_ctx_decref(ctx);
+	}
+	ctx->reloc = malloc(ctx->max_reloc * sizeof(struct radeon_cs_reloc));
+	if (ctx->reloc == NULL) {
+		return radeon_ctx_decref(ctx);
+	}
+	radeon_ctx_clear(ctx);
 	return ctx;
 }
 
@@ -97,31 +102,33 @@ struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx)
 
 struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
 {
-	unsigned i;
-
 	if (ctx == NULL)
 		return NULL;
 	if (--ctx->refcount > 0) {
 		return NULL;
 	}
 
-	for (i = 0; i < ctx->ndraw; i++) {
-		ctx->draw[i] = radeon_draw_decref(ctx->draw[i]);
-	}
-	for (i = 0; i < ctx->nbo; i++) {
-		ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
-	}
 	ctx->radeon = radeon_decref(ctx->radeon);
-	free(ctx->state);
-	free(ctx->draw);
 	free(ctx->bo);
 	free(ctx->pm4);
 	free(ctx->reloc);
+	free(ctx->state_crc32);
 	memset(ctx, 0, sizeof(*ctx));
 	free(ctx);
 	return NULL;
 }
 
+static int radeon_ctx_bo_id(struct radeon_ctx *ctx, struct radeon_bo *bo)
+{
+	unsigned i;
+
+	for (i = 0; i < ctx->nbo; i++) {
+		if (bo == ctx->bo[i].bo)
+			return i;
+	}
+	return -1;
+}
+
 static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
 {
 	unsigned i, j;
@@ -131,12 +138,15 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
 		return 0;
 	for (i = 0; i < state->nbo; i++) {
 		for (j = 0; j < ctx->nbo; j++) {
-			if (state->bo[i] == ctx->bo[j])
+			if (state->bo[i] == ctx->bo[j].bo)
 				break;
 		}
 		if (j == ctx->nbo) {
+			if (ctx->nbo >= ctx->max_bo) {
+				return -EBUSY;
+			}
 			radeon_bo_incref(ctx->radeon, state->bo[i]);
-			r = radeon_ctx_set_bo_new(ctx, state->bo[i]);
+			r = radeon_ctx_set_bo_new(ctx, state->bo[i], state->id);
 			if (r)
 				return r;
 		}
@@ -144,7 +154,6 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
 	return 0;
 }
 
-
 int radeon_ctx_submit(struct radeon_ctx *ctx)
 {
 	struct drm_radeon_cs drmib;
@@ -152,17 +161,17 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
 	uint64_t chunk_array[2];
 	int r = 0;
 
-	if (!ctx->cpm4)
+	if (!ctx->id)
 		return 0;
 #if 0
-	for (r = 0; r < ctx->cpm4; r++) {
+	for (r = 0; r < ctx->id; r++) {
 		fprintf(stderr, "0x%08X\n", ctx->pm4[r]);
 	}
 #endif
 	drmib.num_chunks = 2;
 	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
 	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
-	chunks[0].length_dw = ctx->cpm4;
+	chunks[0].length_dw = ctx->id;
 	chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
 	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
 	chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
@@ -176,11 +185,10 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
 	return r;
 }
 
-static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
+int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			unsigned id, unsigned *placement)
 {
 	unsigned i;
-	struct radeon_cs_reloc *ptr;
 
 	for (i = 0; i < ctx->nreloc; i++) {
 		if (ctx->reloc[i].handle == bo->handle) {
@@ -188,14 +196,13 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			return 0;
 		}
 	}
-	ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1));
-	if (ptr == NULL)
-		return -ENOMEM;
-	ctx->reloc = ptr;
-	ptr[ctx->nreloc].handle = bo->handle;
-	ptr[ctx->nreloc].read_domain = placement[0] | placement [1];
-	ptr[ctx->nreloc].write_domain = placement[0] | placement [1];
-	ptr[ctx->nreloc].flags = 0;
+	if (ctx->nreloc >= ctx->max_reloc) {
+		return -EBUSY;
+	}
+	ctx->reloc[ctx->nreloc].handle = bo->handle;
+	ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1];
+	ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1];
+	ctx->reloc[ctx->nreloc].flags = 0;
 	ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
 	ctx->nreloc++;
 	return 0;
@@ -203,75 +210,90 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 
 static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state)
 {
-	unsigned i, rid, bid, cid;
-	int r;
+	unsigned i, rid, cid;
+	u32 flags;
+	int r, bo_id[4];
 
 	if (state == NULL)
 		return 0;
-	memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4);
-	for (i = 0; i < state->nreloc; i++) {
+	for (i = 0; i < state->nbo; i++) {
+		bo_id[i] = radeon_ctx_bo_id(ctx, state->bo[i]);
+		if (bo_id[i] < 0) {
+			return -EINVAL;
+		}
+		flags = (~ctx->bo[bo_id[i]].bo_flushed) & ctx->radeon->type[state->id].flush_flags;
+		if (flags) {
+			r = ctx->radeon->bo_flush(ctx, state->bo[i], flags, &state->placement[i * 2]);
+			if (r) {
+				return r;
+			}
+		}
+		ctx->bo[bo_id[i]].bo_flushed |= ctx->radeon->type[state->id].flush_flags;
+	}
+	if ((ctx->radeon->type[state->id].header_cpm4 + state->cpm4) > ctx->npm4) {
+		/* need to flush */
+		return -EBUSY;
+	}
+	memcpy(&ctx->pm4[ctx->id], ctx->radeon->type[state->id].header_pm4, ctx->radeon->type[state->id].header_cpm4 * 4);
+	ctx->id += ctx->radeon->type[state->id].header_cpm4;
+	ctx->npm4 -= ctx->radeon->type[state->id].header_cpm4;
+	memcpy(&ctx->pm4[ctx->id], state->states, state->cpm4 * 4);
+	for (i = 0; i < state->nbo; i++) {
 		rid = state->reloc_pm4_id[i];
-		bid = state->reloc_bo_id[i];
 		cid = ctx->id + rid;
-		r = radeon_ctx_reloc(ctx, state->bo[bid], cid,
-					&state->placement[bid * 2]);
+		r = radeon_ctx_reloc(ctx, state->bo[i], cid,
+					&state->placement[i * 2]);
 		if (r) {
-			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type);
+			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->id);
 			return r;
 		}
 	}
 	ctx->id += state->cpm4;
+	ctx->npm4 -= state->cpm4;
+	for (i = 0; i < state->nbo; i++) {
+		ctx->bo[bo_id[i]].bo_flushed &= ~ctx->radeon->type[state->id].dirty_flags;
+	}
 	return 0;
 }
 
 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
 {
-	void *tmp;
+	unsigned ndw = 0;
 	int r = 0;
 
-	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
-	if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
-		return -EINVAL;
-	}
 	r = radeon_state_pm4(state);
 	if (r)
 		return r;
-	if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
-		/* need to flush */
-		return -EBUSY;
-	}
-	if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
-		fprintf(stderr, "%s single state too big %d, max %d\n",
-			__func__, state->cpm4, RADEON_CTX_MAX_PM4);
+
+	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
+	ndw = state->cpm4 + ctx->radeon->type[state->id].header_cpm4;
+	switch (state->id) {
+	case R600_QUERY_BEGIN:
+		/* account QUERY_END at same time of QUERY_BEGIN so we know we
+		 * have room left for QUERY_END
+		 */
+		if ((ndw * 2) > ctx->npm4) {
+			/* need to flush */
+			return -EBUSY;
+		}
+		ctx->npm4 -= ndw;
+		break;
+	case R600_QUERY_END:
+		/* add again ndw from previous accounting */
+		ctx->npm4 += ndw;
+		break;
+	default:
 		return -EINVAL;
 	}
-	tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
-	if (tmp == NULL)
-		return -ENOMEM;
-	ctx->state = tmp;
-	ctx->state[ctx->nstate++] = radeon_state_incref(state);
-	/* BEGIN/END query are balanced in the same cs so account for END
-	 * END query when scheduling BEGIN query
-	 */
-	if (state->type == R600_QUERY_BEGIN_TYPE) {
-		ctx->draw_cpm4 += state->cpm4 * 2;
-	}
-	return 0;
+
+	return radeon_ctx_state_schedule(ctx, state);
 }
 
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
 {
-	struct radeon_draw *pdraw = NULL;
-	struct radeon_draw **ndraw;
-	struct radeon_state *nstate, *ostate;
-	unsigned cpm4, i, cstate;
-	void *tmp;
+	unsigned i, previous_id;
 	int r = 0;
 
-	ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1));
-	if (ndraw == NULL)
-		return -ENOMEM;
-	ctx->draw = ndraw;
 	for (i = 0; i < draw->nstate; i++) {
 		r = radeon_ctx_state_bo(ctx, draw->state[i]);
 		if (r)
@@ -285,76 +307,17 @@ int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
 			__func__, draw->cpm4, RADEON_CTX_MAX_PM4);
 		return -EINVAL;
 	}
-	tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*));
-	if (tmp == NULL)
-		return -ENOMEM;
-	ctx->state = tmp;
-	pdraw = ctx->cdraw;
-	for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) {
-		nstate = draw->state[i];
-		if (nstate) {
-			if (pdraw && pdraw->state[i]) {
-				ostate = pdraw->state[i];
-				if (ostate->pm4_crc != nstate->pm4_crc) {
-					ctx->state[cstate++] = nstate;
-					cpm4 += nstate->cpm4;
-				}
-			} else {
-				ctx->state[cstate++] = nstate;
-				cpm4 += nstate->cpm4;
+	previous_id = ctx->id;
+	for (i = 0; i < draw->nstate; i++) {
+		/* FIXME always force draw state to schedule */
+		if (draw->state[i] && draw->state[i]->pm4_crc != ctx->state_crc32[draw->state[i]->id]) {
+			r = radeon_ctx_state_schedule(ctx, draw->state[i]);
+			if (r) {
+				ctx->id = previous_id;
+				return r;
 			}
 		}
 	}
-	/* The last state is the draw state always add it */
-	if (draw->state[i] == NULL) {
-		fprintf(stderr, "%s no draw command\n", __func__);
-		return -EINVAL;
-	}
-	ctx->state[cstate++] = draw->state[i];
-	cpm4 += draw->state[i]->cpm4;
-	if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) {
-		/* need to flush */
-		return -EBUSY;
-	}
-	ctx->draw_cpm4 += cpm4;
-	ctx->nstate = cstate;
-	ctx->draw[ctx->ndraw++] = draw;
-	ctx->cdraw = draw;
-	return 0;
-}
-
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
-{
-	int r;
-
-	radeon_draw_incref(draw);
-	r = radeon_ctx_set_draw_new(ctx, draw);
-	if (r)
-		radeon_draw_decref(draw);
-	return r;
-}
-
-int radeon_ctx_pm4(struct radeon_ctx *ctx)
-{
-	unsigned i;
-	int r;
-
-	free(ctx->pm4);
-	ctx->cpm4 = 0;
-	ctx->pm4 = malloc(ctx->draw_cpm4 * 4);
-	if (ctx->pm4 == NULL)
-		return -EINVAL;
-	for (i = 0, ctx->id = 0; i < ctx->nstate; i++) {
-		r = radeon_ctx_state_schedule(ctx, ctx->state[i]);
-		if (r)
-			return r;
-	}
-	if (ctx->id != ctx->draw_cpm4) {
-		fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
-			__func__, ctx->draw_cpm4, ctx->id);
-		return -EINVAL;
-	}
-	ctx->cpm4 = ctx->draw_cpm4;
 	return 0;
 }
 
@@ -384,8 +347,8 @@ printf("%d relocs\n", ctx->nreloc);
 	bof_decref(blob);
 	blob = NULL;
 	/* dump cs */
-printf("%d pm4\n", ctx->cpm4);
-	blob = bof_blob(ctx->cpm4 * 4, ctx->pm4);
+printf("%d pm4\n", ctx->id);
+	blob = bof_blob(ctx->id * 4, ctx->pm4);
 	if (blob == NULL)
 		goto out_err;
 	if (bof_object_set(root, "pm4", blob))
@@ -400,23 +363,23 @@ printf("%d pm4\n", ctx->cpm4);
 		bo = bof_object();
 		if (bo == NULL)
 			goto out_err;
-		size = bof_int32(ctx->bo[i]->size);
+		size = bof_int32(ctx->bo[i].bo->size);
 		if (size == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "size", size))
 			goto out_err;
 		bof_decref(size);
 		size = NULL;
-		handle = bof_int32(ctx->bo[i]->handle);
+		handle = bof_int32(ctx->bo[i].bo->handle);
 		if (handle == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "handle", handle))
 			goto out_err;
 		bof_decref(handle);
 		handle = NULL;
-		radeon_bo_map(ctx->radeon, ctx->bo[i]);
-		blob = bof_blob(ctx->bo[i]->size, ctx->bo[i]->data);
-		radeon_bo_unmap(ctx->radeon, ctx->bo[i]);
+		radeon_bo_map(ctx->radeon, ctx->bo[i].bo);
+		blob = bof_blob(ctx->bo[i].bo->size, ctx->bo[i].bo->data);
+		radeon_bo_unmap(ctx->radeon, ctx->bo[i].bo);
 		if (blob == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "data", blob))
diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c
index 4413ed79fb..1b4e557f28 100644
--- a/src/gallium/winsys/r600/drm/radeon_draw.c
+++ b/src/gallium/winsys/r600/drm/radeon_draw.c
@@ -76,8 +76,6 @@ int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
 {
 	if (state == NULL)
 		return 0;
-	if (state->type >= draw->radeon->ntype)
-		return -EINVAL;
 	draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
 	draw->state[state->id] = state;
 	return 0;
@@ -102,6 +100,7 @@ int radeon_draw_check(struct radeon_draw *draw)
 	for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
 		if (draw->state[i]) {
 			draw->cpm4 += draw->state[i]->cpm4;
+			draw->cpm4 += draw->radeon->type[draw->state[i]->id].header_cpm4;
 		}
 	}
 	return 0;
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 96c0d060f7..469a5dce01 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -30,34 +30,26 @@ struct radeon_ctx;
  * radeon functions
  */
 typedef int (*radeon_state_pm4_t)(struct radeon_state *state);
-struct radeon_register {
-	unsigned			offset;
-	unsigned			need_reloc;
-	unsigned			bo_id;
-	char				name[64];
-};
 
 struct radeon_type {
-	unsigned			npm4;
-	unsigned			id;
-	unsigned			range_start;
-	unsigned			range_end;
-	unsigned			stride;
-	unsigned			immediate;
-	char				name[64];
-	unsigned			nstates;
-	radeon_state_pm4_t		pm4;
-	const struct radeon_register	*regs;
+	const u32			*header_pm4;
+	const u32			header_cpm4;
+	const u32			*state_pm4;
+	const u32			state_cpm4;
+	const u32			flush_flags;
+	const u32			dirty_flags;
 };
 
+typedef int (*radeon_ctx_bo_flush_t)(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement);
+
 struct radeon {
 	int				fd;
 	int				refcount;
 	unsigned			device;
 	unsigned			family;
 	unsigned			nstate;
-	unsigned			ntype;
 	const struct radeon_type	*type;
+	radeon_ctx_bo_flush_t		bo_flush;
 };
 
 extern struct radeon *radeon_new(int fd, unsigned device);
@@ -68,12 +60,9 @@ extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
 extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
 extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
 
-
-int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
-struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
-void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
 int radeon_ctx_draw(struct radeon_ctx *ctx);
+int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
+			unsigned id, unsigned *placement);
 
 /*
  * r600/r700 context functions
@@ -90,7 +79,6 @@ extern int radeon_state_register_set(struct radeon_state *state, unsigned offset
 extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state);
 extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate);
 extern int radeon_state_pm4_generic(struct radeon_state *state);
-extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id);
 
 /*
  * radeon draw functions
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index 308288557a..c60b12ef67 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -32,52 +32,29 @@
 /*
  * state core functions
  */
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
+struct radeon_state *radeon_state(struct radeon *radeon, u32 id)
 {
 	struct radeon_state *state;
 
-	if (type > radeon->ntype) {
-		fprintf(stderr, "%s invalid type %d\n", __func__, type);
-		return NULL;
-	}
-	if (id > radeon->nstate) {
-		fprintf(stderr, "%s invalid state id %d\n", __func__, id);
-		return NULL;
-	}
 	state = calloc(1, sizeof(*state));
 	if (state == NULL)
 		return NULL;
 	state->radeon = radeon;
-	state->type = type;
 	state->id = id;
 	state->refcount = 1;
-	state->npm4 = radeon->type[type].npm4;
-	state->nstates = radeon->type[type].nstates;
-	state->states = calloc(1, state->nstates * 4);
-	state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
-	if (state->states == NULL || state->pm4 == NULL) {
-		radeon_state_decref(state);
-		return NULL;
-	}
+	state->cpm4 = radeon->type[id].state_cpm4;
+	memcpy(state->states, radeon->type[id].state_pm4, radeon->type[id].state_cpm4 * 4);
 	return state;
 }
 
 struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
 {
-	struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
+	struct radeon_state *nstate = radeon_state(state->radeon, state->id);
 	unsigned i;
 
 	if (state == NULL)
 		return NULL;
-	nstate->cpm4 = state->cpm4;
-	nstate->nbo = state->nbo;
-	nstate->nreloc = state->nreloc;
-	memcpy(nstate->states, state->states, state->nstates * 4);
-	memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
-	memcpy(nstate->placement, state->placement, 8 * 4);
-	memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
-	memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
-	memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
+	*nstate = *state;
 	for (i = 0; i < state->nbo; i++) {
 		nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]);
 	}
@@ -102,9 +79,6 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
 	for (i = 0; i < state->nbo; i++) {
 		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
 	}
-	free(state->immd);
-	free(state->states);
-	free(state->pm4);
 	memset(state, 0, sizeof(*state));
 	free(state);
 	return NULL;
@@ -145,24 +119,8 @@ static u32 crc32(void *d, size_t len)
 
 int radeon_state_pm4(struct radeon_state *state)
 {
-	int r;
-
-	if (state == NULL || state->cpm4)
+	if (state == NULL)
 		return 0;
-	r = state->radeon->type[state->type].pm4(state);
-	if (r) {
-		fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
-			__func__, state->type, state->id);
-		return r;
-	}
-	state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
-	return 0;
-}
-
-int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id)
-{
-	state->reloc_pm4_id[state->nreloc] = id;
-	state->reloc_bo_id[state->nreloc] = bo_id;
-	state->nreloc++;
+	state->pm4_crc = crc32(state->states, state->cpm4 * 4);
 	return 0;
 }
-- 
cgit v1.2.3


From a49167c1c03dab9452165f503251e543dec2be9a Mon Sep 17 00:00:00 2001
From: Marcin Slusarz <marcin.slusarz@gmail.com>
Date: Mon, 23 Aug 2010 22:40:58 +0200
Subject: nouveau: handle early initialization errors

handle very early errors in pipe_screen creation (failure of
nouveau_screen_init in nv50_screen_create)

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
---
 src/gallium/drivers/nouveau/nouveau_screen.c        | 3 ++-
 src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c
index 513e5e02bc..ebb21a6e5a 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -258,6 +258,7 @@ nouveau_screen_fini(struct nouveau_screen *screen)
 {
 	struct pipe_winsys *ws = screen->base.winsys;
 	nouveau_channel_free(&screen->channel);
-	ws->destroy(ws);
+	if (ws)
+		ws->destroy(ws);
 }
 
diff --git a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
index 660dbd0c33..d4bf124ce6 100644
--- a/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
+++ b/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c
@@ -19,7 +19,8 @@ nouveau_drm_destroy_winsys(struct pipe_winsys *s)
 {
 	struct nouveau_winsys *nv_winsys = nouveau_winsys(s);
 	struct nouveau_screen *nv_screen= nouveau_screen(nv_winsys->pscreen);
-	nouveau_device_close(&nv_screen->device);
+	if (nv_screen)
+		nouveau_device_close(&nv_screen->device);
 	FREE(nv_winsys);
 }
 
-- 
cgit v1.2.3


From c1ab2c327e37119b5dda3de85f672a8af22ad1bb Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Thu, 26 Aug 2010 03:28:47 +0200
Subject: r300g: fix constant buffer upload once again for r3xx->r4xx

---
 src/gallium/drivers/r300/r300_emit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index 90bc9c56d3..58d7e4ffe9 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -182,7 +182,7 @@ void r300_emit_fs_constants(struct r300_context* r300, unsigned size, void *stat
     OUT_CS_REG_SEQ(R300_PFS_PARAM_0_X, count * 4);
     if (buf->remap_table){
         for (i = 0; i < count; i++) {
-            uint32_t *data = &buf->ptr[buf->remap_table[i]*4];
+            float *data = (float*)&buf->ptr[buf->remap_table[i]*4];
             for (j = 0; j < 4; j++)
                 OUT_CS(pack_float24(data[j]));
         }
-- 
cgit v1.2.3


From 038068909fd1dc802bfd45b2154a24d8001daea6 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Thu, 26 Aug 2010 01:38:23 -0700
Subject: r300g: Include missing header in r300_texture_desc.h.

Include p_format.h for enum pipe_format symbol.

Fixes r300g build.
---
 src/gallium/drivers/r300/r300_texture_desc.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_texture_desc.h b/src/gallium/drivers/r300/r300_texture_desc.h
index 95de66f654..3d7fe1fb47 100644
--- a/src/gallium/drivers/r300/r300_texture_desc.h
+++ b/src/gallium/drivers/r300/r300_texture_desc.h
@@ -24,6 +24,7 @@
 #ifndef R300_TEXTURE_DESC_H
 #define R300_TEXTURE_DESC_H
 
+#include "pipe/p_format.h"
 #include "r300_defines.h"
 
 struct pipe_resource;
-- 
cgit v1.2.3


From 4418a493c2466e734e1ca5ace51535d1dbcf8a46 Mon Sep 17 00:00:00 2001
From: Brian Paul <brianp@vmware.com>
Date: Thu, 26 Aug 2010 11:45:25 -0600
Subject: llvmpipe: fix PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS query

Fixes crashes in glean glsl1 and demos/src/glsl/vert-tex.
See comments for details.
---
 src/gallium/drivers/llvmpipe/lp_screen.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c
index 9b7e0d51cd..1e65a91fc6 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -89,7 +89,14 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
       return PIPE_MAX_SAMPLERS;
    case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
-      return PIPE_MAX_VERTEX_SAMPLERS;
+      /* At this time, the draw module and llvmpipe driver only
+       * support vertex shader texture lookups when LLVM is enabled in
+       * the draw module.
+       */
+      if (debug_get_bool_option("DRAW_USE_LLVM", TRUE))
+         return PIPE_MAX_VERTEX_SAMPLERS;
+      else
+         return 0;
    case PIPE_CAP_MAX_COMBINED_SAMPLERS:
       return PIPE_MAX_SAMPLERS + PIPE_MAX_VERTEX_SAMPLERS;
    case PIPE_CAP_NPOT_TEXTURES:
-- 
cgit v1.2.3


From e57437ccd6814ffd4534fd46512afeb0b9e06eed Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 24 Aug 2010 10:29:33 +1000
Subject: r600g: add DPH support.

---
 src/gallium/drivers/r600/r600_shader.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index f0b7df5a6f..6195bd5332 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1265,6 +1265,13 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
 				alu.src[0].chan = alu.src[1].chan = 0;
 			}
 			break;
+		case TGSI_OPCODE_DPH:
+			if (i == 3) {
+				alu.src[0].sel = V_SQ_ALU_SRC_1;
+				alu.src[0].chan = 0;
+				alu.src[0].neg = 0;
+			}
+			break;
 		default:
 			break;
 		}
@@ -1660,7 +1667,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{32,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_ABS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_RCC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_DPH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DPH,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
 	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
 	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
-- 
cgit v1.2.3


From 36d91be75ea9b79878fdf4b789ea022d781e87f4 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 24 Aug 2010 11:47:56 +1000
Subject: r600g: add exp support in theory.

though it isn't passing the test, and this instruction is pure bonghits.
---
 src/gallium/drivers/r600/r600_shader.c | 106 ++++++++++++++++++++++++++++++++-
 1 file changed, 105 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 6195bd5332..5b43a1303b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1627,6 +1627,110 @@ static int tgsi_xpd(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_exp(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
+	struct r600_bc_alu alu;
+	uint32_t use_temp = 0;
+	int i, r;
+
+	/* result.x = 2^floor(src); */
+	if (inst->Dst[0].Register.WriteMask & 1) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR;
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+		if (r)
+			return r;
+
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 0;
+		alu.dst.write = 1;
+		alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 0;
+
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 0;
+		alu.dst.write = 1;
+		alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+		
+	/* result.y = tmp - floor(tmp); */
+	if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT;
+		alu.src[0] = r600_src[0];
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+		if (r)
+			return r;
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+
+		alu.dst.sel = ctx->temp_reg;
+//		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+//		if (r)
+//			return r;
+		alu.dst.write = 1;
+		alu.dst.chan = 1;
+
+		alu.last = 1;
+
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+
+	/* result.z = RoughApprox2ToX(tmp);*/
+	if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+		if (r)
+			return r;
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.write = 1;
+		alu.dst.chan = 2;
+
+		alu.last = 1;
+
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+
+	}
+
+	/* result.w = 1.0;*/
+	if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+		alu.src[0].sel = V_SQ_ALU_SRC_1;
+		alu.src[0].chan = 0;
+
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 3;
+		alu.dst.write = 1;
+		alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return tgsi_helper_copy(ctx, inst);
+}
 
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -1634,7 +1738,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_LIT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
 	{TGSI_OPCODE_RCP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
 	{TGSI_OPCODE_RSQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIPSQRT_IEEE, tgsi_trans_srcx_replicate},
-	{TGSI_OPCODE_EXP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_EXP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_exp},
 	{TGSI_OPCODE_LOG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_MUL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL, tgsi_op2},
 	{TGSI_OPCODE_ADD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
-- 
cgit v1.2.3


From d8fb13bae30b6ff214c5d5158b9bcaf430f56b43 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 25 Aug 2010 16:02:38 +1000
Subject: r600g: optimise op2 and swapped op2 emission.

this makes op2 emission smaller, since it skips instructions
that don't write to the dst. not sure if this could have unwanted
side effects but try it and see.
---
 src/gallium/drivers/r600/r600_shader.c | 85 +++++++++++++++-------------------
 1 file changed, 37 insertions(+), 48 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 5b43a1303b..1470bb5072 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -642,30 +642,44 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s
 	return 0;
 }
 
-static int tgsi_op2(struct r600_shader_ctx *ctx)
+static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_alu_src r600_src[3];
 	struct r600_bc_alu alu;
 	int i, j, r;
+	int lasti = 0;
+
+	for (i = 0; i < 4; i++) {
+		if (inst->Dst[0].Register.WriteMask & (1 << i)) {
+			lasti = i;
+		}
+	}
 
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
-	for (i = 0; i < 4; i++) {
+	for (i = 0; i < lasti + 1; i++) {
+		if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+			continue;
+
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
-			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
-			alu.dst.chan = i;
-		} else {
-			alu.inst = ctx->inst_info->r600_opcode;
+		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+		if (r)
+			return r;
+		
+		alu.inst = ctx->inst_info->r600_opcode;
+		if (!swap) {
 			for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
 				alu.src[j] = r600_src[j];
 				alu.src[j].chan = tgsi_chan(&inst->Src[j], i);
 			}
-			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
-			if (r)
-				return r;
+		} else {
+			alu.src[0] = r600_src[1];
+			alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
+
+			alu.src[1] = r600_src[0];
+			alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
 		}
 		/* handle some special cases */
 		switch (ctx->inst_info->tgsi_opcode) {
@@ -678,7 +692,7 @@ static int tgsi_op2(struct r600_shader_ctx *ctx)
 		default:
 			break;
 		}
-		if (i == 3) {
+		if (i == lasti) {
 			alu.last = 1;
 		}
 		r = r600_bc_add_alu(ctx->bc, &alu);
@@ -688,6 +702,16 @@ static int tgsi_op2(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_op2(struct r600_shader_ctx *ctx)
+{
+	return tgsi_op2_s(ctx, 0);
+}
+
+static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
+{
+	return tgsi_op2_s(ctx, 1);
+}
+
 /* 
  * r600 - trunc to -PI..PI range
  * r700 - normalize by dividing by 2PI
@@ -833,41 +857,6 @@ static int tgsi_kill(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
-static int tgsi_slt(struct r600_shader_ctx *ctx)
-{
-	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
-	struct r600_bc_alu_src r600_src[3];
-	struct r600_bc_alu alu;
-	int i, r;
-
-	r = tgsi_split_constant(ctx, r600_src);
-	if (r)
-		return r;
-	for (i = 0; i < 4; i++) {
-		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
-			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
-			alu.dst.chan = i;
-		} else {
-			alu.inst = ctx->inst_info->r600_opcode;
-			alu.src[1] = r600_src[0];
-			alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
-			alu.src[0] = r600_src[1];
-			alu.src[0].chan = tgsi_chan(&inst->Src[1], i);
-			r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
-			if (r)
-				return r;
-		}
-		if (i == 3) {
-			alu.last = 1;
-		}
-		r = r600_bc_add_alu(ctx->bc, &alu);
-		if (r)
-			return r;
-	}
-	return 0;
-}
-
 static int tgsi_lit(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -1747,7 +1736,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_DST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
 	{TGSI_OPCODE_MAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
-	{TGSI_OPCODE_SLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_slt},
+	{TGSI_OPCODE_SLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
 	{TGSI_OPCODE_SGE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2},
 	{TGSI_OPCODE_MAD,	1, V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD, tgsi_op3},
 	{TGSI_OPCODE_SUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
@@ -1785,7 +1774,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SFL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SGT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2},
 	{TGSI_OPCODE_SIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN, tgsi_trig},
-	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_slt},
+	{TGSI_OPCODE_SLE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGE, tgsi_op2_swap},
 	{TGSI_OPCODE_SNE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETNE, tgsi_op2},
 	{TGSI_OPCODE_STR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TEX,	0, SQ_TEX_INST_SAMPLE, tgsi_tex},
-- 
cgit v1.2.3


From a03d456f5a41926e39194de70b2d50776e64b8a2 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 25 Aug 2010 15:57:41 +1000
Subject: r600g: add initial if/else/endif support

this adds handling for some more CF instructions and conditions
also adds parameter for stack size emission

These seem to pass on VS with the stack size hack but not on FS,

TODO: fix FS + stack size calcs
---
 src/gallium/drivers/r600/r600_asm.c    | 58 +++++++++++++++++---
 src/gallium/drivers/r600/r600_asm.h    | 21 +++++++-
 src/gallium/drivers/r600/r600_shader.c | 98 ++++++++++++++++++++++++++++++++--
 src/gallium/drivers/r600/r600_sq.h     |  5 ++
 4 files changed, 170 insertions(+), 12 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index e6efae4c56..d83bb34648 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -128,7 +128,7 @@ int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
 	return 0;
 }
 
-int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
+int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type)
 {
 	struct r600_bc_alu *nalu = r600_bc_alu();
 	struct r600_bc_alu *lalu;
@@ -140,7 +140,7 @@ int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 	nalu->nliteral = 0;
 
 	/* cf can contains only alu or only vtx or only tex */
-	if (bc->cf_last == NULL || bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) ||
+	if (bc->cf_last == NULL || bc->cf_last->inst != (type << 3) ||
 		bc->force_add_cf) {
 		/* at most 128 slots, one add alu can add 4 slots + 4 constant worst case */
 		r = r600_bc_add_cf(bc);
@@ -148,7 +148,7 @@ int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 			free(nalu);
 			return r;
 		}
-		bc->cf_last->inst = V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3;
+		bc->cf_last->inst = (type << 3);
 	}
 	if (alu->last && (bc->cf_last->ndw >> 1) >= 124) {
 		bc->force_add_cf = 1;
@@ -183,6 +183,11 @@ int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
 	return 0;
 }
 
+int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
+{
+	return r600_bc_add_alu_type(bc, alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU);
+}
+
 int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
 {
 	struct r600_bc_alu *alu;
@@ -193,7 +198,13 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
 	if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_TEX) {
 		return 0;
 	}
-	if (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3) ||
+	if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
+	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
+	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
+		return 0;
+	}
+	if (((bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3)) &&
+	     (bc->cf_last->inst != (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3))) ||
 		LIST_IS_EMPTY(&bc->cf_last->alu)) {
 		R600_ERR("last CF is not ALU (%p)\n", bc->cf_last);
 		return -EINVAL;
@@ -262,6 +273,18 @@ int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex)
 	return 0;
 }
 
+int r600_bc_add_cfinst(struct r600_bc *bc, int inst)
+{
+	int r;
+	r = r600_bc_add_cf(bc);
+	if (r)
+		return r;
+
+	bc->cf_last->cond = V_SQ_CF_COND_ACTIVE;
+	bc->cf_last->inst = inst;
+	return 0;
+}
+
 static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsigned id)
 {
 	bc->bytecode[id++] = S_SQ_VTX_WORD0_BUFFER_ID(vtx->buffer_id) |
@@ -342,7 +365,9 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 					S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
 					S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
 					S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
-					S_SQ_ALU_WORD1_BANK_SWIZZLE(0);
+					S_SQ_ALU_WORD1_BANK_SWIZZLE(0) |
+			                S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
+		 	                S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
 	}
 	if (alu->last) {
 		for (i = 0; i < alu->nliteral; i++) {
@@ -358,6 +383,7 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 
 	switch (cf->inst) {
 	case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
+	case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
 		bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1);
 		bc->bytecode[id++] = S_SQ_CF_ALU_WORD1_CF_INST(cf->inst >> 3) |
 					S_SQ_CF_ALU_WORD1_BARRIER(1) |
@@ -385,6 +411,16 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 			S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst) |
 			S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
 		break;
+	case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+	case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+	case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
+		bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
+					S_SQ_CF_WORD1_BARRIER(1) |
+			                S_SQ_CF_WORD1_COND(cf->cond) |
+			                S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
+
+		break;
 	default:
 		R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
 		return -EINVAL;
@@ -401,13 +437,13 @@ int r600_bc_build(struct r600_bc *bc)
 	unsigned addr;
 	int r;
 
-
 	/* first path compute addr of each CF block */
 	/* addr start after all the CF instructions */
 	addr = bc->cf_last->id + 2;
 	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
 		switch (cf->inst) {
 		case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
+		case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
 			break;
 		case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
 		case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
@@ -419,6 +455,12 @@ int r600_bc_build(struct r600_bc *bc)
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
 			break;
+		case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+		case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+		case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+			/* hack */
+			bc->nstack = 3;
+			break;
 		default:
 			R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
 			return -EINVAL;
@@ -438,6 +480,7 @@ int r600_bc_build(struct r600_bc *bc)
 			return r;
 		switch (cf->inst) {
 		case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU << 3):
+		case (V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE << 3):
 			LIST_FOR_EACH_ENTRY(alu, &cf->alu, list) {
 				switch(bc->chiprev) {
 				case 0:
@@ -477,6 +520,9 @@ int r600_bc_build(struct r600_bc *bc)
 			break;
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+		case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
+		case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
+		case V_SQ_CF_WORD1_SQ_CF_INST_POP:
 			break;
 		default:
 			R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index e944bd02de..dbd885caf9 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -47,6 +47,7 @@ struct r600_bc_alu {
 	unsigned			inst;
 	unsigned			last;
 	unsigned			is_op3;
+	unsigned                        predicate;
 	unsigned			nliteral;
 	unsigned			literal_added;
 	u32				value[4];
@@ -114,12 +115,25 @@ struct r600_bc_cf {
 	unsigned			addr;
 	unsigned			ndw;
 	unsigned			id;
+	unsigned                        cond;
+	unsigned                        pop_count;
+	unsigned                        cf_addr; /* control flow addr */
 	struct list_head		alu;
 	struct list_head		tex;
 	struct list_head		vtx;
 	struct r600_bc_output		output;
 };
 
+#define FC_NONE 0
+#define FC_IF 1
+#define FC_LOOP 2
+
+struct r600_cf_stack_entry {
+	int type;
+	struct r600_bc_cf *start;
+	struct r600_bc_cf *mid; /* used to store the else point */
+};
+	
 struct r600_bc {
 	enum radeon_family		family;
 	int chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
@@ -128,9 +142,13 @@ struct r600_bc {
 	unsigned			ndw;
 	unsigned			ncf;
 	unsigned			ngpr;
+	unsigned                        nstack;
 	unsigned			nresource;
 	unsigned			force_add_cf;
 	u32				*bytecode;
+
+	u32 fc_sp;
+	struct r600_cf_stack_entry fc_stack[32];
 };
 
 int r600_bc_init(struct r600_bc *bc, enum radeon_family family);
@@ -140,5 +158,6 @@ int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx);
 int r600_bc_add_tex(struct r600_bc *bc, const struct r600_bc_tex *tex);
 int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output);
 int r600_bc_build(struct r600_bc *bc);
-
+int r600_bc_add_cfinst(struct r600_bc *bc, int inst);
+int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int type);
 #endif
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 1470bb5072..052b4971f3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -144,7 +144,8 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i / 4] |= tmp;
 	}
 	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
-	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
+	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
+		S_028868_STACK_SIZE(rshader->bc.nstack);
 	rpshader->rstate = state;
 	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
 	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
@@ -200,7 +201,8 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
 							S_0286CC_PERSP_GRADIENT_ENA(1);
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
-	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr);
+	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
+		S_028868_STACK_SIZE(rshader->bc.nstack);
 	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
 	rpshader->rstate = state;
 	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
@@ -276,10 +278,12 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 		R600_ERR("predicate unsupported\n");
 		return -EINVAL;
 	}
+#if 0
 	if (i->Instruction.Label) {
 		R600_ERR("label unsupported\n");
 		return -EINVAL;
 	}
+#endif
 	for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
 		if (i->Src[j].Register.Indirect ||
 			i->Src[j].Register.Dimension ||
@@ -1721,6 +1725,90 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 	return tgsi_helper_copy(ctx, inst);
 }
 
+static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu, *lalu;
+	struct r600_bc_cf *last;
+	int r;
+
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = opcode;
+	alu.predicate = 1;
+
+	alu.dst.sel = ctx->temp_reg;
+	alu.dst.write = 1;
+	alu.dst.chan = 0;
+
+	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+	if (r)
+		return r;
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+	alu.src[1].sel = V_SQ_ALU_SRC_0;
+	alu.src[1].chan = 0;
+	
+	alu.last = 1;
+
+	r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE);
+	if (r)
+		return r;
+
+	return 0;
+}
+
+static int pops(struct r600_shader_ctx *ctx, int pops)
+{
+	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_POP);	
+	ctx->bc->cf_last->pop_count = pops;
+	return 0;
+}
+
+static int tgsi_if(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+
+	emit_logic_pred(ctx, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE);
+
+	ctx->bc->fc_sp++;
+	ctx->bc->fc_stack[ctx->bc->fc_sp].type = FC_IF;
+	ctx->bc->fc_stack[ctx->bc->fc_sp].mid = NULL;
+	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
+
+	ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
+	return 0;
+}
+
+static int tgsi_else(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_ELSE);
+	ctx->bc->cf_last->pop_count = 1;
+
+	/* fixup mid */
+	ctx->bc->fc_stack[ctx->bc->fc_sp].mid = ctx->bc->cf_last;
+	ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
+	return 0;
+}
+
+static int tgsi_endif(struct r600_shader_ctx *ctx)
+{
+	pops(ctx, 1);
+	if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_IF) {
+		R600_ERR("if/endif unbalanced in shader\n");
+		return -1;
+	}
+
+	if (ctx->bc->fc_stack[ctx->bc->fc_sp].mid == NULL) {
+		ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
+		ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
+	} else {
+		ctx->bc->fc_stack[ctx->bc->fc_sp].mid->cf_addr = ctx->bc->cf_last->id + 2;
+	}
+	ctx->bc->fc_sp--;
+
+	return 0;
+}
+
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_MOV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
@@ -1799,12 +1887,12 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_DP2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_TXL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_BRK,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_IF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_IF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
 	/* gap */
 	{75,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{76,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ELSE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDIF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ELSE,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_else},
+	{TGSI_OPCODE_ENDIF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endif},
 	/* gap */
 	{79,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{80,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index ad4de0b072..b4ed435e91 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -603,4 +603,9 @@
 #define   G_SQ_TEX_WORD2_SRC_SEL_W(x)                                (((x) >> 29) & 0x7)
 #define   C_SQ_TEX_WORD2_SRC_SEL_W                                   0x1FFFFFFF
 
+#define V_SQ_CF_COND_ACTIVE                             0x00
+#define V_SQ_CF_COND_FALSE                              0x01
+#define V_SQ_CF_COND_BOOL                               0x02
+#define V_SQ_CF_COND_NOT_BOOL                           0x03
+
 #endif
-- 
cgit v1.2.3


From 2184f3ec3059eaf8a9a2b04c995162543f000862 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 27 Aug 2010 15:45:58 +1000
Subject: Revert "r600g: simplify states"

This reverts commit bd25e23bf3740f59ce8859848c715daeb9e9821f.

Apart from introducing a lot of hex magic numbers and being highly impenetable code,
it causes lots of lockups on an average piglit run that always runs without lockups.

Always run piglit before/after doing big things like this.
---
 src/gallium/drivers/r600/r600_blit.c       |   61 +-
 src/gallium/drivers/r600/r600_context.c    |    9 +-
 src/gallium/drivers/r600/r600_draw.c       |   46 +-
 src/gallium/drivers/r600/r600_query.c      |    6 +-
 src/gallium/drivers/r600/r600_shader.c     |    7 +-
 src/gallium/drivers/r600/r600_state.c      |   78 +-
 src/gallium/drivers/r600/r600_texture.c    |   18 +-
 src/gallium/drivers/r600/radeon.h          |  669 ++-
 src/gallium/winsys/r600/drm/r600_state.c   | 8091 ++--------------------------
 src/gallium/winsys/r600/drm/r600_states.h  |  562 ++
 src/gallium/winsys/r600/drm/radeon.c       |   44 +
 src/gallium/winsys/r600/drm/radeon_ctx.c   |  313 +-
 src/gallium/winsys/r600/drm/radeon_draw.c  |    3 +-
 src/gallium/winsys/r600/drm/radeon_priv.h  |   34 +-
 src/gallium/winsys/r600/drm/radeon_state.c |   56 +-
 15 files changed, 1720 insertions(+), 8277 deletions(-)
 create mode 100644 src/gallium/winsys/r600/drm/r600_states.h

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index d3b722c82f..72175fbbd5 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 				      unsigned srcx, unsigned srcy, unsigned srcz,
 				      unsigned width, unsigned height)
 {
-	util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
+	util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
 				  src, subsrc, srcx, srcy, srcz, width, height);
 }
 
@@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	memcpy(bo->data, vbo, 128);
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 0);
+	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return -ENOMEM;
@@ -199,35 +199,33 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
 	 */
-	rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000080;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000080;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
 	rstate->bo[0] = bo;
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
-	rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return -ENOMEM;
 	}
 	bstates->vs_resource0 = rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + 1);
+	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
 	if (rstate == NULL) {
 		return -ENOMEM;
 	}
-	rstate->states[R600_RESOURCE__RESOURCE_WORD0] = 0x00000010;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD1] = 0x00000070;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD2] = 0x02302000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD3] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD4] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD5] = 0x00000000;
+	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD6] = 0xC0000000;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, bo);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -305,7 +303,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_VS_SHADER);
+	rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return NULL;
@@ -323,8 +321,6 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	rstate->nbo = 2;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	rstate->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
-	rstate->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
 
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -378,7 +374,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_PS_SHADER);
+	rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return NULL;
@@ -395,7 +391,6 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	rstate->bo[0] = bo;
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
 
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -408,7 +403,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VGT);
+	rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
 	if (rstate == NULL)
 		return NULL;
 
@@ -430,7 +425,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_DRAW);
+	rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
 	if (rstate == NULL)
 		return NULL;
 
@@ -453,7 +448,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT0 + id);
+	rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
 	if (rstate == NULL)
 		return NULL;
 
@@ -476,7 +471,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
+	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 	if (rstate == NULL)
 		return NULL;
 
@@ -505,7 +500,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_DSA);
+	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 	if (rstate == NULL)
 		return NULL;
 
@@ -529,7 +524,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_BLEND);
+	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
 	if (rstate == NULL)
 		return NULL;
 
@@ -548,7 +543,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 	if (rstate == NULL)
 		return NULL;
 
@@ -791,10 +786,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	r600_queries_suspend(ctx);
 
 	/* schedule draw*/
-	r = radeon_ctx_set_draw(rctx->ctx, draw);
+	r = radeon_ctx_set_draw_new(rctx->ctx, draw);
 	if (r == -EBUSY) {
 		r600_flush(ctx, 0, NULL);
-		r = radeon_ctx_set_draw(rctx->ctx, draw);
+		r = radeon_ctx_set_draw_new(rctx->ctx, draw);
 	}
 	if (r) {
 		goto out;
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 790a85110b..9af28356c5 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -53,10 +53,12 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 
 	/* suspend queries */
 	r600_queries_suspend(ctx);
+	if (radeon_ctx_pm4(rctx->ctx))
+		goto out;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
-	if (!rctx->ctx->id)
+	if (!rctx->ctx->cpm4)
 		goto out;
 	sprintf(dname, "gallium-%08d.bof", dc);
 	if (dc < 2) {
@@ -71,7 +73,8 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	}
 	dc++;
 out:
-	radeon_ctx_clear(rctx->ctx);
+	rctx->ctx = radeon_ctx_decref(rctx->ctx);
+	rctx->ctx = radeon_ctx(rscreen->rw);
 	/* resume queries */
 	r600_queries_resume(ctx);
 }
@@ -215,7 +218,7 @@ static void r600_init_config(struct r600_context *rctx)
 		num_es_stack_entries = 0;
 		break;
 	}
-	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG);
+	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
 
 	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index a1a392ad2b..1eb868c4c7 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -101,21 +101,19 @@ static int r600_draw_common(struct r600_draw *draw)
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE0 + i);
+		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
 		if (vs_resource == NULL)
 			return -ENOMEM;
 		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		vs_resource->nbo = 1;
-		vs_resource->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
-		vs_resource->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
-		vs_resource->states[R600_RESOURCE__RESOURCE_WORD0] = offset;
-		vs_resource->states[R600_RESOURCE__RESOURCE_WORD1] = rbuffer->bo->size - offset;
-		vs_resource->states[R600_RESOURCE__RESOURCE_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 								S_038008_DATA_FORMAT(format);
-		vs_resource->states[R600_RESOURCE__RESOURCE_WORD3] = 0x00000000;
-		vs_resource->states[R600_RESOURCE__RESOURCE_WORD4] = 0x00000000;
-		vs_resource->states[R600_RESOURCE__RESOURCE_WORD5] = 0x00000000;
-		vs_resource->states[R600_RESOURCE__RESOURCE_WORD6] = 0xC0000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD4] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD5] = 0x00000000;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
 		vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
 		vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
 		r = radeon_draw_set_new(rctx->draw, vs_resource);
@@ -123,29 +121,22 @@ static int r600_draw_common(struct r600_draw *draw)
 			return r;
 	}
 	/* FIXME start need to change winsys */
+	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	if (draw->draw == NULL)
+		return -ENOMEM;
+	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+	draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	if (draw->index_buffer) {
-		draw->draw = radeon_state(rscreen->rw, R600_DRAW);
-		if (draw->draw == NULL)
-			return -ENOMEM;
-		draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-		draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 		rbuffer = (struct r600_resource*)draw->index_buffer;
 		draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
 		draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
 		draw->draw->nbo = 1;
-		draw->draw->reloc_pm4_id[0] = R600_DRAW__INDICES_BO_ID;
-	} else {
-		draw->draw = radeon_state(rscreen->rw, R600_DRAW_AUTO);
-		if (draw->draw == NULL)
-			return -ENOMEM;
-		draw->draw->states[R600_DRAW_AUTO__VGT_NUM_INDICES] = draw->count;
-		draw->draw->states[R600_DRAW_AUTO__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	}
 	r = radeon_draw_set_new(rctx->draw, draw->draw);
 	if (r)
 		return r;
-	draw->vgt = radeon_state(rscreen->rw, R600_VGT);
+	draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
 	if (draw->vgt == NULL)
 		return -ENOMEM;
 	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
@@ -154,18 +145,23 @@ static int r600_draw_common(struct r600_draw *draw)
 	draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
 	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
 	draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+	draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
 	draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
 	r = radeon_draw_set_new(rctx->draw, draw->vgt);
 	if (r)
 		return r;
 	/* FIXME */
-	r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
+	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
 	if (r == -EBUSY) {
 		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw(rctx->ctx, rctx->draw);
+		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
 	}
 	if (r)
 		return r;
+	rctx->draw = radeon_draw_duplicate(rctx->draw);
 	return 0;
 }
 
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 8b4fe8999f..5929606cd2 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -36,11 +36,10 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN);
+	rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
-	rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
@@ -56,11 +55,10 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_QUERY_END);
+	rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
-	rstate->reloc_pm4_id[0] = R600_QUERY__BO_ID;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 052b4971f3..ebcf19c12b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -132,7 +132,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	unsigned i, tmp;
 
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_VS_SHADER);
+	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < 10; i++) {
@@ -152,8 +152,6 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	rpshader->rstate->nbo = 2;
 	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	state->reloc_pm4_id[0] = R600_VS_SHADER__SQ_PGM_START_VS_BO_ID;
-	state->reloc_pm4_id[1] = R600_VS_SHADER__SQ_PGM_START_FS_BO_ID;
 	return radeon_state_pm4(state);
 }
 
@@ -168,7 +166,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 
 	rasterizer = &rctx->rasterizer->state.rasterizer;
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_PS_SHADER);
+	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < rshader->ninput; i++) {
@@ -208,7 +206,6 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
 	rpshader->rstate->nbo = 1;
 	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	state->reloc_pm4_id[0] = R600_PS_SHADER__SQ_PGM_START_PS_BO_ID;
 	return radeon_state_pm4(state);
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e75575da79..b5e5346163 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -283,17 +283,19 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, i, id;
+	unsigned nconstant = 0, i, type, id;
 	struct radeon_state *rstate;
 	struct pipe_transfer *transfer;
 	u32 *ptr;
 
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
-		id = R600_VS_CONSTANT0;
+		id = R600_VS_CONSTANT;
+		type = R600_VS_CONSTANT_TYPE;
 		break;
 	case PIPE_SHADER_FRAGMENT:
-		id = R600_PS_CONSTANT0;
+		id = R600_PS_CONSTANT;
+		type = R600_PS_CONSTANT_TYPE;
 		break;
 	default:
 		R600_ERR("unsupported %d\n", shader);
@@ -305,7 +307,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		if (ptr == NULL)
 			return;
 		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state(rscreen->rw, id + i);
+			rstate = radeon_state(rscreen->rw, type, id + i);
 			if (rstate == NULL)
 				return;
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
@@ -620,7 +622,7 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
 
-	rstate = radeon_state(rscreen->rw, R600_BLEND);
+	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
@@ -679,14 +681,14 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
 	struct radeon_state *rstate;
 	const struct pipe_clip_state *state = &rctx->clip->state.clip;
 
-	rstate = radeon_state(rscreen->rw, R600_UCP0 + clip);
+	rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
 	if (rstate == NULL)
 		return NULL;
 
-	rstate->states[R600_UCP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
-	rstate->states[R600_UCP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
-	rstate->states[R600_UCP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
-	rstate->states[R600_UCP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
+	rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
+	rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
+	rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
+	rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
 
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -709,7 +711,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0 + cb);
+	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
 	if (rstate == NULL)
 		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
@@ -720,9 +722,6 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-	rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
-	rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
-	rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
 	rstate->nbo = 3;
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
@@ -741,14 +740,14 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 		S_0280A0_SOURCE_FORMAT(1) |
 		S_0280A0_NUMBER_TYPE(ntype);
 
-	rstate->states[R600_CB__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
-	rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
+	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
-	rstate->states[R600_CB__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[R600_CB__CB_COLOR0_FRAG] = 0x00000000;
-	rstate->states[R600_CB__CB_COLOR0_TILE] = 0x00000000;
-	rstate->states[R600_CB__CB_COLOR0_MASK] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
@@ -769,7 +768,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	if (state->zsbuf == NULL)
 		return NULL;
 
-	rstate = radeon_state(rscreen->rw, R600_DB);
+	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
 	if (rstate == NULL)
 		return NULL;
 
@@ -783,7 +782,6 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
 	level = state->zsbuf->level;
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
@@ -846,7 +844,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		prov_vtx = 0;
 
 	rctx->flat_shade = state->flatshade;
-	rstate = radeon_state(rscreen->rw, R600_RASTERIZER);
+	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
@@ -927,7 +925,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	}
 	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR);
+	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
@@ -962,7 +960,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
@@ -995,7 +993,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	if (rctx->ps_shader == NULL) {
 		return NULL;
 	}
-	rstate = radeon_state(rscreen->rw, R600_DSA);
+	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
 	if (rstate == NULL)
 		return NULL;
 
@@ -1147,7 +1145,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, id);
+	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
@@ -1248,7 +1246,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 		R600_ERR("unknow format %d\n", view->texture->format);
 		return NULL;
 	}
-	rstate = radeon_state(rscreen->rw, id);
+	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
 	if (rstate == NULL) {
 		return NULL;
 	}
@@ -1270,36 +1268,34 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 	rstate->placement[1] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
-	rstate->reloc_pm4_id[0] = R600_RESOURCE__RESOURCE_BO0_ID;
-	rstate->reloc_pm4_id[1] = R600_RESOURCE__RESOURCE_BO1_ID;
 
 	pitch = (tmp->pitch[0] / tmp->bpt);
 	pitch = (pitch + 0x7) & ~0x7;
 	
 	/* FIXME properly handle first level != 0 */
-	rstate->states[R600_RESOURCE__RESOURCE_WORD0] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
 			S_038000_TILE_MODE(array_mode) |
 			S_038000_TILE_TYPE(tile_type) |
 			S_038000_PITCH((pitch / 8) - 1) |
 			S_038000_TEX_WIDTH(view->texture->width0 - 1);
-	rstate->states[R600_RESOURCE__RESOURCE_WORD1] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD1] =
 			S_038004_TEX_HEIGHT(view->texture->height0 - 1) |
 			S_038004_TEX_DEPTH(view->texture->depth0 - 1) |
 			S_038004_DATA_FORMAT(format);
-	rstate->states[R600_RESOURCE__RESOURCE_WORD2] = tmp->offset[0] >> 8;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD3] = tmp->offset[1] >> 8;
-	rstate->states[R600_RESOURCE__RESOURCE_WORD4] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = tmp->offset[0] >> 8;
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = tmp->offset[1] >> 8;
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD4] =
 		        word4 | 
 			S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_NORM) |
 			S_038010_SRF_MODE_ALL(V_038010_SFR_MODE_NO_ZERO) |
 			S_038010_REQUEST_SIZE(1) |
 			S_038010_BASE_LEVEL(view->first_level);
-	rstate->states[R600_RESOURCE__RESOURCE_WORD5] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD5] =
 			S_038014_LAST_LEVEL(view->last_level) |
 			S_038014_BASE_ARRAY(0) |
 			S_038014_LAST_ARRAY(0);
-	rstate->states[R600_RESOURCE__RESOURCE_WORD6] =
+	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
 			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
@@ -1346,7 +1342,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
-	rstate = radeon_state(rscreen->rw, R600_CB_CNTL);
+	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1423,7 +1419,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 		if (rctx->ps_sampler[i]) {
 			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
 							&rctx->ps_sampler[i]->state.sampler,
-							R600_PS_SAMPLER0 + i);
+							R600_PS_SAMPLER + i);
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
@@ -1431,7 +1427,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 		if (rctx->ps_sampler_view[i]) {
 			rctx->hw_states.ps_resource[i] = r600_resource(ctx,
 							&rctx->ps_sampler_view[i]->state.sampler_view,
-							R600_PS_RESOURCE0 + i);
+							R600_PS_RESOURCE + i);
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 9dc0208eb1..fb84ed9cfe 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -663,7 +663,7 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR);
+	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
 	if (rstate == NULL)
 		return NULL;
 
@@ -707,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0);
+	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -742,16 +742,13 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 		rstate->nbo = 3;
 		color_info = S_0280A0_SOURCE_FORMAT(1);
 	}
-	rstate->reloc_pm4_id[0] = R600_CB__CB_COLOR0_BASE_BO_ID;
-	rstate->reloc_pm4_id[1] = R600_CB__CB_COLOR0_FRAG_BO_ID;
-	rstate->reloc_pm4_id[2] = R600_CB__CB_COLOR0_TILE_BO_ID;
 	color_info |= S_0280A0_FORMAT(format) |
 		S_0280A0_COMP_SWAP(swap) |
 		S_0280A0_BLEND_CLAMP(1) |
 		S_0280A0_NUMBER_TYPE(ntype);
-	rstate->states[R600_CB__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
-	rstate->states[R600_CB__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
+	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
 
 	if (radeon_state_pm4(rstate)) {
@@ -769,7 +766,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	struct r600_resource *rbuffer;
 	unsigned pitch, slice, format;
 
-	rstate = radeon_state(rscreen->rw, R600_DB);
+	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -787,7 +784,6 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
 	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
 						S_028000_SLICE_TILE_MAX(slice);
-	rstate->reloc_pm4_id[0] = R600_DB__DB_DEPTH_BASE_BO_ID;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 1;
@@ -819,7 +815,7 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT);
+	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
 	if (rstate == NULL)
 		return NULL;
 
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 777fe3e792..b2cc74f696 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -104,18 +104,26 @@ int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
 struct radeon_state {
 	struct radeon			*radeon;
 	unsigned			refcount;
+	unsigned			type;
 	unsigned			id;
+	unsigned			nstates;
+	u32				*states;
+	unsigned			npm4;
 	unsigned			cpm4;
-	u32				states[128];
 	u32				pm4_crc;
+	u32				*pm4;
+	u32				nimmd;
+	u32				*immd;
 	unsigned			nbo;
 	struct radeon_bo		*bo[4];
-	unsigned			reloc_pm4_id[4];
+	unsigned			nreloc;
+	unsigned			reloc_pm4_id[8];
+	unsigned			reloc_bo_id[8];
 	u32				placement[8];
 	unsigned			bo_dirty[4];
 };
 
-struct radeon_state *radeon_state(struct radeon *radeon, u32 id);
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
 struct radeon_state *radeon_state_incref(struct radeon_state *state);
 struct radeon_state *radeon_state_decref(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
@@ -139,6 +147,16 @@ int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
 int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
 int radeon_draw_check(struct radeon_draw *draw);
 
+struct radeon_ctx *radeon_ctx(struct radeon *radeon);
+struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
+struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
+int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_pm4(struct radeon_ctx *ctx);
+int radeon_ctx_submit(struct radeon_ctx *ctx);
+void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
+
 /*
  * radeon context functions
  */
@@ -151,216 +169,261 @@ struct radeon_cs_reloc {
 };
 #pragma pack()
 
-struct radeon_ctx_bo {
-	struct radeon_bo		*bo;
-	u32				bo_flushed;
-	unsigned			state_id;
-};
-
 struct radeon_ctx {
 	int				refcount;
 	struct radeon			*radeon;
 	u32				*pm4;
-	int				npm4;
+	u32				cpm4;
+	u32				draw_cpm4;
 	unsigned			id;
+	unsigned			next_id;
 	unsigned			nreloc;
-	unsigned			max_reloc;
 	struct radeon_cs_reloc		*reloc;
 	unsigned			nbo;
-	struct radeon_ctx_bo		*bo;
-	unsigned			max_bo;
-	u32				*state_crc32;
+	struct radeon_bo		**bo;
+	unsigned			ndraw;
+	struct radeon_draw		*cdraw;
+	struct radeon_draw		**draw;
+	unsigned			nstate;
+	struct radeon_state		**state;
 };
 
-struct radeon_ctx *radeon_ctx(struct radeon *radeon);
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
-void radeon_ctx_clear(struct radeon_ctx *ctx);
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
-int radeon_ctx_pm4(struct radeon_ctx *ctx);
-int radeon_ctx_submit(struct radeon_ctx *ctx);
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
-
-
 /*
  * R600/R700
  */
-#define R600_CONFIG		0
-#define R600_CB_CNTL		1
-#define R600_RASTERIZER		2
-#define R600_VIEWPORT		3
-#define R600_SCISSOR		4
-#define R600_BLEND		5
-#define R600_DSA		6
-#define R600_VGT		7
-#define R600_QUERY_BEGIN	8
-#define R600_QUERY_END		9
-#define R600_VS_SHADER		10
-#define R600_PS_SHADER		11
-#define R600_DB			12
-#define R600_CB0		13
-#define R600_UCP0		21
-#define R600_PS_RESOURCE0	27
-#define R600_VS_RESOURCE0	187
-#define R600_FS_RESOURCE0	347
-#define R600_GS_RESOURCE0	363
-#define R600_PS_CONSTANT0	523
-#define R600_VS_CONSTANT0	779
-#define R600_PS_SAMPLER0	1035
-#define R600_VS_SAMPLER0	1053
-#define R600_GS_SAMPLER0	1071
-#define R600_PS_SAMPLER_BORDER0	1089
-#define R600_VS_SAMPLER_BORDER0	1107
-#define R600_GS_SAMPLER_BORDER0	1125
-#define R600_DRAW_AUTO		1143
-#define R600_DRAW		1144
-#define R600_NSTATE		1145
+
+#define R600_NSTATE				1288
+#define R600_NTYPE				35
+
+#define R600_CONFIG				0
+#define R600_CONFIG_TYPE				0
+#define R600_CB_CNTL				1
+#define R600_CB_CNTL_TYPE				1
+#define R600_RASTERIZER				2
+#define R600_RASTERIZER_TYPE				2
+#define R600_VIEWPORT				3
+#define R600_VIEWPORT_TYPE				3
+#define R600_SCISSOR				4
+#define R600_SCISSOR_TYPE				4
+#define R600_BLEND				5
+#define R600_BLEND_TYPE				5
+#define R600_DSA				6
+#define R600_DSA_TYPE				6
+#define R600_VS_SHADER				7
+#define R600_VS_SHADER_TYPE				7
+#define R600_PS_SHADER				8
+#define R600_PS_SHADER_TYPE				8
+#define R600_PS_CONSTANT				9
+#define R600_PS_CONSTANT_TYPE				9
+#define R600_VS_CONSTANT				265
+#define R600_VS_CONSTANT_TYPE				10
+#define R600_PS_RESOURCE				521
+#define R600_PS_RESOURCE_TYPE				11
+#define R600_VS_RESOURCE				681
+#define R600_VS_RESOURCE_TYPE				12
+#define R600_FS_RESOURCE				841
+#define R600_FS_RESOURCE_TYPE				13
+#define R600_GS_RESOURCE				1001
+#define R600_GS_RESOURCE_TYPE				14
+#define R600_PS_SAMPLER				1161
+#define R600_PS_SAMPLER_TYPE				15
+#define R600_VS_SAMPLER				1179
+#define R600_VS_SAMPLER_TYPE				16
+#define R600_GS_SAMPLER				1197
+#define R600_GS_SAMPLER_TYPE				17
+#define R600_PS_SAMPLER_BORDER				1215
+#define R600_PS_SAMPLER_BORDER_TYPE				18
+#define R600_VS_SAMPLER_BORDER				1233
+#define R600_VS_SAMPLER_BORDER_TYPE				19
+#define R600_GS_SAMPLER_BORDER				1251
+#define R600_GS_SAMPLER_BORDER_TYPE				20
+#define R600_CB0				1269
+#define R600_CB0_TYPE				21
+#define R600_CB1				1270
+#define R600_CB1_TYPE				22
+#define R600_CB2				1271
+#define R600_CB2_TYPE				23
+#define R600_CB3				1272
+#define R600_CB3_TYPE				24
+#define R600_CB4				1273
+#define R600_CB4_TYPE				25
+#define R600_CB5				1274
+#define R600_CB5_TYPE				26
+#define R600_CB6				1275
+#define R600_CB6_TYPE				27
+#define R600_CB7				1276
+#define R600_CB7_TYPE				28
+#define R600_QUERY_BEGIN			1277
+#define R600_QUERY_BEGIN_TYPE			29
+#define R600_QUERY_END				1278
+#define R600_QUERY_END_TYPE			30
+#define R600_DB					1279
+#define R600_DB_TYPE				31
+#define R600_CLIP				1280
+#define R600_CLIP_TYPE				32
+#define R600_VGT				1286
+#define R600_VGT_TYPE				33
+#define R600_DRAW				1287
+#define R600_DRAW_TYPE				34
 
 /* R600_CONFIG */
-#define R600_CONFIG__SQ_CONFIG					0
+#define R600_CONFIG__SQ_CONFIG			0
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			1
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2			2
 #define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT			3
 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1			4
 #define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2			5
-#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ		8
-#define R600_CONFIG__TA_CNTL_AUX				11
-#define R600_CONFIG__VC_ENHANCE					14
-#define R600_CONFIG__DB_DEBUG					17
-#define R600_CONFIG__DB_WATERMARKS				20
-#define R600_CONFIG__SX_MISC					23
-#define R600_CONFIG__SPI_THREAD_GROUPING			26
-#define R600_CONFIG__CB_SHADER_CONTROL				29
-#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE			32
-#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE			33
-#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE			34
-#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE			35
-#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE			36
-#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE			37
-#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE			38
-#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE			39
-#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE			40
-#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL			43
-#define R600_CONFIG__VGT_HOS_CNTL				44
-#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL			45
-#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL			46
-#define R600_CONFIG__VGT_HOS_REUSE_DEPTH			47
-#define R600_CONFIG__VGT_GROUP_PRIM_TYPE			48
-#define R600_CONFIG__VGT_GROUP_FIRST_DECR			49
-#define R600_CONFIG__VGT_GROUP_DECR				50
-#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL			51
-#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL			52
-#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL			53
-#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL			54
-#define R600_CONFIG__VGT_GS_MODE				55
-#define R600_CONFIG__PA_SC_MODE_CNTL				58
-#define R600_CONFIG__VGT_STRMOUT_EN				61
-#define R600_CONFIG__VGT_REUSE_OFF				62
-#define R600_CONFIG__VGT_VTX_CNT_EN				63
-#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN			66
+#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ			6
+#define R600_CONFIG__TA_CNTL_AUX			7
+#define R600_CONFIG__VC_ENHANCE			8
+#define R600_CONFIG__DB_DEBUG			9
+#define R600_CONFIG__DB_WATERMARKS			10
+#define R600_CONFIG__SX_MISC			11
+#define R600_CONFIG__SPI_THREAD_GROUPING			12
+#define R600_CONFIG__CB_SHADER_CONTROL			13
+#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE			14
+#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE			15
+#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE			16
+#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE			17
+#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE			18
+#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE			19
+#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE			20
+#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE			21
+#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE			22
+#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL			23
+#define R600_CONFIG__VGT_HOS_CNTL			24
+#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL			25
+#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL			26
+#define R600_CONFIG__VGT_HOS_REUSE_DEPTH			27
+#define R600_CONFIG__VGT_GROUP_PRIM_TYPE			28
+#define R600_CONFIG__VGT_GROUP_FIRST_DECR			29
+#define R600_CONFIG__VGT_GROUP_DECR			30
+#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL			31
+#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL			32
+#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL			33
+#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL			34
+#define R600_CONFIG__VGT_GS_MODE			35
+#define R600_CONFIG__PA_SC_MODE_CNTL			36
+#define R600_CONFIG__VGT_STRMOUT_EN			37
+#define R600_CONFIG__VGT_REUSE_OFF			38
+#define R600_CONFIG__VGT_VTX_CNT_EN			39
+#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN			40
+#define R600_CONFIG_SIZE				41
+#define R600_CONFIG_PM4				128
 /* R600_CB_CNTL */
-#define R600_CB_CNTL__CB_CLEAR_RED				0
-#define R600_CB_CNTL__CB_CLEAR_GREEN				1
-#define R600_CB_CNTL__CB_CLEAR_BLUE				2
-#define R600_CB_CNTL__CB_CLEAR_ALPHA				3
-#define R600_CB_CNTL__CB_SHADER_MASK				6
-#define R600_CB_CNTL__CB_TARGET_MASK				7
-#define R600_CB_CNTL__CB_FOG_RED				10
-#define R600_CB_CNTL__CB_FOG_GREEN				11
-#define R600_CB_CNTL__CB_FOG_BLUE				12
-#define R600_CB_CNTL__CB_COLOR_CONTROL				15
-#define R600_CB_CNTL__PA_SC_AA_CONFIG				18
-#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX			21
-#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX		22
-#define R600_CB_CNTL__CB_CLRCMP_CONTROL				25
-#define R600_CB_CNTL__CB_CLRCMP_SRC				26
-#define R600_CB_CNTL__CB_CLRCMP_DST				27
-#define R600_CB_CNTL__CB_CLRCMP_MSK				28
-#define R600_CB_CNTL__PA_SC_AA_MASK				31
+#define R600_CB_CNTL__CB_CLEAR_RED			0
+#define R600_CB_CNTL__CB_CLEAR_GREEN			1
+#define R600_CB_CNTL__CB_CLEAR_BLUE			2
+#define R600_CB_CNTL__CB_CLEAR_ALPHA			3
+#define R600_CB_CNTL__CB_SHADER_MASK			4
+#define R600_CB_CNTL__CB_TARGET_MASK			5
+#define R600_CB_CNTL__CB_FOG_RED			6
+#define R600_CB_CNTL__CB_FOG_GREEN			7
+#define R600_CB_CNTL__CB_FOG_BLUE			8
+#define R600_CB_CNTL__CB_COLOR_CONTROL			9
+#define R600_CB_CNTL__PA_SC_AA_CONFIG			10
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX			11
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX			12
+#define R600_CB_CNTL__CB_CLRCMP_CONTROL			13
+#define R600_CB_CNTL__CB_CLRCMP_SRC			14
+#define R600_CB_CNTL__CB_CLRCMP_DST			15
+#define R600_CB_CNTL__CB_CLRCMP_MSK			16
+#define R600_CB_CNTL__PA_SC_AA_MASK			17
+#define R600_CB_CNTL_SIZE				18
+#define R600_CB_CNTL_PM4				128
 /* R600_RASTERIZER */
 #define R600_RASTERIZER__SPI_INTERP_CONTROL_0			0
-#define R600_RASTERIZER__PA_CL_CLIP_CNTL			3
-#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL			4
-#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL			7
-#define R600_RASTERIZER__PA_CL_NANINF_CNTL			8
-#define R600_RASTERIZER__PA_SU_POINT_SIZE			11
-#define R600_RASTERIZER__PA_SU_POINT_MINMAX			12
-#define R600_RASTERIZER__PA_SU_LINE_CNTL			13
-#define R600_RASTERIZER__PA_SC_LINE_STIPPLE			14
-#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL			17
-#define R600_RASTERIZER__PA_SC_LINE_CNTL			20
-#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ			23
-#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ			24
-#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ			25
-#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ			26
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL		29
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP		30
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE		31
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET		32
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE		33
-#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET		34
+#define R600_RASTERIZER__PA_CL_CLIP_CNTL			1
+#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL			2
+#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL			3
+#define R600_RASTERIZER__PA_CL_NANINF_CNTL			4
+#define R600_RASTERIZER__PA_SU_POINT_SIZE			5
+#define R600_RASTERIZER__PA_SU_POINT_MINMAX			6
+#define R600_RASTERIZER__PA_SU_LINE_CNTL			7
+#define R600_RASTERIZER__PA_SC_LINE_STIPPLE			8
+#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL			9
+#define R600_RASTERIZER__PA_SC_LINE_CNTL			10
+#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ			11
+#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ			12
+#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ			13
+#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ			14
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL			15
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP			16
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE			17
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET			18
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE			19
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET			20
+#define R600_RASTERIZER_SIZE				21
+#define R600_RASTERIZER_PM4				128
 /* R600_VIEWPORT */
 #define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0			0
 #define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0			1
-#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0			4
-#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0			7
-#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0			10
-#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0			13
-#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0			16
-#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0			19
-#define R600_VIEWPORT__PA_CL_VTE_CNTL				22
+#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0			2
+#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0			3
+#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0			4
+#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0			5
+#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0			6
+#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0			7
+#define R600_VIEWPORT__PA_CL_VTE_CNTL			8
+#define R600_VIEWPORT_SIZE				9
+#define R600_VIEWPORT_PM4				128
 /* R600_SCISSOR */
 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL			0
 #define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR			1
-#define R600_SCISSOR__PA_SC_WINDOW_OFFSET			4
-#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL			5
-#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR			6
-#define R600_SCISSOR__PA_SC_CLIPRECT_RULE			7
-#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL			8
-#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR			9
-#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL			10
-#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR			11
-#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL			12
-#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR			13
-#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL			14
-#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR			15
-#define R600_SCISSOR__PA_SC_EDGERULE				16
-#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL			19
-#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR			20
-#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL			23
-#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR			24
+#define R600_SCISSOR__PA_SC_WINDOW_OFFSET			2
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL			3
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR			4
+#define R600_SCISSOR__PA_SC_CLIPRECT_RULE			5
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL			6
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR			7
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL			8
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR			9
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL			10
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR			11
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL			12
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR			13
+#define R600_SCISSOR__PA_SC_EDGERULE			14
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL			15
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR			16
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL			17
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR			18
+#define R600_SCISSOR_SIZE				19
+#define R600_SCISSOR_PM4				128
 /* R600_BLEND */
-#define R600_BLEND__CB_BLEND_RED				0
-#define R600_BLEND__CB_BLEND_GREEN				1
-#define R600_BLEND__CB_BLEND_BLUE				2
-#define R600_BLEND__CB_BLEND_ALPHA				3
-#define R600_BLEND__CB_BLEND0_CONTROL				6
-#define R600_BLEND__CB_BLEND1_CONTROL				7
-#define R600_BLEND__CB_BLEND2_CONTROL				8
-#define R600_BLEND__CB_BLEND3_CONTROL				9
-#define R600_BLEND__CB_BLEND4_CONTROL				10
-#define R600_BLEND__CB_BLEND5_CONTROL				11
-#define R600_BLEND__CB_BLEND6_CONTROL				12
-#define R600_BLEND__CB_BLEND7_CONTROL				13
-#define R600_BLEND__CB_BLEND_CONTROL				16
+#define R600_BLEND__CB_BLEND_RED			0
+#define R600_BLEND__CB_BLEND_GREEN			1
+#define R600_BLEND__CB_BLEND_BLUE			2
+#define R600_BLEND__CB_BLEND_ALPHA			3
+#define R600_BLEND__CB_BLEND0_CONTROL			4
+#define R600_BLEND__CB_BLEND1_CONTROL			5
+#define R600_BLEND__CB_BLEND2_CONTROL			6
+#define R600_BLEND__CB_BLEND3_CONTROL			7
+#define R600_BLEND__CB_BLEND4_CONTROL			8
+#define R600_BLEND__CB_BLEND5_CONTROL			9
+#define R600_BLEND__CB_BLEND6_CONTROL			10
+#define R600_BLEND__CB_BLEND7_CONTROL			11
+#define R600_BLEND__CB_BLEND_CONTROL			12
+#define R600_BLEND_SIZE				13
+#define R600_BLEND_PM4				128
 /* R600_DSA */
-#define R600_DSA__DB_STENCIL_CLEAR				0
-#define R600_DSA__DB_DEPTH_CLEAR				1
-#define R600_DSA__SX_ALPHA_TEST_CONTROL				4
-#define R600_DSA__DB_STENCILREFMASK				7
-#define R600_DSA__DB_STENCILREFMASK_BF				8
-#define R600_DSA__SX_ALPHA_REF					9
-#define R600_DSA__SPI_FOG_FUNC_SCALE				12
-#define R600_DSA__SPI_FOG_FUNC_BIAS				13
-#define R600_DSA__SPI_FOG_CNTL					16
-#define R600_DSA__DB_DEPTH_CONTROL				19
-#define R600_DSA__DB_SHADER_CONTROL				22
-#define R600_DSA__DB_RENDER_CONTROL				25
-#define R600_DSA__DB_RENDER_OVERRIDE				26
-#define R600_DSA__DB_SRESULTS_COMPARE_STATE1			29
-#define R600_DSA__DB_PRELOAD_CONTROL				30
-#define R600_DSA__DB_ALPHA_TO_MASK				33
+#define R600_DSA__DB_STENCIL_CLEAR			0
+#define R600_DSA__DB_DEPTH_CLEAR			1
+#define R600_DSA__SX_ALPHA_TEST_CONTROL			2
+#define R600_DSA__DB_STENCILREFMASK			3
+#define R600_DSA__DB_STENCILREFMASK_BF			4
+#define R600_DSA__SX_ALPHA_REF			5
+#define R600_DSA__SPI_FOG_FUNC_SCALE			6
+#define R600_DSA__SPI_FOG_FUNC_BIAS			7
+#define R600_DSA__SPI_FOG_CNTL			8
+#define R600_DSA__DB_DEPTH_CONTROL			9
+#define R600_DSA__DB_SHADER_CONTROL			10
+#define R600_DSA__DB_RENDER_CONTROL			11
+#define R600_DSA__DB_RENDER_OVERRIDE			12
+#define R600_DSA__DB_SRESULTS_COMPARE_STATE1			13
+#define R600_DSA__DB_PRELOAD_CONTROL			14
+#define R600_DSA__DB_ALPHA_TO_MASK			15
+#define R600_DSA_SIZE				16
+#define R600_DSA_PM4				128
 /* R600_VS_SHADER */
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_0			0
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_1			1
@@ -394,25 +457,25 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_29			29
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_30			30
 #define R600_VS_SHADER__SQ_VTX_SEMANTIC_31			31
-#define R600_VS_SHADER__SPI_VS_OUT_ID_0				34
-#define R600_VS_SHADER__SPI_VS_OUT_ID_1				35
-#define R600_VS_SHADER__SPI_VS_OUT_ID_2				36
-#define R600_VS_SHADER__SPI_VS_OUT_ID_3				37
-#define R600_VS_SHADER__SPI_VS_OUT_ID_4				38
-#define R600_VS_SHADER__SPI_VS_OUT_ID_5				39
-#define R600_VS_SHADER__SPI_VS_OUT_ID_6				40
-#define R600_VS_SHADER__SPI_VS_OUT_ID_7				41
-#define R600_VS_SHADER__SPI_VS_OUT_ID_8				42
-#define R600_VS_SHADER__SPI_VS_OUT_ID_9				43
-#define R600_VS_SHADER__SPI_VS_OUT_CONFIG			46
-#define R600_VS_SHADER__SQ_PGM_START_VS				49
-#define R600_VS_SHADER__SQ_PGM_START_VS_BO_ID			51
-#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS			54
-#define R600_VS_SHADER__SQ_PGM_START_FS				57
-#define R600_VS_SHADER__SQ_PGM_START_FS_BO_ID			59
-#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS			62
-#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS			65
-#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS			68
+#define R600_VS_SHADER__SPI_VS_OUT_ID_0			32
+#define R600_VS_SHADER__SPI_VS_OUT_ID_1			33
+#define R600_VS_SHADER__SPI_VS_OUT_ID_2			34
+#define R600_VS_SHADER__SPI_VS_OUT_ID_3			35
+#define R600_VS_SHADER__SPI_VS_OUT_ID_4			36
+#define R600_VS_SHADER__SPI_VS_OUT_ID_5			37
+#define R600_VS_SHADER__SPI_VS_OUT_ID_6			38
+#define R600_VS_SHADER__SPI_VS_OUT_ID_7			39
+#define R600_VS_SHADER__SPI_VS_OUT_ID_8			40
+#define R600_VS_SHADER__SPI_VS_OUT_ID_9			41
+#define R600_VS_SHADER__SPI_VS_OUT_CONFIG			42
+#define R600_VS_SHADER__SQ_PGM_START_VS			43
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS			44
+#define R600_VS_SHADER__SQ_PGM_START_FS			45
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS			46
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS			47
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS			48
+#define R600_VS_SHADER_SIZE				49
+#define R600_VS_SHADER_PM4				128
 /* R600_PS_SHADER */
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0			0
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1			1
@@ -446,104 +509,158 @@ void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29			29
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30			30
 #define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31			31
-#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0			34
-#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1			35
-#define R600_PS_SHADER__SPI_INPUT_Z				38
-#define R600_PS_SHADER__SQ_PGM_START_PS				41
-#define R600_PS_SHADER__SQ_PGM_START_PS_BO_ID			43
-#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS			46
-#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS			47
-#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS			50
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0			32
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1			33
+#define R600_PS_SHADER__SPI_INPUT_Z			34
+#define R600_PS_SHADER__SQ_PGM_START_PS			35
+#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS			36
+#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS			37
+#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS			38
+#define R600_PS_SHADER_SIZE				39
+#define R600_PS_SHADER_PM4				128
 /* R600_PS_CONSTANT */
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0			0
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0			1
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0			2
 #define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0			3
+#define R600_PS_CONSTANT_SIZE				4
+#define R600_PS_CONSTANT_PM4				128
 /* R600_VS_CONSTANT */
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256			0
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256			1
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256			2
 #define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256			3
+#define R600_VS_CONSTANT_SIZE				4
+#define R600_VS_CONSTANT_PM4				128
 /* R600_PS_RESOURCE */
-#define R600_RESOURCE__RESOURCE_WORD0				0
-#define R600_RESOURCE__RESOURCE_WORD1				1
-#define R600_RESOURCE__RESOURCE_WORD2				2
-#define R600_RESOURCE__RESOURCE_WORD3				3
-#define R600_RESOURCE__RESOURCE_WORD4				4
-#define R600_RESOURCE__RESOURCE_WORD5				5
-#define R600_RESOURCE__RESOURCE_WORD6				6
-#define R600_RESOURCE__RESOURCE_BO0_ID				8
-#define R600_RESOURCE__RESOURCE_BO1_ID				10
+#define R600_PS_RESOURCE__RESOURCE0_WORD0			0
+#define R600_PS_RESOURCE__RESOURCE0_WORD1			1
+#define R600_PS_RESOURCE__RESOURCE0_WORD2			2
+#define R600_PS_RESOURCE__RESOURCE0_WORD3			3
+#define R600_PS_RESOURCE__RESOURCE0_WORD4			4
+#define R600_PS_RESOURCE__RESOURCE0_WORD5			5
+#define R600_PS_RESOURCE__RESOURCE0_WORD6			6
+#define R600_PS_RESOURCE_SIZE				7
+#define R600_PS_RESOURCE_PM4				128
+/* R600_VS_RESOURCE */
+#define R600_VS_RESOURCE__RESOURCE160_WORD0			0
+#define R600_VS_RESOURCE__RESOURCE160_WORD1			1
+#define R600_VS_RESOURCE__RESOURCE160_WORD2			2
+#define R600_VS_RESOURCE__RESOURCE160_WORD3			3
+#define R600_VS_RESOURCE__RESOURCE160_WORD4			4
+#define R600_VS_RESOURCE__RESOURCE160_WORD5			5
+#define R600_VS_RESOURCE__RESOURCE160_WORD6			6
+#define R600_VS_RESOURCE_SIZE				7
+#define R600_VS_RESOURCE_PM4				128
+/* R600_FS_RESOURCE */
+#define R600_FS_RESOURCE__RESOURCE320_WORD0			0
+#define R600_FS_RESOURCE__RESOURCE320_WORD1			1
+#define R600_FS_RESOURCE__RESOURCE320_WORD2			2
+#define R600_FS_RESOURCE__RESOURCE320_WORD3			3
+#define R600_FS_RESOURCE__RESOURCE320_WORD4			4
+#define R600_FS_RESOURCE__RESOURCE320_WORD5			5
+#define R600_FS_RESOURCE__RESOURCE320_WORD6			6
+#define R600_FS_RESOURCE_SIZE				7
+#define R600_FS_RESOURCE_PM4				128
+/* R600_GS_RESOURCE */
+#define R600_GS_RESOURCE__RESOURCE336_WORD0			0
+#define R600_GS_RESOURCE__RESOURCE336_WORD1			1
+#define R600_GS_RESOURCE__RESOURCE336_WORD2			2
+#define R600_GS_RESOURCE__RESOURCE336_WORD3			3
+#define R600_GS_RESOURCE__RESOURCE336_WORD4			4
+#define R600_GS_RESOURCE__RESOURCE336_WORD5			5
+#define R600_GS_RESOURCE__RESOURCE336_WORD6			6
+#define R600_GS_RESOURCE_SIZE				7
+#define R600_GS_RESOURCE_PM4				128
 /* R600_PS_SAMPLER */
 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0			0
 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0			1
 #define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0			2
+#define R600_PS_SAMPLER_SIZE				3
+#define R600_PS_SAMPLER_PM4				128
 /* R600_VS_SAMPLER */
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18		0
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18		1
-#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18		2
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18			0
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18			1
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18			2
+#define R600_VS_SAMPLER_SIZE				3
+#define R600_VS_SAMPLER_PM4				128
 /* R600_GS_SAMPLER */
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36		0
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36		1
-#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36		2
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36			0
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36			1
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36			2
+#define R600_GS_SAMPLER_SIZE				3
+#define R600_GS_SAMPLER_PM4				128
 /* R600_PS_SAMPLER_BORDER */
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED	0
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN	1
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE	2
-#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA	3
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED			0
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN			1
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE			2
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA			3
+#define R600_PS_SAMPLER_BORDER_SIZE				4
+#define R600_PS_SAMPLER_BORDER_PM4				128
 /* R600_VS_SAMPLER_BORDER */
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED	0
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN	1
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE	2
-#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA	3
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED			0
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN			1
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE			2
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA			3
+#define R600_VS_SAMPLER_BORDER_SIZE				4
+#define R600_VS_SAMPLER_BORDER_PM4				128
 /* R600_GS_SAMPLER_BORDER */
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED	0
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN	1
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE	2
-#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA	3
-/* R600_CB */
-#define R600_CB__CB_COLOR0_BASE					0
-#define R600_CB__CB_COLOR0_BASE_BO_ID				2
-#define R600_CB__CB_COLOR0_INFO					5
-#define R600_CB__CB_COLOR0_SIZE					8
-#define R600_CB__CB_COLOR0_VIEW					11
-#define R600_CB__CB_COLOR0_FRAG					14
-#define R600_CB__CB_COLOR0_FRAG_BO_ID				16
-#define R600_CB__CB_COLOR0_TILE					19
-#define R600_CB__CB_COLOR0_TILE_BO_ID				21
-#define R600_CB__CB_COLOR0_MASK					24
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED			0
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN			1
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE			2
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA			3
+#define R600_GS_SAMPLER_BORDER_SIZE				4
+#define R600_GS_SAMPLER_BORDER_PM4				128
+/* R600_CB0 */
+#define R600_CB0__CB_COLOR0_BASE			0
+#define R600_CB0__CB_COLOR0_INFO			1
+#define R600_CB0__CB_COLOR0_SIZE			2
+#define R600_CB0__CB_COLOR0_VIEW			3
+#define R600_CB0__CB_COLOR0_FRAG			4
+#define R600_CB0__CB_COLOR0_TILE			5
+#define R600_CB0__CB_COLOR0_MASK			6
+#define R600_CB0_SIZE				7
+#define R600_CB0_PM4				128
 /* R600_DB */
-#define R600_DB__DB_DEPTH_BASE					0
-#define R600_DB__DB_DEPTH_BASE_BO_ID				2
-#define R600_DB__DB_DEPTH_SIZE					5
-#define R600_DB__DB_DEPTH_VIEW					6
-#define R600_DB__DB_DEPTH_INFO					9
-#define R600_DB__DB_HTILE_SURFACE				12
-#define R600_DB__DB_PREFETCH_LIMIT				15
+#define R600_DB__DB_DEPTH_BASE			0
+#define R600_DB__DB_DEPTH_SIZE			1
+#define R600_DB__DB_DEPTH_VIEW			2
+#define R600_DB__DB_DEPTH_INFO			3
+#define R600_DB__DB_HTILE_SURFACE			4
+#define R600_DB__DB_PREFETCH_LIMIT			5
+#define R600_DB_SIZE				6
+#define R600_DB_PM4				128
 /* R600_VGT */
-#define R600_VGT__VGT_MAX_VTX_INDX				0
-#define R600_VGT__VGT_MIN_VTX_INDX				1
-#define R600_VGT__VGT_INDX_OFFSET				2
-#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX			3
-#define R600_VGT__VGT_PRIMITIVE_TYPE				6
-#define R600_VGT__VGT_DMA_INDEX_TYPE				8
-#define R600_VGT__VGT_DMA_NUM_INSTANCES				10
-/* R600_DRAW_AUTO */
-#define R600_DRAW_AUTO__VGT_NUM_INDICES				0
-#define R600_DRAW_AUTO__VGT_DRAW_INITIATOR			1
+#define R600_VGT__VGT_PRIMITIVE_TYPE			0
+#define R600_VGT__VGT_MAX_VTX_INDX			1
+#define R600_VGT__VGT_MIN_VTX_INDX			2
+#define R600_VGT__VGT_INDX_OFFSET			3
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX			4
+#define R600_VGT__VGT_DMA_INDEX_TYPE			5
+#define R600_VGT__VGT_PRIMITIVEID_EN			6
+#define R600_VGT__VGT_DMA_NUM_INSTANCES			7
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN			8
+#define R600_VGT__VGT_INSTANCE_STEP_RATE_0			9
+#define R600_VGT__VGT_INSTANCE_STEP_RATE_1			10
+#define R600_VGT_SIZE				11
+#define R600_VGT_PM4				128
 /* R600_DRAW */
-#define R600_DRAW__VGT_DMA_BASE					0
-#define R600_DRAW__VGT_DMA_BASE_HI				1
-#define R600_DRAW__VGT_NUM_INDICES				2
-#define R600_DRAW__VGT_DRAW_INITIATOR				3
-#define R600_DRAW__INDICES_BO_ID				5
-/* R600_UCP */
-#define R600_UCP__PA_CL_UCP_X_0					0
-#define R600_UCP__PA_CL_UCP_Y_0					1
-#define R600_UCP__PA_CL_UCP_Z_0					2
-#define R600_UCP__PA_CL_UCP_W_0					3
+#define R600_DRAW__VGT_NUM_INDICES			0
+#define R600_DRAW__VGT_DMA_BASE_HI			1
+#define R600_DRAW__VGT_DMA_BASE			2
+#define R600_DRAW__VGT_DRAW_INITIATOR			3
+#define R600_DRAW_SIZE				4
+#define R600_DRAW_PM4				128
+/* R600_CLIP */
+#define R600_CLIP__PA_CL_UCP_X_0  0
+#define R600_CLIP__PA_CL_UCP_Y_0  1
+#define R600_CLIP__PA_CL_UCP_Z_0  2
+#define R600_CLIP__PA_CL_UCP_W_0  3
+#define R600_CLIP_SIZE  4
+#define R600_CLIP_PM4 128
 /* R600 QUERY BEGIN/END */
-#define R600_QUERY__OFFSET					0
-#define R600_QUERY__BO_ID					3
+#define R600_QUERY__OFFSET			0
+#define R600_QUERY_SIZE				1
+#define R600_QUERY_PM4				128
 
 #endif
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 7941563215..9b7c11bdc0 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -30,41 +30,377 @@
 #include "radeon_priv.h"
 #include "r600d.h"
 
-static const struct radeon_type R600_types[];
-static const struct radeon_type R700_types[];
-#define R600_FLUSH_RESOURCE	((~C_0085F0_TC_ACTION_ENA) | (~C_0085F0_VC_ACTION_ENA))
-#define R600_FLUSH_CB0		(~C_0085F0_CB0_DEST_BASE_ENA)
-#define R600_FLUSH_CB1		(~C_0085F0_CB1_DEST_BASE_ENA)
-#define R600_FLUSH_CB2		(~C_0085F0_CB2_DEST_BASE_ENA)
-#define R600_FLUSH_CB3		(~C_0085F0_CB3_DEST_BASE_ENA)
-#define R600_FLUSH_CB4		(~C_0085F0_CB4_DEST_BASE_ENA)
-#define R600_FLUSH_CB5		(~C_0085F0_CB5_DEST_BASE_ENA)
-#define R600_FLUSH_CB6		(~C_0085F0_CB6_DEST_BASE_ENA)
-#define R600_FLUSH_CB7		(~C_0085F0_CB7_DEST_BASE_ENA)
-#define R600_FLUSH_DB		(~C_0085F0_DB_DEST_BASE_ENA)
-#define R600_DIRTY_ALL		0xFFFFFFFF
-#define R600_DIRTY_ALL2		(R600_FLUSH_RESOURCE | R600_FLUSH_DB | R600_FLUSH_CB0\
-				R600_FLUSH_CB1 | R600_FLUSH_CB2 | R600_FLUSH_CB3\
-				R600_FLUSH_CB4 | R600_FLUSH_CB5 | R600_FLUSH_CB6\
-				R600_FLUSH_CB7)
+static int r600_state_pm4_resource(struct radeon_state *state);
+static int r600_state_pm4_cb0(struct radeon_state *state);
+static int r600_state_pm4_vgt(struct radeon_state *state);
+static int r600_state_pm4_db(struct radeon_state *state);
+static int r600_state_pm4_shader(struct radeon_state *state);
+static int r600_state_pm4_draw(struct radeon_state *state);
+static int r600_state_pm4_config(struct radeon_state *state);
+static int r600_state_pm4_generic(struct radeon_state *state);
+static int r600_state_pm4_query_begin(struct radeon_state *state);
+static int r600_state_pm4_query_end(struct radeon_state *state);
+static int r700_state_pm4_config(struct radeon_state *state);
+static int r700_state_pm4_cb0(struct radeon_state *state);
+static int r700_state_pm4_db(struct radeon_state *state);
 
-static int r600_ctx_bo_flush(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement)
+#include "r600_states.h"
+
+/*
+ * r600/r700 state functions
+ */
+static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
+{
+	const struct radeon_register *regs = state->radeon->type[state->type].regs;
+	unsigned i;
+	int r;
+
+	if (!offset) {
+		fprintf(stderr, "%s invalid register for state %d %d\n",
+			__func__, state->type, id);
+		return -EINVAL;
+	}
+	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		for (i = 0; i < nreg; i++) {
+			if (regs[id + i].need_reloc) {
+				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+				if (r)
+					return r;
+				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+			}
+		}
+		return 0;
+	}
+	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		for (i = 0; i < nreg; i++) {
+			if (regs[id + i].need_reloc) {
+				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+				if (r)
+					return r;
+				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+			}
+		}
+		return 0;
+	}
+	if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_ALU_CONST, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_ALU_CONST_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		return 0;
+	}
+	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		return 0;
+	}
+	fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset);
+	return -EINVAL;
+}
+
+static int r600_state_pm4_generic(struct radeon_state *state)
+{
+	struct radeon *radeon = state->radeon;
+	unsigned i, offset, nreg, type, coffset, loffset, soffset;
+	unsigned start;
+	int r;
+
+	if (!state->nstates)
+		return 0;
+	type = state->type;
+	soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride;
+	offset = loffset = radeon->type[type].regs[0].offset + soffset;
+	start = 0;
+	for (i = 1, nreg = 1; i < state->nstates; i++) {
+		coffset = radeon->type[type].regs[i].offset + soffset;
+		if (coffset == (loffset + 4)) {
+			nreg++;
+			loffset = coffset;
+		} else {
+			r = r600_state_pm4_bytecode(state, offset, start, nreg);
+			if (r) {
+				fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg);
+				return r;
+			}
+			offset = loffset = coffset;
+			nreg = 1;
+			start = i;
+		}
+	}
+	return r600_state_pm4_bytecode(state, offset, start, nreg);
+}
+
+static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags)
+{
+	unsigned i, j, add, size;
+
+	state->nreloc = 0;
+	for (i = 0; i < state->nbo; i++) {
+		for (j = 0, add = 1; j < state->nreloc; j++) {
+			if (state->bo[state->reloc_bo_id[j]] == state->bo[i]) {
+				add = 0;
+				break;
+			}
+		}
+		if (add) {
+			state->reloc_bo_id[state->nreloc++] = i;
+		}
+	}
+	for (i = 0; i < state->nreloc; i++) {
+		size = (state->bo[state->reloc_bo_id[i]]->size + 255) >> 8;
+		state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
+		state->pm4[state->cpm4++] = flags;
+		state->pm4[state->cpm4++] = size;
+		state->pm4[state->cpm4++] = 0x00000000;
+		state->pm4[state->cpm4++] = 0x0000000A;
+		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+		state->reloc_pm4_id[i] = state->cpm4;
+		state->pm4[state->cpm4++] = state->bo[state->reloc_bo_id[i]]->handle;
+	}
+}
+
+static int r600_state_pm4_cb0(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
+				S_0085F0_CB0_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
+	state->pm4[state->cpm4++] = 0x00000002;
+	return 0;
+}
+
+static int r700_state_pm4_cb0(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
+				S_0085F0_CB0_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	return 0;
+}
+
+static int r600_state_pm4_db(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
+				S_0085F0_DB_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
+	state->pm4[state->cpm4++] = 0x00000001;
+	return 0;
+}
+
+static int r700_state_pm4_db(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
+				S_0085F0_DB_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	return 0;
+}
+
+static int r600_state_pm4_config(struct radeon_state *state)
+{
+	state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0);
+	state->pm4[state->cpm4++] = 0x00000000;
+	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
+	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	state->pm4[state->cpm4++] = 0x00000010;
+	state->pm4[state->cpm4++] = 0x00028000;
+	return r600_state_pm4_generic(state);
+}
+
+static int r600_state_pm4_query_begin(struct radeon_state *state)
+{
+	int r;
+
+	state->cpm4 = 0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = 0x0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	return 0;
+}
+
+static int r600_state_pm4_query_end(struct radeon_state *state)
+{
+	int r;
+
+	state->cpm4 = 0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
+	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = 0x0;
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	return 0;
+}
+
+static int r700_state_pm4_config(struct radeon_state *state)
+{
+	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
+	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	state->pm4[state->cpm4++] = 0x00000010;
+	state->pm4[state->cpm4++] = 0x00028000;
+	return r600_state_pm4_generic(state);
+}
+
+static int r600_state_pm4_shader(struct radeon_state *state)
+{
+	r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1));
+	return r600_state_pm4_generic(state);
+}
+
+static int r600_state_pm4_vgt(struct radeon_state *state)
+{
+	int r;
+
+	r = r600_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, R600_VGT__VGT_MAX_VTX_INDX, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, R600_VGT__VGT_MIN_VTX_INDX, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, R600_VGT__VGT_INDX_OFFSET, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, R600_VGT__VGT_PRIMITIVE_TYPE, 1);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0);
+	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_INDEX_TYPE];
+	state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0);
+	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_NUM_INSTANCES];
+	return 0;
+}
+
+static int r600_state_pm4_draw(struct radeon_state *state)
 {
-	unsigned size;
+	unsigned i;
+	int r;
 
-	if (7 > ctx->npm4) {
-		return -EBUSY;
+	if (state->nbo) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX, 3);
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE];
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE_HI];
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
+		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+		r = radeon_state_reloc(state, state->cpm4, 0);
+		if (r)
+			return r;
+		state->pm4[state->cpm4++] = state->bo[0]->handle;
+	} else if  (state->nimmd) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1);
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
+		for (i = 0; i < state->nimmd; i++) {
+			state->pm4[state->cpm4++] = state->immd[i];
+		}
+	} else {
+		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
 	}
-	size = (bo->size + 255) >> 8;
-	ctx->pm4[ctx->id++] = PKT3(PKT3_SURFACE_SYNC, 3);
-	ctx->pm4[ctx->id++] = flags;
-	ctx->pm4[ctx->id++] = size;
-	ctx->pm4[ctx->id++] = 0x00000000;
-	ctx->pm4[ctx->id++] = 0x0000000A;
-	ctx->pm4[ctx->id++] = PKT3(PKT3_NOP, 0);
-	ctx->pm4[ctx->id++] = 0x00000000;
-	ctx->npm4 -= 7;
-	return radeon_ctx_reloc(ctx, bo, ctx->id - 1, placement);
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
+	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
+	return 0;
+}
+
+static int r600_state_pm4_resource(struct radeon_state *state)
+{
+	u32 flags, type, nbo, offset, soffset;
+	int r;
+
+	soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride;
+	type = G_038018_TYPE(state->states[6]);
+	switch (type) {
+	case 2:
+		flags = S_0085F0_TC_ACTION_ENA(1);
+		nbo = 2;
+		break;
+	case 3:
+		flags = S_0085F0_VC_ACTION_ENA(1);
+		nbo = 1;
+		break;
+	default:
+		return 0;
+	}
+	if (state->nbo != nbo) {
+		fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo);
+		return -EINVAL;
+	}
+	r600_state_pm4_with_flush(state, flags);
+	offset = state->radeon->type[state->type].regs[0].offset + soffset;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7);
+	state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = state->states[1];
+	state->pm4[state->cpm4++] = state->states[2];
+	state->pm4[state->cpm4++] = state->states[3];
+	state->pm4[state->cpm4++] = state->states[4];
+	state->pm4[state->cpm4++] = state->states[5];
+	state->pm4[state->cpm4++] = state->states[6];
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	if (type == 2) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+		r = radeon_state_reloc(state, state->cpm4, 1);
+		if (r)
+			return r;
+		state->pm4[state->cpm4++] = state->bo[1]->handle;
+	}
+	return 0;
 }
 
 int r600_init(struct radeon *radeon)
@@ -78,6 +414,7 @@ int r600_init(struct radeon *radeon)
 	case CHIP_RV635:
 	case CHIP_RS780:
 	case CHIP_RS880:
+		radeon->ntype = R600_NTYPE;
 		radeon->nstate = R600_NSTATE;
 		radeon->type = R600_types;
 		break;
@@ -85,6 +422,7 @@ int r600_init(struct radeon *radeon)
 	case CHIP_RV730:
 	case CHIP_RV710:
 	case CHIP_RV740:
+		radeon->ntype = R600_NTYPE;
 		radeon->nstate = R600_NSTATE;
 		radeon->type = R700_types;
 		break;
@@ -93,7696 +431,5 @@ int r600_init(struct radeon *radeon)
 			__func__, radeon->device);
 		return -EINVAL;
 	}
-	radeon->bo_flush = &r600_ctx_bo_flush;
 	return 0;
 }
-
-/* CONFIG */
-#define R600_CONFIG_header_cpm4 12
-static const u32 R600_CONFIG_header_pm4[R600_CONFIG_header_cpm4] = {
-	0xC0002400,
-	0x00000000,
-	0xC0012800,
-	0x80000000,
-	0x80000000,
-	0xC0004600,
-	0x00000016,
-	0xC0016800,
-	0x00000010,
-	0x00028000,
-	0xC0066800,
-	0x00000300,
-};
-#define R700_CONFIG_header_cpm4 10
-u32 R700_CONFIG_header_pm4[R700_CONFIG_header_cpm4] = {
-	0xC0012800,
-	0x80000000,
-	0x80000000,
-	0xC0004600,
-	0x00000016,
-	0xC0016800,
-	0x00000010,
-	0x00028000,
-	0xC0066800,
-	0x00000300,
-};
-#define R600_CONFIG_state_cpm4 67
-u32 R600_CONFIG_state_pm4[R600_CONFIG_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016800,
-	0x00000363,
-	0x00000000,
-	0xC0016800,
-	0x00000542,
-	0x00000000,
-	0xC0016800,
-	0x000005C5,
-	0x00000000,
-	0xC0016800,
-	0x0000060C,
-	0x00000000,
-	0xC0016800,
-	0x0000060E,
-	0x00000000,
-	0xC0016900,
-	0x000000D4,
-	0x00000000,
-	0xC0016900,
-	0x000001B2,
-	0x00000000,
-	0xC0016900,
-	0x000001E8,
-	0x00000000,
-	0xC0096900,
-	0x0000022A,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC00D6900,
-	0x00000284,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000293,
-	0x00000000,
-	0xC0036900,
-	0x000002AC,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x000002C8,
-	0x00000000,
-};
-#define R600_CB_CNTL_header_cpm4 2
-u32 R600_CB_CNTL_header_pm4[R600_CB_CNTL_header_cpm4] = {
-	0xC0046900,
-	0x00000048,
-};
-#define R600_CB_CNTL_state_cpm4 32
-u32 R600_CB_CNTL_state_pm4[R600_CB_CNTL_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0026900,
-	0x0000008E,
-	0x00000000,
-	0x00000000,
-	0xC0036900,
-	0x00000109,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000202,
-	0x00000000,
-	0xC0016900,
-	0x00000301,
-	0x00000000,
-	0xC0026900,
-	0x00000307,
-	0x00000000,
-	0x00000000,
-	0xC0046900,
-	0x0000030C,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000312,
-	0x00000000,
-};
-#define R600_RASTERIZER_header_cpm4 2
-u32 R600_RASTERIZER_header_pm4[R600_RASTERIZER_header_cpm4] = {
-	0xC0016900,
-	0x000001B5,
-};
-#define R600_RASTERIZER_state_cpm4 35
-u32 R600_RASTERIZER_state_pm4[R600_RASTERIZER_state_cpm4] = {
-	0x00000000,
-	0xC0026900,
-	0x00000204,
-	0x00000000,
-	0x00000000,
-	0xC0026900,
-	0x00000207,
-	0x00000000,
-	0x00000000,
-	0xC0046900,
-	0x00000280,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000292,
-	0x00000000,
-	0xC0016900,
-	0x00000300,
-	0x00000000,
-	0xC0046900,
-	0x00000303,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0066900,
-	0x0000037E,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-/* R600_VIEWPORT */
-#define R600_VIEWPORT_header_cpm4 2
-u32 R600_VIEWPORT_header_pm4[R600_VIEWPORT_header_cpm4] = {
-	0xC0026900,
-	0x000000B4,
-};
-#define R600_VIEWPORT_state_cpm4 23
-u32 R600_VIEWPORT_state_pm4[R600_VIEWPORT_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x0000010F,
-	0x00000000,
-	0xC0016900,
-	0x00000111,
-	0x00000000,
-	0xC0016900,
-	0x00000113,
-	0x00000000,
-	0xC0016900,
-	0x00000110,
-	0x00000000,
-	0xC0016900,
-	0x00000112,
-	0x00000000,
-	0xC0016900,
-	0x00000114,
-	0x00000000,
-	0xC0016900,
-	0x00000206,
-	0x00000000,
-};
-#define R600_SCISSOR_header_cpm4 2
-u32 R600_SCISSOR_header_pm4[R600_SCISSOR_header_cpm4] = {
-	0xC0026900,
-	0x0000000C,
-};
-#define R600_SCISSOR_state_cpm4 25
-u32 R600_SCISSOR_state_pm4[R600_SCISSOR_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0xC00D6900,
-	0x00000080,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0026900,
-	0x00000090,
-	0x00000000,
-	0x00000000,
-	0xC0026900,
-	0x00000094,
-	0x00000000,
-	0x00000000,
-};
-
-/* R600_BLEND */
-#define R600_BLEND_header_cpm4 2
-u32 R600_BLEND_header_pm4[R600_BLEND_header_cpm4] = {
-	0xC0046900,
-	0x00000105,
-};
-#define R600_BLEND_state_cpm4 17
-u32 R600_BLEND_state_pm4[R600_BLEND_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0086900,
-	0x000001E0,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000201,
-	0x00000000,
-};
-
-/* R600_DSA */
-#define R600_DSA_header_cpm4 2
-u32 R600_DSA_header_pm4[R600_DSA_header_cpm4] = {
-	0xC0026900,
-	0x0000000A,
-};
-#define R600_DSA_state_cpm4 34
-u32 R600_DSA_state_pm4[R600_DSA_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000104,
-	0x00000000,
-	0xC0036900,
-	0x0000010C,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0026900,
-	0x000001B8,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x000001B7,
-	0x00000000,
-	0xC0016900,
-	0x00000200,
-	0x00000000,
-	0xC0016900,
-	0x00000203,
-	0x00000000,
-	0xC0026900,
-	0x00000343,
-	0x00000000,
-	0x00000000,
-	0xC0026900,
-	0x0000034B,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000351,
-	0x00000000,
-};
-
-/* R600_UCP */
-#define R600_UCP_header_cpm4 2
-u32 R600_UCP0_header_pm4[R600_UCP_header_cpm4] = {
-	0xC0046900,
-	0x00000388,
-};
-u32 R600_UCP1_header_pm4[R600_UCP_header_cpm4] = {
-	0xC0046900,
-	0x0000038C,
-};
-u32 R600_UCP2_header_pm4[R600_UCP_header_cpm4] = {
-	0xC0046900,
-	0x00000390,
-};
-u32 R600_UCP3_header_pm4[R600_UCP_header_cpm4] = {
-	0xC0046900,
-	0x00000394,
-};
-u32 R600_UCP4_header_pm4[R600_UCP_header_cpm4] = {
-	0xC0046900,
-	0x00000398,
-};
-u32 R600_UCP5_header_pm4[R600_UCP_header_cpm4] = {
-	0xC0046900,
-	0x0000039C,
-};
-#define R600_UCP_state_cpm4 4
-u32 R600_UCP_state_pm4[R600_UCP_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-/* R600_VGT */
-#define R600_VGT_header_cpm4 2
-u32 R600_VGT_header_pm4[R600_VGT_header_cpm4] = {
-	0xC0046900,
-	0x00000100,
-};
-#define R600_VGT_state_cpm4 11
-u32 R600_VGT_state_pm4[R600_VGT_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016800,
-	0x00000256,
-	0x00000000,
-	0xC0002A00,
-	0x00000000,
-	0xC0002F00,
-	0x00000000,
-};
-
-/* R600_QUERY */
-#define R600_QUERY_header_cpm4 2
-u32 R600_QUERY_header_pm4[R600_QUERY_header_cpm4] = {
-	0xC0024600,
-	0x00000015,
-};
-#define R600_QUERY_state_cpm4 4
-u32 R600_QUERY_state_pm4[R600_QUERY_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-};
-
-/* R600_DRAW_AUTO */
-#define R600_DRAW_AUTO_header_cpm4 1
-u32 R600_DRAW_AUTO_header_pm4[R600_DRAW_AUTO_header_cpm4] = {
-	0xC0012D00,
-};
-#define R600_DRAW_AUTO_state_cpm4 4
-u32 R600_DRAW_AUTO_state_pm4[R600_DRAW_AUTO_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0xC0004600,
-	0x00000016,
-};
-
-/* R600_DRAW */
-#define R600_DRAW_header_cpm4 1
-u32 R600_DRAW_header_pm4[R600_DRAW_header_cpm4] = {
-	0xC0032B00,
-};
-#define R600_DRAW_state_cpm4 8
-u32 R600_DRAW_state_pm4[R600_DRAW_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0004600,
-	0x00000016,
-};
-
-/* R600_VS_SHADER */
-#define R600_VS_SHADER_header_cpm4 2
-u32 R600_VS_SHADER_header_pm4[R600_VS_SHADER_header_cpm4] = {
-	0xC0206900,
-	0x000000E0,
-};
-#define R600_VS_SHADER_state_cpm4 69
-u32 R600_VS_SHADER_state_pm4[R600_VS_SHADER_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC00A6900,
-	0x00000185,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x000001B1,
-	0x00000000,
-	0xC0016900,
-	0x00000216,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x0000021A,
-	0x00000000,
-	0xC0016900,
-	0x00000225,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000229,
-	0x00000000,
-	0xC0016900,
-	0x00000234,
-	0x00000000,
-	0xC0016900,
-	0x00000237,
-	0x00000000,
-};
-
-/* R600_PS_SHADER */
-#define R600_PS_SHADER_header_cpm4 2
-u32 R600_PS_SHADER_header_pm4[R600_PS_SHADER_header_cpm4] = {
-	0xC0206900,
-	0x00000191,
-};
-#define R600_PS_SHADER_state_cpm4 51
-u32 R600_PS_SHADER_state_pm4[R600_PS_SHADER_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0026900,
-	0x000001B3,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x000001B6,
-	0x00000000,
-	0xC0016900,
-	0x00000210,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0026900,
-	0x00000214,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000233,
-	0x00000000,
-};
-
-/* R600_DB */
-#define R600_DB_header_cpm4 2
-u32 R600_DB_header_pm4[R600_DB_header_cpm4] = {
-	0xC0016900,
-	0x00000003,
-};
-#define R600_DB_state_cpm4 18
-u32 R600_DB_state_pm4[R600_DB_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0026900,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0xC0016900,
-	0x00000004,
-	0x00000000,
-	0xC0016900,
-	0x00000349,
-	0x00000000,
-	0xC0016900,
-	0x0000034D,
-	0x00000000,
-	0xC0007300,
-	0x00000001,
-};
-
-/* R600_CB0 */
-#define R600_CB0_header_cpm4 2
-u32 R600_CB0_header_pm4[R600_CB0_header_cpm4] = {
-	0xC0016900,
-	0x00000010,
-};
-#define R600_CB0_state_cpm4 27
-u32 R600_CB0_state_pm4[R600_CB0_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000028,
-	0x00000000,
-	0xC0016900,
-	0x00000018,
-	0x00000000,
-	0xC0016900,
-	0x00000020,
-	0x00000000,
-	0xC0016900,
-	0x00000038,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000030,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000040,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CB1 */
-#define R600_CB1_header_cpm4 2
-u32 R600_CB1_header_pm4[R600_CB1_header_cpm4] = {
-	0xC0016900,
-	0x00000011,
-};
-#define R600_CB1_state_cpm4 27
-u32 R600_CB1_state_pm4[R600_CB1_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000029,
-	0x00000000,
-	0xC0016900,
-	0x00000019,
-	0x00000000,
-	0xC0016900,
-	0x00000021,
-	0x00000000,
-	0xC0016900,
-	0x00000039,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000031,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000041,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CB2 */
-#define R600_CB2_header_cpm4 2
-u32 R600_CB2_header_pm4[R600_CB2_header_cpm4] = {
-	0xC0016900,
-	0x00000012,
-};
-#define R600_CB2_state_cpm4 27
-u32 R600_CB2_state_pm4[R600_CB2_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000004,
-	0xC0016900,
-	0x0000002A,
-	0x00000000,
-	0xC0016900,
-	0x0000001A,
-	0x00000000,
-	0xC0016900,
-	0x00000022,
-	0x00000000,
-	0xC0016900,
-	0x0000003A,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000032,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000042,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CB3 */
-#define R600_CB3_header_cpm4 2
-u32 R600_CB3_header_pm4[R600_CB3_header_cpm4] = {
-	0xC0016900,
-	0x00000013,
-};
-#define R600_CB3_state_cpm4 27
-u32 R600_CB3_state_pm4[R600_CB3_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000004,
-	0xC0016900,
-	0x0000002B,
-	0x00000000,
-	0xC0016900,
-	0x0000001B,
-	0x00000000,
-	0xC0016900,
-	0x00000023,
-	0x00000000,
-	0xC0016900,
-	0x0000003B,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000033,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000043,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CB4 */
-#define R600_CB4_header_cpm4 2
-u32 R600_CB4_header_pm4[R600_CB4_header_cpm4] = {
-	0xC0016900,
-	0x00000014,
-};
-#define R600_CB4_state_cpm4 27
-u32 R600_CB4_state_pm4[R600_CB4_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000004,
-	0xC0016900,
-	0x0000002C,
-	0x00000000,
-	0xC0016900,
-	0x0000001C,
-	0x00000000,
-	0xC0016900,
-	0x00000024,
-	0x00000000,
-	0xC0016900,
-	0x0000003C,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000034,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000044,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CB5 */
-#define R600_CB5_header_cpm4 2
-u32 R600_CB5_header_pm4[R600_CB5_header_cpm4] = {
-	0xC0016900,
-	0x00000015,
-};
-#define R600_CB5_state_cpm4 27
-u32 R600_CB5_state_pm4[R600_CB5_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000004,
-	0xC0016900,
-	0x0000002D,
-	0x00000000,
-	0xC0016900,
-	0x0000001D,
-	0x00000000,
-	0xC0016900,
-	0x00000025,
-	0x00000000,
-	0xC0016900,
-	0x0000003D,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000035,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000045,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CB6 */
-#define R600_CB6_header_cpm4 2
-u32 R600_CB6_header_pm4[R600_CB6_header_cpm4] = {
-	0xC0016900,
-	0x00000016,
-};
-#define R600_CB6_state_cpm4 27
-u32 R600_CB6_state_pm4[R600_CB6_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000004,
-	0xC0016900,
-	0x0000002E,
-	0x00000000,
-	0xC0016900,
-	0x0000001E,
-	0x00000000,
-	0xC0016900,
-	0x00000026,
-	0x00000000,
-	0xC0016900,
-	0x0000003E,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000036,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000046,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CB7 */
-#define R600_CB7_header_cpm4 2
-u32 R600_CB7_header_pm4[R600_CB7_header_cpm4] = {
-	0xC0016900,
-	0x00000017,
-};
-#define R600_CB7_state_cpm4 27
-u32 R600_CB7_state_pm4[R600_CB7_state_cpm4] = {
-	0x00000000,
-	0xC0001000,
-	0x00000004,
-	0xC0016900,
-	0x0000002F,
-	0x00000000,
-	0xC0016900,
-	0x0000001F,
-	0x00000000,
-	0xC0016900,
-	0x00000027,
-	0x00000000,
-	0xC0016900,
-	0x0000003F,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000037,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-	0xC0016900,
-	0x00000047,
-	0x00000000,
-	0xC0007300,
-	0x00000002,
-};
-
-/* R600_CONSTANT */
-#define R600_CONSTANT_header_cpm4 2
-u32 R600_PS_CONSTANT0_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000000,
-};
-u32 R600_PS_CONSTANT1_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000004,
-};
-u32 R600_PS_CONSTANT2_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000008,
-};
-u32 R600_PS_CONSTANT3_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000000C,
-};
-u32 R600_PS_CONSTANT4_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000010,
-};
-u32 R600_PS_CONSTANT5_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000014,
-};
-u32 R600_PS_CONSTANT6_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000018,
-};
-u32 R600_PS_CONSTANT7_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000001C,
-};
-u32 R600_PS_CONSTANT8_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000020,
-};
-u32 R600_PS_CONSTANT9_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000024,
-};
-u32 R600_PS_CONSTANT10_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000028,
-};
-u32 R600_PS_CONSTANT11_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000002C,
-};
-u32 R600_PS_CONSTANT12_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000030,
-};
-u32 R600_PS_CONSTANT13_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000034,
-};
-u32 R600_PS_CONSTANT14_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000038,
-};
-u32 R600_PS_CONSTANT15_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000003C,
-};
-u32 R600_PS_CONSTANT16_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000040,
-};
-u32 R600_PS_CONSTANT17_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000044,
-};
-u32 R600_PS_CONSTANT18_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000048,
-};
-u32 R600_PS_CONSTANT19_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000004C,
-};
-u32 R600_PS_CONSTANT20_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000050,
-};
-u32 R600_PS_CONSTANT21_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000054,
-};
-u32 R600_PS_CONSTANT22_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000058,
-};
-u32 R600_PS_CONSTANT23_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000005C,
-};
-u32 R600_PS_CONSTANT24_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000060,
-};
-u32 R600_PS_CONSTANT25_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000064,
-};
-u32 R600_PS_CONSTANT26_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000068,
-};
-u32 R600_PS_CONSTANT27_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000006C,
-};
-u32 R600_PS_CONSTANT28_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000070,
-};
-u32 R600_PS_CONSTANT29_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000074,
-};
-u32 R600_PS_CONSTANT30_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000078,
-};
-u32 R600_PS_CONSTANT31_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000007C,
-};
-u32 R600_PS_CONSTANT32_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000080,
-};
-u32 R600_PS_CONSTANT33_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000084,
-};
-u32 R600_PS_CONSTANT34_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000088,
-};
-u32 R600_PS_CONSTANT35_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000008C,
-};
-u32 R600_PS_CONSTANT36_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000090,
-};
-u32 R600_PS_CONSTANT37_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000094,
-};
-u32 R600_PS_CONSTANT38_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000098,
-};
-u32 R600_PS_CONSTANT39_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000009C,
-};
-u32 R600_PS_CONSTANT40_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000A0,
-};
-u32 R600_PS_CONSTANT41_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000A4,
-};
-u32 R600_PS_CONSTANT42_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000A8,
-};
-u32 R600_PS_CONSTANT43_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000AC,
-};
-u32 R600_PS_CONSTANT44_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000B0,
-};
-u32 R600_PS_CONSTANT45_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000B4,
-};
-u32 R600_PS_CONSTANT46_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000B8,
-};
-u32 R600_PS_CONSTANT47_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000BC,
-};
-u32 R600_PS_CONSTANT48_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000C0,
-};
-u32 R600_PS_CONSTANT49_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000C4,
-};
-u32 R600_PS_CONSTANT50_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000C8,
-};
-u32 R600_PS_CONSTANT51_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000CC,
-};
-u32 R600_PS_CONSTANT52_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000D0,
-};
-u32 R600_PS_CONSTANT53_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000D4,
-};
-u32 R600_PS_CONSTANT54_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000D8,
-};
-u32 R600_PS_CONSTANT55_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000DC,
-};
-u32 R600_PS_CONSTANT56_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000E0,
-};
-u32 R600_PS_CONSTANT57_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000E4,
-};
-u32 R600_PS_CONSTANT58_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000E8,
-};
-u32 R600_PS_CONSTANT59_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000EC,
-};
-u32 R600_PS_CONSTANT60_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000F0,
-};
-u32 R600_PS_CONSTANT61_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000F4,
-};
-u32 R600_PS_CONSTANT62_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000F8,
-};
-u32 R600_PS_CONSTANT63_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000000FC,
-};
-u32 R600_PS_CONSTANT64_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000100,
-};
-u32 R600_PS_CONSTANT65_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000104,
-};
-u32 R600_PS_CONSTANT66_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000108,
-};
-u32 R600_PS_CONSTANT67_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000010C,
-};
-u32 R600_PS_CONSTANT68_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000110,
-};
-u32 R600_PS_CONSTANT69_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000114,
-};
-u32 R600_PS_CONSTANT70_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000118,
-};
-u32 R600_PS_CONSTANT71_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000011C,
-};
-u32 R600_PS_CONSTANT72_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000120,
-};
-u32 R600_PS_CONSTANT73_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000124,
-};
-u32 R600_PS_CONSTANT74_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000128,
-};
-u32 R600_PS_CONSTANT75_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000012C,
-};
-u32 R600_PS_CONSTANT76_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000130,
-};
-u32 R600_PS_CONSTANT77_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000134,
-};
-u32 R600_PS_CONSTANT78_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000138,
-};
-u32 R600_PS_CONSTANT79_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000013C,
-};
-u32 R600_PS_CONSTANT80_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000140,
-};
-u32 R600_PS_CONSTANT81_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000144,
-};
-u32 R600_PS_CONSTANT82_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000148,
-};
-u32 R600_PS_CONSTANT83_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000014C,
-};
-u32 R600_PS_CONSTANT84_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000150,
-};
-u32 R600_PS_CONSTANT85_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000154,
-};
-u32 R600_PS_CONSTANT86_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000158,
-};
-u32 R600_PS_CONSTANT87_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000015C,
-};
-u32 R600_PS_CONSTANT88_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000160,
-};
-u32 R600_PS_CONSTANT89_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000164,
-};
-u32 R600_PS_CONSTANT90_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000168,
-};
-u32 R600_PS_CONSTANT91_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000016C,
-};
-u32 R600_PS_CONSTANT92_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000170,
-};
-u32 R600_PS_CONSTANT93_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000174,
-};
-u32 R600_PS_CONSTANT94_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000178,
-};
-u32 R600_PS_CONSTANT95_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000017C,
-};
-u32 R600_PS_CONSTANT96_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000180,
-};
-u32 R600_PS_CONSTANT97_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000184,
-};
-u32 R600_PS_CONSTANT98_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000188,
-};
-u32 R600_PS_CONSTANT99_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000018C,
-};
-u32 R600_PS_CONSTANT100_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000190,
-};
-u32 R600_PS_CONSTANT101_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000194,
-};
-u32 R600_PS_CONSTANT102_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000198,
-};
-u32 R600_PS_CONSTANT103_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000019C,
-};
-u32 R600_PS_CONSTANT104_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001A0,
-};
-u32 R600_PS_CONSTANT105_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001A4,
-};
-u32 R600_PS_CONSTANT106_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001A8,
-};
-u32 R600_PS_CONSTANT107_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001AC,
-};
-u32 R600_PS_CONSTANT108_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001B0,
-};
-u32 R600_PS_CONSTANT109_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001B4,
-};
-u32 R600_PS_CONSTANT110_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001B8,
-};
-u32 R600_PS_CONSTANT111_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001BC,
-};
-u32 R600_PS_CONSTANT112_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001C0,
-};
-u32 R600_PS_CONSTANT113_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001C4,
-};
-u32 R600_PS_CONSTANT114_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001C8,
-};
-u32 R600_PS_CONSTANT115_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001CC,
-};
-u32 R600_PS_CONSTANT116_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001D0,
-};
-u32 R600_PS_CONSTANT117_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001D4,
-};
-u32 R600_PS_CONSTANT118_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001D8,
-};
-u32 R600_PS_CONSTANT119_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001DC,
-};
-u32 R600_PS_CONSTANT120_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001E0,
-};
-u32 R600_PS_CONSTANT121_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001E4,
-};
-u32 R600_PS_CONSTANT122_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001E8,
-};
-u32 R600_PS_CONSTANT123_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001EC,
-};
-u32 R600_PS_CONSTANT124_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001F0,
-};
-u32 R600_PS_CONSTANT125_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001F4,
-};
-u32 R600_PS_CONSTANT126_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001F8,
-};
-u32 R600_PS_CONSTANT127_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000001FC,
-};
-u32 R600_PS_CONSTANT128_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000200,
-};
-u32 R600_PS_CONSTANT129_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000204,
-};
-u32 R600_PS_CONSTANT130_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000208,
-};
-u32 R600_PS_CONSTANT131_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000020C,
-};
-u32 R600_PS_CONSTANT132_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000210,
-};
-u32 R600_PS_CONSTANT133_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000214,
-};
-u32 R600_PS_CONSTANT134_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000218,
-};
-u32 R600_PS_CONSTANT135_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000021C,
-};
-u32 R600_PS_CONSTANT136_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000220,
-};
-u32 R600_PS_CONSTANT137_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000224,
-};
-u32 R600_PS_CONSTANT138_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000228,
-};
-u32 R600_PS_CONSTANT139_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000022C,
-};
-u32 R600_PS_CONSTANT140_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000230,
-};
-u32 R600_PS_CONSTANT141_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000234,
-};
-u32 R600_PS_CONSTANT142_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000238,
-};
-u32 R600_PS_CONSTANT143_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000023C,
-};
-u32 R600_PS_CONSTANT144_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000240,
-};
-u32 R600_PS_CONSTANT145_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000244,
-};
-u32 R600_PS_CONSTANT146_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000248,
-};
-u32 R600_PS_CONSTANT147_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000024C,
-};
-u32 R600_PS_CONSTANT148_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000250,
-};
-u32 R600_PS_CONSTANT149_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000254,
-};
-u32 R600_PS_CONSTANT150_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000258,
-};
-u32 R600_PS_CONSTANT151_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000025C,
-};
-u32 R600_PS_CONSTANT152_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000260,
-};
-u32 R600_PS_CONSTANT153_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000264,
-};
-u32 R600_PS_CONSTANT154_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000268,
-};
-u32 R600_PS_CONSTANT155_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000026C,
-};
-u32 R600_PS_CONSTANT156_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000270,
-};
-u32 R600_PS_CONSTANT157_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000274,
-};
-u32 R600_PS_CONSTANT158_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000278,
-};
-u32 R600_PS_CONSTANT159_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000027C,
-};
-u32 R600_PS_CONSTANT160_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000280,
-};
-u32 R600_PS_CONSTANT161_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000284,
-};
-u32 R600_PS_CONSTANT162_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000288,
-};
-u32 R600_PS_CONSTANT163_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000028C,
-};
-u32 R600_PS_CONSTANT164_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000290,
-};
-u32 R600_PS_CONSTANT165_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000294,
-};
-u32 R600_PS_CONSTANT166_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000298,
-};
-u32 R600_PS_CONSTANT167_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000029C,
-};
-u32 R600_PS_CONSTANT168_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002A0,
-};
-u32 R600_PS_CONSTANT169_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002A4,
-};
-u32 R600_PS_CONSTANT170_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002A8,
-};
-u32 R600_PS_CONSTANT171_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002AC,
-};
-u32 R600_PS_CONSTANT172_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002B0,
-};
-u32 R600_PS_CONSTANT173_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002B4,
-};
-u32 R600_PS_CONSTANT174_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002B8,
-};
-u32 R600_PS_CONSTANT175_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002BC,
-};
-u32 R600_PS_CONSTANT176_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002C0,
-};
-u32 R600_PS_CONSTANT177_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002C4,
-};
-u32 R600_PS_CONSTANT178_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002C8,
-};
-u32 R600_PS_CONSTANT179_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002CC,
-};
-u32 R600_PS_CONSTANT180_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002D0,
-};
-u32 R600_PS_CONSTANT181_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002D4,
-};
-u32 R600_PS_CONSTANT182_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002D8,
-};
-u32 R600_PS_CONSTANT183_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002DC,
-};
-u32 R600_PS_CONSTANT184_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002E0,
-};
-u32 R600_PS_CONSTANT185_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002E4,
-};
-u32 R600_PS_CONSTANT186_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002E8,
-};
-u32 R600_PS_CONSTANT187_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002EC,
-};
-u32 R600_PS_CONSTANT188_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002F0,
-};
-u32 R600_PS_CONSTANT189_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002F4,
-};
-u32 R600_PS_CONSTANT190_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002F8,
-};
-u32 R600_PS_CONSTANT191_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000002FC,
-};
-u32 R600_PS_CONSTANT192_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000300,
-};
-u32 R600_PS_CONSTANT193_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000304,
-};
-u32 R600_PS_CONSTANT194_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000308,
-};
-u32 R600_PS_CONSTANT195_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000030C,
-};
-u32 R600_PS_CONSTANT196_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000310,
-};
-u32 R600_PS_CONSTANT197_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000314,
-};
-u32 R600_PS_CONSTANT198_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000318,
-};
-u32 R600_PS_CONSTANT199_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000031C,
-};
-u32 R600_PS_CONSTANT200_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000320,
-};
-u32 R600_PS_CONSTANT201_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000324,
-};
-u32 R600_PS_CONSTANT202_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000328,
-};
-u32 R600_PS_CONSTANT203_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000032C,
-};
-u32 R600_PS_CONSTANT204_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000330,
-};
-u32 R600_PS_CONSTANT205_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000334,
-};
-u32 R600_PS_CONSTANT206_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000338,
-};
-u32 R600_PS_CONSTANT207_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000033C,
-};
-u32 R600_PS_CONSTANT208_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000340,
-};
-u32 R600_PS_CONSTANT209_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000344,
-};
-u32 R600_PS_CONSTANT210_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000348,
-};
-u32 R600_PS_CONSTANT211_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000034C,
-};
-u32 R600_PS_CONSTANT212_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000350,
-};
-u32 R600_PS_CONSTANT213_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000354,
-};
-u32 R600_PS_CONSTANT214_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000358,
-};
-u32 R600_PS_CONSTANT215_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000035C,
-};
-u32 R600_PS_CONSTANT216_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000360,
-};
-u32 R600_PS_CONSTANT217_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000364,
-};
-u32 R600_PS_CONSTANT218_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000368,
-};
-u32 R600_PS_CONSTANT219_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000036C,
-};
-u32 R600_PS_CONSTANT220_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000370,
-};
-u32 R600_PS_CONSTANT221_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000374,
-};
-u32 R600_PS_CONSTANT222_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000378,
-};
-u32 R600_PS_CONSTANT223_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000037C,
-};
-u32 R600_PS_CONSTANT224_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000380,
-};
-u32 R600_PS_CONSTANT225_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000384,
-};
-u32 R600_PS_CONSTANT226_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000388,
-};
-u32 R600_PS_CONSTANT227_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000038C,
-};
-u32 R600_PS_CONSTANT228_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000390,
-};
-u32 R600_PS_CONSTANT229_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000394,
-};
-u32 R600_PS_CONSTANT230_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000398,
-};
-u32 R600_PS_CONSTANT231_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000039C,
-};
-u32 R600_PS_CONSTANT232_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003A0,
-};
-u32 R600_PS_CONSTANT233_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003A4,
-};
-u32 R600_PS_CONSTANT234_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003A8,
-};
-u32 R600_PS_CONSTANT235_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003AC,
-};
-u32 R600_PS_CONSTANT236_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003B0,
-};
-u32 R600_PS_CONSTANT237_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003B4,
-};
-u32 R600_PS_CONSTANT238_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003B8,
-};
-u32 R600_PS_CONSTANT239_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003BC,
-};
-u32 R600_PS_CONSTANT240_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003C0,
-};
-u32 R600_PS_CONSTANT241_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003C4,
-};
-u32 R600_PS_CONSTANT242_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003C8,
-};
-u32 R600_PS_CONSTANT243_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003CC,
-};
-u32 R600_PS_CONSTANT244_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003D0,
-};
-u32 R600_PS_CONSTANT245_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003D4,
-};
-u32 R600_PS_CONSTANT246_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003D8,
-};
-u32 R600_PS_CONSTANT247_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003DC,
-};
-u32 R600_PS_CONSTANT248_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003E0,
-};
-u32 R600_PS_CONSTANT249_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003E4,
-};
-u32 R600_PS_CONSTANT250_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003E8,
-};
-u32 R600_PS_CONSTANT251_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003EC,
-};
-u32 R600_PS_CONSTANT252_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003F0,
-};
-u32 R600_PS_CONSTANT253_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003F4,
-};
-u32 R600_PS_CONSTANT254_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003F8,
-};
-u32 R600_PS_CONSTANT255_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000003FC,
-};
-u32 R600_VS_CONSTANT0_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000400,
-};
-u32 R600_VS_CONSTANT1_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000404,
-};
-u32 R600_VS_CONSTANT2_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000408,
-};
-u32 R600_VS_CONSTANT3_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000040C,
-};
-u32 R600_VS_CONSTANT4_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000410,
-};
-u32 R600_VS_CONSTANT5_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000414,
-};
-u32 R600_VS_CONSTANT6_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000418,
-};
-u32 R600_VS_CONSTANT7_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000041C,
-};
-u32 R600_VS_CONSTANT8_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000420,
-};
-u32 R600_VS_CONSTANT9_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000424,
-};
-u32 R600_VS_CONSTANT10_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000428,
-};
-u32 R600_VS_CONSTANT11_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000042C,
-};
-u32 R600_VS_CONSTANT12_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000430,
-};
-u32 R600_VS_CONSTANT13_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000434,
-};
-u32 R600_VS_CONSTANT14_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000438,
-};
-u32 R600_VS_CONSTANT15_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000043C,
-};
-u32 R600_VS_CONSTANT16_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000440,
-};
-u32 R600_VS_CONSTANT17_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000444,
-};
-u32 R600_VS_CONSTANT18_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000448,
-};
-u32 R600_VS_CONSTANT19_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000044C,
-};
-u32 R600_VS_CONSTANT20_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000450,
-};
-u32 R600_VS_CONSTANT21_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000454,
-};
-u32 R600_VS_CONSTANT22_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000458,
-};
-u32 R600_VS_CONSTANT23_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000045C,
-};
-u32 R600_VS_CONSTANT24_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000460,
-};
-u32 R600_VS_CONSTANT25_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000464,
-};
-u32 R600_VS_CONSTANT26_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000468,
-};
-u32 R600_VS_CONSTANT27_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000046C,
-};
-u32 R600_VS_CONSTANT28_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000470,
-};
-u32 R600_VS_CONSTANT29_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000474,
-};
-u32 R600_VS_CONSTANT30_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000478,
-};
-u32 R600_VS_CONSTANT31_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000047C,
-};
-u32 R600_VS_CONSTANT32_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000480,
-};
-u32 R600_VS_CONSTANT33_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000484,
-};
-u32 R600_VS_CONSTANT34_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000488,
-};
-u32 R600_VS_CONSTANT35_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000048C,
-};
-u32 R600_VS_CONSTANT36_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000490,
-};
-u32 R600_VS_CONSTANT37_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000494,
-};
-u32 R600_VS_CONSTANT38_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000498,
-};
-u32 R600_VS_CONSTANT39_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000049C,
-};
-u32 R600_VS_CONSTANT40_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004A0,
-};
-u32 R600_VS_CONSTANT41_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004A4,
-};
-u32 R600_VS_CONSTANT42_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004A8,
-};
-u32 R600_VS_CONSTANT43_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004AC,
-};
-u32 R600_VS_CONSTANT44_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004B0,
-};
-u32 R600_VS_CONSTANT45_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004B4,
-};
-u32 R600_VS_CONSTANT46_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004B8,
-};
-u32 R600_VS_CONSTANT47_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004BC,
-};
-u32 R600_VS_CONSTANT48_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004C0,
-};
-u32 R600_VS_CONSTANT49_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004C4,
-};
-u32 R600_VS_CONSTANT50_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004C8,
-};
-u32 R600_VS_CONSTANT51_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004CC,
-};
-u32 R600_VS_CONSTANT52_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004D0,
-};
-u32 R600_VS_CONSTANT53_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004D4,
-};
-u32 R600_VS_CONSTANT54_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004D8,
-};
-u32 R600_VS_CONSTANT55_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004DC,
-};
-u32 R600_VS_CONSTANT56_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004E0,
-};
-u32 R600_VS_CONSTANT57_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004E4,
-};
-u32 R600_VS_CONSTANT58_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004E8,
-};
-u32 R600_VS_CONSTANT59_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004EC,
-};
-u32 R600_VS_CONSTANT60_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004F0,
-};
-u32 R600_VS_CONSTANT61_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004F4,
-};
-u32 R600_VS_CONSTANT62_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004F8,
-};
-u32 R600_VS_CONSTANT63_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000004FC,
-};
-u32 R600_VS_CONSTANT64_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000500,
-};
-u32 R600_VS_CONSTANT65_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000504,
-};
-u32 R600_VS_CONSTANT66_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000508,
-};
-u32 R600_VS_CONSTANT67_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000050C,
-};
-u32 R600_VS_CONSTANT68_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000510,
-};
-u32 R600_VS_CONSTANT69_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000514,
-};
-u32 R600_VS_CONSTANT70_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000518,
-};
-u32 R600_VS_CONSTANT71_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000051C,
-};
-u32 R600_VS_CONSTANT72_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000520,
-};
-u32 R600_VS_CONSTANT73_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000524,
-};
-u32 R600_VS_CONSTANT74_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000528,
-};
-u32 R600_VS_CONSTANT75_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000052C,
-};
-u32 R600_VS_CONSTANT76_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000530,
-};
-u32 R600_VS_CONSTANT77_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000534,
-};
-u32 R600_VS_CONSTANT78_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000538,
-};
-u32 R600_VS_CONSTANT79_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000053C,
-};
-u32 R600_VS_CONSTANT80_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000540,
-};
-u32 R600_VS_CONSTANT81_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000544,
-};
-u32 R600_VS_CONSTANT82_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000548,
-};
-u32 R600_VS_CONSTANT83_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000054C,
-};
-u32 R600_VS_CONSTANT84_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000550,
-};
-u32 R600_VS_CONSTANT85_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000554,
-};
-u32 R600_VS_CONSTANT86_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000558,
-};
-u32 R600_VS_CONSTANT87_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000055C,
-};
-u32 R600_VS_CONSTANT88_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000560,
-};
-u32 R600_VS_CONSTANT89_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000564,
-};
-u32 R600_VS_CONSTANT90_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000568,
-};
-u32 R600_VS_CONSTANT91_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000056C,
-};
-u32 R600_VS_CONSTANT92_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000570,
-};
-u32 R600_VS_CONSTANT93_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000574,
-};
-u32 R600_VS_CONSTANT94_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000578,
-};
-u32 R600_VS_CONSTANT95_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000057C,
-};
-u32 R600_VS_CONSTANT96_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000580,
-};
-u32 R600_VS_CONSTANT97_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000584,
-};
-u32 R600_VS_CONSTANT98_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000588,
-};
-u32 R600_VS_CONSTANT99_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000058C,
-};
-u32 R600_VS_CONSTANT100_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000590,
-};
-u32 R600_VS_CONSTANT101_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000594,
-};
-u32 R600_VS_CONSTANT102_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000598,
-};
-u32 R600_VS_CONSTANT103_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000059C,
-};
-u32 R600_VS_CONSTANT104_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005A0,
-};
-u32 R600_VS_CONSTANT105_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005A4,
-};
-u32 R600_VS_CONSTANT106_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005A8,
-};
-u32 R600_VS_CONSTANT107_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005AC,
-};
-u32 R600_VS_CONSTANT108_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005B0,
-};
-u32 R600_VS_CONSTANT109_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005B4,
-};
-u32 R600_VS_CONSTANT110_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005B8,
-};
-u32 R600_VS_CONSTANT111_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005BC,
-};
-u32 R600_VS_CONSTANT112_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005C0,
-};
-u32 R600_VS_CONSTANT113_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005C4,
-};
-u32 R600_VS_CONSTANT114_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005C8,
-};
-u32 R600_VS_CONSTANT115_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005CC,
-};
-u32 R600_VS_CONSTANT116_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005D0,
-};
-u32 R600_VS_CONSTANT117_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005D4,
-};
-u32 R600_VS_CONSTANT118_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005D8,
-};
-u32 R600_VS_CONSTANT119_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005DC,
-};
-u32 R600_VS_CONSTANT120_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005E0,
-};
-u32 R600_VS_CONSTANT121_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005E4,
-};
-u32 R600_VS_CONSTANT122_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005E8,
-};
-u32 R600_VS_CONSTANT123_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005EC,
-};
-u32 R600_VS_CONSTANT124_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005F0,
-};
-u32 R600_VS_CONSTANT125_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005F4,
-};
-u32 R600_VS_CONSTANT126_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005F8,
-};
-u32 R600_VS_CONSTANT127_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000005FC,
-};
-u32 R600_VS_CONSTANT128_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000600,
-};
-u32 R600_VS_CONSTANT129_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000604,
-};
-u32 R600_VS_CONSTANT130_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000608,
-};
-u32 R600_VS_CONSTANT131_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000060C,
-};
-u32 R600_VS_CONSTANT132_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000610,
-};
-u32 R600_VS_CONSTANT133_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000614,
-};
-u32 R600_VS_CONSTANT134_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000618,
-};
-u32 R600_VS_CONSTANT135_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000061C,
-};
-u32 R600_VS_CONSTANT136_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000620,
-};
-u32 R600_VS_CONSTANT137_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000624,
-};
-u32 R600_VS_CONSTANT138_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000628,
-};
-u32 R600_VS_CONSTANT139_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000062C,
-};
-u32 R600_VS_CONSTANT140_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000630,
-};
-u32 R600_VS_CONSTANT141_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000634,
-};
-u32 R600_VS_CONSTANT142_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000638,
-};
-u32 R600_VS_CONSTANT143_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000063C,
-};
-u32 R600_VS_CONSTANT144_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000640,
-};
-u32 R600_VS_CONSTANT145_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000644,
-};
-u32 R600_VS_CONSTANT146_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000648,
-};
-u32 R600_VS_CONSTANT147_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000064C,
-};
-u32 R600_VS_CONSTANT148_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000650,
-};
-u32 R600_VS_CONSTANT149_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000654,
-};
-u32 R600_VS_CONSTANT150_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000658,
-};
-u32 R600_VS_CONSTANT151_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000065C,
-};
-u32 R600_VS_CONSTANT152_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000660,
-};
-u32 R600_VS_CONSTANT153_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000664,
-};
-u32 R600_VS_CONSTANT154_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000668,
-};
-u32 R600_VS_CONSTANT155_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000066C,
-};
-u32 R600_VS_CONSTANT156_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000670,
-};
-u32 R600_VS_CONSTANT157_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000674,
-};
-u32 R600_VS_CONSTANT158_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000678,
-};
-u32 R600_VS_CONSTANT159_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000067C,
-};
-u32 R600_VS_CONSTANT160_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000680,
-};
-u32 R600_VS_CONSTANT161_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000684,
-};
-u32 R600_VS_CONSTANT162_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000688,
-};
-u32 R600_VS_CONSTANT163_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000068C,
-};
-u32 R600_VS_CONSTANT164_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000690,
-};
-u32 R600_VS_CONSTANT165_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000694,
-};
-u32 R600_VS_CONSTANT166_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000698,
-};
-u32 R600_VS_CONSTANT167_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000069C,
-};
-u32 R600_VS_CONSTANT168_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006A0,
-};
-u32 R600_VS_CONSTANT169_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006A4,
-};
-u32 R600_VS_CONSTANT170_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006A8,
-};
-u32 R600_VS_CONSTANT171_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006AC,
-};
-u32 R600_VS_CONSTANT172_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006B0,
-};
-u32 R600_VS_CONSTANT173_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006B4,
-};
-u32 R600_VS_CONSTANT174_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006B8,
-};
-u32 R600_VS_CONSTANT175_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006BC,
-};
-u32 R600_VS_CONSTANT176_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006C0,
-};
-u32 R600_VS_CONSTANT177_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006C4,
-};
-u32 R600_VS_CONSTANT178_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006C8,
-};
-u32 R600_VS_CONSTANT179_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006CC,
-};
-u32 R600_VS_CONSTANT180_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006D0,
-};
-u32 R600_VS_CONSTANT181_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006D4,
-};
-u32 R600_VS_CONSTANT182_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006D8,
-};
-u32 R600_VS_CONSTANT183_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006DC,
-};
-u32 R600_VS_CONSTANT184_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006E0,
-};
-u32 R600_VS_CONSTANT185_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006E4,
-};
-u32 R600_VS_CONSTANT186_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006E8,
-};
-u32 R600_VS_CONSTANT187_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006EC,
-};
-u32 R600_VS_CONSTANT188_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006F0,
-};
-u32 R600_VS_CONSTANT189_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006F4,
-};
-u32 R600_VS_CONSTANT190_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006F8,
-};
-u32 R600_VS_CONSTANT191_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000006FC,
-};
-u32 R600_VS_CONSTANT192_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000700,
-};
-u32 R600_VS_CONSTANT193_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000704,
-};
-u32 R600_VS_CONSTANT194_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000708,
-};
-u32 R600_VS_CONSTANT195_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000070C,
-};
-u32 R600_VS_CONSTANT196_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000710,
-};
-u32 R600_VS_CONSTANT197_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000714,
-};
-u32 R600_VS_CONSTANT198_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000718,
-};
-u32 R600_VS_CONSTANT199_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000071C,
-};
-u32 R600_VS_CONSTANT200_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000720,
-};
-u32 R600_VS_CONSTANT201_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000724,
-};
-u32 R600_VS_CONSTANT202_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000728,
-};
-u32 R600_VS_CONSTANT203_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000072C,
-};
-u32 R600_VS_CONSTANT204_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000730,
-};
-u32 R600_VS_CONSTANT205_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000734,
-};
-u32 R600_VS_CONSTANT206_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000738,
-};
-u32 R600_VS_CONSTANT207_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000073C,
-};
-u32 R600_VS_CONSTANT208_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000740,
-};
-u32 R600_VS_CONSTANT209_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000744,
-};
-u32 R600_VS_CONSTANT210_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000748,
-};
-u32 R600_VS_CONSTANT211_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000074C,
-};
-u32 R600_VS_CONSTANT212_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000750,
-};
-u32 R600_VS_CONSTANT213_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000754,
-};
-u32 R600_VS_CONSTANT214_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000758,
-};
-u32 R600_VS_CONSTANT215_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000075C,
-};
-u32 R600_VS_CONSTANT216_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000760,
-};
-u32 R600_VS_CONSTANT217_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000764,
-};
-u32 R600_VS_CONSTANT218_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000768,
-};
-u32 R600_VS_CONSTANT219_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000076C,
-};
-u32 R600_VS_CONSTANT220_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000770,
-};
-u32 R600_VS_CONSTANT221_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000774,
-};
-u32 R600_VS_CONSTANT222_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000778,
-};
-u32 R600_VS_CONSTANT223_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000077C,
-};
-u32 R600_VS_CONSTANT224_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000780,
-};
-u32 R600_VS_CONSTANT225_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000784,
-};
-u32 R600_VS_CONSTANT226_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000788,
-};
-u32 R600_VS_CONSTANT227_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000078C,
-};
-u32 R600_VS_CONSTANT228_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000790,
-};
-u32 R600_VS_CONSTANT229_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000794,
-};
-u32 R600_VS_CONSTANT230_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x00000798,
-};
-u32 R600_VS_CONSTANT231_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x0000079C,
-};
-u32 R600_VS_CONSTANT232_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007A0,
-};
-u32 R600_VS_CONSTANT233_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007A4,
-};
-u32 R600_VS_CONSTANT234_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007A8,
-};
-u32 R600_VS_CONSTANT235_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007AC,
-};
-u32 R600_VS_CONSTANT236_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007B0,
-};
-u32 R600_VS_CONSTANT237_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007B4,
-};
-u32 R600_VS_CONSTANT238_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007B8,
-};
-u32 R600_VS_CONSTANT239_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007BC,
-};
-u32 R600_VS_CONSTANT240_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007C0,
-};
-u32 R600_VS_CONSTANT241_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007C4,
-};
-u32 R600_VS_CONSTANT242_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007C8,
-};
-u32 R600_VS_CONSTANT243_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007CC,
-};
-u32 R600_VS_CONSTANT244_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007D0,
-};
-u32 R600_VS_CONSTANT245_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007D4,
-};
-u32 R600_VS_CONSTANT246_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007D8,
-};
-u32 R600_VS_CONSTANT247_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007DC,
-};
-u32 R600_VS_CONSTANT248_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007E0,
-};
-u32 R600_VS_CONSTANT249_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007E4,
-};
-u32 R600_VS_CONSTANT250_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007E8,
-};
-u32 R600_VS_CONSTANT251_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007EC,
-};
-u32 R600_VS_CONSTANT252_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007F0,
-};
-u32 R600_VS_CONSTANT253_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007F4,
-};
-u32 R600_VS_CONSTANT254_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007F8,
-};
-u32 R600_VS_CONSTANT255_header_pm4[R600_CONSTANT_header_cpm4] = {
-	0xC0046A00,
-	0x000007FC,
-};
-#define R600_CONSTANT_state_cpm4 4
-u32 R600_CONSTANT_state_pm4[R600_CONSTANT_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-
-/* R600_RESOURCE */
-#define R600_RESOURCE_header_cpm4 2
-u32 R600_PS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000000,
-};
-u32 R600_PS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000007,
-};
-u32 R600_PS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000000E,
-};
-u32 R600_PS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000015,
-};
-u32 R600_PS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000001C,
-};
-u32 R600_PS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000023,
-};
-u32 R600_PS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000002A,
-};
-u32 R600_PS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000031,
-};
-u32 R600_PS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000038,
-};
-u32 R600_PS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000003F,
-};
-u32 R600_PS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000046,
-};
-u32 R600_PS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000004D,
-};
-u32 R600_PS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000054,
-};
-u32 R600_PS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000005B,
-};
-u32 R600_PS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000062,
-};
-u32 R600_PS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000069,
-};
-u32 R600_PS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000070,
-};
-u32 R600_PS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000077,
-};
-u32 R600_PS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000007E,
-};
-u32 R600_PS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000085,
-};
-u32 R600_PS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000008C,
-};
-u32 R600_PS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000093,
-};
-u32 R600_PS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000009A,
-};
-u32 R600_PS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000A1,
-};
-u32 R600_PS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000A8,
-};
-u32 R600_PS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000AF,
-};
-u32 R600_PS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000B6,
-};
-u32 R600_PS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000BD,
-};
-u32 R600_PS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000C4,
-};
-u32 R600_PS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000CB,
-};
-u32 R600_PS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000D2,
-};
-u32 R600_PS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000D9,
-};
-u32 R600_PS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000E0,
-};
-u32 R600_PS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000E7,
-};
-u32 R600_PS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000EE,
-};
-u32 R600_PS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000F5,
-};
-u32 R600_PS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000000FC,
-};
-u32 R600_PS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000103,
-};
-u32 R600_PS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000010A,
-};
-u32 R600_PS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000111,
-};
-u32 R600_PS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000118,
-};
-u32 R600_PS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000011F,
-};
-u32 R600_PS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000126,
-};
-u32 R600_PS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000012D,
-};
-u32 R600_PS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000134,
-};
-u32 R600_PS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000013B,
-};
-u32 R600_PS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000142,
-};
-u32 R600_PS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000149,
-};
-u32 R600_PS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000150,
-};
-u32 R600_PS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000157,
-};
-u32 R600_PS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000015E,
-};
-u32 R600_PS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000165,
-};
-u32 R600_PS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000016C,
-};
-u32 R600_PS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000173,
-};
-u32 R600_PS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000017A,
-};
-u32 R600_PS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000181,
-};
-u32 R600_PS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000188,
-};
-u32 R600_PS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000018F,
-};
-u32 R600_PS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000196,
-};
-u32 R600_PS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000019D,
-};
-u32 R600_PS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001A4,
-};
-u32 R600_PS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001AB,
-};
-u32 R600_PS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001B2,
-};
-u32 R600_PS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001B9,
-};
-u32 R600_PS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001C0,
-};
-u32 R600_PS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001C7,
-};
-u32 R600_PS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001CE,
-};
-u32 R600_PS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001D5,
-};
-u32 R600_PS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001DC,
-};
-u32 R600_PS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001E3,
-};
-u32 R600_PS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001EA,
-};
-u32 R600_PS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001F1,
-};
-u32 R600_PS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001F8,
-};
-u32 R600_PS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000001FF,
-};
-u32 R600_PS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000206,
-};
-u32 R600_PS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000020D,
-};
-u32 R600_PS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000214,
-};
-u32 R600_PS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000021B,
-};
-u32 R600_PS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000222,
-};
-u32 R600_PS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000229,
-};
-u32 R600_PS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000230,
-};
-u32 R600_PS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000237,
-};
-u32 R600_PS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000023E,
-};
-u32 R600_PS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000245,
-};
-u32 R600_PS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000024C,
-};
-u32 R600_PS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000253,
-};
-u32 R600_PS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000025A,
-};
-u32 R600_PS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000261,
-};
-u32 R600_PS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000268,
-};
-u32 R600_PS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000026F,
-};
-u32 R600_PS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000276,
-};
-u32 R600_PS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000027D,
-};
-u32 R600_PS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000284,
-};
-u32 R600_PS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000028B,
-};
-u32 R600_PS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000292,
-};
-u32 R600_PS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000299,
-};
-u32 R600_PS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002A0,
-};
-u32 R600_PS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002A7,
-};
-u32 R600_PS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002AE,
-};
-u32 R600_PS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002B5,
-};
-u32 R600_PS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002BC,
-};
-u32 R600_PS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002C3,
-};
-u32 R600_PS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002CA,
-};
-u32 R600_PS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002D1,
-};
-u32 R600_PS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002D8,
-};
-u32 R600_PS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002DF,
-};
-u32 R600_PS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002E6,
-};
-u32 R600_PS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002ED,
-};
-u32 R600_PS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002F4,
-};
-u32 R600_PS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000002FB,
-};
-u32 R600_PS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000302,
-};
-u32 R600_PS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000309,
-};
-u32 R600_PS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000310,
-};
-u32 R600_PS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000317,
-};
-u32 R600_PS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000031E,
-};
-u32 R600_PS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000325,
-};
-u32 R600_PS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000032C,
-};
-u32 R600_PS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000333,
-};
-u32 R600_PS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000033A,
-};
-u32 R600_PS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000341,
-};
-u32 R600_PS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000348,
-};
-u32 R600_PS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000034F,
-};
-u32 R600_PS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000356,
-};
-u32 R600_PS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000035D,
-};
-u32 R600_PS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000364,
-};
-u32 R600_PS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000036B,
-};
-u32 R600_PS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000372,
-};
-u32 R600_PS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000379,
-};
-u32 R600_PS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000380,
-};
-u32 R600_PS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000387,
-};
-u32 R600_PS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000038E,
-};
-u32 R600_PS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000395,
-};
-u32 R600_PS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000039C,
-};
-u32 R600_PS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003A3,
-};
-u32 R600_PS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003AA,
-};
-u32 R600_PS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003B1,
-};
-u32 R600_PS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003B8,
-};
-u32 R600_PS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003BF,
-};
-u32 R600_PS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003C6,
-};
-u32 R600_PS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003CD,
-};
-u32 R600_PS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003D4,
-};
-u32 R600_PS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003DB,
-};
-u32 R600_PS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003E2,
-};
-u32 R600_PS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003E9,
-};
-u32 R600_PS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003F0,
-};
-u32 R600_PS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003F7,
-};
-u32 R600_PS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000003FE,
-};
-u32 R600_PS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000405,
-};
-u32 R600_PS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000040C,
-};
-u32 R600_PS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000413,
-};
-u32 R600_PS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000041A,
-};
-u32 R600_PS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000421,
-};
-u32 R600_PS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000428,
-};
-u32 R600_PS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000042F,
-};
-u32 R600_PS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000436,
-};
-u32 R600_PS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000043D,
-};
-u32 R600_PS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000444,
-};
-u32 R600_PS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000044B,
-};
-u32 R600_PS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000452,
-};
-u32 R600_PS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000459,
-};
-u32 R600_VS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000460,
-};
-u32 R600_VS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000467,
-};
-u32 R600_VS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000046E,
-};
-u32 R600_VS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000475,
-};
-u32 R600_VS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000047C,
-};
-u32 R600_VS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000483,
-};
-u32 R600_VS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000048A,
-};
-u32 R600_VS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000491,
-};
-u32 R600_VS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000498,
-};
-u32 R600_VS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000049F,
-};
-u32 R600_VS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004A6,
-};
-u32 R600_VS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004AD,
-};
-u32 R600_VS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004B4,
-};
-u32 R600_VS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004BB,
-};
-u32 R600_VS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004C2,
-};
-u32 R600_VS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004C9,
-};
-u32 R600_VS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004D0,
-};
-u32 R600_VS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004D7,
-};
-u32 R600_VS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004DE,
-};
-u32 R600_VS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004E5,
-};
-u32 R600_VS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004EC,
-};
-u32 R600_VS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004F3,
-};
-u32 R600_VS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000004FA,
-};
-u32 R600_VS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000501,
-};
-u32 R600_VS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000508,
-};
-u32 R600_VS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000050F,
-};
-u32 R600_VS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000516,
-};
-u32 R600_VS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000051D,
-};
-u32 R600_VS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000524,
-};
-u32 R600_VS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000052B,
-};
-u32 R600_VS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000532,
-};
-u32 R600_VS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000539,
-};
-u32 R600_VS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000540,
-};
-u32 R600_VS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000547,
-};
-u32 R600_VS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000054E,
-};
-u32 R600_VS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000555,
-};
-u32 R600_VS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000055C,
-};
-u32 R600_VS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000563,
-};
-u32 R600_VS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000056A,
-};
-u32 R600_VS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000571,
-};
-u32 R600_VS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000578,
-};
-u32 R600_VS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000057F,
-};
-u32 R600_VS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000586,
-};
-u32 R600_VS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000058D,
-};
-u32 R600_VS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000594,
-};
-u32 R600_VS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000059B,
-};
-u32 R600_VS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005A2,
-};
-u32 R600_VS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005A9,
-};
-u32 R600_VS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005B0,
-};
-u32 R600_VS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005B7,
-};
-u32 R600_VS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005BE,
-};
-u32 R600_VS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005C5,
-};
-u32 R600_VS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005CC,
-};
-u32 R600_VS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005D3,
-};
-u32 R600_VS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005DA,
-};
-u32 R600_VS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005E1,
-};
-u32 R600_VS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005E8,
-};
-u32 R600_VS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005EF,
-};
-u32 R600_VS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005F6,
-};
-u32 R600_VS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000005FD,
-};
-u32 R600_VS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000604,
-};
-u32 R600_VS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000060B,
-};
-u32 R600_VS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000612,
-};
-u32 R600_VS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000619,
-};
-u32 R600_VS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000620,
-};
-u32 R600_VS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000627,
-};
-u32 R600_VS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000062E,
-};
-u32 R600_VS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000635,
-};
-u32 R600_VS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000063C,
-};
-u32 R600_VS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000643,
-};
-u32 R600_VS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000064A,
-};
-u32 R600_VS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000651,
-};
-u32 R600_VS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000658,
-};
-u32 R600_VS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000065F,
-};
-u32 R600_VS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000666,
-};
-u32 R600_VS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000066D,
-};
-u32 R600_VS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000674,
-};
-u32 R600_VS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000067B,
-};
-u32 R600_VS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000682,
-};
-u32 R600_VS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000689,
-};
-u32 R600_VS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000690,
-};
-u32 R600_VS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000697,
-};
-u32 R600_VS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000069E,
-};
-u32 R600_VS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006A5,
-};
-u32 R600_VS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006AC,
-};
-u32 R600_VS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006B3,
-};
-u32 R600_VS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006BA,
-};
-u32 R600_VS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006C1,
-};
-u32 R600_VS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006C8,
-};
-u32 R600_VS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006CF,
-};
-u32 R600_VS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006D6,
-};
-u32 R600_VS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006DD,
-};
-u32 R600_VS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006E4,
-};
-u32 R600_VS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006EB,
-};
-u32 R600_VS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006F2,
-};
-u32 R600_VS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000006F9,
-};
-u32 R600_VS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000700,
-};
-u32 R600_VS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000707,
-};
-u32 R600_VS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000070E,
-};
-u32 R600_VS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000715,
-};
-u32 R600_VS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000071C,
-};
-u32 R600_VS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000723,
-};
-u32 R600_VS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000072A,
-};
-u32 R600_VS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000731,
-};
-u32 R600_VS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000738,
-};
-u32 R600_VS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000073F,
-};
-u32 R600_VS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000746,
-};
-u32 R600_VS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000074D,
-};
-u32 R600_VS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000754,
-};
-u32 R600_VS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000075B,
-};
-u32 R600_VS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000762,
-};
-u32 R600_VS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000769,
-};
-u32 R600_VS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000770,
-};
-u32 R600_VS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000777,
-};
-u32 R600_VS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000077E,
-};
-u32 R600_VS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000785,
-};
-u32 R600_VS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000078C,
-};
-u32 R600_VS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000793,
-};
-u32 R600_VS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000079A,
-};
-u32 R600_VS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007A1,
-};
-u32 R600_VS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007A8,
-};
-u32 R600_VS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007AF,
-};
-u32 R600_VS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007B6,
-};
-u32 R600_VS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007BD,
-};
-u32 R600_VS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007C4,
-};
-u32 R600_VS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007CB,
-};
-u32 R600_VS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007D2,
-};
-u32 R600_VS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007D9,
-};
-u32 R600_VS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007E0,
-};
-u32 R600_VS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007E7,
-};
-u32 R600_VS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007EE,
-};
-u32 R600_VS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007F5,
-};
-u32 R600_VS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000007FC,
-};
-u32 R600_VS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000803,
-};
-u32 R600_VS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000080A,
-};
-u32 R600_VS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000811,
-};
-u32 R600_VS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000818,
-};
-u32 R600_VS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000081F,
-};
-u32 R600_VS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000826,
-};
-u32 R600_VS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000082D,
-};
-u32 R600_VS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000834,
-};
-u32 R600_VS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000083B,
-};
-u32 R600_VS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000842,
-};
-u32 R600_VS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000849,
-};
-u32 R600_VS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000850,
-};
-u32 R600_VS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000857,
-};
-u32 R600_VS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000085E,
-};
-u32 R600_VS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000865,
-};
-u32 R600_VS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000086C,
-};
-u32 R600_VS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000873,
-};
-u32 R600_VS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000087A,
-};
-u32 R600_VS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000881,
-};
-u32 R600_VS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000888,
-};
-u32 R600_VS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000088F,
-};
-u32 R600_VS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000896,
-};
-u32 R600_VS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000089D,
-};
-u32 R600_VS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008A4,
-};
-u32 R600_VS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008AB,
-};
-u32 R600_VS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008B2,
-};
-u32 R600_VS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008B9,
-};
-u32 R600_FS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008C0,
-};
-u32 R600_FS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008C7,
-};
-u32 R600_FS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008CE,
-};
-u32 R600_FS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008D5,
-};
-u32 R600_FS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008DC,
-};
-u32 R600_FS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008E3,
-};
-u32 R600_FS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008EA,
-};
-u32 R600_FS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008F1,
-};
-u32 R600_FS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008F8,
-};
-u32 R600_FS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000008FF,
-};
-u32 R600_FS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000906,
-};
-u32 R600_FS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000090D,
-};
-u32 R600_FS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000914,
-};
-u32 R600_FS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000091B,
-};
-u32 R600_FS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000922,
-};
-u32 R600_FS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000929,
-};
-u32 R600_GS_RESOURCE0_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000930,
-};
-u32 R600_GS_RESOURCE1_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000937,
-};
-u32 R600_GS_RESOURCE2_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000093E,
-};
-u32 R600_GS_RESOURCE3_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000945,
-};
-u32 R600_GS_RESOURCE4_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000094C,
-};
-u32 R600_GS_RESOURCE5_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000953,
-};
-u32 R600_GS_RESOURCE6_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000095A,
-};
-u32 R600_GS_RESOURCE7_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000961,
-};
-u32 R600_GS_RESOURCE8_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000968,
-};
-u32 R600_GS_RESOURCE9_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000096F,
-};
-u32 R600_GS_RESOURCE10_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000976,
-};
-u32 R600_GS_RESOURCE11_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000097D,
-};
-u32 R600_GS_RESOURCE12_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000984,
-};
-u32 R600_GS_RESOURCE13_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x0000098B,
-};
-u32 R600_GS_RESOURCE14_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000992,
-};
-u32 R600_GS_RESOURCE15_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000999,
-};
-u32 R600_GS_RESOURCE16_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009A0,
-};
-u32 R600_GS_RESOURCE17_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009A7,
-};
-u32 R600_GS_RESOURCE18_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009AE,
-};
-u32 R600_GS_RESOURCE19_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009B5,
-};
-u32 R600_GS_RESOURCE20_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009BC,
-};
-u32 R600_GS_RESOURCE21_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009C3,
-};
-u32 R600_GS_RESOURCE22_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009CA,
-};
-u32 R600_GS_RESOURCE23_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009D1,
-};
-u32 R600_GS_RESOURCE24_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009D8,
-};
-u32 R600_GS_RESOURCE25_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009DF,
-};
-u32 R600_GS_RESOURCE26_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009E6,
-};
-u32 R600_GS_RESOURCE27_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009ED,
-};
-u32 R600_GS_RESOURCE28_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009F4,
-};
-u32 R600_GS_RESOURCE29_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x000009FB,
-};
-u32 R600_GS_RESOURCE30_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A02,
-};
-u32 R600_GS_RESOURCE31_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A09,
-};
-u32 R600_GS_RESOURCE32_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A10,
-};
-u32 R600_GS_RESOURCE33_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A17,
-};
-u32 R600_GS_RESOURCE34_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A1E,
-};
-u32 R600_GS_RESOURCE35_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A25,
-};
-u32 R600_GS_RESOURCE36_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A2C,
-};
-u32 R600_GS_RESOURCE37_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A33,
-};
-u32 R600_GS_RESOURCE38_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A3A,
-};
-u32 R600_GS_RESOURCE39_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A41,
-};
-u32 R600_GS_RESOURCE40_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A48,
-};
-u32 R600_GS_RESOURCE41_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A4F,
-};
-u32 R600_GS_RESOURCE42_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A56,
-};
-u32 R600_GS_RESOURCE43_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A5D,
-};
-u32 R600_GS_RESOURCE44_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A64,
-};
-u32 R600_GS_RESOURCE45_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A6B,
-};
-u32 R600_GS_RESOURCE46_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A72,
-};
-u32 R600_GS_RESOURCE47_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A79,
-};
-u32 R600_GS_RESOURCE48_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A80,
-};
-u32 R600_GS_RESOURCE49_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A87,
-};
-u32 R600_GS_RESOURCE50_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A8E,
-};
-u32 R600_GS_RESOURCE51_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A95,
-};
-u32 R600_GS_RESOURCE52_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000A9C,
-};
-u32 R600_GS_RESOURCE53_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AA3,
-};
-u32 R600_GS_RESOURCE54_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AAA,
-};
-u32 R600_GS_RESOURCE55_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AB1,
-};
-u32 R600_GS_RESOURCE56_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AB8,
-};
-u32 R600_GS_RESOURCE57_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000ABF,
-};
-u32 R600_GS_RESOURCE58_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AC6,
-};
-u32 R600_GS_RESOURCE59_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000ACD,
-};
-u32 R600_GS_RESOURCE60_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AD4,
-};
-u32 R600_GS_RESOURCE61_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000ADB,
-};
-u32 R600_GS_RESOURCE62_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AE2,
-};
-u32 R600_GS_RESOURCE63_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AE9,
-};
-u32 R600_GS_RESOURCE64_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AF0,
-};
-u32 R600_GS_RESOURCE65_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AF7,
-};
-u32 R600_GS_RESOURCE66_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000AFE,
-};
-u32 R600_GS_RESOURCE67_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B05,
-};
-u32 R600_GS_RESOURCE68_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B0C,
-};
-u32 R600_GS_RESOURCE69_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B13,
-};
-u32 R600_GS_RESOURCE70_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B1A,
-};
-u32 R600_GS_RESOURCE71_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B21,
-};
-u32 R600_GS_RESOURCE72_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B28,
-};
-u32 R600_GS_RESOURCE73_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B2F,
-};
-u32 R600_GS_RESOURCE74_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B36,
-};
-u32 R600_GS_RESOURCE75_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B3D,
-};
-u32 R600_GS_RESOURCE76_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B44,
-};
-u32 R600_GS_RESOURCE77_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B4B,
-};
-u32 R600_GS_RESOURCE78_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B52,
-};
-u32 R600_GS_RESOURCE79_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B59,
-};
-u32 R600_GS_RESOURCE80_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B60,
-};
-u32 R600_GS_RESOURCE81_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B67,
-};
-u32 R600_GS_RESOURCE82_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B6E,
-};
-u32 R600_GS_RESOURCE83_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B75,
-};
-u32 R600_GS_RESOURCE84_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B7C,
-};
-u32 R600_GS_RESOURCE85_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B83,
-};
-u32 R600_GS_RESOURCE86_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B8A,
-};
-u32 R600_GS_RESOURCE87_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B91,
-};
-u32 R600_GS_RESOURCE88_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B98,
-};
-u32 R600_GS_RESOURCE89_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000B9F,
-};
-u32 R600_GS_RESOURCE90_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BA6,
-};
-u32 R600_GS_RESOURCE91_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BAD,
-};
-u32 R600_GS_RESOURCE92_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BB4,
-};
-u32 R600_GS_RESOURCE93_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BBB,
-};
-u32 R600_GS_RESOURCE94_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BC2,
-};
-u32 R600_GS_RESOURCE95_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BC9,
-};
-u32 R600_GS_RESOURCE96_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BD0,
-};
-u32 R600_GS_RESOURCE97_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BD7,
-};
-u32 R600_GS_RESOURCE98_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BDE,
-};
-u32 R600_GS_RESOURCE99_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BE5,
-};
-u32 R600_GS_RESOURCE100_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BEC,
-};
-u32 R600_GS_RESOURCE101_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BF3,
-};
-u32 R600_GS_RESOURCE102_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000BFA,
-};
-u32 R600_GS_RESOURCE103_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C01,
-};
-u32 R600_GS_RESOURCE104_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C08,
-};
-u32 R600_GS_RESOURCE105_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C0F,
-};
-u32 R600_GS_RESOURCE106_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C16,
-};
-u32 R600_GS_RESOURCE107_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C1D,
-};
-u32 R600_GS_RESOURCE108_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C24,
-};
-u32 R600_GS_RESOURCE109_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C2B,
-};
-u32 R600_GS_RESOURCE110_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C32,
-};
-u32 R600_GS_RESOURCE111_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C39,
-};
-u32 R600_GS_RESOURCE112_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C40,
-};
-u32 R600_GS_RESOURCE113_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C47,
-};
-u32 R600_GS_RESOURCE114_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C4E,
-};
-u32 R600_GS_RESOURCE115_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C55,
-};
-u32 R600_GS_RESOURCE116_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C5C,
-};
-u32 R600_GS_RESOURCE117_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C63,
-};
-u32 R600_GS_RESOURCE118_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C6A,
-};
-u32 R600_GS_RESOURCE119_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C71,
-};
-u32 R600_GS_RESOURCE120_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C78,
-};
-u32 R600_GS_RESOURCE121_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C7F,
-};
-u32 R600_GS_RESOURCE122_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C86,
-};
-u32 R600_GS_RESOURCE123_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C8D,
-};
-u32 R600_GS_RESOURCE124_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C94,
-};
-u32 R600_GS_RESOURCE125_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000C9B,
-};
-u32 R600_GS_RESOURCE126_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CA2,
-};
-u32 R600_GS_RESOURCE127_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CA9,
-};
-u32 R600_GS_RESOURCE128_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CB0,
-};
-u32 R600_GS_RESOURCE129_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CB7,
-};
-u32 R600_GS_RESOURCE130_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CBE,
-};
-u32 R600_GS_RESOURCE131_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CC5,
-};
-u32 R600_GS_RESOURCE132_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CCC,
-};
-u32 R600_GS_RESOURCE133_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CD3,
-};
-u32 R600_GS_RESOURCE134_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CDA,
-};
-u32 R600_GS_RESOURCE135_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CE1,
-};
-u32 R600_GS_RESOURCE136_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CE8,
-};
-u32 R600_GS_RESOURCE137_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CEF,
-};
-u32 R600_GS_RESOURCE138_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CF6,
-};
-u32 R600_GS_RESOURCE139_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000CFD,
-};
-u32 R600_GS_RESOURCE140_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D04,
-};
-u32 R600_GS_RESOURCE141_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D0B,
-};
-u32 R600_GS_RESOURCE142_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D12,
-};
-u32 R600_GS_RESOURCE143_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D19,
-};
-u32 R600_GS_RESOURCE144_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D20,
-};
-u32 R600_GS_RESOURCE145_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D27,
-};
-u32 R600_GS_RESOURCE146_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D2E,
-};
-u32 R600_GS_RESOURCE147_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D35,
-};
-u32 R600_GS_RESOURCE148_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D3C,
-};
-u32 R600_GS_RESOURCE149_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D43,
-};
-u32 R600_GS_RESOURCE150_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D4A,
-};
-u32 R600_GS_RESOURCE151_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D51,
-};
-u32 R600_GS_RESOURCE152_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D58,
-};
-u32 R600_GS_RESOURCE153_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D5F,
-};
-u32 R600_GS_RESOURCE154_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D66,
-};
-u32 R600_GS_RESOURCE155_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D6D,
-};
-u32 R600_GS_RESOURCE156_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D74,
-};
-u32 R600_GS_RESOURCE157_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D7B,
-};
-u32 R600_GS_RESOURCE158_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D82,
-};
-u32 R600_GS_RESOURCE159_header_pm4[R600_RESOURCE_header_cpm4] = {
-	0xC0076D00,
-	0x00000D89,
-};
-#define R600_RESOURCE_state_cpm4 11
-u32 R600_RESOURCE_state_pm4[R600_RESOURCE_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x80000000,
-	0xC0001000,
-	0x00000000,
-	0xC0001000,
-	0x00000000,
-};
-
-/* R600_SAMPLER */
-#define R600_SAMPLER_header_cpm4 2
-u32 R600_PS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000000,
-};
-u32 R600_PS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000003,
-};
-u32 R600_PS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000006,
-};
-u32 R600_PS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000009,
-};
-u32 R600_PS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000000C,
-};
-u32 R600_PS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000000F,
-};
-u32 R600_PS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000012,
-};
-u32 R600_PS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000015,
-};
-u32 R600_PS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000018,
-};
-u32 R600_PS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000001B,
-};
-u32 R600_PS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000001E,
-};
-u32 R600_PS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000021,
-};
-u32 R600_PS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000024,
-};
-u32 R600_PS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000027,
-};
-u32 R600_PS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000002A,
-};
-u32 R600_PS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000002D,
-};
-u32 R600_PS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000030,
-};
-u32 R600_PS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000033,
-};
-u32 R600_VS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000036,
-};
-u32 R600_VS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000039,
-};
-u32 R600_VS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000003C,
-};
-u32 R600_VS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000003F,
-};
-u32 R600_VS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000042,
-};
-u32 R600_VS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000045,
-};
-u32 R600_VS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000048,
-};
-u32 R600_VS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000004B,
-};
-u32 R600_VS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000004E,
-};
-u32 R600_VS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000051,
-};
-u32 R600_VS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000054,
-};
-u32 R600_VS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000057,
-};
-u32 R600_VS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000005A,
-};
-u32 R600_VS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000005D,
-};
-u32 R600_VS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000060,
-};
-u32 R600_VS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000063,
-};
-u32 R600_VS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000066,
-};
-u32 R600_VS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000069,
-};
-u32 R600_GS_SAMPLER0_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000006C,
-};
-u32 R600_GS_SAMPLER1_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000006F,
-};
-u32 R600_GS_SAMPLER2_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000072,
-};
-u32 R600_GS_SAMPLER3_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000075,
-};
-u32 R600_GS_SAMPLER4_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000078,
-};
-u32 R600_GS_SAMPLER5_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000007B,
-};
-u32 R600_GS_SAMPLER6_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000007E,
-};
-u32 R600_GS_SAMPLER7_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000081,
-};
-u32 R600_GS_SAMPLER8_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000084,
-};
-u32 R600_GS_SAMPLER9_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000087,
-};
-u32 R600_GS_SAMPLER10_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000008A,
-};
-u32 R600_GS_SAMPLER11_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000008D,
-};
-u32 R600_GS_SAMPLER12_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000090,
-};
-u32 R600_GS_SAMPLER13_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000093,
-};
-u32 R600_GS_SAMPLER14_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000096,
-};
-u32 R600_GS_SAMPLER15_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x00000099,
-};
-u32 R600_GS_SAMPLER16_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000009C,
-};
-u32 R600_GS_SAMPLER17_header_pm4[R600_SAMPLER_header_cpm4] = {
-	0xC0036E00,
-	0x0000009F,
-};
-#define R600_SAMPLER_state_cpm4 3
-u32 R600_SAMPLER_state_pm4[R600_SAMPLER_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-/* R600_SAMPLER_BORDER */
-#define R600_SAMPLER_BORDER_header_cpm4 2
-u32 R600_PS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000900,
-};
-u32 R600_PS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000904,
-};
-u32 R600_PS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000908,
-};
-u32 R600_PS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x0000090C,
-};
-u32 R600_PS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000910,
-};
-u32 R600_PS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000914,
-};
-u32 R600_PS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000918,
-};
-u32 R600_PS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x0000091C,
-};
-u32 R600_PS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000920,
-};
-u32 R600_PS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000924,
-};
-u32 R600_PS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000928,
-};
-u32 R600_PS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x0000092C,
-};
-u32 R600_PS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000930,
-};
-u32 R600_PS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000934,
-};
-u32 R600_PS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000938,
-};
-u32 R600_PS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x0000093C,
-};
-u32 R600_PS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000940,
-};
-u32 R600_PS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000944,
-};
-u32 R600_VS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000980,
-};
-u32 R600_VS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000984,
-};
-u32 R600_VS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000988,
-};
-u32 R600_VS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x0000098C,
-};
-u32 R600_VS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000990,
-};
-u32 R600_VS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000994,
-};
-u32 R600_VS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000998,
-};
-u32 R600_VS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x0000099C,
-};
-u32 R600_VS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009A0,
-};
-u32 R600_VS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009A4,
-};
-u32 R600_VS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009A8,
-};
-u32 R600_VS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009AC,
-};
-u32 R600_VS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009B0,
-};
-u32 R600_VS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009B4,
-};
-u32 R600_VS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009B8,
-};
-u32 R600_VS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009BC,
-};
-u32 R600_VS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009C0,
-};
-u32 R600_VS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x000009C4,
-};
-u32 R600_GS_SAMPLER_BORDER0_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A00,
-};
-u32 R600_GS_SAMPLER_BORDER1_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A04,
-};
-u32 R600_GS_SAMPLER_BORDER2_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A08,
-};
-u32 R600_GS_SAMPLER_BORDER3_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A0C,
-};
-u32 R600_GS_SAMPLER_BORDER4_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A10,
-};
-u32 R600_GS_SAMPLER_BORDER5_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A14,
-};
-u32 R600_GS_SAMPLER_BORDER6_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A18,
-};
-u32 R600_GS_SAMPLER_BORDER7_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A1C,
-};
-u32 R600_GS_SAMPLER_BORDER8_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A20,
-};
-u32 R600_GS_SAMPLER_BORDER9_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A24,
-};
-u32 R600_GS_SAMPLER_BORDER10_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A28,
-};
-u32 R600_GS_SAMPLER_BORDER11_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A2C,
-};
-u32 R600_GS_SAMPLER_BORDER12_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A30,
-};
-u32 R600_GS_SAMPLER_BORDER13_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A34,
-};
-u32 R600_GS_SAMPLER_BORDER14_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A38,
-};
-u32 R600_GS_SAMPLER_BORDER15_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A3C,
-};
-u32 R600_GS_SAMPLER_BORDER16_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A40,
-};
-u32 R600_GS_SAMPLER_BORDER17_header_pm4[R600_SAMPLER_BORDER_header_cpm4] = {
-	0xC0046800,
-	0x00000A44,
-};
-#define R600_SAMPLER_BORDER_state_cpm4 4
-u32 R600_SAMPLER_BORDER_state_pm4[R600_SAMPLER_BORDER_state_cpm4] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const struct radeon_type R600_types[] = {
-	{R600_CONFIG_header_pm4, R600_CONFIG_header_cpm4, R600_CONFIG_state_pm4, R600_CONFIG_state_cpm4, 0, 0},
-	{R600_CB_CNTL_header_pm4, R600_CB_CNTL_header_cpm4, R600_CB_CNTL_state_pm4, R600_CB_CNTL_state_cpm4, 0, 0},
-	{R600_RASTERIZER_header_pm4, R600_RASTERIZER_header_cpm4, R600_RASTERIZER_state_pm4, R600_RASTERIZER_state_cpm4, 0, 0},
-	{R600_VIEWPORT_header_pm4, R600_VIEWPORT_header_cpm4, R600_VIEWPORT_state_pm4, R600_VIEWPORT_state_cpm4, 0, 0},
-	{R600_SCISSOR_header_pm4, R600_SCISSOR_header_cpm4, R600_SCISSOR_state_pm4, R600_SCISSOR_state_cpm4, 0, 0},
-	{R600_BLEND_header_pm4, R600_BLEND_header_cpm4, R600_BLEND_state_pm4, R600_BLEND_state_cpm4, 0, 0},
-	{R600_DSA_header_pm4, R600_DSA_header_cpm4, R600_DSA_state_pm4, R600_DSA_state_cpm4, 0, 0},
-	{R600_VGT_header_pm4, R600_VGT_header_cpm4, R600_VGT_state_pm4, R600_VGT_state_cpm4, 0, 0},
-	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
-	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
-	{R600_VS_SHADER_header_pm4, R600_VS_SHADER_header_cpm4, R600_VS_SHADER_state_pm4, R600_VS_SHADER_state_cpm4, 0, 0},
-	{R600_PS_SHADER_header_pm4, R600_PS_SHADER_header_cpm4, R600_PS_SHADER_state_pm4, R600_PS_SHADER_state_cpm4, 0, 0},
-	{R600_DB_header_pm4, R600_DB_header_cpm4, R600_DB_state_pm4, R600_DB_state_cpm4, R600_FLUSH_DB, R600_DIRTY_ALL},
-	{R600_CB0_header_pm4, R600_CB0_header_cpm4, R600_CB0_state_pm4, R600_CB0_state_cpm4, R600_FLUSH_CB0, R600_DIRTY_ALL},
-	{R600_CB1_header_pm4, R600_CB1_header_cpm4, R600_CB1_state_pm4, R600_CB1_state_cpm4, R600_FLUSH_CB1, R600_DIRTY_ALL},
-	{R600_CB2_header_pm4, R600_CB2_header_cpm4, R600_CB2_state_pm4, R600_CB2_state_cpm4, R600_FLUSH_CB2, R600_DIRTY_ALL},
-	{R600_CB3_header_pm4, R600_CB3_header_cpm4, R600_CB3_state_pm4, R600_CB3_state_cpm4, R600_FLUSH_CB3, R600_DIRTY_ALL},
-	{R600_CB4_header_pm4, R600_CB4_header_cpm4, R600_CB4_state_pm4, R600_CB4_state_cpm4, R600_FLUSH_CB4, R600_DIRTY_ALL},
-	{R600_CB5_header_pm4, R600_CB5_header_cpm4, R600_CB5_state_pm4, R600_CB5_state_cpm4, R600_FLUSH_CB5, R600_DIRTY_ALL},
-	{R600_CB6_header_pm4, R600_CB6_header_cpm4, R600_CB6_state_pm4, R600_CB6_state_cpm4, R600_FLUSH_CB6, R600_DIRTY_ALL},
-	{R600_CB7_header_pm4, R600_CB7_header_cpm4, R600_CB7_state_pm4, R600_CB7_state_cpm4, R600_FLUSH_CB7, R600_DIRTY_ALL},
-	{R600_UCP0_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP1_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP2_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP3_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP4_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP5_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_PS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_DRAW_AUTO_header_pm4, R600_DRAW_AUTO_header_cpm4, R600_DRAW_AUTO_state_pm4, R600_DRAW_AUTO_state_cpm4, 0, 0},
-	{R600_DRAW_header_pm4, R600_DRAW_header_cpm4, R600_DRAW_state_pm4, R600_DRAW_state_cpm4, 0, 0}
-};
-
-static const struct radeon_type R700_types[] = {
-	{R700_CONFIG_header_pm4, R700_CONFIG_header_cpm4, R600_CONFIG_state_pm4, R600_CONFIG_state_cpm4, 0, 0},
-	{R600_CB_CNTL_header_pm4, R600_CB_CNTL_header_cpm4, R600_CB_CNTL_state_pm4, R600_CB_CNTL_state_cpm4, 0, 0},
-	{R600_RASTERIZER_header_pm4, R600_RASTERIZER_header_cpm4, R600_RASTERIZER_state_pm4, R600_RASTERIZER_state_cpm4, 0, 0},
-	{R600_VIEWPORT_header_pm4, R600_VIEWPORT_header_cpm4, R600_VIEWPORT_state_pm4, R600_VIEWPORT_state_cpm4, 0, 0},
-	{R600_SCISSOR_header_pm4, R600_SCISSOR_header_cpm4, R600_SCISSOR_state_pm4, R600_SCISSOR_state_cpm4, 0, 0},
-	{R600_BLEND_header_pm4, R600_BLEND_header_cpm4, R600_BLEND_state_pm4, R600_BLEND_state_cpm4, 0, 0},
-	{R600_DSA_header_pm4, R600_DSA_header_cpm4, R600_DSA_state_pm4, R600_DSA_state_cpm4, 0, 0},
-	{R600_VGT_header_pm4, R600_VGT_header_cpm4, R600_VGT_state_pm4, R600_VGT_state_cpm4, 0, 0},
-	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
-	{R600_QUERY_header_pm4, R600_QUERY_header_cpm4, R600_QUERY_state_pm4, R600_QUERY_state_cpm4, 0, 0},
-	{R600_VS_SHADER_header_pm4, R600_VS_SHADER_header_cpm4, R600_VS_SHADER_state_pm4, R600_VS_SHADER_state_cpm4, 0, 0},
-	{R600_PS_SHADER_header_pm4, R600_PS_SHADER_header_cpm4, R600_PS_SHADER_state_pm4, R600_PS_SHADER_state_cpm4, 0, 0},
-	{R600_DB_header_pm4, R600_DB_header_cpm4, R600_DB_state_pm4, R600_DB_state_cpm4, R600_FLUSH_DB, R600_DIRTY_ALL},
-	{R600_CB0_header_pm4, R600_CB0_header_cpm4, R600_CB0_state_pm4, R600_CB0_state_cpm4, R600_FLUSH_CB0, R600_DIRTY_ALL},
-	{R600_CB1_header_pm4, R600_CB1_header_cpm4, R600_CB1_state_pm4, R600_CB1_state_cpm4, R600_FLUSH_CB1, R600_DIRTY_ALL},
-	{R600_CB2_header_pm4, R600_CB2_header_cpm4, R600_CB2_state_pm4, R600_CB2_state_cpm4, R600_FLUSH_CB2, R600_DIRTY_ALL},
-	{R600_CB3_header_pm4, R600_CB3_header_cpm4, R600_CB3_state_pm4, R600_CB3_state_cpm4, R600_FLUSH_CB3, R600_DIRTY_ALL},
-	{R600_CB4_header_pm4, R600_CB4_header_cpm4, R600_CB4_state_pm4, R600_CB4_state_cpm4, R600_FLUSH_CB4, R600_DIRTY_ALL},
-	{R600_CB5_header_pm4, R600_CB5_header_cpm4, R600_CB5_state_pm4, R600_CB5_state_cpm4, R600_FLUSH_CB5, R600_DIRTY_ALL},
-	{R600_CB6_header_pm4, R600_CB6_header_cpm4, R600_CB6_state_pm4, R600_CB6_state_cpm4, R600_FLUSH_CB6, R600_DIRTY_ALL},
-	{R600_CB7_header_pm4, R600_CB7_header_cpm4, R600_CB7_state_pm4, R600_CB7_state_cpm4, R600_FLUSH_CB7, R600_DIRTY_ALL},
-	{R600_UCP0_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP1_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP2_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP3_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP4_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_UCP5_header_pm4, R600_UCP_header_cpm4, R600_UCP_state_pm4, R600_UCP_state_cpm4, 0, 0},
-	{R600_PS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_VS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_FS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE0_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE1_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE2_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE3_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE4_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE5_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE6_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE7_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE8_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE9_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE10_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE11_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE12_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE13_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE14_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE15_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE16_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE17_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE18_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE19_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE20_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE21_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE22_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE23_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE24_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE25_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE26_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE27_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE28_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE29_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE30_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE31_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE32_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE33_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE34_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE35_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE36_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE37_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE38_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE39_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE40_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE41_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE42_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE43_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE44_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE45_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE46_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE47_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE48_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE49_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE50_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE51_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE52_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE53_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE54_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE55_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE56_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE57_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE58_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE59_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE60_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE61_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE62_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE63_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE64_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE65_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE66_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE67_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE68_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE69_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE70_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE71_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE72_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE73_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE74_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE75_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE76_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE77_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE78_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE79_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE80_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE81_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE82_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE83_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE84_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE85_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE86_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE87_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE88_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE89_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE90_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE91_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE92_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE93_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE94_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE95_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE96_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE97_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE98_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE99_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE100_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE101_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE102_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE103_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE104_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE105_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE106_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE107_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE108_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE109_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE110_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE111_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE112_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE113_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE114_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE115_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE116_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE117_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE118_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE119_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE120_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE121_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE122_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE123_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE124_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE125_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE126_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE127_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE128_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE129_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE130_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE131_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE132_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE133_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE134_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE135_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE136_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE137_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE138_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE139_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE140_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE141_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE142_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE143_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE144_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE145_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE146_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE147_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE148_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE149_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE150_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE151_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE152_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE153_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE154_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE155_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE156_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE157_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE158_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_GS_RESOURCE159_header_pm4, R600_RESOURCE_header_cpm4, R600_RESOURCE_state_pm4, R600_RESOURCE_state_cpm4, R600_FLUSH_RESOURCE, 0},
-	{R600_PS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT0_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT1_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT2_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT3_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT4_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT5_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT6_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT7_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT8_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT9_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT10_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT11_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT12_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT13_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT14_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT15_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT16_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT17_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT18_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT19_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT20_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT21_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT22_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT23_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT24_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT25_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT26_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT27_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT28_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT29_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT30_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT31_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT32_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT33_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT34_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT35_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT36_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT37_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT38_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT39_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT40_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT41_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT42_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT43_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT44_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT45_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT46_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT47_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT48_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT49_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT50_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT51_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT52_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT53_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT54_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT55_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT56_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT57_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT58_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT59_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT60_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT61_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT62_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT63_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT64_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT65_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT66_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT67_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT68_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT69_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT70_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT71_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT72_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT73_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT74_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT75_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT76_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT77_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT78_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT79_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT80_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT81_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT82_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT83_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT84_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT85_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT86_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT87_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT88_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT89_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT90_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT91_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT92_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT93_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT94_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT95_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT96_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT97_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT98_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT99_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT100_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT101_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT102_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT103_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT104_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT105_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT106_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT107_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT108_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT109_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT110_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT111_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT112_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT113_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT114_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT115_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT116_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT117_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT118_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT119_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT120_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT121_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT122_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT123_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT124_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT125_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT126_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT127_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT128_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT129_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT130_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT131_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT132_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT133_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT134_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT135_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT136_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT137_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT138_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT139_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT140_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT141_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT142_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT143_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT144_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT145_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT146_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT147_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT148_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT149_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT150_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT151_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT152_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT153_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT154_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT155_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT156_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT157_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT158_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT159_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT160_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT161_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT162_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT163_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT164_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT165_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT166_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT167_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT168_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT169_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT170_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT171_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT172_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT173_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT174_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT175_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT176_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT177_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT178_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT179_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT180_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT181_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT182_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT183_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT184_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT185_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT186_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT187_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT188_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT189_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT190_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT191_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT192_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT193_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT194_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT195_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT196_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT197_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT198_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT199_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT200_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT201_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT202_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT203_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT204_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT205_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT206_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT207_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT208_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT209_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT210_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT211_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT212_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT213_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT214_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT215_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT216_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT217_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT218_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT219_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT220_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT221_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT222_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT223_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT224_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT225_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT226_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT227_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT228_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT229_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT230_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT231_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT232_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT233_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT234_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT235_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT236_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT237_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT238_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT239_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT240_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT241_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT242_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT243_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT244_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT245_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT246_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT247_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT248_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT249_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT250_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT251_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT252_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT253_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT254_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_VS_CONSTANT255_header_pm4, R600_CONSTANT_header_cpm4, R600_CONSTANT_state_pm4, R600_CONSTANT_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER0_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER1_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER2_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER3_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER4_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER5_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER6_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER7_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER8_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER9_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER10_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER11_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER12_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER13_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER14_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER15_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER16_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER17_header_pm4, R600_SAMPLER_header_cpm4, R600_SAMPLER_state_pm4, R600_SAMPLER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_PS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_VS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER0_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER1_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER2_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER3_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER4_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER5_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER6_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER7_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER8_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER9_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER10_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER11_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER12_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER13_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER14_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER15_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER16_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_GS_SAMPLER_BORDER17_header_pm4, R600_SAMPLER_BORDER_header_cpm4, R600_SAMPLER_BORDER_state_pm4, R600_SAMPLER_BORDER_state_cpm4, 0, 0},
-	{R600_DRAW_AUTO_header_pm4, R600_DRAW_AUTO_header_cpm4, R600_DRAW_AUTO_state_pm4, R600_DRAW_AUTO_state_cpm4, 0, 0},
-	{R600_DRAW_header_pm4, R600_DRAW_header_cpm4, R600_DRAW_state_pm4, R600_DRAW_state_cpm4, 0, 0}
-};
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
new file mode 100644
index 0000000000..b5365e4275
--- /dev/null
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -0,0 +1,562 @@
+/*
+ * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#ifndef R600_STATES_H
+#define R600_STATES_H
+
+static const struct radeon_register R600_CONFIG_names[] = {
+	{0x00008C00, 0, 0, "SQ_CONFIG"},
+	{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
+	{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
+	{0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"},
+	{0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
+	{0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
+	{0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
+	{0x00009508, 0, 0, "TA_CNTL_AUX"},
+	{0x00009714, 0, 0, "VC_ENHANCE"},
+	{0x00009830, 0, 0, "DB_DEBUG"},
+	{0x00009838, 0, 0, "DB_WATERMARKS"},
+	{0x00028350, 0, 0, "SX_MISC"},
+	{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
+	{0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
+	{0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
+	{0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
+	{0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
+	{0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
+	{0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
+	{0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
+	{0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"},
+	{0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"},
+	{0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
+	{0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
+	{0x00028A14, 0, 0, "VGT_HOS_CNTL"},
+	{0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
+	{0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
+	{0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
+	{0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
+	{0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
+	{0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
+	{0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
+	{0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
+	{0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
+	{0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
+	{0x00028A40, 0, 0, "VGT_GS_MODE"},
+	{0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"},
+	{0x00028AB0, 0, 0, "VGT_STRMOUT_EN"},
+	{0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
+	{0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
+	{0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
+};
+
+static const struct radeon_register R600_CB_CNTL_names[] = {
+	{0x00028120, 0, 0, "CB_CLEAR_RED"},
+	{0x00028124, 0, 0, "CB_CLEAR_GREEN"},
+	{0x00028128, 0, 0, "CB_CLEAR_BLUE"},
+	{0x0002812C, 0, 0, "CB_CLEAR_ALPHA"},
+	{0x0002823C, 0, 0, "CB_SHADER_MASK"},
+	{0x00028238, 0, 0, "CB_TARGET_MASK"},
+	{0x00028424, 0, 0, "CB_FOG_RED"},
+	{0x00028428, 0, 0, "CB_FOG_GREEN"},
+	{0x0002842C, 0, 0, "CB_FOG_BLUE"},
+	{0x00028808, 0, 0, "CB_COLOR_CONTROL"},
+	{0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
+	{0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
+	{0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"},
+	{0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"},
+	{0x00028C34, 0, 0, "CB_CLRCMP_SRC"},
+	{0x00028C38, 0, 0, "CB_CLRCMP_DST"},
+	{0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
+	{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
+};
+
+static const struct radeon_register R600_RASTERIZER_names[] = {
+	{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
+	{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
+	{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
+	{0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
+	{0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
+	{0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
+	{0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
+	{0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
+	{0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"},
+	{0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
+	{0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
+	{0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
+	{0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
+	{0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
+	{0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
+	{0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
+	{0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
+	{0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
+	{0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
+	{0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
+	{0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
+};
+
+static const struct radeon_register R600_VIEWPORT_names[] = {
+	{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
+	{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
+	{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
+	{0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
+	{0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
+	{0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
+	{0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
+	{0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
+	{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
+};
+
+static const struct radeon_register R600_SCISSOR_names[] = {
+	{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
+	{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
+	{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
+	{0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
+	{0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
+	{0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
+	{0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
+	{0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
+	{0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
+	{0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
+	{0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
+	{0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
+	{0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
+	{0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
+	{0x00028230, 0, 0, "PA_SC_EDGERULE"},
+	{0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
+	{0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
+	{0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
+	{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
+};
+
+static const struct radeon_register R600_BLEND_names[] = {
+	{0x00028414, 0, 0, "CB_BLEND_RED"},
+	{0x00028418, 0, 0, "CB_BLEND_GREEN"},
+	{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
+	{0x00028420, 0, 0, "CB_BLEND_ALPHA"},
+	{0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
+	{0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
+	{0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
+	{0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
+	{0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
+	{0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
+	{0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
+	{0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
+	{0x00028804, 0, 0, "CB_BLEND_CONTROL"},
+};
+
+static const struct radeon_register R600_DSA_names[] = {
+	{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
+	{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
+	{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
+	{0x00028430, 0, 0, "DB_STENCILREFMASK"},
+	{0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
+	{0x00028438, 0, 0, "SX_ALPHA_REF"},
+	{0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"},
+	{0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"},
+	{0x000286DC, 0, 0, "SPI_FOG_CNTL"},
+	{0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
+	{0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
+	{0x00028D0C, 0, 0, "DB_RENDER_CONTROL"},
+	{0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"},
+	{0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
+	{0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"},
+	{0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
+};
+
+static const struct radeon_register R600_VS_SHADER_names[] = {
+	{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
+	{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
+	{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
+	{0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
+	{0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
+	{0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
+	{0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
+	{0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
+	{0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
+	{0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
+	{0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
+	{0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
+	{0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
+	{0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
+	{0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
+	{0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
+	{0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
+	{0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
+	{0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
+	{0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
+	{0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
+	{0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
+	{0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
+	{0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
+	{0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
+	{0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
+	{0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
+	{0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
+	{0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
+	{0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
+	{0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
+	{0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
+	{0x00028614, 0, 0, "SPI_VS_OUT_ID_0"},
+	{0x00028618, 0, 0, "SPI_VS_OUT_ID_1"},
+	{0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"},
+	{0x00028620, 0, 0, "SPI_VS_OUT_ID_3"},
+	{0x00028624, 0, 0, "SPI_VS_OUT_ID_4"},
+	{0x00028628, 0, 0, "SPI_VS_OUT_ID_5"},
+	{0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"},
+	{0x00028630, 0, 0, "SPI_VS_OUT_ID_7"},
+	{0x00028634, 0, 0, "SPI_VS_OUT_ID_8"},
+	{0x00028638, 0, 0, "SPI_VS_OUT_ID_9"},
+	{0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
+	{0x00028858, 1, 0, "SQ_PGM_START_VS"},
+	{0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"},
+	{0x00028894, 1, 1, "SQ_PGM_START_FS"},
+	{0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"},
+	{0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"},
+	{0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
+};
+
+static const struct radeon_register R600_PS_SHADER_names[] = {
+	{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
+	{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
+	{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
+	{0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
+	{0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
+	{0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
+	{0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
+	{0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
+	{0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
+	{0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
+	{0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
+	{0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
+	{0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
+	{0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
+	{0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
+	{0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
+	{0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
+	{0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
+	{0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
+	{0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
+	{0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
+	{0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
+	{0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
+	{0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
+	{0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
+	{0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
+	{0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
+	{0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
+	{0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
+	{0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
+	{0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
+	{0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
+	{0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
+	{0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
+	{0x000286D8, 0, 0, "SPI_INPUT_Z"},
+	{0x00028840, 1, 0, "SQ_PGM_START_PS"},
+	{0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"},
+	{0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"},
+	{0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
+};
+
+static const struct radeon_register R600_PS_CONSTANT_names[] = {
+	{0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
+	{0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
+	{0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
+	{0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
+};
+
+static const struct radeon_register R600_VS_CONSTANT_names[] = {
+	{0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
+	{0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
+	{0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
+	{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
+};
+
+static const struct radeon_register R600_UCP_names[] = {
+	{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
+	{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
+	{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
+	{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
+};
+
+static const struct radeon_register R600_PS_RESOURCE_names[] = {
+	{0x00038000, 0, 0, "RESOURCE0_WORD0"},
+	{0x00038004, 0, 0, "RESOURCE0_WORD1"},
+	{0x00038008, 0, 0, "RESOURCE0_WORD2"},
+	{0x0003800C, 0, 0, "RESOURCE0_WORD3"},
+	{0x00038010, 0, 0, "RESOURCE0_WORD4"},
+	{0x00038014, 0, 0, "RESOURCE0_WORD5"},
+	{0x00038018, 0, 0, "RESOURCE0_WORD6"},
+};
+
+static const struct radeon_register R600_VS_RESOURCE_names[] = {
+	{0x00039180, 0, 0, "RESOURCE160_WORD0"},
+	{0x00039184, 0, 0, "RESOURCE160_WORD1"},
+	{0x00039188, 0, 0, "RESOURCE160_WORD2"},
+	{0x0003918C, 0, 0, "RESOURCE160_WORD3"},
+	{0x00039190, 0, 0, "RESOURCE160_WORD4"},
+	{0x00039194, 0, 0, "RESOURCE160_WORD5"},
+	{0x00039198, 0, 0, "RESOURCE160_WORD6"},
+};
+
+static const struct radeon_register R600_FS_RESOURCE_names[] = {
+	{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
+	{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
+	{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
+	{0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
+	{0x0003A310, 0, 0, "RESOURCE320_WORD4"},
+	{0x0003A314, 0, 0, "RESOURCE320_WORD5"},
+	{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
+};
+
+static const struct radeon_register R600_GS_RESOURCE_names[] = {
+	{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
+	{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
+	{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
+	{0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
+	{0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
+	{0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
+	{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
+};
+
+static const struct radeon_register R600_PS_SAMPLER_names[] = {
+	{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
+	{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
+	{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
+};
+
+static const struct radeon_register R600_VS_SAMPLER_names[] = {
+	{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
+	{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
+	{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
+};
+
+static const struct radeon_register R600_GS_SAMPLER_names[] = {
+	{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
+	{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
+	{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
+};
+
+static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = {
+	{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
+	{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = {
+	{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
+	{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = {
+	{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
+	{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register R600_CB0_names[] = {
+	{0x00028040, 1, 0, "CB_COLOR0_BASE"},
+	{0x000280A0, 0, 0, "CB_COLOR0_INFO"},
+	{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
+	{0x00028080, 0, 0, "CB_COLOR0_VIEW"},
+	{0x000280E0, 1, 1, "CB_COLOR0_FRAG"},
+	{0x000280C0, 1, 2, "CB_COLOR0_TILE"},
+	{0x00028100, 0, 0, "CB_COLOR0_MASK"},
+};
+
+static const struct radeon_register R600_CB1_names[] = {
+	{0x00028044, 1, 0, "CB_COLOR1_BASE"},
+	{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
+	{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
+	{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
+	{0x000280E4, 1, 1, "CB_COLOR1_FRAG"},
+	{0x000280C4, 1, 2, "CB_COLOR1_TILE"},
+	{0x00028104, 0, 0, "CB_COLOR1_MASK"},
+};
+
+static const struct radeon_register R600_CB2_names[] = {
+	{0x00028048, 1, 0, "CB_COLOR2_BASE"},
+	{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
+	{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
+	{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
+	{0x000280E8, 1, 1, "CB_COLOR2_FRAG"},
+	{0x000280C8, 1, 2, "CB_COLOR2_TILE"},
+	{0x00028108, 0, 0, "CB_COLOR2_MASK"},
+};
+
+static const struct radeon_register R600_CB3_names[] = {
+	{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
+	{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
+	{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
+	{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
+	{0x000280EC, 1, 1, "CB_COLOR3_FRAG"},
+	{0x000280CC, 1, 2, "CB_COLOR3_TILE"},
+	{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
+};
+
+static const struct radeon_register R600_CB4_names[] = {
+	{0x00028050, 1, 0, "CB_COLOR4_BASE"},
+	{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
+	{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
+	{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
+	{0x000280F0, 1, 1, "CB_COLOR4_FRAG"},
+	{0x000280D0, 1, 2, "CB_COLOR4_TILE"},
+	{0x00028110, 0, 0, "CB_COLOR4_MASK"},
+};
+
+static const struct radeon_register R600_CB5_names[] = {
+	{0x00028054, 1, 0, "CB_COLOR5_BASE"},
+	{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
+	{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
+	{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
+	{0x000280F4, 1, 1, "CB_COLOR5_FRAG"},
+	{0x000280D4, 1, 2, "CB_COLOR5_TILE"},
+	{0x00028114, 0, 0, "CB_COLOR5_MASK"},
+};
+
+static const struct radeon_register R600_CB6_names[] = {
+	{0x00028058, 1, 0, "CB_COLOR6_BASE"},
+	{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
+	{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
+	{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
+	{0x000280F8, 1, 1, "CB_COLOR6_FRAG"},
+	{0x000280D8, 1, 2, "CB_COLOR6_TILE"},
+	{0x00028118, 0, 0, "CB_COLOR6_MASK"},
+};
+
+static const struct radeon_register R600_CB7_names[] = {
+	{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
+	{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
+	{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
+	{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
+	{0x000280FC, 1, 1, "CB_COLOR7_FRAG"},
+	{0x000280DC, 1, 2, "CB_COLOR7_TILE"},
+	{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
+};
+
+static const struct radeon_register R600_DB_names[] = {
+	{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
+	{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
+	{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
+	{0x00028010, 0, 0, "DB_DEPTH_INFO"},
+	{0x00028D24, 0, 0, "DB_HTILE_SURFACE"},
+	{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
+};
+
+static const struct radeon_register R600_VGT_names[] = {
+	{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
+	{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
+	{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
+	{0x00028408, 0, 0, "VGT_INDX_OFFSET"},
+	{0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"},
+	{0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"},
+	{0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"},
+	{0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"},
+	{0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"},
+	{0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"},
+	{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
+};
+
+static const struct radeon_register R600_DRAW_names[] = {
+	{0x00008970, 0, 0, "VGT_NUM_INDICES"},
+	{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},
+	{0x000287E8, 1, 0, "VGT_DMA_BASE"},
+	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
+};
+
+static const struct radeon_register R600_VGT_EVENT_names[] = {
+	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
+};
+
+static struct radeon_type R600_types[] = {
+	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
+	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
+	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
+	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
+	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
+	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
+	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
+	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
+	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
+	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
+	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
+	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
+	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
+	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
+	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
+	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
+	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
+	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
+	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
+	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
+	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
+	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+};
+
+static struct radeon_type R700_types[] = {
+	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names},
+	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
+	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
+	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
+	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
+	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
+	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
+	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
+	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
+	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
+	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
+	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
+	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
+	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
+	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
+	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
+	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
+	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
+	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
+	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
+	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
+	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
+	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
+	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
+	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
+	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
+	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
+	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
+	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
+	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
+};
+
+#endif
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 2b16e3ce88..80b0a1d397 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -153,3 +153,47 @@ struct radeon *radeon_decref(struct radeon *radeon)
 	free(radeon);
 	return NULL;
 }
+
+int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id)
+{
+	unsigned i, j;
+
+	for (i = 0; i < radeon->ntype; i++) {
+		if (radeon->type[i].range_start) {
+			if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) {
+				*typeid = i;
+				j = offset - radeon->type[i].range_start;
+				j /= radeon->type[i].stride;
+				*stateid = radeon->type[i].id + j;
+				*id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4;
+				return 0;
+			}
+		} else {
+			for (j = 0; j < radeon->type[i].nstates; j++) {
+				if (radeon->type[i].regs[j].offset == offset) {
+					*typeid = i;
+					*stateid = radeon->type[i].id;
+					*id = j;
+					return 0;
+				}
+			}
+		}
+	}
+	fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset);
+	return -EINVAL;
+}
+
+unsigned radeon_type_from_id(struct radeon *radeon, unsigned id)
+{
+	unsigned i;
+
+	for (i = 0; i < radeon->ntype - 1; i++) {
+		if (radeon->type[i].id == id)
+			return i;
+		if (id > radeon->type[i].id && id < radeon->type[i + 1].id)
+			return i;
+	}
+	if (radeon->type[i].id == id)
+		return i;
+	return -1;
+}
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index b8ba9b552d..bd050c4cf9 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -26,40 +26,54 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <unistd.h>
 #include "radeon_priv.h"
 #include "radeon_drm.h"
 #include "bof.h"
 
-static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo, unsigned state_id)
+int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo)
 {
-	ctx->bo[ctx->nbo].bo = bo;
-	ctx->bo[ctx->nbo].bo_flushed = 0;
-	ctx->bo[ctx->nbo].state_id = state_id;
+	void *ptr;
+
+	ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1));
+	if (ptr == NULL) {
+		return -ENOMEM;
+	}
+	ctx->bo = ptr;
+	ctx->bo[ctx->nbo] = bo;
 	ctx->nbo++;
 	return 0;
 }
 
-void radeon_ctx_clear(struct radeon_ctx *ctx)
+struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc)
 {
+	struct radeon_cs_reloc *greloc;
 	unsigned i;
 
-	/* FIXME somethings is wrong, it should be safe to
-	 * delete bo here, kernel should postpone bo deletion
-	 * until bo is no longer referenced by cs (through the
-	 * fence association)
-	 */
-	for (i = 0; i < 50; i++) {
-		usleep(10);
+	greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4);
+	for (i = 0; i < ctx->nbo; i++) {
+		if (ctx->bo[i]->handle == greloc->handle) {
+			return radeon_bo_incref(ctx->radeon, ctx->bo[i]);
+		}
 	}
+	fprintf(stderr, "%s no bo for reloc[%d 0x%08X] %d\n", __func__, reloc, greloc->handle, ctx->nbo);
+	return NULL;
+}
+
+void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement)
+{
+	struct radeon_cs_reloc *greloc;
+	unsigned i;
+
+	placement[0] = 0;
+	placement[1] = 0;
+	greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4);
 	for (i = 0; i < ctx->nbo; i++) {
-		ctx->bo[i].bo = radeon_bo_decref(ctx->radeon, ctx->bo[i].bo);
+		if (ctx->bo[i]->handle == greloc->handle) {
+			placement[0] = greloc->read_domain | greloc->write_domain;
+			placement[1] = placement[0];
+			return;
+		}
 	}
-	ctx->id = 0;
-	ctx->npm4 = RADEON_CTX_MAX_PM4;
-	ctx->nreloc = 0;
-	ctx->nbo = 0;
-	memset(ctx->state_crc32, 0, ctx->radeon->nstate * 4);
 }
 
 struct radeon_ctx *radeon_ctx(struct radeon *radeon)
@@ -72,25 +86,6 @@ struct radeon_ctx *radeon_ctx(struct radeon *radeon)
 	if (ctx == NULL)
 		return NULL;
 	ctx->radeon = radeon_incref(radeon);
-	ctx->max_bo = 4096;
-	ctx->max_reloc = 4096;
-	ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4);
-	if (ctx->pm4 == NULL) {
-		return radeon_ctx_decref(ctx);
-	}
-	ctx->state_crc32 = malloc(ctx->radeon->nstate * 4);
-	if (ctx->state_crc32 == NULL) {
-		return radeon_ctx_decref(ctx);
-	}
-	ctx->bo = malloc(ctx->max_bo * sizeof(struct radeon_ctx_bo));
-	if (ctx->bo == NULL) {
-		return radeon_ctx_decref(ctx);
-	}
-	ctx->reloc = malloc(ctx->max_reloc * sizeof(struct radeon_cs_reloc));
-	if (ctx->reloc == NULL) {
-		return radeon_ctx_decref(ctx);
-	}
-	radeon_ctx_clear(ctx);
 	return ctx;
 }
 
@@ -102,33 +97,31 @@ struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx)
 
 struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
 {
+	unsigned i;
+
 	if (ctx == NULL)
 		return NULL;
 	if (--ctx->refcount > 0) {
 		return NULL;
 	}
 
+	for (i = 0; i < ctx->ndraw; i++) {
+		ctx->draw[i] = radeon_draw_decref(ctx->draw[i]);
+	}
+	for (i = 0; i < ctx->nbo; i++) {
+		ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
+	}
 	ctx->radeon = radeon_decref(ctx->radeon);
+	free(ctx->state);
+	free(ctx->draw);
 	free(ctx->bo);
 	free(ctx->pm4);
 	free(ctx->reloc);
-	free(ctx->state_crc32);
 	memset(ctx, 0, sizeof(*ctx));
 	free(ctx);
 	return NULL;
 }
 
-static int radeon_ctx_bo_id(struct radeon_ctx *ctx, struct radeon_bo *bo)
-{
-	unsigned i;
-
-	for (i = 0; i < ctx->nbo; i++) {
-		if (bo == ctx->bo[i].bo)
-			return i;
-	}
-	return -1;
-}
-
 static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
 {
 	unsigned i, j;
@@ -138,15 +131,12 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
 		return 0;
 	for (i = 0; i < state->nbo; i++) {
 		for (j = 0; j < ctx->nbo; j++) {
-			if (state->bo[i] == ctx->bo[j].bo)
+			if (state->bo[i] == ctx->bo[j])
 				break;
 		}
 		if (j == ctx->nbo) {
-			if (ctx->nbo >= ctx->max_bo) {
-				return -EBUSY;
-			}
 			radeon_bo_incref(ctx->radeon, state->bo[i]);
-			r = radeon_ctx_set_bo_new(ctx, state->bo[i], state->id);
+			r = radeon_ctx_set_bo_new(ctx, state->bo[i]);
 			if (r)
 				return r;
 		}
@@ -154,6 +144,7 @@ static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *stat
 	return 0;
 }
 
+
 int radeon_ctx_submit(struct radeon_ctx *ctx)
 {
 	struct drm_radeon_cs drmib;
@@ -161,17 +152,17 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
 	uint64_t chunk_array[2];
 	int r = 0;
 
-	if (!ctx->id)
+	if (!ctx->cpm4)
 		return 0;
 #if 0
-	for (r = 0; r < ctx->id; r++) {
+	for (r = 0; r < ctx->cpm4; r++) {
 		fprintf(stderr, "0x%08X\n", ctx->pm4[r]);
 	}
 #endif
 	drmib.num_chunks = 2;
 	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
 	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
-	chunks[0].length_dw = ctx->id;
+	chunks[0].length_dw = ctx->cpm4;
 	chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
 	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
 	chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
@@ -185,10 +176,11 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
 	return r;
 }
 
-int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
+static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			unsigned id, unsigned *placement)
 {
 	unsigned i;
+	struct radeon_cs_reloc *ptr;
 
 	for (i = 0; i < ctx->nreloc; i++) {
 		if (ctx->reloc[i].handle == bo->handle) {
@@ -196,13 +188,14 @@ int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			return 0;
 		}
 	}
-	if (ctx->nreloc >= ctx->max_reloc) {
-		return -EBUSY;
-	}
-	ctx->reloc[ctx->nreloc].handle = bo->handle;
-	ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1];
-	ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1];
-	ctx->reloc[ctx->nreloc].flags = 0;
+	ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1));
+	if (ptr == NULL)
+		return -ENOMEM;
+	ctx->reloc = ptr;
+	ptr[ctx->nreloc].handle = bo->handle;
+	ptr[ctx->nreloc].read_domain = placement[0] | placement [1];
+	ptr[ctx->nreloc].write_domain = placement[0] | placement [1];
+	ptr[ctx->nreloc].flags = 0;
 	ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
 	ctx->nreloc++;
 	return 0;
@@ -210,90 +203,75 @@ int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 
 static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state)
 {
-	unsigned i, rid, cid;
-	u32 flags;
-	int r, bo_id[4];
+	unsigned i, rid, bid, cid;
+	int r;
 
 	if (state == NULL)
 		return 0;
-	for (i = 0; i < state->nbo; i++) {
-		bo_id[i] = radeon_ctx_bo_id(ctx, state->bo[i]);
-		if (bo_id[i] < 0) {
-			return -EINVAL;
-		}
-		flags = (~ctx->bo[bo_id[i]].bo_flushed) & ctx->radeon->type[state->id].flush_flags;
-		if (flags) {
-			r = ctx->radeon->bo_flush(ctx, state->bo[i], flags, &state->placement[i * 2]);
-			if (r) {
-				return r;
-			}
-		}
-		ctx->bo[bo_id[i]].bo_flushed |= ctx->radeon->type[state->id].flush_flags;
-	}
-	if ((ctx->radeon->type[state->id].header_cpm4 + state->cpm4) > ctx->npm4) {
-		/* need to flush */
-		return -EBUSY;
-	}
-	memcpy(&ctx->pm4[ctx->id], ctx->radeon->type[state->id].header_pm4, ctx->radeon->type[state->id].header_cpm4 * 4);
-	ctx->id += ctx->radeon->type[state->id].header_cpm4;
-	ctx->npm4 -= ctx->radeon->type[state->id].header_cpm4;
-	memcpy(&ctx->pm4[ctx->id], state->states, state->cpm4 * 4);
-	for (i = 0; i < state->nbo; i++) {
+	memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4);
+	for (i = 0; i < state->nreloc; i++) {
 		rid = state->reloc_pm4_id[i];
+		bid = state->reloc_bo_id[i];
 		cid = ctx->id + rid;
-		r = radeon_ctx_reloc(ctx, state->bo[i], cid,
-					&state->placement[i * 2]);
+		r = radeon_ctx_reloc(ctx, state->bo[bid], cid,
+					&state->placement[bid * 2]);
 		if (r) {
-			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->id);
+			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type);
 			return r;
 		}
 	}
 	ctx->id += state->cpm4;
-	ctx->npm4 -= state->cpm4;
-	for (i = 0; i < state->nbo; i++) {
-		ctx->bo[bo_id[i]].bo_flushed &= ~ctx->radeon->type[state->id].dirty_flags;
-	}
 	return 0;
 }
 
 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
 {
-	unsigned ndw = 0;
+	void *tmp;
 	int r = 0;
 
+	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
+	if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
+		return -EINVAL;
+	}
 	r = radeon_state_pm4(state);
 	if (r)
 		return r;
-
-	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
-	ndw = state->cpm4 + ctx->radeon->type[state->id].header_cpm4;
-	switch (state->id) {
-	case R600_QUERY_BEGIN:
-		/* account QUERY_END at same time of QUERY_BEGIN so we know we
-		 * have room left for QUERY_END
-		 */
-		if ((ndw * 2) > ctx->npm4) {
-			/* need to flush */
-			return -EBUSY;
-		}
-		ctx->npm4 -= ndw;
-		break;
-	case R600_QUERY_END:
-		/* add again ndw from previous accounting */
-		ctx->npm4 += ndw;
-		break;
-	default:
+	if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
+		/* need to flush */
+		return -EBUSY;
+	}
+	if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
+		fprintf(stderr, "%s single state too big %d, max %d\n",
+			__func__, state->cpm4, RADEON_CTX_MAX_PM4);
 		return -EINVAL;
 	}
-
-	return radeon_ctx_state_schedule(ctx, state);
+	tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
+	if (tmp == NULL)
+		return -ENOMEM;
+	ctx->state = tmp;
+	ctx->state[ctx->nstate++] = radeon_state_incref(state);
+	/* BEGIN/END query are balanced in the same cs so account for END
+	 * END query when scheduling BEGIN query
+	 */
+	if (state->type == R600_QUERY_BEGIN_TYPE) {
+		ctx->draw_cpm4 += state->cpm4 * 2;
+	}
+	return 0;
 }
 
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
+int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
 {
-	unsigned i, previous_id;
+	struct radeon_draw *pdraw = NULL;
+	struct radeon_draw **ndraw;
+	struct radeon_state *nstate, *ostate;
+	unsigned cpm4, i, cstate;
+	void *tmp;
 	int r = 0;
 
+	ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1));
+	if (ndraw == NULL)
+		return -ENOMEM;
+	ctx->draw = ndraw;
 	for (i = 0; i < draw->nstate; i++) {
 		r = radeon_ctx_state_bo(ctx, draw->state[i]);
 		if (r)
@@ -307,17 +285,76 @@ int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
 			__func__, draw->cpm4, RADEON_CTX_MAX_PM4);
 		return -EINVAL;
 	}
-	previous_id = ctx->id;
-	for (i = 0; i < draw->nstate; i++) {
-		/* FIXME always force draw state to schedule */
-		if (draw->state[i] && draw->state[i]->pm4_crc != ctx->state_crc32[draw->state[i]->id]) {
-			r = radeon_ctx_state_schedule(ctx, draw->state[i]);
-			if (r) {
-				ctx->id = previous_id;
-				return r;
+	tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*));
+	if (tmp == NULL)
+		return -ENOMEM;
+	ctx->state = tmp;
+	pdraw = ctx->cdraw;
+	for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) {
+		nstate = draw->state[i];
+		if (nstate) {
+			if (pdraw && pdraw->state[i]) {
+				ostate = pdraw->state[i];
+				if (ostate->pm4_crc != nstate->pm4_crc) {
+					ctx->state[cstate++] = nstate;
+					cpm4 += nstate->cpm4;
+				}
+			} else {
+				ctx->state[cstate++] = nstate;
+				cpm4 += nstate->cpm4;
 			}
 		}
 	}
+	/* The last state is the draw state always add it */
+	if (draw->state[i] == NULL) {
+		fprintf(stderr, "%s no draw command\n", __func__);
+		return -EINVAL;
+	}
+	ctx->state[cstate++] = draw->state[i];
+	cpm4 += draw->state[i]->cpm4;
+	if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) {
+		/* need to flush */
+		return -EBUSY;
+	}
+	ctx->draw_cpm4 += cpm4;
+	ctx->nstate = cstate;
+	ctx->draw[ctx->ndraw++] = draw;
+	ctx->cdraw = draw;
+	return 0;
+}
+
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
+{
+	int r;
+
+	radeon_draw_incref(draw);
+	r = radeon_ctx_set_draw_new(ctx, draw);
+	if (r)
+		radeon_draw_decref(draw);
+	return r;
+}
+
+int radeon_ctx_pm4(struct radeon_ctx *ctx)
+{
+	unsigned i;
+	int r;
+
+	free(ctx->pm4);
+	ctx->cpm4 = 0;
+	ctx->pm4 = malloc(ctx->draw_cpm4 * 4);
+	if (ctx->pm4 == NULL)
+		return -EINVAL;
+	for (i = 0, ctx->id = 0; i < ctx->nstate; i++) {
+		r = radeon_ctx_state_schedule(ctx, ctx->state[i]);
+		if (r)
+			return r;
+	}
+	if (ctx->id != ctx->draw_cpm4) {
+		fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
+			__func__, ctx->draw_cpm4, ctx->id);
+		return -EINVAL;
+	}
+	ctx->cpm4 = ctx->draw_cpm4;
 	return 0;
 }
 
@@ -347,8 +384,8 @@ printf("%d relocs\n", ctx->nreloc);
 	bof_decref(blob);
 	blob = NULL;
 	/* dump cs */
-printf("%d pm4\n", ctx->id);
-	blob = bof_blob(ctx->id * 4, ctx->pm4);
+printf("%d pm4\n", ctx->cpm4);
+	blob = bof_blob(ctx->cpm4 * 4, ctx->pm4);
 	if (blob == NULL)
 		goto out_err;
 	if (bof_object_set(root, "pm4", blob))
@@ -363,23 +400,23 @@ printf("%d pm4\n", ctx->id);
 		bo = bof_object();
 		if (bo == NULL)
 			goto out_err;
-		size = bof_int32(ctx->bo[i].bo->size);
+		size = bof_int32(ctx->bo[i]->size);
 		if (size == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "size", size))
 			goto out_err;
 		bof_decref(size);
 		size = NULL;
-		handle = bof_int32(ctx->bo[i].bo->handle);
+		handle = bof_int32(ctx->bo[i]->handle);
 		if (handle == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "handle", handle))
 			goto out_err;
 		bof_decref(handle);
 		handle = NULL;
-		radeon_bo_map(ctx->radeon, ctx->bo[i].bo);
-		blob = bof_blob(ctx->bo[i].bo->size, ctx->bo[i].bo->data);
-		radeon_bo_unmap(ctx->radeon, ctx->bo[i].bo);
+		radeon_bo_map(ctx->radeon, ctx->bo[i]);
+		blob = bof_blob(ctx->bo[i]->size, ctx->bo[i]->data);
+		radeon_bo_unmap(ctx->radeon, ctx->bo[i]);
 		if (blob == NULL)
 			goto out_err;
 		if (bof_object_set(bo, "data", blob))
diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c
index 1b4e557f28..4413ed79fb 100644
--- a/src/gallium/winsys/r600/drm/radeon_draw.c
+++ b/src/gallium/winsys/r600/drm/radeon_draw.c
@@ -76,6 +76,8 @@ int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
 {
 	if (state == NULL)
 		return 0;
+	if (state->type >= draw->radeon->ntype)
+		return -EINVAL;
 	draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
 	draw->state[state->id] = state;
 	return 0;
@@ -100,7 +102,6 @@ int radeon_draw_check(struct radeon_draw *draw)
 	for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
 		if (draw->state[i]) {
 			draw->cpm4 += draw->state[i]->cpm4;
-			draw->cpm4 += draw->radeon->type[draw->state[i]->id].header_cpm4;
 		}
 	}
 	return 0;
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 469a5dce01..96c0d060f7 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -30,26 +30,34 @@ struct radeon_ctx;
  * radeon functions
  */
 typedef int (*radeon_state_pm4_t)(struct radeon_state *state);
+struct radeon_register {
+	unsigned			offset;
+	unsigned			need_reloc;
+	unsigned			bo_id;
+	char				name[64];
+};
 
 struct radeon_type {
-	const u32			*header_pm4;
-	const u32			header_cpm4;
-	const u32			*state_pm4;
-	const u32			state_cpm4;
-	const u32			flush_flags;
-	const u32			dirty_flags;
+	unsigned			npm4;
+	unsigned			id;
+	unsigned			range_start;
+	unsigned			range_end;
+	unsigned			stride;
+	unsigned			immediate;
+	char				name[64];
+	unsigned			nstates;
+	radeon_state_pm4_t		pm4;
+	const struct radeon_register	*regs;
 };
 
-typedef int (*radeon_ctx_bo_flush_t)(struct radeon_ctx *ctx, struct radeon_bo *bo, u32 flags, u32 *placement);
-
 struct radeon {
 	int				fd;
 	int				refcount;
 	unsigned			device;
 	unsigned			family;
 	unsigned			nstate;
+	unsigned			ntype;
 	const struct radeon_type	*type;
-	radeon_ctx_bo_flush_t		bo_flush;
 };
 
 extern struct radeon *radeon_new(int fd, unsigned device);
@@ -60,9 +68,12 @@ extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
 extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
 extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
 
+
+int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
+struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
+void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
+int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
 int radeon_ctx_draw(struct radeon_ctx *ctx);
-int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
-			unsigned id, unsigned *placement);
 
 /*
  * r600/r700 context functions
@@ -79,6 +90,7 @@ extern int radeon_state_register_set(struct radeon_state *state, unsigned offset
 extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state);
 extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate);
 extern int radeon_state_pm4_generic(struct radeon_state *state);
+extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id);
 
 /*
  * radeon draw functions
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index c60b12ef67..308288557a 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -32,29 +32,52 @@
 /*
  * state core functions
  */
-struct radeon_state *radeon_state(struct radeon *radeon, u32 id)
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
 {
 	struct radeon_state *state;
 
+	if (type > radeon->ntype) {
+		fprintf(stderr, "%s invalid type %d\n", __func__, type);
+		return NULL;
+	}
+	if (id > radeon->nstate) {
+		fprintf(stderr, "%s invalid state id %d\n", __func__, id);
+		return NULL;
+	}
 	state = calloc(1, sizeof(*state));
 	if (state == NULL)
 		return NULL;
 	state->radeon = radeon;
+	state->type = type;
 	state->id = id;
 	state->refcount = 1;
-	state->cpm4 = radeon->type[id].state_cpm4;
-	memcpy(state->states, radeon->type[id].state_pm4, radeon->type[id].state_cpm4 * 4);
+	state->npm4 = radeon->type[type].npm4;
+	state->nstates = radeon->type[type].nstates;
+	state->states = calloc(1, state->nstates * 4);
+	state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
+	if (state->states == NULL || state->pm4 == NULL) {
+		radeon_state_decref(state);
+		return NULL;
+	}
 	return state;
 }
 
 struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
 {
-	struct radeon_state *nstate = radeon_state(state->radeon, state->id);
+	struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
 	unsigned i;
 
 	if (state == NULL)
 		return NULL;
-	*nstate = *state;
+	nstate->cpm4 = state->cpm4;
+	nstate->nbo = state->nbo;
+	nstate->nreloc = state->nreloc;
+	memcpy(nstate->states, state->states, state->nstates * 4);
+	memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
+	memcpy(nstate->placement, state->placement, 8 * 4);
+	memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
+	memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
+	memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
 	for (i = 0; i < state->nbo; i++) {
 		nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]);
 	}
@@ -79,6 +102,9 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
 	for (i = 0; i < state->nbo; i++) {
 		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
 	}
+	free(state->immd);
+	free(state->states);
+	free(state->pm4);
 	memset(state, 0, sizeof(*state));
 	free(state);
 	return NULL;
@@ -119,8 +145,24 @@ static u32 crc32(void *d, size_t len)
 
 int radeon_state_pm4(struct radeon_state *state)
 {
-	if (state == NULL)
+	int r;
+
+	if (state == NULL || state->cpm4)
 		return 0;
-	state->pm4_crc = crc32(state->states, state->cpm4 * 4);
+	r = state->radeon->type[state->type].pm4(state);
+	if (r) {
+		fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
+			__func__, state->type, state->id);
+		return r;
+	}
+	state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
+	return 0;
+}
+
+int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id)
+{
+	state->reloc_pm4_id[state->nreloc] = id;
+	state->reloc_bo_id[state->nreloc] = bo_id;
+	state->nreloc++;
 	return 0;
 }
-- 
cgit v1.2.3


From 677623a6c80c96dc6b2c8f49fbb8bddff1054a77 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Fri, 27 Aug 2010 00:04:50 -0700
Subject: r300g: Include missing header in r300_texture.h.

Include p_compiler.h for uint32_t and boolean symbols.
---
 src/gallium/drivers/r300/r300_texture.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_texture.h b/src/gallium/drivers/r300/r300_texture.h
index a4524320fd..5a371a54a8 100644
--- a/src/gallium/drivers/r300/r300_texture.h
+++ b/src/gallium/drivers/r300/r300_texture.h
@@ -23,6 +23,7 @@
 #ifndef R300_TEXTURE_H
 #define R300_TEXTURE_H
 
+#include "pipe/p_compiler.h"
 #include "pipe/p_format.h"
 
 struct pipe_screen;
-- 
cgit v1.2.3


From 0be0ad5d58806bc12ec2c7bb3c00e7f8c7a6d6c4 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Sun, 22 Aug 2010 10:57:12 +0100
Subject: llvmpipe: intrinsics version of triangle coeficient calculation

Looks nice, but makes almost no impact on performance - maybe
a percent or so in isosurf, nothing elsewhere.  May be of use
later on.
---
 src/gallium/drivers/llvmpipe/SConscript            |   2 +
 src/gallium/drivers/llvmpipe/lp_setup_coef.c       | 258 +++++++++++++++
 src/gallium/drivers/llvmpipe/lp_setup_coef.h       |  61 ++++
 .../drivers/llvmpipe/lp_setup_coef_intrin.c        | 208 ++++++++++++
 src/gallium/drivers/llvmpipe/lp_setup_tri.c        | 348 +++------------------
 5 files changed, 577 insertions(+), 300 deletions(-)
 create mode 100644 src/gallium/drivers/llvmpipe/lp_setup_coef.c
 create mode 100644 src/gallium/drivers/llvmpipe/lp_setup_coef.h
 create mode 100644 src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/SConscript b/src/gallium/drivers/llvmpipe/SConscript
index 5583fca38e..8d57db72cf 100644
--- a/src/gallium/drivers/llvmpipe/SConscript
+++ b/src/gallium/drivers/llvmpipe/SConscript
@@ -63,6 +63,8 @@ llvmpipe = env.ConvenienceLibrary(
 		'lp_setup_line.c',
 		'lp_setup_point.c',
 		'lp_setup_tri.c',
+		'lp_setup_coef.c',
+		'lp_setup_coef_intrin.c',
 		'lp_setup_vbuf.c',
 		'lp_state_blend.c',
 		'lp_state_clip.c',
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_coef.c b/src/gallium/drivers/llvmpipe/lp_setup_coef.c
new file mode 100644
index 0000000000..95e3e8fffe
--- /dev/null
+++ b/src/gallium/drivers/llvmpipe/lp_setup_coef.c
@@ -0,0 +1,258 @@
+/**************************************************************************
+ *
+ * Copyright 2010, VMware.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/*
+ * Binning code for triangles
+ */
+
+#include "util/u_math.h"
+#include "util/u_memory.h"
+#include "lp_perf.h"
+#include "lp_setup_context.h"
+#include "lp_setup_coef.h"
+#include "lp_rast.h"
+#include "lp_state_fs.h"
+
+#if !defined(PIPE_ARCH_SSE)
+
+/**
+ * Compute a0 for a constant-valued coefficient (GL_FLAT shading).
+ */
+static void constant_coef( struct lp_rast_shader_inputs *inputs,
+                           unsigned slot,
+			   const float value,
+                           unsigned i )
+{
+   inputs->a0[slot][i] = value;
+   inputs->dadx[slot][i] = 0.0f;
+   inputs->dady[slot][i] = 0.0f;
+}
+
+
+
+static void linear_coef( struct lp_rast_shader_inputs *inputs,
+                         const struct lp_tri_info *info,
+                         unsigned slot,
+                         unsigned vert_attr,
+                         unsigned i)
+{
+   float a0 = info->v0[vert_attr][i];
+   float a1 = info->v1[vert_attr][i];
+   float a2 = info->v2[vert_attr][i];
+
+   float da01 = a0 - a1;
+   float da20 = a2 - a0;
+   float dadx = (da01 * info->dy20_ooa - info->dy01_ooa * da20);
+   float dady = (da20 * info->dx01_ooa - info->dx20_ooa * da01);
+
+   inputs->dadx[slot][i] = dadx;
+   inputs->dady[slot][i] = dady;
+
+   /* calculate a0 as the value which would be sampled for the
+    * fragment at (0,0), taking into account that we want to sample at
+    * pixel centers, in other words (0.5, 0.5).
+    *
+    * this is neat but unfortunately not a good way to do things for
+    * triangles with very large values of dadx or dady as it will
+    * result in the subtraction and re-addition from a0 of a very
+    * large number, which means we'll end up loosing a lot of the
+    * fractional bits and precision from a0.  the way to fix this is
+    * to define a0 as the sample at a pixel center somewhere near vmin
+    * instead - i'll switch to this later.
+    */
+   inputs->a0[slot][i] = a0 - (dadx * info->x0_center +
+				   dady * info->y0_center);
+}
+
+
+/**
+ * Compute a0, dadx and dady for a perspective-corrected interpolant,
+ * for a triangle.
+ * We basically multiply the vertex value by 1/w before computing
+ * the plane coefficients (a0, dadx, dady).
+ * Later, when we compute the value at a particular fragment position we'll
+ * divide the interpolated value by the interpolated W at that fragment.
+ */
+static void perspective_coef( struct lp_rast_shader_inputs *inputs,
+                              const struct lp_tri_info *info,
+                              unsigned slot,
+			      unsigned vert_attr,
+                              unsigned i)
+{
+   /* premultiply by 1/w  (v[0][3] is always 1/w):
+    */
+   float a0 = info->v0[vert_attr][i] * info->v0[0][3];
+   float a1 = info->v1[vert_attr][i] * info->v1[0][3];
+   float a2 = info->v2[vert_attr][i] * info->v2[0][3];
+   float da01 = a0 - a1;
+   float da20 = a2 - a0;
+   float dadx = da01 * info->dy20_ooa - info->dy01_ooa * da20;
+   float dady = da20 * info->dx01_ooa - info->dx20_ooa * da01;
+
+   inputs->dadx[slot][i] = dadx;
+   inputs->dady[slot][i] = dady;
+   inputs->a0[slot][i] = a0 - (dadx * info->x0_center +
+				   dady * info->y0_center);
+}
+
+
+/**
+ * Special coefficient setup for gl_FragCoord.
+ * X and Y are trivial
+ * Z and W are copied from position_coef which should have already been computed.
+ * We could do a bit less work if we'd examine gl_FragCoord's swizzle mask.
+ */
+static void
+setup_fragcoord_coef(struct lp_rast_shader_inputs *inputs,
+                     const struct lp_tri_info *info,
+                     unsigned slot,
+                     unsigned usage_mask)
+{
+   /*X*/
+   if (usage_mask & TGSI_WRITEMASK_X) {
+      inputs->a0[slot][0] = 0.0;
+      inputs->dadx[slot][0] = 1.0;
+      inputs->dady[slot][0] = 0.0;
+   }
+
+   /*Y*/
+   if (usage_mask & TGSI_WRITEMASK_Y) {
+      inputs->a0[slot][1] = 0.0;
+      inputs->dadx[slot][1] = 0.0;
+      inputs->dady[slot][1] = 1.0;
+   }
+
+   /*Z*/
+   if (usage_mask & TGSI_WRITEMASK_Z) {
+      linear_coef(inputs, info, slot, 0, 2);
+   }
+
+   /*W*/
+   if (usage_mask & TGSI_WRITEMASK_W) {
+      linear_coef(inputs, info, slot, 0, 3);
+   }
+}
+
+
+/**
+ * Setup the fragment input attribute with the front-facing value.
+ * \param frontface  is the triangle front facing?
+ */
+static void setup_facing_coef( struct lp_rast_shader_inputs *inputs,
+                               unsigned slot,
+                               boolean frontface,
+                               unsigned usage_mask)
+{
+   /* convert TRUE to 1.0 and FALSE to -1.0 */
+   if (usage_mask & TGSI_WRITEMASK_X)
+      constant_coef( inputs, slot, 2.0f * frontface - 1.0f, 0 );
+
+   if (usage_mask & TGSI_WRITEMASK_Y)
+      constant_coef( inputs, slot, 0.0f, 1 ); /* wasted */
+
+   if (usage_mask & TGSI_WRITEMASK_Z)
+      constant_coef( inputs, slot, 0.0f, 2 ); /* wasted */
+
+   if (usage_mask & TGSI_WRITEMASK_W)
+      constant_coef( inputs, slot, 0.0f, 3 ); /* wasted */
+}
+
+
+/**
+ * Compute the tri->coef[] array dadx, dady, a0 values.
+ */
+void lp_setup_tri_coef( struct lp_setup_context *setup,
+			struct lp_rast_shader_inputs *inputs,
+			const struct lp_tri_info *info)
+{
+   unsigned fragcoord_usage_mask = TGSI_WRITEMASK_XYZ;
+   unsigned slot;
+   unsigned i;
+
+   /* setup interpolation for all the remaining attributes:
+    */
+   for (slot = 0; slot < setup->fs.nr_inputs; slot++) {
+      unsigned vert_attr = setup->fs.input[slot].src_index;
+      unsigned usage_mask = setup->fs.input[slot].usage_mask;
+
+      switch (setup->fs.input[slot].interp) {
+      case LP_INTERP_CONSTANT:
+         if (setup->flatshade_first) {
+            for (i = 0; i < NUM_CHANNELS; i++)
+               if (usage_mask & (1 << i))
+                  constant_coef(inputs, slot+1, info->v0[vert_attr][i], i);
+         }
+         else {
+            for (i = 0; i < NUM_CHANNELS; i++)
+               if (usage_mask & (1 << i))
+                  constant_coef(inputs, slot+1, info->v2[vert_attr][i], i);
+         }
+         break;
+
+      case LP_INTERP_LINEAR:
+         for (i = 0; i < NUM_CHANNELS; i++)
+            if (usage_mask & (1 << i))
+               linear_coef(inputs, info, slot+1, vert_attr, i);
+         break;
+
+      case LP_INTERP_PERSPECTIVE:
+         for (i = 0; i < NUM_CHANNELS; i++)
+            if (usage_mask & (1 << i))
+               perspective_coef(inputs, info, slot+1, vert_attr, i);
+         fragcoord_usage_mask |= TGSI_WRITEMASK_W;
+         break;
+
+      case LP_INTERP_POSITION:
+         /*
+          * The generated pixel interpolators will pick up the coeffs from
+          * slot 0, so all need to ensure that the usage mask is covers all
+          * usages.
+          */
+         fragcoord_usage_mask |= usage_mask;
+         break;
+
+      case LP_INTERP_FACING:
+         setup_facing_coef(inputs, slot+1, info->frontfacing, usage_mask);
+         break;
+
+      default:
+         assert(0);
+      }
+   }
+
+   /* The internal position input is in slot zero:
+    */
+   setup_fragcoord_coef(inputs, info, 0, fragcoord_usage_mask);
+}
+
+#else
+extern void lp_setup_coef_dummy(void);
+void lp_setup_coef_dummy(void)
+{
+}
+
+#endif
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_coef.h b/src/gallium/drivers/llvmpipe/lp_setup_coef.h
new file mode 100644
index 0000000000..d68b39c603
--- /dev/null
+++ b/src/gallium/drivers/llvmpipe/lp_setup_coef.h
@@ -0,0 +1,61 @@
+/**************************************************************************
+ *
+ * Copyright 2010 VMware, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+
+/**
+ * The setup code is concerned with point/line/triangle setup and
+ * putting commands/data into the bins.
+ */
+
+
+#ifndef LP_SETUP_COEF_H
+#define LP_SETUP_COEF_H
+
+
+struct lp_tri_info {
+
+   float x0_center;
+   float y0_center;
+
+   /* turn these into an aligned float[4] */
+   float dy01_ooa;
+   float dy20_ooa;
+   float dx01_ooa;
+   float dx20_ooa;
+
+   const float (*v0)[4];
+   const float (*v1)[4];
+   const float (*v2)[4];
+
+   boolean frontfacing;		/* remove eventually */
+};
+
+void lp_setup_tri_coef( struct lp_setup_context *setup,
+			struct lp_rast_shader_inputs *inputs,
+			const struct lp_tri_info *info);
+
+#endif
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c b/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c
new file mode 100644
index 0000000000..b477bc2113
--- /dev/null
+++ b/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c
@@ -0,0 +1,208 @@
+/**************************************************************************
+ *
+ * Copyright 2010 VMware.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+/*
+ * Binning code for triangles
+ */
+
+#include "util/u_math.h"
+#include "util/u_memory.h"
+#include "lp_perf.h"
+#include "lp_setup_context.h"
+#include "lp_setup_coef.h"
+#include "lp_rast.h"
+#include "lp_state_fs.h"
+
+#if defined(PIPE_ARCH_SSE)
+#include <emmintrin.h>
+
+
+static void constant_coef4( struct lp_rast_shader_inputs *inputs,
+			    const struct lp_tri_info *info,
+			    unsigned slot,
+			    const float *attr)
+{
+   *(__m128 *)inputs->a0[slot]   = *(__m128 *)attr;
+   *(__m128 *)inputs->dadx[slot] = _mm_set1_ps(0.0);
+   *(__m128 *)inputs->dady[slot] = _mm_set1_ps(0.0);
+}
+
+
+
+/**
+ * Setup the fragment input attribute with the front-facing value.
+ * \param frontface  is the triangle front facing?
+ */
+static void setup_facing_coef( struct lp_rast_shader_inputs *inputs,
+			       const struct lp_tri_info *info,
+			       unsigned slot )
+{
+   /* XXX: just pass frontface directly to the shader, don't bother
+    * treating it as an input.
+    */
+   __m128 a0 = _mm_setr_ps(info->frontfacing ? 1.0 : -1.0,
+			   0, 0, 0);
+
+   *(__m128 *)inputs->a0[slot]   = a0;
+   *(__m128 *)inputs->dadx[slot] = _mm_set1_ps(0.0);
+   *(__m128 *)inputs->dady[slot] = _mm_set1_ps(0.0);
+}
+
+
+
+static void calc_coef4( struct lp_rast_shader_inputs *inputs,
+			const struct lp_tri_info *info,
+			unsigned slot,
+			__m128 a0,
+			__m128 a1,
+			__m128 a2)
+{
+   __m128 da01          = _mm_sub_ps(a0, a1);
+   __m128 da20          = _mm_sub_ps(a2, a0);
+
+   __m128 da01_dy20_ooa = _mm_mul_ps(da01, _mm_set1_ps(info->dy20_ooa));
+   __m128 da20_dy01_ooa = _mm_mul_ps(da20, _mm_set1_ps(info->dy01_ooa));   
+   __m128 dadx          = _mm_sub_ps(da01_dy20_ooa, da20_dy01_ooa);
+
+   __m128 da01_dx20_ooa = _mm_mul_ps(da01, _mm_set1_ps(info->dx20_ooa));
+   __m128 da20_dx01_ooa = _mm_mul_ps(da20, _mm_set1_ps(info->dx01_ooa));
+   __m128 dady          = _mm_sub_ps(da20_dx01_ooa, da01_dx20_ooa);
+
+   __m128 dadx_x0       = _mm_mul_ps(dadx, _mm_set1_ps(info->x0_center));
+   __m128 dady_y0       = _mm_mul_ps(dady, _mm_set1_ps(info->y0_center));
+   __m128 attr_v0       = _mm_add_ps(dadx_x0, dady_y0);
+   __m128 attr_0        = _mm_sub_ps(a0, attr_v0);
+
+   *(__m128 *)inputs->a0[slot]   = attr_0;
+   *(__m128 *)inputs->dadx[slot] = dadx;
+   *(__m128 *)inputs->dady[slot] = dady;
+}
+
+
+static void linear_coef( struct lp_rast_shader_inputs *inputs,
+                         const struct lp_tri_info *info,
+                         unsigned slot,
+                         unsigned vert_attr)
+{
+   __m128 a0 = *(const __m128 *)info->v0[vert_attr];
+   __m128 a1 = *(const __m128 *)info->v1[vert_attr];
+   __m128 a2 = *(const __m128 *)info->v2[vert_attr];
+
+   calc_coef4(inputs, info, slot, a0, a1, a2);
+}
+
+
+
+/**
+ * Compute a0, dadx and dady for a perspective-corrected interpolant,
+ * for a triangle.
+ * We basically multiply the vertex value by 1/w before computing
+ * the plane coefficients (a0, dadx, dady).
+ * Later, when we compute the value at a particular fragment position we'll
+ * divide the interpolated value by the interpolated W at that fragment.
+ */
+static void perspective_coef( struct lp_rast_shader_inputs *inputs,
+                              const struct lp_tri_info *info,
+                              unsigned slot,
+			      unsigned vert_attr)
+{
+   /* premultiply by 1/w  (v[0][3] is always 1/w):
+    */
+   __m128 a0 = *(const __m128 *)info->v0[vert_attr];
+   __m128 a1 = *(const __m128 *)info->v1[vert_attr];
+   __m128 a2 = *(const __m128 *)info->v2[vert_attr];
+
+   __m128 a0_oow = _mm_mul_ps(a0, _mm_set1_ps(info->v0[0][3]));
+   __m128 a1_oow = _mm_mul_ps(a1, _mm_set1_ps(info->v1[0][3]));
+   __m128 a2_oow = _mm_mul_ps(a2, _mm_set1_ps(info->v2[0][3]));
+
+   calc_coef4(inputs, info, slot, a0_oow, a1_oow, a2_oow);
+}
+
+
+
+
+
+/**
+ * Compute the inputs-> dadx, dady, a0 values.
+ */
+void lp_setup_tri_coef( struct lp_setup_context *setup,
+			struct lp_rast_shader_inputs *inputs,
+			const struct lp_tri_info *info)
+{
+   unsigned slot;
+
+   /* The internal position input is in slot zero:
+    */
+   linear_coef(inputs, info, 0, 0);
+
+   /* setup interpolation for all the remaining attributes:
+    */
+   for (slot = 0; slot < setup->fs.nr_inputs; slot++) {
+      unsigned vert_attr = setup->fs.input[slot].src_index;
+
+      switch (setup->fs.input[slot].interp) {
+      case LP_INTERP_CONSTANT:
+         if (setup->flatshade_first) {
+	    constant_coef4(inputs, info, slot+1, info->v0[vert_attr]);
+         }
+         else {
+	    constant_coef4(inputs, info, slot+1, info->v2[vert_attr]);
+         }
+         break;
+
+      case LP_INTERP_LINEAR:
+	 linear_coef(inputs, info, slot+1, vert_attr);
+         break;
+
+      case LP_INTERP_PERSPECTIVE:
+	 perspective_coef(inputs, info, slot+1, vert_attr);
+         break;
+
+      case LP_INTERP_POSITION:
+         /*
+          * The generated pixel interpolators will pick up the coeffs from
+          * slot 0.
+          */
+         break;
+
+      case LP_INTERP_FACING:
+         setup_facing_coef(inputs, info, slot+1);
+         break;
+
+      default:
+         assert(0);
+      }
+   }
+}
+
+#else
+extern void lp_setup_coef_dummy(void);
+void lp_setup_coef_dummy(void)
+{
+}
+#endif
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index fe5c9358dd..d86fb8652a 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -34,33 +34,12 @@
 #include "util/u_rect.h"
 #include "lp_perf.h"
 #include "lp_setup_context.h"
+#include "lp_setup_coef.h"
 #include "lp_rast.h"
 #include "lp_state_fs.h"
 
 #define NUM_CHANNELS 4
 
-struct tri_info {
-
-   float pixel_offset;
-
-   /* fixed point vertex coordinates */
-   int x[3];
-   int y[3];
-
-   /* float x,y deltas - all from the original coordinates
-    */
-   float dy01, dy20;
-   float dx01, dx20;
-   float oneoverarea;
-
-   const float (*v0)[4];
-   const float (*v1)[4];
-   const float (*v2)[4];
-
-   boolean frontfacing;
-};
-
-
 
    
 static INLINE int
@@ -77,247 +56,6 @@ fixed_to_float(int a)
 
 
 
-/**
- * Compute a0 for a constant-valued coefficient (GL_FLAT shading).
- */
-static void constant_coef( struct lp_rast_triangle *tri,
-                           unsigned slot,
-			   const float value,
-                           unsigned i )
-{
-   tri->inputs.a0[slot][i] = value;
-   tri->inputs.dadx[slot][i] = 0.0f;
-   tri->inputs.dady[slot][i] = 0.0f;
-}
-
-
-
-static void linear_coef( struct lp_rast_triangle *tri,
-                         const struct tri_info *info,
-                         unsigned slot,
-                         unsigned vert_attr,
-                         unsigned i)
-{
-   float a0 = info->v0[vert_attr][i];
-   float a1 = info->v1[vert_attr][i];
-   float a2 = info->v2[vert_attr][i];
-
-   float da01 = a0 - a1;
-   float da20 = a2 - a0;
-   float dadx = (da01 * info->dy20 - info->dy01 * da20) * info->oneoverarea;
-   float dady = (da20 * info->dx01 - info->dx20 * da01) * info->oneoverarea;
-
-   tri->inputs.dadx[slot][i] = dadx;
-   tri->inputs.dady[slot][i] = dady;
-
-   /* calculate a0 as the value which would be sampled for the
-    * fragment at (0,0), taking into account that we want to sample at
-    * pixel centers, in other words (0.5, 0.5).
-    *
-    * this is neat but unfortunately not a good way to do things for
-    * triangles with very large values of dadx or dady as it will
-    * result in the subtraction and re-addition from a0 of a very
-    * large number, which means we'll end up loosing a lot of the
-    * fractional bits and precision from a0.  the way to fix this is
-    * to define a0 as the sample at a pixel center somewhere near vmin
-    * instead - i'll switch to this later.
-    */
-   tri->inputs.a0[slot][i] = (a0 -
-                              (dadx * (info->v0[0][0] - info->pixel_offset) +
-                               dady * (info->v0[0][1] - info->pixel_offset)));
-}
-
-
-/**
- * Compute a0, dadx and dady for a perspective-corrected interpolant,
- * for a triangle.
- * We basically multiply the vertex value by 1/w before computing
- * the plane coefficients (a0, dadx, dady).
- * Later, when we compute the value at a particular fragment position we'll
- * divide the interpolated value by the interpolated W at that fragment.
- */
-static void perspective_coef( struct lp_rast_triangle *tri,
-                              const struct tri_info *info,
-                              unsigned slot,
-			      unsigned vert_attr,
-                              unsigned i)
-{
-   /* premultiply by 1/w  (v[0][3] is always 1/w):
-    */
-   float a0 = info->v0[vert_attr][i] * info->v0[0][3];
-   float a1 = info->v1[vert_attr][i] * info->v1[0][3];
-   float a2 = info->v2[vert_attr][i] * info->v2[0][3];
-   float da01 = a0 - a1;
-   float da20 = a2 - a0;
-   float dadx = (da01 * info->dy20 - info->dy01 * da20) * info->oneoverarea;
-   float dady = (da20 * info->dx01 - info->dx20 * da01) * info->oneoverarea;
-
-   tri->inputs.dadx[slot][i] = dadx;
-   tri->inputs.dady[slot][i] = dady;
-   tri->inputs.a0[slot][i] = (a0 -
-                              (dadx * (info->v0[0][0] - info->pixel_offset) +
-                               dady * (info->v0[0][1] - info->pixel_offset)));
-}
-
-
-/**
- * Special coefficient setup for gl_FragCoord.
- * X and Y are trivial
- * Z and W are copied from position_coef which should have already been computed.
- * We could do a bit less work if we'd examine gl_FragCoord's swizzle mask.
- */
-static void
-setup_fragcoord_coef(struct lp_rast_triangle *tri,
-                     const struct tri_info *info,
-                     unsigned slot,
-                     unsigned usage_mask)
-{
-   /*X*/
-   if (usage_mask & TGSI_WRITEMASK_X) {
-      tri->inputs.a0[slot][0] = 0.0;
-      tri->inputs.dadx[slot][0] = 1.0;
-      tri->inputs.dady[slot][0] = 0.0;
-   }
-
-   /*Y*/
-   if (usage_mask & TGSI_WRITEMASK_Y) {
-      tri->inputs.a0[slot][1] = 0.0;
-      tri->inputs.dadx[slot][1] = 0.0;
-      tri->inputs.dady[slot][1] = 1.0;
-   }
-
-   /*Z*/
-   if (usage_mask & TGSI_WRITEMASK_Z) {
-      linear_coef(tri, info, slot, 0, 2);
-   }
-
-   /*W*/
-   if (usage_mask & TGSI_WRITEMASK_W) {
-      linear_coef(tri, info, slot, 0, 3);
-   }
-}
-
-
-/**
- * Setup the fragment input attribute with the front-facing value.
- * \param frontface  is the triangle front facing?
- */
-static void setup_facing_coef( struct lp_rast_triangle *tri,
-                               unsigned slot,
-                               boolean frontface,
-                               unsigned usage_mask)
-{
-   /* convert TRUE to 1.0 and FALSE to -1.0 */
-   if (usage_mask & TGSI_WRITEMASK_X)
-      constant_coef( tri, slot, 2.0f * frontface - 1.0f, 0 );
-
-   if (usage_mask & TGSI_WRITEMASK_Y)
-      constant_coef( tri, slot, 0.0f, 1 ); /* wasted */
-
-   if (usage_mask & TGSI_WRITEMASK_Z)
-      constant_coef( tri, slot, 0.0f, 2 ); /* wasted */
-
-   if (usage_mask & TGSI_WRITEMASK_W)
-      constant_coef( tri, slot, 0.0f, 3 ); /* wasted */
-}
-
-
-/**
- * Compute the tri->coef[] array dadx, dady, a0 values.
- */
-static void setup_tri_coefficients( struct lp_setup_context *setup,
-				    struct lp_rast_triangle *tri,
-                                    const struct tri_info *info)
-{
-   unsigned fragcoord_usage_mask = TGSI_WRITEMASK_XYZ;
-   unsigned slot;
-   unsigned i;
-
-   /* setup interpolation for all the remaining attributes:
-    */
-   for (slot = 0; slot < setup->fs.nr_inputs; slot++) {
-      unsigned vert_attr = setup->fs.input[slot].src_index;
-      unsigned usage_mask = setup->fs.input[slot].usage_mask;
-
-      switch (setup->fs.input[slot].interp) {
-      case LP_INTERP_CONSTANT:
-         if (setup->flatshade_first) {
-            for (i = 0; i < NUM_CHANNELS; i++)
-               if (usage_mask & (1 << i))
-                  constant_coef(tri, slot+1, info->v0[vert_attr][i], i);
-         }
-         else {
-            for (i = 0; i < NUM_CHANNELS; i++)
-               if (usage_mask & (1 << i))
-                  constant_coef(tri, slot+1, info->v2[vert_attr][i], i);
-         }
-         break;
-
-      case LP_INTERP_LINEAR:
-         for (i = 0; i < NUM_CHANNELS; i++)
-            if (usage_mask & (1 << i))
-               linear_coef(tri, info, slot+1, vert_attr, i);
-         break;
-
-      case LP_INTERP_PERSPECTIVE:
-         for (i = 0; i < NUM_CHANNELS; i++)
-            if (usage_mask & (1 << i))
-               perspective_coef(tri, info, slot+1, vert_attr, i);
-         fragcoord_usage_mask |= TGSI_WRITEMASK_W;
-         break;
-
-      case LP_INTERP_POSITION:
-         /*
-          * The generated pixel interpolators will pick up the coeffs from
-          * slot 0, so all need to ensure that the usage mask is covers all
-          * usages.
-          */
-         fragcoord_usage_mask |= usage_mask;
-         break;
-
-      case LP_INTERP_FACING:
-         setup_facing_coef(tri, slot+1, info->frontfacing, usage_mask);
-         break;
-
-      default:
-         assert(0);
-      }
-   }
-
-   /* The internal position input is in slot zero:
-    */
-   setup_fragcoord_coef(tri, info, 0, fragcoord_usage_mask);
-
-   if (0) {
-      for (i = 0; i < NUM_CHANNELS; i++) {
-         float a0   = tri->inputs.a0  [0][i];
-         float dadx = tri->inputs.dadx[0][i];
-         float dady = tri->inputs.dady[0][i];
-
-         debug_printf("POS.%c: a0 = %f, dadx = %f, dady = %f\n",
-                      "xyzw"[i],
-                      a0, dadx, dady);
-      }
-
-      for (slot = 0; slot < setup->fs.nr_inputs; slot++) {
-         unsigned usage_mask = setup->fs.input[slot].usage_mask;
-         for (i = 0; i < NUM_CHANNELS; i++) {
-            if (usage_mask & (1 << i)) {
-               float a0   = tri->inputs.a0  [1 + slot][i];
-               float dadx = tri->inputs.dadx[1 + slot][i];
-               float dady = tri->inputs.dady[1 + slot][i];
-
-               debug_printf("IN[%u].%c: a0 = %f, dadx = %f, dady = %f\n",
-                            slot,
-                            "xyzw"[i],
-                            a0, dadx, dady);
-            }
-         }
-      }
-   }
-}
-
-
 
 
 
@@ -440,16 +178,21 @@ lp_rast_cmd lp_rast_tri_tab[8] = {
  */
 static void
 do_triangle_ccw(struct lp_setup_context *setup,
+		const float (*v0)[4],
 		const float (*v1)[4],
 		const float (*v2)[4],
-		const float (*v3)[4],
 		boolean frontfacing )
 {
 
    struct lp_scene *scene = lp_setup_get_current_scene(setup);
    struct lp_fragment_shader_variant *variant = setup->fs.current.variant;
    struct lp_rast_triangle *tri;
-   struct tri_info info;
+   int x[3];
+   int y[3];
+   float dy01, dy20;
+   float dx01, dx20;
+   float oneoverarea;
+   struct lp_tri_info info;
    int area;
    struct u_rect bbox;
    int ix0, ix1, iy0, iy1;
@@ -458,7 +201,7 @@ do_triangle_ccw(struct lp_setup_context *setup,
    int nr_planes = 3;
       
    if (0)
-      lp_setup_print_triangle(setup, v1, v2, v3);
+      lp_setup_print_triangle(setup, v0, v1, v2);
 
    if (setup->scissor_test) {
       nr_planes = 7;
@@ -468,13 +211,12 @@ do_triangle_ccw(struct lp_setup_context *setup,
    }
 
    /* x/y positions in fixed point */
-   info.x[0] = subpixel_snap(v1[0][0] - setup->pixel_offset);
-   info.x[1] = subpixel_snap(v2[0][0] - setup->pixel_offset);
-   info.x[2] = subpixel_snap(v3[0][0] - setup->pixel_offset);
-   info.y[0] = subpixel_snap(v1[0][1] - setup->pixel_offset);
-   info.y[1] = subpixel_snap(v2[0][1] - setup->pixel_offset);
-   info.y[2] = subpixel_snap(v3[0][1] - setup->pixel_offset);
-
+   x[0] = subpixel_snap(v0[0][0] - setup->pixel_offset);
+   x[1] = subpixel_snap(v1[0][0] - setup->pixel_offset);
+   x[2] = subpixel_snap(v2[0][0] - setup->pixel_offset);
+   y[0] = subpixel_snap(v0[0][1] - setup->pixel_offset);
+   y[1] = subpixel_snap(v1[0][1] - setup->pixel_offset);
+   y[2] = subpixel_snap(v2[0][1] - setup->pixel_offset);
 
 
    /* Bounding rectangle (in pixels) */
@@ -486,10 +228,10 @@ do_triangle_ccw(struct lp_setup_context *setup,
        */
       int adj = (setup->pixel_offset != 0) ? 1 : 0;
 
-      bbox.x0 = (MIN3(info.x[0], info.x[1], info.x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      bbox.x1 = (MAX3(info.x[0], info.x[1], info.x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      bbox.y0 = (MIN3(info.y[0], info.y[1], info.y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
-      bbox.y1 = (MAX3(info.y[0], info.y[1], info.y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.x0 = (MIN3(x[0], x[1], x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.x1 = (MAX3(x[0], x[1], x[2]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.y0 = (MIN3(y[0], y[1], y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.y1 = (MAX3(y[0], y[1], y[2]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
 
       /* Inclusive coordinates:
        */
@@ -520,21 +262,21 @@ do_triangle_ccw(struct lp_setup_context *setup,
       return;
 
 #ifdef DEBUG
-   tri->v[0][0] = v1[0][0];
-   tri->v[1][0] = v2[0][0];
-   tri->v[2][0] = v3[0][0];
-   tri->v[0][1] = v1[0][1];
-   tri->v[1][1] = v2[0][1];
-   tri->v[2][1] = v3[0][1];
+   tri->v[0][0] = v0[0][0];
+   tri->v[1][0] = v1[0][0];
+   tri->v[2][0] = v2[0][0];
+   tri->v[0][1] = v0[0][1];
+   tri->v[1][1] = v1[0][1];
+   tri->v[2][1] = v2[0][1];
 #endif
 
-   tri->plane[0].dcdy = info.x[0] - info.x[1];
-   tri->plane[1].dcdy = info.x[1] - info.x[2];
-   tri->plane[2].dcdy = info.x[2] - info.x[0];
+   tri->plane[0].dcdy = x[0] - x[1];
+   tri->plane[1].dcdy = x[1] - x[2];
+   tri->plane[2].dcdy = x[2] - x[0];
 
-   tri->plane[0].dcdx = info.y[0] - info.y[1];
-   tri->plane[1].dcdx = info.y[1] - info.y[2];
-   tri->plane[2].dcdx = info.y[2] - info.y[0];
+   tri->plane[0].dcdx = y[0] - y[1];
+   tri->plane[1].dcdx = y[1] - y[2];
+   tri->plane[2].dcdx = y[2] - y[0];
 
    area = (tri->plane[0].dcdy * tri->plane[2].dcdx -
            tri->plane[2].dcdy * tri->plane[0].dcdx);
@@ -554,20 +296,26 @@ do_triangle_ccw(struct lp_setup_context *setup,
 
    /* 
     */
-   info.pixel_offset = setup->pixel_offset;
-   info.v0 = v1;
-   info.v1 = v2;
-   info.v2 = v3;
-   info.dx01 = info.v0[0][0] - info.v1[0][0];
-   info.dx20 = info.v2[0][0] - info.v0[0][0];
-   info.dy01 = info.v0[0][1] - info.v1[0][1];
-   info.dy20 = info.v2[0][1] - info.v0[0][1];
-   info.oneoverarea = 1.0f / (info.dx01 * info.dy20 - info.dx20 * info.dy01);
+   dx01 = v0[0][0] - v1[0][0];
+   dy01 = v0[0][1] - v1[0][1];
+   dx20 = v2[0][0] - v0[0][0];
+   dy20 = v2[0][1] - v0[0][1];
+   oneoverarea = 1.0f / (dx01 * dy20 - dx20 * dy01);
+
+   info.v0 = v0;
+   info.v1 = v1;
+   info.v2 = v2;
    info.frontfacing = frontfacing;
+   info.x0_center = v0[0][0] - setup->pixel_offset;
+   info.y0_center = v0[0][1] - setup->pixel_offset;
+   info.dx01_ooa  = dx01 * oneoverarea;
+   info.dx20_ooa  = dx20 * oneoverarea;
+   info.dy01_ooa  = dy01 * oneoverarea;
+   info.dy20_ooa  = dy20 * oneoverarea;
 
    /* Setup parameter interpolants:
     */
-   setup_tri_coefficients( setup, tri, &info );
+   lp_setup_tri_coef( setup, &tri->inputs, &info );
 
    tri->inputs.facing = frontfacing ? 1.0F : -1.0F;
    tri->inputs.state = setup->fs.stored;
@@ -580,7 +328,7 @@ do_triangle_ccw(struct lp_setup_context *setup,
       /* half-edge constants, will be interated over the whole render
        * target.
        */
-      plane->c = plane->dcdx * info.x[i] - plane->dcdy * info.y[i];
+      plane->c = plane->dcdx * x[i] - plane->dcdy * y[i];
 
       /* correct for top-left vs. bottom-left fill convention.  
        *
-- 
cgit v1.2.3


From c95ca04b63eadb61add249531c1041aaf5b525d6 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 27 Aug 2010 11:18:11 +0100
Subject: llvmpipe: add lp_setup_coef to makefile

---
 src/gallium/drivers/llvmpipe/Makefile | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/Makefile b/src/gallium/drivers/llvmpipe/Makefile
index 2892b62920..dec874623e 100644
--- a/src/gallium/drivers/llvmpipe/Makefile
+++ b/src/gallium/drivers/llvmpipe/Makefile
@@ -27,6 +27,8 @@ C_SOURCES = \
 	lp_scene_queue.c \
 	lp_screen.c \
 	lp_setup.c \
+	lp_setup_coef.c \
+	lp_setup_coef_intrin.c \
 	lp_setup_line.c \
 	lp_setup_point.c \
 	lp_setup_tri.c \
-- 
cgit v1.2.3


From 5286dd701640976ffc328e8e85fb3830746851a1 Mon Sep 17 00:00:00 2001
From: Hui Qi Tay <hqtay@vmware.com>
Date: Mon, 19 Jul 2010 15:23:09 +0100
Subject: llvmpipe: native rasterization for lines

Rasterize lines directly by treating them as 4-sided polygons.
Still need to check the exact pixel rasteration.
---
 src/gallium/drivers/llvmpipe/lp_context.c          |   2 +-
 src/gallium/drivers/llvmpipe/lp_rast.h             |   4 +-
 src/gallium/drivers/llvmpipe/lp_rast_tri.c         |   4 +
 src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h     |   2 +-
 src/gallium/drivers/llvmpipe/lp_setup.c            |   7 +
 src/gallium/drivers/llvmpipe/lp_setup.h            |   4 +
 src/gallium/drivers/llvmpipe/lp_setup_context.h    |  38 ++
 src/gallium/drivers/llvmpipe/lp_setup_line.c       | 617 ++++++++++++++++++++-
 src/gallium/drivers/llvmpipe/lp_setup_point.c      |   4 +-
 src/gallium/drivers/llvmpipe/lp_setup_tri.c        |  23 +-
 src/gallium/drivers/llvmpipe/lp_state_rasterizer.c |   2 +
 11 files changed, 685 insertions(+), 22 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_context.c b/src/gallium/drivers/llvmpipe/lp_context.c
index 086a2d5898..a6873abbee 100644
--- a/src/gallium/drivers/llvmpipe/lp_context.c
+++ b/src/gallium/drivers/llvmpipe/lp_context.c
@@ -157,7 +157,7 @@ llvmpipe_create_context( struct pipe_screen *screen, void *priv )
 
    /* convert points and lines into triangles: */
    draw_wide_point_threshold(llvmpipe->draw, 0.0);
-   draw_wide_line_threshold(llvmpipe->draw, 0.0);
+   draw_wide_line_threshold(llvmpipe->draw, 10000.0);
 
 #if USE_DRAW_STAGE_PSTIPPLE
    /* Do polygon stipple w/ texture map + frag prog? */
diff --git a/src/gallium/drivers/llvmpipe/lp_rast.h b/src/gallium/drivers/llvmpipe/lp_rast.h
index 102e902d02..b4564ef33b 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast.h
+++ b/src/gallium/drivers/llvmpipe/lp_rast.h
@@ -120,7 +120,7 @@ struct lp_rast_triangle {
    float v[3][2];
 #endif
 
-   struct lp_rast_plane plane[7]; /* NOTE: may allocate fewer planes */
+   struct lp_rast_plane plane[8]; /* NOTE: may allocate fewer planes */
 };
 
 
@@ -236,6 +236,8 @@ void lp_rast_triangle_6( struct lp_rasterizer_task *,
                          const union lp_rast_cmd_arg );
 void lp_rast_triangle_7( struct lp_rasterizer_task *, 
                          const union lp_rast_cmd_arg );
+void lp_rast_triangle_8( struct lp_rasterizer_task *, 
+                         const union lp_rast_cmd_arg );
 
 void lp_rast_shade_tile( struct lp_rasterizer_task *,
                          const union lp_rast_cmd_arg );
diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri.c b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
index 673f67386b..8d729c7481 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
@@ -157,6 +157,10 @@ build_mask_linear(int c, int dcdx, int dcdy)
 #define NR_PLANES 7
 #include "lp_rast_tri_tmp.h"
 
+#define TAG(x) x##_8
+#define NR_PLANES 8
+#include "lp_rast_tri_tmp.h"
+
 
 /* Special case for 3 plane triangle which is contained entirely
  * within a 16x16 block.
diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
index 70a4b64c8d..0def5f7243 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
@@ -32,7 +32,7 @@
 
 
 /**
- * Prototype for a 7 plane rasterizer function.  Will codegenerate
+ * Prototype for a 8 plane rasterizer function.  Will codegenerate
  * several of these.
  *
  * XXX: Varients for more/fewer planes.
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c
index 9aa6c4bf38..4c8275665e 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup.c
@@ -485,7 +485,14 @@ lp_setup_set_triangle_state( struct lp_setup_context *setup,
    }
 }
 
+void 
+lp_setup_set_line_state( struct lp_setup_context *setup,
+			 float line_width)
+{
+   LP_DBG(DEBUG_SETUP, "%s\n", __FUNCTION__);
 
+   setup->line_width = line_width;
+}
 
 void
 lp_setup_set_fs_inputs( struct lp_setup_context *setup,
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.h b/src/gallium/drivers/llvmpipe/lp_setup.h
index a41bb8863b..693550b8c8 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup.h
@@ -100,6 +100,10 @@ lp_setup_set_triangle_state( struct lp_setup_context *setup,
                              boolean scissor,
                              boolean gl_rasterization_rules );
 
+void 
+lp_setup_set_line_state( struct lp_setup_context *setup,
+                         float line_width);
+
 void
 lp_setup_set_fs_inputs( struct lp_setup_context *setup,
                         const struct lp_shader_input *interp,
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_context.h b/src/gallium/drivers/llvmpipe/lp_setup_context.h
index 1a147e0353..a4838d59a5 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup_context.h
@@ -91,6 +91,7 @@ struct lp_setup_context
    boolean scissor_test;
    unsigned cullmode;
    float pixel_offset;
+   float line_width;
 
    struct pipe_framebuffer_state fb;
    struct u_rect framebuffer;
@@ -170,5 +171,42 @@ lp_setup_print_vertex(struct lp_setup_context *setup,
                       const char *name,
                       const float (*v)[4]);
 
+/** shared code between lp_setup_line and lp_setup_tri */
+extern lp_rast_cmd lp_rast_tri_tab[]; 
+
+void
+do_triangle_ccw_whole_tile(struct lp_setup_context *setup,
+                           struct lp_scene *scene,
+                           struct lp_rast_triangle *tri,
+                           int x, int y,
+                           boolean opaque,
+                           int *is_blit);
+
+
+void 
+lp_setup_tri_coefficients( struct lp_setup_context *setup,
+                           struct lp_rast_triangle *tri,
+                           float oneoverarea,
+                           const float (*v1)[4],
+                           const float (*v2)[4],
+                           const float (*v3)[4],
+                           boolean frontface);
+
+struct lp_rast_triangle *
+lp_setup_alloc_triangle(struct lp_scene *scene,
+                        unsigned nr_inputs,
+                        unsigned nr_planes,
+                        unsigned *tri_size);
+
+void
+lp_setup_fragcoord_coef(struct lp_setup_context *setup,
+                         struct lp_rast_triangle *tri,
+                         float oneoverarea,
+                         unsigned slot,
+                         const float (*v1)[4],
+                         const float (*v2)[4],
+                         const float (*v3)[4],
+                         unsigned usage_mask);
+
 #endif
 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_line.c b/src/gallium/drivers/llvmpipe/lp_setup_line.c
index be41c44e6f..930207ae33 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_line.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_line.c
@@ -29,19 +29,624 @@
  * Binning code for lines
  */
 
+#include "util/u_math.h"
+#include "util/u_memory.h"
+#include "lp_perf.h"
 #include "lp_setup_context.h"
+#include "lp_rast.h"
+#include "lp_state_fs.h"
 
-static void line_nop( struct lp_setup_context *setup,
-                      const float (*v0)[4],
-                      const float (*v1)[4] )
+#define NUM_CHANNELS 4
+
+
+static const int step_scissor_minx[16] = {
+   0, 1, 0, 1,
+   2, 3, 2, 3,
+   0, 1, 0, 1,
+   2, 3, 2, 3
+};
+
+static const int step_scissor_maxx[16] = {
+    0, -1,  0, -1,
+   -2, -3, -2, -3,
+    0, -1,  0, -1,
+   -2, -3, -2, -3
+};
+
+static const int step_scissor_miny[16] = {
+   0, 0, 1, 1,
+   0, 0, 1, 1,
+   2, 2, 3, 3,
+   2, 2, 3, 3
+};
+
+static const int step_scissor_maxy[16] = {
+    0,  0, -1, -1,
+    0,  0, -1, -1,
+   -2, -2, -3, -3,
+   -2, -2, -3, -3
+};
+
+
+
+/**
+ * Compute a0 for a constant-valued coefficient (GL_FLAT shading).
+ */
+static void constant_coef( struct lp_setup_context *setup,
+                           struct lp_rast_triangle *tri,
+                           unsigned slot,
+                           const float value,
+                           unsigned i )
+{
+   tri->inputs.a0[slot][i] = value;
+   tri->inputs.dadx[slot][i] = 0.0f;
+   tri->inputs.dady[slot][i] = 0.0f;
+}
+
+
+/**
+ * Compute a0, dadx and dady for a linearly interpolated coefficient,
+ * for a triangle.
+ */
+static void linear_coef( struct lp_setup_context *setup,
+                         struct lp_rast_triangle *tri,
+                         float oneoverarea,
+                         unsigned slot,
+                         const float (*v1)[4],
+                         const float (*v2)[4],
+                         unsigned vert_attr,
+                         unsigned i)
+{
+   float a1 = v1[vert_attr][i]; 
+   float a2 = v2[vert_attr][i];
+      
+   float da21 = a1 - a2;   
+   float dadx = da21 * tri->dx * oneoverarea;
+   float dady = da21 * tri->dy * oneoverarea;
+
+   tri->inputs.dadx[slot][i] = dadx;
+   tri->inputs.dady[slot][i] = dady;  
+   
+   tri->inputs.a0[slot][i] = (a1 -
+                              (dadx * (v1[0][0] - setup->pixel_offset) +
+                               dady * (v1[0][1] - setup->pixel_offset)));
+}
+
+
+/**
+ * Compute a0, dadx and dady for a perspective-corrected interpolant,
+ * for a triangle.
+ * We basically multiply the vertex value by 1/w before computing
+ * the plane coefficients (a0, dadx, dady).
+ * Later, when we compute the value at a particular fragment position we'll
+ * divide the interpolated value by the interpolated W at that fragment.
+ */
+static void perspective_coef( struct lp_setup_context *setup,
+                              struct lp_rast_triangle *tri,
+                              float oneoverarea,
+                              unsigned slot,
+                              const float (*v1)[4],
+                              const float (*v2)[4],
+                              unsigned vert_attr,
+                              unsigned i)
+{
+   /* premultiply by 1/w  (v[0][3] is always 1/w):
+    */
+   float a1 = v1[vert_attr][i] * v1[0][3];
+   float a2 = v2[vert_attr][i] * v2[0][3];
+
+   float da21 = a1 - a2;   
+   float dadx = da21 * tri->dx * oneoverarea;
+   float dady = da21 * tri->dy * oneoverarea;
+
+   tri->inputs.dadx[slot][i] = dadx;
+   tri->inputs.dady[slot][i] = dady;
+   
+   tri->inputs.a0[slot][i] = (a1 -
+                              (dadx * (v1[0][0] - setup->pixel_offset) +
+                               dady * (v1[0][1] - setup->pixel_offset)));
+}
+
+/**
+ * Compute the tri->coef[] array dadx, dady, a0 values.
+ */
+static void setup_line_coefficients( struct lp_setup_context *setup,
+                                     struct lp_rast_triangle *tri,
+                                     float oneoverarea,
+                                     const float (*v1)[4],
+                                     const float (*v2)[4])
 {
+   unsigned fragcoord_usage_mask = TGSI_WRITEMASK_XYZ;
+   unsigned slot;
+
+   /* setup interpolation for all the remaining attributes:
+    */
+   for (slot = 0; slot < setup->fs.nr_inputs; slot++) {
+      unsigned vert_attr = setup->fs.input[slot].src_index;
+      unsigned usage_mask = setup->fs.input[slot].usage_mask;
+      unsigned i;
+           
+      switch (setup->fs.input[slot].interp) {
+      case LP_INTERP_CONSTANT:
+         if (setup->flatshade_first) {
+            for (i = 0; i < NUM_CHANNELS; i++)
+               if (usage_mask & (1 << i))
+                  constant_coef(setup, tri, slot+1, v1[vert_attr][i], i);
+         }
+         else {
+            for (i = 0; i < NUM_CHANNELS; i++)
+               if (usage_mask & (1 << i))
+                  constant_coef(setup, tri, slot+1, v2[vert_attr][i], i);
+         }
+         break;
+
+      case LP_INTERP_LINEAR:
+         for (i = 0; i < NUM_CHANNELS; i++)
+            if (usage_mask & (1 << i))
+               linear_coef(setup, tri, oneoverarea, slot+1, v1, v2, vert_attr, i);
+         break;
+
+      case LP_INTERP_PERSPECTIVE:
+         for (i = 0; i < NUM_CHANNELS; i++)
+            if (usage_mask & (1 << i))
+               perspective_coef(setup, tri, oneoverarea, slot+1, v1, v2, vert_attr, i);
+         fragcoord_usage_mask |= TGSI_WRITEMASK_W;
+         break;
+
+      case LP_INTERP_POSITION:
+         /*
+          * The generated pixel interpolators will pick up the coeffs from
+          * slot 0, so all need to ensure that the usage mask is covers all
+          * usages.
+          */
+         fragcoord_usage_mask |= usage_mask;
+         break;
+
+      default:
+         assert(0);
+      }
+   }
+
+   /* The internal position input is in slot zero:
+    */
+   lp_setup_fragcoord_coef(setup, tri, oneoverarea, 0, v1, v2, v2,
+                            fragcoord_usage_mask);
 }
 
 
-void 
-lp_setup_choose_line( struct lp_setup_context *setup )
+
+static INLINE int subpixel_snap( float a )
 {
-   setup->line = line_nop;
+   return util_iround(FIXED_ONE * a);
+}
+
+
+/**
+ * Print line vertex attribs (for debug).
+ */
+static void
+print_line(struct lp_setup_context *setup,
+           const float (*v1)[4],
+           const float (*v2)[4])
+{
+   uint i;
+
+   debug_printf("llvmpipe line\n");
+   for (i = 0; i < 1 + setup->fs.nr_inputs; i++) {
+      debug_printf("  v1[%d]:  %f %f %f %f\n", i,
+                   v1[i][0], v1[i][1], v1[i][2], v1[i][3]);
+   }
+   for (i = 0; i < 1 + setup->fs.nr_inputs; i++) {
+      debug_printf("  v2[%d]:  %f %f %f %f\n", i,
+                   v2[i][0], v2[i][1], v2[i][2], v2[i][3]);
+   }
+}
+
+
+static void
+lp_setup_line( struct lp_setup_context *setup,
+               const float (*v1)[4],
+               const float (*v2)[4])
+{
+   struct lp_scene *scene = lp_setup_get_current_scene(setup);
+   struct lp_rast_triangle *line;
+   float oneoverarea;
+   float half_width = setup->line_width / 2;
+   int minx, maxx, miny, maxy;
+   int ix0, ix1, iy0, iy1;
+   unsigned tri_bytes;
+   int x[4]; 
+   int y[4];
+   int i;
+   int nr_planes = 4;
+   boolean opaque;
+         
+   if (0)
+      print_line(setup, v1, v2);
+
+   if (setup->scissor_test) {
+      nr_planes = 8;
+   }
+   else {
+      nr_planes = 4;
+   }
+
+   line = lp_setup_alloc_triangle(scene,
+                                  setup->fs.nr_inputs,
+                                  nr_planes,
+                                  &tri_bytes);
+   if (!line)
+      return;
+
+#ifndef DEBUG
+   line->v[0][0] = v1[0][0];
+   line->v[1][0] = v2[0][0];   
+   line->v[0][1] = v1[0][1];
+   line->v[1][1] = v2[0][1];
+#endif
+
+   /* pre-calculation(based on given vertices) to determine if line is
+    * more horizontal or more vertical
+    */
+   line->dx = v1[0][0] - v2[0][0];
+   line->dy = v1[0][1] - v2[0][1];
+   
+   /* x-major line */
+   if (fabsf(line->dx) >= fabsf(line->dy)) {
+      if (line->dx < 0) {
+         /* if v2 is to the right of v1, swap pointers */
+         const float (*temp)[4] = v1;
+         v1 = v2;
+         v2 = temp;
+         line->dx = -line->dx;
+         line->dy = -line->dy;
+      }
+      
+      /* x/y positions in fixed point */
+      x[0] = subpixel_snap(v1[0][0] - setup->pixel_offset);
+      x[1] = subpixel_snap(v2[0][0] - setup->pixel_offset);
+      x[2] = subpixel_snap(v2[0][0] - setup->pixel_offset);
+      x[3] = subpixel_snap(v1[0][0] - setup->pixel_offset);
+      
+      y[0] = subpixel_snap(v1[0][1] - half_width - setup->pixel_offset);
+      y[1] = subpixel_snap(v2[0][1] - half_width - setup->pixel_offset);
+      y[2] = subpixel_snap(v2[0][1] + half_width - setup->pixel_offset);
+      y[3] = subpixel_snap(v1[0][1] + half_width - setup->pixel_offset);
+   }
+   else{
+      /* y-major line */
+      if (line->dy > 0) {
+         /* if v2 is on top of v1, swap pointers */
+         const float (*temp)[4] = v1;
+         v1 = v2;
+         v2 = temp; 
+         line->dx = -line->dx;
+         line->dy = -line->dy;
+      }
+ 
+      x[0] = subpixel_snap(v1[0][0] - half_width - setup->pixel_offset);
+      x[1] = subpixel_snap(v2[0][0] - half_width - setup->pixel_offset);
+      x[2] = subpixel_snap(v2[0][0] + half_width - setup->pixel_offset);
+      x[3] = subpixel_snap(v1[0][0] + half_width - setup->pixel_offset);
+     
+      y[0] = subpixel_snap(v1[0][1] - setup->pixel_offset);
+      y[1] = subpixel_snap(v2[0][1] - setup->pixel_offset);
+      y[2] = subpixel_snap(v2[0][1] - setup->pixel_offset);
+      y[3] = subpixel_snap(v1[0][1] - setup->pixel_offset);
+   }
+
+   /* calculate the deltas */
+   line->plane[0].dcdy = x[0] - x[1];
+   line->plane[1].dcdy = x[1] - x[2];
+   line->plane[2].dcdy = x[2] - x[3];
+   line->plane[3].dcdy = x[3] - x[0];
+
+   line->plane[0].dcdx = y[0] - y[1];
+   line->plane[1].dcdx = y[1] - y[2];
+   line->plane[2].dcdx = y[2] - y[3];
+   line->plane[3].dcdx = y[3] - y[0];
+
+
+   LP_COUNT(nr_tris);
+
+ 
+   /* Bounding rectangle (in pixels) */
+   {
+      /* Yes this is necessary to accurately calculate bounding boxes
+       * with the two fill-conventions we support.  GL (normally) ends
+       * up needing a bottom-left fill convention, which requires
+       * slightly different rounding.
+       */
+      int adj = (setup->pixel_offset != 0) ? 1 : 0;
+
+      minx = (MIN4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      maxx = (MAX4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      miny = (MIN4(y[0], y[1], y[3], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      maxy = (MAX4(y[0], y[1], y[3], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+   }
+
+   if (setup->scissor_test) {
+      minx = MAX2(minx, setup->scissor.current.minx);
+      maxx = MIN2(maxx, setup->scissor.current.maxx);
+      miny = MAX2(miny, setup->scissor.current.miny);
+      maxy = MIN2(maxy, setup->scissor.current.maxy);
+   }
+   else {
+      minx = MAX2(minx, 0);
+      miny = MAX2(miny, 0);
+      maxx = MIN2(maxx, scene->fb.width);
+      maxy = MIN2(maxy, scene->fb.height);
+   }
+
+
+   if (miny >= maxy || minx >= maxx) {
+      lp_scene_putback_data( scene, tri_bytes );
+      return;
+   }
+
+   oneoverarea = 1.0f / (line->dx * line->dx  + line->dy * line->dy);    
+
+   /* Setup parameter interpolants:
+    */
+   setup_line_coefficients( setup, line, oneoverarea, v1, v2); 
+
+   for (i = 0; i < 4; i++) {
+      struct lp_rast_plane *plane = &line->plane[i];
+
+      /* half-edge constants, will be interated over the whole render
+       * target.
+       */
+      plane->c = plane->dcdx * x[i] - plane->dcdy * y[i];
+
+      
+      /* correct for top-left vs. bottom-left fill convention.  
+       *
+       * note that we're overloading gl_rasterization_rules to mean
+       * both (0.5,0.5) pixel centers *and* bottom-left filling
+       * convention.
+       *
+       * GL actually has a top-left filling convention, but GL's
+       * notion of "top" differs from gallium's...
+       *
+       * Also, sometimes (in FBO cases) GL will render upside down
+       * to its usual method, in which case it will probably want
+       * to use the opposite, top-left convention.
+       */         
+      if (plane->dcdx < 0) {
+         /* both fill conventions want this - adjust for left edges */
+         plane->c++;            
+      }
+      else if (plane->dcdx == 0) {
+         if (setup->pixel_offset == 0) {
+            /* correct for top-left fill convention:
+             */
+            if (plane->dcdy > 0) plane->c++;
+         }
+         else {
+            /* correct for bottom-left fill convention:
+             */
+            if (plane->dcdy < 0) plane->c++;
+         }
+      }
+
+      plane->dcdx *= FIXED_ONE;
+      plane->dcdy *= FIXED_ONE;
+
+      /* find trivial reject offsets for each edge for a single-pixel
+       * sized block.  These will be scaled up at each recursive level to
+       * match the active blocksize.  Scaling in this way works best if
+       * the blocks are square.
+       */
+      plane->eo = 0;
+      if (plane->dcdx < 0) plane->eo -= plane->dcdx;
+      if (plane->dcdy > 0) plane->eo += plane->dcdy;
+
+      /* Calculate trivial accept offsets from the above.
+       */
+      plane->ei = plane->dcdy - plane->dcdx - plane->eo;
+
+      plane->step = line->step[i];
+
+      /* Fill in the inputs.step[][] arrays.
+       * We've manually unrolled some loops here.
+       */
+#define SETUP_STEP(j, x, y) \
+      line->step[i][j] = y * plane->dcdy - x * plane->dcdx                                     
+      
+      SETUP_STEP(0, 0, 0);
+      SETUP_STEP(1, 1, 0);
+      SETUP_STEP(2, 0, 1);
+      SETUP_STEP(3, 1, 1);
+
+      SETUP_STEP(4, 2, 0);
+      SETUP_STEP(5, 3, 0);
+      SETUP_STEP(6, 2, 1);
+      SETUP_STEP(7, 3, 1);
+
+      SETUP_STEP(8, 0, 2);
+      SETUP_STEP(9, 1, 2);
+      SETUP_STEP(10, 0, 3);
+      SETUP_STEP(11, 1, 3);
+
+      SETUP_STEP(12, 2, 2);
+      SETUP_STEP(13, 3, 2);
+      SETUP_STEP(14, 2, 3);
+      SETUP_STEP(15, 3, 3);
+#undef STEP
+   }
+
+
+   /* 
+    * When rasterizing scissored tris, use the intersection of the
+    * triangle bounding box and the scissor rect to generate the
+    * scissor planes.
+    *
+    * This permits us to cut off the triangle "tails" that are present
+    * in the intermediate recursive levels caused when two of the
+    * triangles edges don't diverge quickly enough to trivially reject
+    * exterior blocks from the triangle.
+    *
+    * It's not really clear if it's worth worrying about these tails,
+    * but since we generate the planes for each scissored tri, it's
+    * free to trim them in this case.
+    * 
+    * Note that otherwise, the scissor planes only vary in 'C' value,
+    * and even then only on state-changes.  Could alternatively store
+    * these planes elsewhere.
+    */
+   if (nr_planes == 8) {
+      line->plane[4].step = step_scissor_maxx;
+      line->plane[4].dcdx = 1;
+      line->plane[4].dcdy = 0;
+      line->plane[4].c = maxx;
+      line->plane[4].ei = -1;
+      line->plane[4].eo = 0;
+
+      line->plane[5].step = step_scissor_miny;
+      line->plane[5].dcdx = 0;
+      line->plane[5].dcdy = 1;
+      line->plane[5].c = 1-miny;
+      line->plane[5].ei = 0;
+      line->plane[5].eo = 1;
+
+      line->plane[6].step = step_scissor_maxy;
+      line->plane[6].dcdx = 0;
+      line->plane[6].dcdy = -1;
+      line->plane[6].c = maxy;
+      line->plane[6].ei = -1;
+      line->plane[6].eo = 0;
+
+      line->plane[7].step = step_scissor_minx;
+      line->plane[7].dcdx = -1;
+      line->plane[7].dcdy = 0;
+      line->plane[7].c = 1-minx;
+      line->plane[7].ei = 0;
+      line->plane[7].eo = 1;
+   }
+
+
+   /*
+    * All fields of 'tri' are now set.  The remaining code here is
+    * concerned with binning.
+    */
+
+   /* Convert to tile coordinates, and inclusive ranges:
+    */
+   ix0 = minx / TILE_SIZE;
+   iy0 = miny / TILE_SIZE;
+   ix1 = (maxx-1) / TILE_SIZE;
+   iy1 = (maxy-1) / TILE_SIZE;
+
+   /*
+    * Clamp to framebuffer size
+    */
+   assert(ix0 == MAX2(ix0, 0));
+   assert(iy0 == MAX2(iy0, 0));
+   assert(ix1 == MIN2(ix1, scene->tiles_x - 1));
+   assert(iy1 == MIN2(iy1, scene->tiles_y - 1));
+
+   /* Determine which tile(s) intersect the triangle's bounding box
+    */
+   if (iy0 == iy1 && ix0 == ix1)
+   {
+      /* Triangle is contained in a single tile:
+       */
+      lp_scene_bin_command( scene, ix0, iy0,
+                            lp_rast_tri_tab[nr_planes], 
+                            lp_rast_arg_triangle(line, (1<<nr_planes)-1) );
+   }
+   else
+   {
+      int c[8];
+      int ei[8];
+      int eo[8];
+      int xstep[8];
+      int ystep[8];
+      int x, y;
+      int is_blit = -1; /* undetermined */
+      
+      for (i = 0; i < nr_planes; i++) {
+         c[i] = (line->plane[i].c + 
+                 line->plane[i].dcdy * iy0 * TILE_SIZE - 
+                 line->plane[i].dcdx * ix0 * TILE_SIZE);
+
+         ei[i] = line->plane[i].ei << TILE_ORDER;
+         eo[i] = line->plane[i].eo << TILE_ORDER;
+         xstep[i] = -(line->plane[i].dcdx << TILE_ORDER);
+         ystep[i] = line->plane[i].dcdy << TILE_ORDER;
+      }
+
+
+
+      /* Test tile-sized blocks against the triangle.
+       * Discard blocks fully outside the tri.  If the block is fully
+       * contained inside the tri, bin an lp_rast_shade_tile command.
+       * Else, bin a lp_rast_triangle command.
+       */
+      for (y = iy0; y <= iy1; y++)
+      {
+         boolean in = FALSE;  /* are we inside the triangle? */
+         int cx[8];
+
+         for (i = 0; i < nr_planes; i++)
+            cx[i] = c[i];
+
+         for (x = ix0; x <= ix1; x++)
+         {
+            int out = 0;
+            int partial = 0;
+
+            for (i = 0; i < nr_planes; i++) {
+               int planeout = cx[i] + eo[i];
+               int planepartial = cx[i] + ei[i] - 1;
+               out |= (planeout >> 31);
+               partial |= (planepartial >> 31) & (1<<i);      
+            }
+            if (out) {
+               /* do nothing */
+               if (in)
+                  break;  /* exiting triangle, all done with this row */
+               LP_COUNT(nr_empty_64);
+            }
+            else if (partial) {
+               /* Not trivially accepted by at least one plane - 
+                * rasterize/shade partial tile
+                */
+               int count = util_bitcount(partial);
+               in = TRUE;
+               lp_scene_bin_command( scene, x, y,
+                                     lp_rast_tri_tab[count], 
+                                     lp_rast_arg_triangle(line, partial) );
+
+               LP_COUNT(nr_partially_covered_64);
+            }
+            else {
+               /* triangle covers the whole tile- shade whole tile */
+               LP_COUNT(nr_fully_covered_64);
+               in = TRUE;
+               /* leverages on existing code in lp_setup_tri.c */ 
+               do_triangle_ccw_whole_tile(setup, scene, line, x, y,
+                                          opaque, &is_blit);
+            }
+
+            /* Iterate cx values across the region:
+             */
+            for (i = 0; i < nr_planes; i++)
+               cx[i] += xstep[i];
+         }
+      
+         /* Iterate c values down the region:
+          */
+         for (i = 0; i < nr_planes; i++)
+            c[i] += ystep[i];
+      }
+   }
+}
+
+
+void lp_setup_choose_line( struct lp_setup_context *setup ) 
+{ 
+   setup->line = lp_setup_line;
 }
 
 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_point.c b/src/gallium/drivers/llvmpipe/lp_setup_point.c
index 9f69e6c5ce..709c3e2fd2 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_point.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_point.c
@@ -31,7 +31,7 @@
 
 #include "lp_setup_context.h"
 
-static void point_nop( struct lp_setup_context *setup,
+static void lp_setup_point( struct lp_setup_context *setup,
                        const float (*v0)[4] )
 {
 }
@@ -40,7 +40,7 @@ static void point_nop( struct lp_setup_context *setup,
 void 
 lp_setup_choose_point( struct lp_setup_context *setup )
 {
-   setup->point = point_nop;
+   setup->point = lp_setup_point;
 }
 
 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index d86fb8652a..212bb3ab90 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -68,11 +68,11 @@ fixed_to_float(int a)
  * \param nr_inputs  number of fragment shader inputs
  * \return pointer to triangle space
  */
-static INLINE struct lp_rast_triangle *
-alloc_triangle(struct lp_scene *scene,
-               unsigned nr_inputs,
-               unsigned nr_planes,
-               unsigned *tri_size)
+struct lp_rast_triangle *
+lp_setup_alloc_triangle(struct lp_scene *scene,
+                        unsigned nr_inputs,
+                        unsigned nr_planes,
+                        unsigned *tri_size)
 {
    unsigned input_array_sz = NUM_CHANNELS * (nr_inputs + 1) * sizeof(float);
    struct lp_rast_triangle *tri;
@@ -160,7 +160,7 @@ lp_setup_print_triangle(struct lp_setup_context *setup,
 }
 
 
-lp_rast_cmd lp_rast_tri_tab[8] = {
+lp_rast_cmd lp_rast_tri_tab[9] = {
    NULL,               /* should be impossible */
    lp_rast_triangle_1,
    lp_rast_triangle_2,
@@ -168,7 +168,8 @@ lp_rast_cmd lp_rast_tri_tab[8] = {
    lp_rast_triangle_4,
    lp_rast_triangle_5,
    lp_rast_triangle_6,
-   lp_rast_triangle_7
+   lp_rast_triangle_7,
+   lp_rast_triangle_8
 };
 
 /**
@@ -254,10 +255,10 @@ do_triangle_ccw(struct lp_setup_context *setup,
 
    u_rect_find_intersection(&setup->draw_region, &bbox);
 
-   tri = alloc_triangle(scene,
-                        setup->fs.nr_inputs,
-                        nr_planes,
-                        &tri_bytes);
+   tri = lp_setup_alloc_triangle(scene,
+                                 setup->fs.nr_inputs,
+                                 nr_planes,
+                                 &tri_bytes);
    if (!tri)
       return;
 
diff --git a/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c b/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
index afd3e0b21c..67b985aa24 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
@@ -73,6 +73,8 @@ llvmpipe_bind_rasterizer_state(struct pipe_context *pipe, void *handle)
                    llvmpipe->rasterizer->gl_rasterization_rules);
       lp_setup_set_flatshade_first( llvmpipe->setup,
                    llvmpipe->rasterizer->flatshade_first);
+      lp_setup_set_line_state( llvmpipe->setup,
+                   llvmpipe->rasterizer->line_width);
    }
 
    llvmpipe->dirty |= LP_NEW_RASTERIZER;
-- 
cgit v1.2.3


From b91553355f848f2174d53429699b116734781ad7 Mon Sep 17 00:00:00 2001
From: Hui Qi Tay <hqtay@vmware.com>
Date: Wed, 4 Aug 2010 17:13:39 +0100
Subject: llvmpipe: native line rasterization with correct pixel rasterization

Line rasterization that follows diamond exit rule.
Can still optimize logic for start/endpoints.
---
 src/gallium/drivers/llvmpipe/lp_setup_line.c | 242 +++++++++++++++++++++++----
 1 file changed, 213 insertions(+), 29 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup_line.c b/src/gallium/drivers/llvmpipe/lp_setup_line.c
index 930207ae33..1566203117 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_line.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_line.c
@@ -243,6 +243,11 @@ print_line(struct lp_setup_context *setup,
 }
 
 
+static INLINE boolean sign(float x){
+   return x >= 0;  
+}  
+
+
 static void
 lp_setup_line( struct lp_setup_context *setup,
                const float (*v1)[4],
@@ -251,7 +256,7 @@ lp_setup_line( struct lp_setup_context *setup,
    struct lp_scene *scene = lp_setup_get_current_scene(setup);
    struct lp_rast_triangle *line;
    float oneoverarea;
-   float half_width = setup->line_width / 2;
+   float width = MAX2(1.0, setup->line_width);
    int minx, maxx, miny, maxy;
    int ix0, ix1, iy0, iy1;
    unsigned tri_bytes;
@@ -260,7 +265,25 @@ lp_setup_line( struct lp_setup_context *setup,
    int i;
    int nr_planes = 4;
    boolean opaque;
-         
+   
+   /* linewidth should be interpreted as integer */
+   int fixed_width = subpixel_snap(round(width));
+
+   float xdiamond_offset=0;
+   float ydiamond_offset=0;
+   float xdiamond_offset_end=0;
+   float ydiamond_offset_end=0;
+      
+   float x1diff;
+   float y1diff;
+   float x2diff;
+   float y2diff;
+
+   boolean draw_start;
+   boolean draw_end;
+   boolean will_draw_start;
+   boolean will_draw_end;
+
    if (0)
       print_line(setup, v1, v2);
 
@@ -278,21 +301,76 @@ lp_setup_line( struct lp_setup_context *setup,
    if (!line)
       return;
 
-#ifndef DEBUG
+#ifdef DEBUG
    line->v[0][0] = v1[0][0];
    line->v[1][0] = v2[0][0];   
    line->v[0][1] = v1[0][1];
    line->v[1][1] = v2[0][1];
 #endif
 
-   /* pre-calculation(based on given vertices) to determine if line is
-    * more horizontal or more vertical
-    */
    line->dx = v1[0][0] - v2[0][0];
    line->dy = v1[0][1] - v2[0][1];
-   
-   /* x-major line */
+  
+/* X-MAJOR LINE */
    if (fabsf(line->dx) >= fabsf(line->dy)) {
+
+      x1diff = v1[0][0] - (float) floor(v1[0][0]) - 0.5;
+      y1diff = v1[0][1] - (float) floor(v1[0][1]) - 0.5;
+      x2diff = v2[0][0] - (float) floor(v2[0][0]) - 0.5;
+      y2diff = v2[0][1] - (float) floor(v2[0][1]) - 0.5;
+
+      if (y2diff==-0.5 && line->dy<0){
+         y2diff = 0.5;
+      }
+      
+      /* 
+       * Diamond exit rule test for starting point 
+       */    
+      if (fabsf(x1diff) + fabsf(y1diff) < 0.5) {
+         draw_start = TRUE;
+      }
+      else if (sign(x1diff) == sign(-line->dx)) {
+         draw_start = FALSE;
+      }
+      else if (sign(-y1diff) != sign(line->dy)) {
+         draw_start = TRUE;
+      }
+      else {
+         /* do intersection test */
+         float yintersect = v1[0][1] + x1diff*((float)line->dy/(float)line->dx);
+         if (yintersect < ceil(v1[0][1]) && yintersect > floor(v1[0][1])){
+            draw_start = TRUE;
+         }
+         else draw_start = FALSE;
+      }
+
+
+      /* 
+       * Diamond exit rule test for ending point 
+       */    
+      if (fabsf(x2diff) + fabsf(y2diff) < 0.5) {
+         draw_end = FALSE;
+      }
+      else if (sign(x2diff) != sign(-line->dx)) {
+         draw_end = FALSE;
+      }
+      else if (sign(-y2diff) == sign(line->dy)) {
+         draw_end = TRUE;
+      }
+      else {
+         /* do intersection test */
+         float yintersect = v2[0][1] + x2diff*((float)line->dy/(float)line->dx);
+         if (yintersect < ceil(v2[0][1]) && yintersect > floor(v2[0][1])){
+            draw_end = TRUE;
+         }
+         else draw_end = FALSE;
+      }
+
+      /* Are we already drawing start/end?
+       */
+      will_draw_start = sign(-x1diff) != sign(line->dx);
+      will_draw_end = (sign(x2diff) == sign(-line->dx)) || x2diff==0;
+
       if (line->dx < 0) {
          /* if v2 is to the right of v1, swap pointers */
          const float (*temp)[4] = v1;
@@ -300,21 +378,102 @@ lp_setup_line( struct lp_setup_context *setup,
          v2 = temp;
          line->dx = -line->dx;
          line->dy = -line->dy;
+         /* Otherwise shift planes appropriately */
+         if (will_draw_start != draw_start) {
+            xdiamond_offset_end = - x1diff - 0.5;
+            ydiamond_offset_end = xdiamond_offset_end*(float)line->dy/(float)line->dx;
+
+         }
+         if (will_draw_end != draw_end) {
+            xdiamond_offset = - x2diff - 0.5;
+            ydiamond_offset = xdiamond_offset*(float)line->dy/(float)line->dx;
+         }
+
       }
-      
+      else{
+         /* Otherwise shift planes appropriately */
+         if (will_draw_start != draw_start) {
+            xdiamond_offset = - x1diff + 0.5;
+            ydiamond_offset = xdiamond_offset*(float)line->dy/(float)line->dx;
+         }
+         if (will_draw_end != draw_end) {
+            xdiamond_offset_end = - x2diff + 0.5;
+            ydiamond_offset_end = xdiamond_offset_end*(float)line->dy/(float)line->dx;
+         }
+      }
+  
       /* x/y positions in fixed point */
-      x[0] = subpixel_snap(v1[0][0] - setup->pixel_offset);
-      x[1] = subpixel_snap(v2[0][0] - setup->pixel_offset);
-      x[2] = subpixel_snap(v2[0][0] - setup->pixel_offset);
-      x[3] = subpixel_snap(v1[0][0] - setup->pixel_offset);
+      x[0] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset);
+      x[1] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset);
+      x[2] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset);
+      x[3] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset);
+      
+      y[0] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset) - fixed_width/2;
+      y[1] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset) - fixed_width/2;
+      y[2] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset) + fixed_width/2;
+      y[3] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset) + fixed_width/2;
       
-      y[0] = subpixel_snap(v1[0][1] - half_width - setup->pixel_offset);
-      y[1] = subpixel_snap(v2[0][1] - half_width - setup->pixel_offset);
-      y[2] = subpixel_snap(v2[0][1] + half_width - setup->pixel_offset);
-      y[3] = subpixel_snap(v1[0][1] + half_width - setup->pixel_offset);
    }
+
+
    else{
-      /* y-major line */
+/* Y-MAJOR LINE */      
+      x1diff = v1[0][0] - (float) floor(v1[0][0]) - 0.5;
+      y1diff = v1[0][1] - (float) floor(v1[0][1]) - 0.5;
+      x2diff = v2[0][0] - (float) floor(v2[0][0]) - 0.5;
+      y2diff = v2[0][1] - (float) floor(v2[0][1]) - 0.5;
+
+      if (x2diff==-0.5 && line->dx<0){
+         x2diff = 0.5;
+      }
+
+/* 
+ * Diamond exit rule test for starting point 
+ */    
+      if (fabsf(x1diff) + fabsf(y1diff) < 0.5) {
+         draw_start = TRUE;
+      }
+      else if (sign(-y1diff) == sign(line->dy)) {
+         draw_start = FALSE;
+      }
+      else if (sign(x1diff) != sign(-line->dx)) {
+         draw_start = TRUE;
+      }
+      else {
+         /* do intersection test */
+         float xintersect = v1[0][0] + y1diff*((float)line->dx/(float)line->dy);
+         if (xintersect < ceil(v1[0][0]) && xintersect > floor(v1[0][0])){
+            draw_start = TRUE;
+         }
+         else draw_start = FALSE;
+      }
+
+      /* 
+       * Diamond exit rule test for ending point 
+       */    
+      if (fabsf(x2diff) + fabsf(y2diff) < 0.5) {
+         draw_end = FALSE;
+      }
+      else if (sign(-y2diff) != sign(line->dy) ) {
+         draw_end = FALSE;
+      }
+      else if (sign(x2diff) == sign(-line->dx) ) {
+         draw_end = TRUE;
+      }
+      else {
+         /* do intersection test */
+         float xintersect = v2[0][0] + y2diff*((float)line->dx/(float)line->dy);
+         if (xintersect < ceil(v2[0][0]) && xintersect > floor(v2[0][0])){
+            draw_end = TRUE;
+         }
+         else draw_end = FALSE;
+      }
+
+      /* Are we already drawing start/end?
+       */
+      will_draw_start = sign(y1diff) == sign(line->dy);
+      will_draw_end = (sign(-y2diff) == sign(line->dy)) || y2diff==0;
+
       if (line->dy > 0) {
          /* if v2 is on top of v1, swap pointers */
          const float (*temp)[4] = v1;
@@ -322,19 +481,44 @@ lp_setup_line( struct lp_setup_context *setup,
          v2 = temp; 
          line->dx = -line->dx;
          line->dy = -line->dy;
+
+         /* Otherwise shift planes appropriately */
+         if (will_draw_start != draw_start) {
+            ydiamond_offset_end = - y1diff + 0.5;
+            xdiamond_offset_end = ydiamond_offset_end*(float)line->dx/(float)line->dy;
+         }
+         if (will_draw_end != draw_end) {
+            ydiamond_offset = - y2diff + 0.5;
+            xdiamond_offset = ydiamond_offset*(float)line->dx/(float)line->dy;
+         }
+      }
+
+      else{
+         /* Otherwise shift planes appropriately */
+         if (will_draw_start != draw_start) {
+            ydiamond_offset = - y1diff - 0.5;
+            xdiamond_offset = ydiamond_offset*(float)line->dx/(float)line->dy;
+                     
+         }
+         if (will_draw_end != draw_end) {
+            ydiamond_offset_end = - y2diff - 0.5;
+            xdiamond_offset_end = ydiamond_offset_end*(float)line->dx/(float)line->dy;
+         }
       }
  
-      x[0] = subpixel_snap(v1[0][0] - half_width - setup->pixel_offset);
-      x[1] = subpixel_snap(v2[0][0] - half_width - setup->pixel_offset);
-      x[2] = subpixel_snap(v2[0][0] + half_width - setup->pixel_offset);
-      x[3] = subpixel_snap(v1[0][0] + half_width - setup->pixel_offset);
+      /* x/y positions in fixed point */
+      x[0] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset) - fixed_width/2;
+      x[1] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset) - fixed_width/2;
+      x[2] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset) + fixed_width/2;
+      x[3] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset) + fixed_width/2;
      
-      y[0] = subpixel_snap(v1[0][1] - setup->pixel_offset);
-      y[1] = subpixel_snap(v2[0][1] - setup->pixel_offset);
-      y[2] = subpixel_snap(v2[0][1] - setup->pixel_offset);
-      y[3] = subpixel_snap(v1[0][1] - setup->pixel_offset);
+      y[0] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset); 
+      y[1] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset);
+      y[2] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset);
+      y[3] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset);
    }
 
+
    /* calculate the deltas */
    line->plane[0].dcdy = x[0] - x[1];
    line->plane[1].dcdy = x[1] - x[2];
@@ -361,8 +545,8 @@ lp_setup_line( struct lp_setup_context *setup,
 
       minx = (MIN4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
       maxx = (MAX4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      miny = (MIN4(y[0], y[1], y[3], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
-      maxy = (MAX4(y[0], y[1], y[3], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      miny = (MIN4(y[0], y[1], y[2], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      maxy = (MAX4(y[0], y[1], y[2], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
    }
 
    if (setup->scissor_test) {
@@ -526,7 +710,7 @@ lp_setup_line( struct lp_setup_context *setup,
 
 
    /*
-    * All fields of 'tri' are now set.  The remaining code here is
+    * All fields of 'line' are now set.  The remaining code here is
     * concerned with binning.
     */
 
-- 
cgit v1.2.3


From 3783053fa59fceef59fe0356af5c8dbc095e9adf Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Thu, 26 Aug 2010 20:09:22 +0100
Subject: llvmpipe: update line rasterization code to current master

---
 src/gallium/drivers/llvmpipe/lp_rast.h          |   5 +
 src/gallium/drivers/llvmpipe/lp_setup_context.h |  32 +-
 src/gallium/drivers/llvmpipe/lp_setup_line.c    | 531 +++++++++---------------
 src/gallium/drivers/llvmpipe/lp_setup_tri.c     |  33 +-
 4 files changed, 227 insertions(+), 374 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_rast.h b/src/gallium/drivers/llvmpipe/lp_rast.h
index b4564ef33b..37b4fdc31e 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast.h
+++ b/src/gallium/drivers/llvmpipe/lp_rast.h
@@ -116,6 +116,11 @@ struct lp_rast_triangle {
    /* inputs for the shader */
    struct lp_rast_shader_inputs inputs;
 
+   /* XXX: temporarily use these additional fields for line
+    * coefficient setup
+    */
+   float dx, dy; 
+
 #ifdef DEBUG
    float v[3][2];
 #endif
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_context.h b/src/gallium/drivers/llvmpipe/lp_setup_context.h
index a4838d59a5..97919c09d4 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup_context.h
@@ -171,26 +171,6 @@ lp_setup_print_vertex(struct lp_setup_context *setup,
                       const char *name,
                       const float (*v)[4]);
 
-/** shared code between lp_setup_line and lp_setup_tri */
-extern lp_rast_cmd lp_rast_tri_tab[]; 
-
-void
-do_triangle_ccw_whole_tile(struct lp_setup_context *setup,
-                           struct lp_scene *scene,
-                           struct lp_rast_triangle *tri,
-                           int x, int y,
-                           boolean opaque,
-                           int *is_blit);
-
-
-void 
-lp_setup_tri_coefficients( struct lp_setup_context *setup,
-                           struct lp_rast_triangle *tri,
-                           float oneoverarea,
-                           const float (*v1)[4],
-                           const float (*v2)[4],
-                           const float (*v3)[4],
-                           boolean frontface);
 
 struct lp_rast_triangle *
 lp_setup_alloc_triangle(struct lp_scene *scene,
@@ -199,14 +179,10 @@ lp_setup_alloc_triangle(struct lp_scene *scene,
                         unsigned *tri_size);
 
 void
-lp_setup_fragcoord_coef(struct lp_setup_context *setup,
-                         struct lp_rast_triangle *tri,
-                         float oneoverarea,
-                         unsigned slot,
-                         const float (*v1)[4],
-                         const float (*v2)[4],
-                         const float (*v3)[4],
-                         unsigned usage_mask);
+lp_setup_bin_triangle( struct lp_setup_context *setup,
+                       struct lp_rast_triangle *tri,
+                       const struct u_rect *bbox,
+                       int nr_planes );
 
 #endif
 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_line.c b/src/gallium/drivers/llvmpipe/lp_setup_line.c
index 1566203117..ebf000dd19 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_line.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_line.c
@@ -39,35 +39,6 @@
 #define NUM_CHANNELS 4
 
 
-static const int step_scissor_minx[16] = {
-   0, 1, 0, 1,
-   2, 3, 2, 3,
-   0, 1, 0, 1,
-   2, 3, 2, 3
-};
-
-static const int step_scissor_maxx[16] = {
-    0, -1,  0, -1,
-   -2, -3, -2, -3,
-    0, -1,  0, -1,
-   -2, -3, -2, -3
-};
-
-static const int step_scissor_miny[16] = {
-   0, 0, 1, 1,
-   0, 0, 1, 1,
-   2, 2, 3, 3,
-   2, 2, 3, 3
-};
-
-static const int step_scissor_maxy[16] = {
-    0,  0, -1, -1,
-    0,  0, -1, -1,
-   -2, -2, -3, -3,
-   -2, -2, -3, -3
-};
-
-
 
 /**
  * Compute a0 for a constant-valued coefficient (GL_FLAT shading).
@@ -147,6 +118,40 @@ static void perspective_coef( struct lp_setup_context *setup,
                                dady * (v1[0][1] - setup->pixel_offset)));
 }
 
+static void
+setup_fragcoord_coef( struct lp_setup_context *setup,
+                      struct lp_rast_triangle *tri,
+                      float oneoverarea,
+                      unsigned slot,
+                      const float (*v1)[4],
+                      const float (*v2)[4],
+                      unsigned usage_mask)
+{
+   /*X*/
+   if (usage_mask & TGSI_WRITEMASK_X) {
+      tri->inputs.a0[slot][0] = 0.0;
+      tri->inputs.dadx[slot][0] = 1.0;
+      tri->inputs.dady[slot][0] = 0.0;
+   }
+
+   /*Y*/
+   if (usage_mask & TGSI_WRITEMASK_Y) {
+      tri->inputs.a0[slot][1] = 0.0;
+      tri->inputs.dadx[slot][1] = 0.0;
+      tri->inputs.dady[slot][1] = 1.0;
+   }
+
+   /*Z*/
+   if (usage_mask & TGSI_WRITEMASK_Z) {
+      linear_coef(setup, tri, oneoverarea, slot, v1, v2, 0, 2);
+   }
+
+   /*W*/
+   if (usage_mask & TGSI_WRITEMASK_W) {
+      linear_coef(setup, tri, oneoverarea, slot, v1, v2, 0, 3);
+   }
+}
+
 /**
  * Compute the tri->coef[] array dadx, dady, a0 values.
  */
@@ -209,8 +214,8 @@ static void setup_line_coefficients( struct lp_setup_context *setup,
 
    /* The internal position input is in slot zero:
     */
-   lp_setup_fragcoord_coef(setup, tri, oneoverarea, 0, v1, v2, v2,
-                            fragcoord_usage_mask);
+   setup_fragcoord_coef(setup, tri, oneoverarea, 0, v1, v2,
+                        fragcoord_usage_mask);
 }
 
 
@@ -248,6 +253,15 @@ static INLINE boolean sign(float x){
 }  
 
 
+/* Used on positive floats only:
+ */
+static INLINE float fracf(float f)
+{
+   return f - floorf(f);
+}
+
+
+
 static void
 lp_setup_line( struct lp_setup_context *setup,
                const float (*v1)[4],
@@ -257,27 +271,26 @@ lp_setup_line( struct lp_setup_context *setup,
    struct lp_rast_triangle *line;
    float oneoverarea;
    float width = MAX2(1.0, setup->line_width);
-   int minx, maxx, miny, maxy;
-   int ix0, ix1, iy0, iy1;
+   struct u_rect bbox;
    unsigned tri_bytes;
    int x[4]; 
    int y[4];
    int i;
    int nr_planes = 4;
-   boolean opaque;
    
    /* linewidth should be interpreted as integer */
    int fixed_width = subpixel_snap(round(width));
 
-   float xdiamond_offset=0;
-   float ydiamond_offset=0;
-   float xdiamond_offset_end=0;
-   float ydiamond_offset_end=0;
+   float x_offset=0;
+   float y_offset=0;
+   float x_offset_end=0;
+   float y_offset_end=0;
       
    float x1diff;
    float y1diff;
    float x2diff;
    float y2diff;
+   float dx, dy;
 
    boolean draw_start;
    boolean draw_end;
@@ -294,32 +307,20 @@ lp_setup_line( struct lp_setup_context *setup,
       nr_planes = 4;
    }
 
-   line = lp_setup_alloc_triangle(scene,
-                                  setup->fs.nr_inputs,
-                                  nr_planes,
-                                  &tri_bytes);
-   if (!line)
-      return;
-
-#ifdef DEBUG
-   line->v[0][0] = v1[0][0];
-   line->v[1][0] = v2[0][0];   
-   line->v[0][1] = v1[0][1];
-   line->v[1][1] = v2[0][1];
-#endif
 
-   line->dx = v1[0][0] - v2[0][0];
-   line->dy = v1[0][1] - v2[0][1];
+   dx = v1[0][0] - v2[0][0];
+   dy = v1[0][1] - v2[0][1];
   
-/* X-MAJOR LINE */
-   if (fabsf(line->dx) >= fabsf(line->dy)) {
+   /* X-MAJOR LINE */
+   if (fabsf(dx) >= fabsf(dy)) {
+      float dydx = dy / dx;
 
       x1diff = v1[0][0] - (float) floor(v1[0][0]) - 0.5;
       y1diff = v1[0][1] - (float) floor(v1[0][1]) - 0.5;
       x2diff = v2[0][0] - (float) floor(v2[0][0]) - 0.5;
       y2diff = v2[0][1] - (float) floor(v2[0][1]) - 0.5;
 
-      if (y2diff==-0.5 && line->dy<0){
+      if (y2diff==-0.5 && dy<0){
          y2diff = 0.5;
       }
       
@@ -329,19 +330,16 @@ lp_setup_line( struct lp_setup_context *setup,
       if (fabsf(x1diff) + fabsf(y1diff) < 0.5) {
          draw_start = TRUE;
       }
-      else if (sign(x1diff) == sign(-line->dx)) {
+      else if (sign(x1diff) == sign(-dx)) {
          draw_start = FALSE;
       }
-      else if (sign(-y1diff) != sign(line->dy)) {
+      else if (sign(-y1diff) != sign(dy)) {
          draw_start = TRUE;
       }
       else {
          /* do intersection test */
-         float yintersect = v1[0][1] + x1diff*((float)line->dy/(float)line->dx);
-         if (yintersect < ceil(v1[0][1]) && yintersect > floor(v1[0][1])){
-            draw_start = TRUE;
-         }
-         else draw_start = FALSE;
+         float yintersect = fracf(v1[0][1]) + x1diff * dydx;
+         draw_start = (yintersect < 1.0 && yintersect > 0.0);
       }
 
 
@@ -351,101 +349,95 @@ lp_setup_line( struct lp_setup_context *setup,
       if (fabsf(x2diff) + fabsf(y2diff) < 0.5) {
          draw_end = FALSE;
       }
-      else if (sign(x2diff) != sign(-line->dx)) {
+      else if (sign(x2diff) != sign(-dx)) {
          draw_end = FALSE;
       }
-      else if (sign(-y2diff) == sign(line->dy)) {
+      else if (sign(-y2diff) == sign(dy)) {
          draw_end = TRUE;
       }
       else {
          /* do intersection test */
-         float yintersect = v2[0][1] + x2diff*((float)line->dy/(float)line->dx);
-         if (yintersect < ceil(v2[0][1]) && yintersect > floor(v2[0][1])){
-            draw_end = TRUE;
-         }
-         else draw_end = FALSE;
+         float yintersect = fracf(v2[0][1]) + x2diff * dydx;
+         draw_end = (yintersect < 1.0 && yintersect > 0.0);
       }
 
       /* Are we already drawing start/end?
        */
-      will_draw_start = sign(-x1diff) != sign(line->dx);
-      will_draw_end = (sign(x2diff) == sign(-line->dx)) || x2diff==0;
+      will_draw_start = sign(-x1diff) != sign(dx);
+      will_draw_end = (sign(x2diff) == sign(-dx)) || x2diff==0;
 
-      if (line->dx < 0) {
+      if (dx < 0) {
          /* if v2 is to the right of v1, swap pointers */
          const float (*temp)[4] = v1;
          v1 = v2;
          v2 = temp;
-         line->dx = -line->dx;
-         line->dy = -line->dy;
+         dx = -dx;
+         dy = -dy;
          /* Otherwise shift planes appropriately */
          if (will_draw_start != draw_start) {
-            xdiamond_offset_end = - x1diff - 0.5;
-            ydiamond_offset_end = xdiamond_offset_end*(float)line->dy/(float)line->dx;
+            x_offset_end = - x1diff - 0.5;
+            y_offset_end = x_offset_end * dydx;
 
          }
          if (will_draw_end != draw_end) {
-            xdiamond_offset = - x2diff - 0.5;
-            ydiamond_offset = xdiamond_offset*(float)line->dy/(float)line->dx;
+            x_offset = - x2diff - 0.5;
+            y_offset = x_offset * dydx;
          }
 
       }
       else{
          /* Otherwise shift planes appropriately */
          if (will_draw_start != draw_start) {
-            xdiamond_offset = - x1diff + 0.5;
-            ydiamond_offset = xdiamond_offset*(float)line->dy/(float)line->dx;
+            x_offset = - x1diff + 0.5;
+            y_offset = x_offset * dydx;
          }
          if (will_draw_end != draw_end) {
-            xdiamond_offset_end = - x2diff + 0.5;
-            ydiamond_offset_end = xdiamond_offset_end*(float)line->dy/(float)line->dx;
+            x_offset_end = - x2diff + 0.5;
+            y_offset_end = x_offset_end * dydx;
          }
       }
   
       /* x/y positions in fixed point */
-      x[0] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset);
-      x[1] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset);
-      x[2] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset);
-      x[3] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset);
+      x[0] = subpixel_snap(v1[0][0] + x_offset     - setup->pixel_offset);
+      x[1] = subpixel_snap(v2[0][0] + x_offset_end - setup->pixel_offset);
+      x[2] = subpixel_snap(v2[0][0] + x_offset_end - setup->pixel_offset);
+      x[3] = subpixel_snap(v1[0][0] + x_offset     - setup->pixel_offset);
       
-      y[0] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset) - fixed_width/2;
-      y[1] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset) - fixed_width/2;
-      y[2] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset) + fixed_width/2;
-      y[3] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset) + fixed_width/2;
+      y[0] = subpixel_snap(v1[0][1] + y_offset     - setup->pixel_offset) - fixed_width/2;
+      y[1] = subpixel_snap(v2[0][1] + y_offset_end - setup->pixel_offset) - fixed_width/2;
+      y[2] = subpixel_snap(v2[0][1] + y_offset_end - setup->pixel_offset) + fixed_width/2;
+      y[3] = subpixel_snap(v1[0][1] + y_offset     - setup->pixel_offset) + fixed_width/2;
       
    }
+   else {
+      const float dxdy = dx / dy;
 
-
-   else{
-/* Y-MAJOR LINE */      
+      /* Y-MAJOR LINE */      
       x1diff = v1[0][0] - (float) floor(v1[0][0]) - 0.5;
       y1diff = v1[0][1] - (float) floor(v1[0][1]) - 0.5;
       x2diff = v2[0][0] - (float) floor(v2[0][0]) - 0.5;
       y2diff = v2[0][1] - (float) floor(v2[0][1]) - 0.5;
 
-      if (x2diff==-0.5 && line->dx<0){
+      if (x2diff==-0.5 && dx<0) {
          x2diff = 0.5;
       }
 
-/* 
- * Diamond exit rule test for starting point 
- */    
+      /* 
+       * Diamond exit rule test for starting point 
+       */    
       if (fabsf(x1diff) + fabsf(y1diff) < 0.5) {
          draw_start = TRUE;
       }
-      else if (sign(-y1diff) == sign(line->dy)) {
+      else if (sign(-y1diff) == sign(dy)) {
          draw_start = FALSE;
       }
-      else if (sign(x1diff) != sign(-line->dx)) {
+      else if (sign(x1diff) != sign(-dx)) {
          draw_start = TRUE;
       }
       else {
          /* do intersection test */
-         float xintersect = v1[0][0] + y1diff*((float)line->dx/(float)line->dy);
-         if (xintersect < ceil(v1[0][0]) && xintersect > floor(v1[0][0])){
-            draw_start = TRUE;
-         }
-         else draw_start = FALSE;
+         float xintersect = fracf(v1[0][0]) + y1diff * dxdy;
+         draw_start = (xintersect < 1.0 && xintersect > 0.0);
       }
 
       /* 
@@ -454,82 +446,67 @@ lp_setup_line( struct lp_setup_context *setup,
       if (fabsf(x2diff) + fabsf(y2diff) < 0.5) {
          draw_end = FALSE;
       }
-      else if (sign(-y2diff) != sign(line->dy) ) {
+      else if (sign(-y2diff) != sign(dy) ) {
          draw_end = FALSE;
       }
-      else if (sign(x2diff) == sign(-line->dx) ) {
+      else if (sign(x2diff) == sign(-dx) ) {
          draw_end = TRUE;
       }
       else {
          /* do intersection test */
-         float xintersect = v2[0][0] + y2diff*((float)line->dx/(float)line->dy);
-         if (xintersect < ceil(v2[0][0]) && xintersect > floor(v2[0][0])){
-            draw_end = TRUE;
-         }
-         else draw_end = FALSE;
+         float xintersect = fracf(v2[0][0]) + y2diff * dxdy;
+         draw_end = (xintersect < 1.0 && xintersect > 0.0);
       }
 
       /* Are we already drawing start/end?
        */
-      will_draw_start = sign(y1diff) == sign(line->dy);
-      will_draw_end = (sign(-y2diff) == sign(line->dy)) || y2diff==0;
+      will_draw_start = sign(y1diff) == sign(dy);
+      will_draw_end = (sign(-y2diff) == sign(dy)) || y2diff==0;
 
-      if (line->dy > 0) {
+      if (dy > 0) {
          /* if v2 is on top of v1, swap pointers */
          const float (*temp)[4] = v1;
          v1 = v2;
          v2 = temp; 
-         line->dx = -line->dx;
-         line->dy = -line->dy;
+         dx = -dx;
+         dy = -dy;
 
          /* Otherwise shift planes appropriately */
          if (will_draw_start != draw_start) {
-            ydiamond_offset_end = - y1diff + 0.5;
-            xdiamond_offset_end = ydiamond_offset_end*(float)line->dx/(float)line->dy;
+            y_offset_end = - y1diff + 0.5;
+            x_offset_end = y_offset_end * dxdy;
          }
          if (will_draw_end != draw_end) {
-            ydiamond_offset = - y2diff + 0.5;
-            xdiamond_offset = ydiamond_offset*(float)line->dx/(float)line->dy;
+            y_offset = - y2diff + 0.5;
+            x_offset = y_offset * dxdy;
          }
       }
-
-      else{
+      else {
          /* Otherwise shift planes appropriately */
          if (will_draw_start != draw_start) {
-            ydiamond_offset = - y1diff - 0.5;
-            xdiamond_offset = ydiamond_offset*(float)line->dx/(float)line->dy;
+            y_offset = - y1diff - 0.5;
+            x_offset = y_offset * dxdy;
                      
          }
          if (will_draw_end != draw_end) {
-            ydiamond_offset_end = - y2diff - 0.5;
-            xdiamond_offset_end = ydiamond_offset_end*(float)line->dx/(float)line->dy;
+            y_offset_end = - y2diff - 0.5;
+            x_offset_end = y_offset_end * dxdy;
          }
       }
  
       /* x/y positions in fixed point */
-      x[0] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset) - fixed_width/2;
-      x[1] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset) - fixed_width/2;
-      x[2] = subpixel_snap(v2[0][0] + xdiamond_offset_end - setup->pixel_offset) + fixed_width/2;
-      x[3] = subpixel_snap(v1[0][0] + xdiamond_offset - setup->pixel_offset) + fixed_width/2;
+      x[0] = subpixel_snap(v1[0][0] + x_offset     - setup->pixel_offset) - fixed_width/2;
+      x[1] = subpixel_snap(v2[0][0] + x_offset_end - setup->pixel_offset) - fixed_width/2;
+      x[2] = subpixel_snap(v2[0][0] + x_offset_end - setup->pixel_offset) + fixed_width/2;
+      x[3] = subpixel_snap(v1[0][0] + x_offset     - setup->pixel_offset) + fixed_width/2;
      
-      y[0] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset); 
-      y[1] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset);
-      y[2] = subpixel_snap(v2[0][1] + ydiamond_offset_end - setup->pixel_offset);
-      y[3] = subpixel_snap(v1[0][1] + ydiamond_offset - setup->pixel_offset);
+      y[0] = subpixel_snap(v1[0][1] + y_offset     - setup->pixel_offset); 
+      y[1] = subpixel_snap(v2[0][1] + y_offset_end - setup->pixel_offset);
+      y[2] = subpixel_snap(v2[0][1] + y_offset_end - setup->pixel_offset);
+      y[3] = subpixel_snap(v1[0][1] + y_offset     - setup->pixel_offset);
    }
 
 
-   /* calculate the deltas */
-   line->plane[0].dcdy = x[0] - x[1];
-   line->plane[1].dcdy = x[1] - x[2];
-   line->plane[2].dcdy = x[2] - x[3];
-   line->plane[3].dcdy = x[3] - x[0];
-
-   line->plane[0].dcdx = y[0] - y[1];
-   line->plane[1].dcdx = y[1] - y[2];
-   line->plane[2].dcdx = y[2] - y[3];
-   line->plane[3].dcdx = y[3] - y[0];
-
 
    LP_COUNT(nr_tris);
 
@@ -543,37 +520,70 @@ lp_setup_line( struct lp_setup_context *setup,
        */
       int adj = (setup->pixel_offset != 0) ? 1 : 0;
 
-      minx = (MIN4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      maxx = (MAX4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      miny = (MIN4(y[0], y[1], y[2], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
-      maxy = (MAX4(y[0], y[1], y[2], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.x0 = (MIN4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.x1 = (MAX4(x[0], x[1], x[2], x[3]) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.y0 = (MIN4(y[0], y[1], y[2], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.y1 = (MAX4(y[0], y[1], y[2], y[3]) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+
+      /* Inclusive coordinates:
+       */
+      bbox.x1--;
+      bbox.y1--;
    }
 
-   if (setup->scissor_test) {
-      minx = MAX2(minx, setup->scissor.current.minx);
-      maxx = MIN2(maxx, setup->scissor.current.maxx);
-      miny = MAX2(miny, setup->scissor.current.miny);
-      maxy = MIN2(maxy, setup->scissor.current.maxy);
+   if (bbox.x1 < bbox.x0 ||
+       bbox.y1 < bbox.y0) {
+      if (0) debug_printf("empty bounding box\n");
+      LP_COUNT(nr_culled_tris);
+      return;
    }
-   else {
-      minx = MAX2(minx, 0);
-      miny = MAX2(miny, 0);
-      maxx = MIN2(maxx, scene->fb.width);
-      maxy = MIN2(maxy, scene->fb.height);
+
+   if (!u_rect_test_intersection(&setup->draw_region, &bbox)) {
+      if (0) debug_printf("offscreen\n");
+      LP_COUNT(nr_culled_tris);
+      return;
    }
 
+   u_rect_find_intersection(&setup->draw_region, &bbox);
 
-   if (miny >= maxy || minx >= maxx) {
-      lp_scene_putback_data( scene, tri_bytes );
+   line = lp_setup_alloc_triangle(scene,
+                                  setup->fs.nr_inputs,
+                                  nr_planes,
+                                  &tri_bytes);
+   if (!line)
       return;
-   }
 
-   oneoverarea = 1.0f / (line->dx * line->dx  + line->dy * line->dy);    
+#ifdef DEBUG
+   line->v[0][0] = v1[0][0];
+   line->v[1][0] = v2[0][0];   
+   line->v[0][1] = v1[0][1];
+   line->v[1][1] = v2[0][1];
+#endif
+
+   line->dx = dx;
+   line->dy = dy;
+
+   /* calculate the deltas */
+   line->plane[0].dcdy = x[0] - x[1];
+   line->plane[1].dcdy = x[1] - x[2];
+   line->plane[2].dcdy = x[2] - x[3];
+   line->plane[3].dcdy = x[3] - x[0];
+
+   line->plane[0].dcdx = y[0] - y[1];
+   line->plane[1].dcdx = y[1] - y[2];
+   line->plane[2].dcdx = y[2] - y[3];
+   line->plane[3].dcdx = y[3] - y[0];
+
+
+   oneoverarea = 1.0f / (dx * dx  + dy * dy);    
 
    /* Setup parameter interpolants:
     */
    setup_line_coefficients( setup, line, oneoverarea, v1, v2); 
 
+   line->inputs.facing = 1.0F;
+   line->inputs.state = setup->fs.stored;
+
    for (i = 0; i < 4; i++) {
       struct lp_rast_plane *plane = &line->plane[i];
 
@@ -628,35 +638,6 @@ lp_setup_line( struct lp_setup_context *setup,
       /* Calculate trivial accept offsets from the above.
        */
       plane->ei = plane->dcdy - plane->dcdx - plane->eo;
-
-      plane->step = line->step[i];
-
-      /* Fill in the inputs.step[][] arrays.
-       * We've manually unrolled some loops here.
-       */
-#define SETUP_STEP(j, x, y) \
-      line->step[i][j] = y * plane->dcdy - x * plane->dcdx                                     
-      
-      SETUP_STEP(0, 0, 0);
-      SETUP_STEP(1, 1, 0);
-      SETUP_STEP(2, 0, 1);
-      SETUP_STEP(3, 1, 1);
-
-      SETUP_STEP(4, 2, 0);
-      SETUP_STEP(5, 3, 0);
-      SETUP_STEP(6, 2, 1);
-      SETUP_STEP(7, 3, 1);
-
-      SETUP_STEP(8, 0, 2);
-      SETUP_STEP(9, 1, 2);
-      SETUP_STEP(10, 0, 3);
-      SETUP_STEP(11, 1, 3);
-
-      SETUP_STEP(12, 2, 2);
-      SETUP_STEP(13, 3, 2);
-      SETUP_STEP(14, 2, 3);
-      SETUP_STEP(15, 3, 3);
-#undef STEP
    }
 
 
@@ -679,154 +660,34 @@ lp_setup_line( struct lp_setup_context *setup,
     * these planes elsewhere.
     */
    if (nr_planes == 8) {
-      line->plane[4].step = step_scissor_maxx;
-      line->plane[4].dcdx = 1;
+      line->plane[4].dcdx = -1;
       line->plane[4].dcdy = 0;
-      line->plane[4].c = maxx;
-      line->plane[4].ei = -1;
-      line->plane[4].eo = 0;
-
-      line->plane[5].step = step_scissor_miny;
-      line->plane[5].dcdx = 0;
-      line->plane[5].dcdy = 1;
-      line->plane[5].c = 1-miny;
-      line->plane[5].ei = 0;
-      line->plane[5].eo = 1;
-
-      line->plane[6].step = step_scissor_maxy;
-      line->plane[6].dcdx = 0;
-      line->plane[6].dcdy = -1;
-      line->plane[6].c = maxy;
-      line->plane[6].ei = -1;
-      line->plane[6].eo = 0;
-
-      line->plane[7].step = step_scissor_minx;
-      line->plane[7].dcdx = -1;
-      line->plane[7].dcdy = 0;
-      line->plane[7].c = 1-minx;
-      line->plane[7].ei = 0;
-      line->plane[7].eo = 1;
-   }
-
+      line->plane[4].c = 1-bbox.x0;
+      line->plane[4].ei = 0;
+      line->plane[4].eo = 1;
 
-   /*
-    * All fields of 'line' are now set.  The remaining code here is
-    * concerned with binning.
-    */
+      line->plane[5].dcdx = 1;
+      line->plane[5].dcdy = 0;
+      line->plane[5].c = bbox.x1+1;
+      line->plane[5].ei = -1;
+      line->plane[5].eo = 0;
 
-   /* Convert to tile coordinates, and inclusive ranges:
-    */
-   ix0 = minx / TILE_SIZE;
-   iy0 = miny / TILE_SIZE;
-   ix1 = (maxx-1) / TILE_SIZE;
-   iy1 = (maxy-1) / TILE_SIZE;
-
-   /*
-    * Clamp to framebuffer size
-    */
-   assert(ix0 == MAX2(ix0, 0));
-   assert(iy0 == MAX2(iy0, 0));
-   assert(ix1 == MIN2(ix1, scene->tiles_x - 1));
-   assert(iy1 == MIN2(iy1, scene->tiles_y - 1));
-
-   /* Determine which tile(s) intersect the triangle's bounding box
-    */
-   if (iy0 == iy1 && ix0 == ix1)
-   {
-      /* Triangle is contained in a single tile:
-       */
-      lp_scene_bin_command( scene, ix0, iy0,
-                            lp_rast_tri_tab[nr_planes], 
-                            lp_rast_arg_triangle(line, (1<<nr_planes)-1) );
+      line->plane[6].dcdx = 0;
+      line->plane[6].dcdy = 1;
+      line->plane[6].c = 1-bbox.y0;
+      line->plane[6].ei = 0;
+      line->plane[6].eo = 1;
+
+      line->plane[7].dcdx = 0;
+      line->plane[7].dcdy = -1;
+      line->plane[7].c = bbox.y1+1;
+      line->plane[7].ei = -1;
+      line->plane[7].eo = 0;
    }
-   else
-   {
-      int c[8];
-      int ei[8];
-      int eo[8];
-      int xstep[8];
-      int ystep[8];
-      int x, y;
-      int is_blit = -1; /* undetermined */
-      
-      for (i = 0; i < nr_planes; i++) {
-         c[i] = (line->plane[i].c + 
-                 line->plane[i].dcdy * iy0 * TILE_SIZE - 
-                 line->plane[i].dcdx * ix0 * TILE_SIZE);
-
-         ei[i] = line->plane[i].ei << TILE_ORDER;
-         eo[i] = line->plane[i].eo << TILE_ORDER;
-         xstep[i] = -(line->plane[i].dcdx << TILE_ORDER);
-         ystep[i] = line->plane[i].dcdy << TILE_ORDER;
-      }
-
 
-
-      /* Test tile-sized blocks against the triangle.
-       * Discard blocks fully outside the tri.  If the block is fully
-       * contained inside the tri, bin an lp_rast_shade_tile command.
-       * Else, bin a lp_rast_triangle command.
-       */
-      for (y = iy0; y <= iy1; y++)
-      {
-         boolean in = FALSE;  /* are we inside the triangle? */
-         int cx[8];
-
-         for (i = 0; i < nr_planes; i++)
-            cx[i] = c[i];
-
-         for (x = ix0; x <= ix1; x++)
-         {
-            int out = 0;
-            int partial = 0;
-
-            for (i = 0; i < nr_planes; i++) {
-               int planeout = cx[i] + eo[i];
-               int planepartial = cx[i] + ei[i] - 1;
-               out |= (planeout >> 31);
-               partial |= (planepartial >> 31) & (1<<i);      
-            }
-            if (out) {
-               /* do nothing */
-               if (in)
-                  break;  /* exiting triangle, all done with this row */
-               LP_COUNT(nr_empty_64);
-            }
-            else if (partial) {
-               /* Not trivially accepted by at least one plane - 
-                * rasterize/shade partial tile
-                */
-               int count = util_bitcount(partial);
-               in = TRUE;
-               lp_scene_bin_command( scene, x, y,
-                                     lp_rast_tri_tab[count], 
-                                     lp_rast_arg_triangle(line, partial) );
-
-               LP_COUNT(nr_partially_covered_64);
-            }
-            else {
-               /* triangle covers the whole tile- shade whole tile */
-               LP_COUNT(nr_fully_covered_64);
-               in = TRUE;
-               /* leverages on existing code in lp_setup_tri.c */ 
-               do_triangle_ccw_whole_tile(setup, scene, line, x, y,
-                                          opaque, &is_blit);
-            }
-
-            /* Iterate cx values across the region:
-             */
-            for (i = 0; i < nr_planes; i++)
-               cx[i] += xstep[i];
-         }
-      
-         /* Iterate c values down the region:
-          */
-         for (i = 0; i < nr_planes; i++)
-            c[i] += ystep[i];
-      }
-   }
+   lp_setup_bin_triangle(setup, line, &bbox, nr_planes);
 }
-
+   
 
 void lp_setup_choose_line( struct lp_setup_context *setup ) 
 { 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index 212bb3ab90..0180d95090 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -184,9 +184,7 @@ do_triangle_ccw(struct lp_setup_context *setup,
 		const float (*v2)[4],
 		boolean frontfacing )
 {
-
    struct lp_scene *scene = lp_setup_get_current_scene(setup);
-   struct lp_fragment_shader_variant *variant = setup->fs.current.variant;
    struct lp_rast_triangle *tri;
    int x[3];
    int y[3];
@@ -196,7 +194,6 @@ do_triangle_ccw(struct lp_setup_context *setup,
    struct lp_tri_info info;
    int area;
    struct u_rect bbox;
-   int ix0, ix1, iy0, iy1;
    unsigned tri_bytes;
    int i;
    int nr_planes = 3;
@@ -423,6 +420,20 @@ do_triangle_ccw(struct lp_setup_context *setup,
       tri->plane[6].eo = 0;
    }
 
+   lp_setup_bin_triangle( setup, tri, &bbox, nr_planes );
+}
+
+
+void
+lp_setup_bin_triangle( struct lp_setup_context *setup,
+                       struct lp_rast_triangle *tri,
+                       const struct u_rect *bbox,
+                       int nr_planes )
+{
+   struct lp_scene *scene = setup->scene;
+   struct lp_fragment_shader_variant *variant = setup->fs.current.variant;
+   int ix0, ix1, iy0, iy1;
+   int i;
 
    /*
     * All fields of 'tri' are now set.  The remaining code here is
@@ -432,10 +443,10 @@ do_triangle_ccw(struct lp_setup_context *setup,
    /* Convert to tile coordinates, and inclusive ranges:
     */
    if (nr_planes == 3) {
-      int ix0 = bbox.x0 / 16;
-      int iy0 = bbox.y0 / 16;
-      int ix1 = bbox.x1 / 16;
-      int iy1 = bbox.y1 / 16;
+      int ix0 = bbox->x0 / 16;
+      int iy0 = bbox->y0 / 16;
+      int ix1 = bbox->x1 / 16;
+      int iy1 = bbox->y1 / 16;
       
       if (iy0 == iy1 && ix0 == ix1)
       {
@@ -451,10 +462,10 @@ do_triangle_ccw(struct lp_setup_context *setup,
       }
    }
 
-   ix0 = bbox.x0 / TILE_SIZE;
-   iy0 = bbox.y0 / TILE_SIZE;
-   ix1 = bbox.x1 / TILE_SIZE;
-   iy1 = bbox.y1 / TILE_SIZE;
+   ix0 = bbox->x0 / TILE_SIZE;
+   iy0 = bbox->y0 / TILE_SIZE;
+   ix1 = bbox->x1 / TILE_SIZE;
+   iy1 = bbox->y1 / TILE_SIZE;
 
    /*
     * Clamp to framebuffer size
-- 
cgit v1.2.3


From 57d84d9ca4a645ca326b66ff3b82bee0db18ac97 Mon Sep 17 00:00:00 2001
From: Hui Qi Tay <hqtay@vmware.com>
Date: Fri, 27 Aug 2010 10:37:09 +0100
Subject: llvmpipe: native point rasterization

Conflicts:

	src/gallium/drivers/llvmpipe/lp_setup_context.h
	src/gallium/drivers/llvmpipe/lp_setup_line.c
	src/gallium/drivers/llvmpipe/lp_setup_tri.c
---
 src/gallium/drivers/llvmpipe/lp_context.c          |   6 +-
 src/gallium/drivers/llvmpipe/lp_context.h          |   3 +
 src/gallium/drivers/llvmpipe/lp_setup.c            |  15 ++
 src/gallium/drivers/llvmpipe/lp_setup.h            |   4 +
 src/gallium/drivers/llvmpipe/lp_setup_context.h    |   2 +
 src/gallium/drivers/llvmpipe/lp_setup_point.c      | 225 ++++++++++++++++++++-
 src/gallium/drivers/llvmpipe/lp_state_derived.c    |  10 +
 src/gallium/drivers/llvmpipe/lp_state_rasterizer.c |   2 +
 8 files changed, 262 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_context.c b/src/gallium/drivers/llvmpipe/lp_context.c
index a6873abbee..c52b17b298 100644
--- a/src/gallium/drivers/llvmpipe/lp_context.c
+++ b/src/gallium/drivers/llvmpipe/lp_context.c
@@ -155,8 +155,10 @@ llvmpipe_create_context( struct pipe_screen *screen, void *priv )
    draw_install_aapoint_stage(llvmpipe->draw, &llvmpipe->pipe);
    draw_install_pstipple_stage(llvmpipe->draw, &llvmpipe->pipe);
 
-   /* convert points and lines into triangles: */
-   draw_wide_point_threshold(llvmpipe->draw, 0.0);
+   /* convert points and lines into triangles: 
+    * (otherwise, draw points and lines natively)
+    */
+   draw_wide_point_threshold(llvmpipe->draw, 10000.0);
    draw_wide_line_threshold(llvmpipe->draw, 10000.0);
 
 #if USE_DRAW_STAGE_PSTIPPLE
diff --git a/src/gallium/drivers/llvmpipe/lp_context.h b/src/gallium/drivers/llvmpipe/lp_context.h
index 50f9091c3c..34fa20e204 100644
--- a/src/gallium/drivers/llvmpipe/lp_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_context.h
@@ -101,6 +101,9 @@ struct llvmpipe_context {
    
    /** Vertex format */
    struct vertex_info vertex_info;
+   
+   /** Which vertex shader output slot contains point size */
+   int psize_slot;
 
    /** Fragment shader input interpolation info */
    unsigned num_inputs;
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c
index 4c8275665e..778bfb4f6e 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup.c
@@ -494,6 +494,15 @@ lp_setup_set_line_state( struct lp_setup_context *setup,
    setup->line_width = line_width;
 }
 
+void 
+lp_setup_set_point_state( struct lp_setup_context *setup,
+                          float point_size)
+{
+   LP_DBG(DEBUG_SETUP, "%s\n", __FUNCTION__);
+
+   setup->point_size = point_size;
+}
+
 void
 lp_setup_set_fs_inputs( struct lp_setup_context *setup,
                         const struct lp_shader_input *input,
@@ -733,6 +742,12 @@ lp_setup_update_state( struct lp_setup_context *setup )
     */
    {
       struct llvmpipe_context *lp = llvmpipe_context(scene->pipe);
+
+      /* Will probably need to move this somewhere else, just need  
+       * to know about vertex shader point size attribute.
+       */
+      setup->psize = lp->psize_slot;
+
       if (lp->dirty) {
          llvmpipe_update_derived(lp);
       }
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.h b/src/gallium/drivers/llvmpipe/lp_setup.h
index 693550b8c8..6b041e7071 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup.h
@@ -104,6 +104,10 @@ void
 lp_setup_set_line_state( struct lp_setup_context *setup,
                          float line_width);
 
+void 
+lp_setup_set_point_state( struct lp_setup_context *setup,
+                          float point_size);
+
 void
 lp_setup_set_fs_inputs( struct lp_setup_context *setup,
                         const struct lp_shader_input *interp,
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_context.h b/src/gallium/drivers/llvmpipe/lp_setup_context.h
index 97919c09d4..7d486afbbf 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup_context.h
@@ -92,6 +92,8 @@ struct lp_setup_context
    unsigned cullmode;
    float pixel_offset;
    float line_width;
+   float point_size;
+   float psize;
 
    struct pipe_framebuffer_state fb;
    struct u_rect framebuffer;
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_point.c b/src/gallium/drivers/llvmpipe/lp_setup_point.c
index 709c3e2fd2..07a28fc6e3 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_point.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_point.c
@@ -1,6 +1,6 @@
 /**************************************************************************
  *
- * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * Copyright 2010, VMware Inc.
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -18,7 +18,7 @@
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -30,10 +30,229 @@
  */
 
 #include "lp_setup_context.h"
+#include "util/u_math.h"
+#include "util/u_memory.h"
+#include "lp_perf.h"
+#include "lp_setup_context.h"
+#include "lp_rast.h"
+#include "lp_state_fs.h"
+
+#define NUM_CHANNELS 4
+
+struct point_info {
+   /* x,y deltas */
+   int dy01, dy12;
+   int dx01, dx12;
+
+   const float (*v0)[4];
+};   
+
+
+/**
+ * Compute a0 for a constant-valued coefficient (GL_FLAT shading).
+ */
+static void constant_coef( struct lp_setup_context *setup,
+                           struct lp_rast_triangle *point,
+                           unsigned slot,
+                           const float value,
+                           unsigned i )
+{
+   point->inputs.a0[slot][i] = value;
+   point->inputs.dadx[slot][i] = 0.0f;
+   point->inputs.dady[slot][i] = 0.0f;
+}
+
+/**
+ * Special coefficient setup for gl_FragCoord.
+ * X and Y are trivial
+ * Z and W are copied from position_coef which should have already been computed.
+ * We could do a bit less work if we'd examine gl_FragCoord's swizzle mask.
+ */
+static void
+setup_point_fragcoord_coef(struct lp_setup_context *setup,
+                           struct lp_rast_triangle *point,
+                           const struct point_info *info,
+                           unsigned slot,
+                           unsigned usage_mask)
+{
+   /*X*/
+   if (usage_mask & TGSI_WRITEMASK_X) {
+      point->inputs.a0[slot][0] = 0.0;
+      point->inputs.dadx[slot][0] = 1.0;
+      point->inputs.dady[slot][0] = 0.0;
+   }
+
+   /*Y*/
+   if (usage_mask & TGSI_WRITEMASK_Y) {
+      point->inputs.a0[slot][1] = 0.0;
+      point->inputs.dadx[slot][1] = 0.0;
+      point->inputs.dady[slot][1] = 1.0;
+   }
+
+   /*Z*/
+   if (usage_mask & TGSI_WRITEMASK_Z) {
+      constant_coef(setup, point, slot, info->v0[0][2], 2);
+   }
+
+   /*W*/
+   if (usage_mask & TGSI_WRITEMASK_W) {
+      constant_coef(setup, point, slot, info->v0[0][3], 3);
+   }
+}
+
+/**
+ * Compute the point->coef[] array dadx, dady, a0 values.
+ */
+static void   
+setup_point_coefficients( struct lp_setup_context *setup,
+                          struct lp_rast_triangle *point,
+                          const struct point_info *info)
+{
+   unsigned fragcoord_usage_mask = TGSI_WRITEMASK_XYZ;
+   unsigned slot;
+
+   /* setup interpolation for all the remaining attributes:
+    */
+   for (slot = 0; slot < setup->fs.nr_inputs; slot++) {
+      unsigned vert_attr = setup->fs.input[slot].src_index;
+      unsigned usage_mask = setup->fs.input[slot].usage_mask;
+      unsigned i;
+      
+      switch (setup->fs.input[slot].interp) {
+      case LP_INTERP_POSITION:
+         /*
+          * The generated pixel interpolators will pick up the coeffs from
+          * slot 0, so all need to ensure that the usage mask is covers all
+          * usages.
+          */
+         fragcoord_usage_mask |= usage_mask;
+         break;
+
+      default:
+         for (i = 0; i < NUM_CHANNELS; i++) {
+            if (usage_mask & (1 << i))
+               constant_coef(setup, point, slot+1, info->v0[vert_attr][i], i);
+         }
+      }
+   }
+
+   /* The internal position input is in slot zero:
+    */
+   setup_point_fragcoord_coef(setup, point, info, 0,
+                              fragcoord_usage_mask);
+}
+
+static INLINE int
+subpixel_snap(float a)
+{
+   return util_iround(FIXED_ONE * a);
+}
+
 
 static void lp_setup_point( struct lp_setup_context *setup,
-                       const float (*v0)[4] )
+                            const float (*v0)[4] )
 {
+   /* x/y positions in fixed point */
+   const int sizeAttr = setup->psize;
+   const float size
+      = sizeAttr > 0 ? v0[sizeAttr][0]
+      : setup->point_size;
+   const float half_width = 0.5F * size;
+ 
+   const int x0 = subpixel_snap(v0[0][0] - half_width - setup->pixel_offset);
+   const int x1 = subpixel_snap(v0[0][0] - half_width - setup->pixel_offset);
+   const int x2 = subpixel_snap(v0[0][0] + half_width - setup->pixel_offset);
+   const int y0 = subpixel_snap(v0[0][1] - half_width - setup->pixel_offset);
+   const int y1 = subpixel_snap(v0[0][1] + half_width - setup->pixel_offset);
+   const int y2 = subpixel_snap(v0[0][1] + half_width - setup->pixel_offset);
+   struct lp_scene *scene = lp_setup_get_current_scene(setup);
+   struct lp_rast_triangle *point;
+   unsigned bytes;
+   struct u_rect bbox;
+   unsigned nr_planes = 4;
+   struct point_info info;
+
+
+   /* Bounding rectangle (in pixels) */
+   {
+      /* Yes this is necessary to accurately calculate bounding boxes
+       * with the two fill-conventions we support.  GL (normally) ends
+       * up needing a bottom-left fill convention, which requires
+       * slightly different rounding.
+       */
+      int adj = (setup->pixel_offset != 0) ? 1 : 0;
+
+      bbox.x0 = (MIN3(x0, x1, x2) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.x1 = (MAX3(x0, x1, x2) + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.y0 = (MIN3(y0, y1, y2) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.y1 = (MAX3(y0, y1, y2) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+
+      /* Inclusive coordinates:
+       */
+      bbox.x1--;
+      bbox.y1--;
+   }
+   
+   if (!u_rect_test_intersection(&setup->draw_region, &bbox)) {
+      if (0) debug_printf("offscreen\n");
+      LP_COUNT(nr_culled_tris);
+      return;
+   }
+
+   u_rect_find_intersection(&setup->draw_region, &bbox);
+
+   point = lp_setup_alloc_triangle(scene,
+                                   setup->fs.nr_inputs,
+                                   nr_planes,
+                                   &bytes);
+   if (!point)
+      return;
+
+#ifdef DEBUG
+   point->v[0][0] = v0[0][0];
+   point->v[0][1] = v0[0][1];
+#endif
+
+   info.v0 = v0;
+   info.dx01 = x1 - x0;
+   info.dx12 = x2 - x1;
+   info.dy01 = y1 - y0;
+   info.dy12 = y2 - y1;
+   
+   /* Setup parameter interpolants:
+    */
+   setup_point_coefficients(setup, point, &info);
+
+   point->inputs.facing = 1.0F;
+   point->inputs.state = setup->fs.stored;
+
+   {
+      point->plane[0].dcdx = -1;
+      point->plane[0].dcdy = 0;
+      point->plane[0].c = 1-bbox.x0;
+      point->plane[0].ei = 0;
+      point->plane[0].eo = 1;
+
+      point->plane[1].dcdx = 1;
+      point->plane[1].dcdy = 0;
+      point->plane[1].c = bbox.x1+1;
+      point->plane[1].ei = -1;
+      point->plane[1].eo = 0;
+
+      point->plane[2].dcdx = 0;
+      point->plane[2].dcdy = 1;
+      point->plane[2].c = 1-bbox.y0;
+      point->plane[2].ei = 0;
+      point->plane[2].eo = 1;
+
+      point->plane[3].dcdx = 0;
+      point->plane[3].dcdy = -1;
+      point->plane[3].c = bbox.y1+1;
+      point->plane[3].ei = -1;
+      point->plane[3].eo = 0;
+   }
+
+   lp_setup_bin_triangle(setup, point, &bbox, nr_planes);
 }
 
 
diff --git a/src/gallium/drivers/llvmpipe/lp_state_derived.c b/src/gallium/drivers/llvmpipe/lp_state_derived.c
index 77bec4640b..9ef9983307 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_derived.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_derived.c
@@ -125,6 +125,16 @@ compute_vertex_info(struct llvmpipe_context *llvmpipe)
       inputs[i].src_index = vinfo->num_attribs;
       draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_PERSPECTIVE, vs_index);
    }
+
+   /* Figure out if we need pointsize as well.
+    */
+   llvmpipe->psize_slot = draw_find_shader_output(llvmpipe->draw,
+                                                  TGSI_SEMANTIC_PSIZE, 0);
+   if (llvmpipe->psize_slot > 0) {
+      draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_CONSTANT,
+                            llvmpipe->psize_slot);
+   }
+
    llvmpipe->num_inputs = lpfs->info.num_inputs;
 
    draw_compute_vertex_size(vinfo);
diff --git a/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c b/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
index 67b985aa24..f845a0c6e5 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
@@ -75,6 +75,8 @@ llvmpipe_bind_rasterizer_state(struct pipe_context *pipe, void *handle)
                    llvmpipe->rasterizer->flatshade_first);
       lp_setup_set_line_state( llvmpipe->setup,
                    llvmpipe->rasterizer->line_width);
+      lp_setup_set_point_state( llvmpipe->setup,
+                   llvmpipe->rasterizer->point_size);
    }
 
    llvmpipe->dirty |= LP_NEW_RASTERIZER;
-- 
cgit v1.2.3


From 2cd72dd4590b4510931854ed776c72563603f7ff Mon Sep 17 00:00:00 2001
From: Hui Qi Tay <hqtay@vmware.com>
Date: Fri, 27 Aug 2010 10:46:19 +0100
Subject: llvmpipe: native point rasterization with better pixel rasterization

A few subpixel_snap and fixed width changes.

Conflicts:

	src/gallium/drivers/llvmpipe/lp_setup_point.c
---
 src/gallium/drivers/llvmpipe/lp_setup_point.c | 34 ++++++++++++++-------------
 1 file changed, 18 insertions(+), 16 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup_point.c b/src/gallium/drivers/llvmpipe/lp_setup_point.c
index 07a28fc6e3..afbc816fb9 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_point.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_point.c
@@ -157,14 +157,16 @@ static void lp_setup_point( struct lp_setup_context *setup,
    const float size
       = sizeAttr > 0 ? v0[sizeAttr][0]
       : setup->point_size;
-   const float half_width = 0.5F * size;
- 
-   const int x0 = subpixel_snap(v0[0][0] - half_width - setup->pixel_offset);
-   const int x1 = subpixel_snap(v0[0][0] - half_width - setup->pixel_offset);
-   const int x2 = subpixel_snap(v0[0][0] + half_width - setup->pixel_offset);
-   const int y0 = subpixel_snap(v0[0][1] - half_width - setup->pixel_offset);
-   const int y1 = subpixel_snap(v0[0][1] + half_width - setup->pixel_offset);
-   const int y2 = subpixel_snap(v0[0][1] + half_width - setup->pixel_offset);
+   
+   /* Point size as fixed point integer, remove rounding errors 
+    * and gives minimum width for very small points
+    */
+   int fixed_width = MAX2(FIXED_ONE,
+                          (subpixel_snap(size) + FIXED_ONE/2 - 1) & ~(FIXED_ONE-1));
+
+   const int x0 = subpixel_snap(v0[0][0] - setup->pixel_offset) - fixed_width/2;
+   const int y0 = subpixel_snap(v0[0][1] - setup->pixel_offset) - fixed_width/2;
+     
    struct lp_scene *scene = lp_setup_get_current_scene(setup);
    struct lp_rast_triangle *point;
    unsigned bytes;
@@ -182,10 +184,10 @@ static void lp_setup_point( struct lp_setup_context *setup,
        */
       int adj = (setup->pixel_offset != 0) ? 1 : 0;
 
-      bbox.x0 = (MIN3(x0, x1, x2) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      bbox.x1 = (MAX3(x0, x1, x2) + (FIXED_ONE-1)) >> FIXED_ORDER;
-      bbox.y0 = (MIN3(y0, y1, y2) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
-      bbox.y1 = (MAX3(y0, y1, y2) + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.x0 = (x0 + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.x1 = (x0 + fixed_width + (FIXED_ONE-1) + adj) >> FIXED_ORDER;
+      bbox.y0 = (y0 + (FIXED_ONE-1)) >> FIXED_ORDER;
+      bbox.y1 = (y0 + fixed_width + (FIXED_ONE-1)) >> FIXED_ORDER;
 
       /* Inclusive coordinates:
        */
@@ -214,10 +216,10 @@ static void lp_setup_point( struct lp_setup_context *setup,
 #endif
 
    info.v0 = v0;
-   info.dx01 = x1 - x0;
-   info.dx12 = x2 - x1;
-   info.dy01 = y1 - y0;
-   info.dy12 = y2 - y1;
+   info.dx01 = 0;
+   info.dx12 = fixed_width;
+   info.dy01 = fixed_width;
+   info.dy12 = 0;
    
    /* Setup parameter interpolants:
     */
-- 
cgit v1.2.3


From 29ec116e8f21c65250f1083830b82ff59859496d Mon Sep 17 00:00:00 2001
From: Hui Qi Tay <hqtay@vmware.com>
Date: Tue, 10 Aug 2010 11:41:32 +0100
Subject: llvmpipe: point sprites rasterization

Point sprites now done in the rasterizer setup code instead of
going through the draw module.
---
 src/gallium/drivers/llvmpipe/lp_context.c          |  2 +
 src/gallium/drivers/llvmpipe/lp_setup.c            |  6 ++-
 src/gallium/drivers/llvmpipe/lp_setup.h            |  4 +-
 src/gallium/drivers/llvmpipe/lp_setup_context.h    |  2 +
 src/gallium/drivers/llvmpipe/lp_setup_point.c      | 63 +++++++++++++++++++++-
 src/gallium/drivers/llvmpipe/lp_state_derived.c    | 20 +++++--
 src/gallium/drivers/llvmpipe/lp_state_rasterizer.c |  6 ++-
 7 files changed, 93 insertions(+), 10 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_context.c b/src/gallium/drivers/llvmpipe/lp_context.c
index c52b17b298..39f2c6085e 100644
--- a/src/gallium/drivers/llvmpipe/lp_context.c
+++ b/src/gallium/drivers/llvmpipe/lp_context.c
@@ -158,6 +158,8 @@ llvmpipe_create_context( struct pipe_screen *screen, void *priv )
    /* convert points and lines into triangles: 
     * (otherwise, draw points and lines natively)
     */
+   draw_wide_point_sprites(llvmpipe->draw, FALSE);
+   draw_enable_point_sprites(llvmpipe->draw, FALSE);
    draw_wide_point_threshold(llvmpipe->draw, 10000.0);
    draw_wide_line_threshold(llvmpipe->draw, 10000.0);
 
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.c b/src/gallium/drivers/llvmpipe/lp_setup.c
index 778bfb4f6e..3da9097154 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup.c
@@ -496,11 +496,15 @@ lp_setup_set_line_state( struct lp_setup_context *setup,
 
 void 
 lp_setup_set_point_state( struct lp_setup_context *setup,
-                          float point_size)
+                          float point_size,                          
+                          boolean point_size_per_vertex,
+                          uint sprite)
 {
    LP_DBG(DEBUG_SETUP, "%s\n", __FUNCTION__);
 
    setup->point_size = point_size;
+   setup->sprite = sprite;
+   setup->point_size_per_vertex = point_size_per_vertex;
 }
 
 void
diff --git a/src/gallium/drivers/llvmpipe/lp_setup.h b/src/gallium/drivers/llvmpipe/lp_setup.h
index 6b041e7071..821ebb1087 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup.h
@@ -106,7 +106,9 @@ lp_setup_set_line_state( struct lp_setup_context *setup,
 
 void 
 lp_setup_set_point_state( struct lp_setup_context *setup,
-                          float point_size);
+                          float point_size,                          
+                          boolean point_size_per_vertex,
+                          uint sprite);
 
 void
 lp_setup_set_fs_inputs( struct lp_setup_context *setup,
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_context.h b/src/gallium/drivers/llvmpipe/lp_setup_context.h
index 7d486afbbf..877a492c6d 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_context.h
+++ b/src/gallium/drivers/llvmpipe/lp_setup_context.h
@@ -74,6 +74,7 @@ struct lp_setup_context
    uint prim;
    uint vertex_size;
    uint nr_vertices;
+   uint sprite;
    uint vertex_buffer_size;
    void *vertex_buffer;
 
@@ -89,6 +90,7 @@ struct lp_setup_context
    boolean flatshade_first;
    boolean ccw_is_frontface;
    boolean scissor_test;
+   boolean point_size_per_vertex;
    unsigned cullmode;
    float pixel_offset;
    float line_width;
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_point.c b/src/gallium/drivers/llvmpipe/lp_setup_point.c
index afbc816fb9..6ae318d328 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_point.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_point.c
@@ -36,6 +36,7 @@
 #include "lp_setup_context.h"
 #include "lp_rast.h"
 #include "lp_state_fs.h"
+#include "tgsi/tgsi_scan.h"
 
 #define NUM_CHANNELS 4
 
@@ -62,6 +63,49 @@ static void constant_coef( struct lp_setup_context *setup,
    point->inputs.dady[slot][i] = 0.0f;
 }
 
+static void perspective_coef( struct lp_setup_context *setup,
+                              struct lp_rast_triangle *point,
+                              const struct point_info *info,
+                              unsigned slot,
+                              unsigned vert_attr,
+                              unsigned i)
+{
+   if (i == 0) {   
+      float dadx = FIXED_ONE / (float)info->dx12;  
+      float dady =  0.0f;
+      point->inputs.dadx[slot][i] = dadx;
+      point->inputs.dady[slot][i] = dady;
+      point->inputs.a0[slot][i] = (0.5 -
+                                  (dadx * ((float)info->v0[0][0] - setup->pixel_offset) +
+                                   dady * ((float)info->v0[0][1] - setup->pixel_offset)));
+   }
+
+   else if (i == 1) {
+      float dadx =  0.0f; 
+      float dady =  FIXED_ONE / (float)info->dx12;
+   
+      point->inputs.dadx[slot][i] = dadx;
+      point->inputs.dady[slot][i] = dady;
+      point->inputs.a0[slot][i] = (0.5 -
+                                  (dadx * ((float)info->v0[0][0] - setup->pixel_offset) +
+                                   dady * ((float)info->v0[0][1] - setup->pixel_offset)));
+   }
+
+   else if (i == 2) {
+      point->inputs.a0[slot][i] = 0.0f;
+      point->inputs.dadx[slot][i] = 0.0f;
+      point->inputs.dady[slot][i] = 0.0f;
+   }
+      
+   else if (i == 3) {
+      point->inputs.a0[slot][i] = 1.0f;
+      point->inputs.dadx[slot][i] = 0.0f;
+      point->inputs.dady[slot][i] = 0.0f;
+   }
+
+}
+
+
 /**
  * Special coefficient setup for gl_FragCoord.
  * X and Y are trivial
@@ -128,6 +172,23 @@ setup_point_coefficients( struct lp_setup_context *setup,
          fragcoord_usage_mask |= usage_mask;
          break;
 
+      case LP_INTERP_PERSPECTIVE:
+         /* For point sprite textures */        
+         if (setup->fs.current.variant->shader->info.input_semantic_name[slot] 
+             == TGSI_SEMANTIC_GENERIC) 
+         {
+            int index = setup->fs.current.variant->shader->info.input_semantic_index[slot];
+            
+            if (setup->sprite & (1 << index)) {
+               for (i = 0; i < NUM_CHANNELS; i++)
+                  if (usage_mask & (1 << i))
+                     perspective_coef(setup, point, info, slot+1, vert_attr, i);
+               fragcoord_usage_mask |= TGSI_WRITEMASK_W;
+               break;                     
+            }
+         }
+
+         /* Otherwise fallthrough */
       default:
          for (i = 0; i < NUM_CHANNELS; i++) {
             if (usage_mask & (1 << i))
@@ -155,7 +216,7 @@ static void lp_setup_point( struct lp_setup_context *setup,
    /* x/y positions in fixed point */
    const int sizeAttr = setup->psize;
    const float size
-      = sizeAttr > 0 ? v0[sizeAttr][0]
+      = (setup->point_size_per_vertex && sizeAttr > 0) ? v0[sizeAttr][0]
       : setup->point_size;
    
    /* Point size as fixed point integer, remove rounding errors 
diff --git a/src/gallium/drivers/llvmpipe/lp_state_derived.c b/src/gallium/drivers/llvmpipe/lp_state_derived.c
index 9ef9983307..edd723f65f 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_derived.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_derived.c
@@ -74,6 +74,15 @@ compute_vertex_info(struct llvmpipe_context *llvmpipe)
       vs_index = draw_find_shader_output(llvmpipe->draw,
                                          lpfs->info.input_semantic_name[i],
                                          lpfs->info.input_semantic_index[i]);
+      if (vs_index < 0) {
+         /*
+          * This can happen with sprite coordinates - the vertex
+          * shader doesn't need to provide an output as we generate
+          * them internally.  However, lets keep pretending that there
+          * is something there to not confuse other code.
+          */
+         vs_index = 0;
+      }
 
       /* This can be pre-computed, except for flatshade:
        */
@@ -128,11 +137,12 @@ compute_vertex_info(struct llvmpipe_context *llvmpipe)
 
    /* Figure out if we need pointsize as well.
     */
-   llvmpipe->psize_slot = draw_find_shader_output(llvmpipe->draw,
-                                                  TGSI_SEMANTIC_PSIZE, 0);
-   if (llvmpipe->psize_slot > 0) {
-      draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_CONSTANT,
-                            llvmpipe->psize_slot);
+   vs_index = draw_find_shader_output(llvmpipe->draw,
+                                      TGSI_SEMANTIC_PSIZE, 0);
+
+   if (vs_index > 0) {
+      llvmpipe->psize_slot = vinfo->num_attribs;
+      draw_emit_vertex_attr(vinfo, EMIT_4F, INTERP_CONSTANT, vs_index);
    }
 
    llvmpipe->num_inputs = lpfs->info.num_inputs;
diff --git a/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c b/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
index f845a0c6e5..0bad7320f3 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_rasterizer.c
@@ -76,8 +76,10 @@ llvmpipe_bind_rasterizer_state(struct pipe_context *pipe, void *handle)
       lp_setup_set_line_state( llvmpipe->setup,
                    llvmpipe->rasterizer->line_width);
       lp_setup_set_point_state( llvmpipe->setup,
-                   llvmpipe->rasterizer->point_size);
-   }
+                   llvmpipe->rasterizer->point_size,
+                   llvmpipe->rasterizer->point_size_per_vertex,
+                   llvmpipe->rasterizer->sprite_coord_enable);
+       }
 
    llvmpipe->dirty |= LP_NEW_RASTERIZER;
 }
-- 
cgit v1.2.3


From aea6b415deffd7613d67dc85876afab151b7460e Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 27 Aug 2010 11:03:58 +0100
Subject: llvmpipe: eliminate tri->dx, tri->dy values

Use an internal struct for line setup information.
---
 src/gallium/drivers/llvmpipe/lp_rast.h       |  5 --
 src/gallium/drivers/llvmpipe/lp_setup_line.c | 76 ++++++++++++++--------------
 2 files changed, 39 insertions(+), 42 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_rast.h b/src/gallium/drivers/llvmpipe/lp_rast.h
index 37b4fdc31e..b4564ef33b 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast.h
+++ b/src/gallium/drivers/llvmpipe/lp_rast.h
@@ -116,11 +116,6 @@ struct lp_rast_triangle {
    /* inputs for the shader */
    struct lp_rast_shader_inputs inputs;
 
-   /* XXX: temporarily use these additional fields for line
-    * coefficient setup
-    */
-   float dx, dy; 
-
 #ifdef DEBUG
    float v[3][2];
 #endif
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_line.c b/src/gallium/drivers/llvmpipe/lp_setup_line.c
index ebf000dd19..cf770f521d 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_line.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_line.c
@@ -38,6 +38,15 @@
 
 #define NUM_CHANNELS 4
 
+struct lp_line_info {
+
+   float dx;
+   float dy;
+   float oneoverarea;
+
+   const float (*v1)[4];
+   const float (*v2)[4];
+};
 
 
 /**
@@ -61,26 +70,24 @@ static void constant_coef( struct lp_setup_context *setup,
  */
 static void linear_coef( struct lp_setup_context *setup,
                          struct lp_rast_triangle *tri,
-                         float oneoverarea,
+                         struct lp_line_info *info,
                          unsigned slot,
-                         const float (*v1)[4],
-                         const float (*v2)[4],
                          unsigned vert_attr,
                          unsigned i)
 {
-   float a1 = v1[vert_attr][i]; 
-   float a2 = v2[vert_attr][i];
+   float a1 = info->v1[vert_attr][i]; 
+   float a2 = info->v2[vert_attr][i];
       
    float da21 = a1 - a2;   
-   float dadx = da21 * tri->dx * oneoverarea;
-   float dady = da21 * tri->dy * oneoverarea;
+   float dadx = da21 * info->dx * info->oneoverarea;
+   float dady = da21 * info->dy * info->oneoverarea;
 
    tri->inputs.dadx[slot][i] = dadx;
    tri->inputs.dady[slot][i] = dady;  
    
    tri->inputs.a0[slot][i] = (a1 -
-                              (dadx * (v1[0][0] - setup->pixel_offset) +
-                               dady * (v1[0][1] - setup->pixel_offset)));
+                              (dadx * (info->v1[0][0] - setup->pixel_offset) +
+                               dady * (info->v1[0][1] - setup->pixel_offset)));
 }
 
 
@@ -94,37 +101,33 @@ static void linear_coef( struct lp_setup_context *setup,
  */
 static void perspective_coef( struct lp_setup_context *setup,
                               struct lp_rast_triangle *tri,
-                              float oneoverarea,
+                              struct lp_line_info *info,
                               unsigned slot,
-                              const float (*v1)[4],
-                              const float (*v2)[4],
                               unsigned vert_attr,
                               unsigned i)
 {
    /* premultiply by 1/w  (v[0][3] is always 1/w):
     */
-   float a1 = v1[vert_attr][i] * v1[0][3];
-   float a2 = v2[vert_attr][i] * v2[0][3];
+   float a1 = info->v1[vert_attr][i] * info->v1[0][3];
+   float a2 = info->v2[vert_attr][i] * info->v2[0][3];
 
    float da21 = a1 - a2;   
-   float dadx = da21 * tri->dx * oneoverarea;
-   float dady = da21 * tri->dy * oneoverarea;
+   float dadx = da21 * info->dx * info->oneoverarea;
+   float dady = da21 * info->dy * info->oneoverarea;
 
    tri->inputs.dadx[slot][i] = dadx;
    tri->inputs.dady[slot][i] = dady;
    
    tri->inputs.a0[slot][i] = (a1 -
-                              (dadx * (v1[0][0] - setup->pixel_offset) +
-                               dady * (v1[0][1] - setup->pixel_offset)));
+                              (dadx * (info->v1[0][0] - setup->pixel_offset) +
+                               dady * (info->v1[0][1] - setup->pixel_offset)));
 }
 
 static void
 setup_fragcoord_coef( struct lp_setup_context *setup,
                       struct lp_rast_triangle *tri,
-                      float oneoverarea,
+                      struct lp_line_info *info,
                       unsigned slot,
-                      const float (*v1)[4],
-                      const float (*v2)[4],
                       unsigned usage_mask)
 {
    /*X*/
@@ -143,12 +146,12 @@ setup_fragcoord_coef( struct lp_setup_context *setup,
 
    /*Z*/
    if (usage_mask & TGSI_WRITEMASK_Z) {
-      linear_coef(setup, tri, oneoverarea, slot, v1, v2, 0, 2);
+      linear_coef(setup, tri, info, slot, 0, 2);
    }
 
    /*W*/
    if (usage_mask & TGSI_WRITEMASK_W) {
-      linear_coef(setup, tri, oneoverarea, slot, v1, v2, 0, 3);
+      linear_coef(setup, tri, info, slot, 0, 3);
    }
 }
 
@@ -157,9 +160,7 @@ setup_fragcoord_coef( struct lp_setup_context *setup,
  */
 static void setup_line_coefficients( struct lp_setup_context *setup,
                                      struct lp_rast_triangle *tri,
-                                     float oneoverarea,
-                                     const float (*v1)[4],
-                                     const float (*v2)[4])
+                                     struct lp_line_info *info)
 {
    unsigned fragcoord_usage_mask = TGSI_WRITEMASK_XYZ;
    unsigned slot;
@@ -176,25 +177,25 @@ static void setup_line_coefficients( struct lp_setup_context *setup,
          if (setup->flatshade_first) {
             for (i = 0; i < NUM_CHANNELS; i++)
                if (usage_mask & (1 << i))
-                  constant_coef(setup, tri, slot+1, v1[vert_attr][i], i);
+                  constant_coef(setup, tri, slot+1, info->v1[vert_attr][i], i);
          }
          else {
             for (i = 0; i < NUM_CHANNELS; i++)
                if (usage_mask & (1 << i))
-                  constant_coef(setup, tri, slot+1, v2[vert_attr][i], i);
+                  constant_coef(setup, tri, slot+1, info->v2[vert_attr][i], i);
          }
          break;
 
       case LP_INTERP_LINEAR:
          for (i = 0; i < NUM_CHANNELS; i++)
             if (usage_mask & (1 << i))
-               linear_coef(setup, tri, oneoverarea, slot+1, v1, v2, vert_attr, i);
+               linear_coef(setup, tri, info, slot+1, vert_attr, i);
          break;
 
       case LP_INTERP_PERSPECTIVE:
          for (i = 0; i < NUM_CHANNELS; i++)
             if (usage_mask & (1 << i))
-               perspective_coef(setup, tri, oneoverarea, slot+1, v1, v2, vert_attr, i);
+               perspective_coef(setup, tri, info, slot+1, vert_attr, i);
          fragcoord_usage_mask |= TGSI_WRITEMASK_W;
          break;
 
@@ -214,7 +215,7 @@ static void setup_line_coefficients( struct lp_setup_context *setup,
 
    /* The internal position input is in slot zero:
     */
-   setup_fragcoord_coef(setup, tri, oneoverarea, 0, v1, v2,
+   setup_fragcoord_coef(setup, tri, info, 0,
                         fragcoord_usage_mask);
 }
 
@@ -269,7 +270,7 @@ lp_setup_line( struct lp_setup_context *setup,
 {
    struct lp_scene *scene = lp_setup_get_current_scene(setup);
    struct lp_rast_triangle *line;
-   float oneoverarea;
+   struct lp_line_info info;
    float width = MAX2(1.0, setup->line_width);
    struct u_rect bbox;
    unsigned tri_bytes;
@@ -560,9 +561,6 @@ lp_setup_line( struct lp_setup_context *setup,
    line->v[1][1] = v2[0][1];
 #endif
 
-   line->dx = dx;
-   line->dy = dy;
-
    /* calculate the deltas */
    line->plane[0].dcdy = x[0] - x[1];
    line->plane[1].dcdy = x[1] - x[2];
@@ -575,11 +573,15 @@ lp_setup_line( struct lp_setup_context *setup,
    line->plane[3].dcdx = y[3] - y[0];
 
 
-   oneoverarea = 1.0f / (dx * dx  + dy * dy);    
+   info.oneoverarea = 1.0f / (dx * dx  + dy * dy);    
+   info.dx = dx;
+   info.dy = dy;
+   info.v1 = v1;
+   info.v2 = v2;
 
    /* Setup parameter interpolants:
     */
-   setup_line_coefficients( setup, line, oneoverarea, v1, v2); 
+   setup_line_coefficients( setup, line, &info); 
 
    line->inputs.facing = 1.0F;
    line->inputs.state = setup->fs.stored;
-- 
cgit v1.2.3


From 55f4eab93cf964a2ffa540fef9485b6f737a6f41 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Fri, 27 Aug 2010 13:40:23 +0100
Subject: llvmpipe: use util_iround in place of round

Fix mingw build.
---
 src/gallium/drivers/llvmpipe/lp_setup_line.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup_line.c b/src/gallium/drivers/llvmpipe/lp_setup_line.c
index cf770f521d..ce2da55cf4 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_line.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_line.c
@@ -280,7 +280,7 @@ lp_setup_line( struct lp_setup_context *setup,
    int nr_planes = 4;
    
    /* linewidth should be interpreted as integer */
-   int fixed_width = subpixel_snap(round(width));
+   int fixed_width = util_iround(width) * FIXED_ONE;
 
    float x_offset=0;
    float y_offset=0;
-- 
cgit v1.2.3


From 48d8814c03cc7f270985abe7efdaec1f18d120aa Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Fri, 27 Aug 2010 16:52:29 -0400
Subject: r600g: fix vbo size

Silence the kernel, vbo size is size - 1.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_draw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 1eb868c4c7..1c426f755d 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -107,7 +107,7 @@ static int r600_draw_common(struct r600_draw *draw)
 		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		vs_resource->nbo = 1;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
-		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset;
+		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD1] = rbuffer->bo->size - offset - 1;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD2] = S_038008_STRIDE(vertex_buffer->stride) |
 								S_038008_DATA_FORMAT(format);
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD3] = 0x00000000;
-- 
cgit v1.2.3


From 977f7d48eefee281cc6bb3ccfb462290854b05cd Mon Sep 17 00:00:00 2001
From: Jakob Bornecrantz <wallbraker@gmail.com>
Date: Sat, 28 Aug 2010 00:30:00 +0100
Subject: trace: Don't try to dump the rgba array if null

---
 src/gallium/drivers/trace/tr_context.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/trace/tr_context.c b/src/gallium/drivers/trace/tr_context.c
index 9e8a23d35c..271cd4aff5 100644
--- a/src/gallium/drivers/trace/tr_context.c
+++ b/src/gallium/drivers/trace/tr_context.c
@@ -1063,7 +1063,10 @@ trace_context_clear(struct pipe_context *_pipe,
 
    trace_dump_arg(ptr, pipe);
    trace_dump_arg(uint, buffers);
-   trace_dump_arg_array(float, rgba, 4);
+   if (rgba)
+      trace_dump_arg_array(float, rgba, 4);
+   else
+      trace_dump_null();
    trace_dump_arg(float, depth);
    trace_dump_arg(uint, stencil);
 
-- 
cgit v1.2.3


From f7579f2f28999e585ee9a51635c38d57d25c6193 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 28 Aug 2010 00:29:02 -0700
Subject: llvmpipe: Remove unnecessary header.

---
 src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c b/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c
index b477bc2113..73fb70599c 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_coef_intrin.c
@@ -35,7 +35,6 @@
 #include "lp_setup_context.h"
 #include "lp_setup_coef.h"
 #include "lp_rast.h"
-#include "lp_state_fs.h"
 
 #if defined(PIPE_ARCH_SSE)
 #include <emmintrin.h>
-- 
cgit v1.2.3


From 97cbb563f82f9242a4d7588e502eb2d289eb1b36 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Sat, 28 Aug 2010 07:51:55 +0200
Subject: r300g: set the correct value in PVS_NUM_CNTLRS

As per docs.
---
 src/gallium/drivers/r300/r300_emit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index 58d7e4ffe9..232259e21d 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -909,7 +909,7 @@ void r300_emit_vs_state(struct r300_context* r300, unsigned size, void* state)
 
     unsigned pvs_num_slots = MIN3(vtx_mem_size / input_count,
                                   vtx_mem_size / output_count, 10);
-    unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 6);
+    unsigned pvs_num_controllers = MIN2(vtx_mem_size / temp_count, 5);
 
     unsigned imm_first = vs->externals_count;
     unsigned imm_end = vs->code.constants.Count;
-- 
cgit v1.2.3


From c0f0eb866880ff3e701cd3a532d49417f2743283 Mon Sep 17 00:00:00 2001
From: Mathias Fröhlich <mathias.froehlich@gmx.net>
Date: Sat, 28 Aug 2010 18:16:41 +0200
Subject: r300g: fix min/max lod computation

---
 src/gallium/drivers/r300/r300_state.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 2240011368..9adaea3235 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -1213,8 +1213,8 @@ static void*
 
     /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */
     /* We must pass these to the merge function to clamp them properly. */
-    sampler->min_lod = MAX2((unsigned)state->min_lod, 0);
-    sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0);
+    sampler->min_lod = (unsigned)MAX2(state->min_lod, 0);
+    sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0);
 
     lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1);
 
-- 
cgit v1.2.3


From c5b8ba9368fe935af9f350874f3c03f5a230d4b5 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Sat, 28 Aug 2010 07:54:36 +0200
Subject: r300g: fix blitting between 2D NPOT mipmaps

Even though MIP filtering is not supported, we can bind an arbitrary mipmap
as the zero mipmap level.

NPOT textures now follow GL_TEXTURE_BASE_LEVEL and GL_TEXTURE_MIN_LOD.

This fixes piglit/fbo-copyteximage.
---
 src/gallium/drivers/r300/r300_reg.h           |  1 +
 src/gallium/drivers/r300/r300_state_derived.c | 24 +++++++++++----
 src/gallium/drivers/r300/r300_texture.c       | 43 ++++++++++++++++-----------
 src/gallium/drivers/r300/r300_texture.h       |  6 ++++
 4 files changed, 51 insertions(+), 23 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h
index 60d3b600cb..6bea783f69 100644
--- a/src/gallium/drivers/r300/r300_reg.h
+++ b/src/gallium/drivers/r300/r300_reg.h
@@ -1607,6 +1607,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 #	define R300_TX_FORMAT_3D		   (1 << 25)
 #	define R300_TX_FORMAT_CUBIC_MAP		   (2 << 25)
+#	define R300_TX_FORMAT_TEX_COORD_TYPE_MASK  (0x3 << 25)
 
 	/* alpha modes, convenience mostly */
 	/* if you have alpha, pick constant appropriate to the
diff --git a/src/gallium/drivers/r300/r300_state_derived.c b/src/gallium/drivers/r300/r300_state_derived.c
index c8de3e1c52..960dfdbaf0 100644
--- a/src/gallium/drivers/r300/r300_state_derived.c
+++ b/src/gallium/drivers/r300/r300_state_derived.c
@@ -592,6 +592,25 @@ static void r300_merge_textures_and_samplers(struct r300_context* r300)
             texstate->filter1 = sampler->filter1;
             texstate->border_color = sampler->border_color;
 
+            /* determine min/max levels */
+            max_level = MIN3(sampler->max_lod + view->base.first_level,
+                             tex->desc.b.b.last_level, view->base.last_level);
+            min_level = MIN2(sampler->min_lod + view->base.first_level,
+                             max_level);
+
+            if (tex->desc.is_npot && min_level > 0) {
+                /* Even though we do not implement mipmapping for NPOT
+                 * textures, we should at least honor the minimum level
+                 * which is allowed to be displayed. We do this by setting up
+                 * an i-th mipmap level as the zero level. */
+                r300_texture_setup_format_state(r300->screen, &tex->desc,
+                                                min_level,
+                                                &texstate->format);
+                texstate->format.tile_config |=
+                        tex->desc.offset_in_bytes[min_level] & 0xffffffe0;
+                assert((tex->desc.offset_in_bytes[min_level] & 0x1f) == 0);
+            }
+
             /* Assign a texture cache region. */
             texstate->format.format1 |= view->texcache_region;
 
@@ -654,12 +673,7 @@ static void r300_merge_textures_and_samplers(struct r300_context* r300)
                     texstate->filter0 |= R300_TX_WRAP_T(R300_TX_CLAMP_TO_EDGE);
                 }
             } else {
-                /* determine min/max levels */
                 /* the MAX_MIP level is the largest (finest) one */
-                max_level = MIN3(sampler->max_lod + view->base.first_level,
-                                 tex->desc.b.b.last_level, view->base.last_level);
-                min_level = MIN2(sampler->min_lod + view->base.first_level,
-                                 max_level);
                 texstate->format.format0 |= R300_TX_NUM_LEVELS(max_level);
                 texstate->filter0 |= R300_TX_MAX_MIP_LEVEL(min_level);
             }
diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c
index 852acdd462..66f6d80bd0 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -541,48 +541,55 @@ boolean r300_is_sampler_format_supported(enum pipe_format format)
     return r300_translate_texformat(format, 0, TRUE) != ~0;
 }
 
-static void r300_texture_setup_immutable_state(struct r300_screen* screen,
-                                               struct r300_texture* tex)
+void r300_texture_setup_format_state(struct r300_screen *screen,
+                                     struct r300_texture_desc *desc,
+                                     unsigned level,
+                                     struct r300_texture_format_state *out)
 {
-    struct r300_texture_format_state* f = &tex->tx_format;
-    struct pipe_resource *pt = &tex->desc.b.b;
+    struct pipe_resource *pt = &desc->b.b;
     boolean is_r500 = screen->caps.is_r500;
 
+    /* Mask out all the fields we change. */
+    out->format0 = 0;
+    out->format1 &= ~R300_TX_FORMAT_TEX_COORD_TYPE_MASK;
+    out->format2 &= R500_TXFORMAT_MSB;
+    out->tile_config = 0;
+
     /* Set sampler state. */
-    f->format0 = R300_TX_WIDTH((pt->width0 - 1) & 0x7ff) |
-                 R300_TX_HEIGHT((pt->height0 - 1) & 0x7ff);
+    out->format0 = R300_TX_WIDTH((u_minify(pt->width0, level) - 1) & 0x7ff) |
+                   R300_TX_HEIGHT((u_minify(pt->height0, level) - 1) & 0x7ff);
 
-    if (tex->desc.uses_stride_addressing) {
+    if (desc->uses_stride_addressing) {
         /* rectangles love this */
-        f->format0 |= R300_TX_PITCH_EN;
-        f->format2 = (tex->desc.stride_in_pixels[0] - 1) & 0x1fff;
+        out->format0 |= R300_TX_PITCH_EN;
+        out->format2 = (desc->stride_in_pixels[level] - 1) & 0x1fff;
     } else {
         /* Power of two textures (3D, mipmaps, and no pitch),
          * also NPOT textures with a width being POT. */
-        f->format0 |= R300_TX_DEPTH(util_logbase2(pt->depth0) & 0xf);
+        out->format0 |=
+            R300_TX_DEPTH(util_logbase2(u_minify(pt->depth0, level)) & 0xf);
     }
 
-    f->format1 = 0;
     if (pt->target == PIPE_TEXTURE_CUBE) {
-        f->format1 |= R300_TX_FORMAT_CUBIC_MAP;
+        out->format1 |= R300_TX_FORMAT_CUBIC_MAP;
     }
     if (pt->target == PIPE_TEXTURE_3D) {
-        f->format1 |= R300_TX_FORMAT_3D;
+        out->format1 |= R300_TX_FORMAT_3D;
     }
 
     /* large textures on r500 */
     if (is_r500)
     {
         if (pt->width0 > 2048) {
-            f->format2 |= R500_TXWIDTH_BIT11;
+            out->format2 |= R500_TXWIDTH_BIT11;
         }
         if (pt->height0 > 2048) {
-            f->format2 |= R500_TXHEIGHT_BIT11;
+            out->format2 |= R500_TXHEIGHT_BIT11;
         }
     }
 
-    f->tile_config = R300_TXO_MACRO_TILE(tex->desc.macrotile[0]) |
-                     R300_TXO_MICRO_TILE(tex->desc.microtile);
+    out->tile_config = R300_TXO_MACRO_TILE(desc->macrotile[level]) |
+                       R300_TXO_MICRO_TILE(desc->microtile);
 }
 
 static void r300_texture_setup_fb_state(struct r300_screen* screen,
@@ -716,7 +723,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
         return NULL;
     }
     /* Initialize the hardware state. */
-    r300_texture_setup_immutable_state(rscreen, tex);
+    r300_texture_setup_format_state(rscreen, &tex->desc, 0, &tex->tx_format);
     r300_texture_setup_fb_state(rscreen, tex);
 
     tex->desc.b.vtbl = &r300_texture_vtbl;
diff --git a/src/gallium/drivers/r300/r300_texture.h b/src/gallium/drivers/r300/r300_texture.h
index 5a371a54a8..c4588a0c90 100644
--- a/src/gallium/drivers/r300/r300_texture.h
+++ b/src/gallium/drivers/r300/r300_texture.h
@@ -29,6 +29,8 @@
 struct pipe_screen;
 struct pipe_resource;
 struct winsys_handle;
+struct r300_texture_format_state;
+struct r300_texture_desc;
 struct r300_texture;
 struct r300_screen;
 
@@ -51,6 +53,10 @@ boolean r300_is_zs_format_supported(enum pipe_format format);
 
 boolean r300_is_sampler_format_supported(enum pipe_format format);
 
+void r300_texture_setup_format_state(struct r300_screen *screen,
+                                     struct r300_texture_desc *desc,
+                                     unsigned level,
+                                     struct r300_texture_format_state *out);
 
 struct pipe_resource*
 r300_texture_from_handle(struct pipe_screen* screen,
-- 
cgit v1.2.3


From cf1e4b15a4d21342320fed0fdb19ba6211e4628b Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 28 Aug 2010 14:14:33 -0700
Subject: llvmpipe: Include missing header in lp_flush.c.

Include p_screen.h for complete type to pipe_screen.
---
 src/gallium/drivers/llvmpipe/lp_flush.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_flush.c b/src/gallium/drivers/llvmpipe/lp_flush.c
index 040fe0ba9a..e2c723b7a8 100644
--- a/src/gallium/drivers/llvmpipe/lp_flush.c
+++ b/src/gallium/drivers/llvmpipe/lp_flush.c
@@ -31,6 +31,7 @@
 
 
 #include "pipe/p_defines.h"
+#include "pipe/p_screen.h"
 #include "util/u_string.h"
 #include "draw/draw_context.h"
 #include "lp_flush.h"
-- 
cgit v1.2.3


From d42b7d5f8d5eef73c89c2362beab94647ce12281 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 28 Aug 2010 14:21:28 -0700
Subject: softpipe: Include missing header in sp_flush.c.

Include p_screen.h for complete type to pipe_screen.
---
 src/gallium/drivers/softpipe/sp_flush.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/softpipe/sp_flush.c b/src/gallium/drivers/softpipe/sp_flush.c
index 4a53ef048f..1071011db0 100644
--- a/src/gallium/drivers/softpipe/sp_flush.c
+++ b/src/gallium/drivers/softpipe/sp_flush.c
@@ -31,6 +31,7 @@
 
 
 #include "pipe/p_defines.h"
+#include "pipe/p_screen.h"
 #include "draw/draw_context.h"
 #include "sp_flush.h"
 #include "sp_context.h"
-- 
cgit v1.2.3


From 89b2897220acfacdc431f138377fbcec9f0ea812 Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Sun, 29 Aug 2010 06:03:39 +0200
Subject: util: remove util_is_pot in favor of util_is_power_of_two

The function was duplicated.
---
 src/gallium/auxiliary/gallivm/lp_bld_arit.c       |  2 +-
 src/gallium/auxiliary/gallivm/lp_bld_debug.c      |  2 +-
 src/gallium/auxiliary/gallivm/lp_bld_format_aos.c |  4 ++--
 src/gallium/auxiliary/gallivm/lp_bld_sample.c     |  6 +++---
 src/gallium/auxiliary/util/u_math.h               | 10 ----------
 src/gallium/drivers/galahad/glhd_screen.c         |  2 +-
 6 files changed, 8 insertions(+), 18 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_arit.c b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
index bb30e6e9df..7bb57061f5 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_arit.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_arit.c
@@ -538,7 +538,7 @@ lp_build_mul_imm(struct lp_build_context *bld,
    if(b == 2 && bld->type.floating)
       return lp_build_add(bld, a, a);
 
-   if(util_is_pot(b)) {
+   if(util_is_power_of_two(b)) {
       unsigned shift = ffs(b) - 1;
 
       if(bld->type.floating) {
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.c b/src/gallium/auxiliary/gallivm/lp_bld_debug.c
index 39dfc51e50..d3a5afff8c 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.c
@@ -46,7 +46,7 @@
 boolean
 lp_check_alignment(const void *ptr, unsigned alignment)
 {
-   assert(util_is_pot(alignment));
+   assert(util_is_power_of_two(alignment));
    return ((uintptr_t)ptr & (alignment - 1)) == 0;
 }
 
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c b/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
index 247cb83ce6..92123e09d3 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
@@ -388,7 +388,7 @@ lp_build_fetch_rgba_aos(LLVMBuilderRef builder,
 
    if (format_matches_type(format_desc, type) &&
        format_desc->block.bits <= type.width * 4 &&
-       util_is_pot(format_desc->block.bits)) {
+       util_is_power_of_two(format_desc->block.bits)) {
       LLVMValueRef packed;
 
       /*
@@ -416,7 +416,7 @@ lp_build_fetch_rgba_aos(LLVMBuilderRef builder,
         format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) &&
        format_desc->block.width == 1 &&
        format_desc->block.height == 1 &&
-       util_is_pot(format_desc->block.bits) &&
+       util_is_power_of_two(format_desc->block.bits) &&
        format_desc->block.bits <= 32 &&
        format_desc->is_bitmask &&
        !format_desc->is_mixed &&
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.c b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
index 0fd014ab9b..3c4992b25e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
@@ -82,9 +82,9 @@ lp_sampler_static_state(struct lp_sampler_static_state *state,
    state->swizzle_a         = view->swizzle_a;
 
    state->target            = texture->target;
-   state->pot_width         = util_is_pot(texture->width0);
-   state->pot_height        = util_is_pot(texture->height0);
-   state->pot_depth         = util_is_pot(texture->depth0);
+   state->pot_width         = util_is_power_of_two(texture->width0);
+   state->pot_height        = util_is_power_of_two(texture->height0);
+   state->pot_depth         = util_is_power_of_two(texture->depth0);
 
    state->wrap_s            = sampler->wrap_s;
    state->wrap_t            = sampler->wrap_t;
diff --git a/src/gallium/auxiliary/util/u_math.h b/src/gallium/auxiliary/util/u_math.h
index af510dac51..69a7681494 100644
--- a/src/gallium/auxiliary/util/u_math.h
+++ b/src/gallium/auxiliary/util/u_math.h
@@ -360,16 +360,6 @@ util_is_inf_or_nan(float x)
 }
 
 
-/**
- * Test whether x is a power of two.
- */
-static INLINE boolean
-util_is_pot(unsigned x)
-{
-   return (x & (x - 1)) == 0;
-}
-
-
 /**
  * Find first bit set in word.  Least significant bit is 1.
  * Return 0 if no bits set.
diff --git a/src/gallium/drivers/galahad/glhd_screen.c b/src/gallium/drivers/galahad/glhd_screen.c
index a4eac11ae3..75e4c2d82e 100644
--- a/src/gallium/drivers/galahad/glhd_screen.c
+++ b/src/gallium/drivers/galahad/glhd_screen.c
@@ -140,7 +140,7 @@ galahad_screen_resource_create(struct pipe_screen *_screen,
 
    if(templat->target != PIPE_TEXTURE_RECT && templat->target != PIPE_BUFFER && !screen->get_param(screen, PIPE_CAP_NPOT_TEXTURES))
    {
-      if(!util_is_pot(templat->width0) || !util_is_pot(templat->height0))
+      if(!util_is_power_of_two(templat->width0) || !util_is_power_of_two(templat->height0))
          glhd_warn("Requested NPOT (%ux%u) non-rectangle texture without NPOT support", templat->width0, templat->height0);
    }
 
-- 
cgit v1.2.3


From a922725118333e016a357008f37105c23c6f54bc Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Sun, 29 Aug 2010 06:08:24 +0200
Subject: r300g,u_blitter: use u_framebuffer

Removing another function duplication in u_blitter.
---
 src/gallium/auxiliary/util/u_blitter.c  |  2 +-
 src/gallium/auxiliary/util/u_blitter.h  | 36 ++-------------------------------
 src/gallium/drivers/r300/r300_context.c |  2 +-
 src/gallium/drivers/r300/r300_state.c   |  4 ++--
 4 files changed, 6 insertions(+), 38 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/auxiliary/util/u_blitter.c b/src/gallium/auxiliary/util/u_blitter.c
index 8f93dac011..f93ef26ae7 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -320,7 +320,7 @@ static void blitter_restore_CSOs(struct blitter_context_priv *ctx)
     */
    if (ctx->base.saved_fb_state.nr_cbufs != ~0) {
       pipe->set_framebuffer_state(pipe, &ctx->base.saved_fb_state);
-      util_assign_framebuffer_state(&ctx->base.saved_fb_state, NULL);
+      util_unreference_framebuffer_state(&ctx->base.saved_fb_state);
       ctx->base.saved_fb_state.nr_cbufs = ~0;
    }
 
diff --git a/src/gallium/auxiliary/util/u_blitter.h b/src/gallium/auxiliary/util/u_blitter.h
index f316587dea..e33d2e283f 100644
--- a/src/gallium/auxiliary/util/u_blitter.h
+++ b/src/gallium/auxiliary/util/u_blitter.h
@@ -27,6 +27,7 @@
 #ifndef U_BLITTER_H
 #define U_BLITTER_H
 
+#include "util/u_framebuffer.h"
 #include "util/u_inlines.h"
 #include "util/u_memory.h"
 
@@ -258,45 +259,12 @@ void util_blitter_save_vertex_shader(struct blitter_context *blitter,
    blitter->saved_vs = vs;
 }
 
-/* XXX This should probably be moved elsewhere. */
-static INLINE
-void util_assign_framebuffer_state(struct pipe_framebuffer_state *dst,
-                                   const struct pipe_framebuffer_state *src)
-{
-   unsigned i;
-
-   if (src) {
-      /* Reference all surfaces. */
-      for (i = 0; i < src->nr_cbufs; i++) {
-         pipe_surface_reference(&dst->cbufs[i], src->cbufs[i]);
-      }
-      for (; i < dst->nr_cbufs; i++) {
-         pipe_surface_reference(&dst->cbufs[i], NULL);
-      }
-
-      pipe_surface_reference(&dst->zsbuf, src->zsbuf);
-
-      dst->nr_cbufs = src->nr_cbufs;
-      dst->width = src->width;
-      dst->height = src->height;
-   } else {
-      /* Set all surfaces to NULL. */
-      for (i = 0; i < dst->nr_cbufs; i++) {
-         pipe_surface_reference(&dst->cbufs[i], NULL);
-      }
-
-      pipe_surface_reference(&dst->zsbuf, NULL);
-
-      dst->nr_cbufs = 0;
-   }
-}
-
 static INLINE
 void util_blitter_save_framebuffer(struct blitter_context *blitter,
                                    const struct pipe_framebuffer_state *state)
 {
    blitter->saved_fb_state.nr_cbufs = 0; /* It's ~0 now, meaning it's unsaved. */
-   util_assign_framebuffer_state(&blitter->saved_fb_state, state);
+   util_copy_framebuffer_state(&blitter->saved_fb_state, state);
 }
 
 static INLINE
diff --git a/src/gallium/drivers/r300/r300_context.c b/src/gallium/drivers/r300/r300_context.c
index 05f7d09316..624dadd07d 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -65,7 +65,7 @@ static void r300_release_referenced_objects(struct r300_context *r300)
     unsigned i;
 
     /* Framebuffer state. */
-    util_assign_framebuffer_state(fb, NULL);
+    util_unreference_framebuffer_state(fb);
 
     /* Textures. */
     for (i = 0; i < textures->sampler_view_count; i++)
diff --git a/src/gallium/drivers/r300/r300_state.c b/src/gallium/drivers/r300/r300_state.c
index 9adaea3235..8ccb63964e 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -23,7 +23,7 @@
 
 #include "draw/draw_context.h"
 
-#include "util/u_blitter.h"
+#include "util/u_framebuffer.h"
 #include "util/u_math.h"
 #include "util/u_mm.h"
 #include "util/u_memory.h"
@@ -748,7 +748,7 @@ static void
     /* The tiling flags are dependent on the surface miplevel, unfortunately. */
     r300_fb_set_tiling_flags(r300, state);
 
-    util_assign_framebuffer_state(r300->fb_state.state, state);
+    util_copy_framebuffer_state(r300->fb_state.state, state);
 
     r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE);
 
-- 
cgit v1.2.3


From 1fc396204b5676d7ebdbc20089d6442ab3dbcef4 Mon Sep 17 00:00:00 2001
From: Vinson Lee <vlee@vmware.com>
Date: Sat, 28 Aug 2010 22:12:55 -0700
Subject: nvfx: Remove util_is_pot in favor of util_is_power_of_two.

This is a follow up to commit 89b2897220acfacdc431f138377fbcec9f0ea812.
---
 src/gallium/drivers/nvfx/nvfx_miptree.c | 8 ++++----
 src/gallium/drivers/nvfx/nvfx_surface.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_miptree.c b/src/gallium/drivers/nvfx/nvfx_miptree.c
index 46e1f9e4f4..0916aaa828 100644
--- a/src/gallium/drivers/nvfx/nvfx_miptree.c
+++ b/src/gallium/drivers/nvfx/nvfx_miptree.c
@@ -20,9 +20,9 @@ nvfx_miptree_choose_format(struct nvfx_miptree *mt)
 	if(no_swizzle < 0)
 		no_swizzle = debug_get_bool_option("NV40_NO_SWIZZLE", FALSE); /* this will break things on nv30 */
 
-	if (!util_is_pot(pt->width0) ||
-	    !util_is_pot(pt->height0) ||
-	    !util_is_pot(pt->depth0) ||
+	if (!util_is_power_of_two(pt->width0) ||
+	    !util_is_power_of_two(pt->height0) ||
+	    !util_is_power_of_two(pt->depth0) ||
 	    (!nvfx_screen(pt->screen)->is_nv4x && pt->target == PIPE_TEXTURE_RECT)
 	    )
 		uniform_pitch = 1;
@@ -69,7 +69,7 @@ nvfx_miptree_layout(struct nvfx_miptree *mt)
 	if(!nvfx_screen(pt->screen)->is_nv4x)
 	{
 		assert(pt->target == PIPE_TEXTURE_RECT
-			|| (util_is_pot(pt->width0) && util_is_pot(pt->height0)));
+			|| (util_is_power_of_two(pt->width0) && util_is_power_of_two(pt->height0)));
 	}
 
 	for (unsigned l = 0; l <= pt->last_level; l++)
diff --git a/src/gallium/drivers/nvfx/nvfx_surface.c b/src/gallium/drivers/nvfx/nvfx_surface.c
index f6cc985673..a5931b6e15 100644
--- a/src/gallium/drivers/nvfx/nvfx_surface.c
+++ b/src/gallium/drivers/nvfx/nvfx_surface.c
@@ -61,7 +61,7 @@ nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format)
 	default:
 		{
 			int shift;
-			assert(util_is_pot(bits));
+			assert(util_is_power_of_two(bits));
 			shift = util_logbase2(bits) - 3;
 			assert(shift >= 2);
 			rgn->bpps = 2;
-- 
cgit v1.2.3


From e77b1e777d585254db62e872a74e23351bb36f85 Mon Sep 17 00:00:00 2001
From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun, 29 Aug 2010 11:19:22 +0200
Subject: r600g: added literals where needed for POW instruction

Fixes size calculation for the bytecode buffer.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index ebcf19c12b..bf5f28fd9c 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1069,6 +1069,9 @@ static int tgsi_pow(struct r600_shader_ctx *ctx)
 	alu.dst.write = 1;
 	alu.last = 1;
 	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	r = r600_bc_add_literal(ctx->bc,ctx->value);
 	if (r)
 		return r;
 	/* b * LOG2(a) */
@@ -1083,6 +1086,9 @@ static int tgsi_pow(struct r600_shader_ctx *ctx)
 	alu.dst.write = 1;
 	alu.last = 1;
 	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	r = r600_bc_add_literal(ctx->bc,ctx->value);
 	if (r)
 		return r;
 	/* POW(a,b) = EXP2(b * LOG2(a))*/
@@ -1093,6 +1099,9 @@ static int tgsi_pow(struct r600_shader_ctx *ctx)
 	alu.dst.write = 1;
 	alu.last = 1;
 	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	r = r600_bc_add_literal(ctx->bc,ctx->value);
 	if (r)
 		return r;
 	return tgsi_helper_tempx_replicate(ctx);
-- 
cgit v1.2.3


From cd4bd4fb53f82361480f388923ef9e2fa7379d68 Mon Sep 17 00:00:00 2001
From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Date: Sun, 29 Aug 2010 11:19:23 +0200
Subject: r600g: use the values from the correct literals

Created an array for literals as we should not always use the last declared literal.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r600/r600_shader.c | 27 +++++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index bf5f28fd9c..dabc7bec30 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -48,6 +48,8 @@ struct r600_shader_ctx {
 	struct r600_bc				*bc;
 	struct r600_shader			*shader;
 	u32					value[4];
+	u32					*literals;
+	u32					nliterals;
 };
 
 struct r600_shader_tgsi_instruction {
@@ -404,15 +406,24 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 	ctx.temp_reg = ctx.file_offset[TGSI_FILE_TEMPORARY] +
 			ctx.info.file_count[TGSI_FILE_TEMPORARY];
 
+	ctx.nliterals = 0;
+	ctx.literals = NULL;
+
 	while (!tgsi_parse_end_of_tokens(&ctx.parse)) {
 		tgsi_parse_token(&ctx.parse);
 		switch (ctx.parse.FullToken.Token.Type) {
 		case TGSI_TOKEN_TYPE_IMMEDIATE:
 			immediate = &ctx.parse.FullToken.FullImmediate;
-			ctx.value[0] = immediate->u[0].Uint;
-			ctx.value[1] = immediate->u[1].Uint;
-			ctx.value[2] = immediate->u[2].Uint;
-			ctx.value[3] = immediate->u[3].Uint;
+			ctx.literals = realloc(ctx.literals, (ctx.nliterals + 1) * 16);
+			if(ctx.literals == NULL) {
+				r = -ENOMEM;
+				goto out_err;
+			}
+			ctx.literals[ctx.nliterals * 4 + 0] = immediate->u[0].Uint;
+			ctx.literals[ctx.nliterals * 4 + 1] = immediate->u[1].Uint;
+			ctx.literals[ctx.nliterals * 4 + 2] = immediate->u[2].Uint;
+			ctx.literals[ctx.nliterals * 4 + 3] = immediate->u[3].Uint;
+			ctx.nliterals++;
 			break;
 		case TGSI_TOKEN_TYPE_DECLARATION:
 			r = tgsi_declaration(&ctx);
@@ -540,9 +551,11 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 		if (r)
 			goto out_err;
 	}
+	free(ctx.literals);
 	tgsi_parse_free(&ctx.parse);
 	return 0;
 out_err:
+	free(ctx.literals);
 	tgsi_parse_free(&ctx.parse);
 	return r;
 }
@@ -562,10 +575,16 @@ static int tgsi_src(struct r600_shader_ctx *ctx,
 			const struct tgsi_full_src_register *tgsi_src,
 			struct r600_bc_alu_src *r600_src)
 {
+	int index;
 	memset(r600_src, 0, sizeof(struct r600_bc_alu_src));
 	r600_src->sel = tgsi_src->Register.Index;
 	if (tgsi_src->Register.File == TGSI_FILE_IMMEDIATE) {
 		r600_src->sel = 0;
+		index = tgsi_src->Register.Index;
+		ctx->value[0] = ctx->literals[index * 4 + 0];
+		ctx->value[1] = ctx->literals[index * 4 + 1];
+		ctx->value[2] = ctx->literals[index * 4 + 2];
+		ctx->value[3] = ctx->literals[index * 4 + 3];
 	}
 	r600_src->neg = tgsi_src->Register.Negate;
 	r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
-- 
cgit v1.2.3


From 09547e1bcee7df3444dd8682770d1b31da1a5822 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Fri, 27 Aug 2010 16:08:55 +1000
Subject: r600g : add basic loop support.

Adds BGNLOOP, BRK, CONT, ENDLOOP support, ported from r600c.

17 piglits more on r300g.tests.
---
 src/gallium/drivers/r600/r600_asm.c    |  21 ++-
 src/gallium/drivers/r600/r600_asm.h    |  17 ++-
 src/gallium/drivers/r600/r600_shader.c | 232 ++++++++++++++++++++++++++++++---
 3 files changed, 247 insertions(+), 23 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index d83bb34648..03fe950186 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -200,6 +200,10 @@ int r600_bc_add_literal(struct r600_bc *bc, const u32 *value)
 	}
 	if (bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_JUMP ||
 	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_ELSE ||
+	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL ||
+	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK ||
+	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE ||
+	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END ||
 	    bc->cf_last->inst == V_SQ_CF_WORD1_SQ_CF_INST_POP) {
 		return 0;
 	}
@@ -414,6 +418,10 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 	case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
 	case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
 	case V_SQ_CF_WORD1_SQ_CF_INST_POP:
+	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+	case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
 		bc->bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf->cf_addr >> 1);
 		bc->bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf->inst) |
 					S_SQ_CF_WORD1_BARRIER(1) |
@@ -437,6 +445,9 @@ int r600_bc_build(struct r600_bc *bc)
 	unsigned addr;
 	int r;
 
+	if (bc->callstack[0].max > 0)
+	    bc->nstack = ((bc->callstack[0].max + 3) >> 2) + 2;
+
 	/* first path compute addr of each CF block */
 	/* addr start after all the CF instructions */
 	addr = bc->cf_last->id + 2;
@@ -458,8 +469,10 @@ int r600_bc_build(struct r600_bc *bc)
 		case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
 		case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
 		case V_SQ_CF_WORD1_SQ_CF_INST_POP:
-			/* hack */
-			bc->nstack = 3;
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
 			break;
 		default:
 			R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
@@ -520,6 +533,10 @@ int r600_bc_build(struct r600_bc *bc)
 			break;
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT:
 		case V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_EXPORT_DONE:
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL:
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END:
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE:
+		case V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK:
 		case V_SQ_CF_WORD1_SQ_CF_INST_JUMP:
 		case V_SQ_CF_WORD1_SQ_CF_INST_ELSE:
 		case V_SQ_CF_WORD1_SQ_CF_INST_POP:
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index dbd885caf9..bb4f4b77b3 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -127,11 +127,23 @@ struct r600_bc_cf {
 #define FC_NONE 0
 #define FC_IF 1
 #define FC_LOOP 2
+#define FC_REP 3
+#define FC_PUSH_VPM 4
+#define FC_PUSH_WQM 5
 
 struct r600_cf_stack_entry {
 	int type;
 	struct r600_bc_cf *start;
-	struct r600_bc_cf *mid; /* used to store the else point */
+	struct r600_bc_cf **mid; /* used to store the else point */
+	int num_mid;
+};
+
+#define SQ_MAX_CALL_DEPTH 0x00000020
+struct r600_cf_callstack {
+	unsigned fc_sp_before_entry;
+	int sub_desc_index;
+	int current;
+	int max;
 };
 	
 struct r600_bc {
@@ -149,6 +161,9 @@ struct r600_bc {
 
 	u32 fc_sp;
 	struct r600_cf_stack_entry fc_stack[32];
+
+	unsigned call_sp;
+	struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH];
 };
 
 int r600_bc_init(struct r600_bc *bc, enum radeon_family family);
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index dabc7bec30..82f4d73e43 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1650,8 +1650,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_alu_src r600_src[3];
 	struct r600_bc_alu alu;
-	uint32_t use_temp = 0;
-	int i, r;
+	int r;
 
 	/* result.x = 2^floor(src); */
 	if (inst->Dst[0].Register.WriteMask & 1) {
@@ -1753,8 +1752,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
-	struct r600_bc_alu alu, *lalu;
-	struct r600_bc_cf *last;
+	struct r600_bc_alu alu;
 	int r;
 
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -1777,7 +1775,6 @@ static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
 	r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU_PUSH_BEFORE);
 	if (r)
 		return r;
-
 	return 0;
 }
 
@@ -1788,29 +1785,158 @@ static int pops(struct r600_shader_ctx *ctx, int pops)
 	return 0;
 }
 
-static int tgsi_if(struct r600_shader_ctx *ctx)
+static inline void callstack_decrease_current(struct r600_shader_ctx *ctx, unsigned reason)
 {
-	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	switch(reason) {
+	case FC_PUSH_VPM:
+		ctx->bc->callstack[ctx->bc->call_sp].current--;
+		break;
+	case FC_PUSH_WQM:
+	case FC_LOOP:
+		ctx->bc->callstack[ctx->bc->call_sp].current -= 4;
+		break;
+	case FC_REP:
+		/* TOODO : for 16 vp asic should -= 2; */
+		ctx->bc->callstack[ctx->bc->call_sp].current --;
+		break;
+	}
+}
 
-	emit_logic_pred(ctx, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE);
+static inline void callstack_check_depth(struct r600_shader_ctx *ctx, unsigned reason, unsigned check_max_only)
+{
+	if (check_max_only) {
+		int diff;
+		switch (reason) {
+		case FC_PUSH_VPM:
+			diff = 1;
+			break;
+		case FC_PUSH_WQM:
+			diff = 4;
+			break;
+		}
+		if ((ctx->bc->callstack[ctx->bc->call_sp].current + diff) >
+		    ctx->bc->callstack[ctx->bc->call_sp].max) {
+			ctx->bc->callstack[ctx->bc->call_sp].max =
+				ctx->bc->callstack[ctx->bc->call_sp].current + diff;
+		}
+		return;
+	}					
+	switch (reason) {
+	case FC_PUSH_VPM:
+		ctx->bc->callstack[ctx->bc->call_sp].current++;
+		break;
+	case FC_PUSH_WQM:
+	case FC_LOOP:
+		ctx->bc->callstack[ctx->bc->call_sp].current += 4;
+		break;
+	case FC_REP:
+		ctx->bc->callstack[ctx->bc->call_sp].current++;
+		break;
+	}
+
+	if ((ctx->bc->callstack[ctx->bc->call_sp].current) >
+	    ctx->bc->callstack[ctx->bc->call_sp].max) {
+		ctx->bc->callstack[ctx->bc->call_sp].max =
+			ctx->bc->callstack[ctx->bc->call_sp].current;
+	}
+}
+
+static void fc_set_mid(struct r600_shader_ctx *ctx, int fc_sp)
+{
+	struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[fc_sp];
+
+	sp->mid = (struct r600_bc_cf **)realloc((void *)sp->mid,
+						sizeof(struct r600_bc_cf *) * (sp->num_mid + 1));
+	sp->mid[sp->num_mid] = ctx->bc->cf_last;
+	sp->num_mid++;
+}
 
+static void fc_pushlevel(struct r600_shader_ctx *ctx, int type)
+{
 	ctx->bc->fc_sp++;
-	ctx->bc->fc_stack[ctx->bc->fc_sp].type = FC_IF;
-	ctx->bc->fc_stack[ctx->bc->fc_sp].mid = NULL;
+	ctx->bc->fc_stack[ctx->bc->fc_sp].type = type;
+	ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
+}
+
+static void fc_poplevel(struct r600_shader_ctx *ctx)
+{
+	struct r600_cf_stack_entry *sp = &ctx->bc->fc_stack[ctx->bc->fc_sp];
+	if (sp->mid) {
+		free(sp->mid);
+		sp->mid = NULL;
+	}
+	sp->num_mid = 0;
+	sp->start = NULL;
+	sp->type = 0;
+	ctx->bc->fc_sp--;
+}
+
+#if 0
+static int emit_return(struct r600_shader_ctx *ctx)
+{
+	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_RETURN);
+	return 0;
+}
+
+static int emit_jump_to_offset(struct r600_shader_ctx *ctx, int pops, int offset)
+{
+
 	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
+	ctx->bc->cf_last->pop_count = pops;
+	/* TODO work out offset */
+	return 0;
+}
 
-	ctx->bc->fc_stack[ctx->bc->fc_sp].start = ctx->bc->cf_last;
+static int emit_setret_in_loop_flag(struct r600_shader_ctx *ctx, unsigned flag_value)
+{
+	return 0;
+}
+
+static void emit_testflag(struct r600_shader_ctx *ctx)
+{
+	
+}
+
+static void emit_return_on_flag(struct r600_shader_ctx *ctx, unsigned ifidx)
+{
+	emit_testflag(ctx);
+	emit_jump_to_offset(ctx, 1, 4);
+	emit_setret_in_loop_flag(ctx, V_SQ_ALU_SRC_0);
+	pops(ctx, ifidx + 1);
+	emit_return(ctx);
+}
+
+static void break_loop_on_flag(struct r600_shader_ctx *ctx, unsigned fc_sp)
+{
+	emit_testflag(ctx);
+
+	r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
+	ctx->bc->cf_last->pop_count = 1;
+
+	fc_set_mid(ctx, fc_sp);
+
+	pops(ctx, 1);
+}
+#endif
+
+static int tgsi_if(struct r600_shader_ctx *ctx)
+{
+	emit_logic_pred(ctx, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE);
+
+	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_JUMP);
+
+	fc_pushlevel(ctx, FC_IF);
+
+	callstack_check_depth(ctx, FC_PUSH_VPM, 0);
 	return 0;
 }
 
 static int tgsi_else(struct r600_shader_ctx *ctx)
 {
-	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_ELSE);
 	ctx->bc->cf_last->pop_count = 1;
 
-	/* fixup mid */
-	ctx->bc->fc_stack[ctx->bc->fc_sp].mid = ctx->bc->cf_last;
+	fc_set_mid(ctx, ctx->bc->fc_sp);
 	ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id;
 	return 0;
 }
@@ -1827,10 +1953,76 @@ static int tgsi_endif(struct r600_shader_ctx *ctx)
 		ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
 		ctx->bc->fc_stack[ctx->bc->fc_sp].start->pop_count = 1;
 	} else {
-		ctx->bc->fc_stack[ctx->bc->fc_sp].mid->cf_addr = ctx->bc->cf_last->id + 2;
+		ctx->bc->fc_stack[ctx->bc->fc_sp].mid[0]->cf_addr = ctx->bc->cf_last->id + 2;
 	}
-	ctx->bc->fc_sp--;
+	fc_poplevel(ctx);
+
+	callstack_decrease_current(ctx, FC_PUSH_VPM);
+	return 0;
+}
+
+static int tgsi_bgnloop(struct r600_shader_ctx *ctx)
+{
+	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_START_NO_AL);
+
+	fc_pushlevel(ctx, FC_LOOP);
 
+	/* check stack depth */
+	callstack_check_depth(ctx, FC_LOOP, 0);
+	return 0;
+}
+
+static int tgsi_endloop(struct r600_shader_ctx *ctx)
+{
+	int i;
+
+	r600_bc_add_cfinst(ctx->bc, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END);
+
+	if (ctx->bc->fc_stack[ctx->bc->fc_sp].type != FC_LOOP) {
+		R600_ERR("loop/endloop in shader code are not paired.\n");
+		return -EINVAL;
+	}
+
+	/* fixup loop pointers - from r600isa
+	   LOOP END points to CF after LOOP START,
+	   LOOP START point to CF after LOOP END
+	   BRK/CONT point to LOOP END CF
+	*/
+	ctx->bc->cf_last->cf_addr = ctx->bc->fc_stack[ctx->bc->fc_sp].start->id + 2;
+
+	ctx->bc->fc_stack[ctx->bc->fc_sp].start->cf_addr = ctx->bc->cf_last->id + 2;
+
+	for (i = 0; i < ctx->bc->fc_stack[ctx->bc->fc_sp].num_mid; i++) {
+		ctx->bc->fc_stack[ctx->bc->fc_sp].mid[i]->cf_addr = ctx->bc->cf_last->id;
+	}
+	/* TODO add LOOPRET support */
+	fc_poplevel(ctx);
+	callstack_decrease_current(ctx, FC_LOOP);
+	return 0;
+}
+
+static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
+{
+	unsigned int fscp;
+
+	for (fscp = ctx->bc->fc_sp; fscp > 0; fscp--)
+	{
+		if (FC_LOOP == ctx->bc->fc_stack[fscp].type)
+			break;
+	}
+
+	if (fscp == 0) {
+		R600_ERR("Break not inside loop/endloop pair\n");
+		return -EINVAL;
+	}
+
+	r600_bc_add_cfinst(ctx->bc, ctx->inst_info->r600_opcode);
+	ctx->bc->cf_last->pop_count = 1;
+
+	fc_set_mid(ctx, fscp);
+
+	pops(ctx, 1);
+	callstack_check_depth(ctx, FC_PUSH_VPM, 1);
 	return 0;
 }
 
@@ -1911,7 +2103,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_DIV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DP2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_TXL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BRK,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BRK,	0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK, tgsi_loop_brk_cont},
 	{TGSI_OPCODE_IF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_if},
 	/* gap */
 	{75,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
@@ -1937,12 +2129,12 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_SAD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TXF,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_TXQ,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_CONT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_CONT,	0, V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE, tgsi_loop_brk_cont},
 	{TGSI_OPCODE_EMIT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_ENDPRIM,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_BGNLOOP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_BGNLOOP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_bgnloop},
 	{TGSI_OPCODE_BGNSUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-	{TGSI_OPCODE_ENDLOOP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ENDLOOP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_endloop},
 	{TGSI_OPCODE_ENDSUB,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	/* gap */
 	{103,			0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-- 
cgit v1.2.3


From cb08b9fa84bf432dcca2e685daadd2df651b3025 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 30 Aug 2010 14:13:01 +1000
Subject: r600g: fix SSG and op3 neg writing

8 more piglits, mainly the two SSG tests.
---
 src/gallium/drivers/r600/r600_asm.c    | 20 ++++++++------------
 src/gallium/drivers/r600/r600_shader.c |  9 +++++++--
 2 files changed, 15 insertions(+), 14 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 03fe950186..d3a9c6ca1f 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -340,12 +340,15 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 	unsigned i;
 
 	/* don't replace gpr by pv or ps for destination register */
+	bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
+				S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
+				S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
+				S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
+				S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
+				S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
+				S_SQ_ALU_WORD0_LAST(alu->last);
+
 	if (alu->is_op3) {
-		bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
-					S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
-					S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
-					S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
-					S_SQ_ALU_WORD0_LAST(alu->last);
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
 					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
@@ -355,13 +358,6 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 					S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
 					S_SQ_ALU_WORD1_BANK_SWIZZLE(0);
 	} else {
-		bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
-					S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
-					S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
-					S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
-					S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
-					S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
-					S_SQ_ALU_WORD0_LAST(alu->last);
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
 					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 82f4d73e43..4ff705622e 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1142,8 +1142,9 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_CNDGT;
 		alu.is_op3 = 1;
+
 		alu.dst.sel = ctx->temp_reg;
-		alu.dst.write = 1;
+		alu.dst.chan = i;
 
 		alu.src[0] = r600_src[0];
 		alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
@@ -1158,6 +1159,9 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 	}
+	r = r600_bc_add_literal(ctx->bc, ctx->value);
+	if (r)
+		return r;
 
 	/* dst = (-tmp > 0 ? -1 : tmp) */
 	for (i = 0; i < 4; i++) {
@@ -1169,14 +1173,15 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
 			return r;
 
 		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = i;
 		alu.src[0].neg = 1;
 
 		alu.src[1].sel = V_SQ_ALU_SRC_1;
 		alu.src[1].neg = 1;
 
 		alu.src[2].sel = ctx->temp_reg;
+		alu.src[2].chan = i;
 
-		alu.dst.write = 1;
 		if (i == 3)
 			alu.last = 1;
 		r = r600_bc_add_alu(ctx->bc, &alu);
-- 
cgit v1.2.3


From 4502b17901ad491e0598ee59a12d372c008ae03b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 30 Aug 2010 14:41:09 +1000
Subject: r600g: add KILP support

passes glsl1-discard tests
---
 src/gallium/drivers/r600/r600_shader.c | 25 ++++++++++++++++++++-----
 src/gallium/drivers/r600/r600_shader.h |  1 +
 src/gallium/drivers/r600/r600_state.c  |  2 ++
 3 files changed, 23 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 4ff705622e..514288bc8c 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -861,12 +861,20 @@ static int tgsi_kill(struct r600_shader_ctx *ctx)
 	for (i = 0; i < 4; i++) {
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = ctx->inst_info->r600_opcode;
+
 		alu.dst.chan = i;
+
 		alu.src[0].sel = V_SQ_ALU_SRC_0;
-		r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
-		if (r)
-			return r;
-		alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
+
+		if (ctx->inst_info->tgsi_opcode == TGSI_OPCODE_KILP) {
+			alu.src[1].sel = V_SQ_ALU_SRC_1;
+			alu.src[1].neg = 1;
+		} else {
+			r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
+			if (r)
+				return r;
+			alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
+		}
 		if (i == 3) {
 			alu.last = 1;
 		}
@@ -874,6 +882,13 @@ static int tgsi_kill(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 	}
+	r = r600_bc_add_literal(ctx->bc, ctx->value);
+	if (r)
+		return r;
+
+	/* kill must be last in ALU */
+	ctx->bc->force_add_cf = 1;
+	ctx->shader->uses_kill = TRUE;
 	return 0;
 }
 
@@ -2074,7 +2089,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_COS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS, tgsi_trig},
 	{TGSI_OPCODE_DDX,	0, SQ_TEX_INST_GET_GRADIENTS_H, tgsi_tex},
 	{TGSI_OPCODE_DDY,	0, SQ_TEX_INST_GET_GRADIENTS_V, tgsi_tex},
-	{TGSI_OPCODE_KILP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},  /* predicated kill */
+	{TGSI_OPCODE_KILP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT, tgsi_kill},  /* predicated kill */
 	{TGSI_OPCODE_PK2H,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_PK2US,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_PK4B,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index 2ee7780ead..7c722c07cb 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -42,6 +42,7 @@ struct r600_shader {
 	struct r600_shader_io	input[32];
 	struct r600_shader_io	output[32];
 	enum radeon_family	family;
+	boolean                 uses_kill;
 };
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b5e5346163..441be8fd6d 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -999,6 +999,8 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 
 	db_shader_control = 0x210;
 	rshader = &rctx->ps_shader->shader;
+	if (rshader->uses_kill)
+		db_shader_control |= (1 << 6);
 	for (i = 0; i < rshader->noutput; i++) {
 		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
 			db_shader_control |= 1;
-- 
cgit v1.2.3


From 47d5a19df1e7760c4f5f0e340bfc56355c2e428b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 30 Aug 2010 15:19:20 +1000
Subject: r600g: add initial relative support to assembler

passes another ~20 piglits.

/me starts to run out low hanging fruit around now.
---
 src/gallium/drivers/r600/r600_asm.c    |  5 ++++
 src/gallium/drivers/r600/r600_asm.h    |  2 ++
 src/gallium/drivers/r600/r600_shader.c | 42 +++++++++++++++++++++++++++++-----
 src/gallium/drivers/r600/r600_sq.h     |  2 ++
 4 files changed, 45 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index d3a9c6ca1f..1a354a6293 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -341,9 +341,11 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 
 	/* don't replace gpr by pv or ps for destination register */
 	bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
+				S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
 				S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
 				S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
 				S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
+				S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
 				S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
 				S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
 				S_SQ_ALU_WORD0_LAST(alu->last);
@@ -351,8 +353,10 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 	if (alu->is_op3) {
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+					S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
 					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
 					S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
+					S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
 					S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
 					S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
 					S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
@@ -360,6 +364,7 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 	} else {
 		bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
 					S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
+					S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
 					S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
 					S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
 					S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index bb4f4b77b3..9e65fcdd4f 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -31,6 +31,7 @@ struct r600_bc_alu_src {
 	unsigned			chan;
 	unsigned			neg;
 	unsigned			abs;
+	unsigned			rel;
 };
 
 struct r600_bc_alu_dst {
@@ -38,6 +39,7 @@ struct r600_bc_alu_dst {
 	unsigned			chan;
 	unsigned			clamp;
 	unsigned			write;
+	unsigned			rel;
 };
 
 struct r600_bc_alu {
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 514288bc8c..bda829af2b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -284,16 +284,18 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 	}
 #endif
 	for (j = 0; j < i->Instruction.NumSrcRegs; j++) {
-		if (i->Src[j].Register.Indirect ||
-			i->Src[j].Register.Dimension ||
+		if (i->Src[j].Register.Dimension ||
 			i->Src[j].Register.Absolute) {
-			R600_ERR("unsupported src (indirect|dimension|absolute)\n");
+			R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
+				 i->Src[j].Register.Indirect,
+				 i->Src[j].Register.Dimension,
+				 i->Src[j].Register.Absolute);
 			return -EINVAL;
 		}
 	}
 	for (j = 0; j < i->Instruction.NumDstRegs; j++) {
-		if (i->Dst[j].Register.Indirect || i->Dst[j].Register.Dimension) {
-			R600_ERR("unsupported dst (indirect|dimension)\n");
+		if (i->Dst[j].Register.Dimension) {
+			R600_ERR("unsupported dst (dimension)\n");
 			return -EINVAL;
 		}
 	}
@@ -344,6 +346,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 	case TGSI_FILE_CONSTANT:
 	case TGSI_FILE_TEMPORARY:
 	case TGSI_FILE_SAMPLER:
+	case TGSI_FILE_ADDRESS:
 		break;
 	default:
 		R600_ERR("unsupported file %d declaration\n", d->Declaration.File);
@@ -586,6 +589,8 @@ static int tgsi_src(struct r600_shader_ctx *ctx,
 		ctx->value[2] = ctx->literals[index * 4 + 2];
 		ctx->value[3] = ctx->literals[index * 4 + 3];
 	}
+	if (tgsi_src->Register.Indirect)
+		r600_src->rel = V_SQ_REL_RELATIVE;
 	r600_src->neg = tgsi_src->Register.Negate;
 	r600_src->sel += ctx->file_offset[tgsi_src->Register.File];
 	return 0;
@@ -602,6 +607,8 @@ static int tgsi_dst(struct r600_shader_ctx *ctx,
 	r600_dst->sel += ctx->file_offset[tgsi_dst->Register.File];
 	r600_dst->chan = swizzle;
 	r600_dst->write = 1;
+	if (tgsi_dst->Register.Indirect)
+		r600_dst->rel = V_SQ_REL_RELATIVE;
 	if (inst->Instruction.Saturate) {
 		r600_dst->clamp = 1;
 	}
@@ -1769,6 +1776,29 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 	return tgsi_helper_copy(ctx, inst);
 }
 
+static int tgsi_arl(struct r600_shader_ctx *ctx)
+{
+	/* TODO from r600c, ar values don't persist between clauses */
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int r;
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR;
+
+	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+	if (r)
+		return r;
+	alu.src[0].chan = tgsi_chan(&inst->Src[0], 0);
+
+	alu.last = 1;
+
+	r = r600_bc_add_alu_type(ctx->bc, &alu, V_SQ_CF_ALU_WORD1_SQ_CF_INST_ALU);
+	if (r)
+		return r;
+	return 0;
+}
+
 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -2047,7 +2077,7 @@ static int tgsi_loop_brk_cont(struct r600_shader_ctx *ctx)
 }
 
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
-	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_ARL,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_arl},
 	{TGSI_OPCODE_MOV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV, tgsi_op2},
 	{TGSI_OPCODE_LIT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_lit},
 	{TGSI_OPCODE_RCP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE, tgsi_trans_srcx_replicate},
diff --git a/src/gallium/drivers/r600/r600_sq.h b/src/gallium/drivers/r600/r600_sq.h
index b4ed435e91..fa7a31742a 100644
--- a/src/gallium/drivers/r600/r600_sq.h
+++ b/src/gallium/drivers/r600/r600_sq.h
@@ -608,4 +608,6 @@
 #define V_SQ_CF_COND_BOOL                               0x02
 #define V_SQ_CF_COND_NOT_BOOL                           0x03
 
+#define V_SQ_REL_ABSOLUTE 0
+#define V_SQ_REL_RELATIVE 1
 #endif
-- 
cgit v1.2.3


From db92a03aacc0c0e13377af4f54ef5303400b4810 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 30 Aug 2010 15:50:33 +1000
Subject: r600g: fix warning introduced by last commit.

---
 src/gallium/drivers/r600/r600_shader.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index bda829af2b..9a4e39e2cc 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -287,7 +287,6 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 		if (i->Src[j].Register.Dimension ||
 			i->Src[j].Register.Absolute) {
 			R600_ERR("unsupported src %d (dimension %d|absolute %d)\n", j,
-				 i->Src[j].Register.Indirect,
 				 i->Src[j].Register.Dimension,
 				 i->Src[j].Register.Absolute);
 			return -EINVAL;
-- 
cgit v1.2.3


From 92f5c7a597aaf098f4e6b4793e4b89ae539e328a Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 30 Aug 2010 16:09:39 +1000
Subject: r600g: add SCS support.

---
 src/gallium/drivers/r600/r600_shader.c | 75 +++++++++++++++++++++++++++++++---
 1 file changed, 69 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 9a4e39e2cc..15dc406479 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -743,14 +743,14 @@ static int tgsi_op2_swap(struct r600_shader_ctx *ctx)
  * r700 - normalize by dividing by 2PI
  * see fdo bug 27901
  */
-static int tgsi_trig(struct r600_shader_ctx *ctx)
+static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
+			   struct r600_bc_alu_src r600_src[3])
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
-	struct r600_bc_alu_src r600_src[3];
-	struct r600_bc_alu alu;
-	int i, r;
+	int r;
 	uint32_t lit_vals[4];
-
+	struct r600_bc_alu alu;
+	
 	memset(lit_vals, 0, 4*4);
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
@@ -823,6 +823,23 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 	if (r)
 		return r;
 	r = r600_bc_add_literal(ctx->bc, lit_vals);
+	if (r)
+		return r;
+	return 0;
+}
+
+static int tgsi_trig(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
+	struct r600_bc_alu alu;
+	int i, r;
+
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+
+	r = tgsi_setup_trig(ctx, r600_src);
 	if (r)
 		return r;
 
@@ -858,6 +875,52 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_scs(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu_src r600_src[3];
+	struct r600_bc_alu alu;
+	int r;
+
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+
+	r = tgsi_setup_trig(ctx, r600_src);
+	if (r)
+		return r;
+
+
+	/* dst.x = COS */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS;
+	r = tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+	if (r)
+		return r;
+
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 0;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+
+	/* dst.y = SIN */
+	memset(&alu, 0, sizeof(struct r600_bc_alu));
+	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN;
+	r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+	if (r)
+		return r;
+
+	alu.src[0].sel = ctx->temp_reg;
+	alu.src[0].chan = 0;
+	alu.last = 1;
+	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	return 0;
+}
+
 static int tgsi_kill(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -2146,7 +2209,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_RET,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_SSG,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_ssg},
 	{TGSI_OPCODE_CMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_cmp},
-	{TGSI_OPCODE_SCS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_SCS,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_scs},
 	{TGSI_OPCODE_TXB,	0, SQ_TEX_INST_SAMPLE_L, tgsi_tex},
 	{TGSI_OPCODE_NRM,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
 	{TGSI_OPCODE_DIV,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
-- 
cgit v1.2.3


From 57eecbbf6c57fbf5a46b8b81d8d4fbb6bd78ea12 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Mon, 30 Aug 2010 16:22:54 +1000
Subject: r600g: add DST opcode support.

---
 src/gallium/drivers/r600/r600_shader.c | 42 +++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 15dc406479..23b3eabf52 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1861,6 +1861,46 @@ static int tgsi_arl(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int tgsi_opdst(struct r600_shader_ctx *ctx)
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int i, r = 0;
+
+	for (i = 0; i < 4; i++) {
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
+		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+		if (r)
+			return r;
+	
+	        if (i == 0 || i == 3) {
+			alu.src[0].sel = V_SQ_ALU_SRC_1;
+		} else {
+			r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+			if (r)
+				return r;
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], i);
+		}
+
+	        if (i == 0 || i == 2) {
+			alu.src[1].sel = V_SQ_ALU_SRC_1;
+		} else {
+			r = tgsi_src(ctx, &inst->Src[1], &alu.src[1]);
+			if (r)
+				return r;
+			alu.src[1].chan = tgsi_chan(&inst->Src[1], i);
+		}
+		if (i == 3)
+			alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+	}
+	return 0;
+}
+
 static int emit_logic_pred(struct r600_shader_ctx *ctx, int opcode)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -2150,7 +2190,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
 	{TGSI_OPCODE_ADD,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ADD, tgsi_op2},
 	{TGSI_OPCODE_DP3,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
 	{TGSI_OPCODE_DP4,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4, tgsi_dp},
-	{TGSI_OPCODE_DST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
+	{TGSI_OPCODE_DST,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_opdst},
 	{TGSI_OPCODE_MIN,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MIN, tgsi_op2},
 	{TGSI_OPCODE_MAX,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX, tgsi_op2},
 	{TGSI_OPCODE_SLT,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SETGT, tgsi_op2_swap},
-- 
cgit v1.2.3


From 77dac1945f0f8122dc933b45e407f6137c757f1d Mon Sep 17 00:00:00 2001
From: Marek Olšák <maraeo@gmail.com>
Date: Mon, 30 Aug 2010 13:25:07 +0200
Subject: r300g: fix warning in winsys

---
 src/gallium/drivers/r300/r300_winsys.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r300/r300_winsys.h b/src/gallium/drivers/r300/r300_winsys.h
index 187780750f..4597332399 100644
--- a/src/gallium/drivers/r300/r300_winsys.h
+++ b/src/gallium/drivers/r300/r300_winsys.h
@@ -33,6 +33,7 @@
 
 #include "r300_defines.h"
 
+struct winsys_handle;
 struct r300_winsys_screen;
 
 struct r300_winsys_buffer;
-- 
cgit v1.2.3


From 5a70db643295e99ca3f821a34abe474d56a6c872 Mon Sep 17 00:00:00 2001
From: José Fonseca <jfonseca@vmware.com>
Date: Sun, 15 Aug 2010 13:36:02 +0100
Subject: svga: Re-emit bound rendertargets and texture samplers at the
 beginning of every command buffer.

Only non null resources.

To ensure that relocations are emitted for every resource currently
referred.
---
 src/gallium/drivers/svga/svga_context.c           |  5 +++++
 src/gallium/drivers/svga/svga_context.h           |  1 +
 src/gallium/drivers/svga/svga_state_framebuffer.c | 15 ++++++++++-----
 src/gallium/drivers/svga/svga_state_tss.c         | 14 +++++++++++---
 4 files changed, 27 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/svga/svga_context.c b/src/gallium/drivers/svga/svga_context.c
index 3b30b9e341..cd3f6b8982 100644
--- a/src/gallium/drivers/svga/svga_context.c
+++ b/src/gallium/drivers/svga/svga_context.c
@@ -214,6 +214,11 @@ void svga_context_flush( struct svga_context *svga,
 
    svga_screen_cache_flush(svgascreen, fence);
 
+   /* To force the reemission of rendertargets and texture bindings at
+    * the beginning of every command buffer.
+    */
+   svga->dirty |= SVGA_NEW_COMMAND_BUFFER;
+
    if (SVGA_DEBUG & DEBUG_SYNC) {
       if (fence)
          svga->pipe.screen->fence_finish( svga->pipe.screen, fence, 0);
diff --git a/src/gallium/drivers/svga/svga_context.h b/src/gallium/drivers/svga/svga_context.h
index 67a7614c8a..1fb5a04887 100644
--- a/src/gallium/drivers/svga/svga_context.h
+++ b/src/gallium/drivers/svga/svga_context.h
@@ -382,6 +382,7 @@ struct svga_context
 #define SVGA_NEW_ZERO_STRIDE         0x2000000
 #define SVGA_NEW_TEXTURE_FLAGS       0x4000000
 #define SVGA_NEW_STENCIL_REF         0x8000000
+#define SVGA_NEW_COMMAND_BUFFER      0x10000000
 
 
 
diff --git a/src/gallium/drivers/svga/svga_state_framebuffer.c b/src/gallium/drivers/svga/svga_state_framebuffer.c
index bd92f00343..fcbb35e797 100644
--- a/src/gallium/drivers/svga/svga_state_framebuffer.c
+++ b/src/gallium/drivers/svga/svga_state_framebuffer.c
@@ -43,15 +43,18 @@ static int emit_framebuffer( struct svga_context *svga,
 {
    const struct pipe_framebuffer_state *curr = &svga->curr.framebuffer;
    struct pipe_framebuffer_state *hw = &svga->state.hw_clear.framebuffer;
+   boolean reemit = !!(dirty & SVGA_NEW_COMMAND_BUFFER);
    unsigned i;
    enum pipe_error ret;
 
-   /* XXX: Need shadow state in svga->hw to eliminate redundant
-    * uploads, especially of NULL buffers.
+   /*
+    * We need to reemit non-null surface bindings, even when they are not
+    * dirty, to ensure that the resources are paged in.
     */
    
    for(i = 0; i < PIPE_MAX_COLOR_BUFS; ++i) {
-      if (curr->cbufs[i] != hw->cbufs[i]) {
+      if (curr->cbufs[i] != hw->cbufs[i] ||
+          (reemit && hw->cbufs[i])) {
          if (svga->curr.nr_fbs++ > 8)
             return PIPE_ERROR_OUT_OF_MEMORY;
 
@@ -64,7 +67,8 @@ static int emit_framebuffer( struct svga_context *svga,
    }
 
    
-   if (curr->zsbuf != hw->zsbuf) {
+   if (curr->zsbuf != hw->zsbuf ||
+       (reemit && hw->zsbuf)) {
       ret = SVGA3D_SetRenderTarget(svga->swc, SVGA3D_RT_DEPTH, curr->zsbuf);
       if (ret != PIPE_OK)
          return ret;
@@ -92,7 +96,8 @@ static int emit_framebuffer( struct svga_context *svga,
 struct svga_tracked_state svga_hw_framebuffer = 
 {
    "hw framebuffer state",
-   SVGA_NEW_FRAME_BUFFER,
+   SVGA_NEW_FRAME_BUFFER |
+   SVGA_NEW_COMMAND_BUFFER,
    emit_framebuffer
 };
 
diff --git a/src/gallium/drivers/svga/svga_state_tss.c b/src/gallium/drivers/svga/svga_state_tss.c
index e42c4f7fce..4a50b19474 100644
--- a/src/gallium/drivers/svga/svga_state_tss.c
+++ b/src/gallium/drivers/svga/svga_state_tss.c
@@ -56,6 +56,7 @@ static int
 update_tss_binding(struct svga_context *svga, 
                    unsigned dirty )
 {
+   boolean reemit = !!(dirty & SVGA_NEW_COMMAND_BUFFER);
    unsigned i;
    unsigned count = MAX2( svga->curr.num_sampler_views,
                           svga->state.hw_draw.num_views );
@@ -107,12 +108,18 @@ update_tss_binding(struct svga_context *svga,
                                                 max_lod);
       }
 
-      if (view->dirty) {
+      /*
+       * We need to reemit non-null texture bindings, even when they are not
+       * dirty, to ensure that the resources are paged in.
+       */
+
+      if (view->dirty ||
+          (reemit && view->v)) {
          queue.bind[queue.bind_count].unit = i;
          queue.bind[queue.bind_count].view = view;
          queue.bind_count++;
       } 
-      else if (view->v) {
+      if (!view->dirty && view->v) {
          svga_validate_sampler_view(svga, view->v);
       }
    }
@@ -160,7 +167,8 @@ fail:
 struct svga_tracked_state svga_hw_tss_binding = {
    "texture binding emit",
    SVGA_NEW_TEXTURE_BINDING |
-   SVGA_NEW_SAMPLER,
+   SVGA_NEW_SAMPLER |
+   SVGA_NEW_COMMAND_BUFFER,
    update_tss_binding
 };
 
-- 
cgit v1.2.3


From 1bb97610e969918015f46efe6fe32c6c71a8293a Mon Sep 17 00:00:00 2001
From: Michal Krol <michal@vmware.com>
Date: Fri, 27 Aug 2010 13:24:47 +0200
Subject: svga: Fix CMP translation for vertex shader targets.

SVGA3DOP_CMP is not supported for vertex shaders;
use SLT + LRP instead.
---
 src/gallium/drivers/svga/svga_tgsi_insn.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/svga/svga_tgsi_insn.c b/src/gallium/drivers/svga/svga_tgsi_insn.c
index 67e1f22a70..72dccdf150 100644
--- a/src/gallium/drivers/svga/svga_tgsi_insn.c
+++ b/src/gallium/drivers/svga/svga_tgsi_insn.c
@@ -806,6 +806,20 @@ static boolean emit_cmp(struct svga_shader_emitter *emit,
    const struct src_register src2 = translate_src_register(
       emit, &insn->Src[2] );
 
+   if (emit->unit == PIPE_SHADER_VERTEX) {
+      SVGA3dShaderDestToken temp = get_temp(emit);
+      struct src_register zero = scalar(get_zero_immediate(emit), TGSI_SWIZZLE_X);
+
+      /* Since vertex shaders don't support the CMP instruction,
+       * simulate it with SLT and LRP instructions.
+       *    SLT  TMP, SRC0, 0.0
+       *    LRP  DST, TMP, SRC1, SRC2
+       */
+      if (!submit_op2(emit, inst_token(SVGA3DOP_SLT), temp, src0, zero))
+         return FALSE;
+      return submit_op3(emit, inst_token(SVGA3DOP_LRP), dst, src(temp), src1, src2);
+   }
+
    /* CMP  DST, SRC0, SRC2, SRC1 */
    return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst, src0, src2, src1);
 }
@@ -2682,6 +2696,11 @@ needs_to_create_zero( struct svga_shader_emitter *emit )
          return TRUE;
    }
 
+   if (emit->unit == PIPE_SHADER_VERTEX) {
+      if (emit->info.opcode_count[TGSI_OPCODE_CMP] >= 1)
+         return TRUE;
+   }
+
    if (emit->info.opcode_count[TGSI_OPCODE_IF] >= 1 ||
        emit->info.opcode_count[TGSI_OPCODE_BGNLOOP] >= 1 ||
        emit->info.opcode_count[TGSI_OPCODE_DDX] >= 1 ||
-- 
cgit v1.2.3


From 69c30f5d6d429be4f7e211867984dab1a33da79c Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 26 Aug 2010 14:55:48 +1000
Subject: r600g: fixup states generation in winsys.

The current states code had an unhealthy relationship between
that had to somehow magically align themselves, editing either
place meant renumbering all states after the one you were on,
and it was pretty unapproachable code.

This replaces the huge types structures with a simple type + sub
type struct, which is keyed on an stype enum in radeon.h. Each
stype can have a per-shader type subclassing (4 types supported,
PS/VS/GS/FS), and also has a number of states per-subtype. So you
have 256 constants per 4 shaders per one CONSTANT stype.

The interface from the driver is changed to pass in the tuple,
(stype, id, shader_type), and we look for this. If
radeon_state_shader ever shows up on profile, it could use a
hashtable based on stype/shader_type to speed things up.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c       |  23 +++--
 src/gallium/drivers/r600/r600_context.c    |   2 +-
 src/gallium/drivers/r600/r600_draw.c       |  11 ++-
 src/gallium/drivers/r600/r600_query.c      |   4 +-
 src/gallium/drivers/r600/r600_shader.c     |   4 +-
 src/gallium/drivers/r600/r600_state.c      |  38 ++++----
 src/gallium/drivers/r600/r600_texture.c    |   8 +-
 src/gallium/drivers/r600/radeon.h          | 112 ++++++++--------------
 src/gallium/winsys/r600/drm/r600_state.c   | 133 ++++++++++++++++++++------
 src/gallium/winsys/r600/drm/r600_states.h  | 144 +++++++----------------------
 src/gallium/winsys/r600/drm/radeon.c       |  44 ---------
 src/gallium/winsys/r600/drm/radeon_ctx.c   |   6 +-
 src/gallium/winsys/r600/drm/radeon_draw.c  |  11 ++-
 src/gallium/winsys/r600/drm/radeon_priv.h  |  32 +++----
 src/gallium/winsys/r600/drm/radeon_state.c |  58 +++++++++---
 15 files changed, 295 insertions(+), 335 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 72175fbbd5..6b8487695c 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -190,7 +190,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	memcpy(bo->data, vbo, 128);
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 0);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return -ENOMEM;
@@ -215,7 +215,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	}
 	bstates->vs_resource0 = rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + 1);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
 	if (rstate == NULL) {
 		return -ENOMEM;
 	}
@@ -303,7 +303,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return NULL;
@@ -374,7 +374,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
 	if (rstate == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
 		return NULL;
@@ -403,8 +403,7 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
-	if (rstate == NULL)
+	rstate = radeon_state(rscreen->rw, R600_STATE_VGT, 0); if (rstate == NULL)
 		return NULL;
 
 	/* set states (most default value are 0 and struct already
@@ -425,7 +424,7 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	rstate = radeon_state(rscreen->rw, R600_STATE_DRAW, 0);
 	if (rstate == NULL)
 		return NULL;
 
@@ -448,7 +447,7 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VS_CONSTANT_TYPE, R600_VS_CONSTANT + id);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
 	if (rstate == NULL)
 		return NULL;
 
@@ -471,7 +470,7 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
+	rstate = radeon_state(rscreen->rw, R600_STATE_RASTERIZER, 0);
 	if (rstate == NULL)
 		return NULL;
 
@@ -500,7 +499,7 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	rstate = radeon_state(rscreen->rw, R600_STATE_DSA, 0);
 	if (rstate == NULL)
 		return NULL;
 
@@ -524,7 +523,7 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
+	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
 	if (rstate == NULL)
 		return NULL;
 
@@ -543,7 +542,7 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB_CNTL, 0);
 	if (rstate == NULL)
 		return NULL;
 
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 9af28356c5..db170122dd 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -218,7 +218,7 @@ static void r600_init_config(struct r600_context *rctx)
 		num_es_stack_entries = 0;
 		break;
 	}
-	rctx->hw_states.config = radeon_state(rctx->rw, R600_CONFIG_TYPE, R600_CONFIG);
+	rctx->hw_states.config = radeon_state(rctx->rw, R600_STATE_CONFIG, 0);
 
 	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 1c426f755d..88f93bca7b 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -101,7 +101,7 @@ static int r600_draw_common(struct r600_draw *draw)
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		vs_resource = radeon_state(rscreen->rw, R600_VS_RESOURCE_TYPE, R600_VS_RESOURCE + i);
+		vs_resource = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, i, R600_SHADER_VS);
 		if (vs_resource == NULL)
 			return -ENOMEM;
 		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@@ -121,7 +121,7 @@ static int r600_draw_common(struct r600_draw *draw)
 			return r;
 	}
 	/* FIXME start need to change winsys */
-	draw->draw = radeon_state(rscreen->rw, R600_DRAW_TYPE, R600_DRAW);
+	draw->draw = radeon_state(rscreen->rw, R600_STATE_DRAW, 0);
 	if (draw->draw == NULL)
 		return -ENOMEM;
 	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
@@ -136,7 +136,7 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = radeon_draw_set_new(rctx->draw, draw->draw);
 	if (r)
 		return r;
-	draw->vgt = radeon_state(rscreen->rw, R600_VGT_TYPE, R600_VGT);
+	draw->vgt = radeon_state(rscreen->rw, R600_STATE_VGT, 0);
 	if (draw->vgt == NULL)
 		return -ENOMEM;
 	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
@@ -169,6 +169,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_draw draw;
+	int r;
 
 	assert(info->index_bias == 0);
 
@@ -189,5 +190,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 		draw.index_size = 0;
 		draw.index_buffer = NULL;
 	}
-	r600_draw_common(&draw);
+	r = r600_draw_common(&draw);
+	if (r)
+	  fprintf(stderr,"draw common failed %d\n", r);
 }
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index 5929606cd2..af857101e3 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -36,7 +36,7 @@ static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
+	rstate = radeon_state(rscreen->rw, R600_STATE_QUERY_BEGIN, 0);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
@@ -55,7 +55,7 @@ static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r60
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
+	rstate = radeon_state(rscreen->rw, R600_STATE_QUERY_END, 0);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 23b3eabf52..652d4035cc 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -134,7 +134,7 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	unsigned i, tmp;
 
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
+	state = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < 10; i++) {
@@ -168,7 +168,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 
 	rasterizer = &rctx->rasterizer->state.rasterizer;
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
+	state = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
 	if (state == NULL)
 		return -ENOMEM;
 	for (i = 0; i < rshader->ninput; i++) {
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 441be8fd6d..b5db848e35 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -283,19 +283,19 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
-	unsigned nconstant = 0, i, type, id;
+	unsigned nconstant = 0, i, type, shader_class;
 	struct radeon_state *rstate;
 	struct pipe_transfer *transfer;
 	u32 *ptr;
 
+	type = R600_STATE_CONSTANT;
+
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
-		id = R600_VS_CONSTANT;
-		type = R600_VS_CONSTANT_TYPE;
+		shader_class = R600_SHADER_VS;
 		break;
 	case PIPE_SHADER_FRAGMENT:
-		id = R600_PS_CONSTANT;
-		type = R600_PS_CONSTANT_TYPE;
+		shader_class = R600_SHADER_PS;
 		break;
 	default:
 		R600_ERR("unsupported %d\n", shader);
@@ -307,7 +307,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		if (ptr == NULL)
 			return;
 		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state(rscreen->rw, type, id + i);
+			rstate = radeon_state_shader(rscreen->rw, type, i, shader_class);
 			if (rstate == NULL)
 				return;
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
@@ -622,7 +622,7 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
 
-	rstate = radeon_state(rscreen->rw, R600_BLEND_TYPE, R600_BLEND);
+	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
@@ -681,7 +681,7 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
 	struct radeon_state *rstate;
 	const struct pipe_clip_state *state = &rctx->clip->state.clip;
 
-	rstate = radeon_state(rscreen->rw, R600_CLIP_TYPE, R600_CLIP + clip);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CLIP, clip);
 	if (rstate == NULL)
 		return NULL;
 
@@ -711,7 +711,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE + cb, R600_CB0 + cb);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
 	if (rstate == NULL)
 		return NULL;
 	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
@@ -768,7 +768,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	if (state->zsbuf == NULL)
 		return NULL;
 
-	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
 	if (rstate == NULL)
 		return NULL;
 
@@ -844,7 +844,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		prov_vtx = 0;
 
 	rctx->flat_shade = state->flatshade;
-	rstate = radeon_state(rscreen->rw, R600_RASTERIZER_TYPE, R600_RASTERIZER);
+	rstate = radeon_state(rscreen->rw, R600_STATE_RASTERIZER, 0);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
@@ -925,7 +925,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	}
 	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	rstate = radeon_state(rscreen->rw, R600_STATE_SCISSOR, 0);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
@@ -960,7 +960,7 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx)
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	rstate = radeon_state(rscreen->rw, R600_STATE_VIEWPORT, 0);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
@@ -993,7 +993,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	if (rctx->ps_shader == NULL) {
 		return NULL;
 	}
-	rstate = radeon_state(rscreen->rw, R600_DSA_TYPE, R600_DSA);
+	rstate = radeon_state(rscreen->rw, R600_STATE_DSA, 0);
 	if (rstate == NULL)
 		return NULL;
 
@@ -1147,7 +1147,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_PS_SAMPLER_TYPE, id);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
 	if (rstate == NULL)
 		return NULL;
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
@@ -1248,7 +1248,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 		R600_ERR("unknow format %d\n", view->texture->format);
 		return NULL;
 	}
-	rstate = radeon_state(rscreen->rw, R600_PS_RESOURCE_TYPE, id);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
 	if (rstate == NULL) {
 		return NULL;
 	}
@@ -1344,7 +1344,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
-	rstate = radeon_state(rscreen->rw, R600_CB_CNTL_TYPE, R600_CB_CNTL);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB_CNTL, 0);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1421,7 +1421,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 		if (rctx->ps_sampler[i]) {
 			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
 							&rctx->ps_sampler[i]->state.sampler,
-							R600_PS_SAMPLER + i);
+							i);
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
@@ -1429,7 +1429,7 @@ int r600_context_hw_states(struct pipe_context *ctx)
 		if (rctx->ps_sampler_view[i]) {
 			rctx->hw_states.ps_resource[i] = r600_resource(ctx,
 							&rctx->ps_sampler_view[i]->state.sampler_view,
-							R600_PS_RESOURCE + i);
+							i);
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index fb84ed9cfe..77d627cdc8 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -663,7 +663,7 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_SCISSOR_TYPE, R600_SCISSOR);
+	rstate = radeon_state(rscreen->rw, R600_STATE_SCISSOR, 0);
 	if (rstate == NULL)
 		return NULL;
 
@@ -707,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_CB0_TYPE, R600_CB0);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB0, 0);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -766,7 +766,7 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	struct r600_resource *rbuffer;
 	unsigned pitch, slice, format;
 
-	rstate = radeon_state(rscreen->rw, R600_DB_TYPE, R600_DB);
+	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -815,7 +815,7 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 {
 	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
+	rstate = radeon_state(rscreen->rw, R600_STATE_VIEWPORT, 0);
 	if (rstate == NULL)
 		return NULL;
 
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index b2cc74f696..046c264c04 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -98,14 +98,16 @@ struct radeon_bo *radeon_bo_incref(struct radeon *radeon, struct radeon_bo *bo);
 struct radeon_bo *radeon_bo_decref(struct radeon *radeon, struct radeon_bo *bo);
 int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
 
+struct radeon_stype_info;
 /*
  * states functions
  */
 struct radeon_state {
 	struct radeon			*radeon;
 	unsigned			refcount;
-	unsigned			type;
+	struct radeon_stype_info        *stype;
 	unsigned			id;
+	unsigned                        shader_index;
 	unsigned			nstates;
 	u32				*states;
 	unsigned			npm4;
@@ -124,6 +126,7 @@ struct radeon_state {
 };
 
 struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
+struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 type, u32 id, u32 shader_class);
 struct radeon_state *radeon_state_incref(struct radeon_state *state);
 struct radeon_state *radeon_state_decref(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
@@ -192,79 +195,42 @@ struct radeon_ctx {
  * R600/R700
  */
 
-#define R600_NSTATE				1288
-#define R600_NTYPE				35
+enum r600_stype {
+	R600_STATE_CONFIG,  
+	R600_STATE_CB_CNTL,
+	R600_STATE_RASTERIZER,
+	R600_STATE_VIEWPORT,
+	R600_STATE_SCISSOR,
+	R600_STATE_BLEND,
+	R600_STATE_DSA,
+	R600_STATE_SHADER,          /* has PS,VS,GS,FS variants */
+	R600_STATE_CONSTANT,        /* has PS,VS,GS,FS variants */
+	R600_STATE_RESOURCE,        /* has PS,VS,GS,FS variants */
+	R600_STATE_SAMPLER,         /* has PS,VS,GS,FS variants */
+	R600_STATE_SAMPLER_BORDER,  /* has PS,VS,GS,FS variants */
+	R600_STATE_CB0,
+	R600_STATE_CB1,
+	R600_STATE_CB2,
+	R600_STATE_CB3,
+	R600_STATE_CB4,
+	R600_STATE_CB5,
+	R600_STATE_CB6,
+	R600_STATE_CB7,
+	R600_STATE_DB,
+	R600_STATE_QUERY_BEGIN,
+	R600_STATE_QUERY_END,
+	R600_STATE_CLIP,
+	R600_STATE_VGT,
+	R600_STATE_DRAW,
+};
 
-#define R600_CONFIG				0
-#define R600_CONFIG_TYPE				0
-#define R600_CB_CNTL				1
-#define R600_CB_CNTL_TYPE				1
-#define R600_RASTERIZER				2
-#define R600_RASTERIZER_TYPE				2
-#define R600_VIEWPORT				3
-#define R600_VIEWPORT_TYPE				3
-#define R600_SCISSOR				4
-#define R600_SCISSOR_TYPE				4
-#define R600_BLEND				5
-#define R600_BLEND_TYPE				5
-#define R600_DSA				6
-#define R600_DSA_TYPE				6
-#define R600_VS_SHADER				7
-#define R600_VS_SHADER_TYPE				7
-#define R600_PS_SHADER				8
-#define R600_PS_SHADER_TYPE				8
-#define R600_PS_CONSTANT				9
-#define R600_PS_CONSTANT_TYPE				9
-#define R600_VS_CONSTANT				265
-#define R600_VS_CONSTANT_TYPE				10
-#define R600_PS_RESOURCE				521
-#define R600_PS_RESOURCE_TYPE				11
-#define R600_VS_RESOURCE				681
-#define R600_VS_RESOURCE_TYPE				12
-#define R600_FS_RESOURCE				841
-#define R600_FS_RESOURCE_TYPE				13
-#define R600_GS_RESOURCE				1001
-#define R600_GS_RESOURCE_TYPE				14
-#define R600_PS_SAMPLER				1161
-#define R600_PS_SAMPLER_TYPE				15
-#define R600_VS_SAMPLER				1179
-#define R600_VS_SAMPLER_TYPE				16
-#define R600_GS_SAMPLER				1197
-#define R600_GS_SAMPLER_TYPE				17
-#define R600_PS_SAMPLER_BORDER				1215
-#define R600_PS_SAMPLER_BORDER_TYPE				18
-#define R600_VS_SAMPLER_BORDER				1233
-#define R600_VS_SAMPLER_BORDER_TYPE				19
-#define R600_GS_SAMPLER_BORDER				1251
-#define R600_GS_SAMPLER_BORDER_TYPE				20
-#define R600_CB0				1269
-#define R600_CB0_TYPE				21
-#define R600_CB1				1270
-#define R600_CB1_TYPE				22
-#define R600_CB2				1271
-#define R600_CB2_TYPE				23
-#define R600_CB3				1272
-#define R600_CB3_TYPE				24
-#define R600_CB4				1273
-#define R600_CB4_TYPE				25
-#define R600_CB5				1274
-#define R600_CB5_TYPE				26
-#define R600_CB6				1275
-#define R600_CB6_TYPE				27
-#define R600_CB7				1276
-#define R600_CB7_TYPE				28
-#define R600_QUERY_BEGIN			1277
-#define R600_QUERY_BEGIN_TYPE			29
-#define R600_QUERY_END				1278
-#define R600_QUERY_END_TYPE			30
-#define R600_DB					1279
-#define R600_DB_TYPE				31
-#define R600_CLIP				1280
-#define R600_CLIP_TYPE				32
-#define R600_VGT				1286
-#define R600_VGT_TYPE				33
-#define R600_DRAW				1287
-#define R600_DRAW_TYPE				34
+enum {
+	R600_SHADER_PS = 1,
+	R600_SHADER_VS,
+	R600_SHADER_GS,
+	R600_SHADER_FS,
+	R600_SHADER_MAX = R600_SHADER_FS,
+};
 
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index 9b7c11bdc0..e3d0116a2d 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -30,6 +30,8 @@
 #include "radeon_priv.h"
 #include "r600d.h"
 
+#include "util/u_memory.h"
+
 static int r600_state_pm4_resource(struct radeon_state *state);
 static int r600_state_pm4_cb0(struct radeon_state *state);
 static int r600_state_pm4_vgt(struct radeon_state *state);
@@ -46,18 +48,61 @@ static int r700_state_pm4_db(struct radeon_state *state);
 
 #include "r600_states.h"
 
+
+#define SUB_NONE(param) { { 0, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } }
+#define SUB_PS(param) { R600_SHADER_PS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+#define SUB_VS(param) { R600_SHADER_VS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+#define SUB_GS(param) { R600_SHADER_GS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+#define SUB_FS(param) { R600_SHADER_FS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
+
+/* some of these are overriden at runtime for R700 */
+struct radeon_stype_info r600_stypes[] = {
+	{ R600_STATE_CONFIG, 1, 0, r600_state_pm4_config, SUB_NONE(CONFIG), },
+	{ R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, SUB_NONE(CB_CNTL) },
+	{ R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, SUB_NONE(RASTERIZER) },
+	{ R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, SUB_NONE(VIEWPORT) },
+	{ R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, SUB_NONE(SCISSOR) },
+	{ R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, SUB_NONE(BLEND), },
+	{ R600_STATE_DSA, 1, 0, r600_state_pm4_generic, SUB_NONE(DSA), },
+	{ R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { SUB_PS(PS_SHADER), SUB_VS(VS_SHADER) } },
+	{ R600_STATE_CONSTANT, 256, 0x10, r600_state_pm4_generic,  { SUB_PS(PS_CONSTANT), SUB_VS(VS_CONSTANT) } },
+	{ R600_STATE_RESOURCE, 160, 0x1c, r600_state_pm4_resource, { SUB_PS(PS_RESOURCE), SUB_VS(VS_RESOURCE), SUB_GS(GS_RESOURCE), SUB_FS(FS_RESOURCE)} },
+	{ R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER), SUB_VS(VS_SAMPLER), SUB_GS(GS_SAMPLER) } },
+	{ R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER_BORDER), SUB_VS(VS_SAMPLER_BORDER), SUB_GS(GS_SAMPLER_BORDER) } },
+	{ R600_STATE_CB0, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB0) },
+	{ R600_STATE_CB1, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB1) },
+	{ R600_STATE_CB2, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB2) },
+	{ R600_STATE_CB3, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB3) },
+	{ R600_STATE_CB4, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB4) },
+	{ R600_STATE_CB5, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB5) },
+	{ R600_STATE_CB6, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB6) },
+	{ R600_STATE_CB7, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB7) },
+	{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
+	{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
+	{ R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
+	{ R600_STATE_CLIP, 6, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
+	{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
+	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
+};
+#define STYPES_SIZE Elements(r600_stypes)
+
+static const struct radeon_register *get_regs(struct radeon_state *state)
+{
+	return state->stype->reginfo[state->shader_index].regs;
+}
+
 /*
  * r600/r700 state functions
  */
 static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
 {
-	const struct radeon_register *regs = state->radeon->type[state->type].regs;
+	const struct radeon_register *regs = get_regs(state);
 	unsigned i;
 	int r;
 
 	if (!offset) {
 		fprintf(stderr, "%s invalid register for state %d %d\n",
-			__func__, state->type, id);
+			__func__, state->stype->stype, id);
 		return -EINVAL;
 	}
 	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
@@ -116,19 +161,18 @@ static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset,
 
 static int r600_state_pm4_generic(struct radeon_state *state)
 {
-	struct radeon *radeon = state->radeon;
-	unsigned i, offset, nreg, type, coffset, loffset, soffset;
+	const struct radeon_register *regs = get_regs(state);
+	unsigned i, offset, nreg, coffset, loffset, soffset;
 	unsigned start;
 	int r;
 
 	if (!state->nstates)
 		return 0;
-	type = state->type;
-	soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride;
-	offset = loffset = radeon->type[type].regs[0].offset + soffset;
+	soffset = state->id * state->stype->stride;
+	offset = loffset = regs[0].offset + soffset;
 	start = 0;
 	for (i = 1, nreg = 1; i < state->nstates; i++) {
-		coffset = radeon->type[type].regs[i].offset + soffset;
+		coffset = regs[i].offset + soffset;
 		if (coffset == (loffset + 4)) {
 			nreg++;
 			loffset = coffset;
@@ -358,8 +402,9 @@ static int r600_state_pm4_resource(struct radeon_state *state)
 {
 	u32 flags, type, nbo, offset, soffset;
 	int r;
+	const struct radeon_register *regs = get_regs(state);
 
-	soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride;
+	soffset = state->id * state->stype->stride;
 	type = G_038018_TYPE(state->states[6]);
 	switch (type) {
 	case 2:
@@ -378,7 +423,7 @@ static int r600_state_pm4_resource(struct radeon_state *state)
 		return -EINVAL;
 	}
 	r600_state_pm4_with_flush(state, flags);
-	offset = state->radeon->type[state->type].regs[0].offset + soffset;
+	offset = regs[0].offset + soffset;
 	state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7);
 	state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
 	state->pm4[state->cpm4++] = state->states[0];
@@ -403,33 +448,63 @@ static int r600_state_pm4_resource(struct radeon_state *state)
 	return 0;
 }
 
-int r600_init(struct radeon *radeon)
+
+static void r600_modify_type_array(struct radeon *radeon)
 {
+	int i;
 	switch (radeon->family) {
-	case CHIP_R600:
-	case CHIP_RV610:
-	case CHIP_RV630:
-	case CHIP_RV670:
-	case CHIP_RV620:
-	case CHIP_RV635:
-	case CHIP_RS780:
-	case CHIP_RS880:
-		radeon->ntype = R600_NTYPE;
-		radeon->nstate = R600_NSTATE;
-		radeon->type = R600_types;
-		break;
 	case CHIP_RV770:
 	case CHIP_RV730:
 	case CHIP_RV710:
 	case CHIP_RV740:
-		radeon->ntype = R600_NTYPE;
-		radeon->nstate = R600_NSTATE;
-		radeon->type = R700_types;
 		break;
 	default:
-		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
-			__func__, radeon->device);
-		return -EINVAL;
+		return;
+	}
+
+	/* r700 needs some mods */
+	for (i = 0; i < radeon->nstype; i++) {
+		struct radeon_stype_info *info = &radeon->stype[i];
+		
+		switch(info->stype) {
+		case R600_STATE_CONFIG:
+			info->pm4 = r700_state_pm4_config;
+			break;
+		case R600_STATE_CB0:
+			info->pm4 = r700_state_pm4_cb0;
+			break;
+		case R600_STATE_DB:
+			info->pm4 = r700_state_pm4_db;
+		};
 	}
+}
+
+static void r600_build_types_array(struct radeon *radeon)
+{
+	int i, j;
+	int id = 0;
+
+	for (i = 0; i < STYPES_SIZE; i++) {
+		r600_stypes[i].base_id = id;
+		r600_stypes[i].npm4 = 128;
+		if (r600_stypes[i].reginfo[0].shader_type == 0) {
+			id += r600_stypes[i].num;
+		} else {
+			for (j = 0; j < R600_SHADER_MAX; j++) {
+				if (r600_stypes[i].reginfo[j].shader_type)
+					id += r600_stypes[i].num;					
+			}
+		}
+	}
+	radeon->nstate = id;
+	radeon->stype = r600_stypes;
+	radeon->nstype = STYPES_SIZE;
+
+	r600_modify_type_array(radeon);
+}
+
+int r600_init(struct radeon *radeon)
+{
+	r600_build_types_array(radeon);
 	return 0;
 }
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index b5365e4275..51b69b9220 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -17,7 +17,7 @@
 #ifndef R600_STATES_H
 #define R600_STATES_H
 
-static const struct radeon_register R600_CONFIG_names[] = {
+static const struct radeon_register R600_names_CONFIG[] = {
 	{0x00008C00, 0, 0, "SQ_CONFIG"},
 	{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
 	{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
@@ -61,7 +61,7 @@ static const struct radeon_register R600_CONFIG_names[] = {
 	{0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
 };
 
-static const struct radeon_register R600_CB_CNTL_names[] = {
+static const struct radeon_register R600_names_CB_CNTL[] = {
 	{0x00028120, 0, 0, "CB_CLEAR_RED"},
 	{0x00028124, 0, 0, "CB_CLEAR_GREEN"},
 	{0x00028128, 0, 0, "CB_CLEAR_BLUE"},
@@ -82,7 +82,7 @@ static const struct radeon_register R600_CB_CNTL_names[] = {
 	{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
 };
 
-static const struct radeon_register R600_RASTERIZER_names[] = {
+static const struct radeon_register R600_names_RASTERIZER[] = {
 	{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
 	{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
 	{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
@@ -106,7 +106,7 @@ static const struct radeon_register R600_RASTERIZER_names[] = {
 	{0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
 };
 
-static const struct radeon_register R600_VIEWPORT_names[] = {
+static const struct radeon_register R600_names_VIEWPORT[] = {
 	{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
 	{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
 	{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
@@ -118,7 +118,7 @@ static const struct radeon_register R600_VIEWPORT_names[] = {
 	{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
 };
 
-static const struct radeon_register R600_SCISSOR_names[] = {
+static const struct radeon_register R600_names_SCISSOR[] = {
 	{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
 	{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
 	{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
@@ -140,7 +140,7 @@ static const struct radeon_register R600_SCISSOR_names[] = {
 	{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
 };
 
-static const struct radeon_register R600_BLEND_names[] = {
+static const struct radeon_register R600_names_BLEND[] = {
 	{0x00028414, 0, 0, "CB_BLEND_RED"},
 	{0x00028418, 0, 0, "CB_BLEND_GREEN"},
 	{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
@@ -156,7 +156,7 @@ static const struct radeon_register R600_BLEND_names[] = {
 	{0x00028804, 0, 0, "CB_BLEND_CONTROL"},
 };
 
-static const struct radeon_register R600_DSA_names[] = {
+static const struct radeon_register R600_names_DSA[] = {
 	{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
 	{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
 	{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
@@ -175,7 +175,7 @@ static const struct radeon_register R600_DSA_names[] = {
 	{0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
 };
 
-static const struct radeon_register R600_VS_SHADER_names[] = {
+static const struct radeon_register R600_names_VS_SHADER[] = {
 	{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
 	{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
 	{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
@@ -227,7 +227,7 @@ static const struct radeon_register R600_VS_SHADER_names[] = {
 	{0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
 };
 
-static const struct radeon_register R600_PS_SHADER_names[] = {
+static const struct radeon_register R600_names_PS_SHADER[] = {
 	{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
 	{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
 	{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
@@ -269,28 +269,28 @@ static const struct radeon_register R600_PS_SHADER_names[] = {
 	{0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
 };
 
-static const struct radeon_register R600_PS_CONSTANT_names[] = {
+static const struct radeon_register R600_names_PS_CONSTANT[] = {
 	{0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
 	{0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
 	{0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
 	{0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
 };
 
-static const struct radeon_register R600_VS_CONSTANT_names[] = {
+static const struct radeon_register R600_names_VS_CONSTANT[] = {
 	{0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
 	{0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
 	{0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
 	{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
 };
 
-static const struct radeon_register R600_UCP_names[] = {
+static const struct radeon_register R600_names_UCP[] = {
 	{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
 	{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
 	{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
 	{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
 };
 
-static const struct radeon_register R600_PS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_PS_RESOURCE[] = {
 	{0x00038000, 0, 0, "RESOURCE0_WORD0"},
 	{0x00038004, 0, 0, "RESOURCE0_WORD1"},
 	{0x00038008, 0, 0, "RESOURCE0_WORD2"},
@@ -300,7 +300,7 @@ static const struct radeon_register R600_PS_RESOURCE_names[] = {
 	{0x00038018, 0, 0, "RESOURCE0_WORD6"},
 };
 
-static const struct radeon_register R600_VS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_VS_RESOURCE[] = {
 	{0x00039180, 0, 0, "RESOURCE160_WORD0"},
 	{0x00039184, 0, 0, "RESOURCE160_WORD1"},
 	{0x00039188, 0, 0, "RESOURCE160_WORD2"},
@@ -310,7 +310,7 @@ static const struct radeon_register R600_VS_RESOURCE_names[] = {
 	{0x00039198, 0, 0, "RESOURCE160_WORD6"},
 };
 
-static const struct radeon_register R600_FS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_FS_RESOURCE[] = {
 	{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
 	{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
 	{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
@@ -320,7 +320,7 @@ static const struct radeon_register R600_FS_RESOURCE_names[] = {
 	{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
 };
 
-static const struct radeon_register R600_GS_RESOURCE_names[] = {
+static const struct radeon_register R600_names_GS_RESOURCE[] = {
 	{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
 	{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
 	{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
@@ -330,46 +330,46 @@ static const struct radeon_register R600_GS_RESOURCE_names[] = {
 	{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
 };
 
-static const struct radeon_register R600_PS_SAMPLER_names[] = {
+static const struct radeon_register R600_names_PS_SAMPLER[] = {
 	{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
 	{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
 	{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
 };
 
-static const struct radeon_register R600_VS_SAMPLER_names[] = {
+static const struct radeon_register R600_names_VS_SAMPLER[] = {
 	{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
 	{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
 	{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
 };
 
-static const struct radeon_register R600_GS_SAMPLER_names[] = {
+static const struct radeon_register R600_names_GS_SAMPLER[] = {
 	{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
 	{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
 	{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
 };
 
-static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = {
+static const struct radeon_register R600_names_PS_SAMPLER_BORDER[] = {
 	{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
 	{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
 	{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
 	{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
 };
 
-static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = {
+static const struct radeon_register R600_names_VS_SAMPLER_BORDER[] = {
 	{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
 	{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
 	{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
 	{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
 };
 
-static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = {
+static const struct radeon_register R600_names_GS_SAMPLER_BORDER[] = {
 	{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
 	{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
 	{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
 	{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
 };
 
-static const struct radeon_register R600_CB0_names[] = {
+static const struct radeon_register R600_names_CB0[] = {
 	{0x00028040, 1, 0, "CB_COLOR0_BASE"},
 	{0x000280A0, 0, 0, "CB_COLOR0_INFO"},
 	{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
@@ -379,7 +379,7 @@ static const struct radeon_register R600_CB0_names[] = {
 	{0x00028100, 0, 0, "CB_COLOR0_MASK"},
 };
 
-static const struct radeon_register R600_CB1_names[] = {
+static const struct radeon_register R600_names_CB1[] = {
 	{0x00028044, 1, 0, "CB_COLOR1_BASE"},
 	{0x000280A4, 0, 0, "CB_COLOR1_INFO"},
 	{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
@@ -389,7 +389,7 @@ static const struct radeon_register R600_CB1_names[] = {
 	{0x00028104, 0, 0, "CB_COLOR1_MASK"},
 };
 
-static const struct radeon_register R600_CB2_names[] = {
+static const struct radeon_register R600_names_CB2[] = {
 	{0x00028048, 1, 0, "CB_COLOR2_BASE"},
 	{0x000280A8, 0, 0, "CB_COLOR2_INFO"},
 	{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
@@ -399,7 +399,7 @@ static const struct radeon_register R600_CB2_names[] = {
 	{0x00028108, 0, 0, "CB_COLOR2_MASK"},
 };
 
-static const struct radeon_register R600_CB3_names[] = {
+static const struct radeon_register R600_names_CB3[] = {
 	{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
 	{0x000280AC, 0, 0, "CB_COLOR3_INFO"},
 	{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
@@ -409,7 +409,7 @@ static const struct radeon_register R600_CB3_names[] = {
 	{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
 };
 
-static const struct radeon_register R600_CB4_names[] = {
+static const struct radeon_register R600_names_CB4[] = {
 	{0x00028050, 1, 0, "CB_COLOR4_BASE"},
 	{0x000280B0, 0, 0, "CB_COLOR4_INFO"},
 	{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
@@ -419,7 +419,7 @@ static const struct radeon_register R600_CB4_names[] = {
 	{0x00028110, 0, 0, "CB_COLOR4_MASK"},
 };
 
-static const struct radeon_register R600_CB5_names[] = {
+static const struct radeon_register R600_names_CB5[] = {
 	{0x00028054, 1, 0, "CB_COLOR5_BASE"},
 	{0x000280B4, 0, 0, "CB_COLOR5_INFO"},
 	{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
@@ -429,7 +429,7 @@ static const struct radeon_register R600_CB5_names[] = {
 	{0x00028114, 0, 0, "CB_COLOR5_MASK"},
 };
 
-static const struct radeon_register R600_CB6_names[] = {
+static const struct radeon_register R600_names_CB6[] = {
 	{0x00028058, 1, 0, "CB_COLOR6_BASE"},
 	{0x000280B8, 0, 0, "CB_COLOR6_INFO"},
 	{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
@@ -439,7 +439,7 @@ static const struct radeon_register R600_CB6_names[] = {
 	{0x00028118, 0, 0, "CB_COLOR6_MASK"},
 };
 
-static const struct radeon_register R600_CB7_names[] = {
+static const struct radeon_register R600_names_CB7[] = {
 	{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
 	{0x000280BC, 0, 0, "CB_COLOR7_INFO"},
 	{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
@@ -449,7 +449,7 @@ static const struct radeon_register R600_CB7_names[] = {
 	{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
 };
 
-static const struct radeon_register R600_DB_names[] = {
+static const struct radeon_register R600_names_DB[] = {
 	{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
 	{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
 	{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
@@ -458,7 +458,7 @@ static const struct radeon_register R600_DB_names[] = {
 	{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
 };
 
-static const struct radeon_register R600_VGT_names[] = {
+static const struct radeon_register R600_names_VGT[] = {
 	{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
 	{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
 	{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
@@ -472,91 +472,15 @@ static const struct radeon_register R600_VGT_names[] = {
 	{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
 };
 
-static const struct radeon_register R600_DRAW_names[] = {
+static const struct radeon_register R600_names_DRAW[] = {
 	{0x00008970, 0, 0, "VGT_NUM_INDICES"},
 	{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},
 	{0x000287E8, 1, 0, "VGT_DMA_BASE"},
 	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
 };
 
-static const struct radeon_register R600_VGT_EVENT_names[] = {
+static const struct radeon_register R600_names_VGT_EVENT[] = {
 	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
 };
 
-static struct radeon_type R600_types[] = {
-	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
-	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
-	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
-	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
-	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
-	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
-	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
-	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
-	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
-	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
-	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
-	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
-	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
-	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
-	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
-	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
-	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
-	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
-	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
-	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
-	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
-	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
-	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
-	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
-	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
-	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
-	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
-	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
-	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-};
-
-static struct radeon_type R700_types[] = {
-	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r700_state_pm4_config, R600_CONFIG_names},
-	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
-	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
-	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
-	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
-	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
-	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
-	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
-	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
-	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
-	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
-	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
-	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
-	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
-	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
-	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
-	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
-	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
-	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
-	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
-	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
-	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
-	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB1", 7, r600_state_pm4_cb0, R600_CB1_names},
-	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB2", 7, r600_state_pm4_cb0, R600_CB2_names},
-	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB3", 7, r600_state_pm4_cb0, R600_CB3_names},
-	{ 128, 1273, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB4", 7, r600_state_pm4_cb0, R600_CB4_names},
-	{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
-	{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
-	{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
-	{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
-	{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
-	{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
-	{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
-	{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
-	{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
-};
-
 #endif
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 80b0a1d397..2b16e3ce88 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -153,47 +153,3 @@ struct radeon *radeon_decref(struct radeon *radeon)
 	free(radeon);
 	return NULL;
 }
-
-int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id)
-{
-	unsigned i, j;
-
-	for (i = 0; i < radeon->ntype; i++) {
-		if (radeon->type[i].range_start) {
-			if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) {
-				*typeid = i;
-				j = offset - radeon->type[i].range_start;
-				j /= radeon->type[i].stride;
-				*stateid = radeon->type[i].id + j;
-				*id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4;
-				return 0;
-			}
-		} else {
-			for (j = 0; j < radeon->type[i].nstates; j++) {
-				if (radeon->type[i].regs[j].offset == offset) {
-					*typeid = i;
-					*stateid = radeon->type[i].id;
-					*id = j;
-					return 0;
-				}
-			}
-		}
-	}
-	fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset);
-	return -EINVAL;
-}
-
-unsigned radeon_type_from_id(struct radeon *radeon, unsigned id)
-{
-	unsigned i;
-
-	for (i = 0; i < radeon->ntype - 1; i++) {
-		if (radeon->type[i].id == id)
-			return i;
-		if (id > radeon->type[i].id && id < radeon->type[i + 1].id)
-			return i;
-	}
-	if (radeon->type[i].id == id)
-		return i;
-	return -1;
-}
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index bd050c4cf9..1a12c1023e 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -216,7 +216,7 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
 		r = radeon_ctx_reloc(ctx, state->bo[bid], cid,
 					&state->placement[bid * 2]);
 		if (r) {
-			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type);
+			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->stype->stype);
 			return r;
 		}
 	}
@@ -230,7 +230,7 @@ int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *stat
 	int r = 0;
 
 	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
-	if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
+	if (state->stype->stype != R600_STATE_QUERY_BEGIN && state->stype->stype != R600_STATE_QUERY_END) {
 		return -EINVAL;
 	}
 	r = radeon_state_pm4(state);
@@ -253,7 +253,7 @@ int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *stat
 	/* BEGIN/END query are balanced in the same cs so account for END
 	 * END query when scheduling BEGIN query
 	 */
-	if (state->type == R600_QUERY_BEGIN_TYPE) {
+	if (state->stype->stype == R600_STATE_QUERY_BEGIN) {
 		ctx->draw_cpm4 += state->cpm4 * 2;
 	}
 	return 0;
diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c
index 4413ed79fb..0eacdc74a0 100644
--- a/src/gallium/winsys/r600/drm/radeon_draw.c
+++ b/src/gallium/winsys/r600/drm/radeon_draw.c
@@ -74,12 +74,17 @@ struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw)
 
 int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
 {
+	int id;
 	if (state == NULL)
 		return 0;
-	if (state->type >= draw->radeon->ntype)
+
+	id = state->stype->base_id + (state->id + (state->stype->num * state->shader_index));
+	if (id > draw->radeon->nstate)
+	{
 		return -EINVAL;
-	draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
-	draw->state[state->id] = state;
+	}
+	draw->state[id] = radeon_state_decref(draw->state[id]);
+	draw->state[id] = state;
 	return 0;
 }
 
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 96c0d060f7..66ee5f2177 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -37,17 +37,20 @@ struct radeon_register {
 	char				name[64];
 };
 
-struct radeon_type {
-	unsigned			npm4;
-	unsigned			id;
-	unsigned			range_start;
-	unsigned			range_end;
-	unsigned			stride;
-	unsigned			immediate;
-	char				name[64];
-	unsigned			nstates;
-	radeon_state_pm4_t		pm4;
-	const struct radeon_register	*regs;
+struct radeon_sub_type {
+	int shader_type;
+	const struct radeon_register *regs;
+	unsigned nstates;
+};
+
+struct radeon_stype_info {
+	unsigned stype;
+	unsigned num;
+	unsigned stride;
+	radeon_state_pm4_t pm4;
+	struct radeon_sub_type reginfo[R600_SHADER_MAX];
+	unsigned base_id;
+	unsigned npm4;
 };
 
 struct radeon {
@@ -56,8 +59,8 @@ struct radeon {
 	unsigned			device;
 	unsigned			family;
 	unsigned			nstate;
-	unsigned			ntype;
-	const struct radeon_type	*type;
+	unsigned                        nstype;
+	struct radeon_stype_info *stype;
 };
 
 extern struct radeon *radeon_new(int fd, unsigned device);
@@ -65,9 +68,6 @@ extern struct radeon *radeon_incref(struct radeon *radeon);
 extern struct radeon *radeon_decref(struct radeon *radeon);
 extern unsigned radeon_family_from_device(unsigned device);
 extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
-extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
-extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
-
 
 int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
 struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index 308288557a..ef09fdfb96 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -32,29 +32,56 @@
 /*
  * state core functions
  */
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
+struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 id, u32 shader_type)
 {
 	struct radeon_state *state;
+	struct radeon_stype_info *found = NULL;
+	int i, j, shader_index = -1;
 
-	if (type > radeon->ntype) {
-		fprintf(stderr, "%s invalid type %d\n", __func__, type);
-		return NULL;
+	/* traverse the stype array */
+	for (i = 0; i < radeon->nstype; i++) {
+		/* if the type doesn't match, if the shader doesn't match */
+		if (stype != radeon->stype[i].stype)
+			continue;
+		if (shader_type) {
+			for (j = 0; j < 4; j++) {
+				if (radeon->stype[i].reginfo[j].shader_type == shader_type) {
+					shader_index = j;
+					break;
+				}
+			}
+			if (shader_index == -1)
+				continue;
+		} else {
+			if (radeon->stype[i].reginfo[0].shader_type)
+				continue;
+			else
+				shader_index = 0;
+		}
+		if (id > radeon->stype[i].num)
+			continue;
+		
+		found = &radeon->stype[i];
+		break;
 	}
-	if (id > radeon->nstate) {
-		fprintf(stderr, "%s invalid state id %d\n", __func__, id);
+
+	if (!found) {
+		fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
 		return NULL;
 	}
+
 	state = calloc(1, sizeof(*state));
 	if (state == NULL)
 		return NULL;
+	state->stype = found;
 	state->radeon = radeon;
-	state->type = type;
 	state->id = id;
+	state->shader_index = shader_index;
 	state->refcount = 1;
-	state->npm4 = radeon->type[type].npm4;
-	state->nstates = radeon->type[type].nstates;
+	state->npm4 = found->npm4;
+	state->nstates = found->reginfo[shader_index].nstates;
 	state->states = calloc(1, state->nstates * 4);
-	state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
+	state->pm4 = calloc(1, found->npm4 * 4);
 	if (state->states == NULL || state->pm4 == NULL) {
 		radeon_state_decref(state);
 		return NULL;
@@ -62,9 +89,14 @@ struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
 	return state;
 }
 
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
+{
+	return radeon_state_shader(radeon, type, id, 0);
+}
+
 struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
 {
-	struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
+	struct radeon_state *nstate = radeon_state_shader(state->radeon, state->stype->stype, state->id, (1 << state->shader_index));
 	unsigned i;
 
 	if (state == NULL)
@@ -149,10 +181,10 @@ int radeon_state_pm4(struct radeon_state *state)
 
 	if (state == NULL || state->cpm4)
 		return 0;
-	r = state->radeon->type[state->type].pm4(state);
+	r = state->stype->pm4(state);
 	if (r) {
 		fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
-			__func__, state->type, state->id);
+			__func__, state->stype->stype, state->id);
 		return r;
 	}
 	state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
-- 
cgit v1.2.3


From 0bba7796a33d3c47295a9676dc82984da1615fe5 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Sat, 28 Aug 2010 17:47:13 -0400
Subject: r600g: fix depth buffer decompression after states rework

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 6b8487695c..be1fcf9662 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -215,7 +215,7 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	}
 	bstates->vs_resource0 = rstate;
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
+	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
 	if (rstate == NULL) {
 		return -ENOMEM;
 	}
-- 
cgit v1.2.3


From de0b76cab22caa9fc7260f80acb8f151ccced6c5 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Sun, 29 Aug 2010 21:01:51 -0400
Subject: r600g: precompute some of the hw state

Idea is to build hw state at pipe state creation and
reuse them while keeping a non PM4 packet interface
btw winsys & pipe driver. This commit also force rebuild
of pm4 packet on each call to radeon_state_pm4 which
in turn slow down everythings, this will be addressed.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c       |   4 +-
 src/gallium/drivers/r600/r600_context.h    |   2 +-
 src/gallium/drivers/r600/r600_resource.h   |   2 +-
 src/gallium/drivers/r600/r600_screen.h     |   2 +-
 src/gallium/drivers/r600/r600_state.c      | 226 ++++++++++-------------------
 src/gallium/drivers/r600/r600_texture.c    |  43 ++++--
 src/gallium/drivers/r600/radeon.h          |  47 ++++--
 src/gallium/winsys/r600/drm/r600_state.c   |   9 +-
 src/gallium/winsys/r600/drm/r600_states.h  |  28 +++-
 src/gallium/winsys/r600/drm/radeon_priv.h  |  20 +--
 src/gallium/winsys/r600/drm/radeon_state.c |  62 ++++++--
 11 files changed, 229 insertions(+), 216 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index be1fcf9662..dbcd6cdea8 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -670,7 +670,7 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		return r;
 	}
-	r = r600_texture_cb0(ctx, rtexture, level);
+	r = r600_texture_cb(ctx, rtexture, 0, level);
 	if (r) {
 		return r;
 	}
@@ -772,7 +772,7 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		goto out;
 	}
-	r = radeon_draw_set(draw, rtexture->cb0[level]);
+	r = radeon_draw_set(draw, rtexture->cb[0][level]);
 	if (r) {
 		goto out;
 	}
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index d96d5b513f..e9495f0017 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -121,7 +121,7 @@ struct r600_context_hw_states {
 	struct radeon_state	*config;
 	struct radeon_state	*cb_cntl;
 	struct radeon_state	*db;
-	struct radeon_state	*ucp[6];
+	struct radeon_state	*ucp;
 	unsigned		ps_nresource;
 	unsigned		ps_nsampler;
 	struct radeon_state	*ps_resource[160];
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index b880f9369c..8078a83c35 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -57,7 +57,7 @@ struct r600_resource_texture {
 	unsigned			dirty;
 	struct radeon_bo		*uncompressed;
 	struct radeon_state		*scissor[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*cb0[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		*cb[8][PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*db[PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*viewport[PIPE_MAX_TEXTURE_LEVELS];
 };
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 438976f654..b9938f117a 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -84,7 +84,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 				 struct pipe_transfer* transfer);
 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
+int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level);
 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b5db848e35..6049e1328e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -34,6 +34,16 @@
 #include "r600d.h"
 #include "r600_state_inlines.h"
 
+static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state);
+static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state);
+static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state);
+static struct radeon_state *r600_sampler(struct r600_context *rctx,
+				const struct pipe_sampler_state *state,
+				unsigned id);
+static struct radeon_state *r600_resource(struct pipe_context *ctx,
+					const struct pipe_sampler_view *view,
+					unsigned id);
+
 static void *r600_create_blend_state(struct pipe_context *ctx,
 					const struct pipe_blend_state *state)
 {
@@ -86,6 +96,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
 	rstate->state.sampler_view.context = ctx;
+	rstate->rstate = r600_resource(ctx, &rstate->state.sampler_view, 0);
 	return &rstate->state.sampler_view;
 }
 
@@ -229,6 +240,9 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
 		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
+		}
 	}
 	rctx->ps_nsampler = count;
 }
@@ -246,6 +260,9 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
 		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
+		}
 	}
 	rctx->vs_nsampler = count;
 }
@@ -337,6 +354,9 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
 		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
+		}
 	}
 	rctx->ps_nsampler_view = count;
 }
@@ -355,6 +375,9 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
 		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
+		}
 	}
 	rctx->vs_nsampler_view = count;
 }
@@ -363,10 +386,19 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 					const struct pipe_framebuffer_state *state)
 {
 	struct r600_context *rctx = r600_context(ctx);
+	struct r600_resource_texture *rtexture;
 	struct r600_context_state *rstate;
 
 	rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
 	r600_bind_state(ctx, rstate);
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		rtexture = (struct r600_resource_texture*)state->cbufs[i]->texture;
+		r600_texture_cb(ctx, rtexture, i, state->cbufs[i]->level);
+	}
+	if (state->zsbuf) {
+		rtexture = (struct r600_resource_texture*)state->zsbuf->texture;
+		r600_texture_db(ctx, rtexture, state->zsbuf->level);
+	}
 }
 
 static void r600_set_polygon_stipple(struct pipe_context *ctx,
@@ -565,6 +597,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_viewport_type:
 		rstate->state.viewport = (*states).viewport;
+		rstate->rstate = r600_viewport(rctx, &rstate->state.viewport);
 		break;
 	case pipe_depth_type:
 		rstate->state.depth = (*states).depth;
@@ -580,6 +613,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_clip_type:
 		rstate->state.clip = (*states).clip;
+		rstate->rstate = r600_ucp(rctx, &rstate->state.clip);
 		break;
 	case pipe_stencil_type:
 		rstate->state.stencil = (*states).stencil;
@@ -592,6 +626,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_blend_type:
 		rstate->state.blend = (*states).blend;
+		rstate->rstate = r600_blend(rctx, &rstate->state.blend);
 		break;
 	case pipe_stencil_ref_type:
 		rstate->state.stencil_ref = (*states).stencil_ref;
@@ -606,6 +641,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_sampler_type:
 		rstate->state.sampler = (*states).sampler;
+		rstate->rstate = r600_sampler(rctx, &rstate->state.sampler, 0);
 		break;
 	default:
 		R600_ERR("invalid type %d\n", rstate->type);
@@ -615,11 +651,10 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 	return rstate;
 }
 
-static struct radeon_state *r600_blend(struct r600_context *rctx)
+static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
-	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
 
 	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
@@ -675,129 +710,28 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	return rstate;
 }
 
-static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
+static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
-	const struct pipe_clip_state *state = &rctx->clip->state.clip;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_CLIP, clip);
+	rstate = radeon_state(rscreen->rw, R600_STATE_UCP, 0);
 	if (rstate == NULL)
 		return NULL;
 
-	rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
-	rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
-	rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
-	rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
-
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
+	for (int i = 0; i < state->nr; i++) {
+		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
+		rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
+		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
+		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
 	}
-	return rstate;
 
-}
-
-static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
-	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level = state->cbufs[cb]->level;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
-	if (rstate == NULL)
-		return NULL;
-	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
-	rbuffer = &rtex->resource;
-	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 3;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
-
-	ntype = 0;
-	desc = util_format_description(rtex->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_0280A0_NUMBER_SRGB;
-
-	format = r600_translate_colorformat(rtex->resource.base.b.format);
-	swap = r600_translate_colorswap(rtex->resource.base.b.format);
-
-	color_info = S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_SOURCE_FORMAT(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
-
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
-						S_028060_SLICE_TILE_MAX(slice);
-	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
 	}
 	return rstate;
-}
 
-static struct radeon_state *r600_db(struct r600_context *rctx)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
-	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level;
-	unsigned pitch, slice, format;
-
-	if (state->zsbuf == NULL)
-		return NULL;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
-	if (rstate == NULL)
-		return NULL;
-
-	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
-	rtex->tilled = 1;
-	rtex->array_mode = 2;
-	rtex->tile_type = 1;
-	rtex->depth = 1;
-	rbuffer = &rtex->resource;
-
-	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	level = state->zsbuf->level;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
-	format = r600_translate_dbformat(state->zsbuf->texture->format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = rtex->offset[level] >> 8;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
-					S_028010_FORMAT(format);
-	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
-	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
 }
 
 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
@@ -954,9 +888,8 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	return rstate;
 }
 
-static struct radeon_state *r600_viewport(struct r600_context *rctx)
+static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state)
 {
-	const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
@@ -1366,6 +1299,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 int r600_context_hw_states(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = r600_context(ctx);
+	struct r600_resource_texture *rtexture;
 	unsigned i;
 	int r;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
@@ -1377,69 +1311,59 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	/* free previous TODO determine what need to be updated, what
 	 * doesn't
 	 */
-	//radeon_state_decref(rctx->hw_states.config);
 	rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
-	rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
 	rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
 	rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
 	rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
-	rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
-	rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
-	for (i = 0; i < 8; i++) {
-		rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
-	}
-	for (i = 0; i < 6; i++) {
-		rctx->hw_states.ucp[i] = radeon_state_decref(rctx->hw_states.ucp[i]);
-	}
-	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
-		radeon_state_decref(rctx->hw_states.ps_resource[i]);
-		rctx->hw_states.ps_resource[i] = NULL;
-	}
-	rctx->hw_states.ps_nresource = 0;
-	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
-		radeon_state_decref(rctx->hw_states.ps_sampler[i]);
-		rctx->hw_states.ps_sampler[i] = NULL;
-	}
-	rctx->hw_states.ps_nsampler = 0;
 
 	/* build new states */
+	rctx->hw_states.blend = NULL;
+	rctx->hw_states.viewport = NULL;
+	rctx->hw_states.ucp = NULL;
 	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
 	rctx->hw_states.scissor = r600_scissor(rctx);
 	rctx->hw_states.dsa = r600_dsa(rctx);
-	rctx->hw_states.blend = r600_blend(rctx);
-	rctx->hw_states.viewport = r600_viewport(rctx);
-	for (i = 0; i < nr_cbufs; i++) {
-		rctx->hw_states.cb[i] = r600_cb(rctx, i);
+	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
+	if (rctx->viewport) {
+		rctx->hw_states.viewport = rctx->viewport->rstate;
 	}
-	for (i = 0; i < ucp_nclip; i++) {
-		rctx->hw_states.ucp[i] = r600_ucp(rctx, i);
+	if (rctx->blend) {
+		rctx->hw_states.blend = rctx->blend->rstate;
 	}
-	rctx->hw_states.db = r600_db(rctx);
-	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
+	if (rctx->clip) {
+		rctx->hw_states.ucp = rctx->clip->rstate;
+	}
+	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
+		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.cbufs[i]->texture;
+		rctx->hw_states.cb[i] = rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level];
+	}
+	if (rctx->framebuffer->state.framebuffer.zsbuf) {
+		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.zsbuf->texture;
+		rctx->hw_states.db = rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level];
+	}
+
 
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
-							&rctx->ps_sampler[i]->state.sampler,
-							i);
+			rctx->hw_states.ps_sampler[i] = rctx->ps_sampler[i]->rstate;
+		} else {
+			rctx->hw_states.ps_sampler[i] = NULL;
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			rctx->hw_states.ps_resource[i] = r600_resource(ctx,
-							&rctx->ps_sampler_view[i]->state.sampler_view,
-							i);
+			rctx->hw_states.ps_resource[i] = rctx->ps_sampler_view[i]->rstate;
+		} else {
+			rctx->hw_states.ps_resource[i] = NULL;
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
 
 	/* bind states */
-	for (i = 0; i < ucp_nclip; i++) {
-		r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp[i]);
-		if (r)
-			return r;
-	}
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp);
+	if (r)
+		return r;
 	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
 	if (r)
 		return r;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 77d627cdc8..ec1d50566a 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -128,13 +128,25 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 	return &resource->base.b;
 }
 
+static void r600_texture_destroy_state(struct pipe_resource *ptexture)
+{
+	struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
+
+	for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
+		radeon_state_decref(rtexture->scissor[i]);
+		radeon_state_decref(rtexture->db[i]);
+		for (int j = 0; j < 8; j++) {
+			radeon_state_decref(rtexture->cb[j][i]);
+		}
+	}
+}
+
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
 	struct r600_screen *rscreen = r600_screen(screen);
-	unsigned i;
 
 	if (resource->bo) {
 		radeon_bo_decref(rscreen->rw, resource->bo);
@@ -142,11 +154,7 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	if (rtex->uncompressed) {
 		radeon_bo_decref(rscreen->rw, rtex->uncompressed);
 	}
-	for (i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
-		radeon_state_decref(rtex->scissor[i]);
-		radeon_state_decref(rtex->cb0[i]);
-		radeon_state_decref(rtex->db[i]);
-	}
+	r600_texture_destroy_state(ptex);
 	FREE(rtex);
 }
 
@@ -211,9 +219,12 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	pipe_reference_init(&resource->base.b.reference, 1);
 	resource->base.b.screen = screen;
 	resource->bo = bo;
+	rtex->depth = 0;
 	rtex->pitch_override = whandle->stride;
 	rtex->bpt = util_format_get_blocksize(templ->format);
 	rtex->pitch[0] = whandle->stride;
+	rtex->width[0] = templ->width0;
+	rtex->height[0] = templ->height0;
 	rtex->offset[0] = 0;
 	rtex->size = align(rtex->pitch[0] * templ->height0, 64);
 
@@ -696,9 +707,9 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 	return rstate;
 }
 
-static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
+static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
 				struct r600_resource_texture *rtexture,
-				unsigned level)
+				unsigned cb, unsigned level)
 {
 	struct radeon_state *rstate;
 	struct r600_resource *rbuffer;
@@ -707,7 +718,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0, 0);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -770,6 +781,10 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
+	rtexture->tilled = 1;
+	rtexture->array_mode = 2;
+	rtexture->tile_type = 1;
+	rtexture->depth = 1;
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -838,14 +853,14 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 	return rstate;
 }
 
-int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->cb0[level] == NULL) {
-		rtexture->cb0[level] = r600_texture_state_cb0(rscreen, rtexture, level);
-		if (rtexture->cb0[level] == NULL) {
-			R600_ERR("failed to create cb0 state for texture\n");
+	if (rtexture->cb[cb][level] == NULL) {
+		rtexture->cb[cb][level] = r600_texture_state_cb(rscreen, rtexture, cb, level);
+		if (rtexture->cb[cb][level] == NULL) {
+			R600_ERR("failed to create cb%d state for texture\n", cb);
 			return -ENOMEM;
 		}
 	}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 046c264c04..3f1ca95f69 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -109,13 +109,11 @@ struct radeon_state {
 	unsigned			id;
 	unsigned                        shader_index;
 	unsigned			nstates;
-	u32				*states;
+	u32				states[64];
 	unsigned			npm4;
 	unsigned			cpm4;
 	u32				pm4_crc;
-	u32				*pm4;
-	u32				nimmd;
-	u32				*immd;
+	u32				pm4[128];
 	unsigned			nbo;
 	struct radeon_bo		*bo[4];
 	unsigned			nreloc;
@@ -130,6 +128,7 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 type, u32 id
 struct radeon_state *radeon_state_incref(struct radeon_state *state);
 struct radeon_state *radeon_state_decref(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
+int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
 
 /*
  * draw functions
@@ -219,7 +218,7 @@ enum r600_stype {
 	R600_STATE_DB,
 	R600_STATE_QUERY_BEGIN,
 	R600_STATE_QUERY_END,
-	R600_STATE_CLIP,
+	R600_STATE_UCP,
 	R600_STATE_VGT,
 	R600_STATE_DRAW,
 };
@@ -613,17 +612,37 @@ enum {
 /* R600_DRAW */
 #define R600_DRAW__VGT_NUM_INDICES			0
 #define R600_DRAW__VGT_DMA_BASE_HI			1
-#define R600_DRAW__VGT_DMA_BASE			2
+#define R600_DRAW__VGT_DMA_BASE				2
 #define R600_DRAW__VGT_DRAW_INITIATOR			3
-#define R600_DRAW_SIZE				4
-#define R600_DRAW_PM4				128
+#define R600_DRAW_SIZE					4
+#define R600_DRAW_PM4					128
 /* R600_CLIP */
-#define R600_CLIP__PA_CL_UCP_X_0  0
-#define R600_CLIP__PA_CL_UCP_Y_0  1
-#define R600_CLIP__PA_CL_UCP_Z_0  2
-#define R600_CLIP__PA_CL_UCP_W_0  3
-#define R600_CLIP_SIZE  4
-#define R600_CLIP_PM4 128
+#define R600_CLIP__PA_CL_UCP_X_0			0
+#define R600_CLIP__PA_CL_UCP_Y_0			1
+#define R600_CLIP__PA_CL_UCP_Z_0			2
+#define R600_CLIP__PA_CL_UCP_W_0			3
+#define R600_CLIP__PA_CL_UCP_X_1			4
+#define R600_CLIP__PA_CL_UCP_Y_1			5
+#define R600_CLIP__PA_CL_UCP_Z_1			6
+#define R600_CLIP__PA_CL_UCP_W_1			7
+#define R600_CLIP__PA_CL_UCP_X_2			8
+#define R600_CLIP__PA_CL_UCP_Y_2			9
+#define R600_CLIP__PA_CL_UCP_Z_2			10
+#define R600_CLIP__PA_CL_UCP_W_2			11
+#define R600_CLIP__PA_CL_UCP_X_3			12
+#define R600_CLIP__PA_CL_UCP_Y_3			13
+#define R600_CLIP__PA_CL_UCP_Z_3			14
+#define R600_CLIP__PA_CL_UCP_W_3			15
+#define R600_CLIP__PA_CL_UCP_X_4			16
+#define R600_CLIP__PA_CL_UCP_Y_4			17
+#define R600_CLIP__PA_CL_UCP_Z_4			18
+#define R600_CLIP__PA_CL_UCP_W_4			19
+#define R600_CLIP__PA_CL_UCP_X_5			20
+#define R600_CLIP__PA_CL_UCP_Y_5			21
+#define R600_CLIP__PA_CL_UCP_Z_5			22
+#define R600_CLIP__PA_CL_UCP_W_5			23
+#define R600_CLIP_SIZE					24
+#define R600_CLIP_PM4					128
 /* R600 QUERY BEGIN/END */
 #define R600_QUERY__OFFSET			0
 #define R600_QUERY_SIZE				1
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index e3d0116a2d..f6a428e884 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -80,7 +80,7 @@ struct radeon_stype_info r600_stypes[] = {
 	{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
 	{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
 	{ R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
-	{ R600_STATE_CLIP, 6, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
+	{ R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
 	{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
 	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
 };
@@ -381,13 +381,6 @@ static int r600_state_pm4_draw(struct radeon_state *state)
 		if (r)
 			return r;
 		state->pm4[state->cpm4++] = state->bo[0]->handle;
-	} else if  (state->nimmd) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1);
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
-		for (i = 0; i < state->nimmd; i++) {
-			state->pm4[state->cpm4++] = state->immd[i];
-		}
 	} else {
 		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
 		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 51b69b9220..09d79d498d 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -284,10 +284,30 @@ static const struct radeon_register R600_names_VS_CONSTANT[] = {
 };
 
 static const struct radeon_register R600_names_UCP[] = {
-	{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
-	{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
-	{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
-	{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
+	{0x00028E20, 0, 0, "PA_CL_UCP0_X"},
+	{0x00028E24, 0, 0, "PA_CL_UCP0_Y"},
+	{0x00028E28, 0, 0, "PA_CL_UCP0_Z"},
+	{0x00028E2C, 0, 0, "PA_CL_UCP0_W"},
+	{0x00028E30, 0, 0, "PA_CL_UCP1_X"},
+	{0x00028E34, 0, 0, "PA_CL_UCP1_Y"},
+	{0x00028E38, 0, 0, "PA_CL_UCP1_Z"},
+	{0x00028E3C, 0, 0, "PA_CL_UCP1_W"},
+	{0x00028E40, 0, 0, "PA_CL_UCP2_X"},
+	{0x00028E44, 0, 0, "PA_CL_UCP2_Y"},
+	{0x00028E48, 0, 0, "PA_CL_UCP2_Z"},
+	{0x00028E4C, 0, 0, "PA_CL_UCP2_W"},
+	{0x00028E50, 0, 0, "PA_CL_UCP3_X"},
+	{0x00028E54, 0, 0, "PA_CL_UCP3_Y"},
+	{0x00028E58, 0, 0, "PA_CL_UCP3_Z"},
+	{0x00028E5C, 0, 0, "PA_CL_UCP3_W"},
+	{0x00028E60, 0, 0, "PA_CL_UCP4_X"},
+	{0x00028E64, 0, 0, "PA_CL_UCP4_Y"},
+	{0x00028E68, 0, 0, "PA_CL_UCP4_Z"},
+	{0x00028E6C, 0, 0, "PA_CL_UCP4_W"},
+	{0x00028E70, 0, 0, "PA_CL_UCP5_X"},
+	{0x00028E74, 0, 0, "PA_CL_UCP5_Y"},
+	{0x00028E78, 0, 0, "PA_CL_UCP5_Z"},
+	{0x00028E7C, 0, 0, "PA_CL_UCP5_W"},
 };
 
 static const struct radeon_register R600_names_PS_RESOURCE[] = {
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 66ee5f2177..af5319efd1 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -38,19 +38,19 @@ struct radeon_register {
 };
 
 struct radeon_sub_type {
-	int shader_type;
-	const struct radeon_register *regs;
-	unsigned nstates;
+	int				shader_type;
+	const struct radeon_register	*regs;
+	unsigned			nstates;
 };
 
 struct radeon_stype_info {
-	unsigned stype;
-	unsigned num;
-	unsigned stride;
-	radeon_state_pm4_t pm4;
-	struct radeon_sub_type reginfo[R600_SHADER_MAX];
-	unsigned base_id;
-	unsigned npm4;
+	unsigned			stype;
+	unsigned			num;
+	unsigned			stride;
+	radeon_state_pm4_t		pm4;
+	struct radeon_sub_type		reginfo[R600_SHADER_MAX];
+	unsigned			base_id;
+	unsigned			npm4;
 };
 
 struct radeon {
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index ef09fdfb96..d4e622cf7f 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -80,15 +80,59 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 i
 	state->refcount = 1;
 	state->npm4 = found->npm4;
 	state->nstates = found->reginfo[shader_index].nstates;
-	state->states = calloc(1, state->nstates * 4);
-	state->pm4 = calloc(1, found->npm4 * 4);
-	if (state->states == NULL || state->pm4 == NULL) {
-		radeon_state_decref(state);
-		return NULL;
-	}
 	return state;
 }
 
+int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type)
+{
+	struct radeon_stype_info *found = NULL;
+	int i, j, shader_index = -1;
+
+	if (state == NULL)
+		return 0;
+	/* traverse the stype array */
+	for (i = 0; i < state->radeon->nstype; i++) {
+		/* if the type doesn't match, if the shader doesn't match */
+		if (stype != state->radeon->stype[i].stype)
+			continue;
+		if (shader_type) {
+			for (j = 0; j < 4; j++) {
+				if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) {
+					shader_index = j;
+					break;
+				}
+			}
+			if (shader_index == -1)
+				continue;
+		} else {
+			if (state->radeon->stype[i].reginfo[0].shader_type)
+				continue;
+			else
+				shader_index = 0;
+		}
+		if (id > state->radeon->stype[i].num)
+			continue;
+		
+		found = &state->radeon->stype[i];
+		break;
+	}
+
+	if (!found) {
+		fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
+		return -EINVAL;
+	}
+
+	if (found->reginfo[shader_index].nstates != state->nstates) {
+		fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n",
+			state->stype->stype, state->id, state->shader_index, stype, id, shader_index);
+	}
+
+	state->stype = found;
+	state->id = id;
+	state->shader_index = shader_index;
+	return radeon_state_pm4(state);
+}
+
 struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
 {
 	return radeon_state_shader(radeon, type, id, 0);
@@ -134,9 +178,6 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
 	for (i = 0; i < state->nbo; i++) {
 		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
 	}
-	free(state->immd);
-	free(state->states);
-	free(state->pm4);
 	memset(state, 0, sizeof(*state));
 	free(state);
 	return NULL;
@@ -179,8 +220,9 @@ int radeon_state_pm4(struct radeon_state *state)
 {
 	int r;
 
-	if (state == NULL || state->cpm4)
+	if (state == NULL)
 		return 0;
+	state->cpm4 = 0;
 	r = state->stype->pm4(state);
 	if (r) {
 		fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
-- 
cgit v1.2.3


From 5ea238b7991331c854e66a16911d616d36965dc9 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 09:02:02 +1000
Subject: r600g: add missing literals

Also add an error if we hit this problem again, we need to do this better
possibly tying the literal addition to the last flag.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 src/gallium/drivers/r600/r600_asm.c    |  3 +++
 src/gallium/drivers/r600/r600_shader.c | 31 ++++++++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 1a354a6293..6483dac703 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -375,6 +375,9 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsign
 		 	                S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
 	}
 	if (alu->last) {
+		if (alu->nliteral && !alu->literal_added) {
+			R600_ERR("Bug in ALU processing for instruction 0x%08x, literal not added correctly\n");
+		}
 		for (i = 0; i < alu->nliteral; i++) {
 			bc->bytecode[id++] = alu->value[i];
 		}
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 652d4035cc..4834eaa9de 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1018,6 +1018,10 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	if (r)
 		return r;
 
+	r = r600_bc_add_literal(ctx->bc, ctx->value);
+	if (r)
+		return r;
+
 	if (inst->Dst[0].Register.WriteMask & (1 << 2))
 	{
 		int chan;
@@ -1038,6 +1042,9 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
 		chan = alu.dst.chan;
 		sel = alu.dst.sel;
 
@@ -1063,6 +1070,9 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
 		/* dst.z = exp(tmp.x) */
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
@@ -1149,6 +1159,9 @@ static int tgsi_trans_srcx_replicate(struct r600_shader_ctx *ctx)
 	alu.dst.write = 1;
 	alu.last = 1;
 	r = r600_bc_add_alu(ctx->bc, &alu);
+	if (r)
+		return r;
+	r = r600_bc_add_literal(ctx->bc, ctx->value);
 	if (r)
 		return r;
 	/* replicate result */
@@ -1760,6 +1773,10 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 		if (r)
 			return r;
 
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
+
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE;
 		alu.src[0].sel = ctx->temp_reg;
 		alu.src[0].chan = 0;
@@ -1771,6 +1788,10 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
 			return r;
+
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
 	}
 		
 	/* result.y = tmp - floor(tmp); */
@@ -1796,6 +1817,9 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
 			return r;
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
 	}
 
 	/* result.z = RoughApprox2ToX(tmp);*/
@@ -1816,7 +1840,9 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
 			return r;
-
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
 	}
 
 	/* result.w = 1.0;*/
@@ -1834,6 +1860,9 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
 			return r;
+		r = r600_bc_add_literal(ctx->bc, ctx->value);
+		if (r)
+			return r;
 	}
 	return tgsi_helper_copy(ctx, inst);
 }
-- 
cgit v1.2.3


From 85e401d8bfd80450a31eac234e13008e33e64227 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 09:56:35 +1000
Subject: r600g: fix LIT tests

---
 src/gallium/drivers/r600/r600_shader.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 4834eaa9de..2210f83283 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -987,7 +987,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	if (r)
 		return r;
 	alu.src[1].sel  = V_SQ_ALU_SRC_0; /*0.0*/
-	alu.src[1].chan = tgsi_chan(&inst->Src[0], 0);
+	alu.src[1].chan = 0;
 	r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
 	if (r)
 		return r;
@@ -1033,7 +1033,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
 		if (r)
 			return r;
-		alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
 		r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
 		if (r)
 			return r;
@@ -1045,6 +1045,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_literal(ctx->bc, ctx->value);
 		if (r)
 			return r;
+
 		chan = alu.dst.chan;
 		sel = alu.dst.sel;
 
-- 
cgit v1.2.3


From 9bbc54a10d225679a180a085f7ca5bb88ee2bd15 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 10:43:04 +1000
Subject: r600g: fix constant splitting

constant splitting was broken for multi-constant cases, fixes fp1 CMP+MAD, vp1 CMP.
---
 src/gallium/drivers/r600/r600_shader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 2210f83283..2197a1610f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -650,7 +650,7 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s
 			for (k = 0; k < 4; k++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-				alu.src[0].sel = r600_src[0].sel;
+				alu.src[0].sel = r600_src[j].sel;
 				alu.src[0].chan = k;
 				alu.dst.sel = ctx->temp_reg + j;
 				alu.dst.chan = k;
@@ -661,7 +661,7 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s
 				if (r)
 					return r;
 			}
-			r600_src[0].sel = ctx->temp_reg + j;
+			r600_src[j].sel = ctx->temp_reg + j;
 			j--;
 		}
 	}
-- 
cgit v1.2.3


From ee0153f891bb75ee14db579e6628d592032d6801 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 10:43:54 +1000
Subject: r600g: make sure LIT splits constants

---
 src/gallium/drivers/r600/r600_shader.c | 25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 2197a1610f..be6023268a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -861,7 +861,6 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.src[0].sel = ctx->temp_reg;
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-		alu.dst.chan = i;
 		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 		if (r)
 			return r;
@@ -965,8 +964,13 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
 	struct r600_bc_alu alu;
+	struct r600_bc_alu_src r600_src[3];
 	int r;
 
+	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+
 	/* dst.x, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
 	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
@@ -983,9 +987,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	/* dst.y = max(src.x, 0.0) */
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
 	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX;
-	r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
-	if (r)
-		return r;
+	alu.src[0] = r600_src[0];
 	alu.src[1].sel  = V_SQ_ALU_SRC_0; /*0.0*/
 	alu.src[1].chan = 0;
 	r = tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
@@ -1030,10 +1032,8 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		/* dst.z = log(src.y) */
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED;
-		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
-		if (r)
-			return r;
-		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
+		alu.src[0] = r600_src[0];
+		alu.src[0].chan = tgsi_chan(&inst->Src[0], 1);
 		r = tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
 		if (r)
 			return r;
@@ -1052,15 +1052,12 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 		/* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT;
-		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
-		if (r)
-			return r;
+		alu.src[0] = r600_src[0];
 		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
 		alu.src[1].sel  = sel;
 		alu.src[1].chan = chan;
-		r = tgsi_src(ctx, &inst->Src[0], &alu.src[2]);
-		if (r)
-			return r;
+
+		alu.src[2] = r600_src[0];
 		alu.src[2].chan = tgsi_chan(&inst->Src[0], 0);
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = 0;
-- 
cgit v1.2.3


From be7816f2b7f0b064a47fb3f101477ad5dba74017 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 11:42:01 +1000
Subject: r600g: fixup trig functions when input is a literal

So as the trig functions used up the literal spots for the PI work, if the arg0 was an immediate
we'd hit failure, so copy the literal before starting.

add some tracking of max temp used to avoid trashing temp regs.

5 more piglits, fp1 COS,SCS,SIN tests
---
 src/gallium/drivers/r600/r600_shader.c | 76 ++++++++++++++++++++++++++++++----
 1 file changed, 67 insertions(+), 9 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index be6023268a..ed953d3f1d 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -50,6 +50,7 @@ struct r600_shader_ctx {
 	u32					value[4];
 	u32					*literals;
 	u32					nliterals;
+	u32                                     max_driver_temp_used;
 };
 
 struct r600_shader_tgsi_instruction {
@@ -354,6 +355,11 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
 	return 0;
 }
 
+static int r600_get_temp(struct r600_shader_ctx *ctx)
+{
+	return ctx->temp_reg + ctx->max_driver_temp_used++;
+}
+
 int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *shader)
 {
 	struct tgsi_full_immediate *immediate;
@@ -436,6 +442,9 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 			r = tgsi_is_supported(&ctx);
 			if (r)
 				goto out_err;
+			ctx.max_driver_temp_used = 0;
+			/* reserve first tmp for everyone */
+			r600_get_temp(&ctx);
 			opcode = ctx.parse.FullToken.FullInstruction.Instruction.Opcode;
 			ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
 			r = ctx.inst_info->process(&ctx);
@@ -647,12 +656,13 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s
 	}
 	for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
 		if (inst->Src[j].Register.File == TGSI_FILE_CONSTANT && j > 0) {
+			int treg = r600_get_temp(ctx);
 			for (k = 0; k < 4; k++) {
 				memset(&alu, 0, sizeof(struct r600_bc_alu));
 				alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
 				alu.src[0].sel = r600_src[j].sel;
 				alu.src[0].chan = k;
-				alu.dst.sel = ctx->temp_reg + j;
+				alu.dst.sel = treg;
 				alu.dst.chan = k;
 				alu.dst.write = 1;
 				if (k == 3)
@@ -661,13 +671,52 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_s
 				if (r)
 					return r;
 			}
-			r600_src[j].sel = ctx->temp_reg + j;
+			r600_src[j].sel = treg;
 			j--;
 		}
 	}
 	return 0;
 }
 
+/* need to move any immediate into a temp - for trig functions which use literal for PI stuff */
+static int tgsi_split_literal_constant(struct r600_shader_ctx *ctx, struct r600_bc_alu_src r600_src[3])
+{
+	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
+	struct r600_bc_alu alu;
+	int i, j, k, nliteral, r;
+
+	for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
+		if (inst->Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
+			nliteral++;
+		}
+	}
+	for (i = 0, j = 0; i < inst->Instruction.NumSrcRegs; i++) {
+		if (inst->Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
+			int treg = r600_get_temp(ctx);
+			for (k = 0; k < 4; k++) {
+				memset(&alu, 0, sizeof(struct r600_bc_alu));
+				alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+				alu.src[0].sel = r600_src[j].sel;
+				alu.src[0].chan = k;
+				alu.dst.sel = treg;
+				alu.dst.chan = k;
+				alu.dst.write = 1;
+				if (k == 3)
+					alu.last = 1;
+				r = r600_bc_add_alu(ctx->bc, &alu);
+				if (r)
+					return r;
+			}
+			r = r600_bc_add_literal(ctx->bc, ctx->value);
+			if (r)
+				return r;
+			r600_src[j].sel = treg;
+			j++;
+		}
+	}
+	return 0;
+}
+
 static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
 {
 	struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
@@ -755,6 +804,11 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
 	r = tgsi_split_constant(ctx, r600_src);
 	if (r)
 		return r;
+
+	r = tgsi_split_literal_constant(ctx, r600_src);
+	if (r)
+		return r;
+
 	lit_vals[0] = fui(1.0 /(3.1415926535 * 2));
 	lit_vals[1] = fui(0.5f);
 
@@ -834,10 +888,7 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 	struct r600_bc_alu_src r600_src[3];
 	struct r600_bc_alu alu;
 	int i, r;
-
-	r = tgsi_split_constant(ctx, r600_src);
-	if (r)
-		return r;
+	int lasti = 0;
 
 	r = tgsi_setup_trig(ctx, r600_src);
 	if (r)
@@ -858,14 +909,21 @@ static int tgsi_trig(struct r600_shader_ctx *ctx)
 
 	/* replicate result */
 	for (i = 0; i < 4; i++) {
+		if (inst->Dst[0].Register.WriteMask & (1 << i))
+			lasti = i;
+	}
+	for (i = 0; i < lasti + 1; i++) {
+		if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
+			continue;
+
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
-		alu.src[0].sel = ctx->temp_reg;
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
+
+		alu.src[0].sel = ctx->temp_reg;
 		r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
 		if (r)
 			return r;
-		alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
-		if (i == 3)
+		if (i == lasti)
 			alu.last = 1;
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
-- 
cgit v1.2.3


From d3fa92584b109bf59dce32501eec73f8de74f42b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 11:57:04 +1000
Subject: r600g: make LIT work properly

this is a bit of a workaround, something is wrong with the literal emits here
so we just use the trig copy function to copy the immd to a temp at start of op.

fix VP/FP LIT tests
---
 src/gallium/drivers/r600/r600_shader.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index ed953d3f1d..bac96e8a30 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1026,6 +1026,9 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	int r;
 
 	r = tgsi_split_constant(ctx, r600_src);
+	if (r)
+		return r;
+	r = tgsi_split_literal_constant(ctx, r600_src);
 	if (r)
 		return r;
 
@@ -1056,14 +1059,6 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
 	if (r)
 		return r;
 
-	/* dst.z = NOP - fill Z slot */
-	memset(&alu, 0, sizeof(struct r600_bc_alu));
-	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP;
-	alu.dst.chan = 2;
-	r = r600_bc_add_alu(ctx->bc, &alu);
-	if (r)
-		return r;
-
 	/* dst.w, <- 1.0  */
 	memset(&alu, 0, sizeof(struct r600_bc_alu));
 	alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
-- 
cgit v1.2.3


From 4e61f085d04c5d182989c6cb388c375b007e6b76 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 13:54:19 +1000
Subject: r600g: remove unneeded function call from scs

---
 src/gallium/drivers/r600/r600_shader.c | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index bac96e8a30..b760ee70ea 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -939,10 +939,6 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
 	struct r600_bc_alu alu;
 	int r;
 
-	r = tgsi_split_constant(ctx, r600_src);
-	if (r)
-		return r;
-
 	r = tgsi_setup_trig(ctx, r600_src);
 	if (r)
 		return r;
-- 
cgit v1.2.3


From 5d66a8606d68caf0fb4754c144c5fb7d87fbf7df Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 14:52:52 +1000
Subject: r600g: fix position input to fragment shader.

this fixes a few if the fs shader tests, 10 more piglits
---
 src/gallium/drivers/r600/r600_shader.c | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index b760ee70ea..5675e39542 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -166,6 +166,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	struct r600_context *rctx = r600_context(ctx);
 	struct radeon_state *state;
 	unsigned i, tmp, exports_ps, num_cout;
+	boolean have_pos = FALSE;
 
 	rasterizer = &rctx->rasterizer->state.rasterizer;
 	rpshader->rstate = radeon_state_decref(rpshader->rstate);
@@ -175,6 +176,8 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	for (i = 0; i < rshader->ninput; i++) {
 		tmp = S_028644_SEMANTIC(i);
 		tmp |= S_028644_SEL_CENTROID(1);
+		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
+			have_pos = TRUE;
 		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
 			rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
 			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
@@ -201,6 +204,10 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
 							S_0286CC_PERSP_GRADIENT_ENA(1);
+	if (have_pos) {
+		state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1);
+		                                                       S_0286CC_BARYC_SAMPLE_CNTL(1);
+	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
 		S_028868_STACK_SIZE(rshader->bc.nstack);
-- 
cgit v1.2.3


From 580781babe99bbfd0181b911e1e53e94728faa04 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 14:57:57 +1000
Subject: r600g: fix typo in last commit

---
 src/gallium/drivers/r600/r600_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 5675e39542..dae3781978 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -205,7 +205,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
 							S_0286CC_PERSP_GRADIENT_ENA(1);
 	if (have_pos) {
-		state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1);
+		state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1) |
 		                                                       S_0286CC_BARYC_SAMPLE_CNTL(1);
 	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
-- 
cgit v1.2.3


From ad202678fc4859b51a9198575a886707f57ad05b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 15:12:24 +1000
Subject: r600g: fix fp-fragment-position test.

---
 src/gallium/drivers/r600/r600_shader.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index dae3781978..d81308b211 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -207,6 +207,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	if (have_pos) {
 		state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] |=  S_0286CC_POSITION_ENA(1) |
 		                                                       S_0286CC_BARYC_SAMPLE_CNTL(1);
+		state->states[R600_PS_SHADER__SPI_INPUT_Z] |= 1;
 	}
 	state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
-- 
cgit v1.2.3


From b87b6e5bf798fcfa486e8082a09b4425a40cf3c4 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Tue, 31 Aug 2010 16:13:03 +1000
Subject: r600g: fix up depth write swizzles.

For some reason r600c, emits extra instructions in the FP to do the depth write output swizzle,
I'm not sure this is required, so here I'm doing it in the exports.

this fixes the mesa trivial demos tri-depthwrite and tri-depthwrite2, it doesn't fix
the glsl1 gl_FragDepth writing test however.
---
 src/gallium/drivers/r600/r600_shader.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index d81308b211..bc1811129b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -179,7 +179,8 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
 			have_pos = TRUE;
 		if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
-			rshader->input[i].name == TGSI_SEMANTIC_BCOLOR) {
+		    rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
+		    rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
 			tmp |= S_028644_FLAT_SHADE(rshader->flat_shade);
 		}
 		if (rasterizer->sprite_coord_enable & (1 << i)) {
@@ -503,6 +504,8 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s
 				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else if (shader->output[i].name == TGSI_SEMANTIC_POSITION) {
 				output[i].array_base = 61;
+				output[i].swizzle_x = 2;
+				output[i].swizzle_y = output[i].swizzle_z = output[i].swizzle_w = 7;
 				output[i].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
 			} else {
 				R600_ERR("unsupported fragment output name %d\n", shader->output[i].name);
-- 
cgit v1.2.3


From d8c92a1eea555f8b9d673a3f2a708de5faf8b3cd Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Sun, 15 Aug 2010 18:19:52 +0100
Subject: llvmpipe: intrinsics versions of build_mask functions

---
 src/gallium/drivers/llvmpipe/lp_rast_tri.c | 78 +++++++++++++++++++++++++++++-
 1 file changed, 77 insertions(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri.c b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
index 8d729c7481..5b3ad6e0a7 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
@@ -67,7 +67,7 @@ block_full_16(struct lp_rasterizer_task *task,
 	 block_full_4(task, tri, x + ix, y + iy);
 }
 
-
+#if !defined(PIPE_ARCH_SSE)
 static INLINE unsigned
 build_mask(int c, int dcdx, int dcdy)
 {
@@ -98,6 +98,7 @@ build_mask(int c, int dcdx, int dcdy)
    return mask;
 }
 
+
 static INLINE unsigned
 build_mask_linear(int c, int dcdx, int dcdy)
 {
@@ -127,6 +128,81 @@ build_mask_linear(int c, int dcdx, int dcdy)
   
    return mask;
 }
+#else
+#include <emmintrin.h>
+#include "util/u_sse.h"
+
+
+static INLINE unsigned
+build_mask_linear(int c, int dcdx, int dcdy)
+{
+   __m128i cstep0 = _mm_setr_epi32(c, c+dcdx, c+dcdx*2, c+dcdx*3);
+   __m128i xdcdy = _mm_set1_epi32(dcdy);
+
+   /* Get values across the quad
+    */
+   __m128i cstep1 = _mm_add_epi32(cstep0, xdcdy);
+   __m128i cstep2 = _mm_add_epi32(cstep1, xdcdy);
+   __m128i cstep3 = _mm_add_epi32(cstep2, xdcdy);
+
+   /* pack pairs of results into epi16
+    */
+   __m128i cstep01 = _mm_packs_epi32(cstep0, cstep1);
+   __m128i cstep23 = _mm_packs_epi32(cstep2, cstep3);
+
+   /* pack into epi8, preserving sign bits
+    */
+   __m128i result = _mm_packs_epi16(cstep01, cstep23);
+
+   /* extract sign bits to create mask
+    */
+   return _mm_movemask_epi8(result);
+}
+
+static INLINE unsigned
+build_mask(int c, int dcdx, int dcdy)
+{
+   __m128i step = _mm_setr_epi32(0, dcdx, dcdy, dcdx + dcdy);
+   __m128i c0 = _mm_set1_epi32(c);
+
+   /* Get values across the quad
+    */
+   __m128i cstep0 = _mm_add_epi32(c0, step);
+
+   /* Scale up step for moving between quads.  This should probably
+    * be an arithmetic shift left, but there doesn't seem to be
+    * such a thing in SSE.  It's unlikely that the step value is
+    * going to be large enough to overflow across 4 pixels, though
+    * if it is that big, rendering will be incorrect anyway.
+    */
+   __m128i step4 = _mm_slli_epi32(step, 1);
+
+   /* Get values for the remaining quads:
+    */
+   __m128i cstep1 = _mm_add_epi32(cstep0, 
+				  _mm_shuffle_epi32(step4, _MM_SHUFFLE(1,1,1,1)));
+   __m128i cstep2 = _mm_add_epi32(cstep0,
+				  _mm_shuffle_epi32(step4, _MM_SHUFFLE(2,2,2,2)));
+   __m128i cstep3 = _mm_add_epi32(cstep2,
+				  _mm_shuffle_epi32(step4, _MM_SHUFFLE(1,1,1,1)));
+
+   /* pack pairs of results into epi16
+    */
+   __m128i cstep01 = _mm_packs_epi32(cstep0, cstep1);
+   __m128i cstep23 = _mm_packs_epi32(cstep2, cstep3);
+
+   /* pack into epi8, preserving sign bits
+    */
+   __m128i result = _mm_packs_epi16(cstep01, cstep23);
+
+   /* extract sign bits to create mask
+    */
+   return _mm_movemask_epi8(result);
+}
+
+#endif
+
+
 
 
 #define TAG(x) x##_1
-- 
cgit v1.2.3


From 0aa3a09ced07e150901cd0f7a7917556a018c252 Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Sun, 22 Aug 2010 22:56:54 +0100
Subject: llvmpipe: combine linear mask calculation

---
 src/gallium/drivers/llvmpipe/lp_rast_tri.c     | 73 ++++++++++++++++++++++++--
 src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h | 26 +++++----
 2 files changed, 84 insertions(+), 15 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri.c b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
index 5b3ad6e0a7..bdb8d131cc 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
@@ -128,11 +128,71 @@ build_mask_linear(int c, int dcdx, int dcdy)
   
    return mask;
 }
+
+
+static INLINE void
+build_masks(int c, 
+	    int cdiff,
+	    int dcdx,
+	    int dcdy,
+	    unsigned *outmask,
+	    unsigned *partmask)
+{
+   *outmask |= build_mask_linear(c, dcdx, dcdy);
+   *partmask |= build_mask_linear(c + cdiff, dcdx, dcdy);
+}
+
 #else
 #include <emmintrin.h>
 #include "util/u_sse.h"
 
 
+static INLINE void
+build_masks(int c, 
+	    int cdiff,
+	    int dcdx,
+	    int dcdy,
+	    unsigned *outmask,
+	    unsigned *partmask)
+{
+   __m128i cstep0 = _mm_setr_epi32(c, c+dcdx, c+dcdx*2, c+dcdx*3);
+   __m128i xdcdy = _mm_set1_epi32(dcdy);
+
+   /* Get values across the quad
+    */
+   __m128i cstep1 = _mm_add_epi32(cstep0, xdcdy);
+   __m128i cstep2 = _mm_add_epi32(cstep1, xdcdy);
+   __m128i cstep3 = _mm_add_epi32(cstep2, xdcdy);
+
+   {
+      __m128i cstep01, cstep23, result;
+
+      cstep01 = _mm_packs_epi32(cstep0, cstep1);
+      cstep23 = _mm_packs_epi32(cstep2, cstep3);
+      result = _mm_packs_epi16(cstep01, cstep23);
+
+      *outmask |= _mm_movemask_epi8(result);
+   }
+
+
+   {
+      __m128i cio4 = _mm_set1_epi32(cdiff);
+      __m128i cstep01, cstep23, result;
+
+      cstep0 = _mm_add_epi32(cstep0, cio4);
+      cstep1 = _mm_add_epi32(cstep1, cio4);
+      cstep2 = _mm_add_epi32(cstep2, cio4);
+      cstep3 = _mm_add_epi32(cstep3, cio4);
+
+      cstep01 = _mm_packs_epi32(cstep0, cstep1);
+      cstep23 = _mm_packs_epi32(cstep2, cstep3);
+      result = _mm_packs_epi16(cstep01, cstep23);
+
+      *partmask |= _mm_movemask_epi8(result);
+   }
+}
+
+
 static INLINE unsigned
 build_mask_linear(int c, int dcdx, int dcdy)
 {
@@ -263,11 +323,14 @@ lp_rast_triangle_3_16(struct lp_rasterizer_task *task,
       {
 	 const int dcdx = -plane[j].dcdx * 4;
 	 const int dcdy = plane[j].dcdy * 4;
-	 const int cox = c[j] + plane[j].eo * 4;
-	 const int cio = c[j] + plane[j].ei * 4 - 1;
-
-	 outmask |= build_mask_linear(cox, dcdx, dcdy);
-	 partmask |= build_mask_linear(cio, dcdx, dcdy);
+	 const int cox = plane[j].eo * 4;
+	 const int cio = plane[j].ei * 4 - 1;
+
+	 build_masks(c[j] + cox,
+		     cio - cox,
+		     dcdx, dcdy, 
+		     &outmask,   /* sign bits from c[i][0..15] + cox */
+		     &partmask); /* sign bits from c[i][0..15] + cio */
       }
    }
 
diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
index 0def5f7243..99a0bae45d 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri_tmp.h
@@ -81,11 +81,14 @@ TAG(do_block_16)(struct lp_rasterizer_task *task,
    for (j = 0; j < NR_PLANES; j++) {
       const int dcdx = -plane[j].dcdx * 4;
       const int dcdy = plane[j].dcdy * 4;
-      const int cox = c[j] + plane[j].eo * 4;
-      const int cio = c[j] + plane[j].ei * 4 - 1;
-
-      outmask |= build_mask_linear(cox, dcdx, dcdy);
-      partmask |= build_mask_linear(cio, dcdx, dcdy);
+      const int cox = plane[j].eo * 4;
+      const int cio = plane[j].ei * 4 - 1;
+
+      build_masks(c[j] + cox,
+		  cio - cox,
+		  dcdx, dcdy, 
+		  &outmask,   /* sign bits from c[i][0..15] + cox */
+		  &partmask); /* sign bits from c[i][0..15] + cio */
    }
 
    if (outmask == 0xffff)
@@ -171,11 +174,14 @@ TAG(lp_rast_triangle)(struct lp_rasterizer_task *task,
       {
 	 const int dcdx = -plane[j].dcdx * 16;
 	 const int dcdy = plane[j].dcdy * 16;
-	 const int cox = c[j] + plane[j].eo * 16;
-	 const int cio = c[j] + plane[j].ei * 16 - 1;
-
-	 outmask |= build_mask_linear(cox, dcdx, dcdy);
-	 partmask |= build_mask_linear(cio, dcdx, dcdy);
+	 const int cox = plane[j].eo * 16;
+	 const int cio = plane[j].ei * 16 - 1;
+
+	 build_masks(c[j] + cox,
+		     cio - cox,
+		     dcdx, dcdy, 
+		     &outmask,   /* sign bits from c[i][0..15] + cox */
+		     &partmask); /* sign bits from c[i][0..15] + cio */
       }
 
       j++;
-- 
cgit v1.2.3


From e38d2f716381385e2aad219a3d125065ec0a01bd Mon Sep 17 00:00:00 2001
From: Keith Whitwell <keithw@vmware.com>
Date: Tue, 24 Aug 2010 23:05:57 +0100
Subject: llvmpipe: slightly simplify build_mask

---
 src/gallium/drivers/llvmpipe/lp_rast_tri.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/llvmpipe/lp_rast_tri.c b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
index bdb8d131cc..dbaa8e023a 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast_tri.c
@@ -229,13 +229,9 @@ build_mask(int c, int dcdx, int dcdy)
     */
    __m128i cstep0 = _mm_add_epi32(c0, step);
 
-   /* Scale up step for moving between quads.  This should probably
-    * be an arithmetic shift left, but there doesn't seem to be
-    * such a thing in SSE.  It's unlikely that the step value is
-    * going to be large enough to overflow across 4 pixels, though
-    * if it is that big, rendering will be incorrect anyway.
+   /* Scale up step for moving between quads.
     */
-   __m128i step4 = _mm_slli_epi32(step, 1);
+   __m128i step4 = _mm_add_epi32(step, step);
 
    /* Get values for the remaining quads:
     */
-- 
cgit v1.2.3


From bea5f559a6f52e8fb7c32ee8e9f9c5f04c05b582 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 1 Sep 2010 11:37:39 +1000
Subject: r600g: fix glean texCube and shadows.

add cube and shadow support to the texture code.
---
 src/gallium/drivers/r600/r600_shader.c | 154 +++++++++++++++++++++++++++++++--
 1 file changed, 149 insertions(+), 5 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index bc1811129b..a26290062a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1470,6 +1470,9 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	struct r600_bc_alu alu;
 	unsigned src_gpr;
 	int r, i;
+	int opcode;
+	boolean src_not_temp = inst->Src[0].Register.File != TGSI_FILE_TEMPORARY;
+	uint32_t lit_vals[4];
 
 	src_gpr = ctx->file_offset[inst->Src[0].Register.File] + inst->Src[0].Register.Index;
 
@@ -1477,7 +1480,10 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		/* Add perspective divide */
 		memset(&alu, 0, sizeof(struct r600_bc_alu));
 		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
-		alu.src[0].sel = src_gpr;
+		r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+		if (r)
+			return r;
+
 		alu.src[0].chan = tgsi_chan(&inst->Src[0], 3);
 		alu.dst.sel = ctx->temp_reg;
 		alu.dst.chan = 3;
@@ -1492,7 +1498,9 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL;
 			alu.src[0].sel = ctx->temp_reg;
 			alu.src[0].chan = 3;
-			alu.src[1].sel = src_gpr;
+			r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
+			if (r)
+				return r;
 			alu.src[1].chan = tgsi_chan(&inst->Src[0], i);
 			alu.dst.sel = ctx->temp_reg;
 			alu.dst.chan = i;
@@ -1512,8 +1520,122 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		r = r600_bc_add_alu(ctx->bc, &alu);
 		if (r)
 			return r;
+		src_not_temp = false;
 		src_gpr = ctx->temp_reg;
-	} else if (inst->Src[0].Register.File != TGSI_FILE_TEMPORARY) {
+	}
+
+	if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
+		int src_chan, src2_chan;
+
+		/* tmp1.xyzw = CUBE(R0.zzxy, R0.yxzz) */
+		for (i = 0; i < 4; i++) {
+			memset(&alu, 0, sizeof(struct r600_bc_alu));
+			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
+			switch (i) {
+			case 0:
+				src_chan = 2;
+				src2_chan = 1;
+				break;
+			case 1:
+				src_chan = 2;
+				src2_chan = 0;
+				break;
+			case 2:
+				src_chan = 0;
+				src2_chan = 2;
+				break;
+			case 3:
+				src_chan = 1;
+				src2_chan = 2;
+				break;
+			}
+			r = tgsi_src(ctx, &inst->Src[0], &alu.src[0]);
+			if (r)
+				return r;
+			alu.src[0].chan = tgsi_chan(&inst->Src[0], src_chan);
+			r = tgsi_src(ctx, &inst->Src[0], &alu.src[1]);
+			if (r)
+				return r;
+			alu.src[1].chan = tgsi_chan(&inst->Src[0], src2_chan);
+			alu.dst.sel = ctx->temp_reg;
+			alu.dst.chan = i;
+			if (i == 3)
+				alu.last = 1;
+			alu.dst.write = 1;
+			r = r600_bc_add_alu(ctx->bc, &alu);
+			if (r)
+				return r;
+		}
+
+		/* tmp1.z = RCP_e(|tmp1.z|) */
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE;
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 2;
+		alu.src[0].abs = 1;
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 2;
+		alu.dst.write = 1;
+		alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+		
+		/* MULADD R0.x,  R0.x,  PS1,  (0x3FC00000, 1.5f).x
+		 * MULADD R0.y,  R0.y,  PS1,  (0x3FC00000, 1.5f).x
+		 * muladd has no writemask, have to use another temp 
+		 */
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
+		alu.is_op3 = 1;
+
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 0;
+		alu.src[1].sel = ctx->temp_reg;
+		alu.src[1].chan = 2;
+		
+		alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
+		alu.src[2].chan = 0;
+
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 0;
+		alu.dst.write = 1;
+
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+
+		memset(&alu, 0, sizeof(struct r600_bc_alu));
+		alu.inst = V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MULADD;
+		alu.is_op3 = 1;
+
+		alu.src[0].sel = ctx->temp_reg;
+		alu.src[0].chan = 1;
+		alu.src[1].sel = ctx->temp_reg;
+		alu.src[1].chan = 2;
+		
+		alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
+		alu.src[2].chan = 0;
+
+		alu.dst.sel = ctx->temp_reg;
+		alu.dst.chan = 1;
+		alu.dst.write = 1;
+
+		alu.last = 1;
+		r = r600_bc_add_alu(ctx->bc, &alu);
+		if (r)
+			return r;
+
+		lit_vals[0] = fui(1.5f);
+
+		r = r600_bc_add_literal(ctx->bc, lit_vals);
+		if (r)
+			return r;
+		src_not_temp = false;
+		src_gpr = ctx->temp_reg;
+	}
+
+	if (src_not_temp) {
 		for (i = 0; i < 4; i++) {
 			memset(&alu, 0, sizeof(struct r600_bc_alu));
 			alu.inst = V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV;
@@ -1530,9 +1652,14 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 		}
 		src_gpr = ctx->temp_reg;
 	}
+	
+	opcode = ctx->inst_info->r600_opcode;
+	if (opcode == SQ_TEX_INST_SAMPLE &&
+	    (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D))
+		opcode = SQ_TEX_INST_SAMPLE_C;
 
 	memset(&tex, 0, sizeof(struct r600_bc_tex));
-	tex.inst = ctx->inst_info->r600_opcode;
+	tex.inst = opcode;
 	tex.resource_id = ctx->file_offset[inst->Src[1].Register.File] + inst->Src[1].Register.Index;
 	tex.sampler_id = tex.resource_id;
 	tex.src_gpr = src_gpr;
@@ -1546,13 +1673,30 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	tex.src_sel_z = 2;
 	tex.src_sel_w = 3;
 
+	if (inst->Texture.Texture == TGSI_TEXTURE_CUBE) {
+		tex.src_sel_x = 1;
+		tex.src_sel_y = 0;
+		tex.src_sel_z = 3;
+		tex.src_sel_w = 1;
+	}
+
 	if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
 		tex.coord_type_x = 1;
 		tex.coord_type_y = 1;
 		tex.coord_type_z = 1;
 		tex.coord_type_w = 1;
 	}
-	return r600_bc_add_tex(ctx->bc, &tex);
+
+	if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
+		tex.coord_type_w = 2;
+
+	r = r600_bc_add_tex(ctx->bc, &tex);
+	if (r)
+		return r;
+
+	/* add shadow ambient support  - gallium doesn't do it yet */
+	return 0;
+	
 }
 
 static int tgsi_lrp(struct r600_shader_ctx *ctx)
-- 
cgit v1.2.3


From d7e2509692d3aa8afb8d2236a4f28b6ab502ec62 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 1 Sep 2010 13:54:38 +1000
Subject: r600g: fix typo causing segfault.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

fixes warning that
r600_blit.c: In function ‘r600_resource_copy_region’:
r600_blit.c:136: warning: passing argument 1 of ‘util_resource_copy_region’ from incompatible pointer type

and also 7 more piglit tests.
---
 src/gallium/drivers/r600/r600_blit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index dbcd6cdea8..a8263ccbce 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -132,7 +132,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 				      unsigned srcx, unsigned srcy, unsigned srcz,
 				      unsigned width, unsigned height)
 {
-	util_resource_copy_region(pipe, dst, subdst, dstx, dsty, dstz,
+	util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
 				  src, subsrc, srcx, srcy, srcz, width, height);
 }
 
-- 
cgit v1.2.3


From 1fa7245c348cb7aced81f1672140f64cb6450e2f Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 1 Sep 2010 14:56:04 +1000
Subject: Revert "r600g: precompute some of the hw state"

This reverts commit de0b76cab22caa9fc7260f80acb8f151ccced6c5, its pre-computes the texture state wrong,

you can't just use an array of levels, since you can have FBOs to depth texture slices inside a level as well
it would get really messy quickly. Probably need to split commits like this up into pieces for each piece
of state, so we can revert bits easier in case of regressions.

This also break 5 piglit tests, and valgrind starts to warn about invalid read/writes after this.
---
 src/gallium/drivers/r600/r600_blit.c       |   4 +-
 src/gallium/drivers/r600/r600_context.h    |   2 +-
 src/gallium/drivers/r600/r600_resource.h   |   2 +-
 src/gallium/drivers/r600/r600_screen.h     |   2 +-
 src/gallium/drivers/r600/r600_state.c      | 226 +++++++++++++++++++----------
 src/gallium/drivers/r600/r600_texture.c    |  43 ++----
 src/gallium/drivers/r600/radeon.h          |  47 ++----
 src/gallium/winsys/r600/drm/r600_state.c   |   9 +-
 src/gallium/winsys/r600/drm/r600_states.h  |  28 +---
 src/gallium/winsys/r600/drm/radeon_priv.h  |  20 +--
 src/gallium/winsys/r600/drm/radeon_state.c |  62 ++------
 11 files changed, 216 insertions(+), 229 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index a8263ccbce..1d197e92b2 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -670,7 +670,7 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		return r;
 	}
-	r = r600_texture_cb(ctx, rtexture, 0, level);
+	r = r600_texture_cb0(ctx, rtexture, level);
 	if (r) {
 		return r;
 	}
@@ -772,7 +772,7 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		goto out;
 	}
-	r = radeon_draw_set(draw, rtexture->cb[0][level]);
+	r = radeon_draw_set(draw, rtexture->cb0[level]);
 	if (r) {
 		goto out;
 	}
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index e9495f0017..d96d5b513f 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -121,7 +121,7 @@ struct r600_context_hw_states {
 	struct radeon_state	*config;
 	struct radeon_state	*cb_cntl;
 	struct radeon_state	*db;
-	struct radeon_state	*ucp;
+	struct radeon_state	*ucp[6];
 	unsigned		ps_nresource;
 	unsigned		ps_nsampler;
 	struct radeon_state	*ps_resource[160];
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 8078a83c35..b880f9369c 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -57,7 +57,7 @@ struct r600_resource_texture {
 	unsigned			dirty;
 	struct radeon_bo		*uncompressed;
 	struct radeon_state		*scissor[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*cb[8][PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		*cb0[PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*db[PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*viewport[PIPE_MAX_TEXTURE_LEVELS];
 };
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index b9938f117a..438976f654 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -84,7 +84,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 				 struct pipe_transfer* transfer);
 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level);
+int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 6049e1328e..b5db848e35 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -34,16 +34,6 @@
 #include "r600d.h"
 #include "r600_state_inlines.h"
 
-static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state);
-static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state);
-static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state);
-static struct radeon_state *r600_sampler(struct r600_context *rctx,
-				const struct pipe_sampler_state *state,
-				unsigned id);
-static struct radeon_state *r600_resource(struct pipe_context *ctx,
-					const struct pipe_sampler_view *view,
-					unsigned id);
-
 static void *r600_create_blend_state(struct pipe_context *ctx,
 					const struct pipe_blend_state *state)
 {
@@ -96,7 +86,6 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
 	rstate->state.sampler_view.context = ctx;
-	rstate->rstate = r600_resource(ctx, &rstate->state.sampler_view, 0);
 	return &rstate->state.sampler_view;
 }
 
@@ -240,9 +229,6 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
 		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
-		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
-		}
 	}
 	rctx->ps_nsampler = count;
 }
@@ -260,9 +246,6 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
 		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
-		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
-		}
 	}
 	rctx->vs_nsampler = count;
 }
@@ -354,9 +337,6 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
 		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
-		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
-		}
 	}
 	rctx->ps_nsampler_view = count;
 }
@@ -375,9 +355,6 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
 		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
-		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
-		}
 	}
 	rctx->vs_nsampler_view = count;
 }
@@ -386,19 +363,10 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 					const struct pipe_framebuffer_state *state)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct r600_resource_texture *rtexture;
 	struct r600_context_state *rstate;
 
 	rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
 	r600_bind_state(ctx, rstate);
-	for (int i = 0; i < state->nr_cbufs; i++) {
-		rtexture = (struct r600_resource_texture*)state->cbufs[i]->texture;
-		r600_texture_cb(ctx, rtexture, i, state->cbufs[i]->level);
-	}
-	if (state->zsbuf) {
-		rtexture = (struct r600_resource_texture*)state->zsbuf->texture;
-		r600_texture_db(ctx, rtexture, state->zsbuf->level);
-	}
 }
 
 static void r600_set_polygon_stipple(struct pipe_context *ctx,
@@ -597,7 +565,6 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_viewport_type:
 		rstate->state.viewport = (*states).viewport;
-		rstate->rstate = r600_viewport(rctx, &rstate->state.viewport);
 		break;
 	case pipe_depth_type:
 		rstate->state.depth = (*states).depth;
@@ -613,7 +580,6 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_clip_type:
 		rstate->state.clip = (*states).clip;
-		rstate->rstate = r600_ucp(rctx, &rstate->state.clip);
 		break;
 	case pipe_stencil_type:
 		rstate->state.stencil = (*states).stencil;
@@ -626,7 +592,6 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_blend_type:
 		rstate->state.blend = (*states).blend;
-		rstate->rstate = r600_blend(rctx, &rstate->state.blend);
 		break;
 	case pipe_stencil_ref_type:
 		rstate->state.stencil_ref = (*states).stencil_ref;
@@ -641,7 +606,6 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_sampler_type:
 		rstate->state.sampler = (*states).sampler;
-		rstate->rstate = r600_sampler(rctx, &rstate->state.sampler, 0);
 		break;
 	default:
 		R600_ERR("invalid type %d\n", rstate->type);
@@ -651,10 +615,11 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 	return rstate;
 }
 
-static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state)
+static struct radeon_state *r600_blend(struct r600_context *rctx)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
+	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
 
 	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
@@ -710,28 +675,129 @@ static struct radeon_state *r600_blend(struct r600_context *rctx, const struct p
 	return rstate;
 }
 
-static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state)
+static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
+	const struct pipe_clip_state *state = &rctx->clip->state.clip;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_UCP, 0);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CLIP, clip);
 	if (rstate == NULL)
 		return NULL;
 
-	for (int i = 0; i < state->nr; i++) {
-		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
-		rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
-		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
-		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
+	rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
+	rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
+	rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
+	rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
+
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
 	}
+	return rstate;
 
+}
+
+static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
+	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
+	unsigned level = state->cbufs[cb]->level;
+	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
+	if (rstate == NULL)
+		return NULL;
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	rbuffer = &rtex->resource;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+	rstate->nbo = 3;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_0280A0_NUMBER_SRGB;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+
+	color_info = S_0280A0_FORMAT(format) |
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_SOURCE_FORMAT(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
+
+	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
+	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+						S_028060_SLICE_TILE_MAX(slice);
+	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
 	if (radeon_state_pm4(rstate)) {
 		radeon_state_decref(rstate);
 		return NULL;
 	}
 	return rstate;
+}
 
+static struct radeon_state *r600_db(struct r600_context *rctx)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	struct radeon_state *rstate;
+	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
+	unsigned level;
+	unsigned pitch, slice, format;
+
+	if (state->zsbuf == NULL)
+		return NULL;
+
+	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
+	if (rstate == NULL)
+		return NULL;
+
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rtex->tilled = 1;
+	rtex->array_mode = 2;
+	rtex->tile_type = 1;
+	rtex->depth = 1;
+	rbuffer = &rtex->resource;
+
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	level = state->zsbuf->level;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
+	rstate->states[R600_DB__DB_DEPTH_BASE] = rtex->offset[level] >> 8;
+	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
+					S_028010_FORMAT(format);
+	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
+	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
+	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
+						S_028000_SLICE_TILE_MAX(slice);
+	if (radeon_state_pm4(rstate)) {
+		radeon_state_decref(rstate);
+		return NULL;
+	}
+	return rstate;
 }
 
 static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
@@ -888,8 +954,9 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	return rstate;
 }
 
-static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state)
+static struct radeon_state *r600_viewport(struct r600_context *rctx)
 {
+	const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
@@ -1299,7 +1366,6 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 int r600_context_hw_states(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct r600_resource_texture *rtexture;
 	unsigned i;
 	int r;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
@@ -1311,59 +1377,69 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	/* free previous TODO determine what need to be updated, what
 	 * doesn't
 	 */
+	//radeon_state_decref(rctx->hw_states.config);
 	rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
+	rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
 	rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
 	rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
 	rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
+	rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
+	rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
+	for (i = 0; i < 8; i++) {
+		rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
+	}
+	for (i = 0; i < 6; i++) {
+		rctx->hw_states.ucp[i] = radeon_state_decref(rctx->hw_states.ucp[i]);
+	}
+	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
+		radeon_state_decref(rctx->hw_states.ps_resource[i]);
+		rctx->hw_states.ps_resource[i] = NULL;
+	}
+	rctx->hw_states.ps_nresource = 0;
+	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
+		radeon_state_decref(rctx->hw_states.ps_sampler[i]);
+		rctx->hw_states.ps_sampler[i] = NULL;
+	}
+	rctx->hw_states.ps_nsampler = 0;
 
 	/* build new states */
-	rctx->hw_states.blend = NULL;
-	rctx->hw_states.viewport = NULL;
-	rctx->hw_states.ucp = NULL;
 	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
 	rctx->hw_states.scissor = r600_scissor(rctx);
 	rctx->hw_states.dsa = r600_dsa(rctx);
-	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
-	if (rctx->viewport) {
-		rctx->hw_states.viewport = rctx->viewport->rstate;
-	}
-	if (rctx->blend) {
-		rctx->hw_states.blend = rctx->blend->rstate;
-	}
-	if (rctx->clip) {
-		rctx->hw_states.ucp = rctx->clip->rstate;
-	}
-	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
-		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.cbufs[i]->texture;
-		rctx->hw_states.cb[i] = rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level];
+	rctx->hw_states.blend = r600_blend(rctx);
+	rctx->hw_states.viewport = r600_viewport(rctx);
+	for (i = 0; i < nr_cbufs; i++) {
+		rctx->hw_states.cb[i] = r600_cb(rctx, i);
 	}
-	if (rctx->framebuffer->state.framebuffer.zsbuf) {
-		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.zsbuf->texture;
-		rctx->hw_states.db = rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level];
+	for (i = 0; i < ucp_nclip; i++) {
+		rctx->hw_states.ucp[i] = r600_ucp(rctx, i);
 	}
-
+	rctx->hw_states.db = r600_db(rctx);
+	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
 
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			rctx->hw_states.ps_sampler[i] = rctx->ps_sampler[i]->rstate;
-		} else {
-			rctx->hw_states.ps_sampler[i] = NULL;
+			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
+							&rctx->ps_sampler[i]->state.sampler,
+							i);
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			rctx->hw_states.ps_resource[i] = rctx->ps_sampler_view[i]->rstate;
-		} else {
-			rctx->hw_states.ps_resource[i] = NULL;
+			rctx->hw_states.ps_resource[i] = r600_resource(ctx,
+							&rctx->ps_sampler_view[i]->state.sampler_view,
+							i);
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
 
 	/* bind states */
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp);
-	if (r)
-		return r;
+	for (i = 0; i < ucp_nclip; i++) {
+		r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp[i]);
+		if (r)
+			return r;
+	}
 	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
 	if (r)
 		return r;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index ec1d50566a..77d627cdc8 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -128,25 +128,13 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 	return &resource->base.b;
 }
 
-static void r600_texture_destroy_state(struct pipe_resource *ptexture)
-{
-	struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
-
-	for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
-		radeon_state_decref(rtexture->scissor[i]);
-		radeon_state_decref(rtexture->db[i]);
-		for (int j = 0; j < 8; j++) {
-			radeon_state_decref(rtexture->cb[j][i]);
-		}
-	}
-}
-
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
 	struct r600_screen *rscreen = r600_screen(screen);
+	unsigned i;
 
 	if (resource->bo) {
 		radeon_bo_decref(rscreen->rw, resource->bo);
@@ -154,7 +142,11 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	if (rtex->uncompressed) {
 		radeon_bo_decref(rscreen->rw, rtex->uncompressed);
 	}
-	r600_texture_destroy_state(ptex);
+	for (i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
+		radeon_state_decref(rtex->scissor[i]);
+		radeon_state_decref(rtex->cb0[i]);
+		radeon_state_decref(rtex->db[i]);
+	}
 	FREE(rtex);
 }
 
@@ -219,12 +211,9 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	pipe_reference_init(&resource->base.b.reference, 1);
 	resource->base.b.screen = screen;
 	resource->bo = bo;
-	rtex->depth = 0;
 	rtex->pitch_override = whandle->stride;
 	rtex->bpt = util_format_get_blocksize(templ->format);
 	rtex->pitch[0] = whandle->stride;
-	rtex->width[0] = templ->width0;
-	rtex->height[0] = templ->height0;
 	rtex->offset[0] = 0;
 	rtex->size = align(rtex->pitch[0] * templ->height0, 64);
 
@@ -707,9 +696,9 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 	return rstate;
 }
 
-static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
+static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 				struct r600_resource_texture *rtexture,
-				unsigned cb, unsigned level)
+				unsigned level)
 {
 	struct radeon_state *rstate;
 	struct r600_resource *rbuffer;
@@ -718,7 +707,7 @@ static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB0, 0);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -781,10 +770,6 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
-	rtexture->tilled = 1;
-	rtexture->array_mode = 2;
-	rtexture->tile_type = 1;
-	rtexture->depth = 1;
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -853,14 +838,14 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 	return rstate;
 }
 
-int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
+int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->cb[cb][level] == NULL) {
-		rtexture->cb[cb][level] = r600_texture_state_cb(rscreen, rtexture, cb, level);
-		if (rtexture->cb[cb][level] == NULL) {
-			R600_ERR("failed to create cb%d state for texture\n", cb);
+	if (rtexture->cb0[level] == NULL) {
+		rtexture->cb0[level] = r600_texture_state_cb0(rscreen, rtexture, level);
+		if (rtexture->cb0[level] == NULL) {
+			R600_ERR("failed to create cb0 state for texture\n");
 			return -ENOMEM;
 		}
 	}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 3f1ca95f69..046c264c04 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -109,11 +109,13 @@ struct radeon_state {
 	unsigned			id;
 	unsigned                        shader_index;
 	unsigned			nstates;
-	u32				states[64];
+	u32				*states;
 	unsigned			npm4;
 	unsigned			cpm4;
 	u32				pm4_crc;
-	u32				pm4[128];
+	u32				*pm4;
+	u32				nimmd;
+	u32				*immd;
 	unsigned			nbo;
 	struct radeon_bo		*bo[4];
 	unsigned			nreloc;
@@ -128,7 +130,6 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 type, u32 id
 struct radeon_state *radeon_state_incref(struct radeon_state *state);
 struct radeon_state *radeon_state_decref(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
-int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
 
 /*
  * draw functions
@@ -218,7 +219,7 @@ enum r600_stype {
 	R600_STATE_DB,
 	R600_STATE_QUERY_BEGIN,
 	R600_STATE_QUERY_END,
-	R600_STATE_UCP,
+	R600_STATE_CLIP,
 	R600_STATE_VGT,
 	R600_STATE_DRAW,
 };
@@ -612,37 +613,17 @@ enum {
 /* R600_DRAW */
 #define R600_DRAW__VGT_NUM_INDICES			0
 #define R600_DRAW__VGT_DMA_BASE_HI			1
-#define R600_DRAW__VGT_DMA_BASE				2
+#define R600_DRAW__VGT_DMA_BASE			2
 #define R600_DRAW__VGT_DRAW_INITIATOR			3
-#define R600_DRAW_SIZE					4
-#define R600_DRAW_PM4					128
+#define R600_DRAW_SIZE				4
+#define R600_DRAW_PM4				128
 /* R600_CLIP */
-#define R600_CLIP__PA_CL_UCP_X_0			0
-#define R600_CLIP__PA_CL_UCP_Y_0			1
-#define R600_CLIP__PA_CL_UCP_Z_0			2
-#define R600_CLIP__PA_CL_UCP_W_0			3
-#define R600_CLIP__PA_CL_UCP_X_1			4
-#define R600_CLIP__PA_CL_UCP_Y_1			5
-#define R600_CLIP__PA_CL_UCP_Z_1			6
-#define R600_CLIP__PA_CL_UCP_W_1			7
-#define R600_CLIP__PA_CL_UCP_X_2			8
-#define R600_CLIP__PA_CL_UCP_Y_2			9
-#define R600_CLIP__PA_CL_UCP_Z_2			10
-#define R600_CLIP__PA_CL_UCP_W_2			11
-#define R600_CLIP__PA_CL_UCP_X_3			12
-#define R600_CLIP__PA_CL_UCP_Y_3			13
-#define R600_CLIP__PA_CL_UCP_Z_3			14
-#define R600_CLIP__PA_CL_UCP_W_3			15
-#define R600_CLIP__PA_CL_UCP_X_4			16
-#define R600_CLIP__PA_CL_UCP_Y_4			17
-#define R600_CLIP__PA_CL_UCP_Z_4			18
-#define R600_CLIP__PA_CL_UCP_W_4			19
-#define R600_CLIP__PA_CL_UCP_X_5			20
-#define R600_CLIP__PA_CL_UCP_Y_5			21
-#define R600_CLIP__PA_CL_UCP_Z_5			22
-#define R600_CLIP__PA_CL_UCP_W_5			23
-#define R600_CLIP_SIZE					24
-#define R600_CLIP_PM4					128
+#define R600_CLIP__PA_CL_UCP_X_0  0
+#define R600_CLIP__PA_CL_UCP_Y_0  1
+#define R600_CLIP__PA_CL_UCP_Z_0  2
+#define R600_CLIP__PA_CL_UCP_W_0  3
+#define R600_CLIP_SIZE  4
+#define R600_CLIP_PM4 128
 /* R600 QUERY BEGIN/END */
 #define R600_QUERY__OFFSET			0
 #define R600_QUERY_SIZE				1
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index f6a428e884..e3d0116a2d 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -80,7 +80,7 @@ struct radeon_stype_info r600_stypes[] = {
 	{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
 	{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
 	{ R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
-	{ R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
+	{ R600_STATE_CLIP, 6, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
 	{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
 	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
 };
@@ -381,6 +381,13 @@ static int r600_state_pm4_draw(struct radeon_state *state)
 		if (r)
 			return r;
 		state->pm4[state->cpm4++] = state->bo[0]->handle;
+	} else if  (state->nimmd) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1);
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
+		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
+		for (i = 0; i < state->nimmd; i++) {
+			state->pm4[state->cpm4++] = state->immd[i];
+		}
 	} else {
 		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
 		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 09d79d498d..51b69b9220 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -284,30 +284,10 @@ static const struct radeon_register R600_names_VS_CONSTANT[] = {
 };
 
 static const struct radeon_register R600_names_UCP[] = {
-	{0x00028E20, 0, 0, "PA_CL_UCP0_X"},
-	{0x00028E24, 0, 0, "PA_CL_UCP0_Y"},
-	{0x00028E28, 0, 0, "PA_CL_UCP0_Z"},
-	{0x00028E2C, 0, 0, "PA_CL_UCP0_W"},
-	{0x00028E30, 0, 0, "PA_CL_UCP1_X"},
-	{0x00028E34, 0, 0, "PA_CL_UCP1_Y"},
-	{0x00028E38, 0, 0, "PA_CL_UCP1_Z"},
-	{0x00028E3C, 0, 0, "PA_CL_UCP1_W"},
-	{0x00028E40, 0, 0, "PA_CL_UCP2_X"},
-	{0x00028E44, 0, 0, "PA_CL_UCP2_Y"},
-	{0x00028E48, 0, 0, "PA_CL_UCP2_Z"},
-	{0x00028E4C, 0, 0, "PA_CL_UCP2_W"},
-	{0x00028E50, 0, 0, "PA_CL_UCP3_X"},
-	{0x00028E54, 0, 0, "PA_CL_UCP3_Y"},
-	{0x00028E58, 0, 0, "PA_CL_UCP3_Z"},
-	{0x00028E5C, 0, 0, "PA_CL_UCP3_W"},
-	{0x00028E60, 0, 0, "PA_CL_UCP4_X"},
-	{0x00028E64, 0, 0, "PA_CL_UCP4_Y"},
-	{0x00028E68, 0, 0, "PA_CL_UCP4_Z"},
-	{0x00028E6C, 0, 0, "PA_CL_UCP4_W"},
-	{0x00028E70, 0, 0, "PA_CL_UCP5_X"},
-	{0x00028E74, 0, 0, "PA_CL_UCP5_Y"},
-	{0x00028E78, 0, 0, "PA_CL_UCP5_Z"},
-	{0x00028E7C, 0, 0, "PA_CL_UCP5_W"},
+	{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
+	{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
+	{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
+	{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
 };
 
 static const struct radeon_register R600_names_PS_RESOURCE[] = {
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index af5319efd1..66ee5f2177 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -38,19 +38,19 @@ struct radeon_register {
 };
 
 struct radeon_sub_type {
-	int				shader_type;
-	const struct radeon_register	*regs;
-	unsigned			nstates;
+	int shader_type;
+	const struct radeon_register *regs;
+	unsigned nstates;
 };
 
 struct radeon_stype_info {
-	unsigned			stype;
-	unsigned			num;
-	unsigned			stride;
-	radeon_state_pm4_t		pm4;
-	struct radeon_sub_type		reginfo[R600_SHADER_MAX];
-	unsigned			base_id;
-	unsigned			npm4;
+	unsigned stype;
+	unsigned num;
+	unsigned stride;
+	radeon_state_pm4_t pm4;
+	struct radeon_sub_type reginfo[R600_SHADER_MAX];
+	unsigned base_id;
+	unsigned npm4;
 };
 
 struct radeon {
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index d4e622cf7f..ef09fdfb96 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -80,57 +80,13 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 i
 	state->refcount = 1;
 	state->npm4 = found->npm4;
 	state->nstates = found->reginfo[shader_index].nstates;
-	return state;
-}
-
-int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type)
-{
-	struct radeon_stype_info *found = NULL;
-	int i, j, shader_index = -1;
-
-	if (state == NULL)
-		return 0;
-	/* traverse the stype array */
-	for (i = 0; i < state->radeon->nstype; i++) {
-		/* if the type doesn't match, if the shader doesn't match */
-		if (stype != state->radeon->stype[i].stype)
-			continue;
-		if (shader_type) {
-			for (j = 0; j < 4; j++) {
-				if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) {
-					shader_index = j;
-					break;
-				}
-			}
-			if (shader_index == -1)
-				continue;
-		} else {
-			if (state->radeon->stype[i].reginfo[0].shader_type)
-				continue;
-			else
-				shader_index = 0;
-		}
-		if (id > state->radeon->stype[i].num)
-			continue;
-		
-		found = &state->radeon->stype[i];
-		break;
-	}
-
-	if (!found) {
-		fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
-		return -EINVAL;
-	}
-
-	if (found->reginfo[shader_index].nstates != state->nstates) {
-		fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n",
-			state->stype->stype, state->id, state->shader_index, stype, id, shader_index);
+	state->states = calloc(1, state->nstates * 4);
+	state->pm4 = calloc(1, found->npm4 * 4);
+	if (state->states == NULL || state->pm4 == NULL) {
+		radeon_state_decref(state);
+		return NULL;
 	}
-
-	state->stype = found;
-	state->id = id;
-	state->shader_index = shader_index;
-	return radeon_state_pm4(state);
+	return state;
 }
 
 struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
@@ -178,6 +134,9 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
 	for (i = 0; i < state->nbo; i++) {
 		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
 	}
+	free(state->immd);
+	free(state->states);
+	free(state->pm4);
 	memset(state, 0, sizeof(*state));
 	free(state);
 	return NULL;
@@ -220,9 +179,8 @@ int radeon_state_pm4(struct radeon_state *state)
 {
 	int r;
 
-	if (state == NULL)
+	if (state == NULL || state->cpm4)
 		return 0;
-	state->cpm4 = 0;
 	r = state->stype->pm4(state);
 	if (r) {
 		fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
-- 
cgit v1.2.3


From 1d7b4af81781512b5bc5d43249529441d60ecebe Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Wed, 1 Sep 2010 14:28:55 +1000
Subject: r600g: correct cb/zb offset emits.

This fixes fbo-3d and fbo-cubemap
---
 src/gallium/drivers/r600/r600_state.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index b5db848e35..e2265ace97 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -740,7 +740,7 @@ static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
 		S_0280A0_SOURCE_FORMAT(1) |
 		S_0280A0_NUMBER_TYPE(ntype);
 
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = rtex->offset[level] >> 8;
+	rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
 	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
@@ -786,7 +786,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
 	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
 	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
 	format = r600_translate_dbformat(state->zsbuf->texture->format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = rtex->offset[level] >> 8;
+	rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
 	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
 					S_028010_FORMAT(format);
 	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-- 
cgit v1.2.3


From 4a955ab6b78e3b3a4cdd54dc933715f0dafbe7f4 Mon Sep 17 00:00:00 2001
From: Patrice Mandin <patmandin@gmail.com>
Date: Wed, 1 Sep 2010 18:12:11 +0200
Subject: nouveau/nvfx: Remove enforcement of bit depth being same as front
 buffer

Signed-off-by: Patrice Mandin <patmandin@gmail.com>
---
 src/gallium/drivers/nvfx/nvfx_screen.c | 17 -----------------
 1 file changed, 17 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index 99b4d8b58c..65ca265d45 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -14,18 +14,6 @@
 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
 
-/* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
-* to get the pointer to the context front buffer, so I copied nouveau_winsys here.
-* nv30_screen_surface_format_supported() can then use it to enforce creating fbo
-* with same number of bits everywhere.
-*/
-struct nouveau_winsys {
-	struct pipe_winsys base;
-
-	struct pipe_screen *pscreen;
-
-	struct pipe_surface *front;
-};
 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
@@ -170,7 +158,6 @@ nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 				     unsigned bind, unsigned geom_flags)
 {
 	struct nvfx_screen *screen = nvfx_screen(pscreen);
-	struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 
 	 if (sample_count > 1)
 		return FALSE;
@@ -190,11 +177,7 @@ nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 		switch (format) {
 		case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 		case PIPE_FORMAT_X8Z24_UNORM:
-			break;
 		case PIPE_FORMAT_Z16_UNORM:
-			/* TODO: this nv30 limitation probably does not exist */
-			if (!screen->is_nv4x && front && front->format != PIPE_FORMAT_B5G6R5_UNORM)
-				return FALSE;
 			break;
 		default:
 			return FALSE;
-- 
cgit v1.2.3


From 15ce70252c5357081a61f3494261c7e343174301 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 1 Sep 2010 13:04:42 -0400
Subject: Revert "Revert "r600g: precompute some of the hw state""

This reverts commit 1fa7245c348cb7aced81f1672140f64cb6450e2f.

Conflicts:

	src/gallium/drivers/r600/r600_state.c
---
 src/gallium/drivers/r600/r600_blit.c       |   4 +-
 src/gallium/drivers/r600/r600_context.h    |   2 +-
 src/gallium/drivers/r600/r600_resource.h   |   2 +-
 src/gallium/drivers/r600/r600_screen.h     |   2 +-
 src/gallium/drivers/r600/r600_state.c      | 130 +++++++++++++++++------------
 src/gallium/drivers/r600/r600_texture.c    |  43 ++++++----
 src/gallium/drivers/r600/radeon.h          |  47 +++++++----
 src/gallium/winsys/r600/drm/r600_state.c   |   9 +-
 src/gallium/winsys/r600/drm/r600_states.h  |  28 ++++++-
 src/gallium/winsys/r600/drm/radeon_priv.h  |  20 ++---
 src/gallium/winsys/r600/drm/radeon_state.c |  62 +++++++++++---
 11 files changed, 229 insertions(+), 120 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index 1d197e92b2..a8263ccbce 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -670,7 +670,7 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		return r;
 	}
-	r = r600_texture_cb0(ctx, rtexture, level);
+	r = r600_texture_cb(ctx, rtexture, 0, level);
 	if (r) {
 		return r;
 	}
@@ -772,7 +772,7 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		goto out;
 	}
-	r = radeon_draw_set(draw, rtexture->cb0[level]);
+	r = radeon_draw_set(draw, rtexture->cb[0][level]);
 	if (r) {
 		goto out;
 	}
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index d96d5b513f..e9495f0017 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -121,7 +121,7 @@ struct r600_context_hw_states {
 	struct radeon_state	*config;
 	struct radeon_state	*cb_cntl;
 	struct radeon_state	*db;
-	struct radeon_state	*ucp[6];
+	struct radeon_state	*ucp;
 	unsigned		ps_nresource;
 	unsigned		ps_nsampler;
 	struct radeon_state	*ps_resource[160];
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index b880f9369c..8078a83c35 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -57,7 +57,7 @@ struct r600_resource_texture {
 	unsigned			dirty;
 	struct radeon_bo		*uncompressed;
 	struct radeon_state		*scissor[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*cb0[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		*cb[8][PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*db[PIPE_MAX_TEXTURE_LEVELS];
 	struct radeon_state		*viewport[PIPE_MAX_TEXTURE_LEVELS];
 };
diff --git a/src/gallium/drivers/r600/r600_screen.h b/src/gallium/drivers/r600/r600_screen.h
index 438976f654..b9938f117a 100644
--- a/src/gallium/drivers/r600/r600_screen.h
+++ b/src/gallium/drivers/r600/r600_screen.h
@@ -84,7 +84,7 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
 void r600_texture_transfer_unmap(struct pipe_context *ctx,
 				 struct pipe_transfer* transfer);
 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
-int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
+int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level);
 int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
 int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index e2265ace97..d8f53f2ce8 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -34,6 +34,16 @@
 #include "r600d.h"
 #include "r600_state_inlines.h"
 
+static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state);
+static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state);
+static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state);
+static struct radeon_state *r600_sampler(struct r600_context *rctx,
+				const struct pipe_sampler_state *state,
+				unsigned id);
+static struct radeon_state *r600_resource(struct pipe_context *ctx,
+					const struct pipe_sampler_view *view,
+					unsigned id);
+
 static void *r600_create_blend_state(struct pipe_context *ctx,
 					const struct pipe_blend_state *state)
 {
@@ -86,6 +96,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
 	rstate->state.sampler_view.context = ctx;
+	rstate->rstate = r600_resource(ctx, &rstate->state.sampler_view, 0);
 	return &rstate->state.sampler_view;
 }
 
@@ -229,6 +240,9 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
 		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
+		}
 	}
 	rctx->ps_nsampler = count;
 }
@@ -246,6 +260,9 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
 		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
+		}
 	}
 	rctx->vs_nsampler = count;
 }
@@ -337,6 +354,9 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
 		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
+		}
 	}
 	rctx->ps_nsampler_view = count;
 }
@@ -355,6 +375,9 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
 		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
+		if (rstate) {
+			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
+		}
 	}
 	rctx->vs_nsampler_view = count;
 }
@@ -363,10 +386,19 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 					const struct pipe_framebuffer_state *state)
 {
 	struct r600_context *rctx = r600_context(ctx);
+	struct r600_resource_texture *rtexture;
 	struct r600_context_state *rstate;
 
 	rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
 	r600_bind_state(ctx, rstate);
+	for (int i = 0; i < state->nr_cbufs; i++) {
+		rtexture = (struct r600_resource_texture*)state->cbufs[i]->texture;
+		r600_texture_cb(ctx, rtexture, i, state->cbufs[i]->level);
+	}
+	if (state->zsbuf) {
+		rtexture = (struct r600_resource_texture*)state->zsbuf->texture;
+		r600_texture_db(ctx, rtexture, state->zsbuf->level);
+	}
 }
 
 static void r600_set_polygon_stipple(struct pipe_context *ctx,
@@ -565,6 +597,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_viewport_type:
 		rstate->state.viewport = (*states).viewport;
+		rstate->rstate = r600_viewport(rctx, &rstate->state.viewport);
 		break;
 	case pipe_depth_type:
 		rstate->state.depth = (*states).depth;
@@ -580,6 +613,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_clip_type:
 		rstate->state.clip = (*states).clip;
+		rstate->rstate = r600_ucp(rctx, &rstate->state.clip);
 		break;
 	case pipe_stencil_type:
 		rstate->state.stencil = (*states).stencil;
@@ -592,6 +626,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_blend_type:
 		rstate->state.blend = (*states).blend;
+		rstate->rstate = r600_blend(rctx, &rstate->state.blend);
 		break;
 	case pipe_stencil_ref_type:
 		rstate->state.stencil_ref = (*states).stencil_ref;
@@ -606,6 +641,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_sampler_type:
 		rstate->state.sampler = (*states).sampler;
+		rstate->rstate = r600_sampler(rctx, &rstate->state.sampler, 0);
 		break;
 	default:
 		R600_ERR("invalid type %d\n", rstate->type);
@@ -615,11 +651,10 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 	return rstate;
 }
 
-static struct radeon_state *r600_blend(struct r600_context *rctx)
+static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
-	const struct pipe_blend_state *state = &rctx->blend->state.blend;
 	int i;
 
 	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
@@ -675,27 +710,22 @@ static struct radeon_state *r600_blend(struct r600_context *rctx)
 	return rstate;
 }
 
-static struct radeon_state *r600_ucp(struct r600_context *rctx, int clip)
+static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
-	const struct pipe_clip_state *state = &rctx->clip->state.clip;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_CLIP, clip);
+	rstate = radeon_state(rscreen->rw, R600_STATE_UCP, 0);
 	if (rstate == NULL)
 		return NULL;
 
-	rstate->states[R600_CLIP__PA_CL_UCP_X_0] = fui(state->ucp[clip][0]);
-	rstate->states[R600_CLIP__PA_CL_UCP_Y_0] = fui(state->ucp[clip][1]);
-	rstate->states[R600_CLIP__PA_CL_UCP_Z_0] = fui(state->ucp[clip][2]);
-	rstate->states[R600_CLIP__PA_CL_UCP_W_0] = fui(state->ucp[clip][3]);
-
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
+	for (int i = 0; i < state->nr; i++) {
+		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
+		rstate->states[i * 4 + 1] = fui(state->ucp[i][1]);
+		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
+		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
 	}
 	return rstate;
-
 }
 
 static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
@@ -954,9 +984,8 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	return rstate;
 }
 
-static struct radeon_state *r600_viewport(struct r600_context *rctx)
+static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state)
 {
-	const struct pipe_viewport_state *state = &rctx->viewport->state.viewport;
 	struct r600_screen *rscreen = rctx->screen;
 	struct radeon_state *rstate;
 
@@ -1366,6 +1395,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 int r600_context_hw_states(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = r600_context(ctx);
+	struct r600_resource_texture *rtexture;
 	unsigned i;
 	int r;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
@@ -1377,69 +1407,59 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	/* free previous TODO determine what need to be updated, what
 	 * doesn't
 	 */
-	//radeon_state_decref(rctx->hw_states.config);
 	rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
-	rctx->hw_states.db = radeon_state_decref(rctx->hw_states.db);
 	rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
 	rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
 	rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
-	rctx->hw_states.blend = radeon_state_decref(rctx->hw_states.blend);
-	rctx->hw_states.viewport = radeon_state_decref(rctx->hw_states.viewport);
-	for (i = 0; i < 8; i++) {
-		rctx->hw_states.cb[i] = radeon_state_decref(rctx->hw_states.cb[i]);
-	}
-	for (i = 0; i < 6; i++) {
-		rctx->hw_states.ucp[i] = radeon_state_decref(rctx->hw_states.ucp[i]);
-	}
-	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
-		radeon_state_decref(rctx->hw_states.ps_resource[i]);
-		rctx->hw_states.ps_resource[i] = NULL;
-	}
-	rctx->hw_states.ps_nresource = 0;
-	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
-		radeon_state_decref(rctx->hw_states.ps_sampler[i]);
-		rctx->hw_states.ps_sampler[i] = NULL;
-	}
-	rctx->hw_states.ps_nsampler = 0;
 
 	/* build new states */
+	rctx->hw_states.blend = NULL;
+	rctx->hw_states.viewport = NULL;
+	rctx->hw_states.ucp = NULL;
 	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
 	rctx->hw_states.scissor = r600_scissor(rctx);
 	rctx->hw_states.dsa = r600_dsa(rctx);
-	rctx->hw_states.blend = r600_blend(rctx);
-	rctx->hw_states.viewport = r600_viewport(rctx);
-	for (i = 0; i < nr_cbufs; i++) {
-		rctx->hw_states.cb[i] = r600_cb(rctx, i);
+	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
+	if (rctx->viewport) {
+		rctx->hw_states.viewport = rctx->viewport->rstate;
 	}
-	for (i = 0; i < ucp_nclip; i++) {
-		rctx->hw_states.ucp[i] = r600_ucp(rctx, i);
+	if (rctx->blend) {
+		rctx->hw_states.blend = rctx->blend->rstate;
+	}
+	if (rctx->clip) {
+		rctx->hw_states.ucp = rctx->clip->rstate;
+	}
+	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
+		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.cbufs[i]->texture;
+		rctx->hw_states.cb[i] = rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level];
+	}
+	if (rctx->framebuffer->state.framebuffer.zsbuf) {
+		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.zsbuf->texture;
+		rctx->hw_states.db = rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level];
 	}
-	rctx->hw_states.db = r600_db(rctx);
-	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
+
 
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			rctx->hw_states.ps_sampler[i] = r600_sampler(rctx,
-							&rctx->ps_sampler[i]->state.sampler,
-							i);
+			rctx->hw_states.ps_sampler[i] = rctx->ps_sampler[i]->rstate;
+		} else {
+			rctx->hw_states.ps_sampler[i] = NULL;
 		}
 	}
 	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			rctx->hw_states.ps_resource[i] = r600_resource(ctx,
-							&rctx->ps_sampler_view[i]->state.sampler_view,
-							i);
+			rctx->hw_states.ps_resource[i] = rctx->ps_sampler_view[i]->rstate;
+		} else {
+			rctx->hw_states.ps_resource[i] = NULL;
 		}
 	}
 	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
 
 	/* bind states */
-	for (i = 0; i < ucp_nclip; i++) {
-		r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp[i]);
-		if (r)
-			return r;
-	}
+	r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp);
+	if (r)
+		return r;
 	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
 	if (r)
 		return r;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 77d627cdc8..ec1d50566a 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -128,13 +128,25 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 	return &resource->base.b;
 }
 
+static void r600_texture_destroy_state(struct pipe_resource *ptexture)
+{
+	struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
+
+	for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
+		radeon_state_decref(rtexture->scissor[i]);
+		radeon_state_decref(rtexture->db[i]);
+		for (int j = 0; j < 8; j++) {
+			radeon_state_decref(rtexture->cb[j][i]);
+		}
+	}
+}
+
 static void r600_texture_destroy(struct pipe_screen *screen,
 				 struct pipe_resource *ptex)
 {
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
 	struct r600_screen *rscreen = r600_screen(screen);
-	unsigned i;
 
 	if (resource->bo) {
 		radeon_bo_decref(rscreen->rw, resource->bo);
@@ -142,11 +154,7 @@ static void r600_texture_destroy(struct pipe_screen *screen,
 	if (rtex->uncompressed) {
 		radeon_bo_decref(rscreen->rw, rtex->uncompressed);
 	}
-	for (i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
-		radeon_state_decref(rtex->scissor[i]);
-		radeon_state_decref(rtex->cb0[i]);
-		radeon_state_decref(rtex->db[i]);
-	}
+	r600_texture_destroy_state(ptex);
 	FREE(rtex);
 }
 
@@ -211,9 +219,12 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	pipe_reference_init(&resource->base.b.reference, 1);
 	resource->base.b.screen = screen;
 	resource->bo = bo;
+	rtex->depth = 0;
 	rtex->pitch_override = whandle->stride;
 	rtex->bpt = util_format_get_blocksize(templ->format);
 	rtex->pitch[0] = whandle->stride;
+	rtex->width[0] = templ->width0;
+	rtex->height[0] = templ->height0;
 	rtex->offset[0] = 0;
 	rtex->size = align(rtex->pitch[0] * templ->height0, 64);
 
@@ -696,9 +707,9 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 	return rstate;
 }
 
-static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
+static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
 				struct r600_resource_texture *rtexture,
-				unsigned level)
+				unsigned cb, unsigned level)
 {
 	struct radeon_state *rstate;
 	struct r600_resource *rbuffer;
@@ -707,7 +718,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0, 0);
+	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
@@ -770,6 +781,10 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	if (rstate == NULL)
 		return NULL;
 	rbuffer = &rtexture->resource;
+	rtexture->tilled = 1;
+	rtexture->array_mode = 2;
+	rtexture->tile_type = 1;
+	rtexture->depth = 1;
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -838,14 +853,14 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 	return rstate;
 }
 
-int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
+int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->cb0[level] == NULL) {
-		rtexture->cb0[level] = r600_texture_state_cb0(rscreen, rtexture, level);
-		if (rtexture->cb0[level] == NULL) {
-			R600_ERR("failed to create cb0 state for texture\n");
+	if (rtexture->cb[cb][level] == NULL) {
+		rtexture->cb[cb][level] = r600_texture_state_cb(rscreen, rtexture, cb, level);
+		if (rtexture->cb[cb][level] == NULL) {
+			R600_ERR("failed to create cb%d state for texture\n", cb);
 			return -ENOMEM;
 		}
 	}
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 046c264c04..3f1ca95f69 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -109,13 +109,11 @@ struct radeon_state {
 	unsigned			id;
 	unsigned                        shader_index;
 	unsigned			nstates;
-	u32				*states;
+	u32				states[64];
 	unsigned			npm4;
 	unsigned			cpm4;
 	u32				pm4_crc;
-	u32				*pm4;
-	u32				nimmd;
-	u32				*immd;
+	u32				pm4[128];
 	unsigned			nbo;
 	struct radeon_bo		*bo[4];
 	unsigned			nreloc;
@@ -130,6 +128,7 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 type, u32 id
 struct radeon_state *radeon_state_incref(struct radeon_state *state);
 struct radeon_state *radeon_state_decref(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
+int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
 
 /*
  * draw functions
@@ -219,7 +218,7 @@ enum r600_stype {
 	R600_STATE_DB,
 	R600_STATE_QUERY_BEGIN,
 	R600_STATE_QUERY_END,
-	R600_STATE_CLIP,
+	R600_STATE_UCP,
 	R600_STATE_VGT,
 	R600_STATE_DRAW,
 };
@@ -613,17 +612,37 @@ enum {
 /* R600_DRAW */
 #define R600_DRAW__VGT_NUM_INDICES			0
 #define R600_DRAW__VGT_DMA_BASE_HI			1
-#define R600_DRAW__VGT_DMA_BASE			2
+#define R600_DRAW__VGT_DMA_BASE				2
 #define R600_DRAW__VGT_DRAW_INITIATOR			3
-#define R600_DRAW_SIZE				4
-#define R600_DRAW_PM4				128
+#define R600_DRAW_SIZE					4
+#define R600_DRAW_PM4					128
 /* R600_CLIP */
-#define R600_CLIP__PA_CL_UCP_X_0  0
-#define R600_CLIP__PA_CL_UCP_Y_0  1
-#define R600_CLIP__PA_CL_UCP_Z_0  2
-#define R600_CLIP__PA_CL_UCP_W_0  3
-#define R600_CLIP_SIZE  4
-#define R600_CLIP_PM4 128
+#define R600_CLIP__PA_CL_UCP_X_0			0
+#define R600_CLIP__PA_CL_UCP_Y_0			1
+#define R600_CLIP__PA_CL_UCP_Z_0			2
+#define R600_CLIP__PA_CL_UCP_W_0			3
+#define R600_CLIP__PA_CL_UCP_X_1			4
+#define R600_CLIP__PA_CL_UCP_Y_1			5
+#define R600_CLIP__PA_CL_UCP_Z_1			6
+#define R600_CLIP__PA_CL_UCP_W_1			7
+#define R600_CLIP__PA_CL_UCP_X_2			8
+#define R600_CLIP__PA_CL_UCP_Y_2			9
+#define R600_CLIP__PA_CL_UCP_Z_2			10
+#define R600_CLIP__PA_CL_UCP_W_2			11
+#define R600_CLIP__PA_CL_UCP_X_3			12
+#define R600_CLIP__PA_CL_UCP_Y_3			13
+#define R600_CLIP__PA_CL_UCP_Z_3			14
+#define R600_CLIP__PA_CL_UCP_W_3			15
+#define R600_CLIP__PA_CL_UCP_X_4			16
+#define R600_CLIP__PA_CL_UCP_Y_4			17
+#define R600_CLIP__PA_CL_UCP_Z_4			18
+#define R600_CLIP__PA_CL_UCP_W_4			19
+#define R600_CLIP__PA_CL_UCP_X_5			20
+#define R600_CLIP__PA_CL_UCP_Y_5			21
+#define R600_CLIP__PA_CL_UCP_Z_5			22
+#define R600_CLIP__PA_CL_UCP_W_5			23
+#define R600_CLIP_SIZE					24
+#define R600_CLIP_PM4					128
 /* R600 QUERY BEGIN/END */
 #define R600_QUERY__OFFSET			0
 #define R600_QUERY_SIZE				1
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index e3d0116a2d..f6a428e884 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -80,7 +80,7 @@ struct radeon_stype_info r600_stypes[] = {
 	{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
 	{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
 	{ R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
-	{ R600_STATE_CLIP, 6, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
+	{ R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
 	{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
 	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
 };
@@ -381,13 +381,6 @@ static int r600_state_pm4_draw(struct radeon_state *state)
 		if (r)
 			return r;
 		state->pm4[state->cpm4++] = state->bo[0]->handle;
-	} else if  (state->nimmd) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_IMMD, state->nimmd + 1);
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
-		for (i = 0; i < state->nimmd; i++) {
-			state->pm4[state->cpm4++] = state->immd[i];
-		}
 	} else {
 		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
 		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
diff --git a/src/gallium/winsys/r600/drm/r600_states.h b/src/gallium/winsys/r600/drm/r600_states.h
index 51b69b9220..09d79d498d 100644
--- a/src/gallium/winsys/r600/drm/r600_states.h
+++ b/src/gallium/winsys/r600/drm/r600_states.h
@@ -284,10 +284,30 @@ static const struct radeon_register R600_names_VS_CONSTANT[] = {
 };
 
 static const struct radeon_register R600_names_UCP[] = {
-	{0x00028e20, 0, 0, "PA_CL_UCP0_X"},
-	{0x00028e24, 0, 0, "PA_CL_UCP0_Y"},
-	{0x00028e28, 0, 0, "PA_CL_UCP0_Z"},
-	{0x00028e2c, 0, 0, "PA_CL_UCP0_W"},
+	{0x00028E20, 0, 0, "PA_CL_UCP0_X"},
+	{0x00028E24, 0, 0, "PA_CL_UCP0_Y"},
+	{0x00028E28, 0, 0, "PA_CL_UCP0_Z"},
+	{0x00028E2C, 0, 0, "PA_CL_UCP0_W"},
+	{0x00028E30, 0, 0, "PA_CL_UCP1_X"},
+	{0x00028E34, 0, 0, "PA_CL_UCP1_Y"},
+	{0x00028E38, 0, 0, "PA_CL_UCP1_Z"},
+	{0x00028E3C, 0, 0, "PA_CL_UCP1_W"},
+	{0x00028E40, 0, 0, "PA_CL_UCP2_X"},
+	{0x00028E44, 0, 0, "PA_CL_UCP2_Y"},
+	{0x00028E48, 0, 0, "PA_CL_UCP2_Z"},
+	{0x00028E4C, 0, 0, "PA_CL_UCP2_W"},
+	{0x00028E50, 0, 0, "PA_CL_UCP3_X"},
+	{0x00028E54, 0, 0, "PA_CL_UCP3_Y"},
+	{0x00028E58, 0, 0, "PA_CL_UCP3_Z"},
+	{0x00028E5C, 0, 0, "PA_CL_UCP3_W"},
+	{0x00028E60, 0, 0, "PA_CL_UCP4_X"},
+	{0x00028E64, 0, 0, "PA_CL_UCP4_Y"},
+	{0x00028E68, 0, 0, "PA_CL_UCP4_Z"},
+	{0x00028E6C, 0, 0, "PA_CL_UCP4_W"},
+	{0x00028E70, 0, 0, "PA_CL_UCP5_X"},
+	{0x00028E74, 0, 0, "PA_CL_UCP5_Y"},
+	{0x00028E78, 0, 0, "PA_CL_UCP5_Z"},
+	{0x00028E7C, 0, 0, "PA_CL_UCP5_W"},
 };
 
 static const struct radeon_register R600_names_PS_RESOURCE[] = {
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index 66ee5f2177..af5319efd1 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -38,19 +38,19 @@ struct radeon_register {
 };
 
 struct radeon_sub_type {
-	int shader_type;
-	const struct radeon_register *regs;
-	unsigned nstates;
+	int				shader_type;
+	const struct radeon_register	*regs;
+	unsigned			nstates;
 };
 
 struct radeon_stype_info {
-	unsigned stype;
-	unsigned num;
-	unsigned stride;
-	radeon_state_pm4_t pm4;
-	struct radeon_sub_type reginfo[R600_SHADER_MAX];
-	unsigned base_id;
-	unsigned npm4;
+	unsigned			stype;
+	unsigned			num;
+	unsigned			stride;
+	radeon_state_pm4_t		pm4;
+	struct radeon_sub_type		reginfo[R600_SHADER_MAX];
+	unsigned			base_id;
+	unsigned			npm4;
 };
 
 struct radeon {
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index ef09fdfb96..d4e622cf7f 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -80,15 +80,59 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 i
 	state->refcount = 1;
 	state->npm4 = found->npm4;
 	state->nstates = found->reginfo[shader_index].nstates;
-	state->states = calloc(1, state->nstates * 4);
-	state->pm4 = calloc(1, found->npm4 * 4);
-	if (state->states == NULL || state->pm4 == NULL) {
-		radeon_state_decref(state);
-		return NULL;
-	}
 	return state;
 }
 
+int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type)
+{
+	struct radeon_stype_info *found = NULL;
+	int i, j, shader_index = -1;
+
+	if (state == NULL)
+		return 0;
+	/* traverse the stype array */
+	for (i = 0; i < state->radeon->nstype; i++) {
+		/* if the type doesn't match, if the shader doesn't match */
+		if (stype != state->radeon->stype[i].stype)
+			continue;
+		if (shader_type) {
+			for (j = 0; j < 4; j++) {
+				if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) {
+					shader_index = j;
+					break;
+				}
+			}
+			if (shader_index == -1)
+				continue;
+		} else {
+			if (state->radeon->stype[i].reginfo[0].shader_type)
+				continue;
+			else
+				shader_index = 0;
+		}
+		if (id > state->radeon->stype[i].num)
+			continue;
+		
+		found = &state->radeon->stype[i];
+		break;
+	}
+
+	if (!found) {
+		fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
+		return -EINVAL;
+	}
+
+	if (found->reginfo[shader_index].nstates != state->nstates) {
+		fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n",
+			state->stype->stype, state->id, state->shader_index, stype, id, shader_index);
+	}
+
+	state->stype = found;
+	state->id = id;
+	state->shader_index = shader_index;
+	return radeon_state_pm4(state);
+}
+
 struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
 {
 	return radeon_state_shader(radeon, type, id, 0);
@@ -134,9 +178,6 @@ struct radeon_state *radeon_state_decref(struct radeon_state *state)
 	for (i = 0; i < state->nbo; i++) {
 		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
 	}
-	free(state->immd);
-	free(state->states);
-	free(state->pm4);
 	memset(state, 0, sizeof(*state));
 	free(state);
 	return NULL;
@@ -179,8 +220,9 @@ int radeon_state_pm4(struct radeon_state *state)
 {
 	int r;
 
-	if (state == NULL || state->cpm4)
+	if (state == NULL)
 		return 0;
+	state->cpm4 = 0;
 	r = state->stype->pm4(state);
 	if (r) {
 		fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
-- 
cgit v1.2.3


From 66e4cb1cd5a55402606a09417349d2be8b009e89 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Mon, 30 Aug 2010 17:56:59 -0400
Subject: r600g: avoid dynamic allocation of states

Make state statically allocated, this kills a bunch of code
and avoid intensive use of malloc/free. There is still a lot
of useless duplicate function wrapping that can be kill. This
doesn't improve yet performance, needs to avoid memcpy states
in radeon_ctx_set_draw and to avoid rebuilding vs_resources,
dsa, scissor, cb_cntl, ... states at each draw command.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c       | 415 +++++++----------------------
 src/gallium/drivers/r600/r600_context.c    | 142 +++++-----
 src/gallium/drivers/r600/r600_context.h    |  31 +--
 src/gallium/drivers/r600/r600_draw.c       |  92 ++++---
 src/gallium/drivers/r600/r600_query.c      |  48 ++--
 src/gallium/drivers/r600/r600_resource.h   |   8 +-
 src/gallium/drivers/r600/r600_shader.c     |  32 +--
 src/gallium/drivers/r600/r600_state.c      | 386 ++++++---------------------
 src/gallium/drivers/r600/r600_texture.c    | 100 ++-----
 src/gallium/drivers/r600/radeon.h          |  72 ++---
 src/gallium/targets/dri-r600/Makefile      |   4 +-
 src/gallium/winsys/r600/drm/r600_state.c   |   4 +-
 src/gallium/winsys/r600/drm/radeon.c       |  26 +-
 src/gallium/winsys/r600/drm/radeon_ctx.c   | 219 ++++++---------
 src/gallium/winsys/r600/drm/radeon_draw.c  | 113 +-------
 src/gallium/winsys/r600/drm/radeon_priv.h  |  13 +-
 src/gallium/winsys/r600/drm/radeon_state.c |  55 +---
 17 files changed, 523 insertions(+), 1237 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index a8263ccbce..e6ded342e5 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -146,21 +146,20 @@ void r600_init_blit_functions(struct r600_context *rctx)
 
 
 struct r600_blit_states {
-	struct radeon_state	*rasterizer;
-	struct radeon_state	*dsa;
-	struct radeon_state	*blend;
-	struct radeon_state	*cb_cntl;
-	struct radeon_state	*config;
-	struct radeon_state	*vgt;
-	struct radeon_state	*draw;
-	struct radeon_state	*vs_constant0;
-	struct radeon_state	*vs_constant1;
-	struct radeon_state	*vs_constant2;
-	struct radeon_state	*vs_constant3;
-	struct radeon_state	*ps_shader;
-	struct radeon_state	*vs_shader;
-	struct radeon_state	*vs_resource0;
-	struct radeon_state	*vs_resource1;
+	struct radeon_state	rasterizer;
+	struct radeon_state	dsa;
+	struct radeon_state	blend;
+	struct radeon_state	cb_cntl;
+	struct radeon_state	vgt;
+	struct radeon_state	draw;
+	struct radeon_state	vs_constant0;
+	struct radeon_state	vs_constant1;
+	struct radeon_state	vs_constant2;
+	struct radeon_state	vs_constant3;
+	struct radeon_state	ps_shader;
+	struct radeon_state	vs_shader;
+	struct radeon_state	vs_resource0;
+	struct radeon_state	vs_resource1;
 };
 
 static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates)
@@ -190,11 +189,8 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	memcpy(bo->data, vbo, 128);
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
-	if (rstate == NULL) {
-		radeon_bo_decref(rscreen->rw, bo);
-		return -ENOMEM;
-	}
+	rstate = &bstates->vs_resource0;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -210,15 +206,12 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
+		radeon_state_fini(rstate);
 		return -ENOMEM;
 	}
-	bstates->vs_resource0 = rstate;
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
-	if (rstate == NULL) {
-		return -ENOMEM;
-	}
+	rstate = &bstates->vs_resource1;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
 	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
 	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
 	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
@@ -230,17 +223,15 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
+		radeon_state_fini(rstate);
 		return -ENOMEM;
 	}
-	bstates->vs_resource1 = rstate;
 
 	return 0;
 }
 
-static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscreen)
+static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
 	struct radeon_bo *bo;
 	u32 shader_bc_r600[] = {
 		0x00000004, 0x81000400,
@@ -282,11 +273,11 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	/* simple shader */
 	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
 	if (bo == NULL) {
-		return NULL;
+		return;
 	}
 	if (radeon_bo_map(rscreen->rw, bo)) {
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	switch (rscreen->chip_class) {
 	case R600:
@@ -299,15 +290,11 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 		R600_ERR("unsupported chip family\n");
 		radeon_bo_unmap(rscreen->rw, bo);
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
-	if (rstate == NULL) {
-		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
-	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -322,16 +309,11 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscreen)
+static void r600_blit_state_ps_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
 	struct radeon_bo *bo;
 	u32 shader_bc_r600[] = {
 		0x00000002, 0xA00C0000,
@@ -354,10 +336,10 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
 	if (bo == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	if (radeon_bo_map(rscreen->rw, bo)) {
-		return NULL;
+		return;
 	}
 	switch (rscreen->chip_class) {
 	case R600:
@@ -370,15 +352,11 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 		R600_ERR("unsupported chip family\n");
 		radeon_bo_unmap(rscreen->rw, bo);
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-	if (rstate == NULL) {
-		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
-	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -392,19 +370,12 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
+static void r600_blit_state_vgt(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_VGT, 0); if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_VGT, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -413,20 +384,12 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
 	rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
 	rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
+static void r600_blit_state_draw(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_DRAW, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DRAW, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -434,22 +397,13 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
 	rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002;
 	rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscreen,
-					unsigned id, float c0, float c1,
-					float c2, float c3)
+static void r600_blit_state_vs_constant(struct r600_screen *rscreen, struct radeon_state *rstate,
+					unsigned id, float c0, float c1, float c2, float c3)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -459,20 +413,12 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
 	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2);
 	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3);
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscreen)
+static void r600_blit_state_rasterizer(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_RASTERIZER, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -488,20 +434,12 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
+static void r600_blit_state_dsa(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_DSA, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -512,43 +450,18 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
 	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
+static void r600_blit_state_blend(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
-	if (rstate == NULL)
-		return NULL;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
+static void r600_blit_state_cb_cntl(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB_CNTL, 0);
-	if (rstate == NULL)
-		return NULL;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
@@ -556,113 +469,42 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
 	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	int r;
 
-	bstates->ps_shader = r600_blit_state_ps_shader(rscreen);
-	if (bstates->ps_shader == NULL) {
-		R600_ERR("failed creating ps_shader state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_shader = r600_blit_state_vs_shader(rscreen);
-	if (bstates->vs_shader == NULL) {
-		R600_ERR("failed creating vs_shader state\n");
-		return -ENOMEM;
-	}
-	bstates->vgt = r600_blit_state_vgt(rscreen);
-	if (bstates->vgt == NULL) {
-		R600_ERR("failed creating vgt state\n");
-		return -ENOMEM;
-	}
-	bstates->draw = r600_blit_state_draw(rscreen);
-	if (bstates->draw == NULL) {
-		R600_ERR("failed creating draw state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant0 = r600_blit_state_vs_constant(rscreen, 0, 1.0, 0.0, 0.0, 0.0);
-	if (bstates->vs_constant0 == NULL) {
-		R600_ERR("failed creating vs_constant0 state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant1 = r600_blit_state_vs_constant(rscreen, 1, 0.0, 1.0, 0.0, 0.0);
-	if (bstates->vs_constant1 == NULL) {
-		R600_ERR("failed creating vs_constant1 state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant2 = r600_blit_state_vs_constant(rscreen, 2, 0.0, 0.0, -0.00199900055, 0.0);
-	if (bstates->vs_constant2 == NULL) {
-		R600_ERR("failed creating vs_constant2 state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant3 = r600_blit_state_vs_constant(rscreen, 3, 0.0, 0.0, -0.99900049, 1.0);
-	if (bstates->vs_constant3 == NULL) {
-		R600_ERR("failed creating vs_constant3 state\n");
-		return -ENOMEM;
-	}
-	bstates->rasterizer = r600_blit_state_rasterizer(rscreen);
-	if (bstates->rasterizer == NULL) {
-		R600_ERR("failed creating rasterizer state\n");
-		return -ENOMEM;
-	}
-	bstates->dsa = r600_blit_state_dsa(rscreen);
-	if (bstates->dsa == NULL) {
-		R600_ERR("failed creating dsa state\n");
-		return -ENOMEM;
-	}
-	bstates->blend = r600_blit_state_blend(rscreen);
-	if (bstates->blend == NULL) {
-		R600_ERR("failed creating blend state\n");
-		return -ENOMEM;
-	}
-	bstates->cb_cntl = r600_blit_state_cb_cntl(rscreen);
-	if (bstates->cb_cntl == NULL) {
-		R600_ERR("failed creating cb_cntl state\n");
-		return -ENOMEM;
-	}
-	r = r600_blit_state_vs_resources(rscreen, bstates);
-	if (r) {
-		R600_ERR("failed creating vs_resource state\n");
-		return r;
-	}
-	bstates->config = radeon_state_incref(rctx->hw_states.config);
+	r600_blit_state_ps_shader(rscreen, &bstates->ps_shader);
+	r600_blit_state_vs_shader(rscreen, &bstates->vs_shader);
+	r600_blit_state_vgt(rscreen, &bstates->vgt);
+	r600_blit_state_draw(rscreen, &bstates->draw);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant0, 0, 1.0, 0.0, 0.0, 0.0);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant1, 1, 0.0, 1.0, 0.0, 0.0);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant2, 2, 0.0, 0.0, -0.00199900055, 0.0);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant3, 3, 0.0, 0.0, -0.99900049, 1.0);
+	r600_blit_state_rasterizer(rscreen, &bstates->rasterizer);
+	r600_blit_state_dsa(rscreen, &bstates->dsa);
+	r600_blit_state_blend(rscreen, &bstates->blend);
+	r600_blit_state_cb_cntl(rscreen, &bstates->cb_cntl);
+	r600_blit_state_vs_resources(rscreen, bstates);
 	return 0;
 }
 
 static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates)
 {
-	radeon_state_decref(bstates->rasterizer);
-	radeon_state_decref(bstates->dsa);
-	radeon_state_decref(bstates->blend);
-	radeon_state_decref(bstates->cb_cntl);
-	radeon_state_decref(bstates->config);
-	radeon_state_decref(bstates->vgt);
-	radeon_state_decref(bstates->draw);
-	radeon_state_decref(bstates->vs_constant0);
-	radeon_state_decref(bstates->vs_constant1);
-	radeon_state_decref(bstates->vs_constant2);
-	radeon_state_decref(bstates->vs_constant3);
-	radeon_state_decref(bstates->ps_shader);
-	radeon_state_decref(bstates->vs_shader);
-	radeon_state_decref(bstates->vs_resource0);
-	radeon_state_decref(bstates->vs_resource1);
+	radeon_state_fini(&bstates->ps_shader);
+	radeon_state_fini(&bstates->vs_shader);
+	radeon_state_fini(&bstates->vs_resource0);
+	radeon_state_fini(&bstates->vs_resource1);
 }
 
 int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_draw *draw = NULL;
+	struct radeon_draw draw;
 	struct r600_blit_states bstates;
 	int r;
 
@@ -687,108 +529,51 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		return r;
 	}
-	bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
-	bstates.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
+	bstates.dsa.states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
+	bstates.cb_cntl.states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
 	/* force rebuild */
-	bstates.dsa->cpm4 = bstates.cb_cntl->cpm4 = 0;
-	if (radeon_state_pm4(bstates.dsa)) {
+	bstates.dsa.cpm4 = bstates.cb_cntl.cpm4 = 0;
+	if (radeon_state_pm4(&bstates.dsa)) {
 		goto out;
 	}
-	if (radeon_state_pm4(bstates.cb_cntl)) {
+	if (radeon_state_pm4(&bstates.cb_cntl)) {
 		goto out;
 	}
 
-	draw = radeon_draw(rscreen->rw);
-	if (draw == NULL) {
+	r = radeon_draw_init(&draw, rscreen->rw);
+	if (r) {
 		R600_ERR("failed creating draw for uncompressing textures\n");
 		goto out;
 	}
 
-	r = radeon_draw_set(draw, bstates.vs_shader);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.ps_shader);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.rasterizer);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.dsa);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.blend);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.cb_cntl);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.config);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vgt);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.draw);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_resource0);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_resource1);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant0);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant1);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant2);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant3);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->viewport[level]);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->scissor[level]);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->cb[0][level]);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->db[level]);
-	if (r) {
-		goto out;
-	}
+	radeon_draw_bind(&draw, &bstates.vs_shader);
+	radeon_draw_bind(&draw, &bstates.ps_shader);
+	radeon_draw_bind(&draw, &bstates.rasterizer);
+	radeon_draw_bind(&draw, &bstates.dsa);
+	radeon_draw_bind(&draw, &bstates.blend);
+	radeon_draw_bind(&draw, &bstates.cb_cntl);
+	radeon_draw_bind(&draw, &rctx->config);
+	radeon_draw_bind(&draw, &bstates.vgt);
+	radeon_draw_bind(&draw, &bstates.draw);
+	radeon_draw_bind(&draw, &bstates.vs_resource0);
+	radeon_draw_bind(&draw, &bstates.vs_resource1);
+	radeon_draw_bind(&draw, &bstates.vs_constant0);
+	radeon_draw_bind(&draw, &bstates.vs_constant1);
+	radeon_draw_bind(&draw, &bstates.vs_constant2);
+	radeon_draw_bind(&draw, &bstates.vs_constant3);
+	radeon_draw_bind(&draw, &rtexture->viewport[level]);
+	radeon_draw_bind(&draw, &rtexture->scissor[level]);
+	radeon_draw_bind(&draw, &rtexture->cb[0][level]);
+	radeon_draw_bind(&draw, &rtexture->db[level]);
 
 	/* suspend queries */
 	r600_queries_suspend(ctx);
 
 	/* schedule draw*/
-	r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+	r = radeon_ctx_set_draw(&rctx->ctx, &draw);
 	if (r == -EBUSY) {
 		r600_flush(ctx, 0, NULL);
-		r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+		r = radeon_ctx_set_draw(&rctx->ctx, &draw);
 	}
 	if (r) {
 		goto out;
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index db170122dd..95e9b6a8ed 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -46,35 +46,31 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 			struct pipe_fence_handle **fence)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct r600_screen *rscreen = rctx->screen;
 	struct r600_query *rquery;
 	static int dc = 0;
 	char dname[256];
 
 	/* suspend queries */
 	r600_queries_suspend(ctx);
-	if (radeon_ctx_pm4(rctx->ctx))
-		goto out;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
-	if (!rctx->ctx->cpm4)
+	if (!rctx->ctx.cdwords)
 		goto out;
 	sprintf(dname, "gallium-%08d.bof", dc);
 	if (dc < 2) {
-		radeon_ctx_dump_bof(rctx->ctx, dname);
+		radeon_ctx_dump_bof(&rctx->ctx, dname);
 		R600_ERR("dumped %s\n", dname);
 	}
 #if 1
-	radeon_ctx_submit(rctx->ctx);
+	radeon_ctx_submit(&rctx->ctx);
 #endif
 	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
 		rquery->flushed = true;
 	}
 	dc++;
 out:
-	rctx->ctx = radeon_ctx_decref(rctx->ctx);
-	rctx->ctx = radeon_ctx(rscreen->rw);
+	radeon_ctx_clear(&rctx->ctx);
 	/* resume queries */
 	r600_queries_resume(ctx);
 }
@@ -218,9 +214,9 @@ static void r600_init_config(struct r600_context *rctx)
 		num_es_stack_entries = 0;
 		break;
 	}
-	rctx->hw_states.config = radeon_state(rctx->rw, R600_STATE_CONFIG, 0);
+	radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
 	case CHIP_RV610:
 	case CHIP_RV620:
@@ -229,75 +225,75 @@ static void r600_init_config(struct r600_context *rctx)
 	case CHIP_RV710:
 		break;
 	default:
-		rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 		break;
 	}
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->hw_states.config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-	rctx->hw_states.config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-	rctx->hw_states.config->states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-	rctx->hw_states.config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(rctx->hw_states.config);
+	rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+	rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+	rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+	rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+	rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+	rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
+	rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
+	radeon_state_pm4(&rctx->config);
 }
 
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
@@ -331,7 +327,7 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 
 	r600_init_config(rctx);
 
-	rctx->ctx = radeon_ctx(rscreen->rw);
-	rctx->draw = radeon_draw(rscreen->rw);
+	radeon_ctx_init(&rctx->ctx, rscreen->rw);
+	radeon_draw_init(&rctx->draw, rscreen->rw);
 	return &rctx->context;
 }
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index e9495f0017..a48dca4915 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -53,7 +53,7 @@ struct r600_query {
 	unsigned				buffer_size;
 	/* linked list of queries */
 	struct list_head			list;
-	struct radeon_state			*rstate;
+	struct radeon_state			rstate;
 };
 
 /* XXX move this to a more appropriate place */
@@ -99,7 +99,7 @@ struct r600_context_state {
 	union pipe_states		state;
 	unsigned			refcount;
 	unsigned			type;
-	struct radeon_state		*rstate;
+	struct radeon_state		rstate;
 	struct r600_shader		shader;
 	struct radeon_bo		*bo;
 };
@@ -112,29 +112,24 @@ struct r600_vertex_element
 };
 
 struct r600_context_hw_states {
-	struct radeon_state	*rasterizer;
-	struct radeon_state	*scissor;
-	struct radeon_state	*dsa;
-	struct radeon_state	*blend;
-	struct radeon_state	*viewport;
-	struct radeon_state	*cb[8];
-	struct radeon_state	*config;
-	struct radeon_state	*cb_cntl;
-	struct radeon_state	*db;
-	struct radeon_state	*ucp;
-	unsigned		ps_nresource;
-	unsigned		ps_nsampler;
-	struct radeon_state	*ps_resource[160];
-	struct radeon_state	*ps_sampler[16];
+	struct radeon_state	rasterizer;
+	struct radeon_state	scissor;
+	struct radeon_state	dsa;
+	struct radeon_state	cb_cntl;
 };
 
 struct r600_context {
 	struct pipe_context		context;
 	struct r600_screen		*screen;
 	struct radeon			*rw;
-	struct radeon_ctx		*ctx;
+	struct radeon_ctx		ctx;
 	struct blitter_context		*blitter;
-	struct radeon_draw		*draw;
+	struct radeon_draw		draw;
+	struct radeon_state		config;
+	/* FIXME get rid of those vs_resource,vs/ps_constant */
+	struct radeon_state		vs_resource[160];
+	struct radeon_state		vs_constant[256];
+	struct radeon_state		ps_constant[256];
 	/* hw states */
 	struct r600_context_hw_states	hw_states;
 	/* pipe states */
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 88f93bca7b..bddc81e50a 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -31,6 +31,7 @@
 #include <util/u_math.h>
 #include <util/u_inlines.h>
 #include <util/u_memory.h>
+#include "radeon.h"
 #include "r600_screen.h"
 #include "r600_context.h"
 #include "r600_resource.h"
@@ -38,8 +39,8 @@
 
 struct r600_draw {
 	struct pipe_context	*ctx;
-	struct radeon_state	*draw;
-	struct radeon_state	*vgt;
+	struct radeon_state	draw;
+	struct radeon_state	vgt;
 	unsigned		mode;
 	unsigned		start;
 	unsigned		count;
@@ -51,6 +52,7 @@ static int r600_draw_common(struct r600_draw *draw)
 {
 	struct r600_context *rctx = r600_context(draw->ctx);
 	struct r600_screen *rscreen = rctx->screen;
+	/* FIXME vs_resource */
 	struct radeon_state *vs_resource;
 	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
@@ -81,6 +83,7 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_conv_pipe_prim(draw->mode, &prim);
 	if (r)
 		return r;
+
 	/* rebuild vertex shader if input format changed */
 	r = r600_pipe_shader_update(draw->ctx, rctx->vs_shader);
 	if (r)
@@ -88,22 +91,17 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
-	if (r)
-		return r;
+	radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate);
+	radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate);
 
 	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
+		vs_resource = &rctx->vs_resource[i];
 		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
 		vertex_buffer = &rctx->vertex_buffer[j];
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		vs_resource = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, i, R600_SHADER_VS);
-		if (vs_resource == NULL)
-			return -ENOMEM;
+		radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, i, R600_SHADER_VS);
 		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		vs_resource->nbo = 1;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
@@ -116,53 +114,53 @@ static int r600_draw_common(struct r600_draw *draw)
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
 		vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
 		vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
-		r = radeon_draw_set_new(rctx->draw, vs_resource);
-		if (r)
+		r = radeon_state_pm4(vs_resource);
+		if (r) {
 			return r;
+		}
+		radeon_draw_bind(&rctx->draw, vs_resource);
 	}
 	/* FIXME start need to change winsys */
-	draw->draw = radeon_state(rscreen->rw, R600_STATE_DRAW, 0);
-	if (draw->draw == NULL)
-		return -ENOMEM;
-	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
+	radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
+	draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+	draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	if (draw->index_buffer) {
 		rbuffer = (struct r600_resource*)draw->index_buffer;
-		draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw->nbo = 1;
+		draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw.nbo = 1;
 	}
-	r = radeon_draw_set_new(rctx->draw, draw->draw);
-	if (r)
+	r = radeon_state_pm4(&draw->draw);
+	if (r) {
 		return r;
-	draw->vgt = radeon_state(rscreen->rw, R600_STATE_VGT, 0);
-	if (draw->vgt == NULL)
-		return -ENOMEM;
-	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
-	draw->vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
-	draw->vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
-	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
-	r = radeon_draw_set_new(rctx->draw, draw->vgt);
-	if (r)
+	}
+	radeon_draw_bind(&rctx->draw, &draw->draw);
+
+	radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
+	draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
+	draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+	draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
+	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+	draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
+	r = radeon_state_pm4(&draw->vgt);
+	if (r) {
 		return r;
-	/* FIXME */
-	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+	}
+	radeon_draw_bind(&rctx->draw, &draw->vgt);
+
+	r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 	if (r == -EBUSY) {
 		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+		r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 	}
-	if (r)
-		return r;
-	rctx->draw = radeon_draw_duplicate(rctx->draw);
-	return 0;
+	return r;
 }
 
 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index af857101e3..530940ed84 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -31,42 +31,36 @@
 #include "r600_screen.h"
 #include "r600_context.h"
 
-static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
+static void r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rquery->rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_QUERY_BEGIN, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_fini(rstate);
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_BEGIN, 0, 0);
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
+		radeon_state_fini(rstate);
 	}
-	return rstate;
 }
 
-static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
+static void r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rquery->rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_QUERY_END, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_fini(rstate);
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_END, 0, 0);
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
+		radeon_state_fini(rstate);
 	}
-	return rstate;
 }
 
 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
@@ -137,8 +131,7 @@ static void r600_query_resume(struct pipe_context *ctx, struct r600_query *rquer
 		}
 		r600_query_result(ctx, rquery);
 	}
-	rquery->rstate = radeon_state_decref(rquery->rstate);
-	rquery->rstate = r600_query_begin(rctx, rquery);
+	r600_query_begin(rctx, rquery);
 	rquery->flushed = false;
 }
 
@@ -146,8 +139,7 @@ static void r600_query_suspend(struct pipe_context *ctx, struct r600_query *rque
 {
 	struct r600_context *rctx = r600_context(ctx);
 
-	rquery->rstate = radeon_state_decref(rquery->rstate);
-	rquery->rstate = r600_query_end(rctx, rquery);
+	r600_query_end(rctx, rquery);
 	rquery->num_results += 16;
 }
 
@@ -161,12 +153,12 @@ static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
 	rquery->num_results = 0;
 	rquery->flushed = false;
 	r600_query_resume(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	if (r == -EBUSY) {
 		/* this shouldn't happen */
 		R600_ERR("had to flush while emitting end query\n");
 		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+		r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	}
 }
 
@@ -179,12 +171,12 @@ static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
 	rquery->state &= ~R600_QUERY_STATE_STARTED;
 	rquery->state |= R600_QUERY_STATE_ENDED;
 	r600_query_suspend(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	if (r == -EBUSY) {
 		/* this shouldn't happen */
 		R600_ERR("had to flush while emitting end query\n");
 		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+		r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	}
 }
 
@@ -197,12 +189,12 @@ void r600_queries_suspend(struct pipe_context *ctx)
 	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
 		if (rquery->state & R600_QUERY_STATE_STARTED) {
 			r600_query_suspend(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			if (r == -EBUSY) {
 				/* this shouldn't happen */
 				R600_ERR("had to flush while emitting end query\n");
 				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+				r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			}
 		}
 		rquery->state |= R600_QUERY_STATE_SUSPENDED;
@@ -218,12 +210,12 @@ void r600_queries_resume(struct pipe_context *ctx)
 	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
 		if (rquery->state & R600_QUERY_STATE_STARTED) {
 			r600_query_resume(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			if (r == -EBUSY) {
 				/* this shouldn't happen */
 				R600_ERR("had to flush while emitting end query\n");
 				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+				r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			}
 		}
 		rquery->state &= ~R600_QUERY_STATE_SUSPENDED;
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 8078a83c35..129667ad20 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -56,10 +56,10 @@ struct r600_resource_texture {
 	unsigned			depth;
 	unsigned			dirty;
 	struct radeon_bo		*uncompressed;
-	struct radeon_state		*scissor[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*cb[8][PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*db[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*viewport[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		scissor[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		cb[8][PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		db[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		viewport[PIPE_MAX_TEXTURE_LEVELS];
 };
 
 void r600_init_context_resource_functions(struct r600_context *r600);
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index a26290062a..9af45b7793 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -134,10 +134,9 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	struct radeon_state *state;
 	unsigned i, tmp;
 
-	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
-	if (state == NULL)
-		return -ENOMEM;
+	state = &rpshader->rstate;
+	radeon_state_fini(&rpshader->rstate);
+	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 	for (i = 0; i < 10; i++) {
 		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
 	}
@@ -149,12 +148,11 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
 	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
 		S_028868_STACK_SIZE(rshader->bc.nstack);
-	rpshader->rstate = state;
-	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->nbo = 2;
-	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->nbo = 2;
+	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	state->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
@@ -168,11 +166,10 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	unsigned i, tmp, exports_ps, num_cout;
 	boolean have_pos = FALSE;
 
+	state = &rpshader->rstate;
 	rasterizer = &rctx->rasterizer->state.rasterizer;
-	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-	if (state == NULL)
-		return -ENOMEM;
+	radeon_state_fini(state);
+	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
 	for (i = 0; i < rshader->ninput; i++) {
 		tmp = S_028644_SEMANTIC(i);
 		tmp |= S_028644_SEL_CENTROID(1);
@@ -214,10 +211,9 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
 		S_028868_STACK_SIZE(rshader->bc.nstack);
 	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
-	rpshader->rstate = state;
-	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->nbo = 1;
-	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->nbo = 1;
+	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index d8f53f2ce8..c6810ffe36 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -34,15 +34,12 @@
 #include "r600d.h"
 #include "r600_state_inlines.h"
 
-static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state);
-static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state);
-static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state);
-static struct radeon_state *r600_sampler(struct r600_context *rctx,
-				const struct pipe_sampler_state *state,
-				unsigned id);
-static struct radeon_state *r600_resource(struct pipe_context *ctx,
-					const struct pipe_sampler_view *view,
-					unsigned id);
+static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
+static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
+static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
+static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
+static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
+
 
 static void *r600_create_blend_state(struct pipe_context *ctx,
 					const struct pipe_blend_state *state)
@@ -96,7 +93,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
 	rstate->state.sampler_view.context = ctx;
-	rstate->rstate = r600_resource(ctx, &rstate->state.sampler_view, 0);
+	r600_resource(ctx, &rstate->rstate, &rstate->state.sampler_view, 0);
 	return &rstate->state.sampler_view;
 }
 
@@ -241,7 +238,7 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)states[i];
 		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
 		}
 	}
 	rctx->ps_nsampler = count;
@@ -261,7 +258,7 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)states[i];
 		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
 		}
 	}
 	rctx->vs_nsampler = count;
@@ -301,7 +298,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
 	unsigned nconstant = 0, i, type, shader_class;
-	struct radeon_state *rstate;
+	struct radeon_state *rstate, *rstates;
 	struct pipe_transfer *transfer;
 	u32 *ptr;
 
@@ -310,9 +307,11 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
 		shader_class = R600_SHADER_VS;
+		rstates = rctx->vs_constant;
 		break;
 	case PIPE_SHADER_FRAGMENT:
 		shader_class = R600_SHADER_PS;
+		rstates = rctx->ps_constant;
 		break;
 	default:
 		R600_ERR("unsupported %d\n", shader);
@@ -324,17 +323,15 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		if (ptr == NULL)
 			return;
 		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state_shader(rscreen->rw, type, i, shader_class);
-			if (rstate == NULL)
-				return;
+			rstate = &rstates[i];
+			radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
 			if (radeon_state_pm4(rstate))
 				return;
-			if (radeon_draw_set_new(rctx->draw, rstate))
-				return;
+			radeon_draw_bind(&rctx->draw, rstate);
 		}
 		pipe_buffer_unmap(ctx, buffer, transfer);
 	}
@@ -355,7 +352,7 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)views[i];
 		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
 		}
 	}
 	rctx->ps_nsampler_view = count;
@@ -376,7 +373,7 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)views[i];
 		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
 		}
 	}
 	rctx->vs_nsampler_view = count;
@@ -564,7 +561,7 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state *
 		R600_ERR("invalid type %d\n", rstate->type);
 		return NULL;
 	}
-	radeon_state_decref(rstate->rstate);
+	radeon_state_fini(&rstate->rstate);
 	FREE(rstate);
 	return NULL;
 }
@@ -597,7 +594,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_viewport_type:
 		rstate->state.viewport = (*states).viewport;
-		rstate->rstate = r600_viewport(rctx, &rstate->state.viewport);
+		r600_viewport(rctx, &rstate->rstate, &rstate->state.viewport);
 		break;
 	case pipe_depth_type:
 		rstate->state.depth = (*states).depth;
@@ -613,7 +610,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_clip_type:
 		rstate->state.clip = (*states).clip;
-		rstate->rstate = r600_ucp(rctx, &rstate->state.clip);
+		r600_ucp(rctx, &rstate->rstate, &rstate->state.clip);
 		break;
 	case pipe_stencil_type:
 		rstate->state.stencil = (*states).stencil;
@@ -626,7 +623,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_blend_type:
 		rstate->state.blend = (*states).blend;
-		rstate->rstate = r600_blend(rctx, &rstate->state.blend);
+		r600_blend(rctx, &rstate->rstate, &rstate->state.blend);
 		break;
 	case pipe_stencil_ref_type:
 		rstate->state.stencil_ref = (*states).stencil_ref;
@@ -641,7 +638,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_sampler_type:
 		rstate->state.sampler = (*states).sampler;
-		rstate->rstate = r600_sampler(rctx, &rstate->state.sampler, 0);
+		r600_sampler(rctx, &rstate->rstate, &rstate->state.sampler, 0);
 		break;
 	default:
 		R600_ERR("invalid type %d\n", rstate->type);
@@ -651,15 +648,12 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 	return rstate;
 }
 
-static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state)
+static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	int i;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
 	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
 	rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
 	rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
@@ -703,21 +697,15 @@ static struct radeon_state *r600_blend(struct r600_context *rctx, const struct p
 			rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
 	}
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state)
+static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_clip_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_UCP, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
 
 	for (int i = 0; i < state->nr; i++) {
 		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
@@ -725,118 +713,15 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pip
 		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
 		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
 	}
-	return rstate;
-}
-
-static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
-	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level = state->cbufs[cb]->level;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
-	if (rstate == NULL)
-		return NULL;
-	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
-	rbuffer = &rtex->resource;
-	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 3;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
-
-	ntype = 0;
-	desc = util_format_description(rtex->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_0280A0_NUMBER_SRGB;
-
-	format = r600_translate_colorformat(rtex->resource.base.b.format);
-	swap = r600_translate_colorswap(rtex->resource.base.b.format);
-
-	color_info = S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_SOURCE_FORMAT(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
-
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
-						S_028060_SLICE_TILE_MAX(slice);
-	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
-}
-
-static struct radeon_state *r600_db(struct r600_context *rctx)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
-	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level;
-	unsigned pitch, slice, format;
-
-	if (state->zsbuf == NULL)
-		return NULL;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
-	if (rstate == NULL)
-		return NULL;
-
-	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
-	rtex->tilled = 1;
-	rtex->array_mode = 2;
-	rtex->tile_type = 1;
-	rtex->depth = 1;
-	rbuffer = &rtex->resource;
-
-	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	level = state->zsbuf->level;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
-	format = r600_translate_dbformat(state->zsbuf->texture->format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
-					S_028010_FORMAT(format);
-	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
-	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
+static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
 	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	const struct pipe_clip_state *clip = NULL;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	float offset_units = 0, offset_scale = 0;
 	char depth = 0;
 	unsigned offset_db_fmt_cntl = 0;
@@ -865,7 +750,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 			break;
 		default:
 			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
-			return NULL;
+			return;
 		}
 	}
 	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
@@ -874,9 +759,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		prov_vtx = 0;
 
 	rctx->flat_shade = state->flatshade;
-	rstate = radeon_state(rscreen->rw, R600_STATE_RASTERIZER, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 	if (state->sprite_coord_enable) {
 		rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
@@ -926,19 +809,14 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_scissor(struct r600_context *rctx)
+static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
 	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	unsigned minx, maxx, miny, maxy;
 	u32 tl, br;
 
@@ -955,9 +833,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	}
 	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
-	rstate = radeon_state(rscreen->rw, R600_STATE_SCISSOR, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
@@ -977,21 +853,14 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state)
+static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_VIEWPORT, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
@@ -1001,14 +870,10 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx, const struc
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_dsa(struct r600_context *rctx)
+static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
@@ -1016,15 +881,12 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 	unsigned stencil_ref_mask, stencil_ref_mask_bf;
 	struct r600_shader *rshader;
-	struct radeon_state *rstate;
 	int i;
 
 	if (rctx->ps_shader == NULL) {
-		return NULL;
+		return;
 	}
-	rstate = radeon_state(rscreen->rw, R600_STATE_DSA, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
 	db_shader_control = 0x210;
 	rshader = &rctx->ps_shader->shader;
@@ -1087,11 +949,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
 	rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
 	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 static inline unsigned r600_tex_wrap(unsigned wrap)
@@ -1169,16 +1027,12 @@ static INLINE u32 S_FIXED(float value, u32 frac_bits)
 	return value * (1 << frac_bits);
 }
 
-static struct radeon_state *r600_sampler(struct r600_context *rctx,
-				const struct pipe_sampler_state *state,
-				unsigned id)
+static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_sampler_state *state, unsigned id)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
 			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
@@ -1193,11 +1047,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
 			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 static inline unsigned r600_tex_swizzle(unsigned swizzle)
@@ -1248,21 +1098,20 @@ static inline unsigned r600_tex_dim(unsigned dim)
 	}
 }
 
-static struct radeon_state *r600_resource(struct pipe_context *ctx,
-					const struct pipe_sampler_view *view,
-					unsigned id)
+static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
+			const struct pipe_sampler_view *view, unsigned id)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_screen *rscreen = rctx->screen;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
 	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
 	unsigned format;
 	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
 	int r;
 
+	rstate->cpm4 = 0;
 	swizzle[0] = view->swizzle_r;
 	swizzle[1] = view->swizzle_g;
 	swizzle[2] = view->swizzle_b;
@@ -1270,23 +1119,21 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 	format = r600_translate_texformat(view->texture->format,
 					  swizzle,
 					  &word4, &yuv_format);
-	if (format == ~0)
-		return NULL;
+	if (format == ~0) {
+		return;
+	}
 	desc = util_format_description(view->texture->format);
 	if (desc == NULL) {
 		R600_ERR("unknow format %d\n", view->texture->format);
-		return NULL;
-	}
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
-	if (rstate == NULL) {
-		return NULL;
+		return;
 	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
 	tmp = (struct r600_resource_texture*)view->texture;
 	rbuffer = &tmp->resource;
 	if (tmp->depth) {
 		r = r600_texture_from_depth(ctx, tmp, view->first_level);
 		if (r) {
-			return NULL;
+			return;
 		}
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
 		rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
@@ -1302,7 +1149,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 
 	pitch = (tmp->pitch[0] / tmp->bpt);
 	pitch = (pitch + 0x7) & ~0x7;
-	
+
 	/* FIXME properly handle first level != 0 */
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
@@ -1328,17 +1175,12 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 			S_038014_LAST_ARRAY(0);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
 			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
+static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
 	uint32_t color_control, target_mask, shader_mask;
@@ -1373,7 +1215,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB_CNTL, 0);
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1385,11 +1227,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
 	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 int r600_context_hw_states(struct pipe_context *ctx)
@@ -1397,110 +1235,46 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_resource_texture *rtexture;
 	unsigned i;
-	int r;
-	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
-	int ucp_nclip = 0;
 
-	if (rctx->clip) 
-		ucp_nclip = rctx->clip->state.clip.nr;
+	/* build new states */
+	r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
+	r600_scissor(rctx, &rctx->hw_states.scissor);
+	r600_dsa(rctx, &rctx->hw_states.dsa);
+	r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
 
-	/* free previous TODO determine what need to be updated, what
-	 * doesn't
-	 */
-	rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
-	rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
-	rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
-	rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
+	/* bind states */
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
+
+	radeon_draw_bind(&rctx->draw, &rctx->config);
 
-	/* build new states */
-	rctx->hw_states.blend = NULL;
-	rctx->hw_states.viewport = NULL;
-	rctx->hw_states.ucp = NULL;
-	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
-	rctx->hw_states.scissor = r600_scissor(rctx);
-	rctx->hw_states.dsa = r600_dsa(rctx);
-	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
 	if (rctx->viewport) {
-		rctx->hw_states.viewport = rctx->viewport->rstate;
+		radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate);
 	}
 	if (rctx->blend) {
-		rctx->hw_states.blend = rctx->blend->rstate;
+		radeon_draw_bind(&rctx->draw, &rctx->blend->rstate);
 	}
 	if (rctx->clip) {
-		rctx->hw_states.ucp = rctx->clip->rstate;
+		radeon_draw_bind(&rctx->draw, &rctx->clip->rstate);
 	}
 	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
 		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.cbufs[i]->texture;
-		rctx->hw_states.cb[i] = rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level];
+		radeon_draw_bind(&rctx->draw, &rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level]);
 	}
 	if (rctx->framebuffer->state.framebuffer.zsbuf) {
 		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.zsbuf->texture;
-		rctx->hw_states.db = rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level];
+		radeon_draw_bind(&rctx->draw, &rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level]);
 	}
-
-
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			rctx->hw_states.ps_sampler[i] = rctx->ps_sampler[i]->rstate;
-		} else {
-			rctx->hw_states.ps_sampler[i] = NULL;
+			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate);
 		}
 	}
-	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			rctx->hw_states.ps_resource[i] = rctx->ps_sampler_view[i]->rstate;
-		} else {
-			rctx->hw_states.ps_resource[i] = NULL;
-		}
-	}
-	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
-
-	/* bind states */
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
-	if (r)
-		return r;
-	for (i = 0; i < nr_cbufs; i++) {
-		r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
-		if (r)
-			return r;
-	}
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
-	if (r)
-		return r;
-	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
-		if (rctx->hw_states.ps_resource[i]) {
-			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
-			if (r)
-				return r;
-		}
-	}
-	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
-		if (rctx->hw_states.ps_sampler[i]) {
-			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
-			if (r)
-				return r;
+			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate);
 		}
 	}
 	return 0;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index ec1d50566a..c472d4f37b 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -133,10 +133,10 @@ static void r600_texture_destroy_state(struct pipe_resource *ptexture)
 	struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
 
 	for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
-		radeon_state_decref(rtexture->scissor[i]);
-		radeon_state_decref(rtexture->db[i]);
+		radeon_state_fini(&rtexture->scissor[i]);
+		radeon_state_fini(&rtexture->db[i]);
 		for (int j = 0; j < 8; j++) {
-			radeon_state_decref(rtexture->cb[j][i]);
+			radeon_state_fini(&rtexture->cb[j][i]);
 		}
 	}
 }
@@ -668,16 +668,13 @@ int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_textu
 	return 0;
 }
 
-static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscreen,
+static void r600_texture_state_scissor(struct r600_screen *rscreen,
 					struct r600_resource_texture *rtexture,
 					unsigned level)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_SCISSOR, 0);
-	if (rstate == NULL)
-		return NULL;
+	struct radeon_state *rstate = &rtexture->scissor[level];
 
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
 	 */
@@ -700,16 +697,10 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
-				struct r600_resource_texture *rtexture,
-				unsigned cb, unsigned level)
+static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 {
 	struct radeon_state *rstate;
 	struct r600_resource *rbuffer;
@@ -718,9 +709,8 @@ static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
-	if (rstate == NULL)
-		return NULL;
+	rstate = &rtexture->cb[cb][level];
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
 	rbuffer = &rtexture->resource;
 
 	/* set states (most default value are 0 and struct already
@@ -762,24 +752,16 @@ static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
-				struct r600_resource_texture *rtexture,
-				unsigned level)
+static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
 {
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rtexture->db[level];
 	struct r600_resource *rbuffer;
 	unsigned pitch, slice, format;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
 	rbuffer = &rtexture->resource;
 	rtexture->tilled = 1;
 	rtexture->array_mode = 2;
@@ -803,36 +785,24 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 1;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->scissor[level] == NULL) {
-		rtexture->scissor[level] = r600_texture_state_scissor(rscreen, rtexture, level);
-		if (rtexture->scissor[level] == NULL) {
-			R600_ERR("failed to create scissor for uncompressing depth\n");
-			return -ENOMEM;
-		}
+	if (!rtexture->scissor[level].cpm4) {
+		r600_texture_state_scissor(rscreen, rtexture, level);
 	}
 	return 0;
 }
 
-static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscreen,
-					struct r600_resource_texture *rtexture,
-					unsigned level)
+static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
 {
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rtexture->viewport[level];
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_VIEWPORT, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -846,23 +816,15 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->cb[cb][level] == NULL) {
-		rtexture->cb[cb][level] = r600_texture_state_cb(rscreen, rtexture, cb, level);
-		if (rtexture->cb[cb][level] == NULL) {
-			R600_ERR("failed to create cb%d state for texture\n", cb);
-			return -ENOMEM;
-		}
+	if (!rtexture->cb[cb][level].cpm4) {
+		r600_texture_state_cb(rscreen, rtexture, cb, level);
 	}
 	return 0;
 }
@@ -871,12 +833,8 @@ int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtex
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->db[level] == NULL) {
-		rtexture->db[level] = r600_texture_state_db(rscreen, rtexture, level);
-		if (rtexture->db[level] == NULL) {
-			R600_ERR("failed to create db state for texture\n");
-			return -ENOMEM;
-		}
+	if (!rtexture->db[level].cpm4) {
+		r600_texture_state_db(rscreen, rtexture, level);
 	}
 	return 0;
 }
@@ -885,12 +843,8 @@ int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->viewport[level] == NULL) {
-		rtexture->viewport[level] = r600_texture_state_viewport(rscreen, rtexture, level);
-		if (rtexture->viewport[level] == NULL) {
-			R600_ERR("failed to create viewport state for texture\n");
-			return -ENOMEM;
-		}
+	if (!rtexture->viewport[level].cpm4) {
+		r600_texture_state_viewport(rscreen, rtexture, level);
 	}
 	return 0;
 }
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 3f1ca95f69..aaac8de528 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -77,6 +77,14 @@ enum radeon_family {
 	CHIP_LAST,
 };
 
+enum {
+	R600_SHADER_PS = 1,
+	R600_SHADER_VS,
+	R600_SHADER_GS,
+	R600_SHADER_FS,
+	R600_SHADER_MAX = R600_SHADER_FS,
+};
+
 enum radeon_family radeon_get_family(struct radeon *rw);
 
 /*
@@ -105,9 +113,10 @@ struct radeon_stype_info;
 struct radeon_state {
 	struct radeon			*radeon;
 	unsigned			refcount;
-	struct radeon_stype_info        *stype;
+	struct radeon_stype_info	*stype;
+	unsigned			state_id;
 	unsigned			id;
-	unsigned                        shader_index;
+	unsigned			shader_index;
 	unsigned			nstates;
 	u32				states[64];
 	unsigned			npm4;
@@ -123,10 +132,8 @@ struct radeon_state {
 	unsigned			bo_dirty[4];
 };
 
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
-struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 type, u32 id, u32 shader_class);
-struct radeon_state *radeon_state_incref(struct radeon_state *state);
-struct radeon_state *radeon_state_decref(struct radeon_state *state);
+int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class);
+void radeon_state_fini(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
 int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
 
@@ -134,30 +141,13 @@ int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shad
  * draw functions
  */
 struct radeon_draw {
-	unsigned			refcount;
 	struct radeon			*radeon;
-	unsigned			nstate;
 	struct radeon_state		**state;
-	unsigned			cpm4;
 };
 
-struct radeon_draw *radeon_draw(struct radeon *radeon);
-struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw);
-struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw);
-struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw);
-int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
-int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
-int radeon_draw_check(struct radeon_draw *draw);
-
-struct radeon_ctx *radeon_ctx(struct radeon *radeon);
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_pm4(struct radeon_ctx *ctx);
-int radeon_ctx_submit(struct radeon_ctx *ctx);
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
+int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
+void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state);
+void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state);
 
 /*
  * radeon context functions
@@ -172,30 +162,30 @@ struct radeon_cs_reloc {
 #pragma pack()
 
 struct radeon_ctx {
-	int				refcount;
 	struct radeon			*radeon;
 	u32				*pm4;
-	u32				cpm4;
-	u32				draw_cpm4;
-	unsigned			id;
-	unsigned			next_id;
+	int				cdwords;
+	int				ndwords;
 	unsigned			nreloc;
 	struct radeon_cs_reloc		*reloc;
 	unsigned			nbo;
 	struct radeon_bo		**bo;
-	unsigned			ndraw;
-	struct radeon_draw		*cdraw;
-	struct radeon_draw		**draw;
-	unsigned			nstate;
-	struct radeon_state		**state;
 };
 
+int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon);
+void radeon_ctx_fini(struct radeon_ctx *ctx);
+void radeon_ctx_clear(struct radeon_ctx *ctx);
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_submit(struct radeon_ctx *ctx);
+void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
+
 /*
  * R600/R700
  */
 
 enum r600_stype {
-	R600_STATE_CONFIG,  
+	R600_STATE_CONFIG,
 	R600_STATE_CB_CNTL,
 	R600_STATE_RASTERIZER,
 	R600_STATE_VIEWPORT,
@@ -223,14 +213,6 @@ enum r600_stype {
 	R600_STATE_DRAW,
 };
 
-enum {
-	R600_SHADER_PS = 1,
-	R600_SHADER_VS,
-	R600_SHADER_GS,
-	R600_SHADER_FS,
-	R600_SHADER_MAX = R600_SHADER_FS,
-};
-
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			1
diff --git a/src/gallium/targets/dri-r600/Makefile b/src/gallium/targets/dri-r600/Makefile
index ff886b37f2..661283de6a 100644
--- a/src/gallium/targets/dri-r600/Makefile
+++ b/src/gallium/targets/dri-r600/Makefile
@@ -4,12 +4,12 @@ include $(TOP)/configs/current
 LIBNAME = r600_dri.so
 
 PIPE_DRIVERS = \
+	$(TOP)/src/gallium/drivers/r600/libr600.a \
 	$(TOP)/src/gallium/state_trackers/dri/drm/libdridrm.a \
 	$(TOP)/src/gallium/winsys/r600/drm/libr600winsys.a \
 	$(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \
 	$(TOP)/src/gallium/drivers/trace/libtrace.a \
-	$(TOP)/src/gallium/drivers/rbug/librbug.a \
-	$(TOP)/src/gallium/drivers/r600/libr600.a
+	$(TOP)/src/gallium/drivers/rbug/librbug.a
 
 C_SOURCES = \
 	target.c \
diff --git a/src/gallium/winsys/r600/drm/r600_state.c b/src/gallium/winsys/r600/drm/r600_state.c
index f6a428e884..71d65f0fea 100644
--- a/src/gallium/winsys/r600/drm/r600_state.c
+++ b/src/gallium/winsys/r600/drm/r600_state.c
@@ -367,7 +367,6 @@ static int r600_state_pm4_vgt(struct radeon_state *state)
 
 static int r600_state_pm4_draw(struct radeon_state *state)
 {
-	unsigned i;
 	int r;
 
 	if (state->nbo) {
@@ -485,11 +484,10 @@ static void r600_build_types_array(struct radeon *radeon)
 		} else {
 			for (j = 0; j < R600_SHADER_MAX; j++) {
 				if (r600_stypes[i].reginfo[j].shader_type)
-					id += r600_stypes[i].num;					
+					id += r600_stypes[i].num;
 			}
 		}
 	}
-	radeon->nstate = id;
 	radeon->stype = r600_stypes;
 	radeon->nstype = STYPES_SIZE;
 
diff --git a/src/gallium/winsys/r600/drm/radeon.c b/src/gallium/winsys/r600/drm/radeon.c
index 2b16e3ce88..e2d813ebac 100644
--- a/src/gallium/winsys/r600/drm/radeon.c
+++ b/src/gallium/winsys/r600/drm/radeon.c
@@ -42,24 +42,13 @@ static int radeon_get_device(struct radeon *radeon)
 	return r;
 }
 
-/* symbol missing drove me crazy hack to get symbol exported */
-static void fake(void)
-{
-	struct radeon_ctx *ctx;
-	struct radeon_draw *draw;
-
-	ctx = radeon_ctx(NULL);
-	draw = radeon_draw(NULL);
-}
-
 struct radeon *radeon_new(int fd, unsigned device)
 {
 	struct radeon *radeon;
-	int r;
+	int r, i, id;
 
 	radeon = calloc(1, sizeof(*radeon));
 	if (radeon == NULL) {
-		fake();
 		return NULL;
 	}
 	radeon->fd = fd;
@@ -131,6 +120,19 @@ struct radeon *radeon_new(int fd, unsigned device)
 			__func__, radeon->device);
 		break;
 	}
+	radeon->state_type_id = calloc(radeon->nstype, sizeof(unsigned));
+	if (radeon->state_type_id == NULL) {
+		return radeon_decref(radeon);
+	}
+	for (i = 0, id = 0; i < radeon->nstype; i++) {
+		radeon->state_type_id[i] = id;
+		for (int j = 0; j < radeon->nstype; j++) {
+			if (radeon->stype[j].stype != i)
+				continue;
+			id += radeon->stype[j].num;
+		}
+	}
+	radeon->nstate_per_shader = id;
 	return radeon;
 }
 
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index 1a12c1023e..50c5e4741e 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -30,21 +30,16 @@
 #include "radeon_drm.h"
 #include "bof.h"
 
-int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo)
+static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo)
 {
-	void *ptr;
-
-	ptr = realloc(ctx->bo, sizeof(struct radeon_bo) * (ctx->nbo + 1));
-	if (ptr == NULL) {
-		return -ENOMEM;
-	}
-	ctx->bo = ptr;
+	if (ctx->nbo >= RADEON_CTX_MAX_PM4)
+		return -EBUSY;
 	ctx->bo[ctx->nbo] = bo;
 	ctx->nbo++;
 	return 0;
 }
 
-struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc)
+static struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc)
 {
 	struct radeon_cs_reloc *greloc;
 	unsigned i;
@@ -59,7 +54,7 @@ struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc)
 	return NULL;
 }
 
-void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement)
+static void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement)
 {
 	struct radeon_cs_reloc *greloc;
 	unsigned i;
@@ -76,50 +71,58 @@ void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *place
 	}
 }
 
-struct radeon_ctx *radeon_ctx(struct radeon *radeon)
+void radeon_ctx_clear(struct radeon_ctx *ctx)
 {
-	struct radeon_ctx *ctx;
-
-	if (radeon == NULL)
-		return NULL;
-	ctx = calloc(1, sizeof(*ctx));
-	if (ctx == NULL)
-		return NULL;
-	ctx->radeon = radeon_incref(radeon);
-	return ctx;
+	for (int i = 0; i < ctx->nbo; i++) {
+		ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
+	}
+	ctx->ndwords = RADEON_CTX_MAX_PM4;
+	ctx->cdwords = 0;
+	ctx->nreloc = 0;
+	ctx->nbo = 0;
 }
 
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx)
+int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon)
 {
-	ctx->refcount++;
-	return ctx;
+	if (radeon == NULL)
+		return -EINVAL;
+	memset(ctx, 0, sizeof(struct radeon_ctx));
+	ctx->radeon = radeon_incref(radeon);
+	radeon_ctx_clear(ctx);
+	ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4);
+	if (ctx->pm4 == NULL) {
+		radeon_ctx_fini(ctx);
+		return -ENOMEM;
+	}
+	ctx->reloc = malloc(sizeof(struct radeon_cs_reloc) * RADEON_CTX_MAX_PM4);
+	if (ctx->reloc == NULL) {
+		radeon_ctx_fini(ctx);
+		return -ENOMEM;
+	}
+	ctx->bo = malloc(sizeof(void *) * RADEON_CTX_MAX_PM4);
+	if (ctx->bo == NULL) {
+		radeon_ctx_fini(ctx);
+		return -ENOMEM;
+	}
+	return 0;
 }
 
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx)
+void radeon_ctx_fini(struct radeon_ctx *ctx)
 {
 	unsigned i;
 
 	if (ctx == NULL)
-		return NULL;
-	if (--ctx->refcount > 0) {
-		return NULL;
-	}
+		return;
 
-	for (i = 0; i < ctx->ndraw; i++) {
-		ctx->draw[i] = radeon_draw_decref(ctx->draw[i]);
-	}
 	for (i = 0; i < ctx->nbo; i++) {
 		ctx->bo[i] = radeon_bo_decref(ctx->radeon, ctx->bo[i]);
 	}
 	ctx->radeon = radeon_decref(ctx->radeon);
-	free(ctx->state);
-	free(ctx->draw);
 	free(ctx->bo);
 	free(ctx->pm4);
 	free(ctx->reloc);
 	memset(ctx, 0, sizeof(*ctx));
 	free(ctx);
-	return NULL;
 }
 
 static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
@@ -152,17 +155,17 @@ int radeon_ctx_submit(struct radeon_ctx *ctx)
 	uint64_t chunk_array[2];
 	int r = 0;
 
-	if (!ctx->cpm4)
+	if (!ctx->cdwords)
 		return 0;
 #if 0
-	for (r = 0; r < ctx->cpm4; r++) {
+	for (r = 0; r < ctx->cdwords; r++) {
 		fprintf(stderr, "0x%08X\n", ctx->pm4[r]);
 	}
 #endif
 	drmib.num_chunks = 2;
 	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
 	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
-	chunks[0].length_dw = ctx->cpm4;
+	chunks[0].length_dw = ctx->cdwords;
 	chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
 	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
 	chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
@@ -180,7 +183,6 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			unsigned id, unsigned *placement)
 {
 	unsigned i;
-	struct radeon_cs_reloc *ptr;
 
 	for (i = 0; i < ctx->nreloc; i++) {
 		if (ctx->reloc[i].handle == bo->handle) {
@@ -188,14 +190,13 @@ static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_bo *bo,
 			return 0;
 		}
 	}
-	ptr = realloc(ctx->reloc, sizeof(struct radeon_cs_reloc) * (ctx->nreloc + 1));
-	if (ptr == NULL)
-		return -ENOMEM;
-	ctx->reloc = ptr;
-	ptr[ctx->nreloc].handle = bo->handle;
-	ptr[ctx->nreloc].read_domain = placement[0] | placement [1];
-	ptr[ctx->nreloc].write_domain = placement[0] | placement [1];
-	ptr[ctx->nreloc].flags = 0;
+	if (ctx->nreloc >= RADEON_CTX_MAX_PM4) {
+		return -EBUSY;
+	}
+	ctx->reloc[ctx->nreloc].handle = bo->handle;
+	ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1];
+	ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1];
+	ctx->reloc[ctx->nreloc].flags = 0;
 	ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
 	ctx->nreloc++;
 	return 0;
@@ -208,11 +209,14 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
 
 	if (state == NULL)
 		return 0;
-	memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4);
+	if (state->cpm4 > ctx->ndwords) {
+		return -EBUSY;
+	}
+	memcpy(&ctx->pm4[ctx->cdwords], state->pm4, state->cpm4 * 4);
 	for (i = 0; i < state->nreloc; i++) {
 		rid = state->reloc_pm4_id[i];
 		bid = state->reloc_bo_id[i];
-		cid = ctx->id + rid;
+		cid = ctx->cdwords + rid;
 		r = radeon_ctx_reloc(ctx, state->bo[bid], cid,
 					&state->placement[bid * 2]);
 		if (r) {
@@ -220,120 +224,65 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
 			return r;
 		}
 	}
-	ctx->id += state->cpm4;
+	ctx->cdwords += state->cpm4;
+	ctx->ndwords -= state->cpm4;
 	return 0;
 }
 
 int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
 {
-	void *tmp;
 	int r = 0;
 
 	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
-	if (state->stype->stype != R600_STATE_QUERY_BEGIN && state->stype->stype != R600_STATE_QUERY_END) {
-		return -EINVAL;
-	}
 	r = radeon_state_pm4(state);
 	if (r)
 		return r;
-	if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
-		/* need to flush */
-		return -EBUSY;
-	}
-	if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
-		fprintf(stderr, "%s single state too big %d, max %d\n",
-			__func__, state->cpm4, RADEON_CTX_MAX_PM4);
-		return -EINVAL;
-	}
-	tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
-	if (tmp == NULL)
-		return -ENOMEM;
-	ctx->state = tmp;
-	ctx->state[ctx->nstate++] = radeon_state_incref(state);
 	/* BEGIN/END query are balanced in the same cs so account for END
 	 * END query when scheduling BEGIN query
 	 */
-	if (state->stype->stype == R600_STATE_QUERY_BEGIN) {
-		ctx->draw_cpm4 += state->cpm4 * 2;
+	switch (state->stype->stype) {
+	case R600_STATE_QUERY_BEGIN:
+		/* is there enough place for begin & end */
+		if ((state->cpm4 * 2) > ctx->ndwords)
+			return -EBUSY;
+		ctx->ndwords -= state->cpm4;
+		break;
+	case R600_STATE_QUERY_END:
+		ctx->ndwords += state->cpm4;
+		break;
+	default:
+		return -EINVAL;
 	}
-	return 0;
+	return radeon_ctx_state_schedule(ctx, state);
 }
 
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
 {
-	struct radeon_draw *pdraw = NULL;
-	struct radeon_draw **ndraw;
-	struct radeon_state *nstate, *ostate;
-	unsigned cpm4, i, cstate;
-	void *tmp;
+	unsigned previous_cdwords;
 	int r = 0;
 
-	ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1));
-	if (ndraw == NULL)
-		return -ENOMEM;
-	ctx->draw = ndraw;
-	for (i = 0; i < draw->nstate; i++) {
+	for (int i = 0; i < (ctx->radeon->nstate_per_shader * R600_SHADER_MAX); i++) {
 		r = radeon_ctx_state_bo(ctx, draw->state[i]);
 		if (r)
 			return r;
 	}
-	r = radeon_draw_check(draw);
-	if (r)
-		return r;
-	if (draw->cpm4 >= RADEON_CTX_MAX_PM4) {
-		fprintf(stderr, "%s single draw too big %d, max %d\n",
-			__func__, draw->cpm4, RADEON_CTX_MAX_PM4);
-		return -EINVAL;
-	}
-	tmp = realloc(ctx->state, (ctx->nstate + draw->nstate) * sizeof(void*));
-	if (tmp == NULL)
-		return -ENOMEM;
-	ctx->state = tmp;
-	pdraw = ctx->cdraw;
-	for (i = 0, cpm4 = 0, cstate = ctx->nstate; i < draw->nstate - 1; i++) {
-		nstate = draw->state[i];
-		if (nstate) {
-			if (pdraw && pdraw->state[i]) {
-				ostate = pdraw->state[i];
-				if (ostate->pm4_crc != nstate->pm4_crc) {
-					ctx->state[cstate++] = nstate;
-					cpm4 += nstate->cpm4;
+	previous_cdwords = ctx->cdwords;
+	for (int i = 0, id = 0; i < ctx->radeon->nstate_per_shader; i++) {
+		for (int j = 0; j < R600_SHADER_MAX; j++) {
+			id = j * ctx->radeon->nstate_per_shader + i;
+			if (draw->state[id]) {
+				r = radeon_ctx_state_schedule(ctx, draw->state[id]);
+				if (r) {
+					ctx->cdwords = previous_cdwords;
+					return r;
 				}
-			} else {
-				ctx->state[cstate++] = nstate;
-				cpm4 += nstate->cpm4;
 			}
 		}
 	}
-	/* The last state is the draw state always add it */
-	if (draw->state[i] == NULL) {
-		fprintf(stderr, "%s no draw command\n", __func__);
-		return -EINVAL;
-	}
-	ctx->state[cstate++] = draw->state[i];
-	cpm4 += draw->state[i]->cpm4;
-	if ((ctx->draw_cpm4 + cpm4) > RADEON_CTX_MAX_PM4) {
-		/* need to flush */
-		return -EBUSY;
-	}
-	ctx->draw_cpm4 += cpm4;
-	ctx->nstate = cstate;
-	ctx->draw[ctx->ndraw++] = draw;
-	ctx->cdraw = draw;
 	return 0;
 }
 
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
-{
-	int r;
-
-	radeon_draw_incref(draw);
-	r = radeon_ctx_set_draw_new(ctx, draw);
-	if (r)
-		radeon_draw_decref(draw);
-	return r;
-}
-
+#if 0
 int radeon_ctx_pm4(struct radeon_ctx *ctx)
 {
 	unsigned i;
@@ -345,9 +294,6 @@ int radeon_ctx_pm4(struct radeon_ctx *ctx)
 	if (ctx->pm4 == NULL)
 		return -EINVAL;
 	for (i = 0, ctx->id = 0; i < ctx->nstate; i++) {
-		r = radeon_ctx_state_schedule(ctx, ctx->state[i]);
-		if (r)
-			return r;
 	}
 	if (ctx->id != ctx->draw_cpm4) {
 		fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
@@ -357,6 +303,7 @@ int radeon_ctx_pm4(struct radeon_ctx *ctx)
 	ctx->cpm4 = ctx->draw_cpm4;
 	return 0;
 }
+#endif
 
 void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file)
 {
@@ -384,8 +331,8 @@ printf("%d relocs\n", ctx->nreloc);
 	bof_decref(blob);
 	blob = NULL;
 	/* dump cs */
-printf("%d pm4\n", ctx->cpm4);
-	blob = bof_blob(ctx->cpm4 * 4, ctx->pm4);
+printf("%d pm4\n", ctx->cdwords);
+	blob = bof_blob(ctx->cdwords * 4, ctx->pm4);
 	if (blob == NULL)
 		goto out_err;
 	if (bof_object_set(root, "pm4", blob))
diff --git a/src/gallium/winsys/r600/drm/radeon_draw.c b/src/gallium/winsys/r600/drm/radeon_draw.c
index 0eacdc74a0..b992c4a55d 100644
--- a/src/gallium/winsys/r600/drm/radeon_draw.c
+++ b/src/gallium/winsys/r600/drm/radeon_draw.c
@@ -31,116 +31,27 @@
 /*
  * draw functions
  */
-struct radeon_draw *radeon_draw(struct radeon *radeon)
+int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon)
 {
-	struct radeon_draw *draw;
-
-	draw = calloc(1, sizeof(*draw));
-	if (draw == NULL)
-		return NULL;
-	draw->nstate = radeon->nstate;
 	draw->radeon = radeon;
-	draw->refcount = 1;
-	draw->state = calloc(1, sizeof(void*) * draw->nstate);
-	if (draw->state == NULL) {
-		free(draw);
-		return NULL;
-	}
-	return draw;
-}
-
-struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw)
-{
-	draw->refcount++;
-	return draw;
-}
-
-struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw)
-{
-	unsigned i;
-
-	if (draw == NULL)
-		return NULL;
-	if (--draw->refcount > 0)
-		return NULL;
-	for (i = 0; i < draw->nstate; i++) {
-		draw->state[i] = radeon_state_decref(draw->state[i]);
-	}
-	free(draw->state);
-	memset(draw, 0, sizeof(*draw));
-	free(draw);
-	return NULL;
-}
-
-int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state)
-{
-	int id;
-	if (state == NULL)
-		return 0;
-
-	id = state->stype->base_id + (state->id + (state->stype->num * state->shader_index));
-	if (id > draw->radeon->nstate)
-	{
-		return -EINVAL;
-	}
-	draw->state[id] = radeon_state_decref(draw->state[id]);
-	draw->state[id] = state;
+	draw->state = calloc(radeon->nstate_per_shader * R600_SHADER_MAX, sizeof(void*));
+	if (draw->state == NULL)
+		return -ENOMEM;
 	return 0;
 }
 
-int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state)
+void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state)
 {
 	if (state == NULL)
-		return 0;
-	radeon_state_incref(state);
-	return radeon_draw_set_new(draw, state);
+		return;
+	draw->state[state->state_id] = state;
 }
 
-int radeon_draw_check(struct radeon_draw *draw)
+void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state)
 {
-	unsigned i;
-	int r;
-
-	r = radeon_draw_pm4(draw);
-	if (r)
-		return r;
-	for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
-		if (draw->state[i]) {
-			draw->cpm4 += draw->state[i]->cpm4;
-		}
-	}
-	return 0;
-}
-
-struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw)
-{
-	struct radeon_draw *ndraw;
-	unsigned i;
-
-	if (draw == NULL)
-		return NULL;
-	ndraw = radeon_draw(draw->radeon);
-	if (ndraw == NULL) {
-		return NULL;
-	}
-	for (i = 0; i < draw->nstate; i++) {
-		if (radeon_draw_set(ndraw, draw->state[i])) {
-			radeon_draw_decref(ndraw);
-			return NULL;
-		}
-	}
-	return ndraw;
-}
-
-int radeon_draw_pm4(struct radeon_draw *draw)
-{
-	unsigned i;
-	int r;
-
-	for (i = 0; i < draw->nstate; i++) {
-		r = radeon_state_pm4(draw->state[i]);
-		if (r)
-			return r;
+	if (state == NULL)
+		return;
+	if (draw->state[state->state_id] == state) {
+		draw->state[state->state_id] = NULL;
 	}
-	return 0;
 }
diff --git a/src/gallium/winsys/r600/drm/radeon_priv.h b/src/gallium/winsys/r600/drm/radeon_priv.h
index af5319efd1..84e552ba4d 100644
--- a/src/gallium/winsys/r600/drm/radeon_priv.h
+++ b/src/gallium/winsys/r600/drm/radeon_priv.h
@@ -58,9 +58,10 @@ struct radeon {
 	int				refcount;
 	unsigned			device;
 	unsigned			family;
-	unsigned			nstate;
-	unsigned                        nstype;
-	struct radeon_stype_info *stype;
+	unsigned			nstype;
+	unsigned			nstate_per_shader;
+	unsigned			*state_type_id;
+	struct radeon_stype_info	*stype;
 };
 
 extern struct radeon *radeon_new(int fd, unsigned device);
@@ -69,12 +70,6 @@ extern struct radeon *radeon_decref(struct radeon *radeon);
 extern unsigned radeon_family_from_device(unsigned device);
 extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
 
-int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_bo *bo);
-struct radeon_bo *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
-void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_draw(struct radeon_ctx *ctx);
-
 /*
  * r600/r700 context functions
  */
diff --git a/src/gallium/winsys/r600/drm/radeon_state.c b/src/gallium/winsys/r600/drm/radeon_state.c
index d4e622cf7f..ac60485b28 100644
--- a/src/gallium/winsys/r600/drm/radeon_state.c
+++ b/src/gallium/winsys/r600/drm/radeon_state.c
@@ -32,9 +32,8 @@
 /*
  * state core functions
  */
-struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 id, u32 shader_type)
+int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 stype, u32 id, u32 shader_type)
 {
-	struct radeon_state *state;
 	struct radeon_stype_info *found = NULL;
 	int i, j, shader_index = -1;
 
@@ -67,12 +66,11 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 i
 
 	if (!found) {
 		fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
-		return NULL;
+		return -EINVAL;
 	}
 
-	state = calloc(1, sizeof(*state));
-	if (state == NULL)
-		return NULL;
+	memset(state, 0, sizeof(struct radeon_state));
+	state->state_id = radeon->nstate_per_shader * shader_index + radeon->state_type_id[stype] + id;
 	state->stype = found;
 	state->radeon = radeon;
 	state->id = id;
@@ -80,7 +78,7 @@ struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 stype, u32 i
 	state->refcount = 1;
 	state->npm4 = found->npm4;
 	state->nstates = found->reginfo[shader_index].nstates;
-	return state;
+	return 0;
 }
 
 int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type)
@@ -130,57 +128,20 @@ int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shad
 	state->stype = found;
 	state->id = id;
 	state->shader_index = shader_index;
+	state->state_id = state->radeon->nstate_per_shader * shader_index + state->radeon->state_type_id[stype] + id;
 	return radeon_state_pm4(state);
 }
 
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
-{
-	return radeon_state_shader(radeon, type, id, 0);
-}
-
-struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
-{
-	struct radeon_state *nstate = radeon_state_shader(state->radeon, state->stype->stype, state->id, (1 << state->shader_index));
-	unsigned i;
-
-	if (state == NULL)
-		return NULL;
-	nstate->cpm4 = state->cpm4;
-	nstate->nbo = state->nbo;
-	nstate->nreloc = state->nreloc;
-	memcpy(nstate->states, state->states, state->nstates * 4);
-	memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
-	memcpy(nstate->placement, state->placement, 8 * 4);
-	memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
-	memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
-	memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
-	for (i = 0; i < state->nbo; i++) {
-		nstate->bo[i] = radeon_bo_incref(state->radeon, state->bo[i]);
-	}
-	return nstate;
-}
-
-struct radeon_state *radeon_state_incref(struct radeon_state *state)
-{
-	state->refcount++;
-	return state;
-}
-
-struct radeon_state *radeon_state_decref(struct radeon_state *state)
+void radeon_state_fini(struct radeon_state *state)
 {
 	unsigned i;
 
 	if (state == NULL)
 		return NULL;
-	if (--state->refcount > 0) {
-		return NULL;
-	}
 	for (i = 0; i < state->nbo; i++) {
 		state->bo[i] = radeon_bo_decref(state->radeon, state->bo[i]);
 	}
-	memset(state, 0, sizeof(*state));
-	free(state);
-	return NULL;
+	memset(state, 0, sizeof(struct radeon_state));
 }
 
 int radeon_state_replace_always(struct radeon_state *ostate,
-- 
cgit v1.2.3


From c70459a1b9f718ae0748070cbf8c7c623d8840ac Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexdeucher@gmail.com>
Date: Wed, 1 Sep 2010 13:57:52 -0400
Subject: r600g: fix up default state differences between r6xx and r7xx

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
---
 src/gallium/drivers/r600/r600_context.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 95e9b6a8ed..f1781ce7fb 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -258,13 +258,24 @@ static void r600_init_config(struct r600_context *rctx)
 	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
 	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 
-	rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
 	rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
 	rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+
+	if (family >= CHIP_RV770) {
+		rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+		rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+		rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+		rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+		rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000000;
+		rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	} else {
+		rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00000000;
+		rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000003;
+		rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x82000000;
+		rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x01020204;
+		rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+		rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00004010;
+	}
 	rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
 	rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
 	rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
@@ -288,7 +299,6 @@ static void r600_init_config(struct r600_context *rctx)
 	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
 	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
 	rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
 	rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
 	rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
 	rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-- 
cgit v1.2.3


From 67234b4b42a8285a9b14da48dd113cbe2ee871fd Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 1 Sep 2010 18:04:38 -0400
Subject: r600g: refix db/cb state

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.c |   2 +
 src/gallium/drivers/r600/r600_context.h |   2 +-
 src/gallium/drivers/r600/r600_draw.c    |   4 +-
 src/gallium/drivers/r600/r600_shader.c  |   6 +-
 src/gallium/drivers/r600/r600_state.c   | 135 ++++++++++++++++++++++++++------
 src/gallium/drivers/r600/r600_texture.c |   2 +-
 6 files changed, 119 insertions(+), 32 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index f1781ce7fb..0e5e0632bf 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -57,11 +57,13 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 	 */
 	if (!rctx->ctx.cdwords)
 		goto out;
+#if 0
 	sprintf(dname, "gallium-%08d.bof", dc);
 	if (dc < 2) {
 		radeon_ctx_dump_bof(&rctx->ctx, dname);
 		R600_ERR("dumped %s\n", dname);
 	}
+#endif
 #if 1
 	radeon_ctx_submit(&rctx->ctx);
 #endif
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index a48dca4915..eb7a64bfbd 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -99,7 +99,7 @@ struct r600_context_state {
 	union pipe_states		state;
 	unsigned			refcount;
 	unsigned			type;
-	struct radeon_state		rstate;
+	struct radeon_state		rstate[16];
 	struct r600_shader		shader;
 	struct radeon_bo		*bo;
 };
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index bddc81e50a..9cc26bbada 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -91,8 +91,8 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate);
-	radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate);
+	radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate[0]);
+	radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate[0]);
 
 	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
 		vs_resource = &rctx->vs_resource[i];
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 9af45b7793..3147bc7ca3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -134,8 +134,8 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	struct radeon_state *state;
 	unsigned i, tmp;
 
-	state = &rpshader->rstate;
-	radeon_state_fini(&rpshader->rstate);
+	state = &rpshader->rstate[0];
+	radeon_state_fini(&rpshader->rstate[0]);
 	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 	for (i = 0; i < 10; i++) {
 		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
@@ -166,7 +166,7 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	unsigned i, tmp, exports_ps, num_cout;
 	boolean have_pos = FALSE;
 
-	state = &rpshader->rstate;
+	state = &rpshader->rstate[0];
 	rasterizer = &rctx->rasterizer->state.rasterizer;
 	radeon_state_fini(state);
 	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index c6810ffe36..bb12b42213 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -39,6 +39,10 @@ static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate
 static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
 static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
 static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
+static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_framebuffer_state *state, int cb);
+static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_framebuffer_state *state);
 
 
 static void *r600_create_blend_state(struct pipe_context *ctx,
@@ -93,7 +97,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
 	rstate->state.sampler_view.context = ctx;
-	r600_resource(ctx, &rstate->rstate, &rstate->state.sampler_view, 0);
+	r600_resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
 	return &rstate->state.sampler_view;
 }
 
@@ -238,7 +242,7 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)states[i];
 		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
+			radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_PS);
 		}
 	}
 	rctx->ps_nsampler = count;
@@ -258,7 +262,7 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)states[i];
 		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
+			radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_VS);
 		}
 	}
 	rctx->vs_nsampler = count;
@@ -352,7 +356,7 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)views[i];
 		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
+			radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_PS);
 		}
 	}
 	rctx->ps_nsampler_view = count;
@@ -373,7 +377,7 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)views[i];
 		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
+			radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_VS);
 		}
 	}
 	rctx->vs_nsampler_view = count;
@@ -383,18 +387,15 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
 					const struct pipe_framebuffer_state *state)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct r600_resource_texture *rtexture;
 	struct r600_context_state *rstate;
 
 	rstate = r600_context_state(rctx, pipe_framebuffer_type, state);
 	r600_bind_state(ctx, rstate);
 	for (int i = 0; i < state->nr_cbufs; i++) {
-		rtexture = (struct r600_resource_texture*)state->cbufs[i]->texture;
-		r600_texture_cb(ctx, rtexture, i, state->cbufs[i]->level);
+		r600_cb(rctx, &rstate->rstate[i+1], state, i);
 	}
 	if (state->zsbuf) {
-		rtexture = (struct r600_resource_texture*)state->zsbuf->texture;
-		r600_texture_db(ctx, rtexture, state->zsbuf->level);
+		r600_db(rctx, &rstate->rstate[0], state);
 	}
 }
 
@@ -561,7 +562,7 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state *
 		R600_ERR("invalid type %d\n", rstate->type);
 		return NULL;
 	}
-	radeon_state_fini(&rstate->rstate);
+	radeon_state_fini(&rstate->rstate[0]);
 	FREE(rstate);
 	return NULL;
 }
@@ -594,7 +595,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_viewport_type:
 		rstate->state.viewport = (*states).viewport;
-		r600_viewport(rctx, &rstate->rstate, &rstate->state.viewport);
+		r600_viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
 		break;
 	case pipe_depth_type:
 		rstate->state.depth = (*states).depth;
@@ -610,7 +611,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_clip_type:
 		rstate->state.clip = (*states).clip;
-		r600_ucp(rctx, &rstate->rstate, &rstate->state.clip);
+		r600_ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
 		break;
 	case pipe_stencil_type:
 		rstate->state.stencil = (*states).stencil;
@@ -623,7 +624,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_blend_type:
 		rstate->state.blend = (*states).blend;
-		r600_blend(rctx, &rstate->rstate, &rstate->state.blend);
+		r600_blend(rctx, &rstate->rstate[0], &rstate->state.blend);
 		break;
 	case pipe_stencil_ref_type:
 		rstate->state.stencil_ref = (*states).stencil_ref;
@@ -638,7 +639,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_sampler_type:
 		rstate->state.sampler = (*states).sampler;
-		r600_sampler(rctx, &rstate->rstate, &rstate->state.sampler, 0);
+		r600_sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
 		break;
 	default:
 		R600_ERR("invalid type %d\n", rstate->type);
@@ -716,6 +717,93 @@ static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
 	radeon_state_pm4(rstate);
 }
 
+static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
+			struct pipe_framebuffer_state *state, int cb)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level = state->cbufs[cb]->level;
+	unsigned pitch, slice;
+	unsigned color_info;
+	unsigned format, swap, ntype;
+	const struct util_format_description *desc;
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
+	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	rbuffer = &rtex->resource;
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
+	rstate->nbo = 3;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
+
+	ntype = 0;
+	desc = util_format_description(rtex->resource.base.b.format);
+	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+		ntype = V_0280A0_NUMBER_SRGB;
+
+	format = r600_translate_colorformat(rtex->resource.base.b.format);
+	swap = r600_translate_colorswap(rtex->resource.base.b.format);
+
+	color_info = S_0280A0_FORMAT(format) |
+		S_0280A0_COMP_SWAP(swap) |
+		S_0280A0_BLEND_CLAMP(1) |
+		S_0280A0_SOURCE_FORMAT(1) |
+		S_0280A0_NUMBER_TYPE(ntype);
+
+	rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
+	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
+	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
+						S_028060_SLICE_TILE_MAX(slice);
+	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
+	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
+	radeon_state_pm4(rstate);
+}
+
+static void r600_db(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_framebuffer_state *state)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_resource_texture *rtex;
+	struct r600_resource *rbuffer;
+	unsigned level;
+	unsigned pitch, slice, format;
+
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
+	if (state->zsbuf == NULL)
+		return;
+
+	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
+	rtex->tilled = 1;
+	rtex->array_mode = 2;
+	rtex->tile_type = 1;
+	rtex->depth = 1;
+	rbuffer = &rtex->resource;
+
+	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+	rstate->nbo = 1;
+	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
+	level = state->zsbuf->level;
+	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
+	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
+	format = r600_translate_dbformat(state->zsbuf->texture->format);
+	rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
+	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
+					S_028010_FORMAT(format);
+	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
+	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
+	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
+						S_028000_SLICE_TILE_MAX(slice);
+	radeon_state_pm4(rstate);
+}
+
 static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
@@ -1233,7 +1321,6 @@ static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 int r600_context_hw_states(struct pipe_context *ctx)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct r600_resource_texture *rtexture;
 	unsigned i;
 
 	/* build new states */
@@ -1251,30 +1338,28 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	radeon_draw_bind(&rctx->draw, &rctx->config);
 
 	if (rctx->viewport) {
-		radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate);
+		radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
 	}
 	if (rctx->blend) {
-		radeon_draw_bind(&rctx->draw, &rctx->blend->rstate);
+		radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
 	}
 	if (rctx->clip) {
-		radeon_draw_bind(&rctx->draw, &rctx->clip->rstate);
+		radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
 	}
 	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
-		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.cbufs[i]->texture;
-		radeon_draw_bind(&rctx->draw, &rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level]);
+		radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
 	}
 	if (rctx->framebuffer->state.framebuffer.zsbuf) {
-		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.zsbuf->texture;
-		radeon_draw_bind(&rctx->draw, &rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level]);
+		radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
 	}
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate);
+			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate[0]);
 		}
 	}
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate);
+			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate[0]);
 		}
 	}
 	return 0;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index c472d4f37b..83fd01e8a1 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -632,7 +632,7 @@ out_word4:
 		*yuv_format_p = yuv_format;
 	return result;
 out_unknown:
-	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
+//	R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format));
 	return ~0;
 }
 
-- 
cgit v1.2.3


From ffcb443cd7be563071725885b87085bd5701d980 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 1 Sep 2010 18:09:37 -0400
Subject: r600g: silence compiler warning

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index bb12b42213..4f00cfb381 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -718,7 +718,7 @@ static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
 }
 
 static void r600_cb(struct r600_context *rctx, struct radeon_state *rstate,
-			struct pipe_framebuffer_state *state, int cb)
+			const struct pipe_framebuffer_state *state, int cb)
 {
 	struct r600_screen *rscreen = rctx->screen;
 	struct r600_resource_texture *rtex;
-- 
cgit v1.2.3


From 36192b772eda190c4d78e8a4979c4e3c6377ae61 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 2 Sep 2010 11:16:31 +1000
Subject: r600g: fix incorrect state naming in pipe_sampler vs
 pipe_sampler_view

fixes problems in valgrind with uninitialised values.
---
 src/gallium/drivers/r600/r600_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 4f00cfb381..888507747b 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -92,7 +92,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_context_state *rstate;
 
-	rstate = r600_context_state(rctx, pipe_sampler_type, state);
+	rstate = r600_context_state(rctx, pipe_sampler_view_type, state);
 	pipe_reference(NULL, &texture->reference);
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
-- 
cgit v1.2.3


From 31b84acbd2ae2dc7555844c5a2eead932b8759a7 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Wed, 1 Sep 2010 21:57:43 -0400
Subject: r600g: fix binding of same texture to several target slot

One can bind same texture or sampler to different slot,
each slot needs it own state. The solution implemented
here is not exactly beautifull or optimal need to think
to somethings better.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.h | 13 +++---
 src/gallium/drivers/r600/r600_state.c   | 72 ++++++++++++++++++++++++---------
 2 files changed, 62 insertions(+), 23 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index eb7a64bfbd..d4e3baa69d 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -95,13 +95,16 @@ enum pipe_state_type {
 	pipe_type_count
 };
 
+#define R600_MAX_RSTATE		16
+
 struct r600_context_state {
 	union pipe_states		state;
 	unsigned			refcount;
 	unsigned			type;
-	struct radeon_state		rstate[16];
+	struct radeon_state		rstate[R600_MAX_RSTATE];
 	struct r600_shader		shader;
 	struct radeon_bo		*bo;
+	unsigned			nrstate;
 };
 
 struct r600_vertex_element
@@ -153,10 +156,10 @@ struct r600_context {
 	struct r600_context_state	*stencil_ref;
 	struct r600_context_state	*viewport;
 	struct r600_context_state	*framebuffer;
-	struct r600_context_state	*ps_sampler[PIPE_MAX_ATTRIBS];
-	struct r600_context_state	*vs_sampler[PIPE_MAX_ATTRIBS];
-	struct r600_context_state	*ps_sampler_view[PIPE_MAX_ATTRIBS];
-	struct r600_context_state	*vs_sampler_view[PIPE_MAX_ATTRIBS];
+	struct radeon_state		*ps_sampler[PIPE_MAX_ATTRIBS];
+	struct radeon_state		*vs_sampler[PIPE_MAX_ATTRIBS];
+	struct radeon_state		*ps_sampler_view[PIPE_MAX_ATTRIBS];
+	struct radeon_state		*vs_sampler_view[PIPE_MAX_ATTRIBS];
 	struct r600_vertex_element	*vertex_elements;
 	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
 	struct pipe_index_buffer	index_buffer;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 888507747b..95611d1739 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -235,14 +235,23 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
 	struct r600_context_state *rstate;
 	unsigned i;
 
-	for (i = 0; i < rctx->ps_nsampler; i++) {
-		rctx->ps_sampler[i] = r600_context_state_decref(rctx->ps_sampler[i]);
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)states[i];
+		if (rstate) {
+			rstate->nrstate = 0;
+		}
 	}
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
-		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_PS);
+			if (rstate->nrstate >= R600_MAX_RSTATE)
+				continue;
+			if (rstate->nrstate) {
+				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+			}
+			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_PS);
+			rctx->ps_sampler[i] = &rstate->rstate[rstate->nrstate];
+			rstate->nrstate++;
 		}
 	}
 	rctx->ps_nsampler = count;
@@ -255,14 +264,23 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
 	struct r600_context_state *rstate;
 	unsigned i;
 
-	for (i = 0; i < rctx->vs_nsampler; i++) {
-		rctx->vs_sampler[i] = r600_context_state_decref(rctx->vs_sampler[i]);
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)states[i];
+		if (rstate) {
+			rstate->nrstate = 0;
+		}
 	}
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)states[i];
-		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate[0], R600_STATE_SAMPLER, i, R600_SHADER_VS);
+			if (rstate->nrstate >= R600_MAX_RSTATE)
+				continue;
+			if (rstate->nrstate) {
+				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+			}
+			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, R600_SHADER_VS);
+			rctx->vs_sampler[i] = &rstate->rstate[rstate->nrstate];
+			rstate->nrstate++;
 		}
 	}
 	rctx->vs_nsampler = count;
@@ -349,14 +367,23 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 	struct r600_context_state *rstate;
 	unsigned i;
 
-	for (i = 0; i < rctx->ps_nsampler_view; i++) {
-		rctx->ps_sampler_view[i] = r600_context_state_decref(rctx->ps_sampler_view[i]);
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)views[i];
+		if (rstate) {
+			rstate->nrstate = 0;
+		}
 	}
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
-		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_PS);
+			if (rstate->nrstate >= R600_MAX_RSTATE)
+				continue;
+			if (rstate->nrstate) {
+				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+			}
+			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_PS);
+			rctx->ps_sampler_view[i] = &rstate->rstate[rstate->nrstate];
+			rstate->nrstate++;
 		}
 	}
 	rctx->ps_nsampler_view = count;
@@ -370,14 +397,23 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 	struct r600_context_state *rstate;
 	unsigned i;
 
-	for (i = 0; i < rctx->vs_nsampler_view; i++) {
-		rctx->vs_sampler_view[i] = r600_context_state_decref(rctx->vs_sampler_view[i]);
+	for (i = 0; i < count; i++) {
+		rstate = (struct r600_context_state *)views[i];
+		if (rstate) {
+			rstate->nrstate = 0;
+		}
 	}
 	for (i = 0; i < count; i++) {
 		rstate = (struct r600_context_state *)views[i];
-		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(&rstate->rstate[0], R600_STATE_RESOURCE, i, R600_SHADER_VS);
+			if (rstate->nrstate >= R600_MAX_RSTATE)
+				continue;
+			if (rstate->nrstate) {
+				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
+			}
+			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, R600_SHADER_VS);
+			rctx->vs_sampler_view[i] = &rstate->rstate[rstate->nrstate];
+			rstate->nrstate++;
 		}
 	}
 	rctx->vs_nsampler_view = count;
@@ -1354,12 +1390,12 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	}
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate[0]);
+			radeon_draw_bind(&rctx->draw, rctx->ps_sampler[i]);
 		}
 	}
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate[0]);
+			radeon_draw_bind(&rctx->draw, rctx->ps_sampler_view[i]);
 		}
 	}
 	return 0;
-- 
cgit v1.2.3


From 7299023c2aa5378b2d54663a53cb2fa4e743fa73 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 2 Sep 2010 13:32:25 +1000
Subject: r600g: add missing vertex fetch formats to the translation table.

fixes at least 2 more piglits.
---
 src/gallium/drivers/r600/r600_state_inlines.h | 2 ++
 src/gallium/drivers/r600/r600d.h              | 1 +
 2 files changed, 3 insertions(+)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state_inlines.h b/src/gallium/drivers/r600/r600_state_inlines.h
index d67d4be6f8..84866825aa 100644
--- a/src/gallium/drivers/r600/r600_state_inlines.h
+++ b/src/gallium/drivers/r600/r600_state_inlines.h
@@ -252,6 +252,7 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 	case PIPE_FORMAT_X8B8G8R8_UNORM:
 	case PIPE_FORMAT_X8R8G8B8_UNORM:
+	case PIPE_FORMAT_R8G8B8_UNORM:
 		return V_0280A0_COLOR_8_8_8_8;
 
 	case PIPE_FORMAT_R10G10B10A2_UNORM:
@@ -278,6 +279,7 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
 
 		/* 128-bit buffers. */
 	case PIPE_FORMAT_R32G32B32_FLOAT:
+	  	return V_0280A0_COLOR_32_32_32_FLOAT;
 	case PIPE_FORMAT_R32G32B32A32_FLOAT:
 		return V_0280A0_COLOR_32_32_32_32_FLOAT;
 
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 9bdfe4f966..7b9a983d53 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -199,6 +199,7 @@
 #define     V_0280A0_COLOR_16_16_16_16_FLOAT           0x00000020
 #define     V_0280A0_COLOR_32_32_32_32                 0x00000022
 #define     V_0280A0_COLOR_32_32_32_32_FLOAT           0x00000023
+#define     V_0280A0_COLOR_32_32_32_FLOAT              0x00000030
 #define   S_0280A0_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
 #define   G_0280A0_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
 #define   C_0280A0_ARRAY_MODE                          0xFFFFF0FF
-- 
cgit v1.2.3


From e8ff0f63b6f078b17989e42dd05c9b69729b341b Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 2 Sep 2010 15:51:23 +1000
Subject: r600g: fix depth texture tests

---
 src/gallium/drivers/r600/r600_texture.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 83fd01e8a1..b6698e3885 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -455,6 +455,8 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 	};
 	desc = util_format_description(format);
 
+	word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
+
 	/* Colorspace (return non-RGB formats directly). */
 	switch (desc->colorspace) {
 		/* Depth stencil formats */
@@ -493,8 +495,6 @@ uint32_t r600_translate_texformat(enum pipe_format format,
 		break;
 	}
 	
-	word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
-
 	/* S3TC formats. TODO */
 	if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 		goto out_unknown;
-- 
cgit v1.2.3


From 76d0541e79d4fe2ffcb25b17f9dd540fafc14ba2 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 2 Sep 2010 16:39:32 +1000
Subject: r600g: fix logicop, the 3d ROP is the 2D rop shifted twice.

---
 src/gallium/drivers/r600/r600_state.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 95611d1739..66cab7d7a6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1319,7 +1319,7 @@ static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 	}
 
 	if (pbs->logicop_enable) {
-		color_control |= (pbs->logicop_func) << 16;
+		color_control |= (pbs->logicop_func << 16) | (pbs->logicop_func << 20);
 	} else {
 		color_control |= (0xcc << 16);
 	}
-- 
cgit v1.2.3


From 5d5f693cefe452bd8bd7e45f8b5d7ed991ae5115 Mon Sep 17 00:00:00 2001
From: Dave Airlie <airlied@redhat.com>
Date: Thu, 2 Sep 2010 21:25:42 +1000
Subject: r600g: fix thinko in shadow code.

spotted by taiu on irc
---
 src/gallium/drivers/r600/r600_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 3147bc7ca3..0ba26a2311 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1684,7 +1684,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
 	}
 
 	if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D || inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D)
-		tex.coord_type_w = 2;
+		tex.src_sel_w = 2;
 
 	r = r600_bc_add_tex(ctx->bc, &tex);
 	if (r)
-- 
cgit v1.2.3


From e73c5501b2fe20290d1b691c85a5d82ac3a0431c Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Thu, 2 Sep 2010 11:32:32 -0400
Subject: r600g: fix memory/bo leak

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_context.c  | 15 +++++++++++++++
 src/gallium/drivers/r600/r600_context.h  |  1 +
 src/gallium/drivers/r600/r600_draw.c     |  4 ++++
 src/gallium/winsys/r600/drm/radeon_ctx.c |  3 +--
 4 files changed, 21 insertions(+), 2 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index 0e5e0632bf..7a0e5b4049 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -39,6 +39,21 @@ static void r600_destroy_context(struct pipe_context *context)
 {
 	struct r600_context *rctx = r600_context(context);
 
+	rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
+	rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
+	rctx->scissor = r600_context_state_decref(rctx->scissor);
+	rctx->clip = r600_context_state_decref(rctx->clip);
+	rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
+	rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
+	rctx->depth = r600_context_state_decref(rctx->depth);
+	rctx->stencil = r600_context_state_decref(rctx->stencil);
+	rctx->alpha = r600_context_state_decref(rctx->alpha);
+	rctx->dsa = r600_context_state_decref(rctx->dsa);
+	rctx->blend = r600_context_state_decref(rctx->blend);
+	rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
+	rctx->viewport = r600_context_state_decref(rctx->viewport);
+	rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
+	radeon_ctx_fini(&rctx->ctx);
 	FREE(rctx);
 }
 
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index d4e3baa69d..cea0813054 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -131,6 +131,7 @@ struct r600_context {
 	struct radeon_state		config;
 	/* FIXME get rid of those vs_resource,vs/ps_constant */
 	struct radeon_state		vs_resource[160];
+	unsigned			vs_nresource;
 	struct radeon_state		vs_constant[256];
 	struct radeon_state		ps_constant[256];
 	/* hw states */
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 9cc26bbada..fabd337d23 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -94,6 +94,9 @@ static int r600_draw_common(struct r600_draw *draw)
 	radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate[0]);
 	radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate[0]);
 
+	for (i = 0 ; i < rctx->vs_nresource; i++) {
+		radeon_state_fini(&rctx->vs_resource[i]);
+	}
 	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
 		vs_resource = &rctx->vs_resource[i];
 		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
@@ -120,6 +123,7 @@ static int r600_draw_common(struct r600_draw *draw)
 		}
 		radeon_draw_bind(&rctx->draw, vs_resource);
 	}
+	rctx->vs_nresource = rctx->vertex_elements->count;
 	/* FIXME start need to change winsys */
 	radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
 	draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
diff --git a/src/gallium/winsys/r600/drm/radeon_ctx.c b/src/gallium/winsys/r600/drm/radeon_ctx.c
index 50c5e4741e..47fca76136 100644
--- a/src/gallium/winsys/r600/drm/radeon_ctx.c
+++ b/src/gallium/winsys/r600/drm/radeon_ctx.c
@@ -121,8 +121,7 @@ void radeon_ctx_fini(struct radeon_ctx *ctx)
 	free(ctx->bo);
 	free(ctx->pm4);
 	free(ctx->reloc);
-	memset(ctx, 0, sizeof(*ctx));
-	free(ctx);
+	memset(ctx, 0, sizeof(struct radeon_ctx));
 }
 
 static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
-- 
cgit v1.2.3