From 66e4cb1cd5a55402606a09417349d2be8b009e89 Mon Sep 17 00:00:00 2001
From: Jerome Glisse <jglisse@redhat.com>
Date: Mon, 30 Aug 2010 17:56:59 -0400
Subject: r600g: avoid dynamic allocation of states

Make state statically allocated, this kills a bunch of code
and avoid intensive use of malloc/free. There is still a lot
of useless duplicate function wrapping that can be kill. This
doesn't improve yet performance, needs to avoid memcpy states
in radeon_ctx_set_draw and to avoid rebuilding vs_resources,
dsa, scissor, cb_cntl, ... states at each draw command.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
---
 src/gallium/drivers/r600/r600_blit.c     | 415 ++++++++-----------------------
 src/gallium/drivers/r600/r600_context.c  | 142 +++++------
 src/gallium/drivers/r600/r600_context.h  |  31 +--
 src/gallium/drivers/r600/r600_draw.c     |  92 ++++---
 src/gallium/drivers/r600/r600_query.c    |  48 ++--
 src/gallium/drivers/r600/r600_resource.h |   8 +-
 src/gallium/drivers/r600/r600_shader.c   |  32 ++-
 src/gallium/drivers/r600/r600_state.c    | 386 ++++++----------------------
 src/gallium/drivers/r600/r600_texture.c  | 100 ++------
 src/gallium/drivers/r600/radeon.h        |  72 ++----
 10 files changed, 399 insertions(+), 927 deletions(-)

(limited to 'src/gallium/drivers')

diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index a8263ccbce..e6ded342e5 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -146,21 +146,20 @@ void r600_init_blit_functions(struct r600_context *rctx)
 
 
 struct r600_blit_states {
-	struct radeon_state	*rasterizer;
-	struct radeon_state	*dsa;
-	struct radeon_state	*blend;
-	struct radeon_state	*cb_cntl;
-	struct radeon_state	*config;
-	struct radeon_state	*vgt;
-	struct radeon_state	*draw;
-	struct radeon_state	*vs_constant0;
-	struct radeon_state	*vs_constant1;
-	struct radeon_state	*vs_constant2;
-	struct radeon_state	*vs_constant3;
-	struct radeon_state	*ps_shader;
-	struct radeon_state	*vs_shader;
-	struct radeon_state	*vs_resource0;
-	struct radeon_state	*vs_resource1;
+	struct radeon_state	rasterizer;
+	struct radeon_state	dsa;
+	struct radeon_state	blend;
+	struct radeon_state	cb_cntl;
+	struct radeon_state	vgt;
+	struct radeon_state	draw;
+	struct radeon_state	vs_constant0;
+	struct radeon_state	vs_constant1;
+	struct radeon_state	vs_constant2;
+	struct radeon_state	vs_constant3;
+	struct radeon_state	ps_shader;
+	struct radeon_state	vs_shader;
+	struct radeon_state	vs_resource0;
+	struct radeon_state	vs_resource1;
 };
 
 static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600_blit_states *bstates)
@@ -190,11 +189,8 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	memcpy(bo->data, vbo, 128);
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
-	if (rstate == NULL) {
-		radeon_bo_decref(rscreen->rw, bo);
-		return -ENOMEM;
-	}
+	rstate = &bstates->vs_resource0;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 0, R600_SHADER_VS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -210,15 +206,12 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
+		radeon_state_fini(rstate);
 		return -ENOMEM;
 	}
-	bstates->vs_resource0 = rstate;
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
-	if (rstate == NULL) {
-		return -ENOMEM;
-	}
+	rstate = &bstates->vs_resource1;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, 1, R600_SHADER_VS);
 	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD0] = 0x00000010;
 	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD1] = 0x00000070;
 	rstate->states[R600_VS_RESOURCE__RESOURCE160_WORD2] = 0x02302000;
@@ -230,17 +223,15 @@ static int r600_blit_state_vs_resources(struct r600_screen *rscreen, struct r600
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
+		radeon_state_fini(rstate);
 		return -ENOMEM;
 	}
-	bstates->vs_resource1 = rstate;
 
 	return 0;
 }
 
-static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscreen)
+static void r600_blit_state_vs_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
 	struct radeon_bo *bo;
 	u32 shader_bc_r600[] = {
 		0x00000004, 0x81000400,
@@ -282,11 +273,11 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	/* simple shader */
 	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
 	if (bo == NULL) {
-		return NULL;
+		return;
 	}
 	if (radeon_bo_map(rscreen->rw, bo)) {
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	switch (rscreen->chip_class) {
 	case R600:
@@ -299,15 +290,11 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 		R600_ERR("unsupported chip family\n");
 		radeon_bo_unmap(rscreen->rw, bo);
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
-	if (rstate == NULL) {
-		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
-	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -322,16 +309,11 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscreen)
+static void r600_blit_state_ps_shader(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
 	struct radeon_bo *bo;
 	u32 shader_bc_r600[] = {
 		0x00000002, 0xA00C0000,
@@ -354,10 +336,10 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
 	if (bo == NULL) {
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	if (radeon_bo_map(rscreen->rw, bo)) {
-		return NULL;
+		return;
 	}
 	switch (rscreen->chip_class) {
 	case R600:
@@ -370,15 +352,11 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 		R600_ERR("unsupported chip family\n");
 		radeon_bo_unmap(rscreen->rw, bo);
 		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
+		return;
 	}
 	radeon_bo_unmap(rscreen->rw, bo);
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-	if (rstate == NULL) {
-		radeon_bo_decref(rscreen->rw, bo);
-		return NULL;
-	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -392,19 +370,12 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
+static void r600_blit_state_vgt(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_VGT, 0); if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_VGT, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -413,20 +384,12 @@ static struct radeon_state *r600_blit_state_vgt(struct r600_screen *rscreen)
 	rstate->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
 	rstate->states[R600_VGT__VGT_PRIMITIVE_TYPE] = 0x00000005;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
+static void r600_blit_state_draw(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_DRAW, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DRAW, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -434,22 +397,13 @@ static struct radeon_state *r600_blit_state_draw(struct r600_screen *rscreen)
 	rstate->states[R600_DRAW__VGT_DRAW_INITIATOR] = 0x00000002;
 	rstate->states[R600_DRAW__VGT_NUM_INDICES] = 0x00000004;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscreen,
-					unsigned id, float c0, float c1,
-					float c2, float c3)
+static void r600_blit_state_vs_constant(struct r600_screen *rscreen, struct radeon_state *rstate,
+					unsigned id, float c0, float c1, float c2, float c3)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CONSTANT, id, R600_SHADER_VS);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -459,20 +413,12 @@ static struct radeon_state *r600_blit_state_vs_constant(struct r600_screen *rscr
 	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256] = fui(c2);
 	rstate->states[R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256] = fui(c3);
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscreen)
+static void r600_blit_state_rasterizer(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_RASTERIZER, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -488,20 +434,12 @@ static struct radeon_state *r600_blit_state_rasterizer(struct r600_screen *rscre
 	rstate->states[R600_RASTERIZER__PA_SU_SC_MODE_CNTL] = 0x00080004;
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
+static void r600_blit_state_dsa(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_DSA, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -512,43 +450,18 @@ static struct radeon_state *r600_blit_state_dsa(struct r600_screen *rscreen)
 	rstate->states[R600_DSA__DB_RENDER_OVERRIDE] = 0x0000002A;
 	rstate->states[R600_DSA__DB_SHADER_CONTROL] = 0x00000210;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
+static void r600_blit_state_blend(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
-	if (rstate == NULL)
-		return NULL;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
-
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
+static void r600_blit_state_cb_cntl(struct r600_screen *rscreen, struct radeon_state *rstate)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB_CNTL, 0);
-	if (rstate == NULL)
-		return NULL;
-
-	/* set states (most default value are 0 and struct already
-	 * initialized to 0, thus avoid resetting them)
-	 */
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_CONTROL] = 0x01000000;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
@@ -556,113 +469,42 @@ static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = 0x0000000F;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x0000000F;
 	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_states *bstates)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	int r;
 
-	bstates->ps_shader = r600_blit_state_ps_shader(rscreen);
-	if (bstates->ps_shader == NULL) {
-		R600_ERR("failed creating ps_shader state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_shader = r600_blit_state_vs_shader(rscreen);
-	if (bstates->vs_shader == NULL) {
-		R600_ERR("failed creating vs_shader state\n");
-		return -ENOMEM;
-	}
-	bstates->vgt = r600_blit_state_vgt(rscreen);
-	if (bstates->vgt == NULL) {
-		R600_ERR("failed creating vgt state\n");
-		return -ENOMEM;
-	}
-	bstates->draw = r600_blit_state_draw(rscreen);
-	if (bstates->draw == NULL) {
-		R600_ERR("failed creating draw state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant0 = r600_blit_state_vs_constant(rscreen, 0, 1.0, 0.0, 0.0, 0.0);
-	if (bstates->vs_constant0 == NULL) {
-		R600_ERR("failed creating vs_constant0 state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant1 = r600_blit_state_vs_constant(rscreen, 1, 0.0, 1.0, 0.0, 0.0);
-	if (bstates->vs_constant1 == NULL) {
-		R600_ERR("failed creating vs_constant1 state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant2 = r600_blit_state_vs_constant(rscreen, 2, 0.0, 0.0, -0.00199900055, 0.0);
-	if (bstates->vs_constant2 == NULL) {
-		R600_ERR("failed creating vs_constant2 state\n");
-		return -ENOMEM;
-	}
-	bstates->vs_constant3 = r600_blit_state_vs_constant(rscreen, 3, 0.0, 0.0, -0.99900049, 1.0);
-	if (bstates->vs_constant3 == NULL) {
-		R600_ERR("failed creating vs_constant3 state\n");
-		return -ENOMEM;
-	}
-	bstates->rasterizer = r600_blit_state_rasterizer(rscreen);
-	if (bstates->rasterizer == NULL) {
-		R600_ERR("failed creating rasterizer state\n");
-		return -ENOMEM;
-	}
-	bstates->dsa = r600_blit_state_dsa(rscreen);
-	if (bstates->dsa == NULL) {
-		R600_ERR("failed creating dsa state\n");
-		return -ENOMEM;
-	}
-	bstates->blend = r600_blit_state_blend(rscreen);
-	if (bstates->blend == NULL) {
-		R600_ERR("failed creating blend state\n");
-		return -ENOMEM;
-	}
-	bstates->cb_cntl = r600_blit_state_cb_cntl(rscreen);
-	if (bstates->cb_cntl == NULL) {
-		R600_ERR("failed creating cb_cntl state\n");
-		return -ENOMEM;
-	}
-	r = r600_blit_state_vs_resources(rscreen, bstates);
-	if (r) {
-		R600_ERR("failed creating vs_resource state\n");
-		return r;
-	}
-	bstates->config = radeon_state_incref(rctx->hw_states.config);
+	r600_blit_state_ps_shader(rscreen, &bstates->ps_shader);
+	r600_blit_state_vs_shader(rscreen, &bstates->vs_shader);
+	r600_blit_state_vgt(rscreen, &bstates->vgt);
+	r600_blit_state_draw(rscreen, &bstates->draw);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant0, 0, 1.0, 0.0, 0.0, 0.0);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant1, 1, 0.0, 1.0, 0.0, 0.0);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant2, 2, 0.0, 0.0, -0.00199900055, 0.0);
+	r600_blit_state_vs_constant(rscreen, &bstates->vs_constant3, 3, 0.0, 0.0, -0.99900049, 1.0);
+	r600_blit_state_rasterizer(rscreen, &bstates->rasterizer);
+	r600_blit_state_dsa(rscreen, &bstates->dsa);
+	r600_blit_state_blend(rscreen, &bstates->blend);
+	r600_blit_state_cb_cntl(rscreen, &bstates->cb_cntl);
+	r600_blit_state_vs_resources(rscreen, bstates);
 	return 0;
 }
 
 static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_states *bstates)
 {
-	radeon_state_decref(bstates->rasterizer);
-	radeon_state_decref(bstates->dsa);
-	radeon_state_decref(bstates->blend);
-	radeon_state_decref(bstates->cb_cntl);
-	radeon_state_decref(bstates->config);
-	radeon_state_decref(bstates->vgt);
-	radeon_state_decref(bstates->draw);
-	radeon_state_decref(bstates->vs_constant0);
-	radeon_state_decref(bstates->vs_constant1);
-	radeon_state_decref(bstates->vs_constant2);
-	radeon_state_decref(bstates->vs_constant3);
-	radeon_state_decref(bstates->ps_shader);
-	radeon_state_decref(bstates->vs_shader);
-	radeon_state_decref(bstates->vs_resource0);
-	radeon_state_decref(bstates->vs_resource1);
+	radeon_state_fini(&bstates->ps_shader);
+	radeon_state_fini(&bstates->vs_shader);
+	radeon_state_fini(&bstates->vs_resource0);
+	radeon_state_fini(&bstates->vs_resource1);
 }
 
 int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_draw *draw = NULL;
+	struct radeon_draw draw;
 	struct r600_blit_states bstates;
 	int r;
 
@@ -687,108 +529,51 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
 	if (r) {
 		return r;
 	}
-	bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
-	bstates.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
+	bstates.dsa.states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
+	bstates.cb_cntl.states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
 	/* force rebuild */
-	bstates.dsa->cpm4 = bstates.cb_cntl->cpm4 = 0;
-	if (radeon_state_pm4(bstates.dsa)) {
+	bstates.dsa.cpm4 = bstates.cb_cntl.cpm4 = 0;
+	if (radeon_state_pm4(&bstates.dsa)) {
 		goto out;
 	}
-	if (radeon_state_pm4(bstates.cb_cntl)) {
+	if (radeon_state_pm4(&bstates.cb_cntl)) {
 		goto out;
 	}
 
-	draw = radeon_draw(rscreen->rw);
-	if (draw == NULL) {
+	r = radeon_draw_init(&draw, rscreen->rw);
+	if (r) {
 		R600_ERR("failed creating draw for uncompressing textures\n");
 		goto out;
 	}
 
-	r = radeon_draw_set(draw, bstates.vs_shader);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.ps_shader);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.rasterizer);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.dsa);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.blend);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.cb_cntl);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.config);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vgt);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.draw);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_resource0);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_resource1);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant0);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant1);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant2);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, bstates.vs_constant3);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->viewport[level]);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->scissor[level]);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->cb[0][level]);
-	if (r) {
-		goto out;
-	}
-	r = radeon_draw_set(draw, rtexture->db[level]);
-	if (r) {
-		goto out;
-	}
+	radeon_draw_bind(&draw, &bstates.vs_shader);
+	radeon_draw_bind(&draw, &bstates.ps_shader);
+	radeon_draw_bind(&draw, &bstates.rasterizer);
+	radeon_draw_bind(&draw, &bstates.dsa);
+	radeon_draw_bind(&draw, &bstates.blend);
+	radeon_draw_bind(&draw, &bstates.cb_cntl);
+	radeon_draw_bind(&draw, &rctx->config);
+	radeon_draw_bind(&draw, &bstates.vgt);
+	radeon_draw_bind(&draw, &bstates.draw);
+	radeon_draw_bind(&draw, &bstates.vs_resource0);
+	radeon_draw_bind(&draw, &bstates.vs_resource1);
+	radeon_draw_bind(&draw, &bstates.vs_constant0);
+	radeon_draw_bind(&draw, &bstates.vs_constant1);
+	radeon_draw_bind(&draw, &bstates.vs_constant2);
+	radeon_draw_bind(&draw, &bstates.vs_constant3);
+	radeon_draw_bind(&draw, &rtexture->viewport[level]);
+	radeon_draw_bind(&draw, &rtexture->scissor[level]);
+	radeon_draw_bind(&draw, &rtexture->cb[0][level]);
+	radeon_draw_bind(&draw, &rtexture->db[level]);
 
 	/* suspend queries */
 	r600_queries_suspend(ctx);
 
 	/* schedule draw*/
-	r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+	r = radeon_ctx_set_draw(&rctx->ctx, &draw);
 	if (r == -EBUSY) {
 		r600_flush(ctx, 0, NULL);
-		r = radeon_ctx_set_draw_new(rctx->ctx, draw);
+		r = radeon_ctx_set_draw(&rctx->ctx, &draw);
 	}
 	if (r) {
 		goto out;
diff --git a/src/gallium/drivers/r600/r600_context.c b/src/gallium/drivers/r600/r600_context.c
index db170122dd..95e9b6a8ed 100644
--- a/src/gallium/drivers/r600/r600_context.c
+++ b/src/gallium/drivers/r600/r600_context.c
@@ -46,35 +46,31 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
 			struct pipe_fence_handle **fence)
 {
 	struct r600_context *rctx = r600_context(ctx);
-	struct r600_screen *rscreen = rctx->screen;
 	struct r600_query *rquery;
 	static int dc = 0;
 	char dname[256];
 
 	/* suspend queries */
 	r600_queries_suspend(ctx);
-	if (radeon_ctx_pm4(rctx->ctx))
-		goto out;
 	/* FIXME dumping should be removed once shader support instructions
 	 * without throwing bad code
 	 */
-	if (!rctx->ctx->cpm4)
+	if (!rctx->ctx.cdwords)
 		goto out;
 	sprintf(dname, "gallium-%08d.bof", dc);
 	if (dc < 2) {
-		radeon_ctx_dump_bof(rctx->ctx, dname);
+		radeon_ctx_dump_bof(&rctx->ctx, dname);
 		R600_ERR("dumped %s\n", dname);
 	}
 #if 1
-	radeon_ctx_submit(rctx->ctx);
+	radeon_ctx_submit(&rctx->ctx);
 #endif
 	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
 		rquery->flushed = true;
 	}
 	dc++;
 out:
-	rctx->ctx = radeon_ctx_decref(rctx->ctx);
-	rctx->ctx = radeon_ctx(rscreen->rw);
+	radeon_ctx_clear(&rctx->ctx);
 	/* resume queries */
 	r600_queries_resume(ctx);
 }
@@ -218,9 +214,9 @@ static void r600_init_config(struct r600_context *rctx)
 		num_es_stack_entries = 0;
 		break;
 	}
-	rctx->hw_states.config = radeon_state(rctx->rw, R600_STATE_CONFIG, 0);
+	radeon_state_init(&rctx->config, rctx->rw, R600_STATE_CONFIG, 0, 0);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] = 0x00000000;
 	switch (family) {
 	case CHIP_RV610:
 	case CHIP_RV620:
@@ -229,75 +225,75 @@ static void r600_init_config(struct r600_context *rctx)
 	case CHIP_RV710:
 		break;
 	default:
-		rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
+		rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VC_ENABLE(1);
 		break;
 	}
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_DX9_CONSTS(1);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ALU_INST_PREFER_VECTOR(1);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_PS_PRIO(ps_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_VS_PRIO(vs_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_GS_PRIO(gs_prio);
+	rctx->config.states[R600_CONFIG__SQ_CONFIG] |= S_008C00_ES_PRIO(es_prio);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1] |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
+	rctx->config.states[R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2] |= S_008C08_NUM_GS_GPRS(num_es_gprs);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] = 0;
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
+	rctx->config.states[R600_CONFIG__SQ_THREAD_RESOURCE_MGMT] |= S_008C0C_NUM_ES_THREADS(num_es_threads);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] = 0;
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1] |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
-	rctx->hw_states.config->states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] = 0;
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
+	rctx->config.states[R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2] |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
 
-	rctx->hw_states.config->states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
-	rctx->hw_states.config->states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
-	rctx->hw_states.config->states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__DB_DEBUG] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
-	rctx->hw_states.config->states[R600_CONFIG__SX_MISC] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
-	rctx->hw_states.config->states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
-	rctx->hw_states.config->states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
-	radeon_state_pm4(rctx->hw_states.config);
+	rctx->config.states[R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ] = 0x00004000;
+	rctx->config.states[R600_CONFIG__TA_CNTL_AUX] = 0x07000002;
+	rctx->config.states[R600_CONFIG__VC_ENHANCE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__DB_DEBUG] = 0x00000000;
+	rctx->config.states[R600_CONFIG__DB_WATERMARKS] = 0x00420204;
+	rctx->config.states[R600_CONFIG__SX_MISC] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SPI_THREAD_GROUPING] = 0x00000001;
+	rctx->config.states[R600_CONFIG__CB_SHADER_CONTROL] = 0x00000003;
+	rctx->config.states[R600_CONFIG__SQ_ESGS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GSVS_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_FBUF_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_REDUC_RING_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__SQ_GS_VERT_ITEMSIZE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_OUTPUT_PATH_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_HOS_REUSE_DEPTH] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_PRIM_TYPE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_FIRST_DECR] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_DECR] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_GS_MODE] = 0x00000000;
+	rctx->config.states[R600_CONFIG__PA_SC_MODE_CNTL] = 0x00514000;
+	rctx->config.states[R600_CONFIG__VGT_STRMOUT_EN] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_REUSE_OFF] = 0x00000001;
+	rctx->config.states[R600_CONFIG__VGT_VTX_CNT_EN] = 0x00000000;
+	rctx->config.states[R600_CONFIG__VGT_STRMOUT_BUFFER_EN] = 0x00000000;
+	radeon_state_pm4(&rctx->config);
 }
 
 struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
@@ -331,7 +327,7 @@ struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
 
 	r600_init_config(rctx);
 
-	rctx->ctx = radeon_ctx(rscreen->rw);
-	rctx->draw = radeon_draw(rscreen->rw);
+	radeon_ctx_init(&rctx->ctx, rscreen->rw);
+	radeon_draw_init(&rctx->draw, rscreen->rw);
 	return &rctx->context;
 }
diff --git a/src/gallium/drivers/r600/r600_context.h b/src/gallium/drivers/r600/r600_context.h
index e9495f0017..a48dca4915 100644
--- a/src/gallium/drivers/r600/r600_context.h
+++ b/src/gallium/drivers/r600/r600_context.h
@@ -53,7 +53,7 @@ struct r600_query {
 	unsigned				buffer_size;
 	/* linked list of queries */
 	struct list_head			list;
-	struct radeon_state			*rstate;
+	struct radeon_state			rstate;
 };
 
 /* XXX move this to a more appropriate place */
@@ -99,7 +99,7 @@ struct r600_context_state {
 	union pipe_states		state;
 	unsigned			refcount;
 	unsigned			type;
-	struct radeon_state		*rstate;
+	struct radeon_state		rstate;
 	struct r600_shader		shader;
 	struct radeon_bo		*bo;
 };
@@ -112,29 +112,24 @@ struct r600_vertex_element
 };
 
 struct r600_context_hw_states {
-	struct radeon_state	*rasterizer;
-	struct radeon_state	*scissor;
-	struct radeon_state	*dsa;
-	struct radeon_state	*blend;
-	struct radeon_state	*viewport;
-	struct radeon_state	*cb[8];
-	struct radeon_state	*config;
-	struct radeon_state	*cb_cntl;
-	struct radeon_state	*db;
-	struct radeon_state	*ucp;
-	unsigned		ps_nresource;
-	unsigned		ps_nsampler;
-	struct radeon_state	*ps_resource[160];
-	struct radeon_state	*ps_sampler[16];
+	struct radeon_state	rasterizer;
+	struct radeon_state	scissor;
+	struct radeon_state	dsa;
+	struct radeon_state	cb_cntl;
 };
 
 struct r600_context {
 	struct pipe_context		context;
 	struct r600_screen		*screen;
 	struct radeon			*rw;
-	struct radeon_ctx		*ctx;
+	struct radeon_ctx		ctx;
 	struct blitter_context		*blitter;
-	struct radeon_draw		*draw;
+	struct radeon_draw		draw;
+	struct radeon_state		config;
+	/* FIXME get rid of those vs_resource,vs/ps_constant */
+	struct radeon_state		vs_resource[160];
+	struct radeon_state		vs_constant[256];
+	struct radeon_state		ps_constant[256];
 	/* hw states */
 	struct r600_context_hw_states	hw_states;
 	/* pipe states */
diff --git a/src/gallium/drivers/r600/r600_draw.c b/src/gallium/drivers/r600/r600_draw.c
index 88f93bca7b..bddc81e50a 100644
--- a/src/gallium/drivers/r600/r600_draw.c
+++ b/src/gallium/drivers/r600/r600_draw.c
@@ -31,6 +31,7 @@
 #include <util/u_math.h>
 #include <util/u_inlines.h>
 #include <util/u_memory.h>
+#include "radeon.h"
 #include "r600_screen.h"
 #include "r600_context.h"
 #include "r600_resource.h"
@@ -38,8 +39,8 @@
 
 struct r600_draw {
 	struct pipe_context	*ctx;
-	struct radeon_state	*draw;
-	struct radeon_state	*vgt;
+	struct radeon_state	draw;
+	struct radeon_state	vgt;
 	unsigned		mode;
 	unsigned		start;
 	unsigned		count;
@@ -51,6 +52,7 @@ static int r600_draw_common(struct r600_draw *draw)
 {
 	struct r600_context *rctx = r600_context(draw->ctx);
 	struct r600_screen *rscreen = rctx->screen;
+	/* FIXME vs_resource */
 	struct radeon_state *vs_resource;
 	struct r600_resource *rbuffer;
 	unsigned i, j, offset, format, prim;
@@ -81,6 +83,7 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_conv_pipe_prim(draw->mode, &prim);
 	if (r)
 		return r;
+
 	/* rebuild vertex shader if input format changed */
 	r = r600_pipe_shader_update(draw->ctx, rctx->vs_shader);
 	if (r)
@@ -88,22 +91,17 @@ static int r600_draw_common(struct r600_draw *draw)
 	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
 	if (r)
 		return r;
-	r = radeon_draw_set(rctx->draw, rctx->vs_shader->rstate);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->ps_shader->rstate);
-	if (r)
-		return r;
+	radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate);
+	radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate);
 
 	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
+		vs_resource = &rctx->vs_resource[i];
 		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
 		vertex_buffer = &rctx->vertex_buffer[j];
 		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
 		format = r600_translate_colorformat(rctx->vertex_elements->elements[i].src_format);
-		vs_resource = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, i, R600_SHADER_VS);
-		if (vs_resource == NULL)
-			return -ENOMEM;
+		radeon_state_init(vs_resource, rscreen->rw, R600_STATE_RESOURCE, i, R600_SHADER_VS);
 		vs_resource->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
 		vs_resource->nbo = 1;
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD0] = offset;
@@ -116,53 +114,53 @@ static int r600_draw_common(struct r600_draw *draw)
 		vs_resource->states[R600_PS_RESOURCE__RESOURCE0_WORD6] = 0xC0000000;
 		vs_resource->placement[0] = RADEON_GEM_DOMAIN_GTT;
 		vs_resource->placement[1] = RADEON_GEM_DOMAIN_GTT;
-		r = radeon_draw_set_new(rctx->draw, vs_resource);
-		if (r)
+		r = radeon_state_pm4(vs_resource);
+		if (r) {
 			return r;
+		}
+		radeon_draw_bind(&rctx->draw, vs_resource);
 	}
 	/* FIXME start need to change winsys */
-	draw->draw = radeon_state(rscreen->rw, R600_STATE_DRAW, 0);
-	if (draw->draw == NULL)
-		return -ENOMEM;
-	draw->draw->states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
-	draw->draw->states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
+	radeon_state_init(&draw->draw, rscreen->rw, R600_STATE_DRAW, 0, 0);
+	draw->draw.states[R600_DRAW__VGT_NUM_INDICES] = draw->count;
+	draw->draw.states[R600_DRAW__VGT_DRAW_INITIATOR] = vgt_draw_initiator;
 	if (draw->index_buffer) {
 		rbuffer = (struct r600_resource*)draw->index_buffer;
-		draw->draw->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-		draw->draw->placement[0] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw->placement[1] = RADEON_GEM_DOMAIN_GTT;
-		draw->draw->nbo = 1;
+		draw->draw.bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
+		draw->draw.placement[0] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw.placement[1] = RADEON_GEM_DOMAIN_GTT;
+		draw->draw.nbo = 1;
 	}
-	r = radeon_draw_set_new(rctx->draw, draw->draw);
-	if (r)
+	r = radeon_state_pm4(&draw->draw);
+	if (r) {
 		return r;
-	draw->vgt = radeon_state(rscreen->rw, R600_STATE_VGT, 0);
-	if (draw->vgt == NULL)
-		return -ENOMEM;
-	draw->vgt->states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
-	draw->vgt->states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
-	draw->vgt->states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
-	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
-	draw->vgt->states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
-	draw->vgt->states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
-	draw->vgt->states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
-	r = radeon_draw_set_new(rctx->draw, draw->vgt);
-	if (r)
+	}
+	radeon_draw_bind(&rctx->draw, &draw->draw);
+
+	radeon_state_init(&draw->vgt, rscreen->rw, R600_STATE_VGT, 0, 0);
+	draw->vgt.states[R600_VGT__VGT_PRIMITIVE_TYPE] = prim;
+	draw->vgt.states[R600_VGT__VGT_MAX_VTX_INDX] = 0x00FFFFFF;
+	draw->vgt.states[R600_VGT__VGT_MIN_VTX_INDX] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INDX_OFFSET] = draw->start;
+	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_DMA_INDEX_TYPE] = vgt_dma_index_type;
+	draw->vgt.states[R600_VGT__VGT_PRIMITIVEID_EN] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_DMA_NUM_INSTANCES] = 0x00000001;
+	draw->vgt.states[R600_VGT__VGT_MULTI_PRIM_IB_RESET_EN] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_0] = 0x00000000;
+	draw->vgt.states[R600_VGT__VGT_INSTANCE_STEP_RATE_1] = 0x00000000;
+	r = radeon_state_pm4(&draw->vgt);
+	if (r) {
 		return r;
-	/* FIXME */
-	r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+	}
+	radeon_draw_bind(&rctx->draw, &draw->vgt);
+
+	r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 	if (r == -EBUSY) {
 		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw_new(rctx->ctx, rctx->draw);
+		r = radeon_ctx_set_draw(&rctx->ctx, &rctx->draw);
 	}
-	if (r)
-		return r;
-	rctx->draw = radeon_draw_duplicate(rctx->draw);
-	return 0;
+	return r;
 }
 
 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c
index af857101e3..530940ed84 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -31,42 +31,36 @@
 #include "r600_screen.h"
 #include "r600_context.h"
 
-static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
+static void r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rquery->rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_QUERY_BEGIN, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_fini(rstate);
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_BEGIN, 0, 0);
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
+		radeon_state_fini(rstate);
 	}
-	return rstate;
 }
 
-static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
+static void r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rquery->rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_QUERY_END, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_fini(rstate);
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_END, 0, 0);
 	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
 	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
 	rstate->nbo = 1;
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
+		radeon_state_fini(rstate);
 	}
-	return rstate;
 }
 
 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
@@ -137,8 +131,7 @@ static void r600_query_resume(struct pipe_context *ctx, struct r600_query *rquer
 		}
 		r600_query_result(ctx, rquery);
 	}
-	rquery->rstate = radeon_state_decref(rquery->rstate);
-	rquery->rstate = r600_query_begin(rctx, rquery);
+	r600_query_begin(rctx, rquery);
 	rquery->flushed = false;
 }
 
@@ -146,8 +139,7 @@ static void r600_query_suspend(struct pipe_context *ctx, struct r600_query *rque
 {
 	struct r600_context *rctx = r600_context(ctx);
 
-	rquery->rstate = radeon_state_decref(rquery->rstate);
-	rquery->rstate = r600_query_end(rctx, rquery);
+	r600_query_end(rctx, rquery);
 	rquery->num_results += 16;
 }
 
@@ -161,12 +153,12 @@ static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
 	rquery->num_results = 0;
 	rquery->flushed = false;
 	r600_query_resume(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	if (r == -EBUSY) {
 		/* this shouldn't happen */
 		R600_ERR("had to flush while emitting end query\n");
 		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+		r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	}
 }
 
@@ -179,12 +171,12 @@ static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
 	rquery->state &= ~R600_QUERY_STATE_STARTED;
 	rquery->state |= R600_QUERY_STATE_ENDED;
 	r600_query_suspend(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+	r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	if (r == -EBUSY) {
 		/* this shouldn't happen */
 		R600_ERR("had to flush while emitting end query\n");
 		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+		r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 	}
 }
 
@@ -197,12 +189,12 @@ void r600_queries_suspend(struct pipe_context *ctx)
 	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
 		if (rquery->state & R600_QUERY_STATE_STARTED) {
 			r600_query_suspend(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			if (r == -EBUSY) {
 				/* this shouldn't happen */
 				R600_ERR("had to flush while emitting end query\n");
 				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+				r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			}
 		}
 		rquery->state |= R600_QUERY_STATE_SUSPENDED;
@@ -218,12 +210,12 @@ void r600_queries_resume(struct pipe_context *ctx)
 	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
 		if (rquery->state & R600_QUERY_STATE_STARTED) {
 			r600_query_resume(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+			r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			if (r == -EBUSY) {
 				/* this shouldn't happen */
 				R600_ERR("had to flush while emitting end query\n");
 				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
+				r = radeon_ctx_set_query_state(&rctx->ctx, &rquery->rstate);
 			}
 		}
 		rquery->state &= ~R600_QUERY_STATE_SUSPENDED;
diff --git a/src/gallium/drivers/r600/r600_resource.h b/src/gallium/drivers/r600/r600_resource.h
index 8078a83c35..129667ad20 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -56,10 +56,10 @@ struct r600_resource_texture {
 	unsigned			depth;
 	unsigned			dirty;
 	struct radeon_bo		*uncompressed;
-	struct radeon_state		*scissor[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*cb[8][PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*db[PIPE_MAX_TEXTURE_LEVELS];
-	struct radeon_state		*viewport[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		scissor[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		cb[8][PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		db[PIPE_MAX_TEXTURE_LEVELS];
+	struct radeon_state		viewport[PIPE_MAX_TEXTURE_LEVELS];
 };
 
 void r600_init_context_resource_functions(struct r600_context *r600);
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index a26290062a..9af45b7793 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -134,10 +134,9 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	struct radeon_state *state;
 	unsigned i, tmp;
 
-	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
-	if (state == NULL)
-		return -ENOMEM;
+	state = &rpshader->rstate;
+	radeon_state_fini(&rpshader->rstate);
+	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_VS);
 	for (i = 0; i < 10; i++) {
 		state->states[R600_VS_SHADER__SPI_VS_OUT_ID_0 + i] = 0;
 	}
@@ -149,12 +148,11 @@ static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_VS_SHADER__SPI_VS_OUT_CONFIG] = S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2);
 	state->states[R600_VS_SHADER__SQ_PGM_RESOURCES_VS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
 		S_028868_STACK_SIZE(rshader->bc.nstack);
-	rpshader->rstate = state;
-	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->nbo = 2;
-	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rpshader->rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
+	state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->bo[1] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->nbo = 2;
+	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	state->placement[2] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
@@ -168,11 +166,10 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	unsigned i, tmp, exports_ps, num_cout;
 	boolean have_pos = FALSE;
 
+	state = &rpshader->rstate;
 	rasterizer = &rctx->rasterizer->state.rasterizer;
-	rpshader->rstate = radeon_state_decref(rpshader->rstate);
-	state = radeon_state_shader(rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
-	if (state == NULL)
-		return -ENOMEM;
+	radeon_state_fini(state);
+	radeon_state_init(state, rscreen->rw, R600_STATE_SHADER, 0, R600_SHADER_PS);
 	for (i = 0; i < rshader->ninput; i++) {
 		tmp = S_028644_SEMANTIC(i);
 		tmp |= S_028644_SEL_CENTROID(1);
@@ -214,10 +211,9 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
 	state->states[R600_PS_SHADER__SQ_PGM_RESOURCES_PS] = S_028868_NUM_GPRS(rshader->bc.ngpr) |
 		S_028868_STACK_SIZE(rshader->bc.nstack);
 	state->states[R600_PS_SHADER__SQ_PGM_EXPORTS_PS] = exports_ps;
-	rpshader->rstate = state;
-	rpshader->rstate->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
-	rpshader->rstate->nbo = 1;
-	rpshader->rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
+	state->bo[0] = radeon_bo_incref(rscreen->rw, rpshader->bo);
+	state->nbo = 1;
+	state->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	return radeon_state_pm4(state);
 }
 
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index d8f53f2ce8..c6810ffe36 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -34,15 +34,12 @@
 #include "r600d.h"
 #include "r600_state_inlines.h"
 
-static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state);
-static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state);
-static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state);
-static struct radeon_state *r600_sampler(struct r600_context *rctx,
-				const struct pipe_sampler_state *state,
-				unsigned id);
-static struct radeon_state *r600_resource(struct pipe_context *ctx,
-					const struct pipe_sampler_view *view,
-					unsigned id);
+static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state);
+static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
+static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_clip_state *state);
+static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_sampler_state *state, unsigned id);
+static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate, const struct pipe_sampler_view *view, unsigned id);
+
 
 static void *r600_create_blend_state(struct pipe_context *ctx,
 					const struct pipe_blend_state *state)
@@ -96,7 +93,7 @@ static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *c
 	rstate->state.sampler_view.texture = texture;
 	rstate->state.sampler_view.reference.count = 1;
 	rstate->state.sampler_view.context = ctx;
-	rstate->rstate = r600_resource(ctx, &rstate->state.sampler_view, 0);
+	r600_resource(ctx, &rstate->rstate, &rstate->state.sampler_view, 0);
 	return &rstate->state.sampler_view;
 }
 
@@ -241,7 +238,7 @@ static void r600_bind_ps_sampler(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)states[i];
 		rctx->ps_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_PS);
 		}
 	}
 	rctx->ps_nsampler = count;
@@ -261,7 +258,7 @@ static void r600_bind_vs_sampler(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)states[i];
 		rctx->vs_sampler[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_SAMPLER, i, R600_SHADER_VS);
 		}
 	}
 	rctx->vs_nsampler = count;
@@ -301,7 +298,7 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 	struct r600_context *rctx = r600_context(ctx);
 	unsigned nconstant = 0, i, type, shader_class;
-	struct radeon_state *rstate;
+	struct radeon_state *rstate, *rstates;
 	struct pipe_transfer *transfer;
 	u32 *ptr;
 
@@ -310,9 +307,11 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 	switch (shader) {
 	case PIPE_SHADER_VERTEX:
 		shader_class = R600_SHADER_VS;
+		rstates = rctx->vs_constant;
 		break;
 	case PIPE_SHADER_FRAGMENT:
 		shader_class = R600_SHADER_PS;
+		rstates = rctx->ps_constant;
 		break;
 	default:
 		R600_ERR("unsupported %d\n", shader);
@@ -324,17 +323,15 @@ static void r600_set_constant_buffer(struct pipe_context *ctx,
 		if (ptr == NULL)
 			return;
 		for (i = 0; i < nconstant; i++) {
-			rstate = radeon_state_shader(rscreen->rw, type, i, shader_class);
-			if (rstate == NULL)
-				return;
+			rstate = &rstates[i];
+			radeon_state_init(rstate, rscreen->rw, type, i, shader_class);
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0] = ptr[i * 4 + 0];
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0] = ptr[i * 4 + 1];
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0] = ptr[i * 4 + 2];
 			rstate->states[R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0] = ptr[i * 4 + 3];
 			if (radeon_state_pm4(rstate))
 				return;
-			if (radeon_draw_set_new(rctx->draw, rstate))
-				return;
+			radeon_draw_bind(&rctx->draw, rstate);
 		}
 		pipe_buffer_unmap(ctx, buffer, transfer);
 	}
@@ -355,7 +352,7 @@ static void r600_set_ps_sampler_view(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)views[i];
 		rctx->ps_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_PS);
 		}
 	}
 	rctx->ps_nsampler_view = count;
@@ -376,7 +373,7 @@ static void r600_set_vs_sampler_view(struct pipe_context *ctx,
 		rstate = (struct r600_context_state *)views[i];
 		rctx->vs_sampler_view[i] = r600_context_state_incref(rstate);
 		if (rstate) {
-			radeon_state_convert(rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
+			radeon_state_convert(&rstate->rstate, R600_STATE_RESOURCE, i, R600_SHADER_VS);
 		}
 	}
 	rctx->vs_nsampler_view = count;
@@ -564,7 +561,7 @@ struct r600_context_state *r600_context_state_decref(struct r600_context_state *
 		R600_ERR("invalid type %d\n", rstate->type);
 		return NULL;
 	}
-	radeon_state_decref(rstate->rstate);
+	radeon_state_fini(&rstate->rstate);
 	FREE(rstate);
 	return NULL;
 }
@@ -597,7 +594,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_viewport_type:
 		rstate->state.viewport = (*states).viewport;
-		rstate->rstate = r600_viewport(rctx, &rstate->state.viewport);
+		r600_viewport(rctx, &rstate->rstate, &rstate->state.viewport);
 		break;
 	case pipe_depth_type:
 		rstate->state.depth = (*states).depth;
@@ -613,7 +610,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_clip_type:
 		rstate->state.clip = (*states).clip;
-		rstate->rstate = r600_ucp(rctx, &rstate->state.clip);
+		r600_ucp(rctx, &rstate->rstate, &rstate->state.clip);
 		break;
 	case pipe_stencil_type:
 		rstate->state.stencil = (*states).stencil;
@@ -626,7 +623,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_blend_type:
 		rstate->state.blend = (*states).blend;
-		rstate->rstate = r600_blend(rctx, &rstate->state.blend);
+		r600_blend(rctx, &rstate->rstate, &rstate->state.blend);
 		break;
 	case pipe_stencil_ref_type:
 		rstate->state.stencil_ref = (*states).stencil_ref;
@@ -641,7 +638,7 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 		break;
 	case pipe_sampler_type:
 		rstate->state.sampler = (*states).sampler;
-		rstate->rstate = r600_sampler(rctx, &rstate->state.sampler, 0);
+		r600_sampler(rctx, &rstate->rstate, &rstate->state.sampler, 0);
 		break;
 	default:
 		R600_ERR("invalid type %d\n", rstate->type);
@@ -651,15 +648,12 @@ struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigne
 	return rstate;
 }
 
-static struct radeon_state *r600_blend(struct r600_context *rctx, const struct pipe_blend_state *state)
+static void r600_blend(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_blend_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	int i;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_BLEND, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_BLEND, 0, 0);
 	rstate->states[R600_BLEND__CB_BLEND_RED] = fui(rctx->blend_color.color[0]);
 	rstate->states[R600_BLEND__CB_BLEND_GREEN] = fui(rctx->blend_color.color[1]);
 	rstate->states[R600_BLEND__CB_BLEND_BLUE] = fui(rctx->blend_color.color[2]);
@@ -703,21 +697,15 @@ static struct radeon_state *r600_blend(struct r600_context *rctx, const struct p
 			rstate->states[R600_BLEND__CB_BLEND_CONTROL] = bc;
 	}
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pipe_clip_state *state)
+static void r600_ucp(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_clip_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_UCP, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_UCP, 0, 0);
 
 	for (int i = 0; i < state->nr; i++) {
 		rstate->states[i * 4 + 0] = fui(state->ucp[i][0]);
@@ -725,118 +713,15 @@ static struct radeon_state *r600_ucp(struct r600_context *rctx, const struct pip
 		rstate->states[i * 4 + 2] = fui(state->ucp[i][2]);
 		rstate->states[i * 4 + 3] = fui(state->ucp[i][3]);
 	}
-	return rstate;
-}
-
-static struct radeon_state *r600_cb(struct r600_context *rctx, int cb)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
-	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level = state->cbufs[cb]->level;
-	unsigned pitch, slice;
-	unsigned color_info;
-	unsigned format, swap, ntype;
-	const struct util_format_description *desc;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
-	if (rstate == NULL)
-		return NULL;
-	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
-	rbuffer = &rtex->resource;
-	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->bo[2] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
-	rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
-	rstate->nbo = 3;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->cbufs[cb]->height / 64 - 1;
-
-	ntype = 0;
-	desc = util_format_description(rtex->resource.base.b.format);
-	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-		ntype = V_0280A0_NUMBER_SRGB;
-
-	format = r600_translate_colorformat(rtex->resource.base.b.format);
-	swap = r600_translate_colorswap(rtex->resource.base.b.format);
-
-	color_info = S_0280A0_FORMAT(format) |
-		S_0280A0_COMP_SWAP(swap) |
-		S_0280A0_BLEND_CLAMP(1) |
-		S_0280A0_SOURCE_FORMAT(1) |
-		S_0280A0_NUMBER_TYPE(ntype);
-
-	rstate->states[R600_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
-	rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
-						S_028060_SLICE_TILE_MAX(slice);
-	rstate->states[R600_CB0__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_FRAG] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_TILE] = 0x00000000;
-	rstate->states[R600_CB0__CB_COLOR0_MASK] = 0x00000000;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
-}
-
-static struct radeon_state *r600_db(struct r600_context *rctx)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
-	const struct pipe_framebuffer_state *state = &rctx->framebuffer->state.framebuffer;
-	unsigned level;
-	unsigned pitch, slice, format;
-
-	if (state->zsbuf == NULL)
-		return NULL;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
-	if (rstate == NULL)
-		return NULL;
-
-	rtex = (struct r600_resource_texture*)state->zsbuf->texture;
-	rtex->tilled = 1;
-	rtex->array_mode = 2;
-	rtex->tile_type = 1;
-	rtex->depth = 1;
-	rbuffer = &rtex->resource;
-
-	rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-	level = state->zsbuf->level;
-	pitch = (rtex->pitch[level] / rtex->bpt) / 8 - 1;
-	slice = (rtex->pitch[level] / rtex->bpt) * state->zsbuf->height / 64 - 1;
-	format = r600_translate_dbformat(state->zsbuf->texture->format);
-	rstate->states[R600_DB__DB_DEPTH_BASE] = state->zsbuf->offset >> 8;
-	rstate->states[R600_DB__DB_DEPTH_INFO] = S_028010_ARRAY_MODE(rtex->array_mode) |
-					S_028010_FORMAT(format);
-	rstate->states[R600_DB__DB_DEPTH_VIEW] = 0x00000000;
-	rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (state->zsbuf->height / 8) -1;
-	rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
-						S_028000_SLICE_TILE_MAX(slice);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
+static void r600_rasterizer(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_rasterizer_state *state = &rctx->rasterizer->state.rasterizer;
 	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	const struct pipe_clip_state *clip = NULL;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	float offset_units = 0, offset_scale = 0;
 	char depth = 0;
 	unsigned offset_db_fmt_cntl = 0;
@@ -865,7 +750,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 			break;
 		default:
 			R600_ERR("unsupported %d\n", fb->zsbuf->texture->format);
-			return NULL;
+			return;
 		}
 	}
 	offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
@@ -874,9 +759,7 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 		prov_vtx = 0;
 
 	rctx->flat_shade = state->flatshade;
-	rstate = radeon_state(rscreen->rw, R600_STATE_RASTERIZER, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RASTERIZER, 0, 0);
 	rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] = 0x00000001;
 	if (state->sprite_coord_enable) {
 		rstate->states[R600_RASTERIZER__SPI_INTERP_CONTROL_0] |=
@@ -926,19 +809,14 @@ static struct radeon_state *r600_rasterizer(struct r600_context *rctx)
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET] = fui(offset_units);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE] = fui(offset_scale);
 	rstate->states[R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET] = fui(offset_units);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_scissor(struct r600_context *rctx)
+static void r600_scissor(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_scissor_state *state = &rctx->scissor->state.scissor;
 	const struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	unsigned minx, maxx, miny, maxy;
 	u32 tl, br;
 
@@ -955,9 +833,7 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	}
 	tl = S_028240_TL_X(minx) | S_028240_TL_Y(miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
 	br = S_028244_BR_X(maxx) | S_028244_BR_Y(maxy);
-	rstate = radeon_state(rscreen->rw, R600_STATE_SCISSOR, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_OFFSET] = 0x00000000;
@@ -977,21 +853,14 @@ static struct radeon_state *r600_scissor(struct r600_context *rctx)
 	rstate->states[R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR] = br;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL] = tl;
 	rstate->states[R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR] = br;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_viewport(struct r600_context *rctx, const struct pipe_viewport_state *state)
+static void r600_viewport(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_VIEWPORT, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMIN_0] = 0x00000000;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui(state->scale[0]);
@@ -1001,14 +870,10 @@ static struct radeon_state *r600_viewport(struct r600_context *rctx, const struc
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui(state->translate[1]);
 	rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = fui(state->translate[2]);
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_dsa(struct r600_context *rctx)
+static void r600_dsa(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	const struct pipe_depth_stencil_alpha_state *state = &rctx->dsa->state.dsa;
 	const struct pipe_stencil_ref *stencil_ref = &rctx->stencil_ref->state.stencil_ref;
@@ -1016,15 +881,12 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 	unsigned stencil_ref_mask, stencil_ref_mask_bf;
 	struct r600_shader *rshader;
-	struct radeon_state *rstate;
 	int i;
 
 	if (rctx->ps_shader == NULL) {
-		return NULL;
+		return;
 	}
-	rstate = radeon_state(rscreen->rw, R600_STATE_DSA, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DSA, 0, 0);
 
 	db_shader_control = 0x210;
 	rshader = &rctx->ps_shader->shader;
@@ -1087,11 +949,7 @@ static struct radeon_state *r600_dsa(struct r600_context *rctx)
 	rstate->states[R600_DSA__DB_SRESULTS_COMPARE_STATE1] = 0x00000000;
 	rstate->states[R600_DSA__DB_PRELOAD_CONTROL] = 0x00000000;
 	rstate->states[R600_DSA__DB_ALPHA_TO_MASK] = 0x0000AA00;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 static inline unsigned r600_tex_wrap(unsigned wrap)
@@ -1169,16 +1027,12 @@ static INLINE u32 S_FIXED(float value, u32 frac_bits)
 	return value * (1 << frac_bits);
 }
 
-static struct radeon_state *r600_sampler(struct r600_context *rctx,
-				const struct pipe_sampler_state *state,
-				unsigned id)
+static void r600_sampler(struct r600_context *rctx, struct radeon_state *rstate,
+			const struct pipe_sampler_state *state, unsigned id)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SAMPLER, id, R600_SHADER_PS);
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0] =
 			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
@@ -1193,11 +1047,7 @@ static struct radeon_state *r600_sampler(struct r600_context *rctx,
 			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 			S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 	rstate->states[R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0] = S_03C008_TYPE(1);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 static inline unsigned r600_tex_swizzle(unsigned swizzle)
@@ -1248,21 +1098,20 @@ static inline unsigned r600_tex_dim(unsigned dim)
 	}
 }
 
-static struct radeon_state *r600_resource(struct pipe_context *ctx,
-					const struct pipe_sampler_view *view,
-					unsigned id)
+static void r600_resource(struct pipe_context *ctx, struct radeon_state *rstate,
+			const struct pipe_sampler_view *view, unsigned id)
 {
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_screen *rscreen = rctx->screen;
 	const struct util_format_description *desc;
 	struct r600_resource_texture *tmp;
 	struct r600_resource *rbuffer;
-	struct radeon_state *rstate;
 	unsigned format;
 	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
 	int r;
 
+	rstate->cpm4 = 0;
 	swizzle[0] = view->swizzle_r;
 	swizzle[1] = view->swizzle_g;
 	swizzle[2] = view->swizzle_b;
@@ -1270,23 +1119,21 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 	format = r600_translate_texformat(view->texture->format,
 					  swizzle,
 					  &word4, &yuv_format);
-	if (format == ~0)
-		return NULL;
+	if (format == ~0) {
+		return;
+	}
 	desc = util_format_description(view->texture->format);
 	if (desc == NULL) {
 		R600_ERR("unknow format %d\n", view->texture->format);
-		return NULL;
-	}
-	rstate = radeon_state_shader(rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
-	if (rstate == NULL) {
-		return NULL;
+		return;
 	}
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_RESOURCE, id, R600_SHADER_PS);
 	tmp = (struct r600_resource_texture*)view->texture;
 	rbuffer = &tmp->resource;
 	if (tmp->depth) {
 		r = r600_texture_from_depth(ctx, tmp, view->first_level);
 		if (r) {
-			return NULL;
+			return;
 		}
 		rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
 		rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
@@ -1302,7 +1149,7 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 
 	pitch = (tmp->pitch[0] / tmp->bpt);
 	pitch = (pitch + 0x7) & ~0x7;
-	
+
 	/* FIXME properly handle first level != 0 */
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
 			S_038000_DIM(r600_tex_dim(view->texture->target)) |
@@ -1328,17 +1175,12 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
 			S_038014_LAST_ARRAY(0);
 	rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD6] =
 			S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE);
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
+static void r600_cb_cntl(struct r600_context *rctx, struct radeon_state *rstate)
 {
 	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate;
 	const struct pipe_blend_state *pbs = &rctx->blend->state.blend;
 	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
 	uint32_t color_control, target_mask, shader_mask;
@@ -1373,7 +1215,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 			target_mask |= (pbs->rt[0].colormask << (4 * i));
 		}
 	}
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB_CNTL, 0);
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB_CNTL, 0, 0);
 	rstate->states[R600_CB_CNTL__CB_SHADER_MASK] = shader_mask;
 	rstate->states[R600_CB_CNTL__CB_TARGET_MASK] = target_mask;
 	rstate->states[R600_CB_CNTL__CB_COLOR_CONTROL] = color_control;
@@ -1385,11 +1227,7 @@ static struct radeon_state *r600_cb_cntl(struct r600_context *rctx)
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_DST] = 0x000000FF;
 	rstate->states[R600_CB_CNTL__CB_CLRCMP_MSK] = 0xFFFFFFFF;
 	rstate->states[R600_CB_CNTL__PA_SC_AA_MASK] = 0xFFFFFFFF;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 int r600_context_hw_states(struct pipe_context *ctx)
@@ -1397,110 +1235,46 @@ int r600_context_hw_states(struct pipe_context *ctx)
 	struct r600_context *rctx = r600_context(ctx);
 	struct r600_resource_texture *rtexture;
 	unsigned i;
-	int r;
-	int nr_cbufs = rctx->framebuffer->state.framebuffer.nr_cbufs;
-	int ucp_nclip = 0;
 
-	if (rctx->clip) 
-		ucp_nclip = rctx->clip->state.clip.nr;
+	/* build new states */
+	r600_rasterizer(rctx, &rctx->hw_states.rasterizer);
+	r600_scissor(rctx, &rctx->hw_states.scissor);
+	r600_dsa(rctx, &rctx->hw_states.dsa);
+	r600_cb_cntl(rctx, &rctx->hw_states.cb_cntl);
 
-	/* free previous TODO determine what need to be updated, what
-	 * doesn't
-	 */
-	rctx->hw_states.cb_cntl = radeon_state_decref(rctx->hw_states.cb_cntl);
-	rctx->hw_states.rasterizer = radeon_state_decref(rctx->hw_states.rasterizer);
-	rctx->hw_states.scissor = radeon_state_decref(rctx->hw_states.scissor);
-	rctx->hw_states.dsa = radeon_state_decref(rctx->hw_states.dsa);
+	/* bind states */
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
+	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
+
+	radeon_draw_bind(&rctx->draw, &rctx->config);
 
-	/* build new states */
-	rctx->hw_states.blend = NULL;
-	rctx->hw_states.viewport = NULL;
-	rctx->hw_states.ucp = NULL;
-	rctx->hw_states.rasterizer = r600_rasterizer(rctx);
-	rctx->hw_states.scissor = r600_scissor(rctx);
-	rctx->hw_states.dsa = r600_dsa(rctx);
-	rctx->hw_states.cb_cntl = r600_cb_cntl(rctx);
 	if (rctx->viewport) {
-		rctx->hw_states.viewport = rctx->viewport->rstate;
+		radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate);
 	}
 	if (rctx->blend) {
-		rctx->hw_states.blend = rctx->blend->rstate;
+		radeon_draw_bind(&rctx->draw, &rctx->blend->rstate);
 	}
 	if (rctx->clip) {
-		rctx->hw_states.ucp = rctx->clip->rstate;
+		radeon_draw_bind(&rctx->draw, &rctx->clip->rstate);
 	}
 	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
 		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.cbufs[i]->texture;
-		rctx->hw_states.cb[i] = rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level];
+		radeon_draw_bind(&rctx->draw, &rtexture->cb[i][rctx->framebuffer->state.framebuffer.cbufs[i]->level]);
 	}
 	if (rctx->framebuffer->state.framebuffer.zsbuf) {
 		rtexture = (struct r600_resource_texture*)rctx->framebuffer->state.framebuffer.zsbuf->texture;
-		rctx->hw_states.db = rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level];
+		radeon_draw_bind(&rctx->draw, &rtexture->db[rctx->framebuffer->state.framebuffer.zsbuf->level]);
 	}
-
-
 	for (i = 0; i < rctx->ps_nsampler; i++) {
 		if (rctx->ps_sampler[i]) {
-			rctx->hw_states.ps_sampler[i] = rctx->ps_sampler[i]->rstate;
-		} else {
-			rctx->hw_states.ps_sampler[i] = NULL;
+			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler[i]->rstate);
 		}
 	}
-	rctx->hw_states.ps_nsampler = rctx->ps_nsampler;
 	for (i = 0; i < rctx->ps_nsampler_view; i++) {
 		if (rctx->ps_sampler_view[i]) {
-			rctx->hw_states.ps_resource[i] = rctx->ps_sampler_view[i]->rstate;
-		} else {
-			rctx->hw_states.ps_resource[i] = NULL;
-		}
-	}
-	rctx->hw_states.ps_nresource = rctx->ps_nsampler_view;
-
-	/* bind states */
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.ucp);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.db);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.rasterizer);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.scissor);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.dsa);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.blend);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.viewport);
-	if (r)
-		return r;
-	for (i = 0; i < nr_cbufs; i++) {
-		r = radeon_draw_set(rctx->draw, rctx->hw_states.cb[i]);
-		if (r)
-			return r;
-	}
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.config);
-	if (r)
-		return r;
-	r = radeon_draw_set(rctx->draw, rctx->hw_states.cb_cntl);
-	if (r)
-		return r;
-	for (i = 0; i < rctx->hw_states.ps_nresource; i++) {
-		if (rctx->hw_states.ps_resource[i]) {
-			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_resource[i]);
-			if (r)
-				return r;
-		}
-	}
-	for (i = 0; i < rctx->hw_states.ps_nsampler; i++) {
-		if (rctx->hw_states.ps_sampler[i]) {
-			r = radeon_draw_set(rctx->draw, rctx->hw_states.ps_sampler[i]);
-			if (r)
-				return r;
+			radeon_draw_bind(&rctx->draw, &rctx->ps_sampler_view[i]->rstate);
 		}
 	}
 	return 0;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index ec1d50566a..c472d4f37b 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -133,10 +133,10 @@ static void r600_texture_destroy_state(struct pipe_resource *ptexture)
 	struct r600_resource_texture *rtexture = (struct r600_resource_texture*)ptexture;
 
 	for (int i = 0; i < PIPE_MAX_TEXTURE_LEVELS; i++) {
-		radeon_state_decref(rtexture->scissor[i]);
-		radeon_state_decref(rtexture->db[i]);
+		radeon_state_fini(&rtexture->scissor[i]);
+		radeon_state_fini(&rtexture->db[i]);
 		for (int j = 0; j < 8; j++) {
-			radeon_state_decref(rtexture->cb[j][i]);
+			radeon_state_fini(&rtexture->cb[j][i]);
 		}
 	}
 }
@@ -668,16 +668,13 @@ int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_textu
 	return 0;
 }
 
-static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscreen,
+static void r600_texture_state_scissor(struct r600_screen *rscreen,
 					struct r600_resource_texture *rtexture,
 					unsigned level)
 {
-	struct radeon_state *rstate;
-
-	rstate = radeon_state(rscreen->rw, R600_STATE_SCISSOR, 0);
-	if (rstate == NULL)
-		return NULL;
+	struct radeon_state *rstate = &rtexture->scissor[level];
 
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_SCISSOR, 0, 0);
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
 	 */
@@ -700,16 +697,10 @@ static struct radeon_state *r600_texture_state_scissor(struct r600_screen *rscre
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR] = S_028244_BR_X(rtexture->width[level]) | S_028244_BR_Y(rtexture->height[level]);
 	rstate->states[R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL] = 0x80000000;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
-				struct r600_resource_texture *rtexture,
-				unsigned cb, unsigned level)
+static void r600_texture_state_cb(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 {
 	struct radeon_state *rstate;
 	struct r600_resource *rbuffer;
@@ -718,9 +709,8 @@ static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
 	unsigned format, swap, ntype;
 	const struct util_format_description *desc;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_CB0 + cb, 0);
-	if (rstate == NULL)
-		return NULL;
+	rstate = &rtexture->cb[cb][level];
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_CB0 + cb, 0, 0);
 	rbuffer = &rtexture->resource;
 
 	/* set states (most default value are 0 and struct already
@@ -762,24 +752,16 @@ static struct radeon_state *r600_texture_state_cb(struct r600_screen *rscreen,
 	rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
 						S_028060_SLICE_TILE_MAX(slice);
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
-static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
-				struct r600_resource_texture *rtexture,
-				unsigned level)
+static void r600_texture_state_db(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
 {
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rtexture->db[level];
 	struct r600_resource *rbuffer;
 	unsigned pitch, slice, format;
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_DB, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_DB, 0, 0);
 	rbuffer = &rtexture->resource;
 	rtexture->tilled = 1;
 	rtexture->array_mode = 2;
@@ -803,36 +785,24 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
 	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
 	rstate->nbo = 1;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->scissor[level] == NULL) {
-		rtexture->scissor[level] = r600_texture_state_scissor(rscreen, rtexture, level);
-		if (rtexture->scissor[level] == NULL) {
-			R600_ERR("failed to create scissor for uncompressing depth\n");
-			return -ENOMEM;
-		}
+	if (!rtexture->scissor[level].cpm4) {
+		r600_texture_state_scissor(rscreen, rtexture, level);
 	}
 	return 0;
 }
 
-static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscreen,
-					struct r600_resource_texture *rtexture,
-					unsigned level)
+static void r600_texture_state_viewport(struct r600_screen *rscreen, struct r600_resource_texture *rtexture, unsigned level)
 {
-	struct radeon_state *rstate;
+	struct radeon_state *rstate = &rtexture->viewport[level];
 
-	rstate = radeon_state(rscreen->rw, R600_STATE_VIEWPORT, 0);
-	if (rstate == NULL)
-		return NULL;
+	radeon_state_init(rstate, rscreen->rw, R600_STATE_VIEWPORT, 0, 0);
 
 	/* set states (most default value are 0 and struct already
 	 * initialized to 0, thus avoid resetting them)
@@ -846,23 +816,15 @@ static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscr
 	rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
 	rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
 
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
+	radeon_state_pm4(rstate);
 }
 
 int r600_texture_cb(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned cb, unsigned level)
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->cb[cb][level] == NULL) {
-		rtexture->cb[cb][level] = r600_texture_state_cb(rscreen, rtexture, cb, level);
-		if (rtexture->cb[cb][level] == NULL) {
-			R600_ERR("failed to create cb%d state for texture\n", cb);
-			return -ENOMEM;
-		}
+	if (!rtexture->cb[cb][level].cpm4) {
+		r600_texture_state_cb(rscreen, rtexture, cb, level);
 	}
 	return 0;
 }
@@ -871,12 +833,8 @@ int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtex
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->db[level] == NULL) {
-		rtexture->db[level] = r600_texture_state_db(rscreen, rtexture, level);
-		if (rtexture->db[level] == NULL) {
-			R600_ERR("failed to create db state for texture\n");
-			return -ENOMEM;
-		}
+	if (!rtexture->db[level].cpm4) {
+		r600_texture_state_db(rscreen, rtexture, level);
 	}
 	return 0;
 }
@@ -885,12 +843,8 @@ int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture
 {
 	struct r600_screen *rscreen = r600_screen(ctx->screen);
 
-	if (rtexture->viewport[level] == NULL) {
-		rtexture->viewport[level] = r600_texture_state_viewport(rscreen, rtexture, level);
-		if (rtexture->viewport[level] == NULL) {
-			R600_ERR("failed to create viewport state for texture\n");
-			return -ENOMEM;
-		}
+	if (!rtexture->viewport[level].cpm4) {
+		r600_texture_state_viewport(rscreen, rtexture, level);
 	}
 	return 0;
 }
diff --git a/src/gallium/drivers/r600/radeon.h b/src/gallium/drivers/r600/radeon.h
index 3f1ca95f69..aaac8de528 100644
--- a/src/gallium/drivers/r600/radeon.h
+++ b/src/gallium/drivers/r600/radeon.h
@@ -77,6 +77,14 @@ enum radeon_family {
 	CHIP_LAST,
 };
 
+enum {
+	R600_SHADER_PS = 1,
+	R600_SHADER_VS,
+	R600_SHADER_GS,
+	R600_SHADER_FS,
+	R600_SHADER_MAX = R600_SHADER_FS,
+};
+
 enum radeon_family radeon_get_family(struct radeon *rw);
 
 /*
@@ -105,9 +113,10 @@ struct radeon_stype_info;
 struct radeon_state {
 	struct radeon			*radeon;
 	unsigned			refcount;
-	struct radeon_stype_info        *stype;
+	struct radeon_stype_info	*stype;
+	unsigned			state_id;
 	unsigned			id;
-	unsigned                        shader_index;
+	unsigned			shader_index;
 	unsigned			nstates;
 	u32				states[64];
 	unsigned			npm4;
@@ -123,10 +132,8 @@ struct radeon_state {
 	unsigned			bo_dirty[4];
 };
 
-struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
-struct radeon_state *radeon_state_shader(struct radeon *radeon, u32 type, u32 id, u32 shader_class);
-struct radeon_state *radeon_state_incref(struct radeon_state *state);
-struct radeon_state *radeon_state_decref(struct radeon_state *state);
+int radeon_state_init(struct radeon_state *rstate, struct radeon *radeon, u32 type, u32 id, u32 shader_class);
+void radeon_state_fini(struct radeon_state *state);
 int radeon_state_pm4(struct radeon_state *state);
 int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type);
 
@@ -134,30 +141,13 @@ int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shad
  * draw functions
  */
 struct radeon_draw {
-	unsigned			refcount;
 	struct radeon			*radeon;
-	unsigned			nstate;
 	struct radeon_state		**state;
-	unsigned			cpm4;
 };
 
-struct radeon_draw *radeon_draw(struct radeon *radeon);
-struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw);
-struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw);
-struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw);
-int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
-int radeon_draw_set_new(struct radeon_draw *draw, struct radeon_state *state);
-int radeon_draw_check(struct radeon_draw *draw);
-
-struct radeon_ctx *radeon_ctx(struct radeon *radeon);
-struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
-struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
-int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
-int radeon_ctx_pm4(struct radeon_ctx *ctx);
-int radeon_ctx_submit(struct radeon_ctx *ctx);
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
+int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon);
+void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state);
+void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state);
 
 /*
  * radeon context functions
@@ -172,30 +162,30 @@ struct radeon_cs_reloc {
 #pragma pack()
 
 struct radeon_ctx {
-	int				refcount;
 	struct radeon			*radeon;
 	u32				*pm4;
-	u32				cpm4;
-	u32				draw_cpm4;
-	unsigned			id;
-	unsigned			next_id;
+	int				cdwords;
+	int				ndwords;
 	unsigned			nreloc;
 	struct radeon_cs_reloc		*reloc;
 	unsigned			nbo;
 	struct radeon_bo		**bo;
-	unsigned			ndraw;
-	struct radeon_draw		*cdraw;
-	struct radeon_draw		**draw;
-	unsigned			nstate;
-	struct radeon_state		**state;
 };
 
+int radeon_ctx_init(struct radeon_ctx *ctx, struct radeon *radeon);
+void radeon_ctx_fini(struct radeon_ctx *ctx);
+void radeon_ctx_clear(struct radeon_ctx *ctx);
+int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
+int radeon_ctx_submit(struct radeon_ctx *ctx);
+void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file);
+int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
+
 /*
  * R600/R700
  */
 
 enum r600_stype {
-	R600_STATE_CONFIG,  
+	R600_STATE_CONFIG,
 	R600_STATE_CB_CNTL,
 	R600_STATE_RASTERIZER,
 	R600_STATE_VIEWPORT,
@@ -223,14 +213,6 @@ enum r600_stype {
 	R600_STATE_DRAW,
 };
 
-enum {
-	R600_SHADER_PS = 1,
-	R600_SHADER_VS,
-	R600_SHADER_GS,
-	R600_SHADER_FS,
-	R600_SHADER_MAX = R600_SHADER_FS,
-};
-
 /* R600_CONFIG */
 #define R600_CONFIG__SQ_CONFIG			0
 #define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			1
-- 
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