From 3ee21f30cda27e0ee1357f930163526622ba9434 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 29 Jan 2009 14:57:49 -0800 Subject: intel: Expose more FBconfigs in the 3D driver. We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x (z0,z24,z24s8) on either class of chipsets. The only restriction is no mixing bpp when also mixing tiling. This shouldn't be occurring currently. --- src/mesa/drivers/dri/common/utils.c | 3 ++- src/mesa/drivers/dri/common/utils.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/common') diff --git a/src/mesa/drivers/dri/common/utils.c b/src/mesa/drivers/dri/common/utils.c index e4d228c575..d6de1c0e9b 100644 --- a/src/mesa/drivers/dri/common/utils.c +++ b/src/mesa/drivers/dri/common/utils.c @@ -744,7 +744,8 @@ driCreateConfigs(GLenum fb_format, GLenum fb_type, return configs; } -const __DRIconfig **driConcatConfigs(__DRIconfig **a, __DRIconfig **b) +const __DRIconfig **driConcatConfigs(const __DRIconfig **a, + const __DRIconfig **b) { const __DRIconfig **all; int i, j, index; diff --git a/src/mesa/drivers/dri/common/utils.h b/src/mesa/drivers/dri/common/utils.h index 0c974dbff3..b0908e530a 100644 --- a/src/mesa/drivers/dri/common/utils.h +++ b/src/mesa/drivers/dri/common/utils.h @@ -133,7 +133,8 @@ driCreateConfigs(GLenum fb_format, GLenum fb_type, unsigned num_depth_stencil_bits, const GLenum * db_modes, unsigned num_db_modes); -const __DRIconfig **driConcatConfigs(__DRIconfig **a, __DRIconfig **b); +const __DRIconfig **driConcatConfigs(const __DRIconfig **a, + const __DRIconfig **b); int driGetConfigAttrib(const __DRIconfig *config, -- cgit v1.2.3