From c2f1a1857e553f4d11fc0715bb586f69ac147df0 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 28 Sep 2006 14:07:12 +0000 Subject: i915: Attempt to schedule buffer swap on target vertical blank when possible. This has some advantages over the traditional way of first waiting for the target vertical blank and then emitting the buffer swap, e.g. * glXSwapBuffers returns immediately, only the next time the driver needs the hardware lock will it block until the target vertical blank. This should allow applications that don't intermix rendering and other processing to start processing for the next frame right away. * It's less likely to produce tearing. --- src/mesa/drivers/dri/i915/intel_context.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mesa/drivers/dri/i915/intel_context.h') diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index 0ca8ff268d..6cd6272053 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -261,6 +261,8 @@ struct intel_context GLuint swap_count; GLuint swap_missed_count; + + GLuint swap_scheduled; }; @@ -321,6 +323,13 @@ do { \ char __ret=0; \ DEBUG_CHECK_LOCK(); \ assert(!(intel)->locked); \ + if ((intel)->swap_scheduled) { \ + drmVBlank vbl; \ + vbl.request.type = DRM_VBLANK_ABSOLUTE; \ + vbl.request.sequence = (intel)->vbl_seq; \ + drmWaitVBlank((intel)->driFd, &vbl); \ + (intel)->swap_scheduled = 0; \ + } \ DRM_CAS((intel)->driHwLock, (intel)->hHWContext, \ (DRM_LOCK_HELD|(intel)->hHWContext), __ret); \ if (__ret) \ -- cgit v1.2.3