From bb38cadb1c5f2dc13096a091bdaf61dc3e3cfa4d Mon Sep 17 00:00:00 2001 From: Michal Krol Date: Tue, 11 Apr 2006 11:41:11 +0000 Subject: More GLSL code: - use macros to access and modify render inputs bit-field; - un-alias generic vertex attributes for ARB vertex calls; - use MAX_VERTEX_PROGRAM_ATTRIBS (NV code) or MAX_VERTEX_ATTRIBS (ARB code) in place of VERT_ATTRIB_MAX; - define VERT_ATTRIB_GENERIC0..15 for un-aliased vertex attributes for ARB_vertex_shader; - fix generic attribute index range check in arbprogparse.c; - interface GLSL varyings between vertex and fragment shader; - use 64-bit optimised bitset (bitset.h) for render inputs; --- src/mesa/drivers/dri/i915/i830_context.h | 2 +- src/mesa/drivers/dri/i915/i830_vtbl.c | 45 +++++++++++++++++--------------- src/mesa/drivers/dri/i915/i915_texprog.c | 21 ++++++++------- 3 files changed, 37 insertions(+), 31 deletions(-) (limited to 'src/mesa/drivers/dri/i915') diff --git a/src/mesa/drivers/dri/i915/i830_context.h b/src/mesa/drivers/dri/i915/i830_context.h index 5bdcc21c5a..d5811e6c34 100644 --- a/src/mesa/drivers/dri/i915/i830_context.h +++ b/src/mesa/drivers/dri/i915/i830_context.h @@ -118,7 +118,7 @@ struct i830_context { struct intel_context intel; - GLuint last_index; + DECLARE_RENDERINPUTS(last_index_bitset); struct i830_hw_state meta, initial, state, *current; }; diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index e8913e8063..9e71b11109 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -65,11 +65,13 @@ static void i830_render_start( intelContextPtr intel ) i830ContextPtr i830 = I830_CONTEXT(intel); TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - GLuint index = tnl->render_inputs; + DECLARE_RENDERINPUTS(index_bitset); GLuint v0 = _3DSTATE_VFT0_CMD; GLuint v2 = _3DSTATE_VFT1_CMD; GLuint mcsb1 = 0; + RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset ); + /* Important: */ VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; @@ -78,7 +80,7 @@ static void i830_render_start( intelContextPtr intel ) /* EMIT_ATTR's must be in order as they tell t_vertex.c how to * build up a hardware vertex. */ - if (index & _TNL_BITS_TEX_ANY) { + if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW ); intel->coloroffset = 4; } @@ -87,36 +89,37 @@ static void i830_render_start( intelContextPtr intel ) intel->coloroffset = 3; } - if (index & _TNL_BIT_POINTSIZE) { + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POINTSIZE )) { EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH ); } EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE ); intel->specoffset = 0; - if (index & (_TNL_BIT_COLOR1|_TNL_BIT_FOG)) { - if (index & _TNL_BIT_COLOR1) { - intel->specoffset = intel->coloroffset + 1; - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC ); + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) || + RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) { + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) { + intel->specoffset = intel->coloroffset + 1; + EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC ); } - else - EMIT_PAD( 3 ); - - if (index & _TNL_BIT_FOG) - EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC ); else - EMIT_PAD( 1 ); + EMIT_PAD( 3 ); + + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) + EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC ); + else + EMIT_PAD( 1 ); } - if (index & _TNL_BITS_TEX_ANY) { + if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { int i, count = 0; for (i = 0; i < I830_TEX_UNITS; i++) { - if (index & _TNL_BIT_TEX(i)) { - GLuint sz = VB->TexCoordPtr[i]->size; - GLuint emit; - GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] & - ~TEXCOORDTYPE_MASK); + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) { + GLuint sz = VB->TexCoordPtr[i]->size; + GLuint emit; + GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] & + ~TEXCOORDTYPE_MASK); switch (sz) { case 1: @@ -162,7 +165,7 @@ static void i830_render_start( intelContextPtr intel ) if (v0 != i830->state.Ctx[I830_CTXREG_VF] || v2 != i830->state.Ctx[I830_CTXREG_VF2] || mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] || - index != i830->last_index) { + !RENDERINPUTS_EQUAL( index_bitset, i830->last_index_bitset )) { I830_STATECHANGE( i830, I830_UPLOAD_CTX ); @@ -180,7 +183,7 @@ static void i830_render_start( intelContextPtr intel ) i830->state.Ctx[I830_CTXREG_VF] = v0; i830->state.Ctx[I830_CTXREG_VF2] = v2; i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1; - i830->last_index = index; + RENDERINPUTS_COPY( i830->last_index_bitset, index_bitset ); assert(i830_check_vertex_size( intel, intel->vertex_size )); } diff --git a/src/mesa/drivers/dri/i915/i915_texprog.c b/src/mesa/drivers/dri/i915/i915_texprog.c index 74ece96f8b..4fbce34ba2 100644 --- a/src/mesa/drivers/dri/i915/i915_texprog.c +++ b/src/mesa/drivers/dri/i915/i915_texprog.c @@ -576,11 +576,13 @@ void i915ValidateTextureProgram( i915ContextPtr i915 ) GLcontext *ctx = &intel->ctx; TNLcontext *tnl = TNL_CONTEXT(ctx); struct vertex_buffer *VB = &tnl->vb; - GLuint index = tnl->render_inputs; + DECLARE_RENDERINPUTS(index_bitset); int i, offset; GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK; GLuint s2 = S2_TEXCOORD_NONE; + RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset ); + /* Important: */ VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; @@ -591,9 +593,9 @@ void i915ValidateTextureProgram( i915ContextPtr i915 ) if (i915->vertex_fog == I915_FOG_PIXEL) { EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16 ); - index &= ~_TNL_BIT_FOG; + RENDERINPUTS_CLEAR( index_bitset, _TNL_ATTRIB_FOG ); } - else if (index & _TNL_BITS_TEX_ANY) { + else if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16 ); } else { @@ -601,29 +603,30 @@ void i915ValidateTextureProgram( i915ContextPtr i915 ) } /* How undefined is undefined? */ - if (index & _TNL_BIT_POINTSIZE) { + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_POINTSIZE )) { EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, S4_VFMT_POINT_WIDTH, 4 ); } intel->coloroffset = offset / 4; EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4 ); - if (index & (_TNL_BIT_COLOR1|_TNL_BIT_FOG)) { - if (index & _TNL_BIT_COLOR1) { + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) || + RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) { + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) { intel->specoffset = offset / 4; EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, S4_VFMT_SPEC_FOG, 3 ); } else EMIT_PAD( 3 ); - if (index & _TNL_BIT_FOG) + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, S4_VFMT_SPEC_FOG, 1 ); else EMIT_PAD( 1 ); } - if (index & _TNL_BITS_TEX_ANY) { + if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { for (i = 0; i < 8; i++) { - if (index & _TNL_BIT_TEX(i)) { + if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) { int sz = VB->TexCoordPtr[i]->size; s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK); -- cgit v1.2.3