From cdcef6cbf4dd80047819e9098e34a3b98bd502a4 Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Mon, 19 Apr 2010 15:51:50 +0800 Subject: intel: Clean up chipset name and gen num for Ironlake Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt Signed-off-by: Zhenyu Wang --- src/mesa/drivers/dri/i965/brw_clip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_clip.c') diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index d3275c7a89..029a16500b 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -72,7 +72,7 @@ static void compile_clip_prog( struct brw_context *brw, */ c.header_position_offset = ATTR_SIZE; - if (intel->is_ironlake) + if (intel->gen == 5) delta = 3 * REG_SIZE; else delta = REG_SIZE; @@ -85,7 +85,7 @@ static void compile_clip_prog( struct brw_context *brw, c.nr_attrs = brw_count_bits(c.key.attrs); - if (intel->is_ironlake) + if (intel->gen == 5) c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ else c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ @@ -162,7 +162,7 @@ static void upload_clip_prog(struct brw_context *brw) /* _NEW_TRANSFORM */ key.nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled); - if (intel->is_ironlake) + if (intel->gen == 5) key.clip_mode = BRW_CLIPMODE_KERNEL_CLIP; else key.clip_mode = BRW_CLIPMODE_NORMAL; -- cgit v1.2.3