From 93ba0055c325007656c14ba38302e21be3dc599f Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Fri, 20 Aug 2010 14:37:19 -0700 Subject: i965: Add AccWrCtl support on Sandybridge. Whenever the accumulator results are needed, this bit must be set. --- src/mesa/drivers/dri/i965/brw_eu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mesa/drivers/dri/i965/brw_eu.c') diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c index 4e7c1226ad..2ff39e8e64 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.c +++ b/src/mesa/drivers/dri/i965/brw_eu.c @@ -85,6 +85,12 @@ void brw_set_saturate( struct brw_compile *p, GLuint value ) p->current->header.saturate = value; } +void brw_set_acc_write_control(struct brw_compile *p, GLuint value) +{ + if (p->brw->intel.gen >= 6) + p->current->header.acc_wr_control = value; +} + void brw_push_insn_state( struct brw_compile *p ) { assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]); -- cgit v1.2.3