From 63879d90ace519749fed228ca0e21b5b56c7e1c0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 18 Jan 2011 17:16:49 -0800 Subject: i965/fs: Add an instruction scheduler. Improves performance of my GLSL demo by 5.1% (+/- 1.4%, n=7). It also reschedules the giant multiply tree at the end of glsl-fs-convolution-1 so that we end up not spilling registers, producing the expected level of performance. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mesa/drivers/dri/i965/brw_fs.cpp') diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 5b595a3c0e..c24060b8c6 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -3696,6 +3696,8 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c) progress = v.dead_code_eliminate() || progress; } while (progress); + v.schedule_instructions(); + if (0) { /* Debug of register spilling: Go spill everything. */ int virtual_grf_count = v.virtual_grf_next; -- cgit v1.2.3