From ab12e764ba3f57ad9f0d7252262cfc6e07839928 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Wed, 11 Nov 2009 17:57:56 -0800 Subject: i965: fix EXT_provoking_vertex support This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage. --- src/mesa/drivers/dri/i965/brw_gs.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_gs.h') diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index bbb991ea2e..e0cf07256b 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -43,8 +43,9 @@ struct brw_gs_prog_key { GLuint attrs:32; GLuint primitive:4; GLuint hint_gs_always:1; + GLuint pv_first:1; GLuint need_gs_prog:1; - GLuint pad:26; + GLuint pad:25; }; struct brw_gs_compile { @@ -67,8 +68,8 @@ struct brw_gs_compile { #define ATTR_SIZE (4*4) -void brw_gs_quads( struct brw_gs_compile *c ); -void brw_gs_quad_strip( struct brw_gs_compile *c ); +void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ); +void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ); void brw_gs_tris( struct brw_gs_compile *c ); void brw_gs_lines( struct brw_gs_compile *c ); void brw_gs_points( struct brw_gs_compile *c ); -- cgit v1.2.3 From 5606dfb572bf4b89b4882265924705bacc8c182b Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 17 Nov 2009 16:10:24 -0800 Subject: Merge branch 'outputswritten64' Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h --- src/mesa/drivers/dri/i965/brw_clip.c | 2 +- src/mesa/drivers/dri/i965/brw_clip.h | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 6 +----- src/mesa/drivers/dri/i965/brw_gs.h | 2 +- src/mesa/drivers/dri/i965/brw_sf.c | 6 +++--- src/mesa/drivers/dri/i965/brw_sf.h | 2 +- src/mesa/drivers/dri/i965/brw_sf_emit.c | 18 +++++++++--------- src/mesa/drivers/dri/i965/brw_util.c | 2 +- src/mesa/drivers/dri/i965/brw_util.h | 2 +- src/mesa/drivers/dri/i965/brw_vs.c | 2 +- src/mesa/drivers/dri/i965/brw_vs_emit.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_wm.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_fp.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_pass2.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_state.c | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 15 ++++++++------- src/mesa/main/config.h | 2 +- src/mesa/main/context.c | 8 +++++--- src/mesa/main/ffvertex_prog.c | 2 +- src/mesa/main/mtypes.h | 27 ++++++++++++++++++++++++++- src/mesa/main/texenvprogram.c | 2 +- src/mesa/shader/prog_print.c | 6 +++--- src/mesa/shader/program_parse.tab.c | 2 +- src/mesa/shader/program_parse.y | 2 +- src/mesa/shader/programopt.c | 8 ++++---- src/mesa/shader/slang/slang_link.c | 25 +++++++++++++++---------- src/mesa/state_tracker/st_atom_shader.c | 2 +- src/mesa/state_tracker/st_program.c | 2 +- src/mesa/swrast/s_fragprog.c | 12 ++++++------ src/mesa/tnl/t_context.c | 2 +- src/mesa/tnl/t_vb_program.c | 8 ++++---- 33 files changed, 111 insertions(+), 82 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_gs.h') diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index f45dcf8282..dbd10a5297 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -78,7 +78,7 @@ static void compile_clip_prog( struct brw_context *brw, delta = REG_SIZE; for (i = 0; i < VERT_RESULT_MAX; i++) - if (c.key.attrs & (1<= VERT_RESULT_TEX0 && i <= VERT_RESULT_TEX7) { @@ -147,7 +147,7 @@ static void upload_sf_prog(struct brw_context *brw) * edgeflag testing here, it is already done in the clip * program. */ - if (key.attrs & (1<key.attrs & (1<key.attrs & BITFIELD64_BIT(attr)) ? 1 : 0; } /*********************************************************************** @@ -122,8 +122,8 @@ static void do_twoside_color( struct brw_sf_compile *c ) * Flat shading */ -#define VERT_RESULT_COLOR_BITS ((1<nr_setup_regs - 1); - GLuint persp_mask; - GLuint linear_mask; + GLbitfield64 persp_mask; + GLbitfield64 linear_mask; if (c->key.do_flat_shading || c->key.linear_color) persp_mask = c->key.attrs & ~(FRAG_BIT_WPOS | @@ -331,10 +331,10 @@ static GLboolean calculate_masks( struct brw_sf_compile *c, *pc_linear = 0; *pc = 0xf; - if (persp_mask & (1 << c->idx_to_attr[reg*2])) + if (persp_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2])) *pc_persp = 0xf; - if (linear_mask & (1 << c->idx_to_attr[reg*2])) + if (linear_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2])) *pc_linear = 0xf; /* Maybe only processs one attribute on the final round: @@ -342,10 +342,10 @@ static GLboolean calculate_masks( struct brw_sf_compile *c, if (reg*2+1 < c->nr_setup_attrs) { *pc |= 0xf0; - if (persp_mask & (1 << c->idx_to_attr[reg*2+1])) + if (persp_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2+1])) *pc_persp |= 0xf0; - if (linear_mask & (1 << c->idx_to_attr[reg*2+1])) + if (linear_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2+1])) *pc_linear |= 0xf0; } diff --git a/src/mesa/drivers/dri/i965/brw_util.c b/src/mesa/drivers/dri/i965/brw_util.c index ce21aa4869..bba9249d1b 100644 --- a/src/mesa/drivers/dri/i965/brw_util.c +++ b/src/mesa/drivers/dri/i965/brw_util.c @@ -35,7 +35,7 @@ #include "brw_util.h" #include "brw_defines.h" -GLuint brw_count_bits( GLuint val ) +GLuint brw_count_bits(uint64_t val) { GLuint i; for (i = 0; val ; val >>= 1) diff --git a/src/mesa/drivers/dri/i965/brw_util.h b/src/mesa/drivers/dri/i965/brw_util.h index 33e7cd87e4..04f3175d3e 100644 --- a/src/mesa/drivers/dri/i965/brw_util.h +++ b/src/mesa/drivers/dri/i965/brw_util.h @@ -35,7 +35,7 @@ #include "main/mtypes.h" -extern GLuint brw_count_bits( GLuint val ); +extern GLuint brw_count_bits(uint64_t val); extern GLuint brw_parameter_list_state_flags(struct gl_program_parameter_list *paramList); extern GLuint brw_translate_blend_factor( GLenum factor ); extern GLuint brw_translate_blend_equation( GLenum mode ); diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index f0c79efbd9..fd055e225e 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -56,7 +56,7 @@ static void do_vs_prog( struct brw_context *brw, c.prog_data.inputs_read = vp->program.Base.InputsRead; if (c.key.copy_edgeflag) { - c.prog_data.outputs_written |= 1<prog_data.outputs_written & (1 << i)) { + if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) { c->nr_outputs++; assert(i < Elements(c->regs[PROGRAM_OUTPUT])); if (i == VERT_RESULT_HPOS) { @@ -1124,7 +1124,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) /* Update the header for point size, user clipping flags, and -ve rhw * workaround. */ - if ((c->prog_data.outputs_written & (1<prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || c->key.nr_userclip || BRW_IS_965(p->brw)) { struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); @@ -1134,7 +1134,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) brw_set_access_mode(p, BRW_ALIGN_16); - if (c->prog_data.outputs_written & (1<prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { struct brw_reg psiz = c->regs[PROGRAM_OUTPUT][VERT_RESULT_PSIZ]; brw_MUL(p, brw_writemask(header1, WRITEMASK_W), brw_swizzle1(psiz, 0), brw_imm_f(1<<11)); brw_AND(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8)); @@ -1224,7 +1224,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) */ GLuint i, mrf = 0; for (i = c->first_overflow_output; i < VERT_RESULT_MAX; i++) { - if (c->prog_data.outputs_written & (1 << i)) { + if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) { /* move from GRF to MRF */ brw_MOV(p, brw_message_reg(4+mrf), c->regs[PROGRAM_OUTPUT][i]); mrf++; diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index d8971321f3..77e3b2c32a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -231,7 +231,7 @@ static void brw_wm_populate_key( struct brw_context *brw, ctx->Color.AlphaEnabled) lookup |= IZ_PS_KILL_ALPHATEST_BIT; - if (fp->program.Base.OutputsWritten & (1<program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) lookup |= IZ_PS_COMPUTES_DEPTH_BIT; /* _NEW_DEPTH */ @@ -347,7 +347,7 @@ static void brw_wm_populate_key( struct brw_context *brw, key->nr_color_regions = brw->state.nr_color_regions; /* CACHE_NEW_VS_PROG */ - key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS; + key->vp_outputs_written = brw->vs.prog_data->outputs_written; /* The unique fragment program ID */ key->program_string_id = fp->id; diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index b3c05eb0ad..9dcb6e14bb 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -79,7 +79,7 @@ struct brw_wm_prog_key { GLuint program_string_id:32; GLushort origin_x, origin_y; GLushort drawable_height; - GLuint vp_outputs_written; + GLbitfield64 vp_outputs_written; }; diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 1c4f62ba48..7d03179588 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -986,7 +986,7 @@ static void emit_render_target_writes( struct brw_wm_compile *c ) } else { /* if gl_FragData[0] is written, use it, else use gl_FragColor */ - if (c->fp->program.Base.OutputsWritten & (1 << FRAG_RESULT_DATA0)) + if (c->fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0)) outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_DATA0); else outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_COLOR); diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 3ab446164c..e8c2cb66ec 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -371,7 +371,7 @@ static void prealloc_reg(struct brw_wm_compile *c) for (j = 0; j < 4; j++) set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg); } - if (c->key.vp_outputs_written & (1 << i)) { + if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) { reg_index += 2; } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c index 6faea018fb..31303febf0 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c @@ -82,8 +82,8 @@ static void init_registers( struct brw_wm_compile *c ) for (j = 0; j < c->nr_creg; j++) prealloc_reg(c, &c->creg[j], i++); - for (j = 0; j < FRAG_ATTRIB_MAX; j++) { - if (c->key.vp_outputs_written & (1<key.vp_outputs_written & BITFIELD64_BIT(j)) { int fp_index; if (j >= VERT_RESULT_VAR0) diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 361f91292b..f89ed9bce7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -106,7 +106,7 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) /* as far as we can tell */ key->computes_depth = - (fp->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) != 0; + (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0; /* BRW_NEW_DEPTH_BUFFER * Override for NULL depthbuffer case, required by the Pixel Shader Computed * Depth field. diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index c702910ef2..e7d48a7f29 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -509,25 +509,26 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, prog to a not enabled output however, so just don't mess with it. We only need to change compsel. */ GLuint out_compsel = 0; - GLuint vp_out = rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten; + const GLbitfield64 vp_out = + rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten; vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0]; - assert(vp_out & (1 << VERT_RESULT_HPOS)); + assert(vp_out & BITFIELD64_BIT(VERT_RESULT_HPOS)); out_compsel = R200_OUTPUT_XYZW; - if (vp_out & (1 << VERT_RESULT_COL0)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL0)) { out_compsel |= R200_OUTPUT_COLOR_0; } - if (vp_out & (1 << VERT_RESULT_COL1)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL1)) { out_compsel |= R200_OUTPUT_COLOR_1; } - if (vp_out & (1 << VERT_RESULT_FOGC)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_FOGC)) { out_compsel |= R200_OUTPUT_DISCRETE_FOG; } - if (vp_out & (1 << VERT_RESULT_PSIZ)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { out_compsel |= R200_OUTPUT_PT_SIZE; } for (i = VERT_RESULT_TEX0; i < VERT_RESULT_TEX6; i++) { - if (vp_out & (1 << i)) { + if (vp_out & BITFIELD64_BIT(i)) { out_compsel |= R200_OUTPUT_TEX_0 << (i - VERT_RESULT_TEX0); } } diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h index 8a09efdb53..c5048970cc 100644 --- a/src/mesa/main/config.h +++ b/src/mesa/main/config.h @@ -205,7 +205,7 @@ #define MAX_VARYING 16 /**< number of float[4] vectors */ #define MAX_SAMPLERS MAX_TEXTURE_IMAGE_UNITS #define MAX_PROGRAM_INPUTS 32 -#define MAX_PROGRAM_OUTPUTS 32 +#define MAX_PROGRAM_OUTPUTS 64 /*@}*/ /** For GL_ARB_vertex_program */ diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index 101d3c6b67..b5bf46718f 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -601,9 +601,11 @@ _mesa_init_constants(GLcontext *ctx) ASSERT(MAX_NV_VERTEX_PROGRAM_INPUTS <= VERT_ATTRIB_MAX); ASSERT(MAX_NV_VERTEX_PROGRAM_OUTPUTS <= VERT_RESULT_MAX); - /* check that we don't exceed various 32-bit bitfields */ - ASSERT(VERT_RESULT_MAX <= 32); - ASSERT(FRAG_ATTRIB_MAX <= 32); + /* check that we don't exceed the size of various bitfields */ + ASSERT(VERT_RESULT_MAX <= + (8 * sizeof(ctx->VertexProgram._Current->Base.OutputsWritten))); + ASSERT(FRAG_ATTRIB_MAX <= + (8 * sizeof(ctx->FragmentProgram._Current->Base.InputsRead))); } diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c index 356476e35a..fe2416d894 100644 --- a/src/mesa/main/ffvertex_prog.c +++ b/src/mesa/main/ffvertex_prog.c @@ -438,7 +438,7 @@ static struct ureg register_input( struct tnl_program *p, GLuint input ) */ static struct ureg register_output( struct tnl_program *p, GLuint output ) { - p->program->Base.OutputsWritten |= (1<program->Base.OutputsWritten |= BITFIELD64_BIT(output); return make_ureg(PROGRAM_OUTPUT, output); } diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 34c51b5442..881d233ca3 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -78,6 +78,31 @@ #endif +/** + * \name 64-bit extension of GLbitfield. + */ +/*@{*/ +typedef GLuint64 GLbitfield64; + +#define BITFIELD64_ONE 1ULL +#define BITFIELD64_ALLONES ~0ULL + +/** Set a single bit */ +#define BITFIELD64_BIT(b) (BITFIELD64_ONE << (b)) + +/** Set a mask of the least significant \c b bits */ +#define BITFIELD64_MASK(b) (((b) >= 64) ? BITFIELD64_ALLONES : \ + (BITFIELD64_BIT(b) - 1)) + +/** + * Set all bits from l (low bit) to h (high bit), inclusive. + * + * \note \C BITFIELD_64_RANGE(0, 63) return 64 set bits. + */ +#define BITFIELD64_RANGE(l, h) (BITFIELD64_MASK((h) + 1) & ~BITFIELD64_MASK(l)) +/*@}*/ + + /** * \name Some forward type declarations */ @@ -1670,7 +1695,7 @@ struct gl_program struct prog_instruction *Instructions; GLbitfield InputsRead; /**< Bitmask of which input regs are read */ - GLbitfield OutputsWritten; /**< Bitmask of which output regs are written to */ + GLbitfield64 OutputsWritten; /**< Bitmask of which output regs are written */ GLbitfield InputFlags[MAX_PROGRAM_INPUTS]; /**< PROG_PARAM_BIT_x flags */ GLbitfield OutputFlags[MAX_PROGRAM_OUTPUTS]; /**< PROG_PARAM_BIT_x flags */ GLbitfield TexturesUsed[MAX_TEXTURE_UNITS]; /**< TEXTURE_x_BIT bitmask */ diff --git a/src/mesa/main/texenvprogram.c b/src/mesa/main/texenvprogram.c index d7e77e759e..f439d4addb 100644 --- a/src/mesa/main/texenvprogram.c +++ b/src/mesa/main/texenvprogram.c @@ -367,7 +367,7 @@ static GLbitfield get_fp_input_mask( GLcontext *ctx ) else { /* calculate from vp->outputs */ struct gl_vertex_program *vprog; - GLbitfield vp_outputs; + GLbitfield64 vp_outputs; /* Choose GLSL vertex shader over ARB vertex program. Need this * since vertex shader state validation comes after fragment state diff --git a/src/mesa/shader/prog_print.c b/src/mesa/shader/prog_print.c index ba4d39452f..52c102cbaa 100644 --- a/src/mesa/shader/prog_print.c +++ b/src/mesa/shader/prog_print.c @@ -826,11 +826,11 @@ _mesa_print_program(const struct gl_program *prog) * XXX move to imports.[ch] if useful elsewhere. */ static const char * -binary(GLbitfield val) +binary(GLbitfield64 val) { - static char buf[50]; + static char buf[80]; GLint i, len = 0; - for (i = 31; i >= 0; --i) { + for (i = 63; i >= 0; --i) { if (val & (1 << i)) buf[len++] = '1'; else if (len > 0 || i == 0) diff --git a/src/mesa/shader/program_parse.tab.c b/src/mesa/shader/program_parse.tab.c index b9ef88b64b..d4f8429488 100644 --- a/src/mesa/shader/program_parse.tab.c +++ b/src/mesa/shader/program_parse.tab.c @@ -2622,7 +2622,7 @@ yyreduce: YYERROR; } - state->prog->OutputsWritten |= (1U << (yyval.dst_reg).Index); + state->prog->OutputsWritten |= BITFIELD64_BIT((yyval.dst_reg).Index); } ;} break; diff --git a/src/mesa/shader/program_parse.y b/src/mesa/shader/program_parse.y index d07bf85b36..8ca6f9805b 100644 --- a/src/mesa/shader/program_parse.y +++ b/src/mesa/shader/program_parse.y @@ -643,7 +643,7 @@ maskedDstReg: dstReg optionalMask optionalCcMask YYERROR; } - state->prog->OutputsWritten |= (1U << $$.Index); + state->prog->OutputsWritten |= BITFIELD64_BIT($$.Index); } } ; diff --git a/src/mesa/shader/programopt.c b/src/mesa/shader/programopt.c index 3b8529592d..a0daac1b80 100644 --- a/src/mesa/shader/programopt.c +++ b/src/mesa/shader/programopt.c @@ -109,7 +109,7 @@ _mesa_insert_mvp_dp4_code(GLcontext *ctx, struct gl_vertex_program *vprog) vprog->Base.Instructions = newInst; vprog->Base.NumInstructions = newLen; vprog->Base.InputsRead |= VERT_BIT_POS; - vprog->Base.OutputsWritten |= (1 << VERT_RESULT_HPOS); + vprog->Base.OutputsWritten |= BITFIELD64_BIT(VERT_RESULT_HPOS); } @@ -211,7 +211,7 @@ _mesa_insert_mvp_mad_code(GLcontext *ctx, struct gl_vertex_program *vprog) vprog->Base.Instructions = newInst; vprog->Base.NumInstructions = newLen; vprog->Base.InputsRead |= VERT_BIT_POS; - vprog->Base.OutputsWritten |= (1 << VERT_RESULT_HPOS); + vprog->Base.OutputsWritten |= BITFIELD64_BIT(VERT_RESULT_HPOS); } @@ -613,7 +613,7 @@ _mesa_nop_fragment_program(GLcontext *ctx, struct gl_fragment_program *prog) prog->Base.Instructions = inst; prog->Base.NumInstructions = 2; prog->Base.InputsRead = 1 << inputAttr; - prog->Base.OutputsWritten = 1 << FRAG_RESULT_COLOR; + prog->Base.OutputsWritten = BITFIELD64_BIT(FRAG_RESULT_COLOR); } @@ -657,7 +657,7 @@ _mesa_nop_vertex_program(GLcontext *ctx, struct gl_vertex_program *prog) prog->Base.Instructions = inst; prog->Base.NumInstructions = 2; prog->Base.InputsRead = 1 << inputAttr; - prog->Base.OutputsWritten = 1 << VERT_RESULT_COL0; + prog->Base.OutputsWritten = BITFIELD64_BIT(VERT_RESULT_COL0); /* * Now insert code to do standard modelview/projection transformation. diff --git a/src/mesa/shader/slang/slang_link.c b/src/mesa/shader/slang/slang_link.c index 144c126525..0a2bc49780 100644 --- a/src/mesa/shader/slang/slang_link.c +++ b/src/mesa/shader/slang/slang_link.c @@ -515,7 +515,7 @@ _slang_update_inputs_outputs(struct gl_program *prog) } if (inst->DstReg.File == PROGRAM_OUTPUT) { - prog->OutputsWritten |= 1 << inst->DstReg.Index; + prog->OutputsWritten |= BITFIELD64_BIT(inst->DstReg.Index); if (inst->DstReg.RelAddr) { /* If the output attribute is indexed with relative addressing * we know that it must be a varying or texcoord such as @@ -528,14 +528,17 @@ _slang_update_inputs_outputs(struct gl_program *prog) if (prog->Target == GL_VERTEX_PROGRAM_ARB) { if (inst->DstReg.Index == VERT_RESULT_TEX0) { /* mark all texcoord outputs as written */ - const GLbitfield mask = - ((1 << MAX_TEXTURE_COORD_UNITS) - 1) << VERT_RESULT_TEX0; + const GLbitfield64 mask = + BITFIELD64_RANGE(VERT_RESULT_TEX0, + (VERT_RESULT_TEX0 + + MAX_TEXTURE_COORD_UNITS - 1)); prog->OutputsWritten |= mask; } else if (inst->DstReg.Index == VERT_RESULT_VAR0) { /* mark all generic varying outputs as written */ - const GLbitfield mask = - ((1 << MAX_VARYING) - 1) << VERT_RESULT_VAR0; + const GLbitfield64 mask = + BITFIELD64_RANGE(VERT_RESULT_VAR0, + (VERT_RESULT_VAR0 + MAX_VARYING - 1)); prog->OutputsWritten |= mask; } } @@ -807,7 +810,8 @@ _slang_link(GLcontext *ctx, if (shProg->VertexProgram) { _slang_update_inputs_outputs(&shProg->VertexProgram->Base); _slang_count_temporaries(&shProg->VertexProgram->Base); - if (!(shProg->VertexProgram->Base.OutputsWritten & (1 << VERT_RESULT_HPOS))) { + if (!(shProg->VertexProgram->Base.OutputsWritten + & BITFIELD64_BIT(VERT_RESULT_HPOS))) { /* the vertex program did not compute a vertex position */ link_error(shProg, "gl_Position was not written by vertex shader\n"); @@ -825,7 +829,7 @@ _slang_link(GLcontext *ctx, if (shProg->FragmentProgram) { const GLbitfield varyingRead = shProg->FragmentProgram->Base.InputsRead >> FRAG_ATTRIB_VAR0; - const GLbitfield varyingWritten = shProg->VertexProgram ? + const GLbitfield64 varyingWritten = shProg->VertexProgram ? shProg->VertexProgram->Base.OutputsWritten >> VERT_RESULT_VAR0 : 0x0; if ((varyingRead & varyingWritten) != varyingRead) { link_error(shProg, @@ -836,9 +840,10 @@ _slang_link(GLcontext *ctx, /* check that gl_FragColor and gl_FragData are not both written to */ if (shProg->FragmentProgram) { - GLbitfield outputsWritten = shProg->FragmentProgram->Base.OutputsWritten; - if ((outputsWritten & ((1 << FRAG_RESULT_COLOR))) && - (outputsWritten >= (1 << FRAG_RESULT_DATA0))) { + const GLbitfield64 outputsWritten = + shProg->FragmentProgram->Base.OutputsWritten; + if ((outputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR)) && + (outputsWritten >= BITFIELD64_BIT(FRAG_RESULT_DATA0))) { link_error(shProg, "Fragment program cannot write both gl_FragColor" " and gl_FragData[].\n"); return; diff --git a/src/mesa/state_tracker/st_atom_shader.c b/src/mesa/state_tracker/st_atom_shader.c index ee649be885..6e311e537e 100644 --- a/src/mesa/state_tracker/st_atom_shader.c +++ b/src/mesa/state_tracker/st_atom_shader.c @@ -176,7 +176,7 @@ find_translated_vp(struct st_context *st, /* See if we need to translate vertex program to TGSI form */ if (xvp->serialNo != stvp->serialNo) { GLuint outAttr; - const GLbitfield outputsWritten = stvp->Base.Base.OutputsWritten; + const GLbitfield64 outputsWritten = stvp->Base.Base.OutputsWritten; GLuint numVpOuts = 0; GLboolean emitPntSize = GL_FALSE, emitBFC0 = GL_FALSE, emitBFC1 = GL_FALSE; GLbitfield usedGenerics = 0x0; diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c index 6d02722c13..190b6a5526 100644 --- a/src/mesa/state_tracker/st_program.c +++ b/src/mesa/state_tracker/st_program.c @@ -469,7 +469,7 @@ st_translate_fragment_program(struct st_context *st, */ { uint numColors = 0; - GLbitfield outputsWritten = stfp->Base.Base.OutputsWritten; + GLbitfield64 outputsWritten = stfp->Base.Base.OutputsWritten; /* if z is written, emit that first */ if (outputsWritten & (1 << FRAG_RESULT_DEPTH)) { diff --git a/src/mesa/swrast/s_fragprog.c b/src/mesa/swrast/s_fragprog.c index 77a77f0bcb..a22d34415d 100644 --- a/src/mesa/swrast/s_fragprog.c +++ b/src/mesa/swrast/s_fragprog.c @@ -190,7 +190,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) { SWcontext *swrast = SWRAST_CONTEXT(ctx); const struct gl_fragment_program *program = ctx->FragmentProgram._Current; - const GLbitfield outputsWritten = program->Base.OutputsWritten; + const GLbitfield64 outputsWritten = program->Base.OutputsWritten; struct gl_program_machine *machine = &swrast->FragProgMachine; GLuint i; @@ -201,7 +201,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) if (_mesa_execute_program(ctx, &program->Base, machine)) { /* Store result color */ - if (outputsWritten & (1 << FRAG_RESULT_COLOR)) { + if (outputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR)) { COPY_4V(span->array->attribs[FRAG_ATTRIB_COL0][i], machine->Outputs[FRAG_RESULT_COLOR]); } @@ -212,7 +212,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) */ GLuint buf; for (buf = 0; buf < ctx->DrawBuffer->_NumColorDrawBuffers; buf++) { - if (outputsWritten & (1 << (FRAG_RESULT_DATA0 + buf))) { + if (outputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + buf)) { COPY_4V(span->array->attribs[FRAG_ATTRIB_COL0 + buf][i], machine->Outputs[FRAG_RESULT_DATA0 + buf]); } @@ -220,7 +220,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) } /* Store result depth/z */ - if (outputsWritten & (1 << FRAG_RESULT_DEPTH)) { + if (outputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { const GLfloat depth = machine->Outputs[FRAG_RESULT_DEPTH][2]; if (depth <= 0.0) span->array->z[i] = 0; @@ -256,12 +256,12 @@ _swrast_exec_fragment_program( GLcontext *ctx, SWspan *span ) run_program(ctx, span, 0, span->end); - if (program->Base.OutputsWritten & (1 << FRAG_RESULT_COLOR)) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR)) { span->interpMask &= ~SPAN_RGBA; span->arrayMask |= SPAN_RGBA; } - if (program->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { span->interpMask &= ~SPAN_Z; span->arrayMask |= SPAN_Z; } diff --git a/src/mesa/tnl/t_context.c b/src/mesa/tnl/t_context.c index f2771cde09..db21b4589d 100644 --- a/src/mesa/tnl/t_context.c +++ b/src/mesa/tnl/t_context.c @@ -171,7 +171,7 @@ _tnl_InvalidateState( GLcontext *ctx, GLuint new_state ) if (vp) { GLuint i; for (i = 0; i < MAX_VARYING; i++) { - if (vp->Base.OutputsWritten & (1 << (VERT_RESULT_VAR0 + i))) { + if (vp->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_VAR0 + i)) { RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_GENERIC(i)); } diff --git a/src/mesa/tnl/t_vb_program.c b/src/mesa/tnl/t_vb_program.c index c10a27614f..e69f7d5766 100644 --- a/src/mesa/tnl/t_vb_program.c +++ b/src/mesa/tnl/t_vb_program.c @@ -329,7 +329,7 @@ run_vp( GLcontext *ctx, struct tnl_pipeline_stage *stage ) /* make list of outputs to save some time below */ numOutputs = 0; for (i = 0; i < VERT_RESULT_MAX; i++) { - if (program->Base.OutputsWritten & (1 << i)) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(i)) { outputs[numOutputs++] = i; } } @@ -407,14 +407,14 @@ run_vp( GLcontext *ctx, struct tnl_pipeline_stage *stage ) /* Fixup fog and point size results if needed */ if (program->IsNVProgram) { if (ctx->Fog.Enabled && - (program->Base.OutputsWritten & (1 << VERT_RESULT_FOGC)) == 0) { + (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_FOGC)) == 0) { for (i = 0; i < VB->Count; i++) { store->results[VERT_RESULT_FOGC].data[i][0] = 1.0; } } if (ctx->VertexProgram.PointSizeEnabled && - (program->Base.OutputsWritten & (1 << VERT_RESULT_PSIZ)) == 0) { + (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_PSIZ)) == 0) { for (i = 0; i < VB->Count; i++) { store->results[VERT_RESULT_PSIZ].data[i][0] = ctx->Point.Size; } @@ -472,7 +472,7 @@ run_vp( GLcontext *ctx, struct tnl_pipeline_stage *stage ) } for (i = 0; i < ctx->Const.MaxVarying; i++) { - if (program->Base.OutputsWritten & (1 << (VERT_RESULT_VAR0 + i))) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_VAR0 + i)) { /* Note: varying results get put into the generic attributes */ VB->AttribPtr[VERT_ATTRIB_GENERIC0+i] = &store->results[VERT_RESULT_VAR0 + i]; -- cgit v1.2.3