From 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Mon, 13 Jul 2009 10:48:43 +0800 Subject: i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai ) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout --- src/mesa/drivers/dri/i965/brw_gs.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/i965/brw_gs.h') diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index 18a4537c32..bbb991ea2e 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -62,6 +62,7 @@ struct brw_gs_compile { GLuint nr_attrs; GLuint nr_regs; GLuint nr_bytes; + GLboolean need_ff_sync; }; #define ATTR_SIZE (4*4) -- cgit v1.2.3