From 747c9129c0b592941b14c290ff3d8ab22ad66acb Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Wed, 17 Jan 2007 10:39:50 +0800 Subject: I965: fix bug#9625-get the correct PV for quardstrip The order of vertices in payload for quardstrip is (0, 1, 3, 2), so the PV for quardstrip is c->reg.vertex[2]. --- src/mesa/drivers/dri/i965/brw_gs_emit.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mesa/drivers/dri/i965/brw_gs_emit.c') diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index e4eed36a46..9abb94d82e 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -116,6 +116,16 @@ void brw_gs_quads( struct brw_gs_compile *c ) brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); } +void brw_gs_quad_strip( struct brw_gs_compile *c ) +{ + brw_gs_alloc_regs(c, 4); + + brw_gs_emit_vue(c, c->reg.vertex[2], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); + brw_gs_emit_vue(c, c->reg.vertex[3], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); +} + void brw_gs_tris( struct brw_gs_compile *c ) { brw_gs_alloc_regs(c, 3); -- cgit v1.2.3