From d61f07318c8678901b948fdaa8ccdf37aa3203e9 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 17:09:12 -0500 Subject: Remove leftover __DRI{screen,drawable,context}Private references As part of the DRI driver interface rewrite I merged __DRIscreenPrivate and __DRIscreen, and likewise for __DRIdrawablePrivate and __DRIcontextPrivate. I left typedefs in place though, to avoid renaming all the *Private use internal to the driver. That was probably a mistake, and it turns out a one-line find+sed combo can do the mass rename. Better late than never. --- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c') diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index d437b1e030..2155feec84 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -330,7 +330,7 @@ const struct brw_tracked_state brw_polygon_stipple = { static void upload_polygon_stipple_offset(struct brw_context *brw) { - __DRIdrawablePrivate *dPriv = brw->intel.driDrawable; + __DRIdrawable *dPriv = brw->intel.driDrawable; struct brw_polygon_stipple_offset bpso; memset(&bpso, 0, sizeof(bpso)); -- cgit v1.2.3 From 5203b7227ccb6b618fa42f08434d4a3cf123dca2 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 20:01:08 -0500 Subject: intel: Drop batchbuffer cliprect_mode tracking --- src/mesa/drivers/dri/i915/i830_vtbl.c | 14 +++---- src/mesa/drivers/dri/i915/i915_vtbl.c | 16 +++----- src/mesa/drivers/dri/i915/intel_tris.c | 7 ++-- src/mesa/drivers/dri/i965/brw_curbe.c | 2 +- src/mesa/drivers/dri/i965/brw_draw.c | 5 +-- src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ++-- src/mesa/drivers/dri/i965/brw_misc_state.c | 14 +++---- src/mesa/drivers/dri/i965/brw_queryobj.c | 4 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/brw_state_batch.c | 4 +- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 30 +++----------- src/mesa/drivers/dri/intel/intel_batchbuffer.h | 57 ++------------------------ src/mesa/drivers/dri/intel/intel_blit.c | 14 +++---- 13 files changed, 49 insertions(+), 128 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 1e3c8301d8..f2a67bbb53 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -298,7 +298,7 @@ i830_emit_invarient_state(struct intel_context *intel) { BATCH_LOCALS; - BEGIN_BATCH(29, IGNORE_CLIPRECTS); + BEGIN_BATCH(29); OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); OUT_BATCH(0); @@ -366,7 +366,7 @@ i830_emit_invarient_state(struct intel_context *intel) #define emit( intel, state, size ) \ - intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS ) + intel_batchbuffer_data(intel->batch, state, size ) static GLuint get_dirty(struct i830_hw_state *state) @@ -429,13 +429,9 @@ i830_emit_state(struct intel_context *intel) * It might be better to talk about explicit places where * scheduling is allowed, rather than assume that it is whenever a * batchbuffer fills up. - * - * Set the space as LOOP_CLIPRECTS now, since that's what our primitives - * will be emitted under. */ intel_batchbuffer_require_space(intel->batch, - get_state_size(state) + INTEL_PRIM_EMIT_SIZE, - LOOP_CLIPRECTS); + get_state_size(state) + INTEL_PRIM_EMIT_SIZE); count = 0; again: aper_count = 0; @@ -501,7 +497,7 @@ i830_emit_state(struct intel_context *intel) if (intel->constant_cliprect) count += 6; - BEGIN_BATCH(count, IGNORE_CLIPRECTS); + BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); OUT_RELOC(state->draw_region->buffer, @@ -544,7 +540,7 @@ i830_emit_state(struct intel_context *intel) if ((dirty & I830_UPLOAD_TEX(i))) { DBG("I830_UPLOAD_TEX(%d):\n", i); - BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS); + BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1); OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]); if (state->tex_buffer[i]) { diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 9f7635a953..251c54697b 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -174,7 +174,7 @@ i915_emit_invarient_state(struct intel_context *intel) { BATCH_LOCALS; - BEGIN_BATCH(17, IGNORE_CLIPRECTS); + BEGIN_BATCH(17); OUT_BATCH(_3DSTATE_AA_CMD | AA_LINE_ECAAR_WIDTH_ENABLE | @@ -220,7 +220,7 @@ i915_emit_invarient_state(struct intel_context *intel) #define emit(intel, state, size ) \ - intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS ) + intel_batchbuffer_data(intel->batch, state, size) static GLuint get_dirty(struct i915_hw_state *state) @@ -301,13 +301,9 @@ i915_emit_state(struct intel_context *intel) * It might be better to talk about explicit places where * scheduling is allowed, rather than assume that it is whenever a * batchbuffer fills up. - * - * Set the space as LOOP_CLIPRECTS now, since that's what our primitives - * will be emitted under. */ intel_batchbuffer_require_space(intel->batch, - get_state_size(state) + INTEL_PRIM_EMIT_SIZE, - LOOP_CLIPRECTS); + get_state_size(state) + INTEL_PRIM_EMIT_SIZE); count = 0; again: aper_count = 0; @@ -384,7 +380,7 @@ i915_emit_state(struct intel_context *intel) if (intel->constant_cliprect) count += 6; - BEGIN_BATCH(count, IGNORE_CLIPRECTS); + BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); OUT_RELOC(state->draw_region->buffer, @@ -441,7 +437,7 @@ i915_emit_state(struct intel_context *intel) if (dirty & I915_UPLOAD_TEX(i)) nr++; - BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS); + BEGIN_BATCH(2 + nr * 3); OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr)); OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); for (i = 0; i < I915_TEX_UNITS; i++) @@ -465,7 +461,7 @@ i915_emit_state(struct intel_context *intel) } ADVANCE_BATCH(); - BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS); + BEGIN_BATCH(2 + nr * 3); OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr)); OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); for (i = 0; i < I915_TEX_UNITS; i++) diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index 63c5ae96dc..e99baf8e0e 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -89,7 +89,6 @@ intel_flush_inline_primitive(struct intel_context *intel) static void intel_start_inline(struct intel_context *intel, uint32_t prim) { - uint32_t batch_flags = LOOP_CLIPRECTS; BATCH_LOCALS; intel->vtbl.emit_state(intel); @@ -101,7 +100,7 @@ static void intel_start_inline(struct intel_context *intel, uint32_t prim) /* Emit a slot which will be filled with the inline primitive * command later. */ - BEGIN_BATCH(2, batch_flags); + BEGIN_BATCH(2); OUT_BATCH(0); assert((intel->batch->dirty_state & (1<<1)) == 0); @@ -252,7 +251,7 @@ void intel_flush_prim(struct intel_context *intel) #endif if (intel->gen >= 3) { - BEGIN_BATCH(5, LOOP_CLIPRECTS); + BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(0) | I1_LOAD_S(1) | 1); assert((offset & !S0_VB_OFFSET_MASK) == 0); @@ -270,7 +269,7 @@ void intel_flush_prim(struct intel_context *intel) } else { struct i830_context *i830 = i830_context(&intel->ctx); - BEGIN_BATCH(5, LOOP_CLIPRECTS); + BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(0) | I1_LOAD_S(2) | 1); /* S0 */ diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index aadcfbe2da..190310afbb 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -340,7 +340,7 @@ static void emit_constant_buffer(struct brw_context *brw) struct intel_context *intel = &brw->intel; GLuint sz = brw->curbe.total_size; - BEGIN_BATCH(2, IGNORE_CLIPRECTS); + BEGIN_BATCH(2); if (sz == 0) { OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2)); OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index f99d607d86..8d80c8bcfc 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -157,7 +157,7 @@ static void brw_emit_prim(struct brw_context *brw, } if (prim_packet.verts_per_instance) { intel_batchbuffer_data( brw->intel.batch, &prim_packet, - sizeof(prim_packet), LOOP_CLIPRECTS); + sizeof(prim_packet)); } if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(intel->batch); @@ -353,8 +353,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, * an upper bound of how much we might emit in a single * brw_try_draw_prims(). */ - intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4, - LOOP_CLIPRECTS); + intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4); hw_prim = brw_set_prim(brw, prim[i].mode); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 2c9902c90f..c773b71507 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -494,7 +494,7 @@ static void brw_emit_vertices(struct brw_context *brw) * a VE loads from them. */ if (brw->vb.nr_enabled == 0) { - BEGIN_BATCH(3, IGNORE_CLIPRECTS); + BEGIN_BATCH(3); OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1); OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) | BRW_VE0_VALID | @@ -514,7 +514,7 @@ static void brw_emit_vertices(struct brw_context *brw) * are interleaved or from the same VBO. TBD if this makes a * performance difference. */ - BEGIN_BATCH(1 + brw->vb.nr_enabled * 4, IGNORE_CLIPRECTS); + BEGIN_BATCH(1 + brw->vb.nr_enabled * 4); OUT_BATCH((CMD_VERTEX_BUFFER << 16) | ((1 + brw->vb.nr_enabled * 4) - 2)); @@ -537,7 +537,7 @@ static void brw_emit_vertices(struct brw_context *brw) } ADVANCE_BATCH(); - BEGIN_BATCH(1 + brw->vb.nr_enabled * 2, IGNORE_CLIPRECTS); + BEGIN_BATCH(1 + brw->vb.nr_enabled * 2); OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + brw->vb.nr_enabled * 2) - 2)); for (i = 0; i < brw->vb.nr_enabled; i++) { struct brw_vertex_element *input = brw->vb.enabled[i]; @@ -704,7 +704,7 @@ static void brw_emit_index_buffer(struct brw_context *brw) ib.header.bits.index_format = get_index_type(index_buffer->type); ib.header.bits.cut_index_enable = 0; - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH( ib.header.dword ); OUT_RELOC(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 2155feec84..1bd3979f9b 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -81,7 +81,7 @@ static void upload_drawing_rect(struct brw_context *brw) if (!intel->constant_cliprect) return; - BEGIN_BATCH(4, NO_LOOP_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965); OUT_BATCH(0); /* xmin, ymin */ OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) | @@ -116,7 +116,7 @@ static void upload_binding_table_pointers(struct brw_context *brw) { struct intel_context *intel = &brw->intel; - BEGIN_BATCH(6, IGNORE_CLIPRECTS); + BEGIN_BATCH(6); OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2)); if (brw->vs.bind_bo != NULL) OUT_RELOC(brw->vs.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* vs */ @@ -150,7 +150,7 @@ static void upload_pipelined_state_pointers(struct brw_context *brw ) { struct intel_context *intel = &brw->intel; - BEGIN_BATCH(7, IGNORE_CLIPRECTS); + BEGIN_BATCH(7); OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2)); OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); if (brw->gs.prog_active) @@ -215,7 +215,7 @@ static void emit_depthbuffer(struct brw_context *brw) unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5; if (region == NULL) { - BEGIN_BATCH(len, IGNORE_CLIPRECTS); + BEGIN_BATCH(len); OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29)); @@ -247,7 +247,7 @@ static void emit_depthbuffer(struct brw_context *brw) assert(region->tiling != I915_TILING_X); - BEGIN_BATCH(len, IGNORE_CLIPRECTS); + BEGIN_BATCH(len); OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | (format << 18) | @@ -513,7 +513,7 @@ static void upload_state_base_address( struct brw_context *brw ) * batchbuffer, so we can emit relocations inline. */ if (intel->is_ironlake) { - BEGIN_BATCH(8, IGNORE_CLIPRECTS); + BEGIN_BATCH(8); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); OUT_BATCH(1); /* General state base address */ OUT_BATCH(1); /* Surface state base address */ @@ -524,7 +524,7 @@ static void upload_state_base_address( struct brw_context *brw ) OUT_BATCH(1); /* Instruction access upper bound */ ADVANCE_BATCH(); } else { - BEGIN_BATCH(6, IGNORE_CLIPRECTS); + BEGIN_BATCH(6); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2)); OUT_BATCH(1); /* General state base address */ OUT_BATCH(1); /* Surface state base address */ diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index a195bc32b0..5399a74244 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -188,7 +188,7 @@ brw_emit_query_begin(struct brw_context *brw) if (brw->query.active || is_empty_list(&brw->query.active_head)) return; - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); @@ -227,7 +227,7 @@ brw_emit_query_end(struct brw_context *brw) if (!brw->query.active) return; - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 14d5319796..9c9d145c4b 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -151,7 +151,7 @@ void brw_state_cache_bo_delete(struct brw_cache *cache, dri_bo *bo); /*********************************************************************** * brw_state_batch.c */ -#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s)), IGNORE_CLIPRECTS) +#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s))) #define BRW_CACHED_BATCH_STRUCT(brw, s) brw_cached_batch_struct( brw, (s), sizeof(*(s)) ) GLboolean brw_cached_batch_struct( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c index 7821898cf9..ed8120d617 100644 --- a/src/mesa/drivers/dri/i965/brw_state_batch.c +++ b/src/mesa/drivers/dri/i965/brw_state_batch.c @@ -48,7 +48,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw, struct header *newheader = (struct header *)data; if (brw->emit_state_always) { - intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS); + intel_batchbuffer_data(brw->intel.batch, data, sz); return GL_TRUE; } @@ -75,7 +75,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw, emit: memcpy(item->header, newheader, sz); - intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS); + intel_batchbuffer_data(brw->intel.batch, data, sz); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 77a0159f18..3a4b21a844 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -94,7 +94,6 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch) batch->size = intel->maxBatchSize; batch->ptr = batch->map; batch->dirty_state = ~0; - batch->cliprect_mode = IGNORE_CLIPRECTS; } struct intel_batchbuffer * @@ -133,8 +132,6 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used) { struct intel_context *intel = batch->intel; int ret = 0; - unsigned int num_cliprects = 0; - struct drm_clip_rect *cliprects = NULL; int x_off = 0, y_off = 0; if (batch->buffer) @@ -145,19 +142,7 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used) batch->map = NULL; batch->ptr = NULL; - - if (batch->cliprect_mode == LOOP_CLIPRECTS) { - intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); - } - /* Dispatch the batchbuffer, if it has some effect (nonzero cliprects). - * Can't short-circuit like this once we have hardware contexts, but we - * should always be in DRI2 mode by then anyway. - */ - if ((batch->cliprect_mode != LOOP_CLIPRECTS || - num_cliprects != 0) && !intel->no_hw) { - dri_bo_exec(batch->buf, used, cliprects, num_cliprects, - (x_off & 0xffff) | (y_off << 16)); - } + dri_bo_exec(batch->buf, used, NULL, 0, (x_off & 0xffff) | (y_off << 16)); if (INTEL_DEBUG & DEBUG_BATCH) { dri_bo_map(batch->buf, GL_FALSE); @@ -187,10 +172,8 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, drm_intel_bo_reference(intel->first_post_swapbuffers_batch); } - if (used == 0) { - batch->cliprect_mode = IGNORE_CLIPRECTS; + if (used == 0) return; - } if (INTEL_DEBUG & DEBUG_BATCH) fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line, @@ -280,11 +263,10 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, void intel_batchbuffer_data(struct intel_batchbuffer *batch, - const void *data, GLuint bytes, - enum cliprect_mode cliprect_mode) + const void *data, GLuint bytes) { assert((bytes & 3) == 0); - intel_batchbuffer_require_space(batch, bytes, cliprect_mode); + intel_batchbuffer_require_space(batch, bytes); __memcpy(batch->ptr, data, bytes); batch->ptr += bytes; } @@ -301,7 +283,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) struct intel_context *intel = batch->intel; if (intel->gen >= 4) { - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_WRITE_FLUSH | @@ -311,7 +293,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); } else { - BEGIN_BATCH(1, IGNORE_CLIPRECTS); + BEGIN_BATCH(1); OUT_BATCH(MI_FLUSH); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index d4a94454dd..b052b724d8 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -10,35 +10,6 @@ #define BATCH_SZ 16384 #define BATCH_RESERVED 16 -enum cliprect_mode { - /** - * Batchbuffer contents may be looped over per cliprect, but do not - * require it. - */ - IGNORE_CLIPRECTS, - /** - * Batchbuffer contents require looping over per cliprect at batch submit - * time. - * - * This will be upgraded to NO_LOOP_CLIPRECTS when there's a single - * constant cliprect, as in DRI2 or FBO rendering. - */ - LOOP_CLIPRECTS, - /** - * Batchbuffer contents contain drawing that should not be executed multiple - * times. - */ - NO_LOOP_CLIPRECTS, - /** - * Batchbuffer contents contain drawing that already handles cliprects, such - * as 2D drawing to front/back/depth that doesn't respect DRAWING_RECTANGLE. - * - * Equivalent behavior to NO_LOOP_CLIPRECTS, but may not persist in batch - * outside of LOCK/UNLOCK. This is upgraded to just NO_LOOP_CLIPRECTS when - * there's a constant cliprect, as in DRI2 or FBO rendering. - */ - REFERENCES_CLIPRECTS -}; struct intel_batchbuffer { @@ -51,8 +22,6 @@ struct intel_batchbuffer GLubyte *map; GLubyte *ptr; - enum cliprect_mode cliprect_mode; - GLuint size; /** Tracking of BEGIN_BATCH()/OUT_BATCH()/ADVANCE_BATCH() debugging */ @@ -85,8 +54,7 @@ void intel_batchbuffer_reset(struct intel_batchbuffer *batch); * intel_buffer_dword() calls. */ void intel_batchbuffer_data(struct intel_batchbuffer *batch, - const void *data, GLuint bytes, - enum cliprect_mode cliprect_mode); + const void *data, GLuint bytes); void intel_batchbuffer_release_space(struct intel_batchbuffer *batch, GLuint bytes); @@ -121,36 +89,19 @@ intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, GLuint dword) static INLINE void intel_batchbuffer_require_space(struct intel_batchbuffer *batch, - GLuint sz, - enum cliprect_mode cliprect_mode) + GLuint sz) { assert(sz < batch->size - 8); if (intel_batchbuffer_space(batch) < sz) intel_batchbuffer_flush(batch); - - if ((cliprect_mode == LOOP_CLIPRECTS || - cliprect_mode == REFERENCES_CLIPRECTS) && - batch->intel->constant_cliprect) - cliprect_mode = NO_LOOP_CLIPRECTS; - - if (cliprect_mode != IGNORE_CLIPRECTS) { - if (batch->cliprect_mode == IGNORE_CLIPRECTS) { - batch->cliprect_mode = cliprect_mode; - } else { - if (batch->cliprect_mode != cliprect_mode) { - intel_batchbuffer_flush(batch); - batch->cliprect_mode = cliprect_mode; - } - } - } } /* Here are the crusty old macros, to be removed: */ #define BATCH_LOCALS -#define BEGIN_BATCH(n, cliprect_mode) do { \ - intel_batchbuffer_require_space(intel->batch, (n)*4, cliprect_mode); \ +#define BEGIN_BATCH(n) do { \ + intel_batchbuffer_require_space(intel->batch, (n)*4); \ assert(intel->batch->emit.start_ptr == NULL); \ intel->batch->emit.total = (n) * 4; \ intel->batch->emit.start_ptr = intel->batch->ptr; \ diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index c6e4341d71..55bee0084c 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -134,7 +134,7 @@ intelEmitCopyBlit(struct intel_context *intel, return GL_TRUE; } - intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); + intel_batchbuffer_require_space(intel->batch, 8 * 4); DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", __FUNCTION__, src_buffer, src_pitch, src_offset, src_x, src_y, @@ -179,7 +179,7 @@ intelEmitCopyBlit(struct intel_context *intel, assert(dst_x < dst_x2); assert(dst_y < dst_y2); - BEGIN_BATCH(8, NO_LOOP_CLIPRECTS); + BEGIN_BATCH(8); OUT_BATCH(CMD); OUT_BATCH(BR13 | (uint16_t)dst_pitch); OUT_BATCH((dst_y << 16) | dst_x); @@ -393,7 +393,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) assert(x1 < x2); assert(y1 < y2); - BEGIN_BATCH(6, REFERENCES_CLIPRECTS); + BEGIN_BATCH(6); OUT_BATCH(CMD); OUT_BATCH(BR13); OUT_BATCH((y1 << 16) | x1); @@ -449,8 +449,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, intel_batchbuffer_require_space( intel->batch, (8 * 4) + (3 * 4) + - dwords * 4, - REFERENCES_CLIPRECTS ); + dwords * 4 ); opcode = XY_SETUP_BLT_CMD; if (cpp == 4) @@ -472,7 +471,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, if (dst_tiling != I915_TILING_NONE) blit_cmd |= XY_DST_TILED; - BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS); + BEGIN_BATCH(8 + 3); OUT_BATCH(opcode); OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ @@ -491,8 +490,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, intel_batchbuffer_data( intel->batch, src_bits, - dwords * 4, - REFERENCES_CLIPRECTS ); + dwords * 4 ); intel_batchbuffer_emit_mi_flush(intel->batch); -- cgit v1.2.3 From 2861d9200be15cc44e8825387d3bd79086523c67 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 22:56:36 -0500 Subject: intel: Drop more cliprect bookkeeping --- src/mesa/drivers/dri/i915/i830_vtbl.c | 46 +++++++++---------------- src/mesa/drivers/dri/i915/i915_vtbl.c | 46 +++++++++---------------- src/mesa/drivers/dri/i965/brw_draw.c | 4 --- src/mesa/drivers/dri/i965/brw_misc_state.c | 3 -- src/mesa/drivers/dri/intel/intel_buffers.c | 54 +++++++----------------------- src/mesa/drivers/dri/intel/intel_context.h | 13 ------- 6 files changed, 44 insertions(+), 122 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_misc_state.c') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index f2a67bbb53..4471ca2bbb 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -487,16 +487,13 @@ i830_emit_state(struct intel_context *intel) } if (dirty & I830_UPLOAD_BUFFERS) { - GLuint count = 9; + GLuint count = 15; DBG("I830_UPLOAD_BUFFERS:\n"); if (state->depth_region) count += 3; - if (intel->constant_cliprect) - count += 6; - BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); @@ -519,15 +516,13 @@ i830_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I830_DESTREG_SR1]); OUT_BATCH(state->Buffer[I830_DESTREG_SR2]); - if (intel->constant_cliprect) { - assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]); - } + assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]); ADVANCE_BATCH(); } @@ -669,23 +664,14 @@ i830_state_draw_region(struct intel_context *intel, } state->Buffer[I830_DESTREG_DV1] = value; - if (intel->constant_cliprect) { - state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; - state->Buffer[I830_DESTREG_DRAWRECT1] = 0; - state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ - state->Buffer[I830_DESTREG_DRAWRECT3] = - (ctx->DrawBuffer->Width & 0xffff) | - (ctx->DrawBuffer->Height << 16); - state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ - state->Buffer[I830_DESTREG_DRAWRECT5] = 0; - } else { - state->Buffer[I830_DESTREG_DRAWRECT0] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT1] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT2] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT3] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT4] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP; - } + state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; + state->Buffer[I830_DESTREG_DRAWRECT1] = 0; + state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ + state->Buffer[I830_DESTREG_DRAWRECT3] = + (ctx->DrawBuffer->Width & 0xffff) | + (ctx->DrawBuffer->Height << 16); + state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ + state->Buffer[I830_DESTREG_DRAWRECT5] = 0; I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS); diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 251c54697b..266e6848c3 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -369,7 +369,7 @@ i915_emit_state(struct intel_context *intel) } if (dirty & I915_UPLOAD_BUFFERS) { - GLuint count = 9; + GLuint count = 15; if (INTEL_DEBUG & DEBUG_STATE) fprintf(stderr, "I915_UPLOAD_BUFFERS:\n"); @@ -377,9 +377,6 @@ i915_emit_state(struct intel_context *intel) if (state->depth_region) count += 3; - if (intel->constant_cliprect) - count += 6; - BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); @@ -402,15 +399,13 @@ i915_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I915_DESTREG_SR1]); OUT_BATCH(state->Buffer[I915_DESTREG_SR2]); - if (intel->constant_cliprect) { - assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]); - } + assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]); ADVANCE_BATCH(); } @@ -619,23 +614,14 @@ i915_state_draw_region(struct intel_context *intel, } state->Buffer[I915_DESTREG_DV1] = value; - if (intel->constant_cliprect) { - state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; - state->Buffer[I915_DESTREG_DRAWRECT1] = 0; - state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ - state->Buffer[I915_DESTREG_DRAWRECT3] = - (ctx->DrawBuffer->Width & 0xffff) | - (ctx->DrawBuffer->Height << 16); - state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ - state->Buffer[I915_DESTREG_DRAWRECT5] = 0; - } else { - state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP; - } + state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; + state->Buffer[I915_DESTREG_DRAWRECT1] = 0; + state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ + state->Buffer[I915_DESTREG_DRAWRECT3] = + (ctx->DrawBuffer->Width & 0xffff) | + (ctx->DrawBuffer->Height << 16); + state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ + state->Buffer[I915_DESTREG_DRAWRECT5] = 0; I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); } diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 8d80c8bcfc..df281b27d5 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -339,10 +339,6 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, * so can't access it earlier. */ - if (!intel->constant_cliprect && intel->driDrawable->numClipRects == 0) { - return GL_TRUE; - } - for (i = 0; i < nr_prims; i++) { uint32_t hw_prim; diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 1bd3979f9b..7b70f787b7 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -78,9 +78,6 @@ static void upload_drawing_rect(struct brw_context *brw) struct intel_context *intel = &brw->intel; GLcontext *ctx = &intel->ctx; - if (!intel->constant_cliprect) - return; - BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965); OUT_BATCH(0); /* xmin, ymin */ diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index 219b3603f7..7c4b79f743 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -102,33 +102,15 @@ intel_get_cliprects(struct intel_context *intel, unsigned int *num_cliprects, int *x_off, int *y_off) { - __DRIdrawable *dPriv = intel->driDrawable; - - if (intel->constant_cliprect) { - /* FBO or DRI2 rendering, which can just use the fb's size. */ - intel->fboRect.x1 = 0; - intel->fboRect.y1 = 0; - intel->fboRect.x2 = intel->ctx.DrawBuffer->Width; - intel->fboRect.y2 = intel->ctx.DrawBuffer->Height; - - *cliprects = &intel->fboRect; - *num_cliprects = 1; - *x_off = 0; - *y_off = 0; - } else if (intel->front_cliprects || dPriv->numBackClipRects == 0) { - /* use the front clip rects */ - *cliprects = dPriv->pClipRects; - *num_cliprects = dPriv->numClipRects; - *x_off = dPriv->x; - *y_off = dPriv->y; - } - else { - /* use the back clip rects */ - *num_cliprects = dPriv->numBackClipRects; - *cliprects = dPriv->pBackClipRects; - *x_off = dPriv->backX; - *y_off = dPriv->backY; - } + intel->fboRect.x1 = 0; + intel->fboRect.y1 = 0; + intel->fboRect.x2 = intel->ctx.DrawBuffer->Width; + intel->fboRect.y2 = intel->ctx.DrawBuffer->Height; + + *cliprects = &intel->fboRect; + *num_cliprects = 1; + *x_off = 0; + *y_off = 0; } @@ -202,7 +184,6 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) || (fb->_NumColorDrawBuffers == 0)) { /* writing to 0 */ colorRegions[0] = NULL; - intel->constant_cliprect = GL_TRUE; } else if (fb->_NumColorDrawBuffers > 1) { int i; @@ -212,34 +193,23 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); colorRegions[i] = irb ? irb->region : NULL; } - intel->constant_cliprect = GL_TRUE; } else { /* Get the intel_renderbuffer for the single colorbuffer we're drawing - * into, and set up cliprects if it's a DRI1 window front buffer. + * into. */ if (fb->Name == 0) { - intel->constant_cliprect = intel->driScreen->dri2.enabled; /* drawing to window system buffer */ - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - if (!intel->constant_cliprect && !intel->front_cliprects) - intel_batchbuffer_flush(intel->batch); - intel->front_cliprects = GL_TRUE; + if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT); - } - else { - if (!intel->constant_cliprect && intel->front_cliprects) - intel_batchbuffer_flush(intel->batch); - intel->front_cliprects = GL_FALSE; + else colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT); - } } else { /* drawing to user-created FBO */ struct intel_renderbuffer *irb; irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]); colorRegions[0] = (irb && irb->region) ? irb->region : NULL; - intel->constant_cliprect = GL_TRUE; } } diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index bd3166d64a..c7b7235836 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -247,19 +247,6 @@ struct intel_context intel_line_func draw_line; intel_tri_func draw_tri; - /** - * Set to true if a single constant cliprect should be used in the - * batchbuffer. Otherwise, cliprects must be calculated at batchbuffer - * flush time while the lock is held. - */ - GLboolean constant_cliprect; - - /** - * In !constant_cliprect mode, set to true if the front cliprects should be - * used instead of back. - */ - GLboolean front_cliprects; - /** * Set if rendering has occured to the drawable's front buffer. * -- cgit v1.2.3