From a1f2ac2b37b8291d1521169b171f6c3ea683cae7 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 25 Aug 2010 16:00:09 -0700 Subject: i965: Fix detection of implicit MOVs to message regs in brw_optimize.c. Texcoords in AmbientApertureLighting were getting trashed since the move of math arguments to implied moves, due to the logic for detecting ALU message reg writes overriding the logic for SEND implicit message reg writes. --- src/mesa/drivers/dri/i965/brw_optimize.c | 62 +++++++++++++++++++------------- 1 file changed, 38 insertions(+), 24 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_optimize.c') diff --git a/src/mesa/drivers/dri/i965/brw_optimize.c b/src/mesa/drivers/dri/i965/brw_optimize.c index 8aa6fb6cc6..afcd1fc15a 100644 --- a/src/mesa/drivers/dri/i965/brw_optimize.c +++ b/src/mesa/drivers/dri/i965/brw_optimize.c @@ -161,20 +161,19 @@ brw_is_grf_written(const struct brw_instruction *inst, return left < right; } -/* Specific path for message register since we need to handle the compr4 case */ -static INLINE GLboolean -brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size) +static GLboolean +brw_is_mrf_written_alu(const struct brw_instruction *inst, + int reg_index, int size) { if (inst_opcode[inst->header.opcode].ndst == 0) return GL_FALSE; - if (inst->bits1.da1.dest_address_mode != BRW_ADDRESS_DIRECT) - if (inst->bits1.ia1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE) - return GL_TRUE; - if (inst->bits1.da1.dest_reg_file != BRW_MESSAGE_REGISTER_FILE) return GL_FALSE; + if (inst->bits1.da1.dest_address_mode != BRW_ADDRESS_DIRECT) + return GL_TRUE; + const int reg_start = reg_index * REG_SIZE; const int reg_end = reg_start + size; @@ -188,8 +187,6 @@ brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size) if (is_compr4 && inst->header.execution_size != BRW_EXECUTE_16) return GL_TRUE; - GLboolean is_written = GL_FALSE; - /* Here we write mrf_{i} and mrf_{i+4}. So we read two times 8 elements */ if (is_compr4) { const int length = 8 * type_size * inst->bits1.da1.dest_horiz_stride; @@ -210,7 +207,8 @@ brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size) const int left1 = MAX2(write_start1, reg_start); const int right1 = MIN2(write_end1, reg_end); - is_written = left0 < right0 || left1 < right1; + if (left0 < right0 || left1 < right1) + return GL_TRUE; } else { int length; @@ -223,25 +221,41 @@ brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size) + inst->bits1.da1.dest_subreg_nr; const int write_end = write_start + length; const int left = MAX2(write_start, reg_start); - const int right = MIN2(write_end, reg_end);; + const int right = MIN2(write_end, reg_end); - is_written = left < right; + if (left < right) + return GL_TRUE; } - /* SEND may perform an implicit mov to a mrf register */ - if (is_written == GL_FALSE && - inst->header.opcode == BRW_OPCODE_SEND && - inst->bits1.da1.src0_reg_file != 0) { + return GL_FALSE; +} - const int mrf_start = inst->header.destreg__conditionalmod; - const int write_start = mrf_start * REG_SIZE; - const int write_end = write_start + REG_SIZE; - const int left = MAX2(write_start, reg_start); - const int right = MIN2(write_end, reg_end);; - is_written = left < right; - } +/* SEND may perform an implicit mov to a mrf register */ +static GLboolean brw_is_mrf_written_send(const struct brw_instruction *inst, + int reg_index, int size) +{ + + const int reg_start = reg_index * REG_SIZE; + const int reg_end = reg_start + size; + const int mrf_start = inst->header.destreg__conditionalmod; + const int write_start = mrf_start * REG_SIZE; + const int write_end = write_start + REG_SIZE; + const int left = MAX2(write_start, reg_start); + const int right = MIN2(write_end, reg_end); + + if (inst->header.opcode != BRW_OPCODE_SEND || + inst->bits1.da1.src0_reg_file == 0) + return GL_FALSE; - return is_written; + return left < right; +} + +/* Specific path for message register since we need to handle the compr4 case */ +static INLINE GLboolean +brw_is_mrf_written(const struct brw_instruction *inst, int reg_index, int size) +{ + return (brw_is_mrf_written_alu(inst, reg_index, size) || + brw_is_mrf_written_send(inst, reg_index, size)); } static INLINE GLboolean -- cgit v1.2.3 From a0ffee2cd79deb5a437784e25de6512d7f8e6bb8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 27 Aug 2010 12:53:48 -0700 Subject: i965: When encountering an unknown opcode in new FS backend, print its name. --- src/mesa/drivers/dri/i965/brw_context.h | 8 +++++++- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +++++++++- src/mesa/drivers/dri/i965/brw_optimize.c | 19 +++++++------------ 3 files changed, 23 insertions(+), 14 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_optimize.c') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 3728a7a122..703a7de78d 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -702,7 +702,13 @@ struct brw_context #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a) - +struct brw_instruction_info { + char *name; + int nsrc; + int ndst; + GLboolean is_arith; +}; +extern const struct brw_instruction_info brw_opcodes[128]; /*====================================================================== * brw_vtbl.c diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 673a31c1dd..41b8ecd681 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -369,6 +369,7 @@ public: this->p = &c->func; this->brw = p->brw; this->intel = &brw->intel; + this->ctx = &intel->ctx; this->mem_ctx = talloc_new(NULL); this->shader = shader; this->fail = false; @@ -431,6 +432,7 @@ public: struct brw_context *brw; struct intel_context *intel; + GLcontext *ctx; struct brw_wm_compile *c; struct brw_compile *p; struct brw_shader *shader; @@ -1453,7 +1455,13 @@ fs_visitor::generate_code() generate_fb_write(inst); break; default: - assert(!"not reached"); + if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) { + _mesa_problem(ctx, "Unsupported opcode `%s' in FS", + brw_opcodes[inst->opcode].name); + } else { + _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode); + } + this->fail = true; } if (annotation_len < p->nr_insn) { diff --git a/src/mesa/drivers/dri/i965/brw_optimize.c b/src/mesa/drivers/dri/i965/brw_optimize.c index afcd1fc15a..cbed2bd5cb 100644 --- a/src/mesa/drivers/dri/i965/brw_optimize.c +++ b/src/mesa/drivers/dri/i965/brw_optimize.c @@ -32,12 +32,7 @@ #include "brw_defines.h" #include "brw_eu.h" -static const struct { - char *name; - int nsrc; - int ndst; - GLboolean is_arith; -} inst_opcode[128] = { +const struct brw_instruction_info brw_opcodes[128] = { [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1, .is_arith = 1 }, [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1, .is_arith = 1 }, [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1, .is_arith = 1 }, @@ -94,7 +89,7 @@ static const struct { static INLINE GLboolean brw_is_arithmetic_inst(const struct brw_instruction *inst) { - return inst_opcode[inst->header.opcode].is_arith; + return brw_opcodes[inst->header.opcode].is_arith; } static const GLuint inst_stride[7] = { @@ -122,7 +117,7 @@ brw_is_grf_written(const struct brw_instruction *inst, int reg_index, int size, int gen) { - if (inst_opcode[inst->header.opcode].ndst == 0) + if (brw_opcodes[inst->header.opcode].ndst == 0) return GL_FALSE; if (inst->bits1.da1.dest_address_mode != BRW_ADDRESS_DIRECT) @@ -165,7 +160,7 @@ static GLboolean brw_is_mrf_written_alu(const struct brw_instruction *inst, int reg_index, int size) { - if (inst_opcode[inst->header.opcode].ndst == 0) + if (brw_opcodes[inst->header.opcode].ndst == 0) return GL_FALSE; if (inst->bits1.da1.dest_reg_file != BRW_MESSAGE_REGISTER_FILE) @@ -298,7 +293,7 @@ static INLINE GLboolean brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size) { int i, j; - if (inst_opcode[inst->header.opcode].nsrc == 0) + if (brw_opcodes[inst->header.opcode].nsrc == 0) return GL_FALSE; /* Look at first source. We must take into account register regions to @@ -306,7 +301,7 @@ brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size) * since we do not take into account the fact that some complete registers * may be skipped */ - if (inst_opcode[inst->header.opcode].nsrc >= 1) { + if (brw_opcodes[inst->header.opcode].nsrc >= 1) { if (inst->bits2.da1.src0_address_mode != BRW_ADDRESS_DIRECT) if (inst->bits1.ia1.src0_reg_file == BRW_GENERAL_REGISTER_FILE) @@ -341,7 +336,7 @@ brw_is_grf_read(const struct brw_instruction *inst, int reg_index, int size) } /* Second src register */ - if (inst_opcode[inst->header.opcode].nsrc >= 2) { + if (brw_opcodes[inst->header.opcode].nsrc >= 2) { if (inst->bits3.da1.src1_address_mode != BRW_ADDRESS_DIRECT) if (inst->bits1.ia1.src1_reg_file == BRW_GENERAL_REGISTER_FILE) -- cgit v1.2.3