From 00e5a743e2ee3981a34b95067a97fa73c0f5d779 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 1 Dec 2010 11:46:46 -0800 Subject: i965: Add support for gen6 BREAK ISA emit. There are now two targets: the hop-to-end-of-block target, and the target for where to resume execution for active channels. --- src/mesa/drivers/dri/i965/brw_structs.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/mesa/drivers/dri/i965/brw_structs.h') diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 8ce9af9c4f..8f97bd136f 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -1539,6 +1539,21 @@ struct brw_instruction GLuint pad0:12; } if_else; + struct + { + /* Signed jump distance to the ip to jump to if all channels + * are disabled after the break or continue. It should point + * to the end of the innermost control flow block, as that's + * where some channel could get re-enabled. + */ + int jip:16; + + /* Signed jump distance to the location to resume execution + * of this channel if it's enabled for the break or continue. + */ + int uip:16; + } break_cont; + struct { GLuint function:4; GLuint int_type:1; -- cgit v1.2.3 From 30f25a10190632a971e2b214c443e54afa463ead Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 15 Jun 2010 17:58:14 -0700 Subject: i965: Set up the correct texture border color state struct for Ironlake. This doesn't actually fix border color on Ironlake, but it appears to be a requirement, and gen6 needs it too. --- src/mesa/drivers/dri/i965/brw_structs.h | 9 ++++++ src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 41 +++++++++++++++++++++--- 2 files changed, 45 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_structs.h') diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 8f97bd136f..0e1f3c9bb8 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -1064,6 +1064,15 @@ struct brw_sampler_default_color { GLfloat color[4]; }; +struct gen5_sampler_default_color { + uint8_t ub[4]; + float f[4]; + uint16_t hf[4]; + uint16_t us[4]; + int16_t s[4]; + uint8_t b[4]; +}; + struct brw_sampler_state { diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index fea96d3538..e7c97a1cb0 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -69,12 +69,43 @@ static GLuint translate_wrap_mode( GLenum wrap ) static drm_intel_bo *upload_default_color( struct brw_context *brw, const GLfloat *color ) { - struct brw_sampler_default_color sdc; + struct intel_context *intel = &brw->intel; - COPY_4V(sdc.color, color); - - return brw_cache_data(&brw->cache, BRW_SAMPLER_DEFAULT_COLOR, - &sdc, sizeof(sdc)); + if (intel->gen >= 5) { + struct gen5_sampler_default_color sdc; + + memset(&sdc, 0, sizeof(sdc)); + + UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[0], color[0]); + UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[1], color[1]); + UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[2], color[2]); + UNCLAMPED_FLOAT_TO_UBYTE(sdc.ub[3], color[3]); + + UNCLAMPED_FLOAT_TO_USHORT(sdc.us[0], color[0]); + UNCLAMPED_FLOAT_TO_USHORT(sdc.us[1], color[1]); + UNCLAMPED_FLOAT_TO_USHORT(sdc.us[2], color[2]); + UNCLAMPED_FLOAT_TO_USHORT(sdc.us[3], color[3]); + + UNCLAMPED_FLOAT_TO_SHORT(sdc.s[0], color[0]); + UNCLAMPED_FLOAT_TO_SHORT(sdc.s[1], color[1]); + UNCLAMPED_FLOAT_TO_SHORT(sdc.s[2], color[2]); + UNCLAMPED_FLOAT_TO_SHORT(sdc.s[3], color[3]); + + /* XXX: Fill in half floats */ + /* XXX: Fill in signed bytes */ + + COPY_4V(sdc.f, color); + + return brw_cache_data(&brw->cache, BRW_SAMPLER_DEFAULT_COLOR, + &sdc, sizeof(sdc)); + } else { + struct brw_sampler_default_color sdc; + + COPY_4V(sdc.color, color); + + return brw_cache_data(&brw->cache, BRW_SAMPLER_DEFAULT_COLOR, + &sdc, sizeof(sdc)); + } } -- cgit v1.2.3 From cfcc2ef587fad91ad1dff1abbd42886dbe9cc095 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 9 Dec 2010 10:03:49 -0800 Subject: i965: Set render_cache_read_write surface state bit on gen6 constant surfs. This is said to be required in the spec, even when you aren't doing writes. --- src/mesa/drivers/dri/i965/brw_structs.h | 5 +++++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 ++++ 2 files changed, 9 insertions(+) (limited to 'src/mesa/drivers/dri/i965/brw_structs.h') diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 0e1f3c9bb8..d341187c1b 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -1179,6 +1179,11 @@ struct brw_surface_state GLuint cube_pos_x:1; GLuint cube_neg_x:1; GLuint pad:4; + /* Required on gen6 for surfaces accessed through render cache messages. + */ + GLuint render_cache_read_write:1; + /* Ironlake and newer: instead of replicating one of the texels */ + GLuint cube_corner_average:1; GLuint mipmap_layout_mode:1; GLuint vert_line_stride_ofs:1; GLuint vert_line_stride:1; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 76fc94df1f..fb0e34e94f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -274,6 +274,7 @@ brw_create_constant_surface(struct brw_context *brw, drm_intel_bo **out_bo, uint32_t *out_offset) { + struct intel_context *intel = &brw->intel; const GLint w = width - 1; struct brw_surface_state surf; void *map; @@ -284,6 +285,9 @@ brw_create_constant_surface(struct brw_context *brw, surf.ss0.surface_type = BRW_SURFACE_BUFFER; surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT; + if (intel->gen >= 6) + surf.ss0.render_cache_read_write = 1; + assert(bo); surf.ss1.base_addr = bo->offset; /* reloc */ -- cgit v1.2.3 From 834cc8e501c2632fd8f9fc78502a1a99803e6fb9 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 9 Dec 2010 11:10:31 -0800 Subject: i965: remove unused variable since brw_wm_glsl.c removal. --- src/mesa/drivers/dri/i965/brw_structs.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_state.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965/brw_structs.h') diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index d341187c1b..461f27048c 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -1178,7 +1178,7 @@ struct brw_surface_state GLuint cube_neg_y:1; GLuint cube_pos_x:1; GLuint cube_neg_x:1; - GLuint pad:4; + GLuint pad:2; /* Required on gen6 for surfaces accessed through render cache messages. */ GLuint render_cache_read_write:1; diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 82835470a3..e9ef635bca 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -87,7 +87,6 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) { struct gl_context *ctx = &brw->intel.ctx; const struct gl_fragment_program *fp = brw->fragment_program; - const struct brw_fragment_program *bfp = (struct brw_fragment_program *) fp; struct intel_context *intel = &brw->intel; memset(key, 0, sizeof(*key)); -- cgit v1.2.3