From f44916414ecd2b888c8a680d56b7467ccdff6886 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 5 Aug 2009 20:12:15 -0700 Subject: i965: Fix source depth reg setting for FSes reading and writing to depth. For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. --- src/mesa/drivers/dri/i965/brw_wm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/i965/brw_wm.h') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index ba497432c6..9eda2cb7ca 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -292,6 +292,7 @@ void brw_wm_print_program( struct brw_wm_compile *c, void brw_wm_lookup_iz( GLuint line_aa, GLuint lookup, + GLboolean ps_uses_depth, struct brw_wm_prog_key *key ); GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp); -- cgit v1.2.3