From 520b64ddfb4c2efa742bc2217fef96fdec5eea9b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 26 Nov 2009 22:03:43 -0800 Subject: i965: Add untested passthrough GS setup. --- src/mesa/drivers/dri/i965/gen6_gs_state.c | 74 +++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 src/mesa/drivers/dri/i965/gen6_gs_state.c (limited to 'src/mesa/drivers/dri/i965/gen6_gs_state.c') diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c new file mode 100644 index 0000000000..3a16bd368c --- /dev/null +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -0,0 +1,74 @@ +/* + * Copyright © 2009 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include "brw_context.h" +#include "brw_state.h" +#include "brw_defines.h" +#include "brw_util.h" +#include "main/macros.h" +#include "main/enums.h" +#include "intel_batchbuffer.h" + +static void +upload_gs_state(struct brw_context *brw) +{ + struct intel_context *intel = &brw->intel; + + BEGIN_BATCH(6); + OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2)); + OUT_BATCH(0); /* prog_bo */ + /* OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */ + OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | + (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | + (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) | + (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); + OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | + GEN6_GS_STATISTICS_ENABLE); + ADVANCE_BATCH(); + + /* Disable all the constant buffers. */ + BEGIN_BATCH(5); + OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); +} + +const struct brw_tracked_state gen6_gs_state = { + .dirty = { + .mesa = _NEW_TRANSFORM, + .brw = (BRW_NEW_CURBE_OFFSETS | + BRW_NEW_URB_FENCE | + BRW_NEW_CONTEXT), + .cache = CACHE_NEW_GS_PROG + }, + .emit = upload_gs_state, +}; -- cgit v1.2.3 From 98f9666f04eed9ae873fdea20c4c4b9db6cead84 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 3 Dec 2009 15:04:37 -0800 Subject: i965: Get vp-tri batchbuffers running (no rendering). --- src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- src/mesa/drivers/dri/i965/gen6_gs_state.c | 40 +++++++++++++++++++--------- src/mesa/drivers/dri/i965/gen6_vs_state.c | 3 +-- 3 files changed, 29 insertions(+), 16 deletions(-) (limited to 'src/mesa/drivers/dri/i965/gen6_gs_state.c') diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 9f5d789e1e..f5446ed73b 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -106,10 +106,10 @@ const struct brw_tracked_state *gen6_atoms[] = { &brw_check_fallback, -#if 0 &brw_wm_input_sizes, &brw_vs_prog, &brw_gs_prog, +#if 0 &brw_sf_prog, &brw_wm_prog, diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 3a16bd368c..31da0dc088 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -38,19 +38,33 @@ upload_gs_state(struct brw_context *brw) { struct intel_context *intel = &brw->intel; - BEGIN_BATCH(6); - OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2)); - OUT_BATCH(0); /* prog_bo */ - /* OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */ - OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | - (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); - OUT_BATCH(0); /* scratch space base offset */ - OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | - (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) | - (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); - OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | - GEN6_GS_STATISTICS_ENABLE); - ADVANCE_BATCH(); + if (brw->gs.prog_bo) { + BEGIN_BATCH(6); + OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2)); + OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); + OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | + (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | + (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) | + (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); + OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | + GEN6_GS_STATISTICS_ENABLE); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(6); + OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2)); + OUT_BATCH(0); /* prog_bo */ + OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | + (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | + (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) | + (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); + OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | + GEN6_GS_STATISTICS_ENABLE); + ADVANCE_BATCH(); + } /* Disable all the constant buffers. */ BEGIN_BATCH(5); diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 4caabf32b0..d82319afa7 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -40,8 +40,7 @@ upload_vs_state(struct brw_context *brw) BEGIN_BATCH(6); OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2)); - OUT_BATCH(0); /* prog_bo */ - /* OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); */ + OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); OUT_BATCH(0); /* scratch space base offset */ -- cgit v1.2.3 From d971375bc1872cb2d95a710e3d62f5b037fbe7f7 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 29 Jan 2010 10:42:17 -0800 Subject: i965: Giant pile of flushing to track down SNB bringup issues. This should go away before we push the code. --- src/mesa/drivers/dri/i965/gen6_cc.c | 2 ++ src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 ++ src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 ++ src/mesa/drivers/dri/i965/gen6_urb.c | 2 ++ src/mesa/drivers/dri/i965/gen6_vs_state.c | 4 ++++ 5 files changed, 12 insertions(+) (limited to 'src/mesa/drivers/dri/i965/gen6_gs_state.c') diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c index b1b6dc7db3..ba1e3abe83 100644 --- a/src/mesa/drivers/dri/i965/gen6_cc.c +++ b/src/mesa/drivers/dri/i965/gen6_cc.c @@ -273,6 +273,8 @@ static void upload_cc_state_pointers(struct brw_context *brw) OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c index f34e5f32cc..5ddfa9aad2 100644 --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c @@ -64,6 +64,8 @@ upload_clip_state(struct brw_context *brw) provoking); OUT_BATCH(0); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_clip_state = { diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 31da0dc088..47702f7f30 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -74,6 +74,8 @@ upload_gs_state(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_gs_state = { diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index dea0aa7100..55f7ac7727 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -68,6 +68,8 @@ upload_urb(struct brw_context *brw) OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) | ((brw->urb.nr_gs_entries) << GEN6_URB_GS_SIZE_SHIFT)); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_urb = { diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 0202871399..ba00e4e1fb 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -59,6 +59,8 @@ upload_vs_state(struct brw_context *brw) GEN6_VS_STATISTICS_ENABLE); ADVANCE_BATCH(); + intel_batchbuffer_emit_mi_flush(intel->batch); + if (vp->use_const_buffer || nr_params == 0) { /* Disable the push constant buffers. */ BEGIN_BATCH(5); @@ -102,6 +104,8 @@ upload_vs_state(struct brw_context *brw) drm_intel_bo_unreference(constant_bo); } + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_vs_state = { -- cgit v1.2.3 From dd743fa36fa9303c2a2d0e7d3798fdc00ef43287 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 17 Dec 2009 18:41:18 -0800 Subject: i965: Fixup Sandybridge GS packet from doc updates. --- src/mesa/drivers/dri/i965/gen6_gs_state.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965/gen6_gs_state.c') diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 47702f7f30..761059c96a 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -39,8 +39,8 @@ upload_gs_state(struct brw_context *brw) struct intel_context *intel = &brw->intel; if (brw->gs.prog_bo) { - BEGIN_BATCH(6); - OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2)); + BEGIN_BATCH(7); + OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2)); OUT_RELOC(brw->gs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); @@ -50,10 +50,11 @@ upload_gs_state(struct brw_context *brw) (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | GEN6_GS_STATISTICS_ENABLE); + OUT_BATCH(GEN6_GS_ENABLE); ADVANCE_BATCH(); } else { - BEGIN_BATCH(6); - OUT_BATCH(CMD_3D_GS_STATE << 16 | (6 - 2)); + BEGIN_BATCH(7); + OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2)); OUT_BATCH(0); /* prog_bo */ OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); @@ -63,6 +64,7 @@ upload_gs_state(struct brw_context *brw) (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | GEN6_GS_STATISTICS_ENABLE); + OUT_BATCH(0); ADVANCE_BATCH(); } -- cgit v1.2.3 From 5878c841e90a8006715877045aa95a752472eaab Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 1 Feb 2010 09:41:26 -0800 Subject: i965: Set GS rendering enabled even when the GS stage is disabled. This is copying the behavior of other drivers. --- src/mesa/drivers/dri/i965/gen6_gs_state.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965/gen6_gs_state.c') diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 761059c96a..9a4a13810a 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -49,7 +49,8 @@ upload_gs_state(struct brw_context *brw) (brw->gs.prog_data->urb_read_length << GEN6_GS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | - GEN6_GS_STATISTICS_ENABLE); + GEN6_GS_STATISTICS_ENABLE | + GEN6_GS_RENDERING_ENABLE); OUT_BATCH(GEN6_GS_ENABLE); ADVANCE_BATCH(); } else { @@ -63,7 +64,8 @@ upload_gs_state(struct brw_context *brw) (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) | (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) | - GEN6_GS_STATISTICS_ENABLE); + GEN6_GS_STATISTICS_ENABLE | + GEN6_GS_RENDERING_ENABLE); OUT_BATCH(0); ADVANCE_BATCH(); } -- cgit v1.2.3 From 078e7b62f69658e40aedea59cf6f005162a29f83 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 23 Feb 2010 17:42:20 -0800 Subject: i965: Emit SNB FF unit state after the unit's push constants. There's a BUN for the WM unit that says WM_STATE must immediately follow PS_CONSTANTS, which this addresses. Presumably other units are roughly the same, too. --- src/mesa/drivers/dri/i965/gen6_gs_state.c | 22 ++++---- src/mesa/drivers/dri/i965/gen6_vs_state.c | 30 +++++------ src/mesa/drivers/dri/i965/gen6_wm_state.c | 86 +++++++++++++++---------------- 3 files changed, 69 insertions(+), 69 deletions(-) (limited to 'src/mesa/drivers/dri/i965/gen6_gs_state.c') diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 9a4a13810a..4032605a85 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -38,6 +38,17 @@ upload_gs_state(struct brw_context *brw) { struct intel_context *intel = &brw->intel; + /* Disable all the constant buffers. */ + BEGIN_BATCH(5); + OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); + if (brw->gs.prog_bo) { BEGIN_BATCH(7); OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2)); @@ -69,17 +80,6 @@ upload_gs_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } - - /* Disable all the constant buffers. */ - BEGIN_BATCH(5); - OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - - intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_gs_state = { diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index ba00e4e1fb..04fc16e679 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -46,21 +46,6 @@ upload_vs_state(struct brw_context *brw) drm_intel_bo *constant_bo; int i; - BEGIN_BATCH(6); - OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2)); - OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); - OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | - (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); - OUT_BATCH(0); /* scratch space base offset */ - OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) | - (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | - (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); - OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) | - GEN6_VS_STATISTICS_ENABLE); - ADVANCE_BATCH(); - - intel_batchbuffer_emit_mi_flush(intel->batch); - if (vp->use_const_buffer || nr_params == 0) { /* Disable the push constant buffers. */ BEGIN_BATCH(5); @@ -106,6 +91,21 @@ upload_vs_state(struct brw_context *brw) } intel_batchbuffer_emit_mi_flush(intel->batch); + + BEGIN_BATCH(6); + OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2)); + OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); + OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | + (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(0); /* scratch space base offset */ + OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) | + (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) | + (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT)); + OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) | + GEN6_VS_STATISTICS_ENABLE); + ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_vs_state = { diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c index d896f7dcc0..f4ae7ed750 100644 --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c @@ -47,6 +47,49 @@ upload_wm_state(struct brw_context *brw) int i; uint32_t dw2, dw4, dw5, dw6; + if (fp->use_const_buffer || nr_params == 0) { + /* Disable the push constant buffers. */ + BEGIN_BATCH(5); + OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } else { + /* Updates the ParamaterValues[i] pointers for all parameters of the + * basic type of PROGRAM_STATE_VAR. + */ + _mesa_load_state_parameters(ctx, fp->program.Base.Parameters); + + constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo", + nr_params * 4 * sizeof(float), + 4096); + intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE); + for (i = 0; i < nr_params; i++) { + memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float), + fp->program.Base.Parameters->ParameterValues[i], + 4 * sizeof(float)); + } + intel_bo_unmap_gtt_preferred(intel, constant_bo); + + BEGIN_BATCH(5); + OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | + GEN6_CONSTANT_BUFFER_0_ENABLE | + (5 - 2)); + OUT_RELOC(constant_bo, + I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */ + ALIGN(nr_params, 2) / 2 - 1); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + + drm_intel_bo_unreference(constant_bo); + } + + intel_batchbuffer_emit_mi_flush(intel->batch); + dw2 = dw4 = dw5 = dw6 = 0; dw4 |= GEN6_WM_STATISTICS_ENABLE; dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0; @@ -103,49 +146,6 @@ upload_wm_state(struct brw_context *brw) ADVANCE_BATCH(); intel_batchbuffer_emit_mi_flush(intel->batch); - - if (fp->use_const_buffer || nr_params == 0) { - /* Disable the push constant buffers. */ - BEGIN_BATCH(5); - OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - } else { - /* Updates the ParamaterValues[i] pointers for all parameters of the - * basic type of PROGRAM_STATE_VAR. - */ - _mesa_load_state_parameters(ctx, fp->program.Base.Parameters); - - constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo", - nr_params * 4 * sizeof(float), - 4096); - intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE); - for (i = 0; i < nr_params; i++) { - memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float), - fp->program.Base.Parameters->ParameterValues[i], - 4 * sizeof(float)); - } - intel_bo_unmap_gtt_preferred(intel, constant_bo); - - BEGIN_BATCH(5); - OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | - GEN6_CONSTANT_BUFFER_0_ENABLE | - (5 - 2)); - OUT_RELOC(constant_bo, - I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */ - ALIGN(nr_params, 2) / 2 - 1); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); - - drm_intel_bo_unreference(constant_bo); - } - - intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_wm_state = { -- cgit v1.2.3 From c76d4db25260dd68684bf784efacd7323c7cab8b Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Thu, 25 Feb 2010 23:51:05 -0800 Subject: i965: Remove unnecessary headers. --- src/mesa/drivers/dri/i965/gen6_cc.c | 2 -- src/mesa/drivers/dri/i965/gen6_clip_state.c | 3 --- src/mesa/drivers/dri/i965/gen6_depthstencil.c | 4 ---- src/mesa/drivers/dri/i965/gen6_gs_state.c | 3 --- src/mesa/drivers/dri/i965/gen6_sampler_state.c | 3 --- src/mesa/drivers/dri/i965/gen6_scissor_state.c | 3 --- src/mesa/drivers/dri/i965/gen6_sf_state.c | 1 - src/mesa/drivers/dri/i965/gen6_viewport_state.c | 2 -- src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 -- src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 -- 10 files changed, 25 deletions(-) (limited to 'src/mesa/drivers/dri/i965/gen6_gs_state.c') diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c index ba1e3abe83..65e16e70c7 100644 --- a/src/mesa/drivers/dri/i965/gen6_cc.c +++ b/src/mesa/drivers/dri/i965/gen6_cc.c @@ -30,8 +30,6 @@ #include "brw_defines.h" #include "brw_util.h" #include "intel_batchbuffer.h" -#include "main/macros.h" -#include "main/enums.h" struct brw_blend_state_key { GLboolean color_blend, alpha_enabled; diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c index 9fabd05341..06f8145e32 100644 --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c @@ -28,9 +28,6 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" -#include "brw_util.h" -#include "main/macros.h" -#include "main/enums.h" #include "intel_batchbuffer.h" static void diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c index 960927164c..4924f0fd55 100644 --- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c +++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c @@ -27,10 +27,6 @@ #include "brw_context.h" #include "brw_state.h" -#include "brw_defines.h" -#include "brw_util.h" -#include "main/macros.h" -#include "main/enums.h" struct brw_depth_stencil_state_key { GLenum depth_func; diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 4032605a85..161e7b85c2 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -28,9 +28,6 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" -#include "brw_util.h" -#include "main/macros.h" -#include "main/enums.h" #include "intel_batchbuffer.h" static void diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c index f5d537b1cf..ab8e7516d2 100644 --- a/src/mesa/drivers/dri/i965/gen6_sampler_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c @@ -28,10 +28,7 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" -#include "brw_util.h" #include "intel_batchbuffer.h" -#include "main/macros.h" -#include "main/enums.h" static void upload_sampler_state_pointers(struct brw_context *brw) diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c index 81ebbf4ddf..2e21e5f733 100644 --- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c +++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c @@ -28,10 +28,7 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" -#include "brw_util.h" #include "intel_batchbuffer.h" -#include "main/macros.h" -#include "main/enums.h" static void prepare_scissor_state(struct brw_context *brw) diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c index 548cdb9fca..08e6753a91 100644 --- a/src/mesa/drivers/dri/i965/gen6_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c @@ -30,7 +30,6 @@ #include "brw_defines.h" #include "brw_util.h" #include "main/macros.h" -#include "main/enums.h" #include "intel_batchbuffer.h" static void diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c b/src/mesa/drivers/dri/i965/gen6_viewport_state.c index df3cbfb224..0c2aa4206c 100644 --- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c +++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c @@ -28,10 +28,8 @@ #include "brw_context.h" #include "brw_state.h" #include "brw_defines.h" -#include "brw_util.h" #include "intel_batchbuffer.h" #include "main/macros.h" -#include "main/enums.h" /* The clip VP defines the guardband region where expensive clipping is skipped * and fragments are allowed to be generated and clipped out cheaply by the SF. diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 04fc16e679..211a6231c9 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -29,8 +29,6 @@ #include "brw_state.h" #include "brw_defines.h" #include "brw_util.h" -#include "main/macros.h" -#include "main/enums.h" #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" #include "intel_batchbuffer.h" diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c index f4ae7ed750..e355261769 100644 --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c @@ -29,8 +29,6 @@ #include "brw_state.h" #include "brw_defines.h" #include "brw_util.h" -#include "main/macros.h" -#include "main/enums.h" #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" #include "intel_batchbuffer.h" -- cgit v1.2.3