From c9dc6d425e645f2988118ff51cabe167a0cd3971 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 3 Dec 2009 17:08:32 -0800 Subject: i965: Set up the SNB URB. even with vs disabled, still doesn't work. --- src/mesa/drivers/dri/i965/gen6_urb.c | 81 ++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 src/mesa/drivers/dri/i965/gen6_urb.c (limited to 'src/mesa/drivers/dri/i965/gen6_urb.c') diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c new file mode 100644 index 0000000000..dea0aa7100 --- /dev/null +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -0,0 +1,81 @@ +/* + * Copyright © 2009 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include "main/macros.h" +#include "intel_batchbuffer.h" +#include "brw_context.h" +#include "brw_state.h" +#include "brw_defines.h" + +static void +prepare_urb( struct brw_context *brw ) +{ + brw->urb.nr_vs_entries = 24; + if (brw->gs.prog_bo) + brw->urb.nr_gs_entries = 4; + else + brw->urb.nr_gs_entries = 0; + /* CACHE_NEW_VS_PROG */ + brw->urb.vs_size = MIN2(brw->vs.prog_data->urb_entry_size, 1); + + /* Check that the number of URB rows (8 floats each) allocated is less + * than the URB space. + */ + assert((brw->urb.nr_vs_entries + + brw->urb.nr_gs_entries) * brw->urb.vs_size * 8 < 64 * 1024); +} + +static void +upload_urb(struct brw_context *brw) +{ + struct intel_context *intel = &brw->intel; + + assert(brw->urb.nr_vs_entries % 4 == 0); + assert(brw->urb.nr_gs_entries % 4 == 0); + /* GS requirement */ + assert(!brw->gs.prog_bo || brw->urb.vs_size < 5); + + intel_batchbuffer_emit_mi_flush(intel->batch); + + BEGIN_BATCH(3); + OUT_BATCH(CMD_URB << 16 | (3 - 2)); + OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) | + ((brw->urb.nr_vs_entries) << GEN6_URB_VS_SIZE_SHIFT)); + OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) | + ((brw->urb.nr_gs_entries) << GEN6_URB_GS_SIZE_SHIFT)); + ADVANCE_BATCH(); +} + +const struct brw_tracked_state gen6_urb = { + .dirty = { + .mesa = 0, + .brw = BRW_NEW_CONTEXT, + .cache = CACHE_NEW_VS_PROG, + }, + .prepare = prepare_urb, + .emit = upload_urb, +}; -- cgit v1.2.3 From d971375bc1872cb2d95a710e3d62f5b037fbe7f7 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 29 Jan 2010 10:42:17 -0800 Subject: i965: Giant pile of flushing to track down SNB bringup issues. This should go away before we push the code. --- src/mesa/drivers/dri/i965/gen6_cc.c | 2 ++ src/mesa/drivers/dri/i965/gen6_clip_state.c | 2 ++ src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 ++ src/mesa/drivers/dri/i965/gen6_urb.c | 2 ++ src/mesa/drivers/dri/i965/gen6_vs_state.c | 4 ++++ 5 files changed, 12 insertions(+) (limited to 'src/mesa/drivers/dri/i965/gen6_urb.c') diff --git a/src/mesa/drivers/dri/i965/gen6_cc.c b/src/mesa/drivers/dri/i965/gen6_cc.c index b1b6dc7db3..ba1e3abe83 100644 --- a/src/mesa/drivers/dri/i965/gen6_cc.c +++ b/src/mesa/drivers/dri/i965/gen6_cc.c @@ -273,6 +273,8 @@ static void upload_cc_state_pointers(struct brw_context *brw) OUT_RELOC(brw->cc.blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); OUT_RELOC(brw->cc.depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c index f34e5f32cc..5ddfa9aad2 100644 --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c @@ -64,6 +64,8 @@ upload_clip_state(struct brw_context *brw) provoking); OUT_BATCH(0); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_clip_state = { diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c b/src/mesa/drivers/dri/i965/gen6_gs_state.c index 31da0dc088..47702f7f30 100644 --- a/src/mesa/drivers/dri/i965/gen6_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c @@ -74,6 +74,8 @@ upload_gs_state(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_gs_state = { diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index dea0aa7100..55f7ac7727 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -68,6 +68,8 @@ upload_urb(struct brw_context *brw) OUT_BATCH(((brw->urb.vs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) | ((brw->urb.nr_gs_entries) << GEN6_URB_GS_SIZE_SHIFT)); ADVANCE_BATCH(); + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_urb = { diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index 0202871399..ba00e4e1fb 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -59,6 +59,8 @@ upload_vs_state(struct brw_context *brw) GEN6_VS_STATISTICS_ENABLE); ADVANCE_BATCH(); + intel_batchbuffer_emit_mi_flush(intel->batch); + if (vp->use_const_buffer || nr_params == 0) { /* Disable the push constant buffers. */ BEGIN_BATCH(5); @@ -102,6 +104,8 @@ upload_vs_state(struct brw_context *brw) drm_intel_bo_unreference(constant_bo); } + + intel_batchbuffer_emit_mi_flush(intel->batch); } const struct brw_tracked_state gen6_vs_state = { -- cgit v1.2.3