From 05362682672f5edbd57437fa29c3d5d7d2ad7aba Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Tue, 22 Aug 2006 23:29:03 +0800
Subject: adding pci id of Crestline

---
 src/mesa/drivers/dri/i965/intel_context.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mesa/drivers/dri/i965/intel_context.c')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index d13e287fa7..5fc3d7150c 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -117,6 +117,9 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
       case PCI_CHIP_I946_GZ:
 	 chipset = "Intel(R) 946GZ"; break;
          break;
+      case PCI_CHIP_CRESTLINE:
+	 chipset = "Intel(R) Crestline"; break;
+         break;
       default:
 	 chipset = "Unknown Intel Chipset"; break;
       }
-- 
cgit v1.2.3


From aeda4c589ada4e6304577e55d55b5c50bc274793 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Wed, 13 Dec 2006 13:25:12 -0800
Subject: ARB_occlusion_query support

---
 src/mesa/drivers/dri/i965/brw_wm_state.c       |  2 +-
 src/mesa/drivers/dri/i965/intel_context.c      | 34 ++++++++++++++++++++++++++
 src/mesa/drivers/dri/i965/intel_context.h      |  1 +
 src/mesa/drivers/dri/i965/server/i830_common.h | 19 ++++++++++++++
 4 files changed, 55 insertions(+), 1 deletion(-)

(limited to 'src/mesa/drivers/dri/i965/intel_context.c')

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 4707a709e7..e41042d6d2 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -168,7 +168,7 @@ static void upload_wm_unit(struct brw_context *brw )
       wm.wm5.line_stipple = 1;
    }
 
-   if (INTEL_DEBUG & DEBUG_STATS)
+   if (INTEL_DEBUG & DEBUG_STATS || intel->stats_wm)
       wm.wm4.stats_enable = 1;
 
    brw->wm.state_gs_offset = brw_cache_data( &brw->cache[BRW_WM_UNIT], &wm );
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 5fc3d7150c..6bcc984285 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -70,6 +70,7 @@ int INTEL_DEBUG = (0);
 #define need_GL_ARB_vertex_buffer_object
 #define need_GL_ARB_vertex_program
 #define need_GL_ARB_window_pos
+#define need_GL_ARB_occlusion_query
 #define need_GL_EXT_blend_color
 #define need_GL_EXT_blend_equation_separate
 #define need_GL_EXT_blend_func_separate
@@ -160,6 +161,7 @@ const struct dri_extension card_extensions[] =
     { "GL_ARB_vertex_buffer_object",       GL_ARB_vertex_buffer_object_functions },
     { "GL_ARB_vertex_program",             GL_ARB_vertex_program_functions },
     { "GL_ARB_window_pos",                 GL_ARB_window_pos_functions },
+    { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions},
     { "GL_EXT_blend_color",                GL_EXT_blend_color_functions },
     { "GL_EXT_blend_equation_separate",    GL_EXT_blend_equation_separate_functions },
     { "GL_EXT_blend_func_separate",        GL_EXT_blend_func_separate_functions },
@@ -244,6 +246,36 @@ void intelFinish( GLcontext *ctx )
    bmFinishFence(intel, bmLockAndFence(intel));
 }
 
+static void
+intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+	struct intel_context *intel = intel_context( ctx );
+	GLuint64EXT tmp = 0;	
+	drmI830MMIO io = {
+		.read_write = MMIO_WRITE,
+		.reg = MMIO_REGS_PS_DEPTH_COUNT,
+		.data = &tmp 
+	};
+	intel->stats_wm = GL_TRUE;
+	intelFinish(&intel->ctx);
+	drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+}
+
+static void
+intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
+{
+	struct intel_context *intel = intel_context( ctx );
+	drmI830MMIO io = {
+		.read_write = MMIO_READ,
+		.reg = MMIO_REGS_PS_DEPTH_COUNT,
+		.data = &q->Result
+	};
+	intelFinish(&intel->ctx);
+	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	q->Ready = GL_TRUE;
+	intel->stats_wm = GL_FALSE;
+}
+
 
 void intelInitDriverFunctions( struct dd_function_table *functions )
 {
@@ -253,6 +285,8 @@ void intelInitDriverFunctions( struct dd_function_table *functions )
    functions->Finish = intelFinish;
    functions->GetString = intelGetString;
    functions->UpdateState = intelInvalidateState;
+   functions->BeginQuery = intelBeginQuery;
+   functions->EndQuery = intelEndQuery;
 
    /* CopyPixels can be accelerated even with the current memory
     * manager:
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 85e574cdaf..39eb775301 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -177,6 +177,7 @@ struct intel_context
    GLuint second_last_swap_fence;
    
    GLboolean aub_wrap;
+   GLboolean stats_wm;
 
    struct intel_batchbuffer *batch;
 
diff --git a/src/mesa/drivers/dri/i965/server/i830_common.h b/src/mesa/drivers/dri/i965/server/i830_common.h
index e3bbdc7907..f320378c2a 100644
--- a/src/mesa/drivers/dri/i965/server/i830_common.h
+++ b/src/mesa/drivers/dri/i965/server/i830_common.h
@@ -52,6 +52,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define DRM_I830_INIT_HEAP                0x0a
 #define DRM_I830_CMDBUFFER                0x0b
 #define DRM_I830_DESTROY_HEAP             0x0c
+#define DRM_I830_MMIO		       	  0x10
 
 typedef struct {
    enum {
@@ -199,5 +200,23 @@ typedef struct {
 	int region;
 } drmI830MemDestroyHeap;
 
+#define MMIO_READ  0
+#define MMIO_WRITE 1
+
+#define MMIO_REGS_IA_PRIMATIVES_COUNT           0
+#define MMIO_REGS_IA_VERTICES_COUNT             1
+#define MMIO_REGS_VS_INVOCATION_COUNT           2
+#define MMIO_REGS_GS_PRIMITIVES_COUNT           3
+#define MMIO_REGS_GS_INVOCATION_COUNT           4
+#define MMIO_REGS_CL_PRIMITIVES_COUNT           5
+#define MMIO_REGS_CL_INVOCATION_COUNT           6
+#define MMIO_REGS_PS_INVOCATION_COUNT           7
+#define MMIO_REGS_PS_DEPTH_COUNT                8
+
+typedef struct {
+        unsigned int read_write:1;
+        unsigned int reg:31;
+        void __user *data;
+} drmI830MMIO;
 
 #endif /* _I830_DRM_H_ */
-- 
cgit v1.2.3


From adccb084df57ea5aef1b2ff9c21038ce1b89f7e3 Mon Sep 17 00:00:00 2001
From: Haihao Xiang <haihao.xiang@intel.com>
Date: Tue, 26 Dec 2006 16:45:02 -0800
Subject: Support linear format in i965. Fix bug #117 #118

---
 src/mesa/drivers/dri/i965/intel_context.c | 6 +++---
 src/mesa/drivers/dri/i965/intel_screen.c  | 6 +++++-
 src/mesa/drivers/dri/i965/intel_screen.h  | 1 +
 3 files changed, 9 insertions(+), 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965/intel_context.c')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 6bcc984285..1546b33108 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -440,7 +440,7 @@ GLboolean intelInitContext( struct intel_context *intel,
 				 intelScreen->cpp,
 				 intelScreen->front.pitch / intelScreen->cpp,
 				 intelScreen->height,
-				 GL_FALSE);
+				 intelScreen->front.tiled != 0); /* 0: LINEAR */
 
 
    intel->back_region = 
@@ -451,7 +451,7 @@ GLboolean intelInitContext( struct intel_context *intel,
 				 intelScreen->cpp,
 				 intelScreen->back.pitch / intelScreen->cpp,
 				 intelScreen->height,
-				 (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+                                 intelScreen->back.tiled != 0);
 
    /* Still assuming front.cpp == depth.cpp
     *
@@ -467,7 +467,7 @@ GLboolean intelInitContext( struct intel_context *intel,
 				 intelScreen->cpp,
 				 intelScreen->depth.pitch / intelScreen->cpp,
 				 intelScreen->height,
-				 (INTEL_DEBUG & DEBUG_TILE) ? 0 : 1);
+                                 intelScreen->depth.tiled != 0);
    
    intel_bufferobj_init( intel );
    intel->batch = intel_batchbuffer_alloc( intel );
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 56e6a792fa..8269deba66 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -230,16 +230,19 @@ intelUpdateScreenFromSAREA(intelScreenPrivate *intelScreen,
    intelScreen->front.pitch = sarea->pitch * intelScreen->cpp;
    intelScreen->front.handle = sarea->front_handle;
    intelScreen->front.size = sarea->front_size;
+   intelScreen->front.tiled = sarea->front_tiled;
 
    intelScreen->back.offset = sarea->back_offset;
    intelScreen->back.pitch = sarea->pitch * intelScreen->cpp;
    intelScreen->back.handle = sarea->back_handle;
    intelScreen->back.size = sarea->back_size;
-			 
+   intelScreen->back.tiled = sarea->back_tiled;
+
    intelScreen->depth.offset = sarea->depth_offset;
    intelScreen->depth.pitch = sarea->pitch * intelScreen->cpp;
    intelScreen->depth.handle = sarea->depth_handle;
    intelScreen->depth.size = sarea->depth_size;
+   intelScreen->depth.tiled = sarea->depth_tiled;
 
    intelScreen->tex.offset = sarea->tex_offset;
    intelScreen->logTextureGranularity = sarea->log_tex_granularity;
@@ -249,6 +252,7 @@ intelUpdateScreenFromSAREA(intelScreenPrivate *intelScreen,
    intelScreen->rotated.offset = sarea->rotated_offset;
    intelScreen->rotated.pitch = sarea->rotated_pitch * intelScreen->cpp;
    intelScreen->rotated.size = sarea->rotated_size;
+   intelScreen->rotated.tiled = sarea->rotated_tiled;
    intelScreen->current_rotation = sarea->rotation;
 #if 0
    matrix23Rotate(&intelScreen->rotMatrix,
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index 094158afd8..bf9a716082 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -42,6 +42,7 @@ typedef struct {
    char *map;           /* memory map */
    int offset;          /* from start of video mem, in bytes */
    int pitch;           /* row stride, in pixels */
+   unsigned int tiled; 
 } intelRegion;
 
 typedef struct 
-- 
cgit v1.2.3


From c171166987167db5e8ff67a09327283c0ef1b222 Mon Sep 17 00:00:00 2001
From: Zou Nan hai <nanhai.zou@intel.com>
Date: Thu, 18 Jan 2007 14:41:38 +0800
Subject: 1. Fix bug #155 2. I notice multiple ARB_occlusion_query should be
 able to overlap according to spec.

3. Declaring extern variables in a .c file is evil, fix it.
---
 src/mesa/drivers/dri/i965/intel_context.c | 27 ++++++++++++++++-----------
 src/mesa/drivers/dri/i965/intel_context.h |  2 +-
 src/mesa/drivers/dri/i965/intel_screen.c  |  6 ++----
 3 files changed, 19 insertions(+), 16 deletions(-)

(limited to 'src/mesa/drivers/dri/i965/intel_context.c')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 0daa0ecb7e..f730ea0582 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -187,9 +187,17 @@ const struct dri_extension card_extensions[] =
     { NULL,                                NULL }
 };
 
-static const struct dri_extension arb_oc_extension = 
+const struct dri_extension arb_oc_extension = 
     { "GL_ARB_occlusion_query",            GL_ARB_occlusion_query_functions};
 
+void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging)
+{	     
+	struct intel_context *intel = ctx?intel_context(ctx):NULL;
+	driInitExtensions(ctx, card_extensions, enable_imaging);
+	if (!ctx || intel->intelScreen->drmMinor >= 8)
+		driInitSingleExtension (ctx, &arb_oc_extension);
+}
+
 static const struct dri_debug_control debug_control[] =
 {
     { "fall",  DEBUG_FALLBACKS },
@@ -251,28 +259,29 @@ static void
 intelBeginQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
 {
 	struct intel_context *intel = intel_context( ctx );
-	GLuint64EXT tmp = 0;	
 	drmI830MMIO io = {
 		.read_write = MMIO_WRITE,
 		.reg = MMIO_REGS_PS_DEPTH_COUNT,
-		.data = &tmp 
+		.data = &q->Result 
 	};
 	intel->stats_wm = GL_TRUE;
 	intelFinish(&intel->ctx);
-	drmCommandWrite(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
 }
 
 static void
 intelEndQuery(GLcontext *ctx, GLenum target, struct gl_query_object *q)
 {
 	struct intel_context *intel = intel_context( ctx );
+	GLuint64EXT tmp;	
 	drmI830MMIO io = {
 		.read_write = MMIO_READ,
 		.reg = MMIO_REGS_PS_DEPTH_COUNT,
-		.data = &q->Result
+		.data = &tmp
 	};
 	intelFinish(&intel->ctx);
 	drmCommandRead(intel->driFd, DRM_I830_MMIO, &io, sizeof(io));
+	q->Result = tmp - q->Result;
 	q->Ready = GL_TRUE;
 	intel->stats_wm = GL_FALSE;
 }
@@ -412,12 +421,7 @@ GLboolean intelInitContext( struct intel_context *intel,
       _mesa_printf("IRQs not active.  Exiting\n");
       exit(1);
    }
- 
-   driInitExtensions( ctx, card_extensions, 
-		      GL_TRUE );
-
-   if (intel->intelScreen->drmMinor >= 8)
-      driInitSingleExtension (ctx, &arb_oc_extension);
+   intelInitExtensions(ctx, GL_TRUE); 
 
    INTEL_DEBUG  = driParseDebugString( getenv( "INTEL_DEBUG" ),
 				       debug_control );
@@ -696,3 +700,4 @@ void UNLOCK_HARDWARE( struct intel_context *intel )
    _glthread_UNLOCK_MUTEX(lockMutex); 
 }
 
+
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index 39eb775301..d971b7ed41 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -501,6 +501,7 @@ void intelBitmap(GLcontext * ctx,
 		 const struct gl_pixelstore_attrib *unpack,
 		 const GLubyte * pixels);
 
+void intelInitExtensions(GLcontext *ctx, GLboolean enable_imaging);
 #define _NEW_WINDOW_POS 0x40000000
 
 
@@ -523,6 +524,5 @@ static inline struct intel_texture_image *intel_texture_image( struct gl_texture
    return (struct intel_texture_image *)img;
 }
 
-
 #endif
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 8269deba66..08f0bb340f 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -38,6 +38,7 @@
 
 #include "intel_screen.h"
 
+#include "intel_context.h"
 #include "intel_tex.h"
 #include "intel_span.h"
 #include "intel_ioctl.h"
@@ -61,8 +62,6 @@ const GLuint __driNConfigOptions = 4;
 static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;
 #endif /*USE_NEW_INTERFACE*/
 
-extern const struct dri_extension card_extensions[];
-
 /**
  * Map all the memory regions described by the screen.
  * \return GL_TRUE if success, GL_FALSE if error.
@@ -687,7 +686,6 @@ void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIsc
 					(dri_priv->cpp == 2) ? 16 : 24,
 					(dri_priv->cpp == 2) ? 0  : 8,
 					GL_TRUE );
-
       /* Calling driInitExtensions here, with a NULL context pointer, does not actually
        * enable the extensions.  It just makes sure that all the dispatch offsets for all
        * the extensions that *might* be enables are known.  This is needed because the
@@ -696,7 +694,7 @@ void * __driCreateNewScreen_20050727( __DRInativeDisplay *dpy, int scrn, __DRIsc
        *
        * Hello chicken.  Hello egg.  How are you two today?
        */
-      driInitExtensions( NULL, card_extensions, GL_FALSE );
+      intelInitExtensions(NULL, GL_FALSE);
    }
 
    return (void *) psp;
-- 
cgit v1.2.3


From 6b6760d6bc23b98ee1de27ba78189e56e248ce9b Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Fri, 2 Feb 2007 10:01:42 +0800
Subject: Revert origin crestline pci id patch

---
 src/mesa/drivers/dri/i965/intel_context.c | 3 ---
 src/mesa/drivers/dri/i965/intel_context.h | 1 -
 2 files changed, 4 deletions(-)

(limited to 'src/mesa/drivers/dri/i965/intel_context.c')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index f730ea0582..388600dbbe 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -119,9 +119,6 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
       case PCI_CHIP_I946_GZ:
 	 chipset = "Intel(R) 946GZ"; break;
          break;
-      case PCI_CHIP_CRESTLINE:
-	 chipset = "Intel(R) Crestline"; break;
-         break;
       default:
 	 chipset = "Unknown Intel Chipset"; break;
       }
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index d971b7ed41..d51536c3fe 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -384,7 +384,6 @@ extern int INTEL_DEBUG;
 #define PCI_CHIP_I965_Q			0x2992
 #define PCI_CHIP_I965_G_1		0x2982
 #define PCI_CHIP_I946_GZ		0x2972
-#define PCI_CHIP_CRESTLINE		0x2A02
 
 
 /* ================================================================
-- 
cgit v1.2.3


From 51bfb8fc8c78bb066d24e6ecbc20f00af7210386 Mon Sep 17 00:00:00 2001
From: Wang Zhenyu <zhenyu.z.wang@intel.com>
Date: Fri, 2 Feb 2007 10:04:48 +0800
Subject: Add Intel 965GM chipset info

---
 src/mesa/drivers/dri/i965/intel_context.c | 3 +++
 src/mesa/drivers/dri/i965/intel_context.h | 1 +
 2 files changed, 4 insertions(+)

(limited to 'src/mesa/drivers/dri/i965/intel_context.c')

diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 388600dbbe..fea6e44f0b 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -119,6 +119,9 @@ static const GLubyte *intelGetString( GLcontext *ctx, GLenum name )
       case PCI_CHIP_I946_GZ:
 	 chipset = "Intel(R) 946GZ"; break;
          break;
+      case PCI_CHIP_I965_GM:
+	 chipset = "Intel(R) 965GM"; break;
+         break;
       default:
 	 chipset = "Unknown Intel Chipset"; break;
       }
diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h
index d51536c3fe..74a795c96d 100644
--- a/src/mesa/drivers/dri/i965/intel_context.h
+++ b/src/mesa/drivers/dri/i965/intel_context.h
@@ -384,6 +384,7 @@ extern int INTEL_DEBUG;
 #define PCI_CHIP_I965_Q			0x2992
 #define PCI_CHIP_I965_G_1		0x2982
 #define PCI_CHIP_I946_GZ		0x2972
+#define PCI_CHIP_I965_GM                0x2A02
 
 
 /* ================================================================
-- 
cgit v1.2.3