From b90f7f3ad324b1e4c39e334cdeb9556c3eb808ab Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 14 Dec 2009 16:16:26 -0800 Subject: i965: Use current draw buffer instead of drawable visual to get alpha bits Use the currently bound draw buffer instead of the visual from the drawable used to create the context. This cause problems generating mipmaps for an RGBA texture in an RGB context. This fixes the failure in piglit's glsl-lod-bias test reported in bug #25614. --- src/mesa/drivers/dri/i965/brw_cc.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index ab301b9a3a..bac1c3a49c 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -158,9 +158,9 @@ cc_unit_populate_key(struct brw_context *brw, struct brw_cc_unit_key *key) /* If the renderbuffer is XRGB, we have to frob the blend function to * force the destination alpha to 1.0. This means replacing GL_DST_ALPHA - * with GL_ONE and GL_ONE_MINUS_DST_ALPAH with GL_ZERO. + * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO. */ - if (ctx->Visual.alphaBits == 0) { + if (ctx->DrawBuffer->Visual.alphaBits == 0) { key->blend_src_rgb = fix_xRGB_alpha(key->blend_src_rgb); key->blend_src_a = fix_xRGB_alpha(key->blend_src_a); key->blend_dst_rgb = fix_xRGB_alpha(key->blend_dst_rgb); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 3f9b1fbfdc..8335e5a650 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -581,7 +581,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, /* As mentioned above, disable writes to the alpha component when the * renderbuffer is XRGB. */ - if (ctx->Visual.alphaBits == 0) + if (ctx->DrawBuffer->Visual.alphaBits == 0) key.color_mask[3] = GL_FALSE; key.color_blend = (!ctx->Color._LogicOpEnabled && -- cgit v1.2.3 From 1f7c914ad0beea8a29c1a171c7cd1a12f2efe0fa Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 30 Sep 2009 20:28:45 -0600 Subject: mesa: replace gl_texture_format with gl_format Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum. ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x. gl_texture_format will go away next. --- src/mesa/drivers/common/meta.c | 2 +- src/mesa/drivers/dri/common/texmem.c | 44 ++-- src/mesa/drivers/dri/common/texmem.h | 21 +- src/mesa/drivers/dri/i810/i810tex.c | 18 +- src/mesa/drivers/dri/i810/i810texmem.c | 2 +- src/mesa/drivers/dri/i810/i810texstate.c | 2 +- src/mesa/drivers/dri/i915/i830_texstate.c | 2 +- src/mesa/drivers/dri/i915/i830_vtbl.c | 4 +- src/mesa/drivers/dri/i915/i915_texstate.c | 6 +- src/mesa/drivers/dri/i915/i915_vtbl.c | 4 +- src/mesa/drivers/dri/i965/brw_wm.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +- src/mesa/drivers/dri/intel/intel_blit.c | 4 +- src/mesa/drivers/dri/intel/intel_fbo.c | 47 ++-- src/mesa/drivers/dri/intel/intel_fbo.h | 3 +- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 2 +- src/mesa/drivers/dri/intel/intel_span.c | 2 +- src/mesa/drivers/dri/intel/intel_tex.h | 7 +- src/mesa/drivers/dri/intel/intel_tex_format.c | 72 ++--- src/mesa/drivers/dri/intel/intel_tex_image.c | 24 +- src/mesa/drivers/dri/intel/intel_tex_subimage.c | 4 +- src/mesa/drivers/dri/intel/intel_tex_validate.c | 4 +- src/mesa/drivers/dri/mach64/mach64_tex.c | 34 +-- src/mesa/drivers/dri/mach64/mach64_texmem.c | 4 +- src/mesa/drivers/dri/mach64/mach64_texstate.c | 4 +- src/mesa/drivers/dri/mga/mga_texstate.c | 8 +- src/mesa/drivers/dri/mga/mgatex.c | 46 ++-- src/mesa/drivers/dri/mga/mgatexmem.c | 2 +- src/mesa/drivers/dri/r128/r128_tex.c | 8 +- src/mesa/drivers/dri/r128/r128_texmem.c | 4 +- src/mesa/drivers/dri/r128/r128_texstate.c | 4 +- src/mesa/drivers/dri/r200/r200_texstate.c | 8 +- src/mesa/drivers/dri/r300/r300_texstate.c | 8 +- src/mesa/drivers/dri/r600/r600_texstate.c | 4 +- src/mesa/drivers/dri/radeon/radeon_fbo.c | 31 +-- src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 10 +- src/mesa/drivers/dri/radeon/radeon_texstate.c | 8 +- src/mesa/drivers/dri/radeon/radeon_texture.c | 104 ++++---- src/mesa/drivers/dri/radeon/radeon_texture.h | 22 +- src/mesa/drivers/dri/savage/savagetex.c | 127 +++++---- src/mesa/drivers/dri/sis/sis_tex.c | 57 ++-- src/mesa/drivers/dri/tdfx/tdfx_tex.c | 81 +++--- src/mesa/drivers/dri/unichrome/via_tex.c | 68 ++--- src/mesa/drivers/glide/fxddtex.c | 48 ++-- src/mesa/drivers/x11/xm_dd.c | 6 +- src/mesa/main/dd.h | 4 +- src/mesa/main/debug.c | 2 +- src/mesa/main/fbobject.c | 4 +- src/mesa/main/mipmap.c | 8 +- src/mesa/main/mtypes.h | 2 +- src/mesa/main/texcompress_fxt1.c | 12 +- src/mesa/main/texcompress_s3tc.c | 24 +- src/mesa/main/texformat.c | 147 ++++++----- src/mesa/main/texformat.h | 6 +- src/mesa/main/texformat_tmp.h | 4 +- src/mesa/main/texgetimage.c | 14 +- src/mesa/main/teximage.c | 14 +- src/mesa/main/texparam.c | 2 +- src/mesa/main/texrender.c | 10 +- src/mesa/main/texstore.c | 322 +++++++++++------------ src/mesa/main/texstore.h | 2 +- src/mesa/state_tracker/st_cb_drawpixels.c | 4 +- src/mesa/state_tracker/st_cb_texture.c | 30 +-- src/mesa/state_tracker/st_format.c | 62 ++--- src/mesa/state_tracker/st_format.h | 3 +- src/mesa/state_tracker/st_gen_mipmap.c | 2 +- src/mesa/state_tracker/st_texture.c | 2 +- src/mesa/swrast/s_texfilter.c | 28 +- src/mesa/swrast/s_triangle.c | 4 +- 69 files changed, 869 insertions(+), 822 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index 94cfdfe533..6b35dbb5ad 100644 --- a/src/mesa/drivers/common/meta.c +++ b/src/mesa/drivers/common/meta.c @@ -2407,7 +2407,7 @@ copy_tex_sub_image(GLcontext *ctx, GLuint dims, GLenum target, GLint level, texObj = _mesa_select_tex_object(ctx, texUnit, target); texImage = _mesa_select_tex_image(ctx, texObj, target, level); - format = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + format = _mesa_get_format_base_format(texImage->TexFormat); type = get_temp_image_type(ctx, format); bpp = _mesa_bytes_per_pixel(format, type); if (bpp <= 0) { diff --git a/src/mesa/drivers/dri/common/texmem.c b/src/mesa/drivers/dri/common/texmem.c index b64618a03c..c9c3324ed9 100644 --- a/src/mesa/drivers/dri/common/texmem.c +++ b/src/mesa/drivers/dri/common/texmem.c @@ -1306,16 +1306,16 @@ driCalculateTextureFirstLastLevel( driTextureObject * t ) * little-endian Mesa formats. */ /*@{*/ -const struct gl_texture_format *_dri_texformat_rgba8888 = NULL; -const struct gl_texture_format *_dri_texformat_argb8888 = NULL; -const struct gl_texture_format *_dri_texformat_rgb565 = NULL; -const struct gl_texture_format *_dri_texformat_argb4444 = NULL; -const struct gl_texture_format *_dri_texformat_argb1555 = NULL; -const struct gl_texture_format *_dri_texformat_al88 = NULL; -const struct gl_texture_format *_dri_texformat_a8 = &_mesa_texformat_a8; -const struct gl_texture_format *_dri_texformat_ci8 = &_mesa_texformat_ci8; -const struct gl_texture_format *_dri_texformat_i8 = &_mesa_texformat_i8; -const struct gl_texture_format *_dri_texformat_l8 = &_mesa_texformat_l8; +gl_format _dri_texformat_rgba8888 = MESA_FORMAT_NONE; +gl_format _dri_texformat_argb8888 = MESA_FORMAT_NONE; +gl_format _dri_texformat_rgb565 = MESA_FORMAT_NONE; +gl_format _dri_texformat_argb4444 = MESA_FORMAT_NONE; +gl_format _dri_texformat_argb1555 = MESA_FORMAT_NONE; +gl_format _dri_texformat_al88 = MESA_FORMAT_NONE; +gl_format _dri_texformat_a8 = MESA_FORMAT_NONE; +gl_format _dri_texformat_ci8 = MESA_FORMAT_NONE; +gl_format _dri_texformat_i8 = MESA_FORMAT_NONE; +gl_format _dri_texformat_l8 = MESA_FORMAT_NONE; /*@}*/ @@ -1329,19 +1329,19 @@ driInitTextureFormats(void) const GLubyte littleEndian = *((const GLubyte *) &ui); if (littleEndian) { - _dri_texformat_rgba8888 = &_mesa_texformat_rgba8888; - _dri_texformat_argb8888 = &_mesa_texformat_argb8888; - _dri_texformat_rgb565 = &_mesa_texformat_rgb565; - _dri_texformat_argb4444 = &_mesa_texformat_argb4444; - _dri_texformat_argb1555 = &_mesa_texformat_argb1555; - _dri_texformat_al88 = &_mesa_texformat_al88; + _dri_texformat_rgba8888 = MESA_FORMAT_RGBA8888; + _dri_texformat_argb8888 = MESA_FORMAT_ARGB8888; + _dri_texformat_rgb565 = MESA_FORMAT_RGB565; + _dri_texformat_argb4444 = MESA_FORMAT_ARGB4444; + _dri_texformat_argb1555 = MESA_FORMAT_ARGB1555; + _dri_texformat_al88 = MESA_FORMAT_AL88; } else { - _dri_texformat_rgba8888 = &_mesa_texformat_rgba8888_rev; - _dri_texformat_argb8888 = &_mesa_texformat_argb8888_rev; - _dri_texformat_rgb565 = &_mesa_texformat_rgb565_rev; - _dri_texformat_argb4444 = &_mesa_texformat_argb4444_rev; - _dri_texformat_argb1555 = &_mesa_texformat_argb1555_rev; - _dri_texformat_al88 = &_mesa_texformat_al88_rev; + _dri_texformat_rgba8888 = MESA_FORMAT_RGBA8888_REV; + _dri_texformat_argb8888 = MESA_FORMAT_ARGB8888_REV; + _dri_texformat_rgb565 = MESA_FORMAT_RGB565_REV; + _dri_texformat_argb4444 = MESA_FORMAT_ARGB4444_REV; + _dri_texformat_argb1555 = MESA_FORMAT_ARGB1555_REV; + _dri_texformat_al88 = MESA_FORMAT_AL88_REV; } } diff --git a/src/mesa/drivers/dri/common/texmem.h b/src/mesa/drivers/dri/common/texmem.h index 9c065da8b4..725ba2e119 100644 --- a/src/mesa/drivers/dri/common/texmem.h +++ b/src/mesa/drivers/dri/common/texmem.h @@ -39,6 +39,7 @@ #define DRI_TEXMEM_H #include "main/mtypes.h" +#include "main/formats.h" #include "main/mm.h" #include "xf86drm.h" @@ -317,16 +318,16 @@ GLboolean driValidateTextureHeaps( driTexHeap * const * texture_heaps, extern void driCalculateTextureFirstLastLevel( driTextureObject * t ); -extern const struct gl_texture_format *_dri_texformat_rgba8888; -extern const struct gl_texture_format *_dri_texformat_argb8888; -extern const struct gl_texture_format *_dri_texformat_rgb565; -extern const struct gl_texture_format *_dri_texformat_argb4444; -extern const struct gl_texture_format *_dri_texformat_argb1555; -extern const struct gl_texture_format *_dri_texformat_al88; -extern const struct gl_texture_format *_dri_texformat_a8; -extern const struct gl_texture_format *_dri_texformat_ci8; -extern const struct gl_texture_format *_dri_texformat_i8; -extern const struct gl_texture_format *_dri_texformat_l8; +extern gl_format _dri_texformat_rgba8888; +extern gl_format _dri_texformat_argb8888; +extern gl_format _dri_texformat_rgb565; +extern gl_format _dri_texformat_argb4444; +extern gl_format _dri_texformat_argb1555; +extern gl_format _dri_texformat_al88; +extern gl_format _dri_texformat_a8; +extern gl_format _dri_texformat_ci8; +extern gl_format _dri_texformat_i8; +extern gl_format _dri_texformat_l8; extern void driInitTextureFormats( void ); diff --git a/src/mesa/drivers/dri/i810/i810tex.c b/src/mesa/drivers/dri/i810/i810tex.c index cd6e1a8e6e..8166393eb1 100644 --- a/src/mesa/drivers/dri/i810/i810tex.c +++ b/src/mesa/drivers/dri/i810/i810tex.c @@ -440,7 +440,7 @@ static void i810DeleteTexture( GLcontext *ctx, struct gl_texture_object *tObj ) * The i810 only supports 5 texture modes that are useful to Mesa. That * makes this routine pretty simple. */ -static const struct gl_texture_format * +static gl_format i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -458,9 +458,9 @@ i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, if ( ((format == GL_BGRA) && (type == GL_UNSIGNED_SHORT_1_5_5_5_REV)) || ((format == GL_RGBA) && (type == GL_UNSIGNED_SHORT_5_5_5_1)) || (internalFormat == GL_RGB5_A1) ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case 3: case GL_RGB: @@ -472,7 +472,7 @@ i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_ALPHA4: @@ -502,21 +502,21 @@ i810ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: fprintf(stderr, "unexpected texture format in %s\n", __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } /** diff --git a/src/mesa/drivers/dri/i810/i810texmem.c b/src/mesa/drivers/dri/i810/i810texmem.c index 8cbe38f5fc..c2a5d95fc7 100644 --- a/src/mesa/drivers/dri/i810/i810texmem.c +++ b/src/mesa/drivers/dri/i810/i810texmem.c @@ -97,7 +97,7 @@ static void i810UploadTexLevel( i810ContextPtr imesa, if (!image || !image->Data) return; - texelBytes = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->TexFormat); if (image->Width * texelBytes == t->Pitch) { GLubyte *dst = (GLubyte *)(t->BufAddr + t->image[hwlevel].offset); diff --git a/src/mesa/drivers/dri/i810/i810texstate.c b/src/mesa/drivers/dri/i810/i810texstate.c index 0e09f54c41..b873ddbecb 100644 --- a/src/mesa/drivers/dri/i810/i810texstate.c +++ b/src/mesa/drivers/dri/i810/i810texstate.c @@ -53,7 +53,7 @@ static void i810SetTexImages( i810ContextPtr imesa, /* fprintf(stderr, "%s\n", __FUNCTION__); */ t->texelBytes = 2; - switch (baseImage->TexFormat->MesaFormat) { + switch (baseImage->TexFormat) { case MESA_FORMAT_ARGB1555: textureFormat = MI1_FMT_16BPP | MI1_PF_16BPP_ARGB1555; break; diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 6f998fa6f7..837ae57074 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -166,7 +166,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) 0, intelObj-> firstLevel); - format = translate_texture_format(firstImage->TexFormat->MesaFormat, + format = translate_texture_format(firstImage->TexFormat, firstImage->InternalFormat); pitch = intelObj->mt->pitch * intelObj->mt->cpp; } diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 983f6724c9..d53900b329 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -646,7 +646,7 @@ i830_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */ if (irb != NULL) { - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: value |= DV_PF_8888; break; @@ -661,7 +661,7 @@ i830_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat->MesaFormat); + irb->texformat); } } diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 32d4b30cf9..d6f6cfdb49 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -177,7 +177,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) 0, intelObj-> firstLevel); - format = translate_texture_format(firstImage->TexFormat->MesaFormat, + format = translate_texture_format(firstImage->TexFormat, firstImage->InternalFormat, tObj->DepthMode); pitch = intelObj->mt->pitch * intelObj->mt->cpp; @@ -263,8 +263,8 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) /* YUV conversion: */ - if (firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR || - firstImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR_REV) + if (firstImage->TexFormat == MESA_FORMAT_YCBCR || + firstImage->TexFormat == MESA_FORMAT_YCBCR_REV) state[I915_TEXREG_SS2] |= SS2_COLORSPACE_CONVERSION; /* Shadow: diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 9a723d3cd7..1c3da63da9 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -589,7 +589,7 @@ i915_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | /* .5 */ LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL); if (irb != NULL) { - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: value |= DV_PF_8888; break; @@ -604,7 +604,7 @@ i915_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat->MesaFormat); + irb->texformat); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 2292de94c4..46df778bee 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -288,7 +288,7 @@ static void brw_wm_populate_key( struct brw_context *brw, const struct gl_texture_image *img = t->Image[0][t->BaseLevel]; if (img->InternalFormat == GL_YCBCR_MESA) { key->yuvtex_mask |= 1 << i; - if (img->TexFormat->MesaFormat == MESA_FORMAT_YCBCR) + if (img->TexFormat == MESA_FORMAT_YCBCR) key->yuvtex_swap_mask |= 1 << i; } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 51539ac1e7..855fe7593d 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -287,7 +287,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) key.bo = NULL; key.offset = intelObj->textureOffset; } else { - key.format = firstImage->TexFormat->MesaFormat; + key.format = firstImage->TexFormat; key.internal_format = firstImage->InternalFormat; key.pitch = intelObj->mt->pitch; key.depth = firstImage->Depth; @@ -527,7 +527,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, region_bo = region->buffer; key.surface_type = BRW_SURFACE_2D; - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; @@ -541,8 +541,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM; break; default: - _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat->MesaFormat); + _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->texformat); } key.tiling = region->tiling; if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) { diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 43141c509c..799b22cc90 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -496,7 +496,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: clearVal = intel->ClearColor8888; break; @@ -513,7 +513,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) break; default: _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n", - irb->texformat->MesaFormat); + irb->texformat); clearVal = 0; } } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 0a3d0654d7..1be381b9ea 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -120,7 +120,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->RedBits = 5; rb->GreenBits = 6; rb->BlueBits = 5; - irb->texformat = &_mesa_texformat_rgb565; + irb->texformat = MESA_FORMAT_RGB565; cpp = 2; break; case GL_RGB: @@ -134,7 +134,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->GreenBits = 8; rb->BlueBits = 8; rb->AlphaBits = 0; - irb->texformat = &_mesa_texformat_argb8888; /* XXX: Need xrgb8888 */ + irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ cpp = 4; break; case GL_RGBA: @@ -151,7 +151,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->GreenBits = 8; rb->BlueBits = 8; rb->AlphaBits = 8; - irb->texformat = &_mesa_texformat_argb8888; + irb->texformat = MESA_FORMAT_ARGB8888; cpp = 4; break; case GL_STENCIL_INDEX: @@ -164,14 +164,14 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->DataType = GL_UNSIGNED_INT_24_8_EXT; rb->StencilBits = 8; cpp = 4; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_COMPONENT16: rb->_ActualFormat = GL_DEPTH_COMPONENT16; rb->DataType = GL_UNSIGNED_SHORT; rb->DepthBits = 16; cpp = 2; - irb->texformat = &_mesa_texformat_z16; + irb->texformat = MESA_FORMAT_Z16; break; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: @@ -180,7 +180,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->DataType = GL_UNSIGNED_INT_24_8_EXT; rb->DepthBits = 24; cpp = 4; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: @@ -189,7 +189,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->DepthBits = 24; rb->StencilBits = 8; cpp = 4; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(ctx, @@ -331,7 +331,7 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.GreenBits = 6; irb->Base.BlueBits = 5; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_rgb565; + irb->texformat = MESA_FORMAT_RGB565; break; case GL_RGB8: irb->Base._ActualFormat = GL_RGB8; @@ -341,7 +341,7 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.BlueBits = 8; irb->Base.AlphaBits = 0; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_argb8888; /* XXX: Need xrgb8888 */ + irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: NEED XRGB8888 */ break; case GL_RGBA8: irb->Base._ActualFormat = GL_RGBA8; @@ -351,28 +351,28 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.BlueBits = 8; irb->Base.AlphaBits = 8; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_argb8888; + irb->texformat = MESA_FORMAT_ARGB8888; break; case GL_STENCIL_INDEX8_EXT: irb->Base._ActualFormat = GL_STENCIL_INDEX8_EXT; irb->Base._BaseFormat = GL_STENCIL_INDEX; irb->Base.StencilBits = 8; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_COMPONENT16: irb->Base._ActualFormat = GL_DEPTH_COMPONENT16; irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DepthBits = 16; irb->Base.DataType = GL_UNSIGNED_SHORT; - irb->texformat = &_mesa_texformat_z16; + irb->texformat = MESA_FORMAT_Z16; break; case GL_DEPTH_COMPONENT24: irb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DepthBits = 24; irb->Base.DataType = GL_UNSIGNED_INT; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH24_STENCIL8_EXT: irb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; @@ -380,7 +380,7 @@ intel_create_renderbuffer(GLenum intFormat) irb->Base.DepthBits = 24; irb->Base.StencilBits = 8; irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; - irb->texformat = &_mesa_texformat_s8_z24; + irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(NULL, @@ -468,49 +468,48 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, irb->texformat = texImage->TexFormat; gl_format texFormat; - if (texImage->TexFormat == &_mesa_texformat_argb8888) { + if (texImage->TexFormat == MESA_FORMAT_ARGB8888) { irb->Base._ActualFormat = GL_RGBA8; irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_rgb565) { + else if (texImage->TexFormat == MESA_FORMAT_RGB565) { irb->Base._ActualFormat = GL_RGB5; irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGB5 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb1555) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB1555) { irb->Base._ActualFormat = GL_RGB5_A1; irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB1555 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb4444) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB4444) { irb->Base._ActualFormat = GL_RGBA4; irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB4444 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_z16) { + else if (texImage->TexFormat == MESA_FORMAT_Z16) { irb->Base._ActualFormat = GL_DEPTH_COMPONENT16; irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DataType = GL_UNSIGNED_SHORT; DBG("Render to DEPTH16 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { + else if (texImage->TexFormat == MESA_FORMAT_S8_Z24) { irb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; irb->Base._BaseFormat = GL_DEPTH_STENCIL_EXT; irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; DBG("Render to DEPTH_STENCIL texture OK\n"); } else { - DBG("Render to texture BAD FORMAT %d\n", - texImage->TexFormat->MesaFormat); + DBG("Render to texture BAD FORMAT %d\n", texImage->TexFormat); return GL_FALSE; } - texFormat = texImage->TexFormat->MesaFormat; + texFormat = texImage->TexFormat; irb->Base.InternalFormat = irb->Base._ActualFormat; irb->Base.Width = texImage->Width; @@ -690,7 +689,7 @@ intel_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) continue; } - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_RGB565: case MESA_FORMAT_ARGB1555: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index f0665af482..e0584e3494 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -28,6 +28,7 @@ #ifndef INTEL_FBO_H #define INTEL_FBO_H +#include "main/formats.h" #include "intel_screen.h" struct intel_context; @@ -61,7 +62,7 @@ struct intel_renderbuffer struct gl_renderbuffer Base; struct intel_region *region; - const struct gl_texture_format *texformat; + gl_format texformat; GLuint vbl_pending; /**< vblank sequence number of pending flip */ diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 188333c75f..6bb7481ae4 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -307,7 +307,7 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt, if (!image->IsCompressed && !mt->compressed && - _mesa_get_format_bytes(image->TexFormat->MesaFormat) != mt->cpp) + _mesa_get_format_bytes(image->TexFormat) != mt->cpp) return GL_FALSE; /* Test image dimensions against the base level image adjusted for diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 28eabbc005..f754ce0cd1 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -578,7 +578,7 @@ intel_set_span_functions(struct intel_context *intel, else tiling = I915_TILING_NONE; - switch (irb->texformat->MesaFormat) { + switch (irb->texformat) { case MESA_FORMAT_RGB565: switch (tiling) { case I915_TILING_NONE: diff --git a/src/mesa/drivers/dri/intel/intel_tex.h b/src/mesa/drivers/dri/intel/intel_tex.h index 471aa2a240..f67e1db9e3 100644 --- a/src/mesa/drivers/dri/intel/intel_tex.h +++ b/src/mesa/drivers/dri/intel/intel_tex.h @@ -29,6 +29,7 @@ #define INTELTEX_INC #include "main/mtypes.h" +#include "main/formats.h" #include "intel_context.h" #include "texmem.h" @@ -41,10 +42,8 @@ void intelInitTextureSubImageFuncs(struct dd_function_table *functions); void intelInitTextureCopyImageFuncs(struct dd_function_table *functions); -const struct gl_texture_format *intelChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type); +gl_format intelChooseTextureFormat(GLcontext *ctx, GLint internalFormat, + GLenum format, GLenum type); void intelSetTexOffset(__DRIcontext *pDRICtx, GLint texname, unsigned long long offset, GLint depth, GLuint pitch); diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index 3322a71130..22c010bbd7 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -16,7 +16,7 @@ * these if we take the step of simply swizzling the colors * immediately after sampling... */ -const struct gl_texture_format * +gl_format intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, GLenum format, GLenum type) { @@ -34,48 +34,48 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_COMPRESSED_RGBA: if (format == GL_BGRA) { if (type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if (type == GL_UNSIGNED_SHORT_4_4_4_4_REV) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if (type == GL_UNSIGNED_SHORT_1_5_5_5_REV) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case 3: case GL_RGB: case GL_COMPRESSED_RGB: if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA8: case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case GL_RGB5: case GL_RGB4: case GL_R3_G3_B2: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_ALPHA4: @@ -83,7 +83,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: @@ -92,7 +92,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: @@ -103,7 +103,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: @@ -111,41 +111,41 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT16: case GL_DEPTH_COMPONENT24: case GL_DEPTH_COMPONENT32: #if 0 - return &_mesa_texformat_z16; + return MESA_FORMAT_Z16; #else /* fall-through. * 16bpp depth texture can't be paired with a stencil buffer so @@ -154,7 +154,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, #endif case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - return &_mesa_texformat_s8_z24; + return MESA_FORMAT_S8_Z24; #ifndef I915 case GL_SRGB_EXT: @@ -165,41 +165,41 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_COMPRESSED_SRGB_ALPHA_EXT: case GL_COMPRESSED_SLUMINANCE_EXT: case GL_COMPRESSED_SLUMINANCE_ALPHA_EXT: - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; case GL_SLUMINANCE_EXT: case GL_SLUMINANCE8_EXT: if (IS_G4X(intel->intelScreen->deviceID)) - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; else - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; case GL_SLUMINANCE_ALPHA_EXT: case GL_SLUMINANCE8_ALPHA8_EXT: if (IS_G4X(intel->intelScreen->deviceID)) - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; else - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT: case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT: - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; /* i915 could also do this */ case GL_DUDV_ATI: case GL_DU8DV8_ATI: - return &_mesa_texformat_dudv8; + return MESA_FORMAT_DUDV8; case GL_RGBA_SNORM: case GL_RGBA8_SNORM: - return &_mesa_texformat_signed_rgba8888_rev; + return MESA_FORMAT_SIGNED_RGBA8888_REV; #endif default: fprintf(stderr, "unexpected texture format %s in %s\n", _mesa_lookup_enum_by_nr(internalFormat), __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } int intel_compressed_num_bytes(GLuint mesaFormat) diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 0e13f600a6..bbbeac8f7f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -126,9 +126,9 @@ guess_and_alloc_mipmap_tree(struct intel_context *intel, assert(!intelObj->mt); if (intelImage->base.IsCompressed) - comp_byte = intel_compressed_num_bytes(intelImage->base.TexFormat->MesaFormat); + comp_byte = intel_compressed_num_bytes(intelImage->base.TexFormat); - texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat); intelObj->mt = intel_miptree_create(intel, intelObj->base.Target, @@ -171,7 +171,7 @@ target_to_face(GLenum target) static GLboolean check_pbo_format(GLint internalFormat, GLenum format, GLenum type, - const struct gl_texture_format *mesa_format) + gl_format mesa_format) { switch (internalFormat) { case 4: @@ -179,12 +179,12 @@ check_pbo_format(GLint internalFormat, return (format == GL_BGRA && (type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV) && - mesa_format == &_mesa_texformat_argb8888); + mesa_format == MESA_FORMAT_ARGB8888); case 3: case GL_RGB: return (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5 && - mesa_format == &_mesa_texformat_rgb565); + mesa_format == MESA_FORMAT_RGB565); case GL_YCBCR_MESA: return (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE); default: @@ -337,15 +337,15 @@ intelTexImage(GLcontext * ctx, _mesa_set_fetch_functions(texImage, dims); - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { texelBytes = 0; texImage->IsCompressed = GL_TRUE; texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* Minimum pitch of 32 bytes */ if (postConvWidth * texelBytes < 32) { @@ -403,11 +403,11 @@ intelTexImage(GLcontext * ctx, assert(intelImage->mt); } else if (intelImage->base.Border == 0) { int comp_byte = 0; - GLuint texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat->MesaFormat); - GLenum baseFormat = _mesa_get_format_base_format(intelImage->base.TexFormat->MesaFormat); + GLuint texelBytes = _mesa_get_format_bytes(intelImage->base.TexFormat); + GLenum baseFormat = _mesa_get_format_base_format(intelImage->base.TexFormat); if (intelImage->base.IsCompressed) { comp_byte = - intel_compressed_num_bytes(intelImage->base.TexFormat->MesaFormat); + intel_compressed_num_bytes(intelImage->base.TexFormat); } /* Didn't fit in the object miptree, but it's suitable for inclusion in @@ -497,7 +497,7 @@ intelTexImage(GLcontext * ctx, if (texImage->IsCompressed) { sizeInBytes = texImage->CompressedSize; dstRowStride = - _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + _mesa_compressed_row_stride(texImage->TexFormat, width); assert(dims != 3); } else { diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index ad5c2271a1..bba1b53009 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -87,11 +87,11 @@ intelTexSubimage(GLcontext * ctx, else { if (texImage->IsCompressed) { dstRowStride = - _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + _mesa_compressed_row_stride(texImage->TexFormat, width); assert(dims != 3); } else { - dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat); } } diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index 0393d7915a..0296c92523 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -166,11 +166,11 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) } if (firstImage->base.IsCompressed) { - comp_byte = intel_compressed_num_bytes(firstImage->base.TexFormat->MesaFormat); + comp_byte = intel_compressed_num_bytes(firstImage->base.TexFormat); cpp = comp_byte; } else - cpp = _mesa_get_format_bytes(firstImage->base.TexFormat->MesaFormat); + cpp = _mesa_get_format_bytes(firstImage->base.TexFormat); /* Check tree can hold all active levels. Check tree matches * target, imageFormat, etc. diff --git a/src/mesa/drivers/dri/mach64/mach64_tex.c b/src/mesa/drivers/dri/mach64/mach64_tex.c index 225d23179e..02433e5dd8 100644 --- a/src/mesa/drivers/dri/mach64/mach64_tex.c +++ b/src/mesa/drivers/dri/mach64/mach64_tex.c @@ -138,7 +138,7 @@ mach64AllocTexObj( struct gl_texture_object *texObj ) /* Called by the _mesa_store_teximage[123]d() functions. */ -static const struct gl_texture_format * +static gl_format mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -167,15 +167,15 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGBA2: case GL_COMPRESSED_RGBA: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGBA8: case GL_RGB10_A2: @@ -183,9 +183,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGBA16: case GL_RGBA4: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case 3: case GL_RGB: @@ -198,9 +198,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB16: case GL_COMPRESSED_RGB: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; else - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case 1: case GL_LUMINANCE: @@ -210,9 +210,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; /* inefficient but accurate */ + return MESA_FORMAT_ARGB8888; /* inefficient but accurate */ else - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_INTENSITY4: case GL_INTENSITY: @@ -221,9 +221,9 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: if (mmesa->mach64Screen->cpp == 4) - return &_mesa_texformat_argb8888; /* inefficient but accurate */ + return MESA_FORMAT_ARGB8888; /* inefficient but accurate */ else - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: @@ -232,18 +232,18 @@ mach64ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: _mesa_problem( ctx, "unexpected format in %s", __FUNCTION__ ); - return NULL; + return MESA_FORMAT_NONE; } } diff --git a/src/mesa/drivers/dri/mach64/mach64_texmem.c b/src/mesa/drivers/dri/mach64/mach64_texmem.c index 843b231051..e83aeae3e1 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texmem.c +++ b/src/mesa/drivers/dri/mach64/mach64_texmem.c @@ -86,7 +86,7 @@ static void mach64UploadAGPSubImage( mach64ContextPtr mmesa, if ( !image ) return; - texelBytes = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->TexFormat); switch ( texelBytes ) { case 1: texelsPerDword = 4; break; @@ -153,7 +153,7 @@ static void mach64UploadLocalSubImage( mach64ContextPtr mmesa, if ( !image ) return; - texelBytes = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->TexFormat); switch ( texelBytes ) { case 1: texelsPerDword = 4; break; diff --git a/src/mesa/drivers/dri/mach64/mach64_texstate.c b/src/mesa/drivers/dri/mach64/mach64_texstate.c index ff03b0c40a..c333355324 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texstate.c +++ b/src/mesa/drivers/dri/mach64/mach64_texstate.c @@ -55,7 +55,7 @@ static void mach64SetTexImages( mach64ContextPtr mmesa, if ( MACH64_DEBUG & DEBUG_VERBOSE_API ) fprintf( stderr, "%s( %p )\n", __FUNCTION__, tObj ); - switch (baseImage->TexFormat->MesaFormat) { + switch (baseImage->TexFormat) { case MESA_FORMAT_ARGB8888: t->textureFormat = MACH64_DATATYPE_ARGB8888; break; @@ -89,7 +89,7 @@ static void mach64SetTexImages( mach64ContextPtr mmesa, totalSize = ( baseImage->Height * baseImage->Width * - _mesa_get_format_bytes(baseImage->TexFormat->MesaFormat) ); + _mesa_get_format_bytes(baseImage->TexFormat) ); totalSize = (totalSize + 31) & ~31; diff --git a/src/mesa/drivers/dri/mga/mga_texstate.c b/src/mesa/drivers/dri/mga/mga_texstate.c index 8f78ab9bd4..d52f0fac75 100644 --- a/src/mesa/drivers/dri/mga/mga_texstate.c +++ b/src/mesa/drivers/dri/mga/mga_texstate.c @@ -94,14 +94,14 @@ mgaSetTexImages( mgaContextPtr mmesa, return; } #else - if ( (baseImage->TexFormat->MesaFormat >= TMC_nr_tformat) - || (TMC_tformat[ baseImage->TexFormat->MesaFormat ] == 0) ) + if ( (baseImage->TexFormat >= TMC_nr_tformat) + || (TMC_tformat[ baseImage->TexFormat ] == 0) ) { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); return; } - txformat = TMC_tformat[ baseImage->TexFormat->MesaFormat ]; + txformat = TMC_tformat[ baseImage->TexFormat ]; #endif /* MGA_USE_TABLE_FOR_FORMAT */ @@ -131,7 +131,7 @@ mgaSetTexImages( mgaContextPtr mmesa, break; size = texImage->Width * texImage->Height * - _mesa_get_format_bytes(baseImage->TexFormat->MesaFormat); + _mesa_get_format_bytes(baseImage->TexFormat); t->offsets[i] = totalSize; t->base.dirty_images[0] |= (1<TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); length = texImage->Width * texImage->Height * texelBytes; if ( t->base.heap->heapId == MGA_CARD_HEAP ) { unsigned tex_offset = 0; diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c index 0920270d7b..6acda445f7 100644 --- a/src/mesa/drivers/dri/r128/r128_tex.c +++ b/src/mesa/drivers/dri/r128/r128_tex.c @@ -178,7 +178,7 @@ static r128TexObjPtr r128AllocTexObj( struct gl_texture_object *texObj ) /* Called by the _mesa_store_teximage[123]d() functions. */ -static const struct gl_texture_format * +static gl_format r128ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -282,13 +282,13 @@ r128ChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: _mesa_problem( ctx, "unexpected format in %s", __FUNCTION__ ); - return NULL; + return MESA_FORMAT_NONE; } } diff --git a/src/mesa/drivers/dri/r128/r128_texmem.c b/src/mesa/drivers/dri/r128/r128_texmem.c index c369e14bd5..84f8563b89 100644 --- a/src/mesa/drivers/dri/r128/r128_texmem.c +++ b/src/mesa/drivers/dri/r128/r128_texmem.c @@ -95,7 +95,7 @@ static void uploadSubImage( r128ContextPtr rmesa, r128TexObjPtr t, if ( !image ) return; - switch ( _mesa_get_format_bytes(image->TexFormat->MesaFormat) ) { + switch ( _mesa_get_format_bytes(image->TexFormat) ) { case 1: texelsPerDword = 4; break; case 2: texelsPerDword = 2; break; case 4: texelsPerDword = 1; break; @@ -216,7 +216,7 @@ static void uploadSubImage( r128ContextPtr rmesa, r128TexObjPtr t, /* Copy the next chunck of the texture image into the blit buffer */ { const GLuint texelBytes = - _mesa_get_format_bytes(image->TexFormat->MesaFormat); + _mesa_get_format_bytes(image->TexFormat); const GLubyte *src = (const GLubyte *) image->Data + (y * image->Width + x) * texelBytes; const GLuint bytes = width * height * texelBytes; diff --git a/src/mesa/drivers/dri/r128/r128_texstate.c b/src/mesa/drivers/dri/r128/r128_texstate.c index 9f4f9aea2d..2e71c25861 100644 --- a/src/mesa/drivers/dri/r128/r128_texstate.c +++ b/src/mesa/drivers/dri/r128/r128_texstate.c @@ -61,7 +61,7 @@ static void r128SetTexImages( r128ContextPtr rmesa, if ( R128_DEBUG & DEBUG_VERBOSE_API ) fprintf( stderr, "%s( %p )\n", __FUNCTION__, (void *) tObj ); - switch (baseImage->TexFormat->MesaFormat) { + switch (baseImage->TexFormat) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_ARGB8888_REV: t->textureFormat = R128_DATATYPE_ARGB8888; @@ -123,7 +123,7 @@ static void r128SetTexImages( r128ContextPtr rmesa, totalSize += (tObj->Image[0][i]->Height * tObj->Image[0][i]->Width * - _mesa_get_format_bytes(tObj->Image[0][i]->TexFormat->MesaFormat)); + _mesa_get_format_bytes(tObj->Image[0][i]->TexFormat)); /* Offsets must be 32-byte aligned for host data blits and tiling */ totalSize = (totalSize + 31) & ~31; diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 03f0613e7a..daca318684 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -1437,11 +1437,11 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) log2Width = firstImage->WidthLog2; log2Height = firstImage->HeightLog2; log2Depth = firstImage->DepthLog2; - texelBytes = _mesa_get_format_bytes(firstImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); if (!t->image_override) { - if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + if (VALID_FORMAT(firstImage->TexFormat)) { const struct tx_table *table = _mesa_little_endian() ? tx_table_le : tx_table_be; @@ -1449,8 +1449,8 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) R200_TXFORMAT_ALPHA_IN_MAP); t->pp_txfilter &= ~R200_YUV_TO_RGB; - t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + t->pp_txformat |= table[ firstImage->TexFormat ].format; + t->pp_txfilter |= table[ firstImage->TexFormat ].filter; } else { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index cc40e0d1dc..cb826248f3 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -156,7 +156,7 @@ void r300SetDepthTexMode(struct gl_texture_object *tObj) t = radeon_tex_obj(tObj); - switch (tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat) { + switch (tObj->Image[0][tObj->BaseLevel]->TexFormat) { case MESA_FORMAT_Z16: format = formats[0]; break; @@ -208,14 +208,14 @@ static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t) firstImage = t->base.Image[0][firstlevel]; if (!t->image_override - && VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + && VALID_FORMAT(firstImage->TexFormat)) { if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) { r300SetDepthTexMode(&t->base); } else { - t->pp_txformat = tx_table[firstImage->TexFormat->MesaFormat].format; + t->pp_txformat = tx_table[firstImage->TexFormat].format; } - t->pp_txfilter |= tx_table[firstImage->TexFormat->MesaFormat].filter; + t->pp_txfilter |= tx_table[firstImage->TexFormat].filter; } else if (!t->image_override) { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 7d7e77d355..55b455edc0 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -591,7 +591,7 @@ void r600SetDepthTexMode(struct gl_texture_object *tObj) t = radeon_tex_obj(tObj); - r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat->MesaFormat); + r600GetTexFormat(tObj, tObj->Image[0][tObj->BaseLevel]->TexFormat); } @@ -616,7 +616,7 @@ static void setup_hardware_state(context_t *rmesa, struct gl_texture_object *tex firstImage = t->base.Image[0][firstlevel]; if (!t->image_override) { - if (!r600GetTexFormat(texObj, firstImage->TexFormat->MesaFormat)) { + if (!r600GetTexFormat(texObj, firstImage->TexFormat)) { radeon_error("unexpected texture format in %s\n", __FUNCTION__); return; diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index f19170b612..90ea2ec335 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -390,42 +390,42 @@ radeon_update_wrapper(GLcontext *ctx, struct radeon_renderbuffer *rrb, gl_format texFormat; restart: - if (texImage->TexFormat == &_mesa_texformat_argb8888) { + if (texImage->TexFormat == MESA_FORMAT_ARGB8888) { rrb->cpp = 4; rrb->base._ActualFormat = GL_RGBA8; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_rgb565) { + else if (texImage->TexFormat == MESA_FORMAT_RGB565) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGB5; rrb->base._BaseFormat = GL_RGB; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGB5 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb1555) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB1555) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGB5_A1; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB1555 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_argb4444) { + else if (texImage->TexFormat == MESA_FORMAT_ARGB4444) { rrb->cpp = 2; rrb->base._ActualFormat = GL_RGBA4; rrb->base._BaseFormat = GL_RGBA; rrb->base.DataType = GL_UNSIGNED_BYTE; DBG("Render to ARGB1555 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_z16) { + else if (texImage->TexFormat == MESA_FORMAT_Z16) { rrb->cpp = 2; rrb->base._ActualFormat = GL_DEPTH_COMPONENT16; rrb->base._BaseFormat = GL_DEPTH_COMPONENT; rrb->base.DataType = GL_UNSIGNED_SHORT; DBG("Render to DEPTH16 texture OK\n"); } - else if (texImage->TexFormat == &_mesa_texformat_s8_z24) { + else if (texImage->TexFormat == MESA_FORMAT_S8_Z24) { rrb->cpp = 4; rrb->base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; rrb->base._BaseFormat = GL_DEPTH_STENCIL_EXT; @@ -436,29 +436,30 @@ restart: /* try redoing the FBO */ if (retry == 1) { DBG("Render to texture BAD FORMAT %d\n", - texImage->TexFormat->MesaFormat); + texImage->TexFormat); return GL_FALSE; } texImage->TexFormat = radeonChooseTextureFormat(ctx, texImage->InternalFormat, 0, - _mesa_get_format_datatype(texImage->TexFormat->MesaFormat), + _mesa_get_format_datatype(texImage->TexFormat), 1); retry++; goto restart; } - texFormat = texImage->TexFormat->MesaFormat; + texFormat = texImage->TexFormat; rrb->pitch = texImage->Width * rrb->cpp; rrb->base.InternalFormat = rrb->base._ActualFormat; rrb->base.Width = texImage->Width; rrb->base.Height = texImage->Height; - rrb->Base.RedBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_RED_SIZE); - rrb->Base.GreenBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_GREEN_SIZE); - rrb->Base.BlueBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_BLUE_SIZE); - rrb->Base.AlphaBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_ALPHA_SIZE); - rrb->Base.DepthBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_DEPTH_SIZE_ARB); - rrb->Base.StencilBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_STENCIL_SIZE_EXT); + rrb->base.RedBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_RED_SIZE); + rrb->base.GreenBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_GREEN_SIZE); + rrb->base.BlueBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_BLUE_SIZE); + rrb->base.AlphaBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_ALPHA_SIZE); + rrb->base.DepthBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_DEPTH_SIZE_ARB); + rrb->base.StencilBits = _mesa_get_format_bits(texFormat, GL_TEXTURE_STENCIL_SIZE_EXT); + rrb->base.Delete = radeon_delete_renderbuffer; rrb->base.AllocStorage = radeon_nop_alloc_storage; diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 851474f871..b602bfb4b0 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -325,7 +325,7 @@ GLboolean radeon_miptree_matches_image(radeon_mipmap_tree *mt, if (!texImage->IsCompressed && !mt->compressed && - _mesa_get_format_bytes(texImage->TexFormat->MesaFormat) != mt->bpp) + _mesa_get_format_bytes(texImage->TexFormat) != mt->bpp) return GL_FALSE; lvl = &mt->levels[level - mt->firstLevel]; @@ -354,8 +354,8 @@ GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_textu numfaces = 6; firstImage = texObj->Image[0][firstLevel]; - compressed = firstImage->IsCompressed ? firstImage->TexFormat->MesaFormat : 0; - texelBytes = _mesa_get_format_bytes(firstImage->TexFormat->MesaFormat); + compressed = firstImage->IsCompressed ? firstImage->TexFormat : 0; + texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); return (mt->firstLevel == firstLevel && mt->lastLevel == lastLevel && @@ -374,7 +374,7 @@ GLboolean radeon_miptree_matches_texture(radeon_mipmap_tree *mt, struct gl_textu void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, radeon_texture_image *image, GLuint face, GLuint level) { - GLuint compressed = image->base.IsCompressed ? image->base.TexFormat->MesaFormat : 0; + GLuint compressed = image->base.IsCompressed ? image->base.TexFormat : 0; GLuint numfaces = 1; GLuint firstLevel, lastLevel; GLuint texelBytes; @@ -388,7 +388,7 @@ void radeon_try_alloc_miptree(radeonContextPtr rmesa, radeonTexObj *t, if (level != firstLevel || face >= numfaces) return; - texelBytes = _mesa_get_format_bytes(image->base.TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(image->base.TexFormat); t->mt = radeon_miptree_create(rmesa, t, t->base.Target, image->base.InternalFormat, diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index a00497a8f9..1064602504 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -1031,18 +1031,18 @@ static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int log2Width = firstImage->WidthLog2; log2Height = firstImage->HeightLog2; log2Depth = firstImage->DepthLog2; - texelBytes = _mesa_get_format_bytes(firstImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); if (!t->image_override) { - if (VALID_FORMAT(firstImage->TexFormat->MesaFormat)) { + if (VALID_FORMAT(firstImage->TexFormat)) { const struct tx_table *table = tx_table; t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK | RADEON_TXFORMAT_ALPHA_IN_MAP); t->pp_txfilter &= ~RADEON_YUV_TO_RGB; - t->pp_txformat |= table[ firstImage->TexFormat->MesaFormat ].format; - t->pp_txfilter |= table[ firstImage->TexFormat->MesaFormat ].filter; + t->pp_txformat |= table[ firstImage->TexFormat ].format; + t->pp_txfilter |= table[ firstImage->TexFormat ].filter; } else { _mesa_problem(NULL, "unexpected texture format in %s", __FUNCTION__); diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 3ff8cad93e..0378b3c9fc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -256,9 +256,9 @@ void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_objec /* try to find a format which will only need a memcopy */ -static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa, - GLenum srcFormat, - GLenum srcType, GLboolean fbo) +static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa, + GLenum srcFormat, + GLenum srcType, GLboolean fbo) { const GLuint ui = 1; const GLubyte littleEndian = *((const GLubyte *)&ui); @@ -271,37 +271,37 @@ static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPt (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) { - return &_mesa_texformat_rgba8888; + return MESA_FORMAT_RGBA8888; } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) || (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) { - return &_mesa_texformat_rgba8888_rev; + return MESA_FORMAT_RGBA8888_REV; } else if (IS_R200_CLASS(rmesa->radeonScreen)) { return _dri_texformat_argb8888; } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || srcType == GL_UNSIGNED_INT_8_8_8_8)) { - return &_mesa_texformat_argb8888_rev; + return MESA_FORMAT_ARGB8888_REV; } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else return _dri_texformat_argb8888; } -const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type) +gl_format radeonChooseTextureFormat_mesa(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type) { return radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); } -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type, GLboolean fbo) +gl_format radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo) { radeonContextPtr rmesa = RADEON_CONTEXT(ctx); const GLboolean do32bpt = @@ -425,50 +425,50 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; case GL_ALPHA16F_ARB: - return &_mesa_texformat_alpha_float16; + return MESA_FORMAT_ALPHA_FLOAT16; case GL_ALPHA32F_ARB: - return &_mesa_texformat_alpha_float32; + return MESA_FORMAT_ALPHA_FLOAT32; case GL_LUMINANCE16F_ARB: - return &_mesa_texformat_luminance_float16; + return MESA_FORMAT_LUMINANCE_FLOAT16; case GL_LUMINANCE32F_ARB: - return &_mesa_texformat_luminance_float32; + return MESA_FORMAT_LUMINANCE_FLOAT32; case GL_LUMINANCE_ALPHA16F_ARB: - return &_mesa_texformat_luminance_alpha_float16; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16; case GL_LUMINANCE_ALPHA32F_ARB: - return &_mesa_texformat_luminance_alpha_float32; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32; case GL_INTENSITY16F_ARB: - return &_mesa_texformat_intensity_float16; + return MESA_FORMAT_INTENSITY_FLOAT16; case GL_INTENSITY32F_ARB: - return &_mesa_texformat_intensity_float32; + return MESA_FORMAT_INTENSITY_FLOAT32; case GL_RGB16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGB32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; case GL_RGBA16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGBA32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT16: @@ -476,7 +476,7 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_DEPTH_COMPONENT32: case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - return &_mesa_texformat_s8_z24; + return MESA_FORMAT_S8_Z24; /* EXT_texture_sRGB */ case GL_SRGB: @@ -485,26 +485,26 @@ const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, case GL_SRGB8_ALPHA8: case GL_COMPRESSED_SRGB: case GL_COMPRESSED_SRGB_ALPHA: - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; case GL_SLUMINANCE: case GL_SLUMINANCE8: case GL_COMPRESSED_SLUMINANCE: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case GL_SLUMINANCE_ALPHA: case GL_SLUMINANCE8_ALPHA8: case GL_COMPRESSED_SLUMINANCE_ALPHA: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; default: _mesa_problem(ctx, "unexpected internalFormat 0x%x in %s", (int)internalFormat, __func__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } /** @@ -544,18 +544,18 @@ static void radeon_teximage( texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type, 0); _mesa_set_fetch_functions(texImage, dims); - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { texelBytes = 0; texImage->IsCompressed = GL_TRUE; texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { texImage->IsCompressed = GL_FALSE; texImage->CompressedSize = 0; - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* Minimum pitch of 32 bytes */ if (postConvWidth * texelBytes < 32) { postConvWidth = 32 / texelBytes; @@ -593,7 +593,7 @@ static void radeon_teximage( if (texImage->IsCompressed) { size = texImage->CompressedSize; } else { - size = texImage->Width * texImage->Height * texImage->Depth * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + size = texImage->Width * texImage->Height * texImage->Depth * _mesa_get_format_bytes(texImage->TexFormat); } texImage->Data = _mesa_alloc_texmemory(size); } @@ -613,7 +613,7 @@ static void radeon_teximage( if (compressed) { if (image->mt) { uint32_t srcRowStride, bytesPerRow, rows; - srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat, width); bytesPerRow = srcRowStride; rows = (height + 3) / 4; copy_rows(texImage->Data, image->mt->levels[level].rowstride, @@ -629,7 +629,7 @@ static void radeon_teximage( radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; dstRowStride = lvl->rowstride; } else { - dstRowStride = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat); } if (dims == 3) { @@ -640,7 +640,7 @@ static void radeon_teximage( _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage"); for (i = 0; i < depth; ++i) { - dstImageOffsets[i] = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat->MesaFormat) * height * i; + dstImageOffsets[i] = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat) * height * i; } } else { dstImageOffsets = texImage->ImageOffsets; @@ -756,23 +756,23 @@ static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int leve radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel]; dstRowStride = lvl->rowstride; } else { - dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat); } if (compressed) { uint32_t srcRowStride, bytesPerRow, rows; GLubyte *img_start; if (!image->mt) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, texImage->Width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, texImage->Width); img_start = _mesa_compressed_image_address(xoffset, yoffset, 0, - texImage->TexFormat->MesaFormat, + texImage->TexFormat, texImage->Width, texImage->Data); } else { uint32_t blocks_x = dstRowStride / (image->mt->bpp * 4); img_start = texImage->Data + image->mt->bpp * 4 * (blocks_x * (yoffset / 4) + xoffset / 4); } - srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat, width); bytesPerRow = srcRowStride; rows = (height + 3) / 4; @@ -895,10 +895,10 @@ static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_imag /* need to confirm this value is correct */ if (mt->compressed) { height = (image->base.Height + 3) / 4; - srcrowstride = _mesa_compressed_row_stride(image->base.TexFormat->MesaFormat, image->base.Width); + srcrowstride = _mesa_compressed_row_stride(image->base.TexFormat, image->base.Width); } else { height = image->base.Height * image->base.Depth; - srcrowstride = image->base.Width * _mesa_get_format_bytes(image->base.TexFormat->MesaFormat); + srcrowstride = image->base.Width * _mesa_get_format_bytes(image->base.TexFormat); } // if (mt->tilebits) diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h index 888a55ba91..8995546d77 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.h +++ b/src/mesa/drivers/dri/radeon/radeon_texture.h @@ -30,6 +30,10 @@ #ifndef RADEON_TEXTURE_H #define RADEON_TEXTURE_H + +#include "main/formats.h" + + struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx); void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage); @@ -40,14 +44,16 @@ void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj); void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj); int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj); GLuint radeon_face_for_target(GLenum target); -const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type); -const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx, - GLint internalFormat, - GLenum format, - GLenum type, GLboolean fbo); + +gl_format radeonChooseTextureFormat_mesa(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type); + +gl_format radeonChooseTextureFormat(GLcontext * ctx, + GLint internalFormat, + GLenum format, + GLenum type, GLboolean fbo); void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level, GLint internalFormat, diff --git a/src/mesa/drivers/dri/savage/savagetex.c b/src/mesa/drivers/dri/savage/savagetex.c index fe239e1b05..796da4fc0d 100644 --- a/src/mesa/drivers/dri/savage/savagetex.c +++ b/src/mesa/drivers/dri/savage/savagetex.c @@ -527,6 +527,11 @@ savageAllocTexObj( struct gl_texture_object *texObj ) * components to white. This way we get the correct result. */ +#if 0 +/* Using MESA_FORMAT_RGBA8888 to store alpha-only textures should + * work but is space inefficient. + */ + static GLboolean _savage_texstore_a1114444(TEXSTORE_PARAMS); @@ -590,10 +595,11 @@ _savage_texstore_a1114444(TEXSTORE_PARAMS) return GL_FALSE; _mesa_adjust_image_for_convolution(ctx, dims, &srcWidth, &srcHeight); for (img = 0; img < srcDepth; img++) { + GLuint texelBytes = _mesa_get_format_bytes(dstFormat); GLubyte *dstRow = (GLubyte *) dstAddr - + dstImageOffsets[dstZoffset + img] * dstFormat->TexelBytes + + dstImageOffsets[dstZoffset + img] * texelBytes + dstYoffset * dstRowStride - + dstXoffset * dstFormat->TexelBytes; + + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUI = (GLushort *) dstRow; for (col = 0; col < srcWidth; col++) { @@ -629,10 +635,11 @@ _savage_texstore_a1118888(TEXSTORE_PARAMS) return GL_FALSE; _mesa_adjust_image_for_convolution(ctx, dims, &srcWidth, &srcHeight); for (img = 0; img < srcDepth; img++) { + GLuint texelBytes = _mesa_get_format_bytes(dstFormat); GLubyte *dstRow = (GLubyte *) dstAddr - + dstImageOffsets[dstZoffset + img] * dstFormat->TexelBytes + + dstImageOffsets[dstZoffset + img] * texelBytes + dstYoffset * dstRowStride - + dstXoffset * dstFormat->TexelBytes; + + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; for (col = 0; col < srcWidth; col++) { @@ -647,10 +654,11 @@ _savage_texstore_a1118888(TEXSTORE_PARAMS) return GL_TRUE; } +#endif /* Called by the _mesa_store_teximage[123]d() functions. */ -static const struct gl_texture_format * +static gl_format savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -669,15 +677,15 @@ savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_INT_10_10_10_2: case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; } case 3: @@ -686,129 +694,152 @@ savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_5_6_5: case GL_UNSIGNED_SHORT_5_6_5_REV: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; } case GL_RGBA8: case GL_RGBA12: case GL_RGBA16: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGB10_A2: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGB5: case GL_RGB4: case GL_R3_G3_B2: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_COMPRESSED_ALPHA: - return isSavage4 ? &_mesa_texformat_a8 : ( +#if 0 + return isSavage4 ? MESA_FORMAT_a8 : ( do32bpt ? &_savage_texformat_a1118888 : &_savage_texformat_a1114444); +#else + if (isSavage4) + return MESA_FORMAT_A8; + else if (do32bpt) + return MESA_FORMAT_ARGB8888; + else + return MESA_FORMAT_ARGB4444; +#endif case GL_ALPHA4: - return isSavage4 ? &_mesa_texformat_a8 : &_savage_texformat_a1114444; +#if 0 + return isSavage4 ? MESA_FORMAT_a8 : &_savage_texformat_a1114444; +#else + if (isSavage4) + return MESA_FORMAT_A8; + else + return MESA_FORMAT_ARGB4444; +#endif case GL_ALPHA8: case GL_ALPHA12: case GL_ALPHA16: - return isSavage4 ? &_mesa_texformat_a8 : ( +#if 0 + return isSavage4 ? MESA_FORMAT_a8 : ( !force16bpt ? &_savage_texformat_a1118888 : &_savage_texformat_a1114444); - +#else + if (isSavage4) + return MESA_FORMAT_A8; + else if (force16bpt) + return MESA_FORMAT_ARGB4444; + else + return MESA_FORMAT_ARGB8888; +#endif case 1: case GL_LUMINANCE: case GL_COMPRESSED_LUMINANCE: /* no alpha, but use argb1555 in 16bit case to get pure grey values */ - return isSavage4 ? &_mesa_texformat_l8 : ( - do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555); + return isSavage4 ? MESA_FORMAT_L8 : ( + do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555); case GL_LUMINANCE4: - return isSavage4 ? &_mesa_texformat_l8 : &_mesa_texformat_argb1555; + return isSavage4 ? MESA_FORMAT_L8 : MESA_FORMAT_ARGB1555; case GL_LUMINANCE8: case GL_LUMINANCE12: case GL_LUMINANCE16: - return isSavage4 ? &_mesa_texformat_l8 : ( - !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555); + return isSavage4 ? MESA_FORMAT_L8 : ( + !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555); case 2: case GL_LUMINANCE_ALPHA: case GL_COMPRESSED_LUMINANCE_ALPHA: /* Savage4 has a al44 texture format. But it's not supported by Mesa. */ - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_LUMINANCE4_ALPHA4: case GL_LUMINANCE6_ALPHA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_LUMINANCE8_ALPHA8: case GL_LUMINANCE12_ALPHA4: case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: - return !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; #if 0 /* TFT_I8 produces garbage on ProSavageDDR and subsequent texture * disable keeps rendering garbage. Disabled for now. */ case GL_INTENSITY: case GL_COMPRESSED_INTENSITY: - return isSavage4 ? &_mesa_texformat_i8 : ( - do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444); + return isSavage4 ? MESA_FORMAT_i8 : ( + do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444); case GL_INTENSITY4: - return isSavage4 ? &_mesa_texformat_i8 : &_mesa_texformat_argb4444; + return isSavage4 ? MESA_FORMAT_i8 : MESA_FORMAT_ARGB4444; case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: - return isSavage4 ? &_mesa_texformat_i8 : ( - !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444); + return isSavage4 ? MESA_FORMAT_i8 : ( + !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444); #else case GL_INTENSITY: case GL_COMPRESSED_INTENSITY: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_INTENSITY4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: - return !force16bpt ? &_mesa_texformat_argb8888 : - &_mesa_texformat_argb4444; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; #endif case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: if (!isSavage4) /* Not the best choice but Savage3D/MX/IX don't support DXT3 or DXT5. */ - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; /* fall through */ case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; /* case GL_COLOR_INDEX: @@ -822,7 +853,7 @@ savageChooseTextureFormat( GLcontext *ctx, GLint internalFormat, */ default: _mesa_problem(ctx, "unexpected texture format in %s", __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } } @@ -837,7 +868,7 @@ static void savageSetTexImages( savageContextPtr imesa, assert(t); assert(image); - switch (image->TexFormat->MesaFormat) { + switch (image->TexFormat) { case MESA_FORMAT_ARGB8888: textureFormat = TFT_ARGB8888; t->texelBytes = tileIndex = 4; @@ -2083,6 +2114,7 @@ void savageDDInitTextureFuncs( struct dd_function_table *functions ) /* Texel fetching with our custom texture formats works just like * the standard argb formats. */ +#if 0 _savage_texformat_a1114444.FetchTexel1D = _mesa_texformat_argb4444.FetchTexel1D; _savage_texformat_a1114444.FetchTexel2D = _mesa_texformat_argb4444.FetchTexel2D; _savage_texformat_a1114444.FetchTexel3D = _mesa_texformat_argb4444.FetchTexel3D; @@ -2096,4 +2128,5 @@ void savageDDInitTextureFuncs( struct dd_function_table *functions ) _savage_texformat_a1118888.FetchTexel1Df= _mesa_texformat_argb8888.FetchTexel1Df; _savage_texformat_a1118888.FetchTexel2Df= _mesa_texformat_argb8888.FetchTexel2Df; _savage_texformat_a1118888.FetchTexel3Df= _mesa_texformat_argb8888.FetchTexel3Df; +#endif } diff --git a/src/mesa/drivers/dri/sis/sis_tex.c b/src/mesa/drivers/dri/sis/sis_tex.c index 38a309d41f..5dc05146b1 100644 --- a/src/mesa/drivers/dri/sis/sis_tex.c +++ b/src/mesa/drivers/dri/sis/sis_tex.c @@ -65,7 +65,7 @@ sisAllocTexImage( sisContextPtr smesa, sisTexObjPtr t, int level, if (t->format == 0) { t->format = image->_BaseFormat; - switch (image->TexFormat->MesaFormat) + switch (image->TexFormat) { case MESA_FORMAT_ARGB8888: t->hwformat = TEXEL_ARGB_8888_32; @@ -101,13 +101,12 @@ sisAllocTexImage( sisContextPtr smesa, sisTexObjPtr t, int level, t->hwformat = TEXEL_VUY422; break; default: - sis_fatal_error("Bad texture format 0x%x.\n", - image->TexFormat->MesaFormat); + sis_fatal_error("Bad texture format 0x%x.\n", image->TexFormat); } } assert(t->format == image->_BaseFormat); - texel_size = _mesa_get_format_bytes(image->TexFormat->MesaFormat); + texel_size = _mesa_get_format_bytes(image->TexFormat); size = image->Width * image->Height * texel_size + TEXTURE_HW_PLUS; addr = sisAllocFB( smesa, size, &t->image[level].handle ); @@ -230,7 +229,7 @@ static GLboolean sisIsTextureResident( GLcontext * ctx, return (texObj->DriverData != NULL); } -static const struct gl_texture_format * +static gl_format sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -248,15 +247,15 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_INT_10_10_10_2: case GL_UNSIGNED_INT_2_10_10_10_REV: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; } case 3: @@ -265,46 +264,46 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, switch ( type ) { case GL_UNSIGNED_SHORT_4_4_4_4: case GL_UNSIGNED_SHORT_4_4_4_4_REV: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_UNSIGNED_SHORT_5_5_5_1: case GL_UNSIGNED_SHORT_1_5_5_5_REV: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_UNSIGNED_SHORT_5_6_5: case GL_UNSIGNED_SHORT_5_6_5_REV: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; default: - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; } case GL_RGBA8: case GL_RGBA12: case GL_RGBA16: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGB10_A2: return !force16bpt ? - &_mesa_texformat_argb8888 : &_mesa_texformat_argb1555; + MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB1555; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return !force16bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return !force16bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGB5: case GL_RGB4: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_R3_G3_B2: - return &_mesa_texformat_rgb332; + return MESA_FORMAT_RGB332; case GL_ALPHA: case GL_ALPHA4: /* FIXME: This could use its own texstore */ @@ -312,7 +311,7 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: @@ -321,7 +320,7 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: @@ -332,7 +331,7 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: @@ -340,19 +339,19 @@ sisChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_APPLE || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; default: _mesa_problem(ctx, "unexpected format in sisDDChooseTextureFormat: %d", internalFormat); - return NULL; + return MESA_FORMAT_NONE; } } @@ -425,7 +424,7 @@ static void sisTexSubImage1D( GLcontext *ctx, /* Upload the texture */ WaitEngIdle(smesa); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); copySize = width * texelBytes; src = (char *)texImage->Data + xoffset * texelBytes; @@ -513,7 +512,7 @@ static void sisTexSubImage2D( GLcontext *ctx, /* Upload the texture */ WaitEngIdle(smesa); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); copySize = width * texelBytes; src = (char *)texImage->Data + (xoffset + yoffset * texImage->Width) * diff --git a/src/mesa/drivers/dri/tdfx/tdfx_tex.c b/src/mesa/drivers/dri/tdfx/tdfx_tex.c index 51d86aea37..427d315a01 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_tex.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_tex.c @@ -72,13 +72,13 @@ _mesa_halve2x2_teximage2d ( GLcontext *ctx, GLubyte *_d = NULL; GLenum _t = 0; - if (texImage->TexFormat->MesaFormat == MESA_FORMAT_RGB565) { + if (texImage->TexFormat == MESA_FORMAT_RGB565) { _t = GL_UNSIGNED_SHORT_5_6_5_REV; bpt = bytesPerPixel; - } else if (texImage->TexFormat->MesaFormat == MESA_FORMAT_ARGB4444) { + } else if (texImage->TexFormat == MESA_FORMAT_ARGB4444) { _t = GL_UNSIGNED_SHORT_4_4_4_4_REV; bpt = bytesPerPixel; - } else if (texImage->TexFormat->MesaFormat == MESA_FORMAT_ARGB1555) { + } else if (texImage->TexFormat == MESA_FORMAT_ARGB1555) { _t = GL_UNSIGNED_SHORT_1_5_5_5_REV; bpt = bytesPerPixel; } @@ -94,7 +94,7 @@ _mesa_halve2x2_teximage2d ( GLcontext *ctx, _s = src = MALLOC(srcRowStride * srcHeight); _d = dst = MALLOC(dstWidth * bytesPerPixel * dstHeight); _mesa_texstore(ctx, 2, GL_RGBA, - &_mesa_texformat_rgba8888_rev, src, + MESA_FORMAT_RGBA8888_REV, src, 0, 0, 0, /* dstX/Y/Zoffset */ srcRowStride, /* dstRowStride */ &dstImageOffsets, @@ -190,6 +190,7 @@ tdfxGenerateMipmap(GLcontext *ctx, GLenum target, const tdfxMipMapLevel *mml; texImage = _mesa_get_tex_image(ctx, texObj, target, level); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); assert(!texImage->IsCompressed); mml = TDFX_TEXIMAGE_DATA(texImage); @@ -760,7 +761,7 @@ fxTexusError(const char *string, FxBool fatal) #endif -static const struct gl_texture_format * +static gl_format tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum srcFormat, GLenum srcType ) { @@ -774,7 +775,7 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: case GL_LUMINANCE4: @@ -782,7 +783,7 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: case GL_LUMINANCE4_ALPHA4: @@ -792,48 +793,47 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_R3_G3_B2: case GL_RGB4: case GL_RGB5: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_COMPRESSED_RGB: /* intentional fall-through */ case 3: case GL_RGB: if ( srcFormat == GL_RGB && srcType == GL_UNSIGNED_SHORT_5_6_5 ) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } /* intentional fall through */ case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return (allow32bpt) ? &_mesa_texformat_argb8888 - : &_mesa_texformat_rgb565; + return (allow32bpt) ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA2: case GL_RGBA4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_COMPRESSED_RGBA: /* intentional fall-through */ case 4: case GL_RGBA: if ( srcFormat == GL_BGRA ) { if ( srcType == GL_UNSIGNED_INT_8_8_8_8_REV ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if ( srcType == GL_UNSIGNED_SHORT_4_4_4_4_REV ) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if ( srcType == GL_UNSIGNED_SHORT_1_5_5_5_REV ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } /* intentional fall through */ @@ -841,10 +841,9 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return allow32bpt ? &_mesa_texformat_argb8888 - : &_mesa_texformat_argb4444; + return allow32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: case GL_COLOR_INDEX2_EXT: @@ -852,29 +851,29 @@ tdfxChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; /* GL_EXT_texture_compression_s3tc */ /* GL_S3_s3tc */ case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: case GL_RGB_S3TC: case GL_RGB4_S3TC: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: case GL_RGBA_S3TC: case GL_RGBA4_S3TC: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; /* GL_3DFX_texture_compression_FXT1 */ case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; default: _mesa_problem(ctx, "unexpected format in tdfxChooseTextureFormat"); - return NULL; + return MESA_FORMAT_NONE; } } @@ -1126,7 +1125,9 @@ fetch_rgb_dxt1(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgb_dxt1.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1139,7 +1140,9 @@ fetch_rgba_dxt1(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgba_dxt1.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1152,7 +1155,9 @@ fetch_rgba_dxt3(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgba_dxt3.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1165,7 +1170,9 @@ fetch_rgba_dxt5(const struct gl_texture_image *texImage, i = i * mml->wScale; j = j * mml->hScale; + /* XXX Get fetch func from _mesa_get_texel_fetch_func() _mesa_texformat_rgba_dxt5.FetchTexel2D(texImage, i, j, k, rgba); + */ } @@ -1268,7 +1275,7 @@ adjust2DRatio (GLcontext *ctx, } /* unpack image, apply transfer ops and store in rawImage */ _mesa_texstore(ctx, 2, GL_RGBA, - &_mesa_texformat_rgba8888_rev, rawImage, + MESA_FORMAT_RGBA8888_REV, rawImage, 0, 0, 0, /* dstX/Y/Zoffset */ width * rawBytes, /* dstRowStride */ &dstImageOffsets, @@ -1396,11 +1403,11 @@ tdfxTexImage2D(GLcontext *ctx, GLenum target, GLint level, texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, internalFormat, format, type); assert(texImage->TexFormat); - mesaFormat = texImage->TexFormat->MesaFormat; + mesaFormat = texImage->TexFormat; mml->glideFormat = fxGlideFormat(mesaFormat); ti->info.format = mml->glideFormat; texImage->FetchTexelc = fxFetchFunction(mesaFormat); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); if (texImage->IsCompressed) { texImage->CompressedSize = _mesa_compressed_texture_size(ctx, @@ -1408,7 +1415,7 @@ tdfxTexImage2D(GLcontext *ctx, GLenum target, GLint level, mml->height, 1, mesaFormat); - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, mml->width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, mml->width); texImage->Data = _mesa_alloc_texmemory(texImage->CompressedSize); } else { dstRowStride = mml->width * texelBytes; @@ -1484,9 +1491,9 @@ tdfxTexSubImage2D(GLcontext *ctx, GLenum target, GLint level, assert(texImage->Data); /* must have an existing texture image! */ assert(texImage->_BaseFormat); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, mml->width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, mml->width); } else { dstRowStride = mml->width * texelBytes; } @@ -1626,7 +1633,7 @@ tdfxCompressedTexImage2D (GLcontext *ctx, GLenum target, /* Determine the appropriate Glide texel format, * given the user's internal texture format hint. */ - mesaFormat = texImage->TexFormat->MesaFormat; + mesaFormat = texImage->TexFormat; mml->glideFormat = fxGlideFormat(mesaFormat); ti->info.format = mml->glideFormat; texImage->FetchTexelc = fxFetchFunction(mesaFormat); @@ -1661,7 +1668,7 @@ tdfxCompressedTexImage2D (GLcontext *ctx, GLenum target, * we replicate the data over the padded area. * For now, we take 2) + 3) but texelfetchers will be wrong! */ - const GLuint mesaFormat = texImage->TexFormat->MesaFormat; + const GLuint mesaFormat = texImage->TexFormat; GLuint srcRowStride = _mesa_compressed_row_stride(mesaFormat, width); GLuint destRowStride = _mesa_compressed_row_stride(mesaFormat, @@ -1698,7 +1705,7 @@ tdfxCompressedTexSubImage2D( GLcontext *ctx, GLenum target, GLint destRowStride, srcRowStride; GLint i, rows; GLubyte *dest; - const GLuint mesaFormat = texImage->TexFormat->MesaFormat; + const GLuint mesaFormat = texImage->TexFormat; if (TDFX_DEBUG & DEBUG_VERBOSE_DRI) { fprintf(stderr, "tdfxCompressedTexSubImage2D: id=%d\n", texObj->Name); diff --git a/src/mesa/drivers/dri/unichrome/via_tex.c b/src/mesa/drivers/dri/unichrome/via_tex.c index f700994025..b6be06d1ee 100644 --- a/src/mesa/drivers/dri/unichrome/via_tex.c +++ b/src/mesa/drivers/dri/unichrome/via_tex.c @@ -49,7 +49,7 @@ #include "via_ioctl.h" #include "via_3d_reg.h" -static const struct gl_texture_format * +static gl_format viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -66,56 +66,56 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, if ( format == GL_BGRA ) { if ( type == GL_UNSIGNED_INT_8_8_8_8_REV || type == GL_UNSIGNED_BYTE ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if ( type == GL_UNSIGNED_SHORT_4_4_4_4_REV ) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if ( type == GL_UNSIGNED_SHORT_1_5_5_5_REV ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } else if ( type == GL_UNSIGNED_BYTE || type == GL_UNSIGNED_INT_8_8_8_8_REV || type == GL_UNSIGNED_INT_8_8_8_8 ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_argb4444; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB4444; case 3: case GL_RGB: case GL_COMPRESSED_RGB: if ( format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5 ) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } else if ( type == GL_UNSIGNED_BYTE ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } - return do32bpt ? &_mesa_texformat_argb8888 : &_mesa_texformat_rgb565; + return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA8: case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case GL_RGBA4: case GL_RGBA2: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case GL_RGB5: case GL_RGB4: case GL_R3_G3_B2: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_ALPHA: case GL_ALPHA4: @@ -123,7 +123,7 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case 1: case GL_LUMINANCE: @@ -132,7 +132,7 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case 2: case GL_LUMINANCE_ALPHA: @@ -143,7 +143,7 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: @@ -151,35 +151,35 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_YCBCR_MESA: if (type == GL_UNSIGNED_SHORT_8_8_MESA || type == GL_UNSIGNED_BYTE) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; case GL_RGB_S3TC: case GL_RGB4_S3TC: case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: @@ -188,16 +188,16 @@ viaChooseTexFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; default: fprintf(stderr, "unexpected texture format %s in %s\n", _mesa_lookup_enum_by_nr(internalFormat), __FUNCTION__); - return NULL; + return MESA_FORMAT_NONE; } - return NULL; /* never get here */ + return MESA_FORMAT_NONE; /* never get here */ } static int logbase2(int n) @@ -458,7 +458,7 @@ static GLboolean viaSetTexImages(GLcontext *ctx, GLuint widthExp = 0; GLuint heightExp = 0; - switch (baseImage->image.TexFormat->MesaFormat) { + switch (baseImage->image.TexFormat) { case MESA_FORMAT_ARGB8888: texFormat = HC_HTXnFM_ARGB8888; break; @@ -692,7 +692,7 @@ static void viaTexImage(GLcontext *ctx, _mesa_set_fetch_functions(texImage, dims); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); if (texelBytes == 0) { /* compressed format */ @@ -700,7 +700,7 @@ static void viaTexImage(GLcontext *ctx, texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } /* Minimum pitch of 32 bytes */ @@ -794,10 +794,10 @@ static void viaTexImage(GLcontext *ctx, GLboolean success; if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, width); } else { - dstRowStride = postConvWidth * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + dstRowStride = postConvWidth * _mesa_get_format_bytes(texImage->TexFormat); } success = _mesa_texstore(ctx, dims, texImage->_BaseFormat, diff --git a/src/mesa/drivers/glide/fxddtex.c b/src/mesa/drivers/glide/fxddtex.c index 354015af1d..a64b6a5553 100644 --- a/src/mesa/drivers/glide/fxddtex.c +++ b/src/mesa/drivers/glide/fxddtex.c @@ -1016,7 +1016,7 @@ PrintTexture(int w, int h, int c, const GLubyte * data) #endif -const struct gl_texture_format * +gl_format fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, GLenum srcFormat, GLenum srcType ) { @@ -1033,31 +1033,31 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case 3: case GL_RGB: if ( srcFormat == GL_RGB && srcType == GL_UNSIGNED_SHORT_5_6_5 ) { - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; } /* intentional fall through */ case GL_RGB8: case GL_RGB10: case GL_RGB12: case GL_RGB16: - return (allow32bpt) ? &_mesa_texformat_argb8888 - : &_mesa_texformat_rgb565; + return (allow32bpt) ? MESA_FORMAT_ARGB8888 + : MESA_FORMAT_RGB565; case GL_RGBA2: case GL_RGBA4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case GL_COMPRESSED_RGBA: /* intentional fall through */ case 4: case GL_RGBA: if ( srcFormat == GL_BGRA ) { if ( srcType == GL_UNSIGNED_INT_8_8_8_8_REV ) { - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; } else if ( srcType == GL_UNSIGNED_SHORT_4_4_4_4_REV ) { - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; } else if ( srcType == GL_UNSIGNED_SHORT_1_5_5_5_REV ) { - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; } } /* intentional fall through */ @@ -1065,15 +1065,15 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return (allow32bpt) ? &_mesa_texformat_argb8888 - : &_mesa_texformat_argb4444; + return (allow32bpt) ? MESA_FORMAT_ARGB8888 + : MESA_FORMAT_ARGB4444; case GL_INTENSITY: case GL_INTENSITY4: case GL_INTENSITY8: case GL_INTENSITY12: case GL_INTENSITY16: case GL_COMPRESSED_INTENSITY: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case 1: case GL_LUMINANCE: case GL_LUMINANCE4: @@ -1081,14 +1081,14 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12: case GL_LUMINANCE16: case GL_COMPRESSED_LUMINANCE: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case GL_ALPHA: case GL_ALPHA4: case GL_ALPHA8: case GL_ALPHA12: case GL_ALPHA16: case GL_COMPRESSED_ALPHA: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: case GL_COLOR_INDEX2_EXT: @@ -1096,7 +1096,7 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX8_EXT: case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; case 2: case GL_LUMINANCE_ALPHA: case GL_LUMINANCE4_ALPHA4: @@ -1106,35 +1106,35 @@ fxDDChooseTextureFormat( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_R3_G3_B2: case GL_RGB4: case GL_RGB5: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; /* GL_EXT_texture_compression_s3tc */ /* GL_S3_s3tc */ case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: case GL_RGB_S3TC: case GL_RGB4_S3TC: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: case GL_RGBA_S3TC: case GL_RGBA4_S3TC: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; /* GL_3DFX_texture_compression_FXT1 */ case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; default: _mesa_problem(NULL, "unexpected format in fxDDChooseTextureFormat"); - return NULL; + return MESA_FORMAT_NONE; } } diff --git a/src/mesa/drivers/x11/xm_dd.c b/src/mesa/drivers/x11/xm_dd.c index e2d4aa9b2d..5b00b5b82c 100644 --- a/src/mesa/drivers/x11/xm_dd.c +++ b/src/mesa/drivers/x11/xm_dd.c @@ -1019,15 +1019,15 @@ test_proxy_teximage(GLcontext *ctx, GLenum target, GLint level, /** * In SW, we don't really compress GL_COMPRESSED_RGB[A] textures! */ -static const struct gl_texture_format * +static gl_format choose_tex_format( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { switch (internalFormat) { case GL_COMPRESSED_RGB_ARB: - return &_mesa_texformat_rgb; + return MESA_FORMAT_RGB; case GL_COMPRESSED_RGBA_ARB: - return &_mesa_texformat_rgba; + return MESA_FORMAT_RGBA; default: return _mesa_choose_tex_format(ctx, internalFormat, format, type); } diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h index ce5e158626..9131f20f52 100644 --- a/src/mesa/main/dd.h +++ b/src/mesa/main/dd.h @@ -184,8 +184,8 @@ struct dd_function_table { * functions. The driver should examine \p internalFormat and return a * pointer to an appropriate gl_texture_format. */ - const struct gl_texture_format *(*ChooseTextureFormat)( GLcontext *ctx, - GLint internalFormat, GLenum srcFormat, GLenum srcType ); + GLuint (*ChooseTextureFormat)( GLcontext *ctx, GLint internalFormat, + GLenum srcFormat, GLenum srcType ); /** * Called by glTexImage1D(). diff --git a/src/mesa/main/debug.c b/src/mesa/main/debug.c index 8492c8561d..391180a7c6 100644 --- a/src/mesa/main/debug.c +++ b/src/mesa/main/debug.c @@ -315,7 +315,7 @@ dump_texture_cb(GLuint id, void *data, void *userData) if (texImg) { _mesa_printf(" Image %u: %d x %d x %d, format %u at %p\n", i, texImg->Width, texImg->Height, texImg->Depth, - texImg->TexFormat->MesaFormat, texImg->Data); + texImg->TexFormat, texImg->Data); if (DumpImages && !written) { GLuint face = 0; write_texture_image(texObj, face, i); diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c index 04419da6e5..6610725de8 100644 --- a/src/mesa/main/fbobject.c +++ b/src/mesa/main/fbobject.c @@ -384,7 +384,7 @@ test_attachment_completeness(const GLcontext *ctx, GLenum format, return; } - baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + baseFormat = _mesa_get_format_base_format(texImage->TexFormat); if (format == GL_COLOR) { if (baseFormat != GL_RGB && @@ -393,7 +393,7 @@ test_attachment_completeness(const GLcontext *ctx, GLenum format, att->Complete = GL_FALSE; return; } - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { att_incomplete("compressed internalformat"); att->Complete = GL_FALSE; return; diff --git a/src/mesa/main/mipmap.c b/src/mesa/main/mipmap.c index c02c705228..7e99a5d3de 100644 --- a/src/mesa/main/mipmap.c +++ b/src/mesa/main/mipmap.c @@ -1561,7 +1561,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, } else { /* uncompressed */ - convertFormat = srcImage->TexFormat->MesaFormat; + convertFormat = srcImage->TexFormat; } _mesa_format_to_type_and_comps(convertFormat, &datatype, &comps); @@ -1620,7 +1620,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, = ctx->Driver.CompressedTextureSize(ctx, dstImage->Width, dstImage->Height, dstImage->Depth, - dstImage->TexFormat->MesaFormat); + dstImage->TexFormat); ASSERT(dstImage->CompressedSize > 0); } @@ -1642,7 +1642,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, ASSERT(dstData); } else { - bytesPerTexel = _mesa_get_format_bytes(dstImage->TexFormat->MesaFormat); + bytesPerTexel = _mesa_get_format_bytes(dstImage->TexFormat); ASSERT(dstWidth * dstHeight * dstDepth * bytesPerTexel > 0); dstImage->Data = _mesa_alloc_texmemory(dstWidth * dstHeight * dstDepth * bytesPerTexel); @@ -1666,7 +1666,7 @@ _mesa_generate_mipmap(GLcontext *ctx, GLenum target, /* compress image from dstData into dstImage->Data */ const GLenum srcFormat = _mesa_get_format_base_format(convertFormat); GLint dstRowStride - = _mesa_compressed_row_stride(dstImage->TexFormat->MesaFormat, dstWidth); + = _mesa_compressed_row_stride(dstImage->TexFormat, dstWidth); ASSERT(srcFormat == GL_RGB || srcFormat == GL_RGBA); _mesa_texstore(ctx, 2, dstImage->_BaseFormat, diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index d448e3e158..56d5e9fafd 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -1200,7 +1200,7 @@ struct gl_texture_image GLboolean IsClientData; /**< Data owned by client? */ GLboolean _IsPowerOfTwo; /**< Are all dimensions powers of two? */ - const struct gl_texture_format *TexFormat; + GLuint TexFormat; /**< XXX Really gl_format */ struct gl_texture_object *TexObject; /**< Pointer back to parent object */ diff --git a/src/mesa/main/texcompress_fxt1.c b/src/mesa/main/texcompress_fxt1.c index c401f82be0..54e24fd297 100644 --- a/src/mesa/main/texcompress_fxt1.c +++ b/src/mesa/main/texcompress_fxt1.c @@ -74,7 +74,7 @@ _mesa_texstore_rgb_fxt1(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 8 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgb_fxt1); + ASSERT(dstFormat == MESA_FORMAT_RGB_FXT1); ASSERT(dstXoffset % 8 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset == 0); @@ -88,7 +88,7 @@ _mesa_texstore_rgb_fxt1(TEXSTORE_PARAMS) /* convert image to RGB/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -106,7 +106,7 @@ _mesa_texstore_rgb_fxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); fxt1_encode(srcWidth, srcHeight, 3, pixels, srcRowStride, @@ -131,7 +131,7 @@ _mesa_texstore_rgba_fxt1(TEXSTORE_PARAMS) GLint texWidth = dstRowStride * 8 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_fxt1); + ASSERT(dstFormat == MESA_FORMAT_RGBA_FXT1); ASSERT(dstXoffset % 8 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset == 0); @@ -145,7 +145,7 @@ _mesa_texstore_rgba_fxt1(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -163,7 +163,7 @@ _mesa_texstore_rgba_fxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); fxt1_encode(srcWidth, srcHeight, 4, pixels, srcRowStride, diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c index 2294fdca73..69e43af0fd 100644 --- a/src/mesa/main/texcompress_s3tc.c +++ b/src/mesa/main/texcompress_s3tc.c @@ -165,7 +165,7 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 8; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgb_dxt1); + ASSERT(dstFormat == MESA_FORMAT_RGB_DXT1); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -179,7 +179,7 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS) /* convert image to RGB/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -197,7 +197,7 @@ _mesa_texstore_rgb_dxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { @@ -228,7 +228,7 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 8; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_dxt1); + ASSERT(dstFormat == MESA_FORMAT_RGBA_DXT1); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -242,7 +242,7 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -260,7 +260,7 @@ _mesa_texstore_rgba_dxt1(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels, @@ -290,7 +290,7 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_dxt3); + ASSERT(dstFormat == MESA_FORMAT_RGBA_DXT3); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -304,7 +304,7 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -321,7 +321,7 @@ _mesa_texstore_rgba_dxt3(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels, @@ -351,7 +351,7 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS) const GLint texWidth = dstRowStride * 4 / 16; /* a bit of a hack */ const GLchan *tempImage = NULL; - ASSERT(dstFormat == &_mesa_texformat_rgba_dxt5); + ASSERT(dstFormat == MESA_FORMAT_RGBA_DXT5); ASSERT(dstXoffset % 4 == 0); ASSERT(dstYoffset % 4 == 0); ASSERT(dstZoffset % 4 == 0); @@ -365,7 +365,7 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS) /* convert image to RGBA/GLchan */ tempImage = _mesa_make_temp_chan_image(ctx, dims, baseInternalFormat, - dstFormat->BaseFormat, + _mesa_get_format_base_format(dstFormat), srcWidth, srcHeight, srcDepth, srcFormat, srcType, srcAddr, srcPacking); @@ -382,7 +382,7 @@ _mesa_texstore_rgba_dxt5(TEXSTORE_PARAMS) } dst = _mesa_compressed_image_address(dstXoffset, dstYoffset, 0, - dstFormat->MesaFormat, + dstFormat, texWidth, (GLubyte *) dstAddr); if (ext_tx_compress_dxtn) { (*ext_tx_compress_dxtn)(4, srcWidth, srcHeight, pixels, diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c index 60b2065a6c..019193f134 100644 --- a/src/mesa/main/texformat.c +++ b/src/mesa/main/texformat.c @@ -130,7 +130,7 @@ static void store_null_texel(struct gl_texture_image *texImage, /***************************************************************/ /** \name Default GLchan-based formats */ /*@{*/ - +#if 0 const struct gl_texture_format _mesa_texformat_rgba = { MESA_FORMAT_RGBA, /* MesaFormat */ GL_RGBA, /* BaseFormat */ @@ -1016,6 +1016,7 @@ const struct gl_texture_format _mesa_null_texformat = { 0, /* StencilBits */ 0, /* TexelBytes */ }; +#endif /*@}*/ @@ -1035,7 +1036,7 @@ const struct gl_texture_format _mesa_null_texformat = { * This is called via dd_function_table::ChooseTextureFormat. Hardware drivers * will typically override this function with a specialized version. */ -const struct gl_texture_format * +gl_format _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ) { @@ -1049,15 +1050,15 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_RGB10_A2: case GL_RGBA12: case GL_RGBA16: - return &_mesa_texformat_rgba; + return MESA_FORMAT_RGBA; case GL_RGBA8: - return &_mesa_texformat_rgba8888; + return MESA_FORMAT_RGBA8888; case GL_RGB5_A1: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case GL_RGBA2: - return &_mesa_texformat_argb4444_rev; /* just to test another format*/ + return MESA_FORMAT_ARGB4444_REV; /* just to test another format*/ case GL_RGBA4: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; /* RGB formats */ case 3: @@ -1065,24 +1066,24 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_RGB10: case GL_RGB12: case GL_RGB16: - return &_mesa_texformat_rgb; + return MESA_FORMAT_RGB; case GL_RGB8: - return &_mesa_texformat_rgb888; + return MESA_FORMAT_RGB888; case GL_R3_G3_B2: - return &_mesa_texformat_rgb332; + return MESA_FORMAT_RGB332; case GL_RGB4: - return &_mesa_texformat_rgb565_rev; /* just to test another format */ + return MESA_FORMAT_RGB565_REV; /* just to test another format */ case GL_RGB5: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; /* Alpha formats */ case GL_ALPHA: case GL_ALPHA4: case GL_ALPHA12: case GL_ALPHA16: - return &_mesa_texformat_alpha; + return MESA_FORMAT_ALPHA; case GL_ALPHA8: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; /* Luminance formats */ case 1: @@ -1090,9 +1091,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE4: case GL_LUMINANCE12: case GL_LUMINANCE16: - return &_mesa_texformat_luminance; + return MESA_FORMAT_LUMINANCE; case GL_LUMINANCE8: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; /* Luminance/Alpha formats */ case 2: @@ -1102,17 +1103,17 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_LUMINANCE12_ALPHA4: case GL_LUMINANCE12_ALPHA12: case GL_LUMINANCE16_ALPHA16: - return &_mesa_texformat_luminance_alpha; + return MESA_FORMAT_LUMINANCE_ALPHA; case GL_LUMINANCE8_ALPHA8: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case GL_INTENSITY: case GL_INTENSITY4: case GL_INTENSITY12: case GL_INTENSITY16: - return &_mesa_texformat_intensity; + return MESA_FORMAT_INTENSITY; case GL_INTENSITY8: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case GL_COLOR_INDEX: case GL_COLOR_INDEX1_EXT: @@ -1121,7 +1122,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_COLOR_INDEX12_EXT: case GL_COLOR_INDEX16_EXT: case GL_COLOR_INDEX8_EXT: - return &_mesa_texformat_ci8; + return MESA_FORMAT_CI8; default: ; /* fallthrough */ @@ -1132,9 +1133,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: case GL_DEPTH_COMPONENT32: - return &_mesa_texformat_z32; + return MESA_FORMAT_Z32; case GL_DEPTH_COMPONENT16: - return &_mesa_texformat_z16; + return MESA_FORMAT_Z16; default: ; /* fallthrough */ } @@ -1142,35 +1143,35 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_COMPRESSED_ALPHA_ARB: - return &_mesa_texformat_alpha; + return MESA_FORMAT_ALPHA; case GL_COMPRESSED_LUMINANCE_ARB: - return &_mesa_texformat_luminance; + return MESA_FORMAT_LUMINANCE; case GL_COMPRESSED_LUMINANCE_ALPHA_ARB: - return &_mesa_texformat_luminance_alpha; + return MESA_FORMAT_LUMINANCE_ALPHA; case GL_COMPRESSED_INTENSITY_ARB: - return &_mesa_texformat_intensity; + return MESA_FORMAT_INTENSITY; case GL_COMPRESSED_RGB_ARB: #if FEATURE_texture_fxt1 if (ctx->Extensions.TDFX_texture_compression_FXT1) - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; #endif #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc || ctx->Extensions.S3_s3tc) - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; #endif - return &_mesa_texformat_rgb; + return MESA_FORMAT_RGB; case GL_COMPRESSED_RGBA_ARB: #if FEATURE_texture_fxt1 if (ctx->Extensions.TDFX_texture_compression_FXT1) - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; #endif #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc || ctx->Extensions.S3_s3tc) - return &_mesa_texformat_rgba_dxt3; /* Not rgba_dxt1, see spec */ + return MESA_FORMAT_RGBA_DXT3; /* Not rgba_dxt1, see spec */ #endif - return &_mesa_texformat_rgba; + return MESA_FORMAT_RGBA; default: ; /* fallthrough */ } @@ -1178,9 +1179,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.MESA_ycbcr_texture) { if (internalFormat == GL_YCBCR_MESA) { if (type == GL_UNSIGNED_SHORT_8_8_MESA) - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; else - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; } } @@ -1188,9 +1189,9 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.TDFX_texture_compression_FXT1) { switch (internalFormat) { case GL_COMPRESSED_RGB_FXT1_3DFX: - return &_mesa_texformat_rgb_fxt1; + return MESA_FORMAT_RGB_FXT1; case GL_COMPRESSED_RGBA_FXT1_3DFX: - return &_mesa_texformat_rgba_fxt1; + return MESA_FORMAT_RGBA_FXT1; default: ; /* fallthrough */ } @@ -1201,13 +1202,13 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.EXT_texture_compression_s3tc) { switch (internalFormat) { case GL_COMPRESSED_RGB_S3TC_DXT1_EXT: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; default: ; /* fallthrough */ } @@ -1217,10 +1218,10 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_RGB_S3TC: case GL_RGB4_S3TC: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case GL_RGBA_S3TC: case GL_RGBA4_S3TC: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; default: ; /* fallthrough */ } @@ -1230,29 +1231,29 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, if (ctx->Extensions.ARB_texture_float) { switch (internalFormat) { case GL_ALPHA16F_ARB: - return &_mesa_texformat_alpha_float16; + return MESA_FORMAT_ALPHA_FLOAT16; case GL_ALPHA32F_ARB: - return &_mesa_texformat_alpha_float32; + return MESA_FORMAT_ALPHA_FLOAT32; case GL_LUMINANCE16F_ARB: - return &_mesa_texformat_luminance_float16; + return MESA_FORMAT_LUMINANCE_FLOAT16; case GL_LUMINANCE32F_ARB: - return &_mesa_texformat_luminance_float32; + return MESA_FORMAT_LUMINANCE_FLOAT32; case GL_LUMINANCE_ALPHA16F_ARB: - return &_mesa_texformat_luminance_alpha_float16; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16; case GL_LUMINANCE_ALPHA32F_ARB: - return &_mesa_texformat_luminance_alpha_float32; + return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32; case GL_INTENSITY16F_ARB: - return &_mesa_texformat_intensity_float16; + return MESA_FORMAT_INTENSITY_FLOAT16; case GL_INTENSITY32F_ARB: - return &_mesa_texformat_intensity_float32; + return MESA_FORMAT_INTENSITY_FLOAT32; case GL_RGB16F_ARB: - return &_mesa_texformat_rgb_float16; + return MESA_FORMAT_RGB_FLOAT16; case GL_RGB32F_ARB: - return &_mesa_texformat_rgb_float32; + return MESA_FORMAT_RGB_FLOAT32; case GL_RGBA16F_ARB: - return &_mesa_texformat_rgba_float16; + return MESA_FORMAT_RGBA_FLOAT16; case GL_RGBA32F_ARB: - return &_mesa_texformat_rgba_float32; + return MESA_FORMAT_RGBA_FLOAT32; default: ; /* fallthrough */ } @@ -1262,7 +1263,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: - return &_mesa_texformat_z24_s8; + return MESA_FORMAT_Z24_S8; default: ; /* fallthrough */ } @@ -1272,7 +1273,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_DUDV_ATI: case GL_DU8DV8_ATI: - return &_mesa_texformat_dudv8; + return MESA_FORMAT_DUDV8; default: ; /* fallthrough */ } @@ -1282,7 +1283,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_RGBA_SNORM: case GL_RGBA8_SNORM: - return &_mesa_texformat_signed_rgba8888; + return MESA_FORMAT_SIGNED_RGBA8888; default: ; /* fallthrough */ } @@ -1294,48 +1295,48 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, switch (internalFormat) { case GL_SRGB_EXT: case GL_SRGB8_EXT: - return &_mesa_texformat_srgb8; + return MESA_FORMAT_SRGB8; case GL_SRGB_ALPHA_EXT: case GL_SRGB8_ALPHA8_EXT: - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; case GL_SLUMINANCE_EXT: case GL_SLUMINANCE8_EXT: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case GL_SLUMINANCE_ALPHA_EXT: case GL_SLUMINANCE8_ALPHA8_EXT: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; case GL_COMPRESSED_SLUMINANCE_EXT: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case GL_COMPRESSED_SLUMINANCE_ALPHA_EXT: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; case GL_COMPRESSED_SRGB_EXT: #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; #endif - return &_mesa_texformat_srgb8; + return MESA_FORMAT_SRGB8; case GL_COMPRESSED_SRGB_ALPHA_EXT: #if FEATURE_texture_s3tc if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt3; /* Not srgba_dxt1, see spec */ + return MESA_FORMAT_SRGBA_DXT3; /* Not srgba_dxt1, see spec */ #endif - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; #if FEATURE_texture_s3tc case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; break; case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt1; + return MESA_FORMAT_SRGBA_DXT1; break; case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt3; + return MESA_FORMAT_SRGBA_DXT3; break; case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT: if (ctx->Extensions.EXT_texture_compression_s3tc) - return &_mesa_texformat_srgba_dxt5; + return MESA_FORMAT_SRGBA_DXT5; break; #endif default: @@ -1345,7 +1346,7 @@ _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, #endif /* FEATURE_EXT_texture_sRGB */ _mesa_problem(ctx, "unexpected format in _mesa_choose_tex_format()"); - return NULL; + return MESA_FORMAT_NONE; } diff --git a/src/mesa/main/texformat.h b/src/mesa/main/texformat.h index 638eadff97..9095726ac2 100644 --- a/src/mesa/main/texformat.h +++ b/src/mesa/main/texformat.h @@ -39,7 +39,7 @@ #include "mtypes.h" #include "formats.h" - +#if 0 /** GLchan-valued formats */ /*@{*/ extern const struct gl_texture_format _mesa_texformat_rgba; @@ -143,9 +143,9 @@ extern const struct gl_texture_format _mesa_texformat_rgba_dxt5; /*@{*/ extern const struct gl_texture_format _mesa_null_texformat; /*@}*/ +#endif - -extern const struct gl_texture_format * +extern gl_format _mesa_choose_tex_format( GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type ); diff --git a/src/mesa/main/texformat_tmp.h b/src/mesa/main/texformat_tmp.h index eb160deff9..cb8386bbc8 100644 --- a/src/mesa/main/texformat_tmp.h +++ b/src/mesa/main/texformat_tmp.h @@ -1424,7 +1424,7 @@ static void FETCH(f_z24_s8)( const struct gl_texture_image *texImage, const GLuint *src = TEXEL_ADDR(GLuint, texImage, i, j, k, 1); const GLfloat scale = 1.0F / (GLfloat) 0xffffff; texel[0] = ((*src) >> 8) * scale; - ASSERT(texImage->TexFormat->MesaFormat == MESA_FORMAT_Z24_S8); + ASSERT(texImage->TexFormat == MESA_FORMAT_Z24_S8); ASSERT(texel[0] >= 0.0F); ASSERT(texel[0] <= 1.0F); } @@ -1451,7 +1451,7 @@ static void FETCH(f_s8_z24)( const struct gl_texture_image *texImage, const GLuint *src = TEXEL_ADDR(GLuint, texImage, i, j, k, 1); const GLfloat scale = 1.0F / (GLfloat) 0xffffff; texel[0] = ((*src) & 0x00ffffff) * scale; - ASSERT(texImage->TexFormat->MesaFormat == MESA_FORMAT_S8_Z24); + ASSERT(texImage->TexFormat == MESA_FORMAT_S8_Z24); ASSERT(texel[0] >= 0.0F); ASSERT(texel[0] <= 1.0F); } diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c index 2575d0d868..e9e408d8c5 100644 --- a/src/mesa/main/texgetimage.c +++ b/src/mesa/main/texgetimage.c @@ -49,7 +49,7 @@ static GLboolean is_srgb_teximage(const struct gl_texture_image *texImage) { - switch (texImage->TexFormat->MesaFormat) { + switch (texImage->TexFormat) { case MESA_FORMAT_SRGB8: case MESA_FORMAT_SRGBA8: case MESA_FORMAT_SARGB8: @@ -160,7 +160,7 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint level, if (format == GL_COLOR_INDEX) { GLuint indexRow[MAX_WIDTH]; GLint col; - GLuint indexBits = _mesa_get_format_bits(texImage->TexFormat->MesaFormat, GL_TEXTURE_INDEX_SIZE_EXT); + GLuint indexBits = _mesa_get_format_bits(texImage->TexFormat, GL_TEXTURE_INDEX_SIZE_EXT); /* Can't use FetchTexel here because that returns RGBA */ if (indexBits == 8) { const GLubyte *src = (const GLubyte *) texImage->Data; @@ -210,9 +210,9 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint level, (const GLushort *) texImage->Data + row * rowstride, width * sizeof(GLushort)); /* check for byte swapping */ - if ((texImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR + if ((texImage->TexFormat == MESA_FORMAT_YCBCR && type == GL_UNSIGNED_SHORT_8_8_REV_MESA) || - (texImage->TexFormat->MesaFormat == MESA_FORMAT_YCBCR_REV + (texImage->TexFormat == MESA_FORMAT_YCBCR_REV && type == GL_UNSIGNED_SHORT_8_8_MESA)) { if (!ctx->Pack.SwapBytes) _mesa_swap2((GLushort *) dest, width); @@ -259,7 +259,7 @@ _mesa_get_teximage(GLcontext *ctx, GLenum target, GLint level, GLint col; GLbitfield transferOps = 0x0; GLenum dataType = - _mesa_get_format_datatype(texImage->TexFormat->MesaFormat); + _mesa_get_format_datatype(texImage->TexFormat); /* clamp does not apply to GetTexImage (final conversion)? * Looks like we need clamp though when going from format @@ -350,7 +350,7 @@ _mesa_get_compressed_teximage(GLcontext *ctx, GLenum target, GLint level, /* don't use texImage->CompressedSize since that may be padded out */ size = _mesa_compressed_texture_size(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); /* just memcpy, no pixelstore or pixel transfer */ _mesa_memcpy(img, texImage->Data, size); @@ -439,7 +439,7 @@ getteximage_error_check(GLcontext *ctx, GLenum target, GLint level, return GL_TRUE; } - baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + baseFormat = _mesa_get_format_base_format(texImage->TexFormat); /* Make sure the requested image format is compatible with the * texture's format. Note that a color index texture can be converted diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c index 465da6b046..c4e5ce2682 100644 --- a/src/mesa/main/teximage.c +++ b/src/mesa/main/teximage.c @@ -900,7 +900,7 @@ clear_teximage_fields(struct gl_texture_image *img) img->HeightLog2 = 0; img->DepthLog2 = 0; img->Data = NULL; - img->TexFormat = &_mesa_null_texformat; + img->TexFormat = MESA_FORMAT_NONE; img->FetchTexelc = NULL; img->FetchTexelf = NULL; img->IsCompressed = 0; @@ -2232,8 +2232,8 @@ _mesa_TexImage1D( GLenum target, GLint level, GLint internalFormat, _mesa_init_teximage_fields(ctx, target, texImage, postConvWidth, 1, 1, border, internalFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); } } else { @@ -2352,8 +2352,8 @@ _mesa_TexImage2D( GLenum target, GLint level, GLint internalFormat, _mesa_init_teximage_fields(ctx, target, texImage, postConvWidth, postConvHeight, 1, border, internalFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); } } else { @@ -2456,8 +2456,8 @@ _mesa_TexImage3D( GLenum target, GLint level, GLint internalFormat, /* no error, set the tex image parameters */ _mesa_init_teximage_fields(ctx, target, texImage, width, height, depth, border, internalFormat); - texImage->TexFormat = (*ctx->Driver.ChooseTextureFormat)(ctx, - internalFormat, format, type); + texImage->TexFormat = + ctx->Driver.ChooseTextureFormat(ctx, internalFormat, format, type); } } else { diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c index d38d5a4c23..a9df1dac15 100644 --- a/src/mesa/main/texparam.c +++ b/src/mesa/main/texparam.c @@ -765,7 +765,7 @@ _mesa_GetTexLevelParameteriv( GLenum target, GLint level, goto out; } - texFormat = img->TexFormat->MesaFormat; + texFormat = img->TexFormat; isProxy = _mesa_is_proxy_texture(target); diff --git a/src/mesa/main/texrender.c b/src/mesa/main/texrender.c index 54e5668abc..81bb1d40ff 100644 --- a/src/mesa/main/texrender.c +++ b/src/mesa/main/texrender.c @@ -470,7 +470,7 @@ update_wrapper(GLcontext *ctx, const struct gl_renderbuffer_attachment *att) trb->TexImage = att->Texture->Image[att->CubeMapFace][att->TextureLevel]; ASSERT(trb->TexImage); - trb->Store = _mesa_get_texel_store_func(trb->TexImage->TexFormat->MesaFormat); + trb->Store = _mesa_get_texel_store_func(trb->TexImage->TexFormat); if (!trb->Store) { /* we'll never draw into some textures (compressed formats) */ trb->Store = store_nop; @@ -485,21 +485,21 @@ update_wrapper(GLcontext *ctx, const struct gl_renderbuffer_attachment *att) trb->Zoffset = att->Zoffset; } - texFormat = trb->TexImage->TexFormat->MesaFormat; + texFormat = trb->TexImage->TexFormat; trb->Base.Width = trb->TexImage->Width; trb->Base.Height = trb->TexImage->Height; trb->Base.InternalFormat = trb->TexImage->InternalFormat; /* XXX may need more special cases here */ - if (trb->TexImage->TexFormat->MesaFormat == MESA_FORMAT_Z24_S8) { + if (trb->TexImage->TexFormat == MESA_FORMAT_Z24_S8) { trb->Base._ActualFormat = GL_DEPTH24_STENCIL8_EXT; trb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; } - else if (trb->TexImage->TexFormat->MesaFormat == MESA_FORMAT_Z16) { + else if (trb->TexImage->TexFormat == MESA_FORMAT_Z16) { trb->Base._ActualFormat = GL_DEPTH_COMPONENT; trb->Base.DataType = GL_UNSIGNED_SHORT; } - else if (trb->TexImage->TexFormat->MesaFormat == MESA_FORMAT_Z32) { + else if (trb->TexImage->TexFormat == MESA_FORMAT_Z32) { trb->Base._ActualFormat = GL_DEPTH_COMPONENT; trb->Base.DataType = GL_UNSIGNED_INT; } diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c index ca298bb237..02e3df89cf 100644 --- a/src/mesa/main/texstore.c +++ b/src/mesa/main/texstore.c @@ -932,7 +932,7 @@ _mesa_swizzle_ubyte_image(GLcontext *ctx, static void memcpy_texture(GLcontext *ctx, GLuint dimensions, - const struct gl_texture_format *dstFormat, + gl_format dstFormat, GLvoid *dstAddr, GLint dstXoffset, GLint dstYoffset, GLint dstZoffset, GLint dstRowStride, @@ -948,7 +948,7 @@ memcpy_texture(GLcontext *ctx, srcWidth, srcHeight, srcFormat, srcType); const GLubyte *srcImage = (const GLubyte *) _mesa_image_address(dimensions, srcPacking, srcAddr, srcWidth, srcHeight, srcFormat, srcType, 0, 0, 0); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); const GLint bytesPerRow = srcWidth * texelBytes; #if 0 @@ -1017,15 +1017,15 @@ static GLboolean _mesa_texstore_rgba(TEXSTORE_PARAMS) { const GLint components = _mesa_components_in_format(baseInternalFormat); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); - - ASSERT(dstFormat == &_mesa_texformat_rgba || - dstFormat == &_mesa_texformat_rgb || - dstFormat == &_mesa_texformat_alpha || - dstFormat == &_mesa_texformat_luminance || - dstFormat == &_mesa_texformat_luminance_alpha || - dstFormat == &_mesa_texformat_intensity); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); + + ASSERT(dstFormat == MESA_FORMAT_RGBA || + dstFormat == MESA_FORMAT_RGB || + dstFormat == MESA_FORMAT_ALPHA || + dstFormat == MESA_FORMAT_LUMINANCE || + dstFormat == MESA_FORMAT_LUMINANCE_ALPHA || + dstFormat == MESA_FORMAT_INTENSITY); ASSERT(baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB || baseInternalFormat == GL_ALPHA || @@ -1048,7 +1048,7 @@ _mesa_texstore_rgba(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgb && + dstFormat == MESA_FORMAT_RGB && srcFormat == GL_RGBA && srcType == CHAN_TYPE) { /* extract RGB from RGBA */ @@ -1089,27 +1089,27 @@ _mesa_texstore_rgba(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if (dstFormat == &_mesa_texformat_rgba) { + if (dstFormat == MESA_FORMAT_RGBA) { dstmap = mappings[IDX_RGBA].from_rgba; components = 4; } - else if (dstFormat == &_mesa_texformat_rgb) { + else if (dstFormat == MESA_FORMAT_RGB) { dstmap = mappings[IDX_RGB].from_rgba; components = 3; } - else if (dstFormat == &_mesa_texformat_alpha) { + else if (dstFormat == MESA_FORMAT_ALPHA) { dstmap = mappings[IDX_ALPHA].from_rgba; components = 1; } - else if (dstFormat == &_mesa_texformat_luminance) { + else if (dstFormat == MESA_FORMAT_LUMINANCE) { dstmap = mappings[IDX_LUMINANCE].from_rgba; components = 1; } - else if (dstFormat == &_mesa_texformat_luminance_alpha) { + else if (dstFormat == MESA_FORMAT_LUMINANCE_ALPHA) { dstmap = mappings[IDX_LUMINANCE_ALPHA].from_rgba; components = 2; } - else if (dstFormat == &_mesa_texformat_intensity) { + else if (dstFormat == MESA_FORMAT_INTENSITY) { dstmap = mappings[IDX_INTENSITY].from_rgba; components = 1; } @@ -1168,9 +1168,9 @@ static GLboolean _mesa_texstore_z32(TEXSTORE_PARAMS) { const GLuint depthScale = 0xffffffff; - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) dims; - ASSERT(dstFormat == &_mesa_texformat_z32); + ASSERT(dstFormat == MESA_FORMAT_Z32); ASSERT(texelBytes == sizeof(GLuint)); if (ctx->Pixel.DepthScale == 1.0f && @@ -1217,9 +1217,9 @@ static GLboolean _mesa_texstore_z16(TEXSTORE_PARAMS) { const GLuint depthScale = 0xffff; - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) dims; - ASSERT(dstFormat == &_mesa_texformat_z16); + ASSERT(dstFormat == MESA_FORMAT_Z16); ASSERT(texelBytes == sizeof(GLushort)); if (ctx->Pixel.DepthScale == 1.0f && @@ -1265,16 +1265,16 @@ _mesa_texstore_z16(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgb565(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgb565 || - dstFormat == &_mesa_texformat_rgb565_rev); + ASSERT(dstFormat == MESA_FORMAT_RGB565 || + dstFormat == MESA_FORMAT_RGB565_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgb565 && + dstFormat == MESA_FORMAT_RGB565 && baseInternalFormat == GL_RGB && srcFormat == GL_RGB && srcType == GL_UNSIGNED_SHORT_5_6_5) { @@ -1306,7 +1306,7 @@ _mesa_texstore_rgb565(TEXSTORE_PARAMS) const GLubyte *srcUB = (const GLubyte *) src; GLushort *dstUS = (GLushort *) dst; /* check for byteswapped format */ - if (dstFormat == &_mesa_texformat_rgb565) { + if (dstFormat == MESA_FORMAT_RGB565) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_565( srcUB[0], srcUB[1], srcUB[2] ); srcUB += 3; @@ -1343,7 +1343,7 @@ _mesa_texstore_rgb565(TEXSTORE_PARAMS) for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; /* check for byteswapped format */ - if (dstFormat == &_mesa_texformat_rgb565) { + if (dstFormat == MESA_FORMAT_RGB565) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_565( CHAN_TO_UBYTE(src[RCOMP]), CHAN_TO_UBYTE(src[GCOMP]), @@ -1375,16 +1375,16 @@ static GLboolean _mesa_texstore_rgba8888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba8888 || - dstFormat == &_mesa_texformat_rgba8888_rev); + ASSERT(dstFormat == MESA_FORMAT_RGBA8888 || + dstFormat == MESA_FORMAT_RGBA8888_REV); ASSERT(texelBytes == 4); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba8888 && + dstFormat == MESA_FORMAT_RGBA8888 && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) || @@ -1400,7 +1400,7 @@ _mesa_texstore_rgba8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba8888_rev && + dstFormat == MESA_FORMAT_RGBA8888_REV && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) || (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) || @@ -1425,8 +1425,8 @@ _mesa_texstore_rgba8888(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_rgba8888) || - (!littleEndian && dstFormat == &_mesa_texformat_rgba8888_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_RGBA8888) || + (!littleEndian && dstFormat == MESA_FORMAT_RGBA8888_REV)) { dstmap[3] = 0; dstmap[2] = 1; dstmap[1] = 2; @@ -1469,7 +1469,7 @@ _mesa_texstore_rgba8888(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; - if (dstFormat == &_mesa_texformat_rgba8888) { + if (dstFormat == MESA_FORMAT_RGBA8888) { for (col = 0; col < srcWidth; col++) { dstUI[col] = PACK_COLOR_8888( CHAN_TO_UBYTE(src[RCOMP]), CHAN_TO_UBYTE(src[GCOMP]), @@ -1500,16 +1500,16 @@ static GLboolean _mesa_texstore_argb8888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_argb8888 || - dstFormat == &_mesa_texformat_argb8888_rev); + ASSERT(dstFormat == MESA_FORMAT_ARGB8888 || + dstFormat == MESA_FORMAT_ARGB8888_REV); ASSERT(texelBytes == 4); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888 && + dstFormat == MESA_FORMAT_ARGB8888 && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) || @@ -1524,7 +1524,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888_rev && + dstFormat == MESA_FORMAT_ARGB8888_REV && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) || @@ -1539,7 +1539,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888 && + dstFormat == MESA_FORMAT_ARGB8888 && srcFormat == GL_RGB && (baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB) && @@ -1569,7 +1569,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb8888 && + dstFormat == MESA_FORMAT_ARGB8888 && srcFormat == GL_RGBA && baseInternalFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE) { @@ -1614,16 +1614,16 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_argb8888) || - (!littleEndian && dstFormat == &_mesa_texformat_argb8888_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_ARGB8888) || + (!littleEndian && dstFormat == MESA_FORMAT_ARGB8888_REV)) { dstmap[3] = 3; /* alpha */ dstmap[2] = 0; /* red */ dstmap[1] = 1; /* green */ dstmap[0] = 2; /* blue */ } else { - assert((littleEndian && dstFormat == &_mesa_texformat_argb8888_rev) || - (!littleEndian && dstFormat == &_mesa_texformat_argb8888)); + assert((littleEndian && dstFormat == MESA_FORMAT_ARGB8888_REV) || + (!littleEndian && dstFormat == MESA_FORMAT_ARGB8888)); dstmap[3] = 2; dstmap[2] = 1; dstmap[1] = 0; @@ -1662,7 +1662,7 @@ _mesa_texstore_argb8888(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; - if (dstFormat == &_mesa_texformat_argb8888) { + if (dstFormat == MESA_FORMAT_ARGB8888) { for (col = 0; col < srcWidth; col++) { dstUI[col] = PACK_COLOR_8888( CHAN_TO_UBYTE(src[ACOMP]), CHAN_TO_UBYTE(src[RCOMP]), @@ -1693,10 +1693,10 @@ static GLboolean _mesa_texstore_rgb888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgb888); + ASSERT(dstFormat == MESA_FORMAT_RGB888); ASSERT(texelBytes == 3); if (!ctx->_ImageTransferState && @@ -1820,10 +1820,10 @@ static GLboolean _mesa_texstore_bgr888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_bgr888); + ASSERT(dstFormat == MESA_FORMAT_BGR888); ASSERT(texelBytes == 3); if (!ctx->_ImageTransferState && @@ -1926,15 +1926,15 @@ _mesa_texstore_bgr888(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba4444(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba4444); + ASSERT(dstFormat == MESA_FORMAT_RGBA4444); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba4444 && + dstFormat == MESA_FORMAT_RGBA4444 && baseInternalFormat == GL_RGBA && srcFormat == GL_RGBA && srcType == GL_UNSIGNED_SHORT_4_4_4_4){ @@ -1984,16 +1984,16 @@ _mesa_texstore_rgba4444(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_argb4444(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_argb4444 || - dstFormat == &_mesa_texformat_argb4444_rev); + ASSERT(dstFormat == MESA_FORMAT_ARGB4444 || + dstFormat == MESA_FORMAT_ARGB4444_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb4444 && + dstFormat == MESA_FORMAT_ARGB4444 && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && srcType == GL_UNSIGNED_SHORT_4_4_4_4_REV) { @@ -2025,7 +2025,7 @@ _mesa_texstore_argb4444(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; - if (dstFormat == &_mesa_texformat_argb4444) { + if (dstFormat == MESA_FORMAT_ARGB4444) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_4444( CHAN_TO_UBYTE(src[ACOMP]), CHAN_TO_UBYTE(src[RCOMP]), @@ -2054,15 +2054,15 @@ _mesa_texstore_argb4444(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba5551(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba5551); + ASSERT(dstFormat == MESA_FORMAT_RGBA5551); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_rgba5551 && + dstFormat == MESA_FORMAT_RGBA5551 && baseInternalFormat == GL_RGBA && srcFormat == GL_RGBA && srcType == GL_UNSIGNED_SHORT_5_5_5_1) { @@ -2112,16 +2112,16 @@ _mesa_texstore_rgba5551(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_argb1555(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_argb1555 || - dstFormat == &_mesa_texformat_argb1555_rev); + ASSERT(dstFormat == MESA_FORMAT_ARGB1555 || + dstFormat == MESA_FORMAT_ARGB1555_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_argb1555 && + dstFormat == MESA_FORMAT_ARGB1555 && baseInternalFormat == GL_RGBA && srcFormat == GL_BGRA && srcType == GL_UNSIGNED_SHORT_1_5_5_5_REV) { @@ -2153,7 +2153,7 @@ _mesa_texstore_argb1555(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; - if (dstFormat == &_mesa_texformat_argb1555) { + if (dstFormat == MESA_FORMAT_ARGB1555) { for (col = 0; col < srcWidth; col++) { dstUS[col] = PACK_COLOR_1555( CHAN_TO_UBYTE(src[ACOMP]), CHAN_TO_UBYTE(src[RCOMP]), @@ -2184,16 +2184,16 @@ static GLboolean _mesa_texstore_al88(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_al88 || - dstFormat == &_mesa_texformat_al88_rev); + ASSERT(dstFormat == MESA_FORMAT_AL88 || + dstFormat == MESA_FORMAT_AL88_REV); ASSERT(texelBytes == 2); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_al88 && + dstFormat == MESA_FORMAT_AL88 && baseInternalFormat == GL_LUMINANCE_ALPHA && srcFormat == GL_LUMINANCE_ALPHA && srcType == GL_UNSIGNED_BYTE && @@ -2216,8 +2216,8 @@ _mesa_texstore_al88(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_al88) || - (!littleEndian && dstFormat == &_mesa_texformat_al88_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_AL88) || + (!littleEndian && dstFormat == MESA_FORMAT_AL88_REV)) { dstmap[0] = 0; dstmap[1] = 3; } @@ -2258,7 +2258,7 @@ _mesa_texstore_al88(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLushort *dstUS = (GLushort *) dstRow; - if (dstFormat == &_mesa_texformat_al88) { + if (dstFormat == MESA_FORMAT_AL88) { for (col = 0; col < srcWidth; col++) { /* src[0] is luminance, src[1] is alpha */ dstUS[col] = PACK_COLOR_88( CHAN_TO_UBYTE(src[1]), @@ -2286,10 +2286,10 @@ _mesa_texstore_al88(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgb332(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_rgb332); + ASSERT(dstFormat == MESA_FORMAT_RGB332); ASSERT(texelBytes == 1); if (!ctx->_ImageTransferState && @@ -2344,12 +2344,12 @@ _mesa_texstore_rgb332(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_a8(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_a8 || - dstFormat == &_mesa_texformat_l8 || - dstFormat == &_mesa_texformat_i8); + ASSERT(dstFormat == MESA_FORMAT_A8 || + dstFormat == MESA_FORMAT_L8 || + dstFormat == MESA_FORMAT_I8); ASSERT(texelBytes == 1); if (!ctx->_ImageTransferState && @@ -2373,7 +2373,7 @@ _mesa_texstore_a8(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if (dstFormat == &_mesa_texformat_a8) { + if (dstFormat == MESA_FORMAT_A8) { dstmap[0] = 3; } else { @@ -2429,10 +2429,10 @@ _mesa_texstore_a8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_ci8(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) dims; (void) baseInternalFormat; - ASSERT(dstFormat == &_mesa_texformat_ci8); + ASSERT(dstFormat == MESA_FORMAT_CI8); ASSERT(texelBytes == 1); ASSERT(baseInternalFormat == GL_COLOR_INDEX); @@ -2471,18 +2471,18 @@ _mesa_texstore_ci8(TEXSTORE_PARAMS) /** - * Texstore for _mesa_texformat_ycbcr or _mesa_texformat_ycbcr_rev. + * Texstore for _mesa_texformat_ycbcr or _mesa_texformat_ycbcr_REV. */ static GLboolean _mesa_texstore_ycbcr(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); (void) ctx; (void) dims; (void) baseInternalFormat; - ASSERT((dstFormat == &_mesa_texformat_ycbcr) || - (dstFormat == &_mesa_texformat_ycbcr_rev)); + ASSERT((dstFormat == MESA_FORMAT_YCBCR) || + (dstFormat == MESA_FORMAT_YCBCR_REV)); ASSERT(texelBytes == 2); ASSERT(ctx->Extensions.MESA_ycbcr_texture); ASSERT(srcFormat == GL_YCBCR_MESA); @@ -2502,7 +2502,7 @@ _mesa_texstore_ycbcr(TEXSTORE_PARAMS) /* XXX the logic here _might_ be wrong */ if (srcPacking->SwapBytes ^ (srcType == GL_UNSIGNED_SHORT_8_8_REV_MESA) ^ - (dstFormat == &_mesa_texformat_ycbcr_rev) ^ + (dstFormat == MESA_FORMAT_YCBCR_REV) ^ !littleEndian) { GLint img, row; for (img = 0; img < srcDepth; img++) { @@ -2523,9 +2523,9 @@ static GLboolean _mesa_texstore_dudv8(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_dudv8); + ASSERT(dstFormat == MESA_FORMAT_DUDV8); ASSERT(texelBytes == 2); ASSERT(ctx->Extensions.ATI_envmap_bumpmap); ASSERT((srcFormat == GL_DU8DV8_ATI) || @@ -2617,16 +2617,16 @@ static GLboolean _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) { const GLboolean littleEndian = _mesa_little_endian(); - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); - ASSERT(dstFormat == &_mesa_texformat_signed_rgba8888 || - dstFormat == &_mesa_texformat_signed_rgba8888_rev); + ASSERT(dstFormat == MESA_FORMAT_SIGNED_RGBA8888 || + dstFormat == MESA_FORMAT_SIGNED_RGBA8888_REV); ASSERT(texelBytes == 4); if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_signed_rgba8888 && + dstFormat == MESA_FORMAT_SIGNED_RGBA8888 && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_BYTE && !littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_BYTE && littleEndian))) { @@ -2640,7 +2640,7 @@ _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) } else if (!ctx->_ImageTransferState && !srcPacking->SwapBytes && - dstFormat == &_mesa_texformat_signed_rgba8888_rev && + dstFormat == MESA_FORMAT_SIGNED_RGBA8888_REV && baseInternalFormat == GL_RGBA && ((srcFormat == GL_RGBA && srcType == GL_BYTE && littleEndian) || (srcFormat == GL_ABGR_EXT && srcType == GL_BYTE && !littleEndian))) { @@ -2661,8 +2661,8 @@ _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) /* dstmap - how to swizzle from RGBA to dst format: */ - if ((littleEndian && dstFormat == &_mesa_texformat_signed_rgba8888) || - (!littleEndian && dstFormat == &_mesa_texformat_signed_rgba8888_rev)) { + if ((littleEndian && dstFormat == MESA_FORMAT_SIGNED_RGBA8888) || + (!littleEndian && dstFormat == MESA_FORMAT_SIGNED_RGBA8888_REV)) { dstmap[3] = 0; dstmap[2] = 1; dstmap[1] = 2; @@ -2705,7 +2705,7 @@ _mesa_texstore_signed_rgba8888(TEXSTORE_PARAMS) + dstXoffset * texelBytes; for (row = 0; row < srcHeight; row++) { GLuint *dstUI = (GLuint *) dstRow; - if (dstFormat == &_mesa_texformat_signed_rgba8888) { + if (dstFormat == MESA_FORMAT_SIGNED_RGBA8888) { for (col = 0; col < srcWidth; col++) { dstUI[col] = PACK_COLOR_8888( FLOAT_TO_BYTE_TEX(srcRow[RCOMP]), FLOAT_TO_BYTE_TEX(srcRow[GCOMP]), @@ -2743,7 +2743,7 @@ _mesa_texstore_z24_s8(TEXSTORE_PARAMS) / sizeof(GLuint); GLint img, row; - ASSERT(dstFormat == &_mesa_texformat_z24_s8); + ASSERT(dstFormat == MESA_FORMAT_Z24_S8); ASSERT(srcFormat == GL_DEPTH_STENCIL_EXT || srcFormat == GL_DEPTH_COMPONENT); ASSERT(srcFormat != GL_DEPTH_STENCIL_EXT || srcType == GL_UNSIGNED_INT_24_8_EXT); @@ -2844,7 +2844,7 @@ _mesa_texstore_s8_z24(TEXSTORE_PARAMS) / sizeof(GLuint); GLint img, row; - ASSERT(dstFormat == &_mesa_texformat_s8_z24); + ASSERT(dstFormat == MESA_FORMAT_S8_Z24); ASSERT(srcFormat == GL_DEPTH_STENCIL_EXT || srcFormat == GL_DEPTH_COMPONENT); ASSERT(srcFormat != GL_DEPTH_STENCIL_EXT || srcType == GL_UNSIGNED_INT_24_8_EXT); @@ -2927,16 +2927,16 @@ _mesa_texstore_s8_z24(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba_float32(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); const GLint components = _mesa_components_in_format(baseFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba_float32 || - dstFormat == &_mesa_texformat_rgb_float32 || - dstFormat == &_mesa_texformat_alpha_float32 || - dstFormat == &_mesa_texformat_luminance_float32 || - dstFormat == &_mesa_texformat_luminance_alpha_float32 || - dstFormat == &_mesa_texformat_intensity_float32); + ASSERT(dstFormat == MESA_FORMAT_RGBA_FLOAT32 || + dstFormat == MESA_FORMAT_RGB_FLOAT32 || + dstFormat == MESA_FORMAT_ALPHA_FLOAT32 || + dstFormat == MESA_FORMAT_LUMINANCE_FLOAT32 || + dstFormat == MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32 || + dstFormat == MESA_FORMAT_INTENSITY_FLOAT32); ASSERT(baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB || baseInternalFormat == GL_ALPHA || @@ -2996,16 +2996,16 @@ _mesa_texstore_rgba_float32(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_rgba_float16(TEXSTORE_PARAMS) { - const GLuint texelBytes = _mesa_get_format_bytes(dstFormat->MesaFormat); - const GLenum baseFormat = _mesa_get_format_base_format(dstFormat->MesaFormat); + const GLuint texelBytes = _mesa_get_format_bytes(dstFormat); + const GLenum baseFormat = _mesa_get_format_base_format(dstFormat); const GLint components = _mesa_components_in_format(baseFormat); - ASSERT(dstFormat == &_mesa_texformat_rgba_float16 || - dstFormat == &_mesa_texformat_rgb_float16 || - dstFormat == &_mesa_texformat_alpha_float16 || - dstFormat == &_mesa_texformat_luminance_float16 || - dstFormat == &_mesa_texformat_luminance_alpha_float16 || - dstFormat == &_mesa_texformat_intensity_float16); + ASSERT(dstFormat == MESA_FORMAT_RGBA_FLOAT16 || + dstFormat == MESA_FORMAT_RGB_FLOAT16 || + dstFormat == MESA_FORMAT_ALPHA_FLOAT16 || + dstFormat == MESA_FORMAT_LUMINANCE_FLOAT16 || + dstFormat == MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16 || + dstFormat == MESA_FORMAT_INTENSITY_FLOAT16); ASSERT(baseInternalFormat == GL_RGBA || baseInternalFormat == GL_RGB || baseInternalFormat == GL_ALPHA || @@ -3065,13 +3065,13 @@ _mesa_texstore_rgba_float16(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_srgb8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_srgb8); + ASSERT(dstFormat == MESA_FORMAT_SRGB8); /* reuse normal rgb texstore code */ - newDstFormat = &_mesa_texformat_rgb888; + newDstFormat = MESA_FORMAT_RGB888; k = _mesa_texstore_rgb888(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, @@ -3087,13 +3087,13 @@ _mesa_texstore_srgb8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_srgba8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_srgba8); + ASSERT(dstFormat == MESA_FORMAT_SRGBA8); /* reuse normal rgba texstore code */ - newDstFormat = &_mesa_texformat_rgba8888; + newDstFormat = MESA_FORMAT_RGBA8888; k = _mesa_texstore_rgba8888(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, dstXoffset, dstYoffset, dstZoffset, @@ -3108,13 +3108,13 @@ _mesa_texstore_srgba8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_sargb8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_sargb8); + ASSERT(dstFormat == MESA_FORMAT_SARGB8); /* reuse normal rgba texstore code */ - newDstFormat = &_mesa_texformat_argb8888; + newDstFormat = MESA_FORMAT_ARGB8888; k = _mesa_texstore_argb8888(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, @@ -3130,12 +3130,12 @@ _mesa_texstore_sargb8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_sl8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_sl8); + ASSERT(dstFormat == MESA_FORMAT_SL8); - newDstFormat = &_mesa_texformat_l8; + newDstFormat = MESA_FORMAT_L8; /* _mesa_textore_a8 handles luminance8 too */ k = _mesa_texstore_a8(ctx, dims, baseInternalFormat, @@ -3152,13 +3152,13 @@ _mesa_texstore_sl8(TEXSTORE_PARAMS) static GLboolean _mesa_texstore_sla8(TEXSTORE_PARAMS) { - const struct gl_texture_format *newDstFormat; + gl_format newDstFormat; GLboolean k; - ASSERT(dstFormat == &_mesa_texformat_sla8); + ASSERT(dstFormat == MESA_FORMAT_SLA8); /* reuse normal luminance/alpha texstore code */ - newDstFormat = &_mesa_texformat_al88; + newDstFormat = MESA_FORMAT_AL88; k = _mesa_texstore_al88(ctx, dims, baseInternalFormat, newDstFormat, dstAddr, @@ -3280,7 +3280,7 @@ _mesa_texstore(TEXSTORE_PARAMS) StoreTexImageFunc storeImage; GLboolean success; - storeImage = _mesa_get_texstore_func(dstFormat->MesaFormat); + storeImage = _mesa_get_texstore_func(dstFormat); assert(storeImage); @@ -3390,7 +3390,7 @@ fetch_texel_float_to_chan(const struct gl_texture_image *texImage, GLint i, GLint j, GLint k, GLchan *texelOut) { GLfloat temp[4]; - GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat); ASSERT(texImage->FetchTexelf); texImage->FetchTexelf(texImage, i, j, k, temp); @@ -3417,7 +3417,7 @@ fetch_texel_chan_to_float(const struct gl_texture_image *texImage, GLint i, GLint j, GLint k, GLfloat *texelOut) { GLchan temp[4]; - GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat->MesaFormat); + GLenum baseFormat = _mesa_get_format_base_format(texImage->TexFormat); ASSERT(texImage->FetchTexelc); texImage->FetchTexelc(texImage, i, j, k, temp); @@ -3446,7 +3446,7 @@ _mesa_set_fetch_functions(struct gl_texture_image *texImage, GLuint dims) ASSERT(texImage->TexFormat); texImage->FetchTexelf = - _mesa_get_texel_fetch_func(texImage->TexFormat->MesaFormat, dims); + _mesa_get_texel_fetch_func(texImage->TexFormat, dims); /* now check if we need to use a float/chan adaptor */ if (!texImage->FetchTexelc) { @@ -3466,13 +3466,13 @@ static void compute_texture_size(GLcontext *ctx, struct gl_texture_image *texImage) { texImage->IsCompressed = - _mesa_is_format_compressed(texImage->TexFormat->MesaFormat); + _mesa_is_format_compressed(texImage->TexFormat); if (texImage->IsCompressed) { texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { /* non-compressed format */ @@ -3513,7 +3513,7 @@ _mesa_store_teximage1d(GLcontext *ctx, GLenum target, GLint level, if (texImage->IsCompressed) sizeInBytes = texImage->CompressedSize; else - sizeInBytes = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + sizeInBytes = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat); texImage->Data = _mesa_alloc_texmemory(sizeInBytes); if (!texImage->Data) { _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage1D"); @@ -3578,7 +3578,7 @@ _mesa_store_teximage2d(GLcontext *ctx, GLenum target, GLint level, _mesa_set_fetch_functions(texImage, 2); compute_texture_size(ctx, texImage); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* allocate memory */ if (texImage->IsCompressed) @@ -3605,7 +3605,7 @@ _mesa_store_teximage2d(GLcontext *ctx, GLenum target, GLint level, if (texImage->IsCompressed) { dstRowStride - = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + = _mesa_compressed_row_stride(texImage->TexFormat, width); } else { dstRowStride = texImage->RowStride * texelBytes; @@ -3654,7 +3654,7 @@ _mesa_store_teximage3d(GLcontext *ctx, GLenum target, GLint level, _mesa_set_fetch_functions(texImage, 3); compute_texture_size(ctx, texImage); - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* allocate memory */ if (texImage->IsCompressed) @@ -3681,7 +3681,7 @@ _mesa_store_teximage3d(GLcontext *ctx, GLenum target, GLint level, if (texImage->IsCompressed) { dstRowStride - = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + = _mesa_compressed_row_stride(texImage->TexFormat, width); } else { dstRowStride = texImage->RowStride * texelBytes; @@ -3770,12 +3770,12 @@ _mesa_store_texsubimage2d(GLcontext *ctx, GLenum target, GLint level, GLboolean success; if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, texImage->Width); } else { dstRowStride = texImage->RowStride * - _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + _mesa_get_format_bytes(texImage->TexFormat); } success = _mesa_texstore(ctx, 2, texImage->_BaseFormat, @@ -3820,12 +3820,12 @@ _mesa_store_texsubimage3d(GLcontext *ctx, GLenum target, GLint level, GLboolean success; if (texImage->IsCompressed) { - dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, + dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat, texImage->Width); } else { dstRowStride = texImage->RowStride * - _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + _mesa_get_format_bytes(texImage->TexFormat); } success = _mesa_texstore(ctx, 3, texImage->_BaseFormat, @@ -3985,7 +3985,7 @@ _mesa_store_compressed_texsubimage2d(GLcontext *ctx, GLenum target, GLint i, rows; GLubyte *dest; const GLubyte *src; - const gl_format texFormat = texImage->TexFormat->MesaFormat; + const gl_format texFormat = texImage->TexFormat; (void) format; diff --git a/src/mesa/main/texstore.h b/src/mesa/main/texstore.h index 4a217df103..2db076dfff 100644 --- a/src/mesa/main/texstore.h +++ b/src/mesa/main/texstore.h @@ -58,7 +58,7 @@ #define TEXSTORE_PARAMS \ GLcontext *ctx, GLuint dims, \ GLenum baseInternalFormat, \ - const struct gl_texture_format *dstFormat, \ + gl_format dstFormat, \ GLvoid *dstAddr, \ GLint dstXoffset, GLint dstYoffset, GLint dstZoffset, \ GLint dstRowStride, const GLuint *dstImageOffsets, \ diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c b/src/mesa/state_tracker/st_cb_drawpixels.c index 6da57e817b..081c09c1fb 100644 --- a/src/mesa/state_tracker/st_cb_drawpixels.c +++ b/src/mesa/state_tracker/st_cb_drawpixels.c @@ -338,7 +338,7 @@ make_texture(struct st_context *st, GLcontext *ctx = st->ctx; struct pipe_context *pipe = st->pipe; struct pipe_screen *screen = pipe->screen; - const struct gl_texture_format *mformat; + gl_format mformat; struct pipe_texture *pt; enum pipe_format pipeFormat; GLuint cpp; @@ -350,7 +350,7 @@ make_texture(struct st_context *st, mformat = st_ChooseTextureFormat(ctx, baseFormat, format, type); assert(mformat); - pipeFormat = st_mesa_format_to_pipe_format(mformat->MesaFormat); + pipeFormat = st_mesa_format_to_pipe_format(mformat); assert(pipeFormat); cpp = st_sizeof_format(pipeFormat); diff --git a/src/mesa/state_tracker/st_cb_texture.c b/src/mesa/state_tracker/st_cb_texture.c index d96484c439..716fbc8b29 100644 --- a/src/mesa/state_tracker/st_cb_texture.c +++ b/src/mesa/state_tracker/st_cb_texture.c @@ -95,9 +95,9 @@ gl_target_to_pipe(GLenum target) * format. */ static GLuint -compressed_num_bytes(GLuint mesaFormat) +compressed_num_bytes(gl_format format) { - switch(mesaFormat) { + switch (format) { #if FEATURE_texture_fxt1 case MESA_FORMAT_RGB_FXT1: case MESA_FORMAT_RGBA_FXT1: @@ -117,9 +117,9 @@ compressed_num_bytes(GLuint mesaFormat) static GLboolean -is_compressed_mesa_format(const struct gl_texture_format *format) +is_compressed_mesa_format(gl_format format) { - switch (format->MesaFormat) { + switch (format) { case MESA_FORMAT_RGB_DXT1: case MESA_FORMAT_RGBA_DXT1: case MESA_FORMAT_RGBA_DXT3: @@ -338,7 +338,7 @@ guess_and_alloc_texture(struct st_context *st, lastLevel = firstLevel + MAX2(MAX2(l2width, l2height), l2depth); } - fmt = st_mesa_format_to_pipe_format(stImage->base.TexFormat->MesaFormat); + fmt = st_mesa_format_to_pipe_format(stImage->base.TexFormat); usage = default_usage(fmt); @@ -411,7 +411,7 @@ compress_with_blit(GLcontext * ctx, const GLuint dstImageOffsets[1] = {0}; struct st_texture_image *stImage = st_texture_image(texImage); struct pipe_screen *screen = ctx->st->pipe->screen; - const struct gl_texture_format *mesa_format; + gl_format mesa_format; struct pipe_texture templ; struct pipe_texture *src_tex; struct pipe_surface *dst_surface; @@ -443,7 +443,7 @@ compress_with_blit(GLcontext * ctx, */ memset(&templ, 0, sizeof(templ)); templ.target = PIPE_TEXTURE_2D; - templ.format = st_mesa_format_to_pipe_format(mesa_format->MesaFormat); + templ.format = st_mesa_format_to_pipe_format(mesa_format); pf_get_block(templ.format, &templ.block); templ.width[0] = width; templ.height[0] = height; @@ -559,17 +559,17 @@ st_TexImage(GLcontext * ctx, _mesa_set_fetch_functions(texImage, dims); - if (_mesa_is_format_compressed(texImage->TexFormat->MesaFormat)) { + if (_mesa_is_format_compressed(texImage->TexFormat)) { /* must be a compressed format */ texelBytes = 0; texImage->IsCompressed = GL_TRUE; texImage->CompressedSize = ctx->Driver.CompressedTextureSize(ctx, texImage->Width, texImage->Height, texImage->Depth, - texImage->TexFormat->MesaFormat); + texImage->TexFormat); } else { - texelBytes = _mesa_get_format_bytes(texImage->TexFormat->MesaFormat); + texelBytes = _mesa_get_format_bytes(texImage->TexFormat); /* Minimum pitch of 32 bytes */ if (postConvWidth * texelBytes < 32) { @@ -699,7 +699,7 @@ st_TexImage(GLcontext * ctx, if (texImage->IsCompressed) { sizeInBytes = texImage->CompressedSize; dstRowStride = - _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width); + _mesa_compressed_row_stride(texImage->TexFormat, width); assert(dims != 3); } else { @@ -1824,10 +1824,10 @@ st_finalize_texture(GLcontext *ctx, /* FIXME: determine format block instead of cpp */ if (firstImage->base.IsCompressed) { - cpp = compressed_num_bytes(firstImage->base.TexFormat->MesaFormat); + cpp = compressed_num_bytes(firstImage->base.TexFormat); } else { - cpp = _mesa_get_format_bytes(firstImage->base.TexFormat->MesaFormat); + cpp = _mesa_get_format_bytes(firstImage->base.TexFormat); } /* If we already have a gallium texture, check that it matches the texture @@ -1835,7 +1835,7 @@ st_finalize_texture(GLcontext *ctx, */ if (stObj->pt) { const enum pipe_format fmt = - st_mesa_format_to_pipe_format(firstImage->base.TexFormat->MesaFormat); + st_mesa_format_to_pipe_format(firstImage->base.TexFormat); if (stObj->pt->target != gl_target_to_pipe(stObj->base.Target) || stObj->pt->format != fmt || stObj->pt->last_level < stObj->lastLevel || @@ -1854,7 +1854,7 @@ st_finalize_texture(GLcontext *ctx, */ if (!stObj->pt) { const enum pipe_format fmt = - st_mesa_format_to_pipe_format(firstImage->base.TexFormat->MesaFormat); + st_mesa_format_to_pipe_format(firstImage->base.TexFormat); GLuint usage = default_usage(fmt); stObj->pt = st_texture_create(ctx->st, diff --git a/src/mesa/state_tracker/st_format.c b/src/mesa/state_tracker/st_format.c index dcb90a3107..6f76e2d8c0 100644 --- a/src/mesa/state_tracker/st_format.c +++ b/src/mesa/state_tracker/st_format.c @@ -629,74 +629,74 @@ st_choose_renderbuffer_format(struct pipe_context *pipe, GLenum internalFormat) } -static const struct gl_texture_format * +static gl_format translate_gallium_format_to_mesa_format(enum pipe_format format) { switch (format) { case PIPE_FORMAT_A8R8G8B8_UNORM: - return &_mesa_texformat_argb8888; + return MESA_FORMAT_ARGB8888; case PIPE_FORMAT_A1R5G5B5_UNORM: - return &_mesa_texformat_argb1555; + return MESA_FORMAT_ARGB1555; case PIPE_FORMAT_A4R4G4B4_UNORM: - return &_mesa_texformat_argb4444; + return MESA_FORMAT_ARGB4444; case PIPE_FORMAT_R5G6B5_UNORM: - return &_mesa_texformat_rgb565; + return MESA_FORMAT_RGB565; case PIPE_FORMAT_A8L8_UNORM: - return &_mesa_texformat_al88; + return MESA_FORMAT_AL88; case PIPE_FORMAT_A8_UNORM: - return &_mesa_texformat_a8; + return MESA_FORMAT_A8; case PIPE_FORMAT_L8_UNORM: - return &_mesa_texformat_l8; + return MESA_FORMAT_L8; case PIPE_FORMAT_I8_UNORM: - return &_mesa_texformat_i8; + return MESA_FORMAT_I8; case PIPE_FORMAT_Z16_UNORM: - return &_mesa_texformat_z16; + return MESA_FORMAT_Z16; case PIPE_FORMAT_Z32_UNORM: - return &_mesa_texformat_z32; + return MESA_FORMAT_Z32; case PIPE_FORMAT_Z24S8_UNORM: - return &_mesa_texformat_z24_s8; + return MESA_FORMAT_Z24_S8; case PIPE_FORMAT_S8Z24_UNORM: - return &_mesa_texformat_s8_z24; + return MESA_FORMAT_S8_Z24; case PIPE_FORMAT_YCBCR: - return &_mesa_texformat_ycbcr; + return MESA_FORMAT_YCBCR; case PIPE_FORMAT_YCBCR_REV: - return &_mesa_texformat_ycbcr_rev; + return MESA_FORMAT_YCBCR_REV; #if FEATURE_texture_s3tc case PIPE_FORMAT_DXT1_RGB: - return &_mesa_texformat_rgb_dxt1; + return MESA_FORMAT_RGB_DXT1; case PIPE_FORMAT_DXT1_RGBA: - return &_mesa_texformat_rgba_dxt1; + return MESA_FORMAT_RGBA_DXT1; case PIPE_FORMAT_DXT3_RGBA: - return &_mesa_texformat_rgba_dxt3; + return MESA_FORMAT_RGBA_DXT3; case PIPE_FORMAT_DXT5_RGBA: - return &_mesa_texformat_rgba_dxt5; + return MESA_FORMAT_RGBA_DXT5; #if FEATURE_EXT_texture_sRGB case PIPE_FORMAT_DXT1_SRGB: - return &_mesa_texformat_srgb_dxt1; + return MESA_FORMAT_SRGB_DXT1; case PIPE_FORMAT_DXT1_SRGBA: - return &_mesa_texformat_srgba_dxt1; + return MESA_FORMAT_SRGBA_DXT1; case PIPE_FORMAT_DXT3_SRGBA: - return &_mesa_texformat_srgba_dxt3; + return MESA_FORMAT_SRGBA_DXT3; case PIPE_FORMAT_DXT5_SRGBA: - return &_mesa_texformat_srgba_dxt5; + return MESA_FORMAT_SRGBA_DXT5; #endif #endif #if FEATURE_EXT_texture_sRGB case PIPE_FORMAT_A8L8_SRGB: - return &_mesa_texformat_sla8; + return MESA_FORMAT_SLA8; case PIPE_FORMAT_L8_SRGB: - return &_mesa_texformat_sl8; + return MESA_FORMAT_SL8; case PIPE_FORMAT_R8G8B8_SRGB: - return &_mesa_texformat_srgb8; + return MESA_FORMAT_SRGB8; case PIPE_FORMAT_R8G8B8A8_SRGB: - return &_mesa_texformat_srgba8; + return MESA_FORMAT_SRGBA8; case PIPE_FORMAT_A8R8G8B8_SRGB: - return &_mesa_texformat_sargb8; + return MESA_FORMAT_SARGB8; #endif /* XXX add additional cases */ default: assert(0); - return NULL; + return MESA_FORMAT_NONE; } } @@ -704,7 +704,7 @@ translate_gallium_format_to_mesa_format(enum pipe_format format) /** * Called via ctx->Driver.chooseTextureFormat(). */ -const struct gl_texture_format * +gl_format st_ChooseTextureFormat(GLcontext *ctx, GLint internalFormat, GLenum format, GLenum type) { @@ -716,7 +716,7 @@ st_ChooseTextureFormat(GLcontext *ctx, GLint internalFormat, pFormat = st_choose_format(ctx->st->pipe, internalFormat, PIPE_TEXTURE_2D, PIPE_TEXTURE_USAGE_SAMPLER); if (pFormat == PIPE_FORMAT_NONE) - return NULL; + return MESA_FORMAT_NONE; return translate_gallium_format_to_mesa_format(pFormat); } diff --git a/src/mesa/state_tracker/st_format.h b/src/mesa/state_tracker/st_format.h index 9d9e02fe9b..1a8c6ea98f 100644 --- a/src/mesa/state_tracker/st_format.h +++ b/src/mesa/state_tracker/st_format.h @@ -29,6 +29,7 @@ #ifndef ST_FORMAT_H #define ST_FORMAT_H +#include "main/formats.h" struct pipe_format_info { @@ -71,7 +72,7 @@ extern enum pipe_format st_choose_renderbuffer_format(struct pipe_context *pipe, GLenum internalFormat); -extern const struct gl_texture_format * +extern gl_format st_ChooseTextureFormat(GLcontext * ctx, GLint internalFormat, GLenum format, GLenum type); diff --git a/src/mesa/state_tracker/st_gen_mipmap.c b/src/mesa/state_tracker/st_gen_mipmap.c index 63a6956a7a..58f6933652 100644 --- a/src/mesa/state_tracker/st_gen_mipmap.c +++ b/src/mesa/state_tracker/st_gen_mipmap.c @@ -115,7 +115,7 @@ fallback_generate_mipmap(GLcontext *ctx, GLenum target, assert(target != GL_TEXTURE_3D); /* not done yet */ - _mesa_format_to_type_and_comps(texObj->Image[face][baseLevel]->TexFormat->MesaFormat, + _mesa_format_to_type_and_comps(texObj->Image[face][baseLevel]->TexFormat, &datatype, &comps); for (dstLevel = baseLevel + 1; dstLevel <= lastLevel; dstLevel++) { diff --git a/src/mesa/state_tracker/st_texture.c b/src/mesa/state_tracker/st_texture.c index bbc2830e69..1790e1b28d 100644 --- a/src/mesa/state_tracker/st_texture.c +++ b/src/mesa/state_tracker/st_texture.c @@ -128,7 +128,7 @@ st_texture_match_image(const struct pipe_texture *pt, /* Check if this image's format matches the established texture's format. */ - if (st_mesa_format_to_pipe_format(image->TexFormat->MesaFormat) != pt->format) + if (st_mesa_format_to_pipe_format(image->TexFormat) != pt->format) return GL_FALSE; /* Test if this image's size matches what's expected in the diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c index 004d4e05ae..11c8f9256a 100644 --- a/src/mesa/swrast/s_texfilter.c +++ b/src/mesa/swrast/s_texfilter.c @@ -745,7 +745,7 @@ get_border_color(const struct gl_texture_object *tObj, const struct gl_texture_image *img, GLfloat rgba[4]) { - switch (img->TexFormat->BaseFormat) { + switch (img->_BaseFormat) { case GL_RGB: rgba[0] = tObj->BorderColor[0]; rgba[1] = tObj->BorderColor[1]; @@ -1152,7 +1152,7 @@ sample_2d_linear_repeat(GLcontext *ctx, ASSERT(tObj->WrapS == GL_REPEAT); ASSERT(tObj->WrapT == GL_REPEAT); ASSERT(img->Border == 0); - ASSERT(img->TexFormat->BaseFormat != GL_COLOR_INDEX); + ASSERT(img->_BaseFormat != GL_COLOR_INDEX); ASSERT(img->_IsPowerOfTwo); linear_repeat_texel_location(width, texcoord[0], &i0, &i1, &wi); @@ -1343,7 +1343,7 @@ opt_sample_rgb_2d(GLcontext *ctx, ASSERT(tObj->WrapS==GL_REPEAT); ASSERT(tObj->WrapT==GL_REPEAT); ASSERT(img->Border==0); - ASSERT(img->TexFormat->MesaFormat==MESA_FORMAT_RGB); + ASSERT(img->TexFormat == MESA_FORMAT_RGB); ASSERT(img->_IsPowerOfTwo); for (k=0; kWrapS==GL_REPEAT); ASSERT(tObj->WrapT==GL_REPEAT); ASSERT(img->Border==0); - ASSERT(img->TexFormat->MesaFormat==MESA_FORMAT_RGBA); + ASSERT(img->TexFormat == MESA_FORMAT_RGBA); ASSERT(img->_IsPowerOfTwo); for (i = 0; i < n; i++) { @@ -1414,7 +1414,7 @@ sample_lambda_2d(GLcontext *ctx, const GLboolean repeatNoBorderPOT = (tObj->WrapS == GL_REPEAT) && (tObj->WrapT == GL_REPEAT) && (tImg->Border == 0 && (tImg->Width == tImg->RowStride)) - && (tImg->TexFormat->BaseFormat != GL_COLOR_INDEX) + && (tImg->_BaseFormat != GL_COLOR_INDEX) && tImg->_IsPowerOfTwo; ASSERT(lambda != NULL); @@ -1427,7 +1427,7 @@ sample_lambda_2d(GLcontext *ctx, switch (tObj->MinFilter) { case GL_NEAREST: if (repeatNoBorderPOT) { - switch (tImg->TexFormat->MesaFormat) { + switch (tImg->TexFormat) { case MESA_FORMAT_RGB: opt_sample_rgb_2d(ctx, tObj, m, texcoords + minStart, NULL, rgba + minStart); @@ -1484,7 +1484,7 @@ sample_lambda_2d(GLcontext *ctx, switch (tObj->MagFilter) { case GL_NEAREST: if (repeatNoBorderPOT) { - switch (tImg->TexFormat->MesaFormat) { + switch (tImg->TexFormat) { case MESA_FORMAT_RGB: opt_sample_rgb_2d(ctx, tObj, m, texcoords + magStart, NULL, rgba + magStart); @@ -2152,7 +2152,7 @@ sample_nearest_rect(GLcontext *ctx, ASSERT(tObj->WrapT == GL_CLAMP || tObj->WrapT == GL_CLAMP_TO_EDGE || tObj->WrapT == GL_CLAMP_TO_BORDER); - ASSERT(img->TexFormat->BaseFormat != GL_COLOR_INDEX); + ASSERT(img->_BaseFormat != GL_COLOR_INDEX); for (i = 0; i < n; i++) { GLint row, col; @@ -2186,7 +2186,7 @@ sample_linear_rect(GLcontext *ctx, ASSERT(tObj->WrapT == GL_CLAMP || tObj->WrapT == GL_CLAMP_TO_EDGE || tObj->WrapT == GL_CLAMP_TO_BORDER); - ASSERT(img->TexFormat->BaseFormat != GL_COLOR_INDEX); + ASSERT(img->_BaseFormat != GL_COLOR_INDEX); for (i = 0; i < n; i++) { GLint i0, j0, i1, j1; @@ -2973,8 +2973,8 @@ sample_depth_texture( GLcontext *ctx, (void) lambda; - ASSERT(img->TexFormat->BaseFormat == GL_DEPTH_COMPONENT || - img->TexFormat->BaseFormat == GL_DEPTH_STENCIL_EXT); + ASSERT(img->_BaseFormat == GL_DEPTH_COMPONENT || + img->_BaseFormat == GL_DEPTH_STENCIL_EXT); ASSERT(tObj->Target == GL_TEXTURE_1D || tObj->Target == GL_TEXTURE_2D || @@ -3154,7 +3154,7 @@ _swrast_choose_texture_sample_func( GLcontext *ctx, } else { const GLboolean needLambda = (GLboolean) (t->MinFilter != t->MagFilter); - const GLenum format = t->Image[0][t->BaseLevel]->TexFormat->BaseFormat; + const GLenum format = t->Image[0][t->BaseLevel]->_BaseFormat; switch (t->Target) { case GL_TEXTURE_1D: @@ -3189,14 +3189,14 @@ _swrast_choose_texture_sample_func( GLcontext *ctx, t->WrapT == GL_REPEAT && img->_IsPowerOfTwo && img->Border == 0 && - img->TexFormat->MesaFormat == MESA_FORMAT_RGB) { + img->TexFormat == MESA_FORMAT_RGB) { return &opt_sample_rgb_2d; } else if (t->WrapS == GL_REPEAT && t->WrapT == GL_REPEAT && img->_IsPowerOfTwo && img->Border == 0 && - img->TexFormat->MesaFormat == MESA_FORMAT_RGBA) { + img->TexFormat == MESA_FORMAT_RGBA) { return &opt_sample_rgba_2d; } else { diff --git a/src/mesa/swrast/s_triangle.c b/src/mesa/swrast/s_triangle.c index 1ab0e19f92..7b59763f11 100644 --- a/src/mesa/swrast/s_triangle.c +++ b/src/mesa/swrast/s_triangle.c @@ -1055,11 +1055,11 @@ _swrast_choose_triangle( GLcontext *ctx ) const struct gl_texture_object *texObj2D; const struct gl_texture_image *texImg; GLenum minFilter, magFilter, envMode; - GLint format; + gl_format format; texObj2D = ctx->Texture.Unit[0].CurrentTex[TEXTURE_2D_INDEX]; texImg = texObj2D ? texObj2D->Image[0][texObj2D->BaseLevel] : NULL; - format = texImg ? texImg->TexFormat->MesaFormat : -1; + format = texImg ? texImg->TexFormat : -1; minFilter = texObj2D ? texObj2D->MinFilter : (GLenum) 0; magFilter = texObj2D ? texObj2D->MagFilter : (GLenum) 0; envMode = ctx->Texture.Unit[0].EnvMode; -- cgit v1.2.3 From 3e34a2a2b97e7c93955deedb7c12b73bccd6662d Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 5 Oct 2009 18:11:35 -0600 Subject: drivers: don't include texformat.h And remove other unneeded #includes while we're at it. --- src/mesa/drivers/dri/gamma/gamma_tex.c | 13 +++++-------- src/mesa/drivers/dri/i810/i810tex.c | 1 - src/mesa/drivers/dri/i810/i810texmem.c | 1 - src/mesa/drivers/dri/i810/i810texstate.c | 1 - src/mesa/drivers/dri/i915/i830_texblend.c | 1 - src/mesa/drivers/dri/i915/i830_texstate.c | 1 - src/mesa/drivers/dri/i915/i830_vtbl.c | 1 - src/mesa/drivers/dri/i915/i915_texstate.c | 1 - src/mesa/drivers/dri/i915/i915_vtbl.c | 1 - src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 1 - src/mesa/drivers/dri/i965/brw_wm.c | 1 - src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 1 - src/mesa/drivers/dri/intel/intel_blit.c | 1 - src/mesa/drivers/dri/intel/intel_fbo.c | 1 - src/mesa/drivers/dri/intel/intel_span.c | 1 - src/mesa/drivers/dri/intel/intel_tex_format.c | 1 - src/mesa/drivers/dri/intel/intel_tex_image.c | 1 - src/mesa/drivers/dri/mach64/mach64_tex.c | 1 - src/mesa/drivers/dri/mach64/mach64_texmem.c | 11 +++++------ src/mesa/drivers/dri/mach64/mach64_texstate.c | 1 - src/mesa/drivers/dri/mga/mga_texstate.c | 15 ++++++--------- src/mesa/drivers/dri/mga/mgatex.c | 13 ++++++------- src/mesa/drivers/dri/r128/r128_tex.c | 1 - src/mesa/drivers/dri/r128/r128_texmem.c | 1 - src/mesa/drivers/dri/r128/r128_texstate.c | 1 - src/mesa/drivers/dri/r200/r200_tex.c | 1 - src/mesa/drivers/dri/r200/r200_texstate.c | 1 - src/mesa/drivers/dri/r300/r300_state.c | 1 - src/mesa/drivers/dri/r300/r300_tex.c | 1 - src/mesa/drivers/dri/r300/r300_texstate.c | 1 - src/mesa/drivers/dri/r600/r600_tex.c | 1 - src/mesa/drivers/dri/r600/r600_texstate.c | 1 - src/mesa/drivers/dri/r600/r700_state.c | 1 - src/mesa/drivers/dri/radeon/radeon_fbo.c | 1 - src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 1 - src/mesa/drivers/dri/radeon/radeon_tex.c | 1 - src/mesa/drivers/dri/radeon/radeon_texstate.c | 1 - src/mesa/drivers/dri/radeon/radeon_texture.c | 1 - src/mesa/drivers/dri/s3v/s3v_tex.c | 4 ---- src/mesa/drivers/dri/savage/savage_xmesa.c | 2 +- src/mesa/drivers/dri/savage/savagetex.c | 23 +++++++++-------------- src/mesa/drivers/dri/sis/sis_tex.c | 8 +++----- src/mesa/drivers/dri/sis/sis_texstate.c | 1 - src/mesa/drivers/dri/tdfx/tdfx_state.c | 1 - src/mesa/drivers/dri/tdfx/tdfx_tex.c | 1 - src/mesa/drivers/dri/unichrome/via_tex.c | 3 +-- 46 files changed, 36 insertions(+), 93 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/gamma/gamma_tex.c b/src/mesa/drivers/dri/gamma/gamma_tex.c index 97797d4788..0dad250e4d 100644 --- a/src/mesa/drivers/dri/gamma/gamma_tex.c +++ b/src/mesa/drivers/dri/gamma/gamma_tex.c @@ -1,21 +1,18 @@ -#include -#include - #include "main/glheader.h" #include "main/mtypes.h" +#include "main/colormac.h" #include "main/imports.h" #include "main/simple_list.h" #include "main/enums.h" +#include "main/mm.h" #include "main/texstore.h" -#include "teximage.h" -#include "main/texformat.h" -#include "texobj.h" +#include "main/teximage.h" +#include "main/texobj.h" + #include "swrast/swrast.h" -#include "main/mm.h" #include "gammacontext.h" -#include "colormac.h" /* diff --git a/src/mesa/drivers/dri/i810/i810tex.c b/src/mesa/drivers/dri/i810/i810tex.c index 8166393eb1..2f6978f5aa 100644 --- a/src/mesa/drivers/dri/i810/i810tex.c +++ b/src/mesa/drivers/dri/i810/i810tex.c @@ -28,7 +28,6 @@ #include "main/simple_list.h" #include "main/enums.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/colormac.h" diff --git a/src/mesa/drivers/dri/i810/i810texmem.c b/src/mesa/drivers/dri/i810/i810texmem.c index c2a5d95fc7..d93afbf9ef 100644 --- a/src/mesa/drivers/dri/i810/i810texmem.c +++ b/src/mesa/drivers/dri/i810/i810texmem.c @@ -30,7 +30,6 @@ #include "main/enums.h" #include "main/colormac.h" #include "main/mm.h" -#include "main/texformat.h" #include "i810screen.h" #include "i810_dri.h" diff --git a/src/mesa/drivers/dri/i810/i810texstate.c b/src/mesa/drivers/dri/i810/i810texstate.c index b873ddbecb..bff28c11c8 100644 --- a/src/mesa/drivers/dri/i810/i810texstate.c +++ b/src/mesa/drivers/dri/i810/i810texstate.c @@ -25,7 +25,6 @@ #include "main/glheader.h" #include "main/macros.h" #include "main/mtypes.h" -#include "main/texformat.h" #include "main/simple_list.h" #include "main/enums.h" #include "main/mm.h" diff --git a/src/mesa/drivers/dri/i915/i830_texblend.c b/src/mesa/drivers/dri/i915/i830_texblend.c index 09f7f37e76..3f64be8c96 100644 --- a/src/mesa/drivers/dri/i915/i830_texblend.c +++ b/src/mesa/drivers/dri/i915/i830_texblend.c @@ -30,7 +30,6 @@ #include "main/mtypes.h" #include "main/simple_list.h" #include "main/enums.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/mm.h" diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 837ae57074..98fb853c68 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -27,7 +27,6 @@ #include "main/mtypes.h" #include "main/enums.h" -#include "main/texformat.h" #include "intel_mipmap_tree.h" #include "intel_tex.h" diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index d53900b329..22f8bc7f19 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -26,7 +26,6 @@ **************************************************************************/ #include "glapi/glapi.h" -#include "main/texformat.h" #include "i830_context.h" #include "i830_reg.h" diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index d6f6cfdb49..03ed8a6311 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -27,7 +27,6 @@ #include "main/mtypes.h" #include "main/enums.h" -#include "main/texformat.h" #include "intel_mipmap_tree.h" #include "intel_tex.h" diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 1c3da63da9..a4b00b06e7 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -32,7 +32,6 @@ #include "main/imports.h" #include "main/macros.h" #include "main/colormac.h" -#include "main/texformat.h" #include "tnl/t_context.h" #include "tnl/t_vertex.h" diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index 89f47522a1..4fa3269bed 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -30,7 +30,6 @@ */ #include "main/mtypes.h" -#include "main/texformat.h" #include "main/texstore.h" #include "shader/prog_parameter.h" diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 46df778bee..5a2ac1a651 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -29,7 +29,6 @@ * Keith Whitwell */ -#include "main/texformat.h" #include "brw_context.h" #include "brw_util.h" #include "brw_wm.h" diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 855fe7593d..ea559d2ac7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -31,7 +31,6 @@ #include "main/mtypes.h" -#include "main/texformat.h" #include "main/texstore.h" #include "shader/prog_parameter.h" diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 799b22cc90..0158bd309f 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -29,7 +29,6 @@ #include "main/mtypes.h" #include "main/context.h" #include "main/enums.h" -#include "main/texformat.h" #include "main/colormac.h" #include "intel_blit.h" diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 1be381b9ea..3b4b90f2dc 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -33,7 +33,6 @@ #include "main/framebuffer.h" #include "main/renderbuffer.h" #include "main/context.h" -#include "main/texformat.h" #include "main/texrender.h" #include "drivers/common/meta.h" diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index f754ce0cd1..5bbcce6fe4 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -29,7 +29,6 @@ #include "main/macros.h" #include "main/mtypes.h" #include "main/colormac.h" -#include "main/texformat.h" #include "intel_buffers.h" #include "intel_fbo.h" diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index 22c010bbd7..eca0f6d572 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -1,7 +1,6 @@ #include "intel_context.h" #include "intel_tex.h" #include "intel_chipset.h" -#include "main/texformat.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index f32ff0dd05..b159010b8e 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -7,7 +7,6 @@ #include "main/convolve.h" #include "main/context.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/texgetimage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/mach64/mach64_tex.c b/src/mesa/drivers/dri/mach64/mach64_tex.c index 02433e5dd8..cce0e4d3ff 100644 --- a/src/mesa/drivers/dri/mach64/mach64_tex.c +++ b/src/mesa/drivers/dri/mach64/mach64_tex.c @@ -41,7 +41,6 @@ #include "main/simple_list.h" #include "main/enums.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/imports.h" diff --git a/src/mesa/drivers/dri/mach64/mach64_texmem.c b/src/mesa/drivers/dri/mach64/mach64_texmem.c index e83aeae3e1..b97e9eec25 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texmem.c +++ b/src/mesa/drivers/dri/mach64/mach64_texmem.c @@ -31,6 +31,11 @@ * Jose Fonseca */ +#include "main/context.h" +#include "main/macros.h" +#include "main/simple_list.h" +#include "main/imports.h" + #include "mach64_context.h" #include "mach64_state.h" #include "mach64_ioctl.h" @@ -38,12 +43,6 @@ #include "mach64_tris.h" #include "mach64_tex.h" -#include "main/context.h" -#include "main/macros.h" -#include "main/simple_list.h" -#include "main/texformat.h" -#include "main/imports.h" - /* Destroy hardware state associated with texture `t'. */ diff --git a/src/mesa/drivers/dri/mach64/mach64_texstate.c b/src/mesa/drivers/dri/mach64/mach64_texstate.c index c333355324..df0a09a5c1 100644 --- a/src/mesa/drivers/dri/mach64/mach64_texstate.c +++ b/src/mesa/drivers/dri/mach64/mach64_texstate.c @@ -33,7 +33,6 @@ #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "mach64_context.h" #include "mach64_ioctl.h" diff --git a/src/mesa/drivers/dri/mga/mga_texstate.c b/src/mesa/drivers/dri/mga/mga_texstate.c index d52f0fac75..54eda62a96 100644 --- a/src/mesa/drivers/dri/mga/mga_texstate.c +++ b/src/mesa/drivers/dri/mga/mga_texstate.c @@ -27,22 +27,19 @@ * Keith Whitwell */ -#include +#include "main/context.h" +#include "main/enums.h" +#include "main/macros.h" #include "main/mm.h" +#include "main/imports.h" +#include "main/simple_list.h" + #include "mgacontext.h" #include "mgatex.h" #include "mgaregs.h" #include "mgatris.h" #include "mgaioctl.h" -#include "main/context.h" -#include "main/enums.h" -#include "main/macros.h" -#include "main/imports.h" - -#include "main/simple_list.h" -#include "main/texformat.h" - #define MGA_USE_TABLE_FOR_FORMAT #ifdef MGA_USE_TABLE_FOR_FORMAT #define TMC_nr_tformat (MESA_FORMAT_YCBCR_REV + 1) diff --git a/src/mesa/drivers/dri/mga/mgatex.c b/src/mesa/drivers/dri/mga/mgatex.c index 71a8400e3b..9163371b33 100644 --- a/src/mesa/drivers/dri/mga/mgatex.c +++ b/src/mesa/drivers/dri/mga/mgatex.c @@ -27,23 +27,22 @@ #include "main/glheader.h" #include "main/mm.h" -#include "mgacontext.h" -#include "mgatex.h" -#include "mgaregs.h" -#include "mgatris.h" -#include "mgaioctl.h" - #include "main/colormac.h" #include "main/context.h" #include "main/enums.h" #include "main/simple_list.h" #include "main/imports.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" +#include "mgacontext.h" +#include "mgatex.h" +#include "mgaregs.h" +#include "mgatris.h" +#include "mgaioctl.h" + #include "swrast/swrast.h" #include "xmlpool.h" diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c index 6acda445f7..0a1207fb89 100644 --- a/src/mesa/drivers/dri/r128/r128_tex.c +++ b/src/mesa/drivers/dri/r128/r128_tex.c @@ -44,7 +44,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/simple_list.h" #include "main/enums.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/imports.h" diff --git a/src/mesa/drivers/dri/r128/r128_texmem.c b/src/mesa/drivers/dri/r128/r128_texmem.c index 84f8563b89..4ddcb86bcd 100644 --- a/src/mesa/drivers/dri/r128/r128_texmem.c +++ b/src/mesa/drivers/dri/r128/r128_texmem.c @@ -41,7 +41,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/context.h" #include "main/macros.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/imports.h" #define TEX_0 1 diff --git a/src/mesa/drivers/dri/r128/r128_texstate.c b/src/mesa/drivers/dri/r128/r128_texstate.c index 2e71c25861..cb2b5f9536 100644 --- a/src/mesa/drivers/dri/r128/r128_texstate.c +++ b/src/mesa/drivers/dri/r128/r128_texstate.c @@ -36,7 +36,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "r128_context.h" #include "r128_state.h" diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index 36d9e37d87..5a21a8b9c5 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -38,7 +38,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/enums.h" #include "main/image.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c index 1a6fa9f548..20ec6fffaf 100644 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ b/src/mesa/drivers/dri/r200/r200_texstate.c @@ -36,7 +36,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 3060f49aaf..ac20c08e20 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -45,7 +45,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/framebuffer.h" #include "main/simple_list.h" #include "main/api_arrayelt.h" -#include "main/texformat.h" #include "swrast/swrast.h" #include "swrast_setup/swrast_setup.h" diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index 10daeca9e6..27b78a912f 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/image.h" #include "main/mipmap.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/r300/r300_texstate.c b/src/mesa/drivers/dri/r300/r300_texstate.c index cb826248f3..1e9bd3e849 100644 --- a/src/mesa/drivers/dri/r300/r300_texstate.c +++ b/src/mesa/drivers/dri/r300/r300_texstate.c @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index 47081c968e..20965bb3c8 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -40,7 +40,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/image.h" #include "main/mipmap.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c index 55b455edc0..35186ef970 100644 --- a/src/mesa/drivers/dri/r600/r600_texstate.c +++ b/src/mesa/drivers/dri/r600/r600_texstate.c @@ -39,7 +39,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/imports.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index fbff109455..65f83b8315 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -46,7 +46,6 @@ #include "shader/prog_parameter.h" #include "shader/prog_statevars.h" #include "vbo/vbo.h" -#include "main/texformat.h" #include "r600_context.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index 90ea2ec335..3f4f382d6c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -33,7 +33,6 @@ #include "main/framebuffer.h" #include "main/renderbuffer.h" #include "main/context.h" -#include "main/texformat.h" #include "main/texrender.h" #include "drivers/common/meta.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c index 5429525587..86f596deb9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c +++ b/src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c @@ -32,7 +32,6 @@ #include "main/simple_list.h" #include "main/texcompress.h" -#include "main/texformat.h" static GLuint radeon_compressed_texture_size(GLcontext *ctx, GLsizei width, GLsizei height, GLsizei depth, diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 99865fff27..60981aada2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -38,7 +38,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/enums.h" #include "main/image.h" #include "main/simple_list.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c index cb17f48bf3..c7786381ae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texstate.c +++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c @@ -38,7 +38,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texobj.h" #include "main/enums.h" diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 17e42e72ee..8e9276c5ae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -34,7 +34,6 @@ #include "main/convolve.h" #include "main/mipmap.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/s3v/s3v_tex.c b/src/mesa/drivers/dri/s3v/s3v_tex.c index ec1182f34f..517f5e5ca7 100644 --- a/src/mesa/drivers/dri/s3v/s3v_tex.c +++ b/src/mesa/drivers/dri/s3v/s3v_tex.c @@ -2,16 +2,12 @@ * Author: Max Lingua */ -#include -#include - #include "main/glheader.h" #include "main/mtypes.h" #include "main/simple_list.h" #include "main/enums.h" #include "main/mm.h" #include "main/texstore.h" -#include "main/texformat.h" #include "main/teximage.h" #include "swrast/swrast.h" diff --git a/src/mesa/drivers/dri/savage/savage_xmesa.c b/src/mesa/drivers/dri/savage/savage_xmesa.c index 06179edae3..048fbe452c 100644 --- a/src/mesa/drivers/dri/savage/savage_xmesa.c +++ b/src/mesa/drivers/dri/savage/savage_xmesa.c @@ -574,7 +574,7 @@ savageDestroyContext(__DRIcontextPrivate *driContextPriv) _mesa_destroy_context(imesa->glCtx); /* no longer use vertex_dma_buf*/ - Xfree(imesa); + _mesa_free(imesa); } } diff --git a/src/mesa/drivers/dri/savage/savagetex.c b/src/mesa/drivers/dri/savage/savagetex.c index 796da4fc0d..6c97bb6c70 100644 --- a/src/mesa/drivers/dri/savage/savagetex.c +++ b/src/mesa/drivers/dri/savage/savagetex.c @@ -23,29 +23,24 @@ */ -#include -#include - -#include - +#include "main/context.h" #include "main/mm.h" -#include "savagecontext.h" -#include "savagetex.h" -#include "savagetris.h" -#include "savageioctl.h" -#include "main/simple_list.h" -#include "main/enums.h" -#include "savage_bci.h" - #include "main/macros.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/texobj.h" #include "main/convolve.h" #include "main/colormac.h" +#include "main/simple_list.h" +#include "main/enums.h" #include "swrast/swrast.h" +#include "savagecontext.h" +#include "savagetex.h" +#include "savagetris.h" +#include "savageioctl.h" +#include "savage_bci.h" + #include "xmlpool.h" #define TILE_INDEX_DXT1 0 diff --git a/src/mesa/drivers/dri/sis/sis_tex.c b/src/mesa/drivers/dri/sis/sis_tex.c index 5dc05146b1..951c470dad 100644 --- a/src/mesa/drivers/dri/sis/sis_tex.c +++ b/src/mesa/drivers/dri/sis/sis_tex.c @@ -28,17 +28,15 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * Eric Anholt */ -#include "sis_context.h" -#include "sis_alloc.h" -#include "sis_tex.h" - #include "swrast/swrast.h" #include "main/imports.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" #include "main/texobj.h" +#include "sis_context.h" +#include "sis_alloc.h" +#include "sis_tex.h" #include "xmlpool.h" #define ALIGN(value, align) (GLubyte *)((long)(value + align - 1) & ~(align - 1)) diff --git a/src/mesa/drivers/dri/sis/sis_texstate.c b/src/mesa/drivers/dri/sis/sis_texstate.c index 46417ce414..a507173b21 100644 --- a/src/mesa/drivers/dri/sis/sis_texstate.c +++ b/src/mesa/drivers/dri/sis/sis_texstate.c @@ -36,7 +36,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #include "main/colormac.h" #include "main/context.h" #include "main/macros.h" -#include "main/texformat.h" #include "sis_context.h" #include "sis_state.h" diff --git a/src/mesa/drivers/dri/tdfx/tdfx_state.c b/src/mesa/drivers/dri/tdfx/tdfx_state.c index 591df8a905..cf2712720f 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_state.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_state.c @@ -40,7 +40,6 @@ #include "main/mtypes.h" #include "main/colormac.h" -#include "main/texformat.h" #include "main/texstore.h" #include "main/teximage.h" diff --git a/src/mesa/drivers/dri/tdfx/tdfx_tex.c b/src/mesa/drivers/dri/tdfx/tdfx_tex.c index 5e9421aa2a..0cd9051613 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_tex.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_tex.c @@ -42,7 +42,6 @@ #include "main/image.h" #include "main/mipmap.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/teximage.h" #include "main/texstore.h" #include "main/texobj.h" diff --git a/src/mesa/drivers/dri/unichrome/via_tex.c b/src/mesa/drivers/dri/unichrome/via_tex.c index fa7542c5cb..a72dcd6be2 100644 --- a/src/mesa/drivers/dri/unichrome/via_tex.c +++ b/src/mesa/drivers/dri/unichrome/via_tex.c @@ -35,13 +35,12 @@ #include "main/convolve.h" #include "main/context.h" #include "main/mipmap.h" +#include "main/mm.h" #include "main/simple_list.h" #include "main/texcompress.h" -#include "main/texformat.h" #include "main/texobj.h" #include "main/texstore.h" -#include "main/mm.h" #include "via_context.h" #include "via_fb.h" #include "via_tex.h" -- cgit v1.2.3 From 9b8d2e76c395d6e1fcd09a61cd319cdc2d70c466 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 1 Oct 2009 18:16:52 -0700 Subject: i965: Use bo_references for the state cache delete function. This appears to shave about 3% off the CPU usage in cairo-gl for firefox. --- src/mesa/drivers/dri/i965/brw_state_cache.c | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index f8e46aacf7..c262e1db8b 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -534,14 +534,9 @@ brw_state_cache_bo_delete(struct brw_cache *cache, dri_bo *bo) for (i = 0; i < cache->size; i++) { for (prev = &cache->items[i]; *prev;) { struct brw_cache_item *c = *prev; - int j; - - for (j = 0; j < c->nr_reloc_bufs; j++) { - if (c->reloc_bufs[j] == bo) - break; - } - if (j != c->nr_reloc_bufs) { + if (drm_intel_bo_references(c->bo, bo)) { + int j; *prev = c->next; @@ -551,17 +546,8 @@ brw_state_cache_bo_delete(struct brw_cache *cache, dri_bo *bo) free((void *)c->key); free(c); cache->n_items--; - - /* Delete up the tree. Notably we're trying to get from - * a request to delete the surface, to deleting the surface state - * object, to deleting the binding table. We're slack and restart - * the deletion process when we do this because the other delete - * may kill our *prev. - */ - brw_state_cache_bo_delete(cache, c->bo); - prev = &cache->items[i]; } else { - prev = &(*prev)->next; + prev = &c->next; } } } -- cgit v1.2.3 From a82da7fa263c7fb6b902285994136890e6dc3278 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Sun, 11 Oct 2009 11:04:09 -0700 Subject: i965: Fix the bounds emitted in the vertex buffer packets. It's the address of the last valid byte, not the address of the first invalid byte. This should also fix problems with rendering with the new sanity checks in the kernel. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 4aa17fa02d..5c33246749 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -539,12 +539,12 @@ static void brw_emit_vertices(struct brw_context *brw) if (input->stride) { OUT_RELOC(input->bo, I915_GEM_DOMAIN_VERTEX, 0, - input->offset + input->stride * input->count); + input->offset + input->stride * input->count - 1); } else { assert(input->count == 1); OUT_RELOC(input->bo, I915_GEM_DOMAIN_VERTEX, 0, - input->offset + input->element_size); + input->offset + input->element_size - 1); } } else OUT_BATCH(input->stride ? input->count : 0); -- cgit v1.2.3 From f3be27c0cf8a4c47230f31d9d66bde7340ffb204 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Sun, 11 Oct 2009 11:16:03 -0700 Subject: i965: Fix the last valid address setting for the index buffer. Again, last valid address, not first invalid address. Fixes regression in 255e5be265133280293bbfd8b2f9b74b2dec50bb that the kernel now catches and caused piglit draw_elements_base_vertex to fail. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 5c33246749..9d089e113e 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -726,7 +726,7 @@ static void brw_emit_index_buffer(struct brw_context *brw) brw->ib.offset); OUT_RELOC(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, - brw->ib.offset + brw->ib.size); + brw->ib.offset + brw->ib.size - 1); OUT_BATCH( 0 ); ADVANCE_BATCH(); } -- cgit v1.2.3 From 15d2ef602461ca75e7160af46a2b5040742a91c9 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 12 Oct 2009 17:32:16 -0600 Subject: i965: remove unused var --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 9c28a22a29..f7cc5153a8 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -693,7 +693,6 @@ brw_wm_get_binding_table(struct brw_context *brw) static void prepare_wm_surfaces(struct brw_context *brw ) { GLcontext *ctx = &brw->intel.ctx; - struct intel_context *intel = &brw->intel; GLuint i; int old_nr_surfaces; -- cgit v1.2.3 From f094b86bb5ab93aedc03df5cf5bdf51ab9d37045 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Fri, 16 Oct 2009 09:33:11 -0600 Subject: mesa: lift default symlinks target into Makefile.template Driver Makefiles can still add symlink dependencies/rules if needed. --- src/mesa/drivers/dri/Makefile.template | 4 ++++ src/mesa/drivers/dri/fb/Makefile | 2 -- src/mesa/drivers/dri/ffb/Makefile | 1 - src/mesa/drivers/dri/gamma/Makefile | 1 - src/mesa/drivers/dri/i810/Makefile | 1 - src/mesa/drivers/dri/i915/Makefile | 1 - src/mesa/drivers/dri/i965/Makefile | 1 - src/mesa/drivers/dri/mach64/Makefile | 1 - src/mesa/drivers/dri/mga/Makefile | 1 - src/mesa/drivers/dri/r128/Makefile | 1 - src/mesa/drivers/dri/r200/Makefile | 1 - src/mesa/drivers/dri/r300/Makefile | 2 -- src/mesa/drivers/dri/r600/Makefile | 1 - src/mesa/drivers/dri/radeon/Makefile | 1 - src/mesa/drivers/dri/s3v/Makefile | 1 - src/mesa/drivers/dri/savage/Makefile | 1 - src/mesa/drivers/dri/sis/Makefile | 1 - src/mesa/drivers/dri/swrast/Makefile | 1 - src/mesa/drivers/dri/tdfx/Makefile | 2 -- src/mesa/drivers/dri/trident/Makefile | 1 - src/mesa/drivers/dri/unichrome/Makefile | 1 - 21 files changed, 4 insertions(+), 23 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/Makefile.template b/src/mesa/drivers/dri/Makefile.template index d2731aebae..1ce9315530 100644 --- a/src/mesa/drivers/dri/Makefile.template +++ b/src/mesa/drivers/dri/Makefile.template @@ -86,6 +86,10 @@ subdirs: fi +.PHONY: symlinks +symlinks: + + depend: $(C_SOURCES) $(ASM_SOURCES) $(SYMLINKS) @ echo "running $(MKDEP)" @ rm -f depend diff --git a/src/mesa/drivers/dri/fb/Makefile b/src/mesa/drivers/dri/fb/Makefile index 309f50b95f..cf9b3a8556 100644 --- a/src/mesa/drivers/dri/fb/Makefile +++ b/src/mesa/drivers/dri/fb/Makefile @@ -25,5 +25,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: - diff --git a/src/mesa/drivers/dri/ffb/Makefile b/src/mesa/drivers/dri/ffb/Makefile index cb73238c03..e9da8f9066 100644 --- a/src/mesa/drivers/dri/ffb/Makefile +++ b/src/mesa/drivers/dri/ffb/Makefile @@ -33,4 +33,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/gamma/Makefile b/src/mesa/drivers/dri/gamma/Makefile index 250d3ac089..09df1578fc 100644 --- a/src/mesa/drivers/dri/gamma/Makefile +++ b/src/mesa/drivers/dri/gamma/Makefile @@ -32,4 +32,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/i810/Makefile b/src/mesa/drivers/dri/i810/Makefile index a7825b49b4..3874faee51 100644 --- a/src/mesa/drivers/dri/i810/Makefile +++ b/src/mesa/drivers/dri/i810/Makefile @@ -29,4 +29,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile index 393312e732..37f15aa767 100644 --- a/src/mesa/drivers/dri/i915/Makefile +++ b/src/mesa/drivers/dri/i915/Makefile @@ -72,4 +72,3 @@ intel_decode.o: ../intel/intel_decode.c intel_tex_layout.o: ../intel/intel_tex_layout.c -symlinks: diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index 57dcc91586..7a55333e89 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -100,6 +100,5 @@ DRI_LIB_DEPS += -ldrm_intel include ../Makefile.template -symlinks: intel_decode.o: ../intel/intel_decode.c intel_tex_layout.o: ../intel/intel_tex_layout.c diff --git a/src/mesa/drivers/dri/mach64/Makefile b/src/mesa/drivers/dri/mach64/Makefile index 7246d51f5d..a8f463e9fd 100644 --- a/src/mesa/drivers/dri/mach64/Makefile +++ b/src/mesa/drivers/dri/mach64/Makefile @@ -30,4 +30,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/mga/Makefile b/src/mesa/drivers/dri/mga/Makefile index a871064c62..0cc329fb22 100644 --- a/src/mesa/drivers/dri/mga/Makefile +++ b/src/mesa/drivers/dri/mga/Makefile @@ -31,4 +31,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/r128/Makefile b/src/mesa/drivers/dri/r128/Makefile index 796dfbc516..52c5a38a70 100644 --- a/src/mesa/drivers/dri/r128/Makefile +++ b/src/mesa/drivers/dri/r128/Makefile @@ -29,4 +29,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/r200/Makefile b/src/mesa/drivers/dri/r200/Makefile index fbce70c37b..776f1e3f3f 100644 --- a/src/mesa/drivers/dri/r200/Makefile +++ b/src/mesa/drivers/dri/r200/Makefile @@ -66,4 +66,3 @@ include ../Makefile.template #INCLUDES += -I../radeon/server -symlinks: diff --git a/src/mesa/drivers/dri/r300/Makefile b/src/mesa/drivers/dri/r300/Makefile index 0e5b29b685..cb0f715fa0 100644 --- a/src/mesa/drivers/dri/r300/Makefile +++ b/src/mesa/drivers/dri/r300/Makefile @@ -78,5 +78,3 @@ EXTRA_MODULES = compiler/libr300compiler.a include ../Makefile.template -symlinks: - diff --git a/src/mesa/drivers/dri/r600/Makefile b/src/mesa/drivers/dri/r600/Makefile index 7d5a7b1ab6..9b7c42042e 100644 --- a/src/mesa/drivers/dri/r600/Makefile +++ b/src/mesa/drivers/dri/r600/Makefile @@ -76,4 +76,3 @@ DRI_LIB_DEPS += $(RADEON_LDFLAGS) include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/radeon/Makefile b/src/mesa/drivers/dri/radeon/Makefile index b1efc72872..ae2e695bfc 100644 --- a/src/mesa/drivers/dri/radeon/Makefile +++ b/src/mesa/drivers/dri/radeon/Makefile @@ -55,4 +55,3 @@ X86_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/s3v/Makefile b/src/mesa/drivers/dri/s3v/Makefile index 9bd7973154..da7e6cdc20 100644 --- a/src/mesa/drivers/dri/s3v/Makefile +++ b/src/mesa/drivers/dri/s3v/Makefile @@ -33,4 +33,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/savage/Makefile b/src/mesa/drivers/dri/savage/Makefile index 018482f66b..2e5c40802c 100644 --- a/src/mesa/drivers/dri/savage/Makefile +++ b/src/mesa/drivers/dri/savage/Makefile @@ -27,4 +27,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/sis/Makefile b/src/mesa/drivers/dri/sis/Makefile index d2354e6776..ad009fc239 100644 --- a/src/mesa/drivers/dri/sis/Makefile +++ b/src/mesa/drivers/dri/sis/Makefile @@ -34,4 +34,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/swrast/Makefile b/src/mesa/drivers/dri/swrast/Makefile index 5f3a4f2191..771169c1ff 100644 --- a/src/mesa/drivers/dri/swrast/Makefile +++ b/src/mesa/drivers/dri/swrast/Makefile @@ -21,4 +21,3 @@ SWRAST_COMMON_SOURCES = \ include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/tdfx/Makefile b/src/mesa/drivers/dri/tdfx/Makefile index 092c580fea..b9f25db4fe 100644 --- a/src/mesa/drivers/dri/tdfx/Makefile +++ b/src/mesa/drivers/dri/tdfx/Makefile @@ -32,6 +32,4 @@ ASM_SOURCES = include ../Makefile.template -symlinks: - diff --git a/src/mesa/drivers/dri/trident/Makefile b/src/mesa/drivers/dri/trident/Makefile index 9ee24c504c..bd9b7f35a2 100644 --- a/src/mesa/drivers/dri/trident/Makefile +++ b/src/mesa/drivers/dri/trident/Makefile @@ -23,4 +23,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: diff --git a/src/mesa/drivers/dri/unichrome/Makefile b/src/mesa/drivers/dri/unichrome/Makefile index 5fe00c1bd1..344d34fce3 100644 --- a/src/mesa/drivers/dri/unichrome/Makefile +++ b/src/mesa/drivers/dri/unichrome/Makefile @@ -29,4 +29,3 @@ ASM_SOURCES = include ../Makefile.template -symlinks: -- cgit v1.2.3 From 4bd70b5cff13039a4b0e0c554156fec06e3c3906 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 21 Oct 2009 20:00:43 -0600 Subject: i965: change parameter type to gl_format --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index ea559d2ac7..5d8bb7a14b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -69,7 +69,8 @@ static GLuint translate_tex_target( GLenum target ) } -static GLuint translate_tex_format( GLuint mesa_format, GLenum internal_format, +static GLuint translate_tex_format( gl_format mesa_format, + GLenum internal_format, GLenum depth_mode ) { switch( mesa_format ) { -- cgit v1.2.3 From 2f7abf5c042a1bcf97d77d6dad4a17bda37e0567 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 22 Oct 2009 16:26:54 -0600 Subject: i965: remove unused BRW_FALLBACK_TEXTURE bit The value was probably wrong too. It was the same as INTEL_FALLBACK_DRAW_BUFFER. --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index a5209ac41b..b7d6c7ce7e 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -115,7 +115,7 @@ * Handles blending and (presumably) depth and stencil testing. */ -#define BRW_FALLBACK_TEXTURE 0x1 + #define BRW_MAX_CURBE (32*16) struct brw_context; -- cgit v1.2.3 From f9bbbe5803a72eceb8ed6ddc73bb48c8bcdc0179 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 22 Oct 2009 16:32:08 -0600 Subject: i965: remove unused brw_context::tmp_fallback field --- src/mesa/drivers/dri/i965/brw_context.h | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index b7d6c7ce7e..da0e091bfd 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -454,7 +454,6 @@ struct brw_context GLuint primitive; GLboolean emit_state_always; - GLboolean tmp_fallback; GLboolean no_batch_wrap; struct { -- cgit v1.2.3 From 8810b8f67135185d1044746bb861fe2ff997626c Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 22 Oct 2009 16:45:50 -0600 Subject: i965: fix hacked Fallback usage in brw_prepare_vertices() Setting intel->Fallback = 1 clobbered any fallback state that was already set. Not sure where this hack originated (the git history is a little convoluted). Define and use a new BRW_FALLBACK_DRAW bit instead. This shouldn't break anything and could potentially fix some bugs (but no specific ones are known). --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index da0e091bfd..b1e7ec8465 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -116,6 +116,8 @@ */ +#define BRW_FALLBACK_DRAW (INTEL_FALLBACK_DRIVER << 0) + #define BRW_MAX_CURBE (32*16) struct brw_context; diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 9d089e113e..4f8ceb37bd 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -375,9 +375,10 @@ static void brw_prepare_vertices(struct brw_context *brw) * isn't an issue at this point. */ if (brw->vb.nr_enabled >= BRW_VEP_MAX) { - intel->Fallback = 1; + FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); return; } + FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); for (i = 0; i < brw->vb.nr_enabled; i++) { struct brw_vertex_element *input = brw->vb.enabled[i]; @@ -427,9 +428,10 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Position array not properly enabled: */ if (input->glarray->StrideB == 0) { - intel->Fallback = 1; + FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); return; } + FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); interleave = input->glarray->StrideB; ptr = input->glarray->Ptr; -- cgit v1.2.3 From 2d17dbfb5346b6d75e87c839148cbe125bf5cd6d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 9 Jul 2009 09:32:21 -0700 Subject: intel: Keep track of x,y offsets in miptrees and use them for blitting. By just using offsets, we confused the hardware's tiling calculations, resulting in failures in miptree validation and blit clears. Fixes piglit fbo-clearmipmap. Bug #23552. (automatic mipmap generation) --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +- src/mesa/drivers/dri/intel/intel_blit.c | 19 ++-- src/mesa/drivers/dri/intel/intel_fbo.c | 24 ++--- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 137 +++++++++++-------------- src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 29 ++---- src/mesa/drivers/dri/intel/intel_regions.h | 2 + src/mesa/drivers/dri/intel/intel_tex_copy.c | 17 +-- src/mesa/drivers/dri/intel/intel_tex_image.c | 23 +++-- 8 files changed, 118 insertions(+), 140 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 5986cbffad..e59e52ed86 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -86,10 +86,10 @@ GLboolean brw_miptree_layout(struct intel_context *intel, mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch); if (mt->compressed) { - qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * mt->pitch * mt->cpp; + qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4; mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6; } else { - qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * mt->pitch * mt->cpp; + qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h); mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6; } @@ -102,7 +102,8 @@ GLboolean brw_miptree_layout(struct intel_context *intel, height, 1); for (q = 0; q < nr_images; q++) - intel_miptree_set_image_offset_ex(mt, level, q, x, y, q * qpitch); + intel_miptree_set_image_offset(mt, level, q, + x, y + q * qpitch); if (mt->compressed) img_height = MAX2(1, height/4); diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 0c5be4c798..ec4a5b492a 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -441,6 +441,10 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) intel_region_buffer(intel, irb->region, all ? INTEL_WRITE_FULL : INTEL_WRITE_PART); + int x1 = b.x1 + irb->region->draw_x; + int y1 = b.y1 + irb->region->draw_y; + int x2 = b.x2 + irb->region->draw_x; + int y2 = b.y2 + irb->region->draw_y; GLuint clearVal; GLint pitch, cpp; @@ -449,11 +453,10 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) pitch = irb->region->pitch; cpp = irb->region->cpp; - DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", + DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", __FUNCTION__, irb->region->buffer, (pitch * cpp), - irb->region->draw_offset, - b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1); + x1, y1, x2 - x1, y2 - y1); BR13 = 0xf0 << 16; CMD = XY_COLOR_BLT_CMD; @@ -526,17 +529,17 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) buf, irb->Base.Name); */ - assert(b.x1 < b.x2); - assert(b.y1 < b.y2); + assert(x1 < x2); + assert(y1 < y2); BEGIN_BATCH(6, REFERENCES_CLIPRECTS); OUT_BATCH(CMD); OUT_BATCH(BR13); - OUT_BATCH((b.y1 << 16) | b.x1); - OUT_BATCH((b.y2 << 16) | b.x2); + OUT_BATCH((y1 << 16) | x1); + OUT_BATCH((y2 << 16) | x2); OUT_RELOC(write_buffer, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, - irb->region->draw_offset); + 0); OUT_BATCH(clearVal); ADVANCE_BATCH(); clearMask &= ~bufBit; /* turn off bit, for faster loop exit */ diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 804c034840..cf007d5b62 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -571,7 +571,7 @@ intel_render_texture(GLcontext * ctx, = att->Texture->Image[att->CubeMapFace][att->TextureLevel]; struct intel_renderbuffer *irb = intel_renderbuffer(att->Renderbuffer); struct intel_texture_image *intel_image; - GLuint imageOffset; + GLuint dst_x, dst_y; (void) fb; @@ -618,18 +618,16 @@ intel_render_texture(GLcontext * ctx, } /* compute offset of the particular 2D image within the texture region */ - imageOffset = intel_miptree_image_offset(intel_image->mt, - att->CubeMapFace, - att->TextureLevel); - - if (att->Texture->Target == GL_TEXTURE_3D) { - const GLuint *offsets = intel_miptree_depth_offsets(intel_image->mt, - att->TextureLevel); - imageOffset += offsets[att->Zoffset]; - } - - /* store that offset in the region */ - intel_image->mt->region->draw_offset = imageOffset; + intel_miptree_get_image_offset(intel_image->mt, + att->TextureLevel, + att->CubeMapFace, + att->Zoffset, + &dst_x, &dst_y); + + intel_image->mt->region->draw_offset = (dst_y * intel_image->mt->pitch + + dst_x) * intel_image->mt->cpp; + intel_image->mt->region->draw_x = dst_x; + intel_image->mt->region->draw_y = dst_y; /* update drawing region, etc */ intel_draw_buffer(ctx, fb); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 4f5101a312..0589d82db2 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -287,9 +287,10 @@ intel_miptree_release(struct intel_context *intel, intel_region_release(&((*mt)->region)); - for (i = 0; i < MAX_TEXTURE_LEVELS; i++) - if ((*mt)->level[i].image_offset) - free((*mt)->level[i].image_offset); + for (i = 0; i < MAX_TEXTURE_LEVELS; i++) { + free((*mt)->level[i].x_offset); + free((*mt)->level[i].y_offset); + } free(*mt); } @@ -350,82 +351,58 @@ intel_miptree_set_level_info(struct intel_mipmap_tree *mt, mt->level[level].height = h; mt->level[level].depth = d; mt->level[level].level_offset = (x + y * mt->pitch) * mt->cpp; + mt->level[level].level_x = x; + mt->level[level].level_y = y; mt->level[level].nr_images = nr_images; DBG("%s level %d size: %d,%d,%d offset %d,%d (0x%x)\n", __FUNCTION__, level, w, h, d, x, y, mt->level[level].level_offset); - /* Not sure when this would happen, but anyway: - */ - if (mt->level[level].image_offset) { - free(mt->level[level].image_offset); - mt->level[level].image_offset = NULL; - } - assert(nr_images); + assert(!mt->level[level].x_offset); - mt->level[level].image_offset = malloc(nr_images * sizeof(GLuint)); - mt->level[level].image_offset[0] = 0; + mt->level[level].x_offset = malloc(nr_images * sizeof(GLuint)); + mt->level[level].x_offset[0] = mt->level[level].level_x; + mt->level[level].y_offset = malloc(nr_images * sizeof(GLuint)); + mt->level[level].y_offset[0] = mt->level[level].level_y; } void -intel_miptree_set_image_offset_ex(struct intel_mipmap_tree *mt, - GLuint level, GLuint img, - GLuint x, GLuint y, - GLuint offset) +intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, + GLuint level, GLuint img, + GLuint x, GLuint y) { if (img == 0 && level == 0) assert(x == 0 && y == 0); assert(img < mt->level[level].nr_images); - mt->level[level].image_offset[img] = (x + y * mt->pitch) * mt->cpp + offset; + mt->level[level].x_offset[img] = mt->level[level].level_x + x; + mt->level[level].y_offset[img] = mt->level[level].level_y + y; - DBG("%s level %d img %d pos %d,%d image_offset %x\n", - __FUNCTION__, level, img, x, y, mt->level[level].image_offset[img]); + DBG("%s level %d img %d pos %d,%d\n", + __FUNCTION__, level, img, + mt->level[level].x_offset[img], mt->level[level].y_offset[img]); } void -intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, - GLuint level, GLuint img, - GLuint x, GLuint y) -{ - intel_miptree_set_image_offset_ex(mt, level, img, x, y, 0); -} - - -/* Although we use the image_offset[] array to store relative offsets - * to cube faces, Mesa doesn't know anything about this and expects - * each cube face to be treated as a separate image. - * - * These functions present that view to mesa: - */ -const GLuint * -intel_miptree_depth_offsets(struct intel_mipmap_tree *mt, GLuint level) -{ - static const GLuint zero = 0; - - if (mt->target != GL_TEXTURE_3D || mt->level[level].nr_images == 1) - return &zero; - else - return mt->level[level].image_offset; -} - - -GLuint -intel_miptree_image_offset(struct intel_mipmap_tree *mt, - GLuint face, GLuint level) +intel_miptree_get_image_offset(struct intel_mipmap_tree *mt, + GLuint level, GLuint face, GLuint depth, + GLuint *x, GLuint *y) { - if (mt->target == GL_TEXTURE_CUBE_MAP_ARB) - return (mt->level[level].level_offset + - mt->level[level].image_offset[face]); - else - return mt->level[level].level_offset; + if (mt->target == GL_TEXTURE_CUBE_MAP_ARB) { + *x = mt->level[level].x_offset[face]; + *y = mt->level[level].y_offset[face]; + } else if (mt->target == GL_TEXTURE_3D) { + *x = mt->level[level].x_offset[depth]; + *y = mt->level[level].y_offset[depth]; + } else { + *x = mt->level[level].x_offset[0]; + *y = mt->level[level].y_offset[0]; + } } - - /** * Map a teximage in a mipmap tree. * \param row_stride returns row stride in bytes @@ -441,6 +418,7 @@ intel_miptree_image_map(struct intel_context * intel, GLuint level, GLuint * row_stride, GLuint * image_offsets) { + GLuint x, y; DBG("%s \n", __FUNCTION__); if (row_stride) @@ -449,17 +427,23 @@ intel_miptree_image_map(struct intel_context * intel, if (mt->target == GL_TEXTURE_3D) { int i; - for (i = 0; i < mt->level[level].depth; i++) - image_offsets[i] = mt->level[level].image_offset[i] / mt->cpp; + for (i = 0; i < mt->level[level].depth; i++) { + + intel_miptree_get_image_offset(mt, level, face, i, + &x, &y); + image_offsets[i] = x + y * mt->pitch; + } + + return intel_region_map(intel, mt->region); } else { assert(mt->level[level].depth == 1); - assert(mt->target == GL_TEXTURE_CUBE_MAP || - mt->level[level].image_offset[0] == 0); + intel_miptree_get_image_offset(mt, level, face, 0, + &x, &y); image_offsets[0] = 0; - } - return (intel_region_map(intel, mt->region) + - intel_miptree_image_offset(mt, face, level)); + return intel_region_map(intel, mt->region) + + (x + y * mt->pitch) * mt->cpp; + } } void @@ -484,20 +468,19 @@ intel_miptree_image_data(struct intel_context *intel, GLuint src_image_pitch) { GLuint depth = dst->level[level].depth; - GLuint dst_offset = intel_miptree_image_offset(dst, face, level); - const GLuint *dst_depth_offset = intel_miptree_depth_offsets(dst, level); GLuint i; - GLuint height = 0; DBG("%s: %d/%d\n", __FUNCTION__, face, level); for (i = 0; i < depth; i++) { + GLuint dst_x, dst_y, height; + + intel_miptree_get_image_offset(dst, level, face, i, &dst_x, &dst_y); + height = dst->level[level].height; if(dst->compressed) height = (height + 3) / 4; intel_region_data(intel, - dst->region, - dst_offset + dst_depth_offset[i], /* dst_offset */ - 0, 0, /* dstx, dsty */ + dst->region, 0, dst_x, dst_y, src, src_row_pitch, 0, 0, /* source x, y */ @@ -519,10 +502,7 @@ intel_miptree_image_copy(struct intel_context *intel, GLuint width = src->level[level].width; GLuint height = src->level[level].height; GLuint depth = src->level[level].depth; - GLuint dst_offset = intel_miptree_image_offset(dst, face, level); - GLuint src_offset = intel_miptree_image_offset(src, face, level); - const GLuint *dst_depth_offset = intel_miptree_depth_offsets(dst, level); - const GLuint *src_depth_offset = intel_miptree_depth_offsets(src, level); + GLuint src_x, src_y, dst_x, dst_y; GLuint i; GLboolean success; @@ -535,22 +515,23 @@ intel_miptree_image_copy(struct intel_context *intel, } for (i = 0; i < depth; i++) { + intel_miptree_get_image_offset(src, level, face, i, &src_x, &src_y); + intel_miptree_get_image_offset(dst, level, face, i, &dst_x, &dst_y); success = intel_region_copy(intel, - dst->region, dst_offset + dst_depth_offset[i], - 0, 0, - src->region, src_offset + src_depth_offset[i], - 0, 0, width, height, GL_COPY); + dst->region, 0, dst_x, dst_y, + src->region, 0, src_x, src_y, width, height, + GL_COPY); if (!success) { GLubyte *src_ptr, *dst_ptr; src_ptr = intel_region_map(intel, src->region); dst_ptr = intel_region_map(intel, dst->region); - _mesa_copy_rect(dst_ptr + dst_offset + dst_depth_offset[i], + _mesa_copy_rect(dst_ptr + dst->cpp * (dst_x + dst_y * dst->pitch), dst->cpp, dst->pitch, 0, 0, width, height, - src_ptr + src_offset + src_depth_offset[i], + src_ptr + src->cpp * (src_x + src_y * src->pitch), src->pitch, 0, 0); intel_region_unmap(intel, src->region); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h index c890b2a0d0..3bce54daa1 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h @@ -70,6 +70,10 @@ struct intel_mipmap_level * always zero in that case. */ GLuint level_offset; + /** Offset to this miptree level, used in computing x_offset. */ + GLuint level_x; + /** Offset to this miptree level, used in computing y_offset. */ + GLuint level_y; GLuint width; GLuint height; /** Depth of the mipmap at this level: 1 for 1D/2D/CUBE, n for 3D. */ @@ -86,7 +90,7 @@ struct intel_mipmap_level * compute the offsets of depth/cube images within a mipmap level, * so have to store them as a lookup table. */ - GLuint *image_offset; + GLuint *x_offset, *y_offset; }; struct intel_mipmap_tree @@ -176,19 +180,10 @@ GLubyte *intel_miptree_image_map(struct intel_context *intel, void intel_miptree_image_unmap(struct intel_context *intel, struct intel_mipmap_tree *mt); - -/* Return the linear offset of an image relative to the start of the - * tree: - */ -GLuint intel_miptree_image_offset(struct intel_mipmap_tree *mt, - GLuint face, GLuint level); - -/* Return pointers to each 2d slice within an image. Indexed by depth - * value. - */ -const GLuint *intel_miptree_depth_offsets(struct intel_mipmap_tree *mt, - GLuint level); - +void +intel_miptree_get_image_offset(struct intel_mipmap_tree *mt, + GLuint level, GLuint face, GLuint depth, + GLuint *x, GLuint *y); void intel_miptree_set_level_info(struct intel_mipmap_tree *mt, GLuint level, @@ -196,16 +191,10 @@ void intel_miptree_set_level_info(struct intel_mipmap_tree *mt, GLuint x, GLuint y, GLuint w, GLuint h, GLuint d); -void intel_miptree_set_image_offset_ex(struct intel_mipmap_tree *mt, - GLuint level, - GLuint img, GLuint x, GLuint y, - GLuint offset); - void intel_miptree_set_image_offset(struct intel_mipmap_tree *mt, GLuint level, GLuint img, GLuint x, GLuint y); - /* Upload an image into a tree */ void intel_miptree_image_data(struct intel_context *intel, diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h index 0d379bdc6e..535fcd7be0 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.h +++ b/src/mesa/drivers/dri/intel/intel_regions.h @@ -62,6 +62,8 @@ struct intel_region GLuint map_refcount; /**< Reference count for mapping */ GLuint draw_offset; /**< Offset of drawing address within the region */ + GLuint draw_x, draw_y; /**< Offset of drawing within the region */ + uint32_t tiling; /**< Which tiling mode the region is in */ uint32_t bit_6_swizzle; /**< GEM flag for address swizzling requirement */ drmAddress classic_map; /**< drmMap of the region when not in GEM mode */ diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index b241c11625..9d58b11b14 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -115,20 +115,22 @@ do_copy_texsubimage(struct intel_context *intel, drm_intel_bo *dst_bo = intel_region_buffer(intel, intelImage->mt->region, INTEL_WRITE_PART); - GLuint image_offset = intel_miptree_image_offset(intelImage->mt, - intelImage->face, - intelImage->level); const GLint orig_x = x; const GLint orig_y = y; + GLuint image_x, image_y; GLshort src_pitch; + intel_miptree_get_image_offset(intelImage->mt, + intelImage->level, + intelImage->face, + 0, + &image_x, &image_y); /* Update dst for clipped src. Need to also clip the source rect. */ dstx += x - orig_x; dsty += y - orig_y; /* Can't blit to tiled buffers with non-tile-aligned offset. */ - if (intelImage->mt->region->tiling != I915_TILING_NONE && - (image_offset & 4095) != 0) { + if (intelImage->mt->region->tiling == I915_TILING_Y) { UNLOCK_HARDWARE(intel); return GL_FALSE; } @@ -160,9 +162,10 @@ do_copy_texsubimage(struct intel_context *intel, src->tiling, intelImage->mt->pitch, dst_bo, - image_offset, + 0, intelImage->mt->region->tiling, - x, y, dstx, dsty, width, height, + x, y, image_x + dstx, image_y + dsty, + width, height, GL_COPY)) { UNLOCK_HARDWARE(intel); return GL_FALSE; diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index c5f5220837..2e0945c365 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -204,7 +204,7 @@ try_pbo_upload(struct intel_context *intel, { struct intel_buffer_object *pbo = intel_buffer_object(unpack->BufferObj); GLuint src_offset, src_stride; - GLuint dst_offset, dst_stride; + GLuint dst_x, dst_y, dst_stride; if (unpack->BufferObj->Name == 0 || intel->ctx._ImageTransferState || @@ -221,9 +221,9 @@ try_pbo_upload(struct intel_context *intel, else src_stride = width; - dst_offset = intel_miptree_image_offset(intelImage->mt, - intelImage->face, - intelImage->level); + intel_miptree_get_image_offset(intelImage->mt, intelImage->level, + intelImage->face, 0, + &dst_x, &dst_y); dst_stride = intelImage->mt->pitch; @@ -239,8 +239,8 @@ try_pbo_upload(struct intel_context *intel, if (!intelEmitCopyBlit(intel, intelImage->mt->cpp, src_stride, src_buffer, src_offset, GL_FALSE, - dst_stride, dst_buffer, dst_offset, GL_FALSE, - 0, 0, 0, 0, width, height, + dst_stride, dst_buffer, 0, GL_FALSE, + 0, 0, dst_x, dst_y, width, height, GL_COPY)) { UNLOCK_HARDWARE(intel); return GL_FALSE; @@ -262,7 +262,7 @@ try_pbo_zcopy(struct intel_context *intel, { struct intel_buffer_object *pbo = intel_buffer_object(unpack->BufferObj); GLuint src_offset, src_stride; - GLuint dst_offset, dst_stride; + GLuint dst_x, dst_y, dst_stride; if (unpack->BufferObj->Name == 0 || intel->ctx._ImageTransferState || @@ -279,13 +279,14 @@ try_pbo_zcopy(struct intel_context *intel, else src_stride = width; - dst_offset = intel_miptree_image_offset(intelImage->mt, - intelImage->face, - intelImage->level); + intel_miptree_get_image_offset(intelImage->mt, intelImage->level, + intelImage->face, 0, + &dst_x, &dst_y); dst_stride = intelImage->mt->pitch; - if (src_stride != dst_stride || dst_offset != 0 || src_offset != 0) { + if (src_stride != dst_stride || dst_x != 0 || dst_y != 0 || + src_offset != 0) { DBG("%s: failure 2\n", __FUNCTION__); return GL_FALSE; } -- cgit v1.2.3 From bfd51dc34d45ba584683c70b1f854a513d9104d3 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 7 Jul 2009 19:33:55 -0700 Subject: i965: Annotate _NEW_COLOR dependency for brw_update_renderbuffer_surface(). --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index f7cc5153a8..1dd8a0728a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -564,6 +564,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.cpp = 4; key.draw_offset = 0; } + /* _NEW_COLOR */ memcpy(key.color_mask, ctx->Color.ColorMask, sizeof(key.color_mask)); key.color_blend = (!ctx->Color._LogicOpEnabled && @@ -696,7 +697,7 @@ static void prepare_wm_surfaces(struct brw_context *brw ) GLuint i; int old_nr_surfaces; - /* _NEW_BUFFERS */ + /* _NEW_BUFFERS | _NEW_COLOR */ /* Update surfaces for drawing buffers */ if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { -- cgit v1.2.3 From f9e334cb32152fd342ac6b1dd4776215af6e1d49 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 09:27:44 -0600 Subject: Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()" This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c. It turns out the i965 driver uses the intel->Fallback field as a boolean, not as a bitmask. The intelFallback() function is a no-op in the i965 driver. It would have been nice if there were some comments about this. I'll fix that next... --- src/mesa/drivers/dri/i965/brw_context.h | 2 -- src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 ++---- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index b1e7ec8465..da0e091bfd 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -116,8 +116,6 @@ */ -#define BRW_FALLBACK_DRAW (INTEL_FALLBACK_DRIVER << 0) - #define BRW_MAX_CURBE (32*16) struct brw_context; diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 4f8ceb37bd..9d089e113e 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -375,10 +375,9 @@ static void brw_prepare_vertices(struct brw_context *brw) * isn't an issue at this point. */ if (brw->vb.nr_enabled >= BRW_VEP_MAX) { - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); + intel->Fallback = 1; return; } - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); for (i = 0; i < brw->vb.nr_enabled; i++) { struct brw_vertex_element *input = brw->vb.enabled[i]; @@ -428,10 +427,9 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Position array not properly enabled: */ if (input->glarray->StrideB == 0) { - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); + intel->Fallback = 1; return; } - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); interleave = input->glarray->StrideB; ptr = input->glarray->Ptr; -- cgit v1.2.3 From 43dc91f8bbb69499a6a0326a78e434b313f73c2c Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 09:31:31 -0600 Subject: i965: be clear that the Fallback field is a boolean, not a bitfield --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 4 ++-- src/mesa/drivers/dri/i965/brw_fallback.c | 6 +++++- src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 9d089e113e..348c66154f 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -375,7 +375,7 @@ static void brw_prepare_vertices(struct brw_context *brw) * isn't an issue at this point. */ if (brw->vb.nr_enabled >= BRW_VEP_MAX) { - intel->Fallback = 1; + intel->Fallback = GL_TRUE; /* boolean, not bitfield */ return; } @@ -427,7 +427,7 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Position array not properly enabled: */ if (input->glarray->StrideB == 0) { - intel->Fallback = 1; + intel->Fallback = GL_TRUE; /* boolean, not bitfield */ return; } diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index d27c6c24ca..562a17844b 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -133,7 +133,11 @@ const struct brw_tracked_state brw_check_fallback = { -/* Not used: +/** + * Called by the INTEL_FALLBACK() macro. + * NOTE: this is a no-op for the i965 driver. The brw->intel.Fallback + * field is treated as a boolean, not a bitmask. It's only set in a + * couple of places. */ void intelFallback( struct intel_context *intel, GLuint bit, GLboolean mode ) { diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index b817b741e7..ee447afa62 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -308,7 +308,7 @@ void brw_validate_state( struct brw_context *brw ) if (brw->state.dirty.brw & BRW_NEW_CONTEXT) brw_clear_batch_cache(brw); - brw->intel.Fallback = 0; + brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */ /* do prepare stage for all atoms */ for (i = 0; i < Elements(atoms); i++) { -- cgit v1.2.3 From 755161b88843f3cfead9a02e076d1a04687d9082 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 09:27:44 -0600 Subject: Revert "i965: fix hacked Fallback usage in brw_prepare_vertices()" This reverts commit 8810b8f67135185d1044746bb861fe2ff997626c. It turns out the i965 driver uses the intel->Fallback field as a boolean, not as a bitmask. The intelFallback() function is a no-op in the i965 driver. It would have been nice if there were some comments about this. I'll fix that next... --- src/mesa/drivers/dri/i965/brw_context.h | 2 -- src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 ++---- 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 01b6a4a168..7834569761 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -116,8 +116,6 @@ */ -#define BRW_FALLBACK_DRAW (INTEL_FALLBACK_DRIVER << 0) - #define BRW_MAX_CURBE (32*16) struct brw_context; diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 375afadcbe..a3ff6c58d8 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -375,10 +375,9 @@ static void brw_prepare_vertices(struct brw_context *brw) * isn't an issue at this point. */ if (brw->vb.nr_enabled >= BRW_VEP_MAX) { - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); + intel->Fallback = 1; return; } - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); for (i = 0; i < brw->vb.nr_enabled; i++) { struct brw_vertex_element *input = brw->vb.enabled[i]; @@ -428,10 +427,9 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Position array not properly enabled: */ if (input->glarray->StrideB == 0) { - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_TRUE); + intel->Fallback = 1; return; } - FALLBACK(intel, BRW_FALLBACK_DRAW, GL_FALSE); interleave = input->glarray->StrideB; ptr = input->glarray->Ptr; -- cgit v1.2.3 From e9b17d6477f99838fc7f261ea1b8d47eea12f42f Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 27 Oct 2009 09:31:31 -0600 Subject: i965: be clear that the Fallback field is a boolean, not a bitfield --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 4 ++-- src/mesa/drivers/dri/i965/brw_fallback.c | 6 +++++- src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index a3ff6c58d8..0fefbd9d81 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -375,7 +375,7 @@ static void brw_prepare_vertices(struct brw_context *brw) * isn't an issue at this point. */ if (brw->vb.nr_enabled >= BRW_VEP_MAX) { - intel->Fallback = 1; + intel->Fallback = GL_TRUE; /* boolean, not bitfield */ return; } @@ -427,7 +427,7 @@ static void brw_prepare_vertices(struct brw_context *brw) /* Position array not properly enabled: */ if (input->glarray->StrideB == 0) { - intel->Fallback = 1; + intel->Fallback = GL_TRUE; /* boolean, not bitfield */ return; } diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index d27c6c24ca..562a17844b 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -133,7 +133,11 @@ const struct brw_tracked_state brw_check_fallback = { -/* Not used: +/** + * Called by the INTEL_FALLBACK() macro. + * NOTE: this is a no-op for the i965 driver. The brw->intel.Fallback + * field is treated as a boolean, not a bitmask. It's only set in a + * couple of places. */ void intelFallback( struct intel_context *intel, GLuint bit, GLboolean mode ) { diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index b817b741e7..ee447afa62 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -308,7 +308,7 @@ void brw_validate_state( struct brw_context *brw ) if (brw->state.dirty.brw & BRW_NEW_CONTEXT) brw_clear_batch_cache(brw); - brw->intel.Fallback = 0; + brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */ /* do prepare stage for all atoms */ for (i = 0; i < Elements(atoms); i++) { -- cgit v1.2.3 From 92e7c6a2581b5f612a84587500399bb00318c6f0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 28 Oct 2009 16:36:35 -0700 Subject: i965: Fix fallout from ARB_depth_clamp enablement that broke glDepthRange. If a backwards glDepthRange was supplied (as with the old Quake no-z-clearing hack), the hardware would have always clamped because we weren't clamping to the min of near/far and the max of near/far. Also, we shouldn't be clamping to near/far at all when not in depth clamp mode (this usually didn't matter since near/far are usually the same as the 0.0, 1.0 clamping you do for fixed-point depth). This should fix funny depth issues in PlaneShift, and fixes piglit depth-clamp-range --- src/mesa/drivers/dri/i965/brw_cc.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index 1088a7a607..5cca605c3f 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -44,9 +44,15 @@ static void prepare_cc_vp( struct brw_context *brw ) memset(&ccv, 0, sizeof(ccv)); - /* _NEW_VIEWPORT */ - ccv.min_depth = ctx->Viewport.Near; - ccv.max_depth = ctx->Viewport.Far; + /* _NEW_TRANSOFORM */ + if (ctx->Transform.DepthClamp) { + /* _NEW_VIEWPORT */ + ccv.min_depth = MIN2(ctx->Viewport.Near, ctx->Viewport.Far); + ccv.max_depth = MAX2(ctx->Viewport.Near, ctx->Viewport.Far); + } else { + ccv.min_depth = 0.0; + ccv.max_depth = 1.0; + } dri_bo_unreference(brw->cc.vp_bo); brw->cc.vp_bo = brw_cache_data( &brw->cache, BRW_CC_VP, &ccv, NULL, 0 ); @@ -54,7 +60,7 @@ static void prepare_cc_vp( struct brw_context *brw ) const struct brw_tracked_state brw_cc_vp = { .dirty = { - .mesa = _NEW_VIEWPORT, + .mesa = _NEW_VIEWPORT | _NEW_TRANSFORM, .brw = BRW_NEW_CONTEXT, .cache = 0 }, -- cgit v1.2.3 From 374447244165b3b79892cb6840a76ea4c2f21f1e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 29 Oct 2009 10:36:22 -0700 Subject: i965: Replace a MIN(MAX()) with CLAMP(). --- src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index dff466587a..416ffc9761 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -228,8 +228,8 @@ static void brw_update_sampler_state(struct wm_sampler_entry *key, */ sampler->ss0.base_level = U_FIXED(0, 1); - sampler->ss1.max_lod = U_FIXED(MIN2(MAX2(key->maxlod, 0), 13), 6); - sampler->ss1.min_lod = U_FIXED(MIN2(MAX2(key->minlod, 0), 13), 6); + sampler->ss1.max_lod = U_FIXED(CLAMP(key->maxlod, 0, 13), 6); + sampler->ss1.min_lod = U_FIXED(CLAMP(key->minlod, 0, 13), 6); sampler->ss2.default_color_pointer = sdc_bo->offset >> 5; /* reloc */ } -- cgit v1.2.3 From f8f40b53a6a4551630e25bfd7f6e12334bb0f3f8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 29 Oct 2009 11:52:28 -0700 Subject: i915: Implement min/max LOD clamping with the hardware. This gets us expected behavior for clamping between mipmap levels, and avoids relayout of textures for doing clamping. Fixes piglit lodclamp-between. --- src/mesa/drivers/dri/i915/i915_texstate.c | 12 ++++-- src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 13 ------- src/mesa/drivers/dri/intel/intel_context.h | 13 +++++++ src/mesa/drivers/dri/intel/intel_tex_validate.c | 48 ++++++++++++------------ 4 files changed, 46 insertions(+), 40 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 3a20e9c3ab..1397f04a59 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -27,6 +27,7 @@ #include "main/mtypes.h" #include "main/enums.h" +#include "main/macros.h" #include "intel_mipmap_tree.h" #include "intel_tex.h" @@ -200,10 +201,10 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) } state[I915_TEXREG_MS4] = - ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) | MS4_CUBE_FACE_ENA_MASK | - ((((intelObj->lastLevel - intelObj->firstLevel) * 4)) << - MS4_MAX_LOD_SHIFT) | ((firstImage->Depth - 1) << - MS4_VOLUME_DEPTH_SHIFT)); + ((((pitch / 4) - 1) << MS4_PITCH_SHIFT) | + MS4_CUBE_FACE_ENA_MASK | + (U_FIXED(CLAMP(tObj->MaxLod, 0.0, 11.0), 2) << MS4_MAX_LOD_SHIFT) | + ((firstImage->Depth - 1) << MS4_VOLUME_DEPTH_SHIFT)); { @@ -333,6 +334,9 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) (translate_wrap_mode(wr) << SS3_TCZ_ADDR_MODE_SHIFT)); state[I915_TEXREG_SS3] |= (unit << SS3_TEXTUREMAP_INDEX_SHIFT); + state[I915_TEXREG_SS3] |= (U_FIXED(CLAMP(tObj->MinLod, 0.0, 11.0), 4) << + SS3_MIN_LOD_SHIFT); + } /* convert border color from float to ubyte */ diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index 416ffc9761..0acb027431 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -66,19 +66,6 @@ static GLuint translate_wrap_mode( GLenum wrap ) } } - -static GLuint U_FIXED(GLfloat value, GLuint frac_bits) -{ - value *= (1<prim.flush) \ diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index d5b562f5e5..504993989a 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -5,6 +5,7 @@ #include "intel_batchbuffer.h" #include "intel_mipmap_tree.h" #include "intel_tex.h" +#include "intel_chipset.h" #define FILE_DEBUG_FLAG DEBUG_TEXTURE @@ -14,7 +15,8 @@ * GL_TEXTURE_MAX_LOD, GL_TEXTURE_BASE_LEVEL, and GL_TEXTURE_MAX_LEVEL. */ static void -intel_calculate_first_last_level(struct intel_texture_object *intelObj) +intel_calculate_first_last_level(struct intel_context *intel, + struct intel_texture_object *intelObj) { struct gl_texture_object *tObj = &intelObj->base; const struct gl_texture_image *const baseImage = @@ -40,27 +42,27 @@ intel_calculate_first_last_level(struct intel_texture_object *intelObj) firstLevel = lastLevel = tObj->BaseLevel; } else { -#ifdef I915 - firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5); - firstLevel = MAX2(firstLevel, tObj->BaseLevel); - firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); - lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5); - lastLevel = MAX2(lastLevel, tObj->BaseLevel); - lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); - lastLevel = MIN2(lastLevel, tObj->MaxLevel); - lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ -#else - /* Currently not taking min/max lod into account here, those - * values are programmed as sampler state elsewhere and we - * upload the same mipmap levels regardless. Not sure if - * this makes sense as it means it isn't possible for the app - * to use min/max lod to reduce texture memory pressure: - */ - firstLevel = tObj->BaseLevel; - lastLevel = MIN2(tObj->BaseLevel + baseImage->MaxLog2, - tObj->MaxLevel); - lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ -#endif + if (!IS_9XX(intel->intelScreen->deviceID)) { + firstLevel = tObj->BaseLevel + (GLint) (tObj->MinLod + 0.5); + firstLevel = MAX2(firstLevel, tObj->BaseLevel); + firstLevel = MIN2(firstLevel, tObj->BaseLevel + baseImage->MaxLog2); + lastLevel = tObj->BaseLevel + (GLint) (tObj->MaxLod + 0.5); + lastLevel = MAX2(lastLevel, tObj->BaseLevel); + lastLevel = MIN2(lastLevel, tObj->BaseLevel + baseImage->MaxLog2); + lastLevel = MIN2(lastLevel, tObj->MaxLevel); + lastLevel = MAX2(firstLevel, lastLevel); /* need at least one level */ + } else { + /* Min/max LOD are taken into account in sampler state. We don't + * want to re-layout textures just because clamping has been applied + * since it means a bunch of blitting around and probably no memory + * savings (since we have to keep the other levels around anyway). + */ + firstLevel = tObj->BaseLevel; + lastLevel = MIN2(tObj->BaseLevel + baseImage->MaxLog2, + tObj->MaxLevel); + /* need at least one level */ + lastLevel = MAX2(firstLevel, lastLevel); + } } break; case GL_TEXTURE_RECTANGLE_NV: @@ -135,7 +137,7 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) /* What levels must the tree include at a minimum? */ - intel_calculate_first_last_level(intelObj); + intel_calculate_first_last_level(intel, intelObj); firstImage = intel_texture_image(intelObj->base.Image[0][intelObj->firstLevel]); -- cgit v1.2.3 From a0959bcee5df4272db40a56c468f8c7cc299d5ef Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 14:16:18 -0600 Subject: i965: minor code reformatting --- src/mesa/drivers/dri/i965/brw_wm_fp.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 4e3edfbbff..4ef437e2fa 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -971,13 +971,12 @@ static void emit_fb_write( struct brw_wm_compile *c ) if (brw->state.nr_color_regions > 1) { for (i = 0 ; i < brw->state.nr_color_regions; i++) { outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_DATA0 + i); - last_inst = inst = emit_op(c, - WM_FB_WRITE, dst_mask(dst_undef(),0), 0, - outcolor, payload_r0_depth, outdepth); + last_inst = inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(), 0), + 0, outcolor, payload_r0_depth, outdepth); inst->Aux = (i<<1); if (c->fp_fragcolor_emitted) { outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_COLOR); - last_inst = inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(),0), + last_inst = inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(), 0), 0, outcolor, payload_r0_depth, outdepth); inst->Aux = (i<<1); } -- cgit v1.2.3 From a8d233e509a2c1aada7cd4e83b126ba06cb90565 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 14:29:55 -0600 Subject: i965: use macros to get/set prog_instruction::Aux field This makes things a bit easier to remember/understand. --- src/mesa/drivers/dri/i965/brw_wm.h | 6 ++++++ src/mesa/drivers/dri/i965/brw_wm_fp.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_pass0.c | 4 ++-- 4 files changed, 14 insertions(+), 8 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 872b1f3ecf..f13a958a44 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -271,6 +271,12 @@ struct brw_wm_compile { }; +/** Bits for prog_instruction::Aux field */ +#define INST_AUX_EOT 0x1 +#define INST_AUX_TARGET(T) (T << 1) +#define INST_AUX_GET_TARGET(AUX) ((AUX) >> 1) + + GLuint brw_wm_nr_args( GLuint opcode ); GLuint brw_wm_is_scalar_result( GLuint opcode ); diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 4ef437e2fa..d33fd9abed 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -973,15 +973,15 @@ static void emit_fb_write( struct brw_wm_compile *c ) outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_DATA0 + i); last_inst = inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(), 0), 0, outcolor, payload_r0_depth, outdepth); - inst->Aux = (i<<1); + inst->Aux = INST_AUX_TARGET(i); if (c->fp_fragcolor_emitted) { outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_COLOR); last_inst = inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(), 0), 0, outcolor, payload_r0_depth, outdepth); - inst->Aux = (i<<1); + inst->Aux = INST_AUX_TARGET(i); } } - last_inst->Aux |= 1; //eot + last_inst->Aux |= INST_AUX_EOT; } else { /* if gl_FragData[0] is written, use it, else use gl_FragColor */ @@ -992,7 +992,7 @@ static void emit_fb_write( struct brw_wm_compile *c ) inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(),0), 0, outcolor, payload_r0_depth, outdepth); - inst->Aux = 1|(0<<1); + inst->Aux = INST_AUX_EOT | INST_AUX_TARGET(0); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index c9fe1dd8ad..28d6d4eba5 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -841,8 +841,8 @@ static void emit_fb_write(struct brw_wm_compile *c, nr += 2; } - target = inst->Aux >> 1; - eot = inst->Aux & 1; + target = INST_AUX_GET_TARGET(inst->Aux); + eot = inst->Aux & INST_AUX_EOT; fire_fb_write(c, 0, nr, target, eot); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass0.c b/src/mesa/drivers/dri/i965/brw_wm_pass0.c index 6279258339..602b1351ef 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass0.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass0.c @@ -322,8 +322,8 @@ translate_insn(struct brw_wm_compile *c, out->tex_unit = inst->TexSrcUnit; out->tex_idx = inst->TexSrcTarget; out->tex_shadow = inst->TexShadow; - out->eot = inst->Aux & 1; - out->target = inst->Aux >> 1; + out->eot = inst->Aux & INST_AUX_EOT; + out->target = INST_AUX_GET_TARGET(inst->Aux); /* Args: */ -- cgit v1.2.3 From 9ef33b86855c4d000271774030bd1b19b6d79687 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 14:53:53 -0600 Subject: i965: don't use context state in emit_fb_write() Put the state that we care about in the hash key. Issue spotted by Keith Whitwell. --- src/mesa/drivers/dri/i965/brw_wm.c | 2 ++ src/mesa/drivers/dri/i965/brw_wm.h | 1 + src/mesa/drivers/dri/i965/brw_wm_fp.c | 4 ++-- 3 files changed, 5 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 5a2ac1a651..eeb25980fa 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -325,6 +325,8 @@ static void brw_wm_populate_key( struct brw_context *brw, key->drawable_height = brw->intel.driDrawable->h; } + key->nr_color_regions = brw->state.nr_color_regions; + /* CACHE_NEW_VS_PROG */ key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS; diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index f13a958a44..d0f30607d0 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -67,6 +67,7 @@ struct brw_wm_prog_key { GLuint flat_shade:1; GLuint linear_color:1; /**< linear interpolation vs perspective interp */ GLuint runtime_check_aads_emit:1; + GLuint nr_color_regions:2; GLbitfield proj_attrib_mask; /**< one bit per fragment program attribute */ GLuint shadowtex_mask:16; diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index d33fd9abed..9a0aea872b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -968,8 +968,8 @@ static void emit_fb_write( struct brw_wm_compile *c ) /* The inst->Aux field is used for FB write target and the EOT marker */ - if (brw->state.nr_color_regions > 1) { - for (i = 0 ; i < brw->state.nr_color_regions; i++) { + if (c->key.nr_color_regions > 1) { + for (i = 0 ; i < c->key.nr_color_regions; i++) { outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_DATA0 + i); last_inst = inst = emit_op(c, WM_FB_WRITE, dst_mask(dst_undef(), 0), 0, outcolor, payload_r0_depth, outdepth); -- cgit v1.2.3 From 7648c80ac8dd0631c5a0f86ad03347675a48eee6 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 15:00:18 -0600 Subject: i965: remove unused var --- src/mesa/drivers/dri/i965/brw_wm_fp.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 9a0aea872b..53fdd06f42 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -964,7 +964,6 @@ static void emit_fb_write( struct brw_wm_compile *c ) GLuint i; struct prog_instruction *inst, *last_inst; - struct brw_context *brw = c->func.brw; /* The inst->Aux field is used for FB write target and the EOT marker */ -- cgit v1.2.3 From 198ec96d364dabd82952a451eeda7937db383f0d Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 15:01:02 -0600 Subject: i965: define, use BRW_MAX_DRAW_BUFFERS i965 might support more than 4 color draw buffers. But if not, this protects from breakage if the Mesa limit is raised. --- src/mesa/drivers/dri/i965/brw_context.c | 1 + src/mesa/drivers/dri/i965/brw_context.h | 9 ++++++--- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index c300c33adc..48685c087b 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -105,6 +105,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline; + ctx->Const.MaxDrawBuffers = BRW_MAX_DRAW_BUFFERS; ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT; ctx->Const.MaxTextureCoordUnits = 8; /* Mesa limit */ ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits, diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 7834569761..59f9475b5a 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -252,20 +252,23 @@ struct brw_vs_ouput_sizes { /** Number of texture sampler units */ #define BRW_MAX_TEX_UNIT 16 +/** Max number of render targets in a shader */ +#define BRW_MAX_DRAW_BUFFERS 4 + /** * Size of our surface binding table for the WM. * This contains pointers to the drawing surfaces and current texture * objects and shader constant buffers (+2). */ -#define BRW_WM_MAX_SURF (MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1) +#define BRW_WM_MAX_SURF (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1) /** * Helpers to convert drawing buffers, textures and constant buffers * to surface binding table indexes, for WM. */ #define SURF_INDEX_DRAW(d) (d) -#define SURF_INDEX_FRAG_CONST_BUFFER (MAX_DRAW_BUFFERS) -#define SURF_INDEX_TEXTURE(t) (MAX_DRAW_BUFFERS + 1 + (t)) +#define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS) +#define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 1 + (t)) /** * Size of surface binding table for the VS. diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 73ae06eea1..3b2c6a25be 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -709,7 +709,7 @@ static void prepare_wm_surfaces(struct brw_context *brw ) } old_nr_surfaces = brw->wm.nr_surfaces; - brw->wm.nr_surfaces = MAX_DRAW_BUFFERS; + brw->wm.nr_surfaces = BRW_MAX_DRAW_BUFFERS; if (brw->wm.surf_bo[SURF_INDEX_FRAG_CONST_BUFFER] != NULL) brw->wm.nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1; -- cgit v1.2.3 From 861fec163c1ae7e431956db0a08989d841e2b74e Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 15:29:41 -0600 Subject: i965: avoid shader translation on window resize If the fragment shader doesn't use FRAG_ATTRIB_WPOS (gl_FragCoord) we don't need to worry about the window size and origin in brw_wm_populate_key(). This avoids re-generating the i965 shader code when a window is resized. Issue spotted by Keith Whitwell. --- src/mesa/drivers/dri/i965/brw_wm.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index eeb25980fa..964ee104c2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -308,6 +308,9 @@ static void brw_wm_populate_key( struct brw_context *brw, * from the incoming screen origin relative position we get as part of our * payload. * + * This is only needed for the WM_WPOSXY opcode when the fragment program + * uses the gl_FragCoord input. + * * We could avoid recompiling by including this as a constant referenced by * our program, but if we were to do that it would also be nice to handle * getting that constant updated at batchbuffer submit time (when we @@ -316,13 +319,15 @@ static void brw_wm_populate_key( struct brw_context *brw, * just avoid using this as key data if the program doesn't use * fragment.position. * - * This pretty much becomes moot with DRI2 and redirected buffers anyway, - * as our origins will always be zero then. + * For DRI2 the origin_x/y will always be (0,0) but we still need the + * drawable height in order to invert the Y axis. */ - if (brw->intel.driDrawable != NULL) { - key->origin_x = brw->intel.driDrawable->x; - key->origin_y = brw->intel.driDrawable->y; - key->drawable_height = brw->intel.driDrawable->h; + if (fp->program.Base.InputsRead & FRAG_BIT_WPOS) { + if (brw->intel.driDrawable != NULL) { + key->origin_x = brw->intel.driDrawable->x; + key->origin_y = brw->intel.driDrawable->y; + key->drawable_height = brw->intel.driDrawable->h; + } } key->nr_color_regions = brw->state.nr_color_regions; -- cgit v1.2.3 From 035b21f365f563cba9bf9b8cb4fef613ceb9d3ac Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 15:57:22 -0600 Subject: i965: make brw_wm_prog_key a little smaller GLushort is big enough for the swizzle and origin fields. The key could probably be made smaller still by re-ordering things. I'll hold off on that until after the outputswritten64 branch is merged. The key will get a little larger again with the GLbitfield64 fields. --- src/mesa/drivers/dri/i965/brw_wm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index d0f30607d0..dd4644fc36 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -74,11 +74,11 @@ struct brw_wm_prog_key { GLuint yuvtex_mask:16; GLuint yuvtex_swap_mask:16; /* UV swaped */ - GLuint tex_swizzles[BRW_MAX_TEX_UNIT]; + GLushort tex_swizzles[BRW_MAX_TEX_UNIT]; GLuint program_string_id:32; - GLuint origin_x, origin_y; - GLuint drawable_height; + GLushort origin_x, origin_y; + GLushort drawable_height; GLuint vp_outputs_written; }; -- cgit v1.2.3 From 26d22b094bb7b2f37d4bc8edfeb1b2a9a1c96d88 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 16:02:35 -0600 Subject: i965: make brw_sf_prog_key::sprite_origin_lower_left one bit Shrinks size of key to 8 bytes from 12. Note that progs/demos/spriteblast.c is still broken. --- src/mesa/drivers/dri/i965/brw_sf.c | 2 +- src/mesa/drivers/dri/i965/brw_sf.h | 4 ++-- src/mesa/drivers/dri/i965/brw_sf_emit.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c index e1c2c7777b..f350cbd74e 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.c +++ b/src/mesa/drivers/dri/i965/brw_sf.c @@ -161,7 +161,7 @@ static void upload_sf_prog(struct brw_context *brw) } key.do_point_sprite = ctx->Point.PointSprite; - key.SpriteOrigin = ctx->Point.SpriteOrigin; + key.sprite_origin_lower_left = (ctx->Point.SpriteOrigin == GL_LOWER_LEFT); /* _NEW_LIGHT */ key.do_flat_shading = (ctx->Light.ShadeModel == GL_FLAT); key.do_twoside_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide); diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h index 6426b6df9f..e415bbd775 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.h +++ b/src/mesa/drivers/dri/i965/brw_sf.h @@ -52,8 +52,8 @@ struct brw_sf_prog_key { GLuint frontface_ccw:1; GLuint do_point_sprite:1; GLuint linear_color:1; /**< linear interp vs. perspective interp */ - GLuint pad:25; - GLenum SpriteOrigin; + GLuint sprite_origin_lower_left:1; + GLuint pad:24; }; struct brw_sf_point_tex { diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c index ca8f97f9f9..561fcd501b 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_emit.c +++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c @@ -551,7 +551,7 @@ void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate) BRW_MATH_DATA_SCALAR, BRW_MATH_PRECISION_FULL); - if (c->key.SpriteOrigin == GL_LOWER_LEFT) { + if (c->key.sprite_origin_lower_left) { brw_MUL(p, c->m1Cx, c->tmp, c->inv_w[0]); brw_MOV(p, vec1(suboffset(c->m1Cx, 1)), brw_imm_f(0.0)); brw_MUL(p, c->m2Cy, c->tmp, negate(c->inv_w[0])); @@ -570,7 +570,7 @@ void brw_emit_point_sprite_setup( struct brw_sf_compile *c, GLboolean allocate) { brw_set_predicate_control_flag_value(p, pc); if (tex->CoordReplace) { - if (c->key.SpriteOrigin == GL_LOWER_LEFT) { + if (c->key.sprite_origin_lower_left) { brw_MUL(p, c->m3C0, c->inv_w[0], brw_imm_f(1.0)); brw_MOV(p, vec1(suboffset(c->m3C0, 0)), brw_imm_f(0.0)); } -- cgit v1.2.3 From 217a40d8d92d377e73ed1ab5a326703fab779dd1 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 16:06:30 -0600 Subject: i965: indentation fix --- src/mesa/drivers/dri/i965/brw_sf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_sf.h b/src/mesa/drivers/dri/i965/brw_sf.h index e415bbd775..e835229a1d 100644 --- a/src/mesa/drivers/dri/i965/brw_sf.h +++ b/src/mesa/drivers/dri/i965/brw_sf.h @@ -57,7 +57,7 @@ struct brw_sf_prog_key { }; struct brw_sf_point_tex { - GLboolean CoordReplace; + GLboolean CoordReplace; }; struct brw_sf_compile { -- cgit v1.2.3 From 4a253431abf43a0638afb43605b44a8742b72a60 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Thu, 29 Oct 2009 19:12:50 -0600 Subject: intel: update intel_create_renderbuffer(format), add XRGB support Pass a gl_format to intel_create_renderbuffer() instead of GLenum. Add cases for MESA_FORMAT_XRGB8888 textures and renderbuffers. However, we don't yet create any renderbuffers or textures with that format. It seems the default alpha value is zero instead of one. Need to investigate that first. --- src/mesa/drivers/dri/i915/i830_texstate.c | 2 ++ src/mesa/drivers/dri/i915/i830_vtbl.c | 1 + src/mesa/drivers/dri/i915/i915_texstate.c | 2 ++ src/mesa/drivers/dri/i915/i915_vtbl.c | 1 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 ++++ src/mesa/drivers/dri/intel/intel_blit.c | 1 + src/mesa/drivers/dri/intel/intel_fbo.c | 44 +++++++++--------------- src/mesa/drivers/dri/intel/intel_fbo.h | 2 +- src/mesa/drivers/dri/intel/intel_pixel_draw.c | 2 +- src/mesa/drivers/dri/intel/intel_screen.c | 14 ++++---- src/mesa/drivers/dri/intel/intel_span.c | 15 ++++++++ src/mesa/drivers/dri/intel/intel_tex_format.c | 2 ++ 12 files changed, 57 insertions(+), 36 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 28263fbe3c..f4bbb53b86 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -59,6 +59,8 @@ translate_texture_format(GLuint mesa_format, GLuint internal_format) return MAPSURF_32BIT | MT_32BIT_XRGB8888; else return MAPSURF_32BIT | MT_32BIT_ARGB8888; + case MESA_FORMAT_XRGB8888: + return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: return (MAPSURF_422 | MT_422_YCRCB_NORMAL); case MESA_FORMAT_YCBCR: diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 22f8bc7f19..4133696129 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -647,6 +647,7 @@ i830_state_draw_region(struct intel_context *intel, if (irb != NULL) { switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; break; case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index bea47f5af8..d6689af53f 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -60,6 +60,8 @@ translate_texture_format(gl_format mesa_format, GLuint internal_format, return MAPSURF_32BIT | MT_32BIT_XRGB8888; else return MAPSURF_32BIT | MT_32BIT_ARGB8888; + case MESA_FORMAT_XRGB8888: + return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: return (MAPSURF_422 | MT_422_YCRCB_NORMAL); case MESA_FORMAT_YCBCR: diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index d84df1a142..3c1b2dd0b0 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -589,6 +589,7 @@ i915_state_draw_region(struct intel_context *intel, if (irb != NULL) { switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; break; case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 3b2c6a25be..0bf735c0f2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -96,7 +96,11 @@ static GLuint translate_tex_format( gl_format mesa_format, else return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + case MESA_FORMAT_XRGB8888: + return BRW_SURFACEFORMAT_B8G8R8X8_UNORM; + case MESA_FORMAT_RGBA8888_REV: + _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()"); if (internal_format == GL_RGB) return BRW_SURFACEFORMAT_R8G8B8X8_UNORM; else @@ -531,6 +535,9 @@ brw_update_renderbuffer_surface(struct brw_context *brw, case MESA_FORMAT_ARGB8888: key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; + case MESA_FORMAT_XRGB8888: + key.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; + break; case MESA_FORMAT_RGB565: key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; break; diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 55d97a0f76..817223da41 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -498,6 +498,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: clearVal = intel->ClearColor8888; break; case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index d006389f5a..9c780d40cc 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -292,7 +292,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *rb, * not a user-created renderbuffer. */ struct intel_renderbuffer * -intel_create_renderbuffer(GLenum intFormat) +intel_create_renderbuffer(gl_format format) { GET_CURRENT_CONTEXT(ctx); @@ -308,48 +308,30 @@ intel_create_renderbuffer(GLenum intFormat) _mesa_init_renderbuffer(&irb->Base, name); irb->Base.ClassID = INTEL_RB_CLASS; - switch (intFormat) { - case GL_RGB5: - irb->Base.Format = MESA_FORMAT_RGB565; + switch (format) { + case MESA_FORMAT_RGB565: irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_RGB565; break; - case GL_RGB8: - irb->Base.Format = MESA_FORMAT_ARGB8888; /* XXX: NEED XRGB8888 */ + case MESA_FORMAT_XRGB8888: irb->Base._BaseFormat = GL_RGB; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: NEED XRGB8888 */ break; - case GL_RGBA8: - irb->Base.Format = MESA_FORMAT_ARGB8888; + case MESA_FORMAT_ARGB8888: irb->Base._BaseFormat = GL_RGBA; irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; - break; - case GL_STENCIL_INDEX8_EXT: - irb->Base.Format = MESA_FORMAT_S8_Z24; - irb->Base._BaseFormat = GL_STENCIL_INDEX; - irb->Base.DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_S8_Z24; break; - case GL_DEPTH_COMPONENT16: - irb->Base.Format = MESA_FORMAT_Z16; + case MESA_FORMAT_Z16: irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DataType = GL_UNSIGNED_SHORT; - irb->texformat = MESA_FORMAT_Z16; break; - case GL_DEPTH_COMPONENT24: - irb->Base.Format = MESA_FORMAT_S8_Z24; + case MESA_FORMAT_X8_Z24: irb->Base._BaseFormat = GL_DEPTH_COMPONENT; irb->Base.DataType = GL_UNSIGNED_INT; - irb->texformat = MESA_FORMAT_S8_Z24; break; - case GL_DEPTH24_STENCIL8_EXT: - irb->Base.Format = MESA_FORMAT_S8_Z24; + case MESA_FORMAT_S8_Z24: irb->Base._BaseFormat = GL_DEPTH_STENCIL; irb->Base.DataType = GL_UNSIGNED_INT_24_8_EXT; - irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(NULL, @@ -358,7 +340,10 @@ intel_create_renderbuffer(GLenum intFormat) return NULL; } - irb->Base.InternalFormat = intFormat; + assert(irb->Base._BaseFormat == _mesa_get_format_base_format(format)); + irb->Base.Format = format; + irb->Base.InternalFormat = irb->Base._BaseFormat; + irb->texformat = format; /* intel-specific methods */ irb->Base.Delete = intel_delete_renderbuffer; @@ -442,6 +427,10 @@ intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGBA8 texture OK\n"); } + else if (texImage->TexFormat == MESA_FORMAT_XRGB8888) { + irb->Base.DataType = GL_UNSIGNED_BYTE; + DBG("Render to XGBA8 texture OK\n"); + } else if (texImage->TexFormat == MESA_FORMAT_RGB565) { irb->Base.DataType = GL_UNSIGNED_BYTE; DBG("Render to RGB5 texture OK\n"); @@ -644,6 +633,7 @@ intel_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) switch (irb->texformat) { case MESA_FORMAT_ARGB8888: + case MESA_FORMAT_XRGB8888: case MESA_FORMAT_RGB565: case MESA_FORMAT_ARGB1555: case MESA_FORMAT_ARGB4444: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index e0584e3494..50a8a95985 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -115,7 +115,7 @@ intel_renderbuffer_set_region(struct intel_renderbuffer *irb, extern struct intel_renderbuffer * -intel_create_renderbuffer(GLenum intFormat); +intel_create_renderbuffer(gl_format format); extern void diff --git a/src/mesa/drivers/dri/intel/intel_pixel_draw.c b/src/mesa/drivers/dri/intel/intel_pixel_draw.c index 5ffa847fd4..9b382e3622 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_draw.c @@ -169,7 +169,7 @@ intel_stencil_drawpixels(GLcontext * ctx, * buffer. */ depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); - irb = intel_create_renderbuffer(GL_RGBA8); + irb = intel_create_renderbuffer(MESA_FORMAT_ARGB8888); rb = &irb->Base; irb->Base.Width = depth_irb->Base.Width; irb->Base.Height = depth_irb->Base.Height; diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 41342ddcae..62c322b4ed 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -349,7 +349,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, else { GLboolean swStencil = (mesaVis->stencilBits > 0 && mesaVis->depthBits != 24); - GLenum rgbFormat; + gl_format rgbFormat; struct intel_framebuffer *intel_fb = CALLOC_STRUCT(intel_framebuffer); @@ -359,11 +359,11 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, _mesa_initialize_framebuffer(&intel_fb->Base, mesaVis); if (mesaVis->redBits == 5) - rgbFormat = GL_RGB5; + rgbFormat = MESA_FORMAT_RGB565; else if (mesaVis->alphaBits == 0) - rgbFormat = GL_RGB8; + rgbFormat = MESA_FORMAT_ARGB8888; /* XXX change to XRGB someday */ else - rgbFormat = GL_RGBA8; + rgbFormat = MESA_FORMAT_ARGB8888; /* setup the hardware-based renderbuffers */ intel_fb->color_rb[0] = intel_create_renderbuffer(rgbFormat); @@ -382,7 +382,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, if (mesaVis->stencilBits == 8) { /* combined depth/stencil buffer */ struct intel_renderbuffer *depthStencilRb - = intel_create_renderbuffer(GL_DEPTH24_STENCIL8_EXT); + = intel_create_renderbuffer(MESA_FORMAT_S8_Z24); /* note: bind RB to two attachment points */ _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthStencilRb->Base); @@ -390,7 +390,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, &depthStencilRb->Base); } else { struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(GL_DEPTH_COMPONENT24); + = intel_create_renderbuffer(MESA_FORMAT_X8_Z24); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } @@ -398,7 +398,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, else if (mesaVis->depthBits == 16) { /* just 16-bit depth buffer, no hw stencil */ struct intel_renderbuffer *depthRb - = intel_create_renderbuffer(GL_DEPTH_COMPONENT16); + = intel_create_renderbuffer(MESA_FORMAT_Z16); _mesa_add_renderbuffer(&intel_fb->Base, BUFFER_DEPTH, &depthRb->Base); } diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index a36c077fbd..b0484a9959 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -651,8 +651,23 @@ intel_set_span_functions(struct intel_context *intel, break; } break; + case MESA_FORMAT_XRGB8888: + switch (tiling) { + case I915_TILING_NONE: + default: + intelInitPointers_xRGB8888(rb); + break; + case I915_TILING_X: + intel_XTile_InitPointers_xRGB8888(rb); + break; + case I915_TILING_Y: + intel_YTile_InitPointers_xRGB8888(rb); + break; + } + break; case MESA_FORMAT_ARGB8888: if (0 /*rb->AlphaBits == 0*/) { /* XXX: Need xRGB8888 Mesa format */ + /* XXX remove this code someday when we enable XRGB surfaces */ /* 8888 RGBx */ switch (tiling) { case I915_TILING_NONE: diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index eca0f6d572..f37a545c7f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -50,6 +50,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, if (format == GL_RGB && type == GL_UNSIGNED_SHORT_5_6_5) { return MESA_FORMAT_RGB565; } + /* XXX use MESA_FORMAT_XRGB8888 someday */ return do32bpt ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_RGB565; case GL_RGBA8: @@ -69,6 +70,7 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_RGB10: case GL_RGB12: case GL_RGB16: + /* XXX use MESA_FORMAT_XRGB8888 someday */ return MESA_FORMAT_ARGB8888; case GL_RGB5: -- cgit v1.2.3 From 2c30ee9bd69ed606b984c051748a7cdb34905eeb Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 30 Oct 2009 13:20:13 -0700 Subject: i965: Fix BRW_WM_MAX_INSN to reflect current limits. Part of fixing bug #24355. --- src/mesa/drivers/dri/i965/brw_wm.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index dd4644fc36..47aa4da306 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -154,13 +154,12 @@ struct brw_wm_instruction { }; -#define BRW_WM_MAX_INSN (MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3) +#define BRW_WM_MAX_INSN (MAX_PROGRAM_INSTRUCTIONS*3 + FRAG_ATTRIB_MAX + 3) #define BRW_WM_MAX_GRF 128 /* hardware limit */ #define BRW_WM_MAX_VREG (BRW_WM_MAX_INSN * 4) #define BRW_WM_MAX_REF (BRW_WM_MAX_INSN * 12) #define BRW_WM_MAX_PARAM 256 #define BRW_WM_MAX_CONST 256 -#define BRW_WM_MAX_KILLS MAX_NV_FRAGMENT_PROGRAM_INSTRUCTIONS #define BRW_WM_MAX_SUBROUTINE 16 -- cgit v1.2.3 From cb132406ded760a622513cd1ab86bf83bb945671 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 30 Oct 2009 13:28:44 -0700 Subject: i965: Add an index assert on get_fp_inst array like other compiler arrays. --- src/mesa/drivers/dri/i965/brw_wm_fp.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 53fdd06f42..0e86d75dea 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -181,6 +181,7 @@ static void release_temp( struct brw_wm_compile *c, struct prog_dst_register tem static struct prog_instruction *get_fp_inst(struct brw_wm_compile *c) { + assert(c->nr_fp_insns < BRW_WM_MAX_INSN); return &c->prog_instructions[c->nr_fp_insns++]; } -- cgit v1.2.3 From bcbfda71b03303d3f008a6f3cf8cb7d9667bf8d2 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 2 Nov 2009 12:40:04 -0700 Subject: intel: avoid unnecessary front buffer flushing/updating Before, if we just called glXMakeCurrent() and didn't render anything we'd still trigger a flushFrontBuffer() call. Now only set the intel->front_buffer_dirty field at state validation time just before we draw something. NOTE: additional calls to intel_check_front_buffer_rendering() might be needed if I missed some rendering paths. --- src/mesa/drivers/dri/i915/intel_tris.c | 1 + src/mesa/drivers/dri/i965/brw_state_upload.c | 3 +++ src/mesa/drivers/dri/intel/intel_buffers.c | 21 +++++++++++++++++++-- src/mesa/drivers/dri/intel/intel_buffers.h | 2 ++ src/mesa/drivers/dri/intel/intel_span.c | 2 ++ 5 files changed, 27 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index c3cbba8404..bc527aae47 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -1088,6 +1088,7 @@ intelRenderStart(GLcontext * ctx) { struct intel_context *intel = intel_context(ctx); + intel_check_front_buffer_rendering(intel); intel->vtbl.render_start(intel_context(ctx)); intel->vtbl.emit_state(intel); } diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index ee447afa62..f4283bda1b 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -34,6 +34,7 @@ #include "brw_context.h" #include "brw_state.h" #include "intel_batchbuffer.h" +#include "intel_buffers.h" /* This is used to initialize brw->state.atoms[]. We could use this * list directly except for a single atom, brw_constant_buffer, which @@ -324,6 +325,8 @@ void brw_validate_state( struct brw_context *brw ) } } + intel_check_front_buffer_rendering(intel); + /* Make sure that the textures which are referenced by the current * brw fragment program are actually present/valid. * If this fails, we can experience GPU lock-ups. diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index 639ffa6437..6b12d484d8 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -132,6 +132,25 @@ intel_get_cliprects(struct intel_context *intel, } +/** + * Check if we're about to draw into the front color buffer. + * If so, set the intel->front_buffer_dirty field to true. + */ +void +intel_check_front_buffer_rendering(struct intel_context *intel) +{ + const struct gl_framebuffer *fb = intel->ctx.DrawBuffer; + if (fb->Name == 0) { + /* drawing to window system buffer */ + if (fb->_NumColorDrawBuffers > 0) { + if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { + intel->front_buffer_dirty = GL_TRUE; + } + } + } +} + + /** * Update the hardware state for drawing into a window or framebuffer object. * @@ -202,8 +221,6 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) intel_batchbuffer_flush(intel->batch); intel->front_cliprects = GL_TRUE; colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT); - - intel->front_buffer_dirty = GL_TRUE; } else { if (!intel->constant_cliprect && intel->front_cliprects) diff --git a/src/mesa/drivers/dri/intel/intel_buffers.h b/src/mesa/drivers/dri/intel/intel_buffers.h index 6069d38e9e..d7800f2ca2 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.h +++ b/src/mesa/drivers/dri/intel/intel_buffers.h @@ -45,6 +45,8 @@ extern struct intel_region *intel_readbuf_region(struct intel_context *intel); extern struct intel_region *intel_drawbuf_region(struct intel_context *intel); +extern void intel_check_front_buffer_rendering(struct intel_context *intel); + extern void intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb); extern void intelInitBufferFuncs(struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 638e05f2ad..bab13e3665 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -501,6 +501,8 @@ intel_map_unmap_framebuffer(struct intel_context *intel, else intel_renderbuffer_unmap(intel, fb->_StencilBuffer->Wrapped); } + + intel_check_front_buffer_rendering(intel); } /** -- cgit v1.2.3 From 8e0f40d28777f1ae599a95312788fe29a0515a0d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 3 Nov 2009 17:18:36 -0800 Subject: intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing. This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary. --- src/mesa/drivers/dri/i915/i830_vtbl.c | 10 -------- src/mesa/drivers/dri/i915/i915_vtbl.c | 7 ------ src/mesa/drivers/dri/i965/brw_draw.c | 8 ++---- src/mesa/drivers/dri/i965/brw_vtbl.c | 15 ------------ src/mesa/drivers/dri/intel/intel_batchbuffer.c | 34 ++++++++++++++++++++++++-- src/mesa/drivers/dri/intel/intel_batchbuffer.h | 12 +++------ src/mesa/drivers/dri/intel/intel_context.h | 2 -- 7 files changed, 37 insertions(+), 51 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 4133696129..a6f554701e 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -719,15 +719,6 @@ i830_new_batch(struct intel_context *intel) assert(!intel->no_batch_wrap); } - - -static GLuint -i830_flush_cmd(void) -{ - return MI_FLUSH | FLUSH_MAP_CACHE; -} - - static void i830_assert_not_dirty( struct intel_context *intel ) { @@ -753,7 +744,6 @@ i830InitVtbl(struct i830_context *i830) i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state; i830->intel.vtbl.set_draw_region = i830_set_draw_region; i830->intel.vtbl.update_texture_state = i830UpdateTextureState; - i830->intel.vtbl.flush_cmd = i830_flush_cmd; i830->intel.vtbl.render_start = i830_render_start; i830->intel.vtbl.render_prevalidate = i830_render_prevalidate; i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty; diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 3c1b2dd0b0..77ba8d5581 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -672,12 +672,6 @@ i915_new_batch(struct intel_context *intel) assert(!intel->no_batch_wrap); } -static GLuint -i915_flush_cmd(void) -{ - return MI_FLUSH | FLUSH_MAP_CACHE; -} - static void i915_assert_not_dirty( struct intel_context *intel ) { @@ -699,7 +693,6 @@ i915InitVtbl(struct i915_context *i915) i915->intel.vtbl.render_prevalidate = i915_render_prevalidate; i915->intel.vtbl.set_draw_region = i915_set_draw_region; i915->intel.vtbl.update_texture_state = i915UpdateTextureState; - i915->intel.vtbl.flush_cmd = i915_flush_cmd; i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty; i915->intel.vtbl.finish_batch = intel_finish_vb; } diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 44bb7bd588..8bcb6083f7 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -153,18 +153,14 @@ static void brw_emit_prim(struct brw_context *brw, * the besides the draw code. */ if (intel->always_flush_cache) { - BEGIN_BATCH(1, IGNORE_CLIPRECTS); - OUT_BATCH(intel->vtbl.flush_cmd()); - ADVANCE_BATCH(); + intel_batchbuffer_emit_mi_flush(intel->batch); } if (prim_packet.verts_per_instance) { intel_batchbuffer_data( brw->intel.batch, &prim_packet, sizeof(prim_packet), LOOP_CLIPRECTS); } if (intel->always_flush_cache) { - BEGIN_BATCH(1, IGNORE_CLIPRECTS); - OUT_BATCH(intel->vtbl.flush_cmd()); - ADVANCE_BATCH(); + intel_batchbuffer_emit_mi_flush(intel->batch); } brw->no_batch_wrap = GL_FALSE; diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 124fde25fe..114e6bd018 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -175,20 +175,6 @@ static void brw_note_fence( struct intel_context *intel, GLuint fence ) brw_context(&intel->ctx)->state.dirty.brw |= BRW_NEW_FENCE; } -/* called from intelWaitForIdle() and intelFlush() - * - * For now, just flush everything. Could be smarter later. - */ -static GLuint brw_flush_cmd( void ) -{ - struct brw_mi_flush flush; - flush.opcode = CMD_MI_FLUSH; - flush.pad = 0; - flush.flags = BRW_FLUSH_STATE_CACHE; - return *(GLuint *)&flush; -} - - static void brw_invalidate_state( struct intel_context *intel, GLuint new_state ) { /* nothing */ @@ -209,6 +195,5 @@ void brwInitVtbl( struct brw_context *brw ) brw->intel.vtbl.finish_batch = brw_finish_batch; brw->intel.vtbl.destroy = brw_destroy_context; brw->intel.vtbl.set_draw_region = brw_set_draw_region; - brw->intel.vtbl.flush_cmd = brw_flush_cmd; brw->intel.vtbl.debug_batch = brw_debug_batch; } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index e94b8368cd..ca6e2fa5b1 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -210,10 +210,10 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line, used); + batch->reserved_space = 0; /* Emit a flush if the bufmgr doesn't do it for us. */ if (intel->always_flush_cache || !intel->ttm) { - *(GLuint *) (batch->ptr) = intel->vtbl.flush_cmd(); - batch->ptr += 4; + intel_batchbuffer_emit_mi_flush(batch); used = batch->ptr - batch->map; } @@ -244,6 +244,8 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, if (intel->vtbl.finish_batch) intel->vtbl.finish_batch(intel); + batch->reserved_space = BATCH_RESERVED; + /* TODO: Just pass the relocation list and dma buffer up to the * kernel. */ @@ -299,3 +301,31 @@ intel_batchbuffer_data(struct intel_batchbuffer *batch, __memcpy(batch->ptr, data, bytes); batch->ptr += bytes; } + +/* Emit a pipelined flush to either flush render and texture cache for + * reading from a FBO-drawn texture, or flush so that frontbuffer + * render appears on the screen in DRI1. + * + * This is also used for the always_flush_cache driconf debug option. + */ +void +intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) +{ + struct intel_context *intel = batch->intel; + + if (intel->gen >= 4) { + BEGIN_BATCH(4, IGNORE_CLIPRECTS); + OUT_BATCH(_3DSTATE_PIPE_CONTROL | + PIPE_CONTROL_INSTRUCTION_FLUSH | + PIPE_CONTROL_WRITE_FLUSH | + PIPE_CONTROL_NO_WRITE); + OUT_BATCH(0); /* write address */ + OUT_BATCH(0); /* write data */ + OUT_BATCH(0); /* write data */ + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(1, IGNORE_CLIPRECTS); + OUT_BATCH(MI_FLUSH); + ADVANCE_BATCH(); + } +} diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index d4899aab7f..d4a94454dd 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -62,6 +62,7 @@ struct intel_batchbuffer } emit; GLuint dirty_state; + GLuint reserved_space; }; struct intel_batchbuffer *intel_batchbuffer_alloc(struct intel_context @@ -95,6 +96,7 @@ GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, uint32_t read_domains, uint32_t write_domain, uint32_t offset); +void intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch); /* Inline functions - might actually be better off with these * non-inlined. Certainly better off switching all command packets to @@ -104,7 +106,7 @@ GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, static INLINE GLint intel_batchbuffer_space(struct intel_batchbuffer *batch) { - return (batch->size - BATCH_RESERVED) - (batch->ptr - batch->map); + return (batch->size - batch->reserved_space) - (batch->ptr - batch->map); } @@ -173,12 +175,4 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch, intel->batch->emit.start_ptr = NULL; \ } while(0) - -static INLINE void -intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) -{ - intel_batchbuffer_require_space(batch, 4, IGNORE_CLIPRECTS); - intel_batchbuffer_emit_dword(batch, MI_FLUSH); -} - #endif diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 2fc224e51a..84fbfc564c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -117,8 +117,6 @@ struct intel_context struct intel_region * depth_region, GLuint num_regions); - GLuint (*flush_cmd) (void); - void (*reduced_primitive_state) (struct intel_context * intel, GLenum rprim); -- cgit v1.2.3 From 2bc8bcdcd334db715f8916f80ef4f4bc5f9a170d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 3 Nov 2009 17:40:13 -0800 Subject: i965: Remove an XXX comment for testing some code that seems to work. --- src/mesa/drivers/dri/i965/brw_wm_fp.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 0e86d75dea..a453250e79 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -448,7 +448,6 @@ static void emit_interp( struct brw_wm_compile *c, break; case FRAG_ATTRIB_FACE: - /* XXX review/test this case */ emit_op(c, WM_FRONTFACING, dst_mask(dst, WRITEMASK_X), -- cgit v1.2.3 From 8395da2e8af40367714c70afe299568272f36cc8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 5 Nov 2009 10:25:34 -0800 Subject: i965: Always pass the size argument to brw_cache_data. This keeps the individual state files from having to export their structures for brw_state_cache initialization. --- src/mesa/drivers/dri/i965/brw_cc.c | 3 +- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_sf_state.c | 3 +- src/mesa/drivers/dri/i965/brw_state.h | 8 +--- src/mesa/drivers/dri/i965/brw_state_cache.c | 59 ++++++------------------ src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 4 +- 6 files changed, 21 insertions(+), 57 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index 5cca605c3f..d4ccd28c9e 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -55,7 +55,8 @@ static void prepare_cc_vp( struct brw_context *brw ) } dri_bo_unreference(brw->cc.vp_bo); - brw->cc.vp_bo = brw_cache_data( &brw->cache, BRW_CC_VP, &ccv, NULL, 0 ); + brw->cc.vp_bo = brw_cache_data(&brw->cache, BRW_CC_VP, &ccv, sizeof(ccv), + NULL, 0); } const struct brw_tracked_state brw_cc_vp = { diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 59f9475b5a..e01930a4a0 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -333,7 +333,6 @@ struct brw_cache { struct brw_cache_item **items; GLuint size, n_items; - GLuint key_size[BRW_MAX_CACHE]; /* for fixed-size keys */ GLuint aux_size[BRW_MAX_CACHE]; char *name[BRW_MAX_CACHE]; diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index bc0f076073..d6b47b5d8d 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -93,7 +93,8 @@ static void upload_sf_vp(struct brw_context *brw) } dri_bo_unreference(brw->sf.vp_bo); - brw->sf.vp_bo = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0 ); + brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP, &sfv, sizeof(sfv), + NULL, 0); } const struct brw_tracked_state brw_sf_vp = { diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index d639656b9d..ab6f158080 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -119,16 +119,10 @@ void brw_destroy_state(struct brw_context *brw); dri_bo *brw_cache_data(struct brw_cache *cache, enum brw_cache_id cache_id, const void *data, + GLuint size, dri_bo **reloc_bufs, GLuint nr_reloc_bufs); -dri_bo *brw_cache_data_sz(struct brw_cache *cache, - enum brw_cache_id cache_id, - const void *data, - GLuint data_size, - dri_bo **reloc_bufs, - GLuint nr_reloc_bufs); - dri_bo *brw_upload_cache( struct brw_cache *cache, enum brw_cache_id cache_id, const void *key, diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index c262e1db8b..d2ab624783 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -275,15 +275,22 @@ brw_upload_cache( struct brw_cache *cache, /** - * This doesn't really work with aux data. Use search/upload instead + * Wrapper around brw_cache_data_sz using the cache_id's canonical key size. + * + * If nr_reloc_bufs is nonzero, brw_search_cache()/brw_upload_cache() would be + * better to use, as the potentially changing offsets in the data-used-as-key + * will result in excessive cache misses. + * + * If aux data is involved, use search/upload instead. + */ dri_bo * -brw_cache_data_sz(struct brw_cache *cache, - enum brw_cache_id cache_id, - const void *data, - GLuint data_size, - dri_bo **reloc_bufs, - GLuint nr_reloc_bufs) +brw_cache_data(struct brw_cache *cache, + enum brw_cache_id cache_id, + const void *data, + GLuint data_size, + dri_bo **reloc_bufs, + GLuint nr_reloc_bufs) { dri_bo *bo; struct brw_cache_item *item; @@ -306,25 +313,6 @@ brw_cache_data_sz(struct brw_cache *cache, return bo; } - -/** - * Wrapper around brw_cache_data_sz using the cache_id's canonical key size. - * - * If nr_reloc_bufs is nonzero, brw_search_cache()/brw_upload_cache() would be - * better to use, as the potentially changing offsets in the data-used-as-key - * will result in excessive cache misses. - */ -dri_bo * -brw_cache_data(struct brw_cache *cache, - enum brw_cache_id cache_id, - const void *data, - dri_bo **reloc_bufs, - GLuint nr_reloc_bufs) -{ - return brw_cache_data_sz(cache, cache_id, data, cache->key_size[cache_id], - reloc_bufs, nr_reloc_bufs); -} - enum pool_type { DW_SURFACE_STATE, DW_GENERAL_STATE @@ -335,11 +323,9 @@ static void brw_init_cache_id(struct brw_cache *cache, const char *name, enum brw_cache_id id, - GLuint key_size, GLuint aux_size) { cache->name[id] = strdup(name); - cache->key_size[id] = key_size; cache->aux_size[id] = aux_size; } @@ -359,91 +345,76 @@ brw_init_non_surface_cache(struct brw_context *brw) brw_init_cache_id(cache, "CC_VP", BRW_CC_VP, - sizeof(struct brw_cc_viewport), 0); brw_init_cache_id(cache, "CC_UNIT", BRW_CC_UNIT, - sizeof(struct brw_cc_unit_state), 0); brw_init_cache_id(cache, "WM_PROG", BRW_WM_PROG, - sizeof(struct brw_wm_prog_key), sizeof(struct brw_wm_prog_data)); brw_init_cache_id(cache, "SAMPLER_DEFAULT_COLOR", BRW_SAMPLER_DEFAULT_COLOR, - sizeof(struct brw_sampler_default_color), 0); brw_init_cache_id(cache, "SAMPLER", BRW_SAMPLER, - 0, /* variable key/data size */ 0); brw_init_cache_id(cache, "WM_UNIT", BRW_WM_UNIT, - sizeof(struct brw_wm_unit_state), 0); brw_init_cache_id(cache, "SF_PROG", BRW_SF_PROG, - sizeof(struct brw_sf_prog_key), sizeof(struct brw_sf_prog_data)); brw_init_cache_id(cache, "SF_VP", BRW_SF_VP, - sizeof(struct brw_sf_viewport), 0); brw_init_cache_id(cache, "SF_UNIT", BRW_SF_UNIT, - sizeof(struct brw_sf_unit_state), 0); brw_init_cache_id(cache, "VS_UNIT", BRW_VS_UNIT, - sizeof(struct brw_vs_unit_state), 0); brw_init_cache_id(cache, "VS_PROG", BRW_VS_PROG, - sizeof(struct brw_vs_prog_key), sizeof(struct brw_vs_prog_data)); brw_init_cache_id(cache, "CLIP_UNIT", BRW_CLIP_UNIT, - sizeof(struct brw_clip_unit_state), 0); brw_init_cache_id(cache, "CLIP_PROG", BRW_CLIP_PROG, - sizeof(struct brw_clip_prog_key), sizeof(struct brw_clip_prog_data)); brw_init_cache_id(cache, "GS_UNIT", BRW_GS_UNIT, - sizeof(struct brw_gs_unit_state), 0); brw_init_cache_id(cache, "GS_PROG", BRW_GS_PROG, - sizeof(struct brw_gs_prog_key), sizeof(struct brw_gs_prog_data)); } @@ -463,13 +434,11 @@ brw_init_surface_cache(struct brw_context *brw) brw_init_cache_id(cache, "SS_SURFACE", BRW_SS_SURFACE, - sizeof(struct brw_surface_state), 0); brw_init_cache_id(cache, "SS_SURF_BIND", BRW_SS_SURF_BIND, - 0, 0); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index 0acb027431..aa2e519588 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -73,8 +73,8 @@ static dri_bo *upload_default_color( struct brw_context *brw, COPY_4V(sdc.color, color); - return brw_cache_data( &brw->cache, BRW_SAMPLER_DEFAULT_COLOR, &sdc, - NULL, 0 ); + return brw_cache_data(&brw->cache, BRW_SAMPLER_DEFAULT_COLOR, + &sdc, sizeof(sdc), NULL, 0); } -- cgit v1.2.3 From 0f34cdf6210b748db77c5eba2993637f4af6faeb Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 12 Aug 2009 12:56:35 -0700 Subject: i965: Collect GLSL src/dst regs up in generic code. This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced. --- src/mesa/drivers/dri/i965/brw_wm.h | 2 ++ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 22 +++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 47aa4da306..f841d25870 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -162,6 +162,8 @@ struct brw_wm_instruction { #define BRW_WM_MAX_CONST 256 #define BRW_WM_MAX_SUBROUTINE 16 +/* used in masks next to WRITEMASK_*. */ +#define SATURATE (1<<5) /* New opcodes to track internal operations required for WM unit. diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 28d6d4eba5..fd6d6c5602 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -2771,6 +2771,21 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) if (c->fp->use_const_buffer) fetch_constants(c, inst); + if (inst->Opcode != OPCODE_ARL) { + for (j = 0; j < 4; j++) { + if (inst->DstReg.WriteMask & (1 << j)) + dst[j] = get_dst_reg(c, inst, j); + else + dst[j] = brw_null_reg(); + } + } + for (j = 0; j < brw_wm_nr_args(inst->Opcode); j++) + get_argument_regs(c, inst, j, args[j], WRITEMASK_XYZW); + + dst_flags = inst->DstReg.WriteMask; + if (inst->SaturateMode == SATURATE_ZERO_ONE) + dst_flags |= SATURATE; + if (inst->CondUpdate) brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); else @@ -2866,13 +2881,6 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) break; case OPCODE_DDX: case OPCODE_DDY: - for (j = 0; j < 4; j++) { - if (inst->DstReg.WriteMask & (1 << j)) - dst[j] = get_dst_reg(c, inst, j); - else - dst[j] = brw_null_reg(); - } - get_argument_regs(c, inst, 0, args[0], WRITEMASK_XYZW); emit_ddxy(p, dst, dst_flags, (inst->Opcode == OPCODE_DDX), args[0]); break; -- cgit v1.2.3 From 71af5080722afcbbb8a935138d95214ef7afe219 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 11 Aug 2009 16:31:19 -0700 Subject: i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain. --- src/mesa/drivers/dri/i965/brw_wm.h | 17 +++++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 32 +++++----- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 106 ++------------------------------ 3 files changed, 38 insertions(+), 117 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index f841d25870..93f79dbfe5 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -308,6 +308,23 @@ void brw_wm_lookup_iz( GLuint line_aa, GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp); void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c); +/* brw_wm_emit.c */ +void emit_alu1(struct brw_compile *p, + struct brw_instruction *(*func)(struct brw_compile *, + struct brw_reg, + struct brw_reg), + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0); +void emit_alu2(struct brw_compile *p, + struct brw_instruction *(*func)(struct brw_compile *, + struct brw_reg, + struct brw_reg, + struct brw_reg), + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); void emit_ddxy(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index bf80a2942a..5e41a3f571 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -352,13 +352,13 @@ void emit_ddxy(struct brw_compile *p, brw_set_saturate(p, 0); } -static void emit_alu1( struct brw_compile *p, - struct brw_instruction *(*func)(struct brw_compile *, - struct brw_reg, - struct brw_reg), - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0 ) +void emit_alu1(struct brw_compile *p, + struct brw_instruction *(*func)(struct brw_compile *, + struct brw_reg, + struct brw_reg), + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0) { GLuint i; @@ -376,15 +376,15 @@ static void emit_alu1( struct brw_compile *p, } -static void emit_alu2( struct brw_compile *p, - struct brw_instruction *(*func)(struct brw_compile *, - struct brw_reg, - struct brw_reg, - struct brw_reg), - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_alu2(struct brw_compile *p, + struct brw_instruction *(*func)(struct brw_compile *, + struct brw_reg, + struct brw_reg, + struct brw_reg), + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { GLuint i; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index fd6d6c5602..fdd31d4ed5 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -668,26 +668,6 @@ static void emit_trunc( struct brw_wm_compile *c, brw_set_saturate(p, 0); } -static void emit_mov( struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - int i; - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); - for (i = 0; i < 4; i++) { - if (mask & (1<func; - struct brw_reg src0, src1, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - for (i = 0 ; i < 4; i++) { - if (mask & (1<func; - struct brw_reg src0, src1, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - for (i = 0 ; i < 4; i++) { - if (mask & (1<func; - struct brw_reg src0, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - for (i = 0 ; i < 4; i++) { - if (mask & (1<SaturateMode != SATURATE_OFF) - brw_set_saturate(p, 0); -} - -static void emit_flr(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - struct brw_reg src0, dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - for (i = 0 ; i < 4; i++) { - if (mask & (1< Date: Tue, 11 Aug 2009 16:47:15 -0700 Subject: i965: Use a normal alu1 emit for OPCODE_TRUNC. --- src/mesa/drivers/dri/i965/brw_wm_emit.c | 16 +--------------- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 20 +------------------- 2 files changed, 2 insertions(+), 34 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 5e41a3f571..215515d10b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -422,20 +422,6 @@ static void emit_mad( struct brw_compile *p, } } -static void emit_trunc( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0) -{ - GLuint i; - - for (i = 0; i < 4; i++) { - if (mask & (1<func; - GLuint mask = inst->DstReg.WriteMask; - brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF); - for (i = 0; i < 4; i++) { - if (mask & (1< Date: Tue, 11 Aug 2009 17:52:44 -0700 Subject: i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code. --- src/mesa/drivers/dri/i965/brw_wm.h | 6 ++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 12 ++-- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 98 ++++++++++++++++++++------------- 3 files changed, 71 insertions(+), 45 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 93f79dbfe5..66902bab65 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -330,5 +330,11 @@ void emit_ddxy(struct brw_compile *p, GLuint mask, GLboolean is_ddx, const struct brw_reg *arg0); +void emit_lrp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1, + const struct brw_reg *arg2); #endif diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 215515d10b..9e637ef3f2 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -422,12 +422,12 @@ static void emit_mad( struct brw_compile *p, } } -static void emit_lrp( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1, - const struct brw_reg *arg2 ) +void emit_lrp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1, + const struct brw_reg *arg2) { GLuint i; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index cd5a59463c..458d06187a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -650,6 +650,63 @@ static void invoke_subroutine( struct brw_wm_compile *c, } } +/* Workaround for using brw_wm_emit.c's emit functions, which expect + * destination regs to be uniquely written. Moves arguments out to + * temporaries as necessary for instructions which use their destination as + * a temporary. + */ +static void +unalias3(struct brw_wm_compile *c, + void (*func)(struct brw_compile *c, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1, + const struct brw_reg *arg2), + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1, + const struct brw_reg *arg2) +{ + struct brw_compile *p = &c->func; + struct brw_reg tmp_arg0[4], tmp_arg1[4], tmp_arg2[4]; + int i, j; + int mark = mark_tmps(c); + + for (j = 0; j < 4; j++) { + tmp_arg0[j] = arg0[j]; + tmp_arg1[j] = arg1[j]; + tmp_arg2[j] = arg2[j]; + } + + for (i = 0; i < 4; i++) { + if (mask & (1<func; - GLuint mask = inst->DstReg.WriteMask; - struct brw_reg dst, tmp1, tmp2, src0, src1, src2; - int i; - int mark = mark_tmps(c); - for (i = 0; i < 4; i++) { - if (mask & (1<SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_MAC(p, dst, src0, tmp1); - brw_set_saturate(p, 0); - } - release_tmps(c, mark); - } -} - /** * For GLSL shaders, this KIL will be unconditional. * It may be contained inside an IF/ENDIF structure of course. @@ -2722,7 +2741,8 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_alu1(p, brw_RNDD, dst, dst_flags, args[0]); break; case OPCODE_LRP: - emit_lrp(c, inst); + unalias3(c, emit_lrp, + dst, dst_flags, args[0], args[1], args[2]); break; case OPCODE_TRUNC: emit_alu1(p, brw_RNDZ, dst, dst_flags, args[0]); -- cgit v1.2.3 From bad5b120be8de37cf8481d865790298fd9651381 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 11 Aug 2009 19:13:52 -0700 Subject: i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c --- src/mesa/drivers/dri/i965/brw_wm.h | 15 ++++++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 30 ++++++------ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 87 ++------------------------------- 3 files changed, 33 insertions(+), 99 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 66902bab65..18f17f2488 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -330,6 +330,21 @@ void emit_ddxy(struct brw_compile *p, GLuint mask, GLboolean is_ddx, const struct brw_reg *arg0); +void emit_dp3(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); +void emit_dp4(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); +void emit_dph(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); void emit_lrp(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 9e637ef3f2..bc5abb942b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -594,11 +594,11 @@ static void emit_min( struct brw_compile *p, } -static void emit_dp3( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_dp3(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; @@ -616,11 +616,11 @@ static void emit_dp3( struct brw_compile *p, } -static void emit_dp4( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_dp4(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; @@ -639,11 +639,11 @@ static void emit_dp4( struct brw_compile *p, } -static void emit_dph( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_dph(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { const int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 458d06187a..536eac8851 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1038,87 +1038,6 @@ static void emit_xpd(struct brw_wm_compile *c, brw_set_saturate(p, 0); } -static void emit_dp3(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_reg src0[3], src1[3], dst; - int i; - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; - - if (!(mask & WRITEMASK_XYZW)) - return; - - assert(is_power_of_two(mask & WRITEMASK_XYZW)); - - for (i = 0; i < 3; i++) { - src0[i] = get_src_reg(c, inst, 0, i); - src1[i] = get_src_reg_imm(c, inst, 1, i); - } - - dst = get_dst_reg(c, inst, dst_chan); - brw_MUL(p, brw_null_reg(), src0[0], src1[0]); - brw_MAC(p, brw_null_reg(), src0[1], src1[1]); - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_MAC(p, dst, src0[2], src1[2]); - brw_set_saturate(p, 0); -} - -static void emit_dp4(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_reg src0[4], src1[4], dst; - int i; - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; - - if (!(mask & WRITEMASK_XYZW)) - return; - - assert(is_power_of_two(mask & WRITEMASK_XYZW)); - - for (i = 0; i < 4; i++) { - src0[i] = get_src_reg(c, inst, 0, i); - src1[i] = get_src_reg_imm(c, inst, 1, i); - } - dst = get_dst_reg(c, inst, dst_chan); - brw_MUL(p, brw_null_reg(), src0[0], src1[0]); - brw_MAC(p, brw_null_reg(), src0[1], src1[1]); - brw_MAC(p, brw_null_reg(), src0[2], src1[2]); - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_MAC(p, dst, src0[3], src1[3]); - brw_set_saturate(p, 0); -} - -static void emit_dph(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_reg src0[4], src1[4], dst; - int i; - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; - - if (!(mask & WRITEMASK_XYZW)) - return; - - assert(is_power_of_two(mask & WRITEMASK_XYZW)); - - for (i = 0; i < 4; i++) { - src0[i] = get_src_reg(c, inst, 0, i); - src1[i] = get_src_reg_imm(c, inst, 1, i); - } - dst = get_dst_reg(c, inst, dst_chan); - brw_MUL(p, brw_null_reg(), src0[0], src1[0]); - brw_MAC(p, brw_null_reg(), src0[1], src1[1]); - brw_MAC(p, dst, src0[2], src1[2]); - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_ADD(p, dst, dst, src1[3]); - brw_set_saturate(p, 0); -} - /** * Emit a scalar instruction, like RCP, RSQ, LOG, EXP. * Note that the result of the function is smeared across the dest @@ -2752,16 +2671,16 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_alu1(p, brw_MOV, dst, dst_flags, args[0]); break; case OPCODE_DP3: - emit_dp3(c, inst); + emit_dp3(p, dst, dst_flags, args[0], args[1]); break; case OPCODE_DP4: - emit_dp4(c, inst); + emit_dp4(p, dst, dst_flags, args[0], args[1]); break; case OPCODE_XPD: emit_xpd(c, inst); break; case OPCODE_DPH: - emit_dph(c, inst); + emit_dph(p, dst, dst_flags, args[0], args[1]); break; case OPCODE_RCP: emit_rcp(c, inst); -- cgit v1.2.3 From 726ad1560660a1fc769c87e0ea16f8b3334df0d2 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 11 Aug 2009 19:17:31 -0700 Subject: i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c --- src/mesa/drivers/dri/i965/brw_wm.h | 6 ++++++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 12 ++++++------ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 25 +------------------------ 3 files changed, 13 insertions(+), 30 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 18f17f2488..e0445aaf52 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -351,5 +351,11 @@ void emit_lrp(struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1, const struct brw_reg *arg2); +void emit_mad(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1, + const struct brw_reg *arg2); #endif diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index bc5abb942b..6cdc4f7483 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -402,12 +402,12 @@ void emit_alu2(struct brw_compile *p, } -static void emit_mad( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1, - const struct brw_reg *arg2 ) +void emit_mad(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1, + const struct brw_reg *arg2) { GLuint i; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 536eac8851..55e3e9fa7f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1214,29 +1214,6 @@ static void emit_kil(struct brw_wm_compile *c) brw_pop_insn_state(p); } -static void emit_mad(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - struct brw_reg dst, src0, src1, src2; - int i; - - for (i = 0; i < 4; i++) { - if (mask & (1<SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_ADD(p, dst, dst, src2); - brw_set_saturate(p, 0); - } - } -} - static void emit_sop(struct brw_wm_compile *c, const struct prog_instruction *inst, GLuint cond) { @@ -2734,7 +2711,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_pow(c, inst); break; case OPCODE_MAD: - emit_mad(c, inst); + emit_mad(p, dst, dst_flags, args[0], args[1], args[2]); break; case OPCODE_NOISE1: emit_noise1(c, inst); -- cgit v1.2.3 From 7059aa0eff9ff6ec361e584b413f63b25762a89c Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 11 Aug 2009 21:17:14 -0700 Subject: i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c. --- src/mesa/drivers/dri/i965/brw_wm.h | 6 +++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 19 ++++---- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 78 +++++---------------------------- 3 files changed, 29 insertions(+), 74 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index e0445aaf52..df8e467aaf 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -357,5 +357,11 @@ void emit_mad(struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1, const struct brw_reg *arg2); +void emit_sop(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + GLuint cond, + const struct brw_reg *arg0, + const struct brw_reg *arg1); #endif diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 6cdc4f7483..41ebadb553 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -447,21 +447,24 @@ void emit_lrp(struct brw_compile *p, } } -static void emit_sop( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - GLuint cond, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_sop(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + GLuint cond, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { GLuint i; for (i = 0; i < 4; i++) { if (mask & (1<func; - GLuint mask = inst->DstReg.WriteMask; - struct brw_reg dst, src0, src1; - int i; - - for (i = 0; i < 4; i++) { - if (mask & (1< Date: Wed, 12 Aug 2009 09:52:44 -0700 Subject: i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c. --- src/mesa/drivers/dri/i965/brw_wm.h | 16 +++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 139 +++++++++++++++---------- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 177 ++------------------------------ 3 files changed, 111 insertions(+), 221 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index df8e467aaf..7d470e8dfe 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -357,11 +357,27 @@ void emit_mad(struct brw_compile *p, const struct brw_reg *arg0, const struct brw_reg *arg1, const struct brw_reg *arg2); +void emit_math1(struct brw_wm_compile *c, + GLuint function, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0); +void emit_math2(struct brw_wm_compile *c, + GLuint function, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); void emit_sop(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, GLuint cond, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_xpd(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); #endif diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 41ebadb553..763fe4b4d6 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -665,11 +665,11 @@ void emit_dph(struct brw_compile *p, } -static void emit_xpd( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_xpd(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { GLuint i; @@ -690,41 +690,68 @@ static void emit_xpd( struct brw_compile *p, } -static void emit_math1( struct brw_compile *p, - GLuint function, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0 ) +void emit_math1(struct brw_wm_compile *c, + GLuint function, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0) { + struct brw_compile *p = &c->func; int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; + GLuint saturate = ((mask & SATURATE) ? + BRW_MATH_SATURATE_SATURATE : + BRW_MATH_SATURATE_NONE); if (!(mask & WRITEMASK_XYZW)) return; /* Do not emit dead code */ assert(is_power_of_two(mask & WRITEMASK_XYZW)); + /* If compressed, this will write message reg 2,3 from arg0.x's 16 + * channels. + */ brw_MOV(p, brw_message_reg(2), arg0[0]); /* Send two messages to perform all 16 operations: */ - brw_math_16(p, - dst[dst_chan], + brw_push_insn_state(p); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_math(p, + dst[dst_chan], + function, + saturate, + 2, + brw_null_reg(), + BRW_MATH_DATA_VECTOR, + BRW_MATH_PRECISION_FULL); + + if (c->dispatch_width == 16) { + brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); + brw_math(p, + offset(dst[dst_chan],1), function, - (mask & SATURATE) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, - 2, + saturate, + 3, brw_null_reg(), + BRW_MATH_DATA_VECTOR, BRW_MATH_PRECISION_FULL); + } + brw_pop_insn_state(p); } -static void emit_math2( struct brw_compile *p, - GLuint function, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1) +void emit_math2(struct brw_wm_compile *c, + GLuint function, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { + struct brw_compile *p = &c->func; int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; + GLuint saturate = ((mask & SATURATE) ? + BRW_MATH_SATURATE_SATURATE : + BRW_MATH_SATURATE_NONE); if (!(mask & WRITEMASK_XYZW)) return; /* Do not emit dead code */ @@ -735,37 +762,41 @@ static void emit_math2( struct brw_compile *p, brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_MOV(p, brw_message_reg(2), arg0[0]); - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); - brw_MOV(p, brw_message_reg(4), sechalf(arg0[0])); + if (c->dispatch_width == 16) { + brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); + brw_MOV(p, brw_message_reg(4), sechalf(arg0[0])); + } brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_MOV(p, brw_message_reg(3), arg1[0]); - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); - brw_MOV(p, brw_message_reg(5), sechalf(arg1[0])); + if (c->dispatch_width == 16) { + brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); + brw_MOV(p, brw_message_reg(5), sechalf(arg1[0])); + } - - /* Send two messages to perform all 16 operations: - */ brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_math(p, dst[dst_chan], function, - (mask & SATURATE) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, + saturate, 2, brw_null_reg(), BRW_MATH_DATA_VECTOR, BRW_MATH_PRECISION_FULL); - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); - brw_math(p, - offset(dst[dst_chan],1), - function, - (mask & SATURATE) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, - 4, - brw_null_reg(), - BRW_MATH_DATA_VECTOR, - BRW_MATH_PRECISION_FULL); - + /* Send two messages to perform all 16 operations: + */ + if (c->dispatch_width == 16) { + brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); + brw_math(p, + offset(dst[dst_chan],1), + function, + saturate, + 4, + brw_null_reg(), + BRW_MATH_DATA_VECTOR, + BRW_MATH_PRECISION_FULL); + } brw_pop_insn_state(p); } @@ -909,11 +940,13 @@ static void emit_txb( struct brw_wm_compile *c, } -static void emit_lit( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0 ) +static void emit_lit(struct brw_wm_compile *c, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0) { + struct brw_compile *p = &c->func; + assert((mask & WRITEMASK_XW) == 0); if (mask & WRITEMASK_Y) { @@ -923,7 +956,7 @@ static void emit_lit( struct brw_compile *p, } if (mask & WRITEMASK_Z) { - emit_math2(p, BRW_MATH_FUNCTION_POW, + emit_math2(c, BRW_MATH_FUNCTION_POW, &dst[2], WRITEMASK_X | (mask & SATURATE), &arg0[1], @@ -1380,27 +1413,27 @@ void brw_wm_emit( struct brw_wm_compile *c ) /* Higher math functions: */ case OPCODE_RCP: - emit_math1(p, BRW_MATH_FUNCTION_INV, dst, dst_flags, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_INV, dst, dst_flags, args[0]); break; case OPCODE_RSQ: - emit_math1(p, BRW_MATH_FUNCTION_RSQ, dst, dst_flags, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, dst_flags, args[0]); break; case OPCODE_SIN: - emit_math1(p, BRW_MATH_FUNCTION_SIN, dst, dst_flags, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, dst_flags, args[0]); break; case OPCODE_COS: - emit_math1(p, BRW_MATH_FUNCTION_COS, dst, dst_flags, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_COS, dst, dst_flags, args[0]); break; case OPCODE_EX2: - emit_math1(p, BRW_MATH_FUNCTION_EXP, dst, dst_flags, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, dst_flags, args[0]); break; case OPCODE_LG2: - emit_math1(p, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]); break; case OPCODE_SCS: @@ -1408,13 +1441,13 @@ void brw_wm_emit( struct brw_wm_compile *c ) * fixup for 16-element execution. */ if (dst_flags & WRITEMASK_X) - emit_math1(p, BRW_MATH_FUNCTION_COS, dst, (dst_flags&SATURATE)|WRITEMASK_X, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_COS, dst, (dst_flags&SATURATE)|WRITEMASK_X, args[0]); if (dst_flags & WRITEMASK_Y) - emit_math1(p, BRW_MATH_FUNCTION_SIN, dst+1, (dst_flags&SATURATE)|WRITEMASK_X, args[0]); + emit_math1(c, BRW_MATH_FUNCTION_SIN, dst+1, (dst_flags&SATURATE)|WRITEMASK_X, args[0]); break; case OPCODE_POW: - emit_math2(p, BRW_MATH_FUNCTION_POW, dst, dst_flags, args[0], args[1]); + emit_math2(c, BRW_MATH_FUNCTION_POW, dst, dst_flags, args[0], args[1]); break; /* Comparisons: @@ -1452,7 +1485,7 @@ void brw_wm_emit( struct brw_wm_compile *c ) break; case OPCODE_LIT: - emit_lit(p, dst, dst_flags, args[0]); + emit_lit(c, dst, dst_flags, args[0]); break; /* Texturing operations: diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 2df47344d5..02b119154f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -550,42 +550,6 @@ static struct brw_reg get_src_reg(struct brw_wm_compile *c, } } - -/** - * Same as \sa get_src_reg() but if the register is a literal, emit - * a brw_reg encoding the literal. - * Note that a brw instruction only allows one src operand to be a literal. - * For instructions with more than one operand, only the second can be a - * literal. This means that we treat some literals as constants/uniforms - * (which why PROGRAM_CONSTANT is checked in fetch_constants()). - * - */ -static struct brw_reg get_src_reg_imm(struct brw_wm_compile *c, - const struct prog_instruction *inst, - GLuint srcRegIndex, GLuint channel) -{ - const struct prog_src_register *src = &inst->SrcReg[srcRegIndex]; - if (src->File == PROGRAM_CONSTANT) { - /* a literal */ - const int component = GET_SWZ(src->Swizzle, channel); - const GLfloat *param = - c->fp->program.Base.Parameters->ParameterValues[src->Index]; - GLfloat value = param[component]; - if (src->Negate & (1 << channel)) - value = -value; - if (src->Abs) - value = FABSF(value); -#if 0 - printf(" form immed value %f for chan %d\n", value, channel); -#endif - return brw_imm_f(value); - } - else { - return get_src_reg(c, inst, srcRegIndex, channel); - } -} - - /** * Subroutines are minimal support for resusable instruction sequences. * They are implemented as simply as possible to minimise overhead: there @@ -1013,100 +977,6 @@ static void emit_frontfacing(struct brw_wm_compile *c, brw_set_predicate_control_flag_value(p, 0xff); } -static void emit_xpd(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - int i; - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - for (i = 0; i < 4; i++) { - GLuint i2 = (i+2)%3; - GLuint i1 = (i+1)%3; - if (mask & (1<SaturateMode != SATURATE_OFF); - brw_MAC(p, dst, src0, src1); - brw_set_saturate(p, 0); - } - } - brw_set_saturate(p, 0); -} - -/** - * Emit a scalar instruction, like RCP, RSQ, LOG, EXP. - * Note that the result of the function is smeared across the dest - * register's X, Y, Z and W channels (subject to writemasking of course). - */ -static void emit_math1(struct brw_wm_compile *c, - const struct prog_instruction *inst, GLuint func) -{ - struct brw_compile *p = &c->func; - struct brw_reg src0, dst; - GLuint mask = inst->DstReg.WriteMask; - int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; - - if (!(mask & WRITEMASK_XYZW)) - return; - - assert(is_power_of_two(mask & WRITEMASK_XYZW)); - - /* Get first component of source register */ - dst = get_dst_reg(c, inst, dst_chan); - src0 = get_src_reg(c, inst, 0, 0); - - brw_MOV(p, brw_message_reg(2), src0); - brw_math(p, - dst, - func, - (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, - 2, - brw_null_reg(), - BRW_MATH_DATA_VECTOR, - BRW_MATH_PRECISION_FULL); -} - -static void emit_rcp(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - emit_math1(c, inst, BRW_MATH_FUNCTION_INV); -} - -static void emit_rsq(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - emit_math1(c, inst, BRW_MATH_FUNCTION_RSQ); -} - -static void emit_sin(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - emit_math1(c, inst, BRW_MATH_FUNCTION_SIN); -} - -static void emit_cos(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - emit_math1(c, inst, BRW_MATH_FUNCTION_COS); -} - -static void emit_ex2(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - emit_math1(c, inst, BRW_MATH_FUNCTION_EXP); -} - -static void emit_lg2(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - emit_math1(c, inst, BRW_MATH_FUNCTION_LOG); -} - static void emit_arl(struct brw_wm_compile *c, const struct prog_instruction *inst) { @@ -1169,36 +1039,6 @@ static void emit_min_max(struct brw_wm_compile *c, release_tmps(c, mark); } -static void emit_pow(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - struct brw_reg dst, src0, src1; - GLuint mask = inst->DstReg.WriteMask; - int dst_chan = _mesa_ffs(mask & WRITEMASK_XYZW) - 1; - - if (!(mask & WRITEMASK_XYZW)) - return; - - assert(is_power_of_two(mask & WRITEMASK_XYZW)); - - dst = get_dst_reg(c, inst, dst_chan); - src0 = get_src_reg_imm(c, inst, 0, 0); - src1 = get_src_reg_imm(c, inst, 1, 0); - - brw_MOV(p, brw_message_reg(2), src0); - brw_MOV(p, brw_message_reg(3), src1); - - brw_math(p, - dst, - BRW_MATH_FUNCTION_POW, - (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE, - 2, - brw_null_reg(), - BRW_MATH_DATA_VECTOR, - BRW_MATH_PRECISION_FULL); -} - /** * For GLSL shaders, this KIL will be unconditional. * It may be contained inside an IF/ENDIF structure of course. @@ -2594,28 +2434,28 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_dp4(p, dst, dst_flags, args[0], args[1]); break; case OPCODE_XPD: - emit_xpd(c, inst); + emit_xpd(p, dst, dst_flags, args[0], args[1]); break; case OPCODE_DPH: emit_dph(p, dst, dst_flags, args[0], args[1]); break; case OPCODE_RCP: - emit_rcp(c, inst); + emit_math1(c, BRW_MATH_FUNCTION_INV, dst, dst_flags, args[0]); break; case OPCODE_RSQ: - emit_rsq(c, inst); + emit_math1(c, BRW_MATH_FUNCTION_RSQ, dst, dst_flags, args[0]); break; case OPCODE_SIN: - emit_sin(c, inst); + emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, dst_flags, args[0]); break; case OPCODE_COS: - emit_cos(c, inst); + emit_math1(c, BRW_MATH_FUNCTION_COS, dst, dst_flags, args[0]); break; case OPCODE_EX2: - emit_ex2(c, inst); + emit_math1(c, BRW_MATH_FUNCTION_EXP, dst, dst_flags, args[0]); break; case OPCODE_LG2: - emit_lg2(c, inst); + emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]); break; case OPCODE_MIN: case OPCODE_MAX: @@ -2654,7 +2494,8 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_alu2(p, brw_MUL, dst, dst_flags, args[0], args[1]); break; case OPCODE_POW: - emit_pow(c, inst); + emit_math2(c, BRW_MATH_FUNCTION_POW, + dst, dst_flags, args[0], args[1]); break; case OPCODE_MAD: emit_mad(p, dst, dst_flags, args[0], args[1], args[2]); -- cgit v1.2.3 From 2b58c31257f8900067276b6d6537bb2ce54b1b10 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 12 Aug 2009 10:19:31 -0700 Subject: i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst. --- src/mesa/drivers/dri/i965/brw_wm.h | 34 +++++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 115 ++++++++------ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 257 +------------------------------- 3 files changed, 109 insertions(+), 297 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 7d470e8dfe..eba828f6e3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -325,11 +325,19 @@ void emit_alu2(struct brw_compile *p, GLuint mask, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_cinterp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0); void emit_ddxy(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, GLboolean is_ddx, const struct brw_reg *arg0); +void emit_delta_xy(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0); void emit_dp3(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, @@ -345,6 +353,14 @@ void emit_dph(struct brw_compile *p, GLuint mask, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_frontfacing(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask); +void emit_linterp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *deltas); void emit_lrp(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, @@ -368,12 +384,30 @@ void emit_math2(struct brw_wm_compile *c, GLuint mask, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_pinterp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *deltas, + const struct brw_reg *w); +void emit_pixel_xy(struct brw_wm_compile *c, + const struct brw_reg *dst, + GLuint mask); +void emit_pixel_w(struct brw_wm_compile *c, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *deltas); void emit_sop(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, GLuint cond, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_wpos_xy(struct brw_wm_compile *c, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0); void emit_xpd(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 763fe4b4d6..6eaa2792be 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -44,6 +44,7 @@ static INLINE struct brw_reg sechalf( struct brw_reg reg ) return reg; } + /* Payload R0: * * R0.0 -- pixel mask, one bit for each of 4 pixels in 4 tiles, @@ -60,42 +61,50 @@ static INLINE struct brw_reg sechalf( struct brw_reg reg ) * R1.8 -- ? */ - -static void emit_pixel_xy(struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask) +void emit_pixel_xy(struct brw_wm_compile *c, + const struct brw_reg *dst, + GLuint mask) { + struct brw_compile *p = &c->func; struct brw_reg r1 = brw_vec1_grf(1, 0); struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW); + struct brw_reg dst0_uw, dst1_uw; + brw_push_insn_state(p); brw_set_compression_control(p, BRW_COMPRESSION_NONE); + if (c->dispatch_width == 16) { + dst0_uw = vec16(retype(dst[0], BRW_REGISTER_TYPE_UW)); + dst1_uw = vec16(retype(dst[1], BRW_REGISTER_TYPE_UW)); + } else { + dst0_uw = vec8(retype(dst[0], BRW_REGISTER_TYPE_UW)); + dst1_uw = vec8(retype(dst[1], BRW_REGISTER_TYPE_UW)); + } + /* Calculate pixel centers by adding 1 or 0 to each of the * micro-tile coordinates passed in r1. */ if (mask & WRITEMASK_X) { brw_ADD(p, - vec16(retype(dst[0], BRW_REGISTER_TYPE_UW)), + dst0_uw, stride(suboffset(r1_uw, 4), 2, 4, 0), brw_imm_v(0x10101010)); } if (mask & WRITEMASK_Y) { brw_ADD(p, - vec16(retype(dst[1], BRW_REGISTER_TYPE_UW)), + dst1_uw, stride(suboffset(r1_uw,5), 2, 4, 0), brw_imm_v(0x11001100)); } - - brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED); + brw_pop_insn_state(p); } - -static void emit_delta_xy(struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0) +void emit_delta_xy(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0) { struct brw_reg r1 = brw_vec1_grf(1, 0); @@ -118,10 +127,10 @@ static void emit_delta_xy(struct brw_compile *p, } } -static void emit_wpos_xy(struct brw_wm_compile *c, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0) +void emit_wpos_xy(struct brw_wm_compile *c, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0) { struct brw_compile *p = &c->func; @@ -146,12 +155,14 @@ static void emit_wpos_xy(struct brw_wm_compile *c, } -static void emit_pixel_w( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *deltas) +void emit_pixel_w(struct brw_wm_compile *c, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *deltas) { + struct brw_compile *p = &c->func; + /* Don't need this if all you are doing is interpolating color, for * instance. */ @@ -165,21 +176,29 @@ static void emit_pixel_w( struct brw_compile *p, brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), deltas[1]); /* Calc w */ - brw_math_16( p, dst[3], - BRW_MATH_FUNCTION_INV, - BRW_MATH_SATURATE_NONE, - 2, brw_null_reg(), - BRW_MATH_PRECISION_FULL); + if (c->dispatch_width == 16) { + brw_math_16(p, dst[3], + BRW_MATH_FUNCTION_INV, + BRW_MATH_SATURATE_NONE, + 2, brw_null_reg(), + BRW_MATH_PRECISION_FULL); + } else { + brw_math(p, dst[3], + BRW_MATH_FUNCTION_INV, + BRW_MATH_SATURATE_NONE, + 2, brw_null_reg(), + BRW_MATH_DATA_VECTOR, + BRW_MATH_PRECISION_FULL); + } } } - -static void emit_linterp( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *deltas ) +void emit_linterp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *deltas) { struct brw_reg interp[4]; GLuint nr = arg0[0].nr; @@ -199,12 +218,12 @@ static void emit_linterp( struct brw_compile *p, } -static void emit_pinterp( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *deltas, - const struct brw_reg *w) +void emit_pinterp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *deltas, + const struct brw_reg *w) { struct brw_reg interp[4]; GLuint nr = arg0[0].nr; @@ -229,10 +248,10 @@ static void emit_pinterp( struct brw_compile *p, } -static void emit_cinterp( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0 ) +void emit_cinterp(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0) { struct brw_reg interp[4]; GLuint nr = arg0[0].nr; @@ -251,9 +270,9 @@ static void emit_cinterp( struct brw_compile *p, } /* Sets the destination channels to 1.0 or 0.0 according to glFrontFacing. */ -static void emit_frontfacing( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask ) +void emit_frontfacing(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask) { struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); GLuint i; @@ -1316,7 +1335,7 @@ void brw_wm_emit( struct brw_wm_compile *c ) /* Generated instructions for calculating triangle interpolants: */ case WM_PIXELXY: - emit_pixel_xy(p, dst, dst_flags); + emit_pixel_xy(c, dst, dst_flags); break; case WM_DELTAXY: @@ -1328,7 +1347,7 @@ void brw_wm_emit( struct brw_wm_compile *c ) break; case WM_PIXELW: - emit_pixel_w(p, dst, dst_flags, args[0], args[1]); + emit_pixel_w(c, dst, dst_flags, args[0], args[1]); break; case WM_LINTERP: diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 02b119154f..d0987362a4 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -671,67 +671,6 @@ unalias3(struct brw_wm_compile *c, release_tmps(c, mark); } -static void emit_pixel_xy(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_reg r1 = brw_vec1_grf(1, 0); - struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW); - - struct brw_reg dst0, dst1; - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - - dst0 = get_dst_reg(c, inst, 0); - dst1 = get_dst_reg(c, inst, 1); - /* Calculate pixel centers by adding 1 or 0 to each of the - * micro-tile coordinates passed in r1. - */ - if (mask & WRITEMASK_X) { - brw_ADD(p, - vec8(retype(dst0, BRW_REGISTER_TYPE_UW)), - stride(suboffset(r1_uw, 4), 2, 4, 0), - brw_imm_v(0x10101010)); - } - - if (mask & WRITEMASK_Y) { - brw_ADD(p, - vec8(retype(dst1, BRW_REGISTER_TYPE_UW)), - stride(suboffset(r1_uw, 5), 2, 4, 0), - brw_imm_v(0x11001100)); - } -} - -static void emit_delta_xy(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_reg r1 = brw_vec1_grf(1, 0); - struct brw_reg dst0, dst1, src0, src1; - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - - dst0 = get_dst_reg(c, inst, 0); - dst1 = get_dst_reg(c, inst, 1); - src0 = get_src_reg(c, inst, 0, 0); - src1 = get_src_reg(c, inst, 0, 1); - /* Calc delta X,Y by subtracting origin in r1 from the pixel - * centers. - */ - if (mask & WRITEMASK_X) { - brw_ADD(p, - dst0, - retype(src0, BRW_REGISTER_TYPE_UW), - negate(r1)); - } - - if (mask & WRITEMASK_Y) { - brw_ADD(p, - dst1, - retype(src1, BRW_REGISTER_TYPE_UW), - negate(suboffset(r1,1))); - - } -} - static void fire_fb_write( struct brw_wm_compile *c, GLuint base_reg, GLuint nr, @@ -829,154 +768,6 @@ static void emit_fb_write(struct brw_wm_compile *c, fire_fb_write(c, 0, nr, target, eot); } -static void emit_pixel_w( struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - if (mask & WRITEMASK_W) { - struct brw_reg dst, src0, delta0, delta1; - struct brw_reg interp3; - - dst = get_dst_reg(c, inst, 3); - src0 = get_src_reg(c, inst, 0, 0); - delta0 = get_src_reg(c, inst, 1, 0); - delta1 = get_src_reg(c, inst, 1, 1); - - interp3 = brw_vec1_grf(src0.nr+1, 4); - /* Calc 1/w - just linterp wpos[3] optimized by putting the - * result straight into a message reg. - */ - brw_LINE(p, brw_null_reg(), interp3, delta0); - brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), delta1); - - /* Calc w */ - brw_math_16( p, dst, - BRW_MATH_FUNCTION_INV, - BRW_MATH_SATURATE_NONE, - 2, brw_null_reg(), - BRW_MATH_PRECISION_FULL); - } -} - -static void emit_linterp(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - GLuint mask = inst->DstReg.WriteMask; - struct brw_reg interp[4]; - struct brw_reg dst, delta0, delta1; - struct brw_reg src0; - GLuint nr, i; - - src0 = get_src_reg(c, inst, 0, 0); - delta0 = get_src_reg(c, inst, 1, 0); - delta1 = get_src_reg(c, inst, 1, 1); - nr = src0.nr; - - interp[0] = brw_vec1_grf(nr, 0); - interp[1] = brw_vec1_grf(nr, 4); - interp[2] = brw_vec1_grf(nr+1, 0); - interp[3] = brw_vec1_grf(nr+1, 4); - - for(i = 0; i < 4; i++ ) { - if (mask & (1<func; - GLuint mask = inst->DstReg.WriteMask; - - struct brw_reg interp[4]; - struct brw_reg dst, src0; - GLuint nr, i; - - src0 = get_src_reg(c, inst, 0, 0); - nr = src0.nr; - - interp[0] = brw_vec1_grf(nr, 0); - interp[1] = brw_vec1_grf(nr, 4); - interp[2] = brw_vec1_grf(nr+1, 0); - interp[3] = brw_vec1_grf(nr+1, 4); - - for(i = 0; i < 4; i++ ) { - if (mask & (1<func; - GLuint mask = inst->DstReg.WriteMask; - - struct brw_reg interp[4]; - struct brw_reg dst, delta0, delta1; - struct brw_reg src0, w; - GLuint nr, i; - - src0 = get_src_reg(c, inst, 0, 0); - delta0 = get_src_reg(c, inst, 1, 0); - delta1 = get_src_reg(c, inst, 1, 1); - w = get_src_reg(c, inst, 2, 3); - nr = src0.nr; - - interp[0] = brw_vec1_grf(nr, 0); - interp[1] = brw_vec1_grf(nr, 4); - interp[2] = brw_vec1_grf(nr+1, 0); - interp[3] = brw_vec1_grf(nr+1, 4); - - for(i = 0; i < 4; i++ ) { - if (mask & (1<func; - struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); - struct brw_reg dst; - GLuint mask = inst->DstReg.WriteMask; - int i; - - for (i = 0; i < 4; i++) { - if (mask & (1<func; - GLuint mask = inst->DstReg.WriteMask; - struct brw_reg src0[2], dst[2]; - - dst[0] = get_dst_reg(c, inst, 0); - dst[1] = get_dst_reg(c, inst, 1); - src0[0] = get_src_reg(c, inst, 0, 0); - src0[1] = get_src_reg(c, inst, 0, 1); - - /* Calculate the pixel offset from window bottom left into destination - * X and Y channels. - */ - if (mask & WRITEMASK_X) { - /* X' = X - origin_x */ - brw_ADD(p, - dst[0], - retype(src0[0], BRW_REGISTER_TYPE_W), - brw_imm_d(0 - c->key.origin_x)); - } - - if (mask & WRITEMASK_Y) { - /* Y' = height - (Y - origin_y) = height + origin_y - Y */ - brw_ADD(p, - dst[1], - negate(retype(src0[1], BRW_REGISTER_TYPE_W)), - brw_imm_d(c->key.origin_y + c->key.drawable_height - 1)); - } -} /* TODO BIAS on SIMD8 not working yet... @@ -2378,31 +2137,31 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) switch (inst->Opcode) { case WM_PIXELXY: - emit_pixel_xy(c, inst); + emit_pixel_xy(c, dst, dst_flags); break; case WM_DELTAXY: - emit_delta_xy(c, inst); + emit_delta_xy(p, dst, dst_flags, args[0]); break; case WM_PIXELW: - emit_pixel_w(c, inst); + emit_pixel_w(c, dst, dst_flags, args[0], args[1]); break; case WM_LINTERP: - emit_linterp(c, inst); + emit_linterp(p, dst, dst_flags, args[0], args[1]); break; case WM_PINTERP: - emit_pinterp(c, inst); + emit_pinterp(p, dst, dst_flags, args[0], args[1], args[2]); break; case WM_CINTERP: - emit_cinterp(c, inst); + emit_cinterp(p, dst, dst_flags, args[0]); break; case WM_WPOSXY: - emit_wpos_xy(c, inst); + emit_wpos_xy(c, dst, dst_flags, args[0]); break; case WM_FB_WRITE: emit_fb_write(c, inst); break; case WM_FRONTFACING: - emit_frontfacing(c, inst); + emit_frontfacing(p, dst, dst_flags); break; case OPCODE_ADD: emit_alu2(p, brw_ADD, dst, dst_flags, args[0], args[1]); -- cgit v1.2.3 From cfa927766ab610a9a76730d337d77008d876ebbd Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 19 Aug 2009 11:48:09 -0700 Subject: i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c This should fix issues with antialiased lines in GLSL. --- src/mesa/drivers/dri/i965/brw_wm.h | 6 ++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 56 +++++++++--------- src/mesa/drivers/dri/i965/brw_wm_fp.c | 4 +- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 101 +------------------------------- 4 files changed, 40 insertions(+), 127 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index eba828f6e3..bde0c366bd 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -353,6 +353,12 @@ void emit_dph(struct brw_compile *p, GLuint mask, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_fb_write(struct brw_wm_compile *c, + struct brw_reg *arg0, + struct brw_reg *arg1, + struct brw_reg *arg2, + GLuint target, + GLuint eot); void emit_frontfacing(struct brw_compile *p, const struct brw_reg *dst, GLuint mask); diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 6eaa2792be..d02e3cb9ac 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1042,7 +1042,13 @@ static void fire_fb_write( struct brw_wm_compile *c, GLuint eot ) { struct brw_compile *p = &c->func; - + struct brw_reg dst; + + if (c->dispatch_width == 16) + dst = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW); + else + dst = retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW); + /* Pass through control information: */ /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */ @@ -1059,7 +1065,7 @@ static void fire_fb_write( struct brw_wm_compile *c, /* Send framebuffer write message: */ /* send (16) null.0<1>:uw m0 r0.0<8;8,1>:uw 0x85a04000:ud { Align1 EOT } */ brw_fb_WRITE(p, - retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW), + dst, base_reg, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), target, @@ -1091,12 +1097,12 @@ static void emit_aa( struct brw_wm_compile *c, * \param arg1 the pass-through depth value * \param arg2 the shader-computed depth value */ -static void emit_fb_write( struct brw_wm_compile *c, - struct brw_reg *arg0, - struct brw_reg *arg1, - struct brw_reg *arg2, - GLuint target, - GLuint eot) +void emit_fb_write(struct brw_wm_compile *c, + struct brw_reg *arg0, + struct brw_reg *arg1, + struct brw_reg *arg2, + GLuint target, + GLuint eot) { struct brw_compile *p = &c->func; GLuint nr = 2; @@ -1110,30 +1116,27 @@ static void emit_fb_write( struct brw_wm_compile *c, /* I don't really understand how this achieves the color interleave * (ie RGBARGBA) in the result: [Do the saturation here] */ - { - brw_push_insn_state(p); - - for (channel = 0; channel < 4; channel++) { - /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ - /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ + brw_push_insn_state(p); - brw_set_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, - brw_message_reg(nr + channel), - arg0[channel]); - + for (channel = 0; channel < 4; channel++) { + /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ + /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_MOV(p, + brw_message_reg(nr + channel), + arg0[channel]); + + if (c->dispatch_width == 16) { brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); brw_MOV(p, brw_message_reg(nr + channel + 4), sechalf(arg0[channel])); } - - /* skip over the regs populated above: - */ - nr += 8; - - brw_pop_insn_state(p); } + /* skip over the regs populated above: + */ + nr += 8; + brw_pop_insn_state(p); if (c->key.source_depth_to_render_target) { @@ -1183,7 +1186,7 @@ static void emit_fb_write( struct brw_wm_compile *c, get_element_ud(brw_vec8_grf(1,0), 6), brw_imm_ud(1<<26)); - jmp = brw_JMPI(p, ip, ip, brw_imm_d(0)); + jmp = brw_JMPI(p, ip, ip, brw_imm_w(0)); { emit_aa(c, arg1, 2); fire_fb_write(c, 0, nr, target, eot); @@ -1197,7 +1200,6 @@ static void emit_fb_write( struct brw_wm_compile *c, } } - /** * Move a GPR to scratch memory. */ diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index a453250e79..549afd31de 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -956,7 +956,7 @@ static void precalc_txp( struct brw_wm_compile *c, -static void emit_fb_write( struct brw_wm_compile *c ) +static void emit_render_target_writes( struct brw_wm_compile *c ) { struct prog_src_register payload_r0_depth = src_reg(PROGRAM_PAYLOAD, PAYLOAD_DEPTH); struct prog_src_register outdepth = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_DEPTH); @@ -1153,7 +1153,7 @@ void brw_wm_pass_fp( struct brw_wm_compile *c ) out->DstReg.WriteMask = 0; break; case OPCODE_END: - emit_fb_write(c); + emit_render_target_writes(c); break; case OPCODE_PRINT: break; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index d0987362a4..be89bcf4ba 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -671,103 +671,6 @@ unalias3(struct brw_wm_compile *c, release_tmps(c, mark); } -static void fire_fb_write( struct brw_wm_compile *c, - GLuint base_reg, - GLuint nr, - GLuint target, - GLuint eot) -{ - struct brw_compile *p = &c->func; - /* Pass through control information: - */ - /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */ - { - brw_push_insn_state(p); - brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */ - brw_MOV(p, - brw_message_reg(base_reg + 1), - brw_vec8_grf(1, 0)); - brw_pop_insn_state(p); - } - /* Send framebuffer write message: */ - brw_fb_WRITE(p, - retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW), - base_reg, - retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW), - target, - nr, - 0, - eot); -} - -static void emit_fb_write(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - int nr = 2; - int channel; - GLuint target, eot; - struct brw_reg src0; - - /* Reserve a space for AA - may not be needed: - */ - if (c->key.aa_dest_stencil_reg) - nr += 1; - - brw_push_insn_state(p); - for (channel = 0; channel < 4; channel++) { - src0 = get_src_reg(c, inst, 0, channel); - /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ - /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ - brw_MOV(p, brw_message_reg(nr + channel), src0); - } - /* skip over the regs populated above: */ - nr += 8; - brw_pop_insn_state(p); - - if (c->key.source_depth_to_render_target) { - if (c->key.computes_depth) { - src0 = get_src_reg(c, inst, 2, 2); - brw_MOV(p, brw_message_reg(nr), src0); - } - else { - src0 = get_src_reg(c, inst, 1, 1); - brw_MOV(p, brw_message_reg(nr), src0); - } - - nr += 2; - } - - if (c->key.dest_depth_reg) { - const GLuint comp = c->key.dest_depth_reg / 2; - const GLuint off = c->key.dest_depth_reg % 2; - - if (off != 0) { - /* XXX this code needs review/testing */ - struct brw_reg arg1_0 = get_src_reg(c, inst, 1, comp); - struct brw_reg arg1_1 = get_src_reg(c, inst, 1, comp+1); - - brw_push_insn_state(p); - brw_set_compression_control(p, BRW_COMPRESSION_NONE); - - brw_MOV(p, brw_message_reg(nr), offset(arg1_0, 1)); - /* 2nd half? */ - brw_MOV(p, brw_message_reg(nr+1), arg1_1); - brw_pop_insn_state(p); - } - else - { - struct brw_reg src = get_src_reg(c, inst, 1, 1); - brw_MOV(p, brw_message_reg(nr), src); - } - nr += 2; - } - - target = INST_AUX_GET_TARGET(inst->Aux); - eot = inst->Aux & INST_AUX_EOT; - fire_fb_write(c, 0, nr, target, eot); -} - static void emit_arl(struct brw_wm_compile *c, const struct prog_instruction *inst) { @@ -2158,7 +2061,9 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_wpos_xy(c, dst, dst_flags, args[0]); break; case WM_FB_WRITE: - emit_fb_write(c, inst); + emit_fb_write(c, args[0], args[1], args[2], + INST_AUX_GET_TARGET(inst->Aux), + inst->Aux & INST_AUX_EOT); break; case WM_FRONTFACING: emit_frontfacing(p, dst, dst_flags); -- cgit v1.2.3 From ec66644ed0af976cacb069ca7c7f0d6731666359 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 19 Aug 2009 11:57:32 -0700 Subject: i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c --- src/mesa/drivers/dri/i965/brw_wm.h | 10 ++++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 20 +++---- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 102 ++++++++++++++++---------------- 3 files changed, 72 insertions(+), 60 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index bde0c366bd..1fa2f1c06c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -390,6 +390,16 @@ void emit_math2(struct brw_wm_compile *c, GLuint mask, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_min(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); +void emit_max(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1); void emit_pinterp(struct brw_compile *p, const struct brw_reg *dst, GLuint mask, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index d02e3cb9ac..9cd1fedacb 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -567,11 +567,11 @@ static void emit_cmp( struct brw_compile *p, } } -static void emit_max( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_max(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { GLuint i; @@ -591,11 +591,11 @@ static void emit_max( struct brw_compile *p, } } -static void emit_min( struct brw_compile *p, - const struct brw_reg *dst, - GLuint mask, - const struct brw_reg *arg0, - const struct brw_reg *arg1 ) +void emit_min(struct brw_compile *p, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) { GLuint i; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index be89bcf4ba..9d3bc66f49 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -671,6 +671,55 @@ unalias3(struct brw_wm_compile *c, release_tmps(c, mark); } +/* Workaround for using brw_wm_emit.c's emit functions, which expect + * destination regs to be uniquely written. Moves arguments out to + * temporaries as necessary for instructions which use their destination as + * a temporary. + */ +static void +unalias2(struct brw_wm_compile *c, + void (*func)(struct brw_compile *c, + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1), + const struct brw_reg *dst, + GLuint mask, + const struct brw_reg *arg0, + const struct brw_reg *arg1) +{ + struct brw_compile *p = &c->func; + struct brw_reg tmp_arg0[4], tmp_arg1[4]; + int i, j; + int mark = mark_tmps(c); + + for (j = 0; j < 4; j++) { + tmp_arg0[j] = arg0[j]; + tmp_arg1[j] = arg1[j]; + } + + for (i = 0; i < 4; i++) { + if (mask & (1<func; - const GLuint mask = inst->DstReg.WriteMask; - const int mark = mark_tmps(c); - int i; - brw_push_insn_state(p); - for (i = 0; i < 4; i++) { - if (mask & (1<SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_MOV(p, dst, src0); - brw_set_saturate(p, 0); - - if (inst->Opcode == OPCODE_MIN) - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0); - else - brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_G, src1, src0); - - brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0); - brw_set_predicate_control(p, BRW_PREDICATE_NORMAL); - brw_MOV(p, dst, src1); - brw_set_saturate(p, 0); - brw_set_predicate_control_flag_value(p, 0xff); - if (use_temp) - brw_MOV(p, real_dst, dst); - } - } - brw_pop_insn_state(p); - release_tmps(c, mark); -} - /** * For GLSL shaders, this KIL will be unconditional. * It may be contained inside an IF/ENDIF structure of course. @@ -2122,8 +2122,10 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_math1(c, BRW_MATH_FUNCTION_LOG, dst, dst_flags, args[0]); break; case OPCODE_MIN: + unalias2(c, emit_min, dst, dst_flags, args[0], args[1]); + break; case OPCODE_MAX: - emit_min_max(c, inst); + unalias2(c, emit_max, dst, dst_flags, args[0], args[1]); break; case OPCODE_DDX: case OPCODE_DDY: -- cgit v1.2.3 From 8baee3d25beb616f6d5ba575684e889d60e38740 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 6 Nov 2009 17:45:13 -0800 Subject: i965: Use Compr4 instruction compression mode on G4X and newer. No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size. --- src/mesa/drivers/dri/i965/brw_eu.h | 10 +++++----- src/mesa/drivers/dri/i965/brw_eu_emit.c | 3 ++- src/mesa/drivers/dri/i965/brw_wm_emit.c | 33 ++++++++++++++++++++++----------- 3 files changed, 29 insertions(+), 17 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index 30603bdd0e..39eb88d7c2 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -170,11 +170,11 @@ static INLINE struct brw_reg brw_reg( GLuint file, GLuint writemask ) { struct brw_reg reg; - if (type == BRW_GENERAL_REGISTER_FILE) + if (file == BRW_GENERAL_REGISTER_FILE) assert(nr < BRW_MAX_GRF); - else if (type == BRW_MESSAGE_REGISTER_FILE) - assert(nr < BRW_MAX_MRF); - else if (type == BRW_ARCHITECTURE_REGISTER_FILE) + else if (file == BRW_MESSAGE_REGISTER_FILE) + assert((nr & ~(1 << 7)) < BRW_MAX_MRF); + else if (file == BRW_ARCHITECTURE_REGISTER_FILE) assert(nr <= BRW_ARF_IP); reg.type = type; @@ -538,7 +538,7 @@ static INLINE struct brw_reg brw_mask_reg( GLuint subnr ) static INLINE struct brw_reg brw_message_reg( GLuint nr ) { - assert(nr < BRW_MAX_MRF); + assert((nr & ~(1 << 7)) < BRW_MAX_MRF); return brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, nr, 0); diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 241cdc33f8..7ceabba288 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -55,7 +55,8 @@ static void guess_execution_size( struct brw_instruction *insn, static void brw_set_dest( struct brw_instruction *insn, struct brw_reg dest ) { - if (dest.type != BRW_ARCHITECTURE_REGISTER_FILE) + if (dest.file != BRW_ARCHITECTURE_REGISTER_FILE && + dest.file != BRW_MESSAGE_REGISTER_FILE) assert(dest.nr < 128); insn->bits1.da1.dest_reg_file = dest.file; diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 9cd1fedacb..eb37ea1864 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1105,6 +1105,7 @@ void emit_fb_write(struct brw_wm_compile *c, GLuint eot) { struct brw_compile *p = &c->func; + struct brw_context *brw = p->brw; GLuint nr = 2; GLuint channel; @@ -1119,18 +1120,28 @@ void emit_fb_write(struct brw_wm_compile *c, brw_push_insn_state(p); for (channel = 0; channel < 4; channel++) { - /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ - /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ - brw_set_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, - brw_message_reg(nr + channel), - arg0[channel]); - - if (c->dispatch_width == 16) { - brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); + if (c->dispatch_width == 16 && (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))) { + /* By setting the high bit of the MRF register number, we indicate + * that we want COMPR4 mode - instead of doing the usual destination + * + 1 for the second half we get destination + 4. + */ brw_MOV(p, - brw_message_reg(nr + channel + 4), - sechalf(arg0[channel])); + brw_message_reg(nr + channel + (1 << 7)), + arg0[channel]); + } else { + /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */ + /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */ + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + brw_MOV(p, + brw_message_reg(nr + channel), + arg0[channel]); + + if (c->dispatch_width == 16) { + brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF); + brw_MOV(p, + brw_message_reg(nr + channel + 4), + sechalf(arg0[channel])); + } } } /* skip over the regs populated above: -- cgit v1.2.3 From d52d78b4bcd6d4c0578f972c0b8ebac09e632196 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 10 Nov 2009 10:43:19 -0800 Subject: i965: Allow use of PROGRAM_LOCAL constants in ARB_vp. Fixes piglit arl.vp. --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 1638ef8111..604d63d5f2 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -912,6 +912,7 @@ get_src_reg( struct brw_vs_compile *c, case PROGRAM_CONSTANT: case PROGRAM_UNIFORM: case PROGRAM_ENV_PARAM: + case PROGRAM_LOCAL_PARAM: if (c->vp->use_const_buffer) { return get_constant(c, inst, argIndex); } @@ -930,7 +931,6 @@ get_src_reg( struct brw_vs_compile *c, /* this is a normal case since we loop over all three src args */ return brw_null_reg(); - case PROGRAM_LOCAL_PARAM: case PROGRAM_WRITE_ONLY: default: assert(0); -- cgit v1.2.3 From 56ab92bad8f1d05bc22b8a8471d5aeb663f220de Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 10 Nov 2009 10:54:15 -0800 Subject: i965: Unalias src/dst registers for SGE and friends. Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 40 +++++++++++++++++---------------- 1 file changed, 21 insertions(+), 19 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 604d63d5f2..15154c3b8e 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -331,63 +331,65 @@ static void unalias3( struct brw_vs_compile *c, } } -static void emit_sop( struct brw_compile *p, +static void emit_sop( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1, GLuint cond) { + struct brw_compile *p = &c->func; + brw_MOV(p, dst, brw_imm_f(0.0f)); brw_CMP(p, brw_null_reg(), cond, arg0, arg1); brw_MOV(p, dst, brw_imm_f(1.0f)); brw_set_predicate_control_flag_value(p, 0xff); } -static void emit_seq( struct brw_compile *p, +static void emit_seq( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_EQ); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_EQ); } -static void emit_sne( struct brw_compile *p, +static void emit_sne( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_NEQ); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_NEQ); } -static void emit_slt( struct brw_compile *p, +static void emit_slt( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_L); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_L); } -static void emit_sle( struct brw_compile *p, +static void emit_sle( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_LE); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_LE); } -static void emit_sgt( struct brw_compile *p, +static void emit_sgt( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_G); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_G); } -static void emit_sge( struct brw_compile *p, +static void emit_sge( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_GE); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_GE); } static void emit_max( struct brw_compile *p, @@ -1473,25 +1475,25 @@ void brw_vs_emit(struct brw_vs_compile *c ) break; case OPCODE_SEQ: - emit_seq(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_seq); break; case OPCODE_SIN: emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, args[0], BRW_MATH_PRECISION_FULL); break; case OPCODE_SNE: - emit_sne(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sne); break; case OPCODE_SGE: - emit_sge(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sge); break; case OPCODE_SGT: - emit_sgt(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sgt); break; case OPCODE_SLT: - emit_slt(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_slt); break; case OPCODE_SLE: - emit_sle(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sle); break; case OPCODE_SUB: brw_ADD(p, dst, args[0], negate(args[1])); -- cgit v1.2.3 From eb6a1f8a00596156cd7164838ef9e9a5b39e7254 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 10 Nov 2009 13:57:29 -0800 Subject: i965: Add a note explaining the data cache domain. --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 0bf735c0f2..e2f0a383e7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -358,7 +358,10 @@ brw_create_constant_surface( struct brw_context *brw, NULL, NULL); if (key->bo) { - /* Emit relocation to surface contents */ + /* Emit relocation to surface contents. Section 5.1.1 of the gen4 + * bspec ("Data Cache") says that the data cache does not exist as + * a separate cache and is just the sampler cache. + */ dri_bo_emit_reloc(bo, I915_GEM_DOMAIN_SAMPLER, 0, 0, -- cgit v1.2.3 From c5413839b3e99c7b162f1260142f3c175502b0ce Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 10 Nov 2009 15:51:29 -0800 Subject: i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile. For an app that's blowing out the state cache, like sauerbraten, the memset of the giant arrays ended up taking 11% of the CPU even when only a "few" of the entries got used. With this, the WM program compile drops back down to 1% of CPU time. Bug #24981 (bisected to BRW_WM_MAX_INSN increase). --- src/mesa/drivers/dri/i965/brw_wm.c | 14 ++++++++++++++ src/mesa/drivers/dri/i965/brw_wm.h | 8 ++++---- src/mesa/drivers/dri/i965/brw_wm_fp.c | 2 ++ src/mesa/drivers/dri/i965/brw_wm_pass0.c | 3 +++ 4 files changed, 23 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 964ee104c2..d8971321f3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -152,8 +152,22 @@ static void do_wm_prog( struct brw_context *brw, */ return; } + c->instruction = _mesa_calloc(BRW_WM_MAX_INSN * sizeof(*c->instruction)); + c->prog_instructions = _mesa_calloc(BRW_WM_MAX_INSN * + sizeof(*c->prog_instructions)); + c->vreg = _mesa_calloc(BRW_WM_MAX_VREG * sizeof(*c->vreg)); + c->refs = _mesa_calloc(BRW_WM_MAX_REF * sizeof(*c->refs)); + c->vreg = _mesa_calloc(BRW_WM_MAX_VREG * sizeof(*c->vreg)); } else { + void *instruction = c->instruction; + void *prog_instructions = c->prog_instructions; + void *vreg = c->vreg; + void *refs = c->refs; memset(c, 0, sizeof(*brw->wm.compile_data)); + c->instruction = instruction; + c->prog_instructions = prog_instructions; + c->vreg = vreg; + c->refs = refs; } memcpy(&c->key, key, sizeof(*key)); diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 1fa2f1c06c..7db212e392 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -202,7 +202,7 @@ struct brw_wm_compile { * simplifying and adding instructions for interpolation and * framebuffer writes. */ - struct prog_instruction prog_instructions[BRW_WM_MAX_INSN]; + struct prog_instruction *prog_instructions; GLuint nr_fp_insns; GLuint fp_temp; GLuint fp_interp_emitted; @@ -213,7 +213,7 @@ struct brw_wm_compile { struct prog_src_register pixel_w; - struct brw_wm_value vreg[BRW_WM_MAX_VREG]; + struct brw_wm_value *vreg; GLuint nr_vreg; struct brw_wm_value creg[BRW_WM_MAX_PARAM]; @@ -230,10 +230,10 @@ struct brw_wm_compile { struct brw_wm_ref undef_ref; struct brw_wm_value undef_value; - struct brw_wm_ref refs[BRW_WM_MAX_REF]; + struct brw_wm_ref *refs; GLuint nr_refs; - struct brw_wm_instruction instruction[BRW_WM_MAX_INSN]; + struct brw_wm_instruction *instruction; GLuint nr_insns; struct brw_wm_constref constref[BRW_WM_MAX_CONST]; diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 549afd31de..1c4f62ba48 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -182,6 +182,8 @@ static void release_temp( struct brw_wm_compile *c, struct prog_dst_register tem static struct prog_instruction *get_fp_inst(struct brw_wm_compile *c) { assert(c->nr_fp_insns < BRW_WM_MAX_INSN); + memset(&c->prog_instructions[c->nr_fp_insns], 0, + sizeof(*c->prog_instructions)); return &c->prog_instructions[c->nr_fp_insns++]; } diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass0.c b/src/mesa/drivers/dri/i965/brw_wm_pass0.c index 602b1351ef..ff4c082d5e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass0.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass0.c @@ -42,12 +42,14 @@ static struct brw_wm_ref *get_ref( struct brw_wm_compile *c ) { assert(c->nr_refs < BRW_WM_MAX_REF); + memset(&c->refs[c->nr_refs], 0, sizeof(*c->refs)); return &c->refs[c->nr_refs++]; } static struct brw_wm_value *get_value( struct brw_wm_compile *c) { assert(c->nr_refs < BRW_WM_MAX_VREG); + memset(&c->vreg[c->nr_vreg], 0, sizeof(*c->vreg)); return &c->vreg[c->nr_vreg++]; } @@ -55,6 +57,7 @@ static struct brw_wm_value *get_value( struct brw_wm_compile *c) static struct brw_wm_instruction *get_instruction( struct brw_wm_compile *c ) { assert(c->nr_insns < BRW_WM_MAX_INSN); + memset(&c->instruction[c->nr_insns], 0, sizeof(*c->instruction)); return &c->instruction[c->nr_insns++]; } -- cgit v1.2.3 From 23a4a6727efb5c8b2bf84f88f638c15e7255b363 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 10 Nov 2009 10:43:19 -0800 Subject: i965: Allow use of PROGRAM_LOCAL constants in ARB_vp. Fixes piglit arl.vp. (cherry picked from commit d52d78b4bcd6d4c0578f972c0b8ebac09e632196) --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 108e19cdbc..ec1f22c92d 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -912,6 +912,7 @@ get_src_reg( struct brw_vs_compile *c, case PROGRAM_CONSTANT: case PROGRAM_UNIFORM: case PROGRAM_ENV_PARAM: + case PROGRAM_LOCAL_PARAM: if (c->vp->use_const_buffer) { return get_constant(c, inst, argIndex); } @@ -930,7 +931,6 @@ get_src_reg( struct brw_vs_compile *c, /* this is a normal case since we loop over all three src args */ return brw_null_reg(); - case PROGRAM_LOCAL_PARAM: case PROGRAM_WRITE_ONLY: default: assert(0); -- cgit v1.2.3 From e5ffb9f5ea03c2acd148222259a334cde0f3afc9 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 10 Nov 2009 10:54:15 -0800 Subject: i965: Unalias src/dst registers for SGE and friends. Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 (cherry picked from commit 56ab92bad8f1d05bc22b8a8471d5aeb663f220de) --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 40 +++++++++++++++++---------------- 1 file changed, 21 insertions(+), 19 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index ec1f22c92d..a4f34660de 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -331,63 +331,65 @@ static void unalias3( struct brw_vs_compile *c, } } -static void emit_sop( struct brw_compile *p, +static void emit_sop( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1, GLuint cond) { + struct brw_compile *p = &c->func; + brw_MOV(p, dst, brw_imm_f(0.0f)); brw_CMP(p, brw_null_reg(), cond, arg0, arg1); brw_MOV(p, dst, brw_imm_f(1.0f)); brw_set_predicate_control_flag_value(p, 0xff); } -static void emit_seq( struct brw_compile *p, +static void emit_seq( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_EQ); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_EQ); } -static void emit_sne( struct brw_compile *p, +static void emit_sne( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_NEQ); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_NEQ); } -static void emit_slt( struct brw_compile *p, +static void emit_slt( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_L); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_L); } -static void emit_sle( struct brw_compile *p, +static void emit_sle( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_LE); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_LE); } -static void emit_sgt( struct brw_compile *p, +static void emit_sgt( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_G); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_G); } -static void emit_sge( struct brw_compile *p, +static void emit_sge( struct brw_vs_compile *c, struct brw_reg dst, struct brw_reg arg0, struct brw_reg arg1 ) { - emit_sop(p, dst, arg0, arg1, BRW_CONDITIONAL_GE); + emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_GE); } static void emit_max( struct brw_compile *p, @@ -1453,25 +1455,25 @@ void brw_vs_emit(struct brw_vs_compile *c ) break; case OPCODE_SEQ: - emit_seq(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_seq); break; case OPCODE_SIN: emit_math1(c, BRW_MATH_FUNCTION_SIN, dst, args[0], BRW_MATH_PRECISION_FULL); break; case OPCODE_SNE: - emit_sne(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sne); break; case OPCODE_SGE: - emit_sge(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sge); break; case OPCODE_SGT: - emit_sgt(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sgt); break; case OPCODE_SLT: - emit_slt(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_slt); break; case OPCODE_SLE: - emit_sle(p, dst, args[0], args[1]); + unalias2(c, dst, args[0], args[1], emit_sle); break; case OPCODE_SUB: brw_ADD(p, dst, args[0], negate(args[1])); -- cgit v1.2.3 From 1220aba99bc78290bb89ade649719508e3031e4b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 10 Nov 2009 14:11:46 -0800 Subject: i965: Fix VS constant buffer value loading. Previously, we'd load linearly from ParameterValues[0] for the constants, though ParameterValues[1] may not equal ParameterValues[0] + 4. Additionally, the STATE_VAL type paramters didn't get updated. Fixes piglit vp-constant-array-huge.vpfp and ET:QW object locations. Bug #23226. --- src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index 89f47522a1..746d097d23 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -53,6 +53,7 @@ brw_vs_update_constant_buffer(struct brw_context *brw) const struct gl_program_parameter_list *params = vp->program.Base.Parameters; const int size = params->NumParameters * 4 * sizeof(GLfloat); drm_intel_bo *const_buffer; + int i; /* BRW_NEW_VERTEX_PROGRAM */ if (!vp->use_const_buffer) @@ -62,7 +63,16 @@ brw_vs_update_constant_buffer(struct brw_context *brw) size, 64); /* _NEW_PROGRAM_CONSTANTS */ - dri_bo_subdata(const_buffer, 0, size, params->ParameterValues); + + /* Updates the ParamaterValues[i] pointers for all parameters of the + * basic type of PROGRAM_STATE_VAR. + */ + _mesa_load_state_parameters(&brw->intel.ctx, vp->program.Base.Parameters); + + for (i = 0; i < params->NumParameters; i++) { + dri_bo_subdata(const_buffer, i * 4 * sizeof(float), 4 * sizeof(float), + params->ParameterValues[i]); + } return const_buffer; } -- cgit v1.2.3 From ab12e764ba3f57ad9f0d7252262cfc6e07839928 Mon Sep 17 00:00:00 2001 From: Roland Scheidegger Date: Wed, 11 Nov 2009 17:57:56 -0800 Subject: i965: fix EXT_provoking_vertex support This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage. --- src/mesa/drivers/dri/i965/brw_clip.c | 1 + src/mesa/drivers/dri/i965/brw_clip.h | 7 +++--- src/mesa/drivers/dri/i965/brw_clip_line.c | 8 +++++-- src/mesa/drivers/dri/i965/brw_clip_tri.c | 12 +++++++--- src/mesa/drivers/dri/i965/brw_gs.c | 10 +++++--- src/mesa/drivers/dri/i965/brw_gs.h | 7 +++--- src/mesa/drivers/dri/i965/brw_gs_emit.c | 38 ++++++++++++++++++++++--------- src/mesa/drivers/dri/i965/brw_sf_state.c | 7 +++--- 8 files changed, 61 insertions(+), 29 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index 20a927cf38..f45dcf8282 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -156,6 +156,7 @@ static void upload_clip_prog(struct brw_context *brw) key.attrs = brw->vs.prog_data->outputs_written; /* _NEW_LIGHT */ key.do_flat_shading = (ctx->Light.ShadeModel == GL_FLAT); + key.pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION); /* _NEW_TRANSFORM */ key.nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled); diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h index 957df441ab..dc550ac793 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.h +++ b/src/mesa/drivers/dri/i965/brw_clip.h @@ -46,18 +46,17 @@ struct brw_clip_prog_key { GLuint primitive:4; GLuint nr_userclip:3; GLuint do_flat_shading:1; + GLuint pv_first:1; GLuint do_unfilled:1; GLuint fill_cw:2; /* includes cull information */ GLuint fill_ccw:2; /* includes cull information */ GLuint offset_cw:1; GLuint offset_ccw:1; - GLuint pad0:17; - GLuint copy_bfc_cw:1; GLuint copy_bfc_ccw:1; GLuint clip_mode:3; - GLuint pad1:27; - + GLuint pad0:11; + GLfloat offset_factor; GLfloat offset_units; }; diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 048ca620fa..fa9648f50f 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -269,8 +269,12 @@ void brw_emit_line_clip( struct brw_clip_compile *c ) brw_clip_line_alloc_regs(c); brw_clip_init_ff_sync(c); - if (c->key.do_flat_shading) - brw_clip_copy_colors(c, 0, 1); + if (c->key.do_flat_shading) { + if (c->key.pv_first) + brw_clip_copy_colors(c, 1, 0); + else + brw_clip_copy_colors(c, 0, 1); + } clip_and_emit_line(c); } diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index 0efd77225e..cf79224be4 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -188,14 +188,20 @@ void brw_clip_tri_flat_shade( struct brw_clip_compile *c ) brw_imm_ud(_3DPRIM_POLYGON)); is_poly = brw_IF(p, BRW_EXECUTE_1); - { + { brw_clip_copy_colors(c, 1, 0); brw_clip_copy_colors(c, 2, 0); } is_poly = brw_ELSE(p, is_poly); { - brw_clip_copy_colors(c, 0, 2); - brw_clip_copy_colors(c, 1, 2); + if (c->key.pv_first) { + brw_clip_copy_colors(c, 1, 0); + brw_clip_copy_colors(c, 2, 0); + } + else { + brw_clip_copy_colors(c, 0, 2); + brw_clip_copy_colors(c, 1, 2); + } } brw_ENDIF(p, is_poly); } diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 48c2b9a41c..610b6c35e2 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -85,10 +85,10 @@ static void compile_gs_prog( struct brw_context *brw, */ switch (key->primitive) { case GL_QUADS: - brw_gs_quads( &c ); + brw_gs_quads( &c, key ); break; case GL_QUAD_STRIP: - brw_gs_quad_strip( &c ); + brw_gs_quad_strip( &c, key ); break; case GL_LINE_LOOP: brw_gs_lines( &c ); @@ -149,6 +149,7 @@ static const GLenum gs_prim[GL_POLYGON+1] = { static void populate_key( struct brw_context *brw, struct brw_gs_prog_key *key ) { + GLcontext *ctx = &brw->intel.ctx; memset(key, 0, sizeof(*key)); /* CACHE_NEW_VS_PROG */ @@ -158,6 +159,9 @@ static void populate_key( struct brw_context *brw, key->primitive = gs_prim[brw->primitive]; key->hint_gs_always = 0; /* debug code? */ + + /* _NEW_LIGHT */ + key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION); key->need_gs_prog = (key->hint_gs_always || brw->primitive == GL_QUADS || @@ -193,7 +197,7 @@ static void prepare_gs_prog(struct brw_context *brw) const struct brw_tracked_state brw_gs_prog = { .dirty = { - .mesa = 0, + .mesa = _NEW_LIGHT, .brw = BRW_NEW_PRIMITIVE, .cache = CACHE_NEW_VS_PROG }, diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index bbb991ea2e..e0cf07256b 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -43,8 +43,9 @@ struct brw_gs_prog_key { GLuint attrs:32; GLuint primitive:4; GLuint hint_gs_always:1; + GLuint pv_first:1; GLuint need_gs_prog:1; - GLuint pad:26; + GLuint pad:25; }; struct brw_gs_compile { @@ -67,8 +68,8 @@ struct brw_gs_compile { #define ATTR_SIZE (4*4) -void brw_gs_quads( struct brw_gs_compile *c ); -void brw_gs_quad_strip( struct brw_gs_compile *c ); +void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ); +void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ); void brw_gs_tris( struct brw_gs_compile *c ); void brw_gs_lines( struct brw_gs_compile *c ); void brw_gs_points( struct brw_gs_compile *c ); diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index a9b2aa2eac..0fc5b02c61 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -120,7 +120,7 @@ static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim) } -void brw_gs_quads( struct brw_gs_compile *c ) +void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) { brw_gs_alloc_regs(c, 4); @@ -128,23 +128,39 @@ void brw_gs_quads( struct brw_gs_compile *c ) * is the PV for quads, but vertex 0 for polygons: */ if (c->need_ff_sync) - brw_gs_ff_sync(c, 1); - brw_gs_emit_vue(c, c->reg.vertex[3], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); - brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); - brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_POLYGON << 2)); - brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); + brw_gs_ff_sync(c, 1); + if (key->pv_first) { + brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); + brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[2], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[3], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); + } + else { + brw_gs_emit_vue(c, c->reg.vertex[3], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); + brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[2], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); + } } -void brw_gs_quad_strip( struct brw_gs_compile *c ) +void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) { brw_gs_alloc_regs(c, 4); if (c->need_ff_sync) brw_gs_ff_sync(c, 1); - brw_gs_emit_vue(c, c->reg.vertex[2], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); - brw_gs_emit_vue(c, c->reg.vertex[3], 0, (_3DPRIM_POLYGON << 2)); - brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); - brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); + if (key->pv_first) { + brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); + brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[2], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[3], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); + } + else { + brw_gs_emit_vue(c, c->reg.vertex[2], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); + brw_gs_emit_vue(c, c->reg.vertex[3], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[0], 0, (_3DPRIM_POLYGON << 2)); + brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_POLYGON << 2) | R02_PRIM_END)); + } } void brw_gs_tris( struct brw_gs_compile *c ) diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index bc0f076073..79f37097d3 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -113,7 +113,8 @@ struct brw_sf_unit_key { unsigned int nr_urb_entries, urb_size, sfsize; - GLenum front_face, cull_face, provoking_vertex; + GLenum front_face, cull_face; + unsigned pv_first:1; unsigned scissor:1; unsigned line_smooth:1; unsigned point_sprite:1; @@ -154,7 +155,7 @@ sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key) key->point_attenuated = ctx->Point._Attenuated; /* _NEW_LIGHT */ - key->provoking_vertex = ctx->Light.ProvokingVertex; + key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION); key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0; } @@ -287,7 +288,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons: */ - if (key->provoking_vertex == GL_LAST_VERTEX_CONVENTION) { + if (!key->pv_first) { sf.sf7.trifan_pv = 2; sf.sf7.linestrip_pv = 1; sf.sf7.tristrip_pv = 2; -- cgit v1.2.3 From 5f305b1db925c819ddeb29a75f6fbad6500a2d11 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 11 Nov 2009 14:49:03 -0800 Subject: i965: Fix VBO last-valid-offset setup on Ironlake. Instead of doing math based on the (broken for VBO && offset != 0) input->count number, just use the BO size. Fixes assertion failure in ETQW. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 348c66154f..2b1347b698 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -536,16 +536,9 @@ static void brw_emit_vertices(struct brw_context *brw) I915_GEM_DOMAIN_VERTEX, 0, input->offset); if (BRW_IS_IGDNG(brw)) { - if (input->stride) { - OUT_RELOC(input->bo, - I915_GEM_DOMAIN_VERTEX, 0, - input->offset + input->stride * input->count - 1); - } else { - assert(input->count == 1); - OUT_RELOC(input->bo, - I915_GEM_DOMAIN_VERTEX, 0, - input->offset + input->element_size - 1); - } + OUT_RELOC(input->bo, + I915_GEM_DOMAIN_VERTEX, 0, + input->bo->size - 1); } else OUT_BATCH(input->stride ? input->count : 0); OUT_BATCH(0); /* Instance data step rate */ -- cgit v1.2.3 From 514544f373b6e6fae11b7b4426949b8ad64c441b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 12 Nov 2009 09:08:50 -0800 Subject: i965: Fix Ironlake shadow comparisons. The cube map array index arg is always present. --- src/mesa/drivers/dri/i965/brw_wm_emit.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 268f7965c0..9b1f54414b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -745,22 +745,32 @@ static void emit_tex( struct brw_wm_compile *c, abort(); } - if (inst->tex_shadow) { - nr = 4; - emit |= WRITEMASK_W; - } + /* For shadow comparisons, we have to supply u,v,r. */ + if (inst->tex_shadow) + nr = 3; msgLength = 1; for (i = 0; i < nr; i++) { - static const GLuint swz[4] = {0,1,2,2}; - if (emit & (1<brw) && inst->tex_shadow) { + brw_MOV(p, brw_message_reg(msgLength+1), brw_imm_f(0)); + msgLength += 2; + } + + /* Fill in the shadow comparison reference value. */ + if (inst->tex_shadow) { + brw_MOV(p, brw_message_reg(msgLength+1), arg[2]); + msgLength += 2; + } + responseLength = 8; /* always */ if (BRW_IS_IGDNG(p->brw)) { -- cgit v1.2.3 From 91bd593109c71310fb7e101c5f73a14f1bbd5f93 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 11 Nov 2009 11:58:12 -0800 Subject: i965: Avoid moving the current value back into the accumulator for MAD. This is a 2.9% (+/-.3%) performance win for my GL demo, which hits MAD sequences for matrix transforms. --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 35 ++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 15154c3b8e..f7b0726636 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1271,6 +1271,38 @@ post_vs_emit( struct brw_vs_compile *c, } } +static GLboolean +accumulator_contains(struct brw_vs_compile *c, struct brw_reg val) +{ + struct brw_compile *p = &c->func; + struct brw_instruction *prev_insn = &p->store[p->nr_insn - 1]; + + if (p->nr_insn == 0) + return GL_FALSE; + + if (val.address_mode != BRW_ADDRESS_DIRECT) + return GL_FALSE; + + switch (prev_insn->header.opcode) { + case BRW_OPCODE_MOV: + case BRW_OPCODE_MAC: + case BRW_OPCODE_MUL: + if (prev_insn->header.access_mode == BRW_ALIGN_16 && + prev_insn->header.execution_size == val.width && + prev_insn->bits1.da1.dest_reg_file == val.file && + prev_insn->bits1.da1.dest_reg_type == val.type && + prev_insn->bits1.da1.dest_address_mode == val.address_mode && + prev_insn->bits1.da1.dest_reg_nr == val.nr && + prev_insn->bits1.da16.dest_subreg_nr == val.subnr / 16 && + prev_insn->bits1.da16.dest_writemask == 0xf) + return GL_TRUE; + else + return GL_FALSE; + default: + return GL_FALSE; + } +} + static uint32_t get_predicate(const struct prog_instruction *inst) { @@ -1449,7 +1481,8 @@ void brw_vs_emit(struct brw_vs_compile *c ) unalias3(c, dst, args[0], args[1], args[2], emit_lrp_noalias); break; case OPCODE_MAD: - brw_MOV(p, brw_acc_reg(), args[2]); + if (!accumulator_contains(c, args[2])) + brw_MOV(p, brw_acc_reg(), args[2]); brw_MAC(p, dst, args[0], args[1]); break; case OPCODE_MAX: -- cgit v1.2.3 From 4e50ce35ee1376062de2c6fa69da144be30a61e2 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 11 Nov 2009 15:29:34 -0800 Subject: i965: Clean up Ironlake sampler type definitions. They're the same regardless of execution width for 8, 4x2, and 16. --- src/mesa/drivers/dri/i965/brw_defines.h | 16 ++++------------ src/mesa/drivers/dri/i965/brw_wm_emit.c | 6 +++--- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 6 +++--- 3 files changed, 10 insertions(+), 18 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 78d457ad2b..c19510bbd4 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -673,18 +673,10 @@ #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_IGDNG 0 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_IGDNG 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_IGDNG 0 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_IGDNG 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_BIAS_IGDNG 1 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS_IGDNG 1 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_IGDNG 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_IGDNG 2 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD_IGDNG 2 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_COMPARE_IGDNG 3 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE_IGDNG 3 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE_IGDNG 3 +#define BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG 0 +#define BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG 1 +#define BRW_SAMPLER_MESSAGE_SAMPLE_LOD_IGDNG 2 +#define BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG 3 /* for IGDNG only */ #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index eb37ea1864..abad5d2692 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -875,9 +875,9 @@ static void emit_tex( struct brw_wm_compile *c, if (BRW_IS_IGDNG(p->brw)) { if (inst->tex_shadow) - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE_IGDNG; + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG; else - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_IGDNG; + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG; } else { if (inst->tex_shadow) msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; @@ -939,7 +939,7 @@ static void emit_txb( struct brw_wm_compile *c, msgLength = 9; if (BRW_IS_IGDNG(p->brw)) - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS_IGDNG; + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG; else msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 9d3bc66f49..42a13fc80f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1850,7 +1850,7 @@ static void emit_txb(struct brw_wm_compile *c, brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); /* ref (unused?) */ if (BRW_IS_IGDNG(p->brw)) { - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_IGDNG; + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG; } else { /* Does it work well on SIMD8? */ msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; @@ -1932,9 +1932,9 @@ static void emit_tex(struct brw_wm_compile *c, if (BRW_IS_IGDNG(p->brw)) { if (shadow) - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_COMPARE_IGDNG; + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG; else - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_IGDNG; + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG; } else { /* Does it work for shadow on SIMD8 ? */ msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; -- cgit v1.2.3 From 8e8586e62671e8337c08b086bf7f3c54cc46191d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 12 Nov 2009 14:05:18 -0800 Subject: i965: Validate the number of URB entries selected for the VS. --- src/mesa/drivers/dri/i965/brw_vs_state.c | 37 ++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index d790ab6555..7285466645 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -109,10 +109,39 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) vs.thread3.urb_entry_read_offset = 0; vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; - if (BRW_IS_IGDNG(brw)) - vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2; - else - vs.thread4.nr_urb_entries = key->nr_urb_entries; + if (BRW_IS_IGDNG(brw)) { + switch (key->nr_urb_entries) { + case 8: + case 12: + case 16: + case 32: + case 64: + case 96: + case 128: + case 168: + case 192: + case 224: + case 256: + vs.thread4.nr_urb_entries = key->nr_urb_entries >> 2; + break; + default: + assert(0); + } + } else { + switch (key->nr_urb_entries) { + case 8: + case 12: + case 16: + case 32: + break; + case 64: + assert(BRW_IS_G4X(brw)); + break; + default: + assert(0); + } + vs.thread4.nr_urb_entries = key->nr_urb_entries; + } vs.thread4.urb_entry_allocation_size = key->urb_size - 1; -- cgit v1.2.3 From ded0ec1ea5db8e08b0bec8ac0d9d30f98e360003 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 12 Nov 2009 14:57:30 -0800 Subject: i965: Use bo_map instead of subdata to upload the bits of constant buffer. Saves CPU time, resulting in a 2.5% FPS win on ETQW. --- src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 7 +++++-- src/mesa/drivers/dri/intel/intel_context.h | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index 5dac632969..3bc9840a97 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -68,10 +68,13 @@ brw_vs_update_constant_buffer(struct brw_context *brw) */ _mesa_load_state_parameters(&brw->intel.ctx, vp->program.Base.Parameters); + intel_bo_map_gtt_preferred(intel, const_buffer, GL_TRUE); for (i = 0; i < params->NumParameters; i++) { - dri_bo_subdata(const_buffer, i * 4 * sizeof(float), 4 * sizeof(float), - params->ParameterValues[i]); + memcpy(const_buffer->virtual + i * 4 * sizeof(float), + params->ParameterValues[i], + 4 * sizeof(float)); } + intel_bo_unmap_gtt_preferred(intel, const_buffer); return const_buffer; } diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 84fbfc564c..8936f757a4 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -590,4 +590,25 @@ is_power_of_two(uint32_t value) return (value & (value - 1)) == 0; } +static inline void +intel_bo_map_gtt_preferred(struct intel_context *intel, + drm_intel_bo *bo, + GLboolean write) +{ + if (intel->intelScreen->kernel_exec_fencing) + drm_intel_gem_bo_map_gtt(bo); + else + drm_intel_bo_map(bo, write); +} + +static inline void +intel_bo_unmap_gtt_preferred(struct intel_context *intel, + drm_intel_bo *bo) +{ + if (intel->intelScreen->kernel_exec_fencing) + drm_intel_gem_bo_unmap_gtt(bo); + else + drm_intel_bo_unmap(bo); +} + #endif -- cgit v1.2.3 From b54f8eeae8e7f5c5b43cb17255fee70227713c9c Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 12 Nov 2009 17:48:55 -0800 Subject: i965: Remove long dead structures for ffvertex_prog.c. --- src/mesa/drivers/dri/i965/brw_context.h | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index e01930a4a0..2681913a90 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -412,23 +412,6 @@ struct brw_vertex_info { GLuint sizes[ATTRIB_BIT_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */ }; - - - -/* Cache for TNL programs. - */ -struct brw_tnl_cache_item { - GLuint hash; - void *key; - void *data; - struct brw_tnl_cache_item *next; -}; - -struct brw_tnl_cache { - struct brw_tnl_cache_item **items; - GLuint size, n_items; -}; - struct brw_query_object { struct gl_query_object Base; -- cgit v1.2.3 From 3727858ceb324c955b00ae29b8c1e12f47060fce Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 12 Nov 2009 18:27:12 -0800 Subject: i965: Remove an unused cache_item field. --- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_state_cache.c | 1 - src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +- 3 files changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 2681913a90..87e8a6aad4 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -320,7 +320,6 @@ struct brw_cache_item { GLuint nr_reloc_bufs; dri_bo *bo; - GLuint data_size; struct brw_cache_item *next; }; diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c b/src/mesa/drivers/dri/i965/brw_state_cache.c index d2ab624783..e4c9ba7d87 100644 --- a/src/mesa/drivers/dri/i965/brw_state_cache.c +++ b/src/mesa/drivers/dri/i965/brw_state_cache.c @@ -245,7 +245,6 @@ brw_upload_cache( struct brw_cache *cache, item->bo = bo; dri_bo_reference(bo); - item->data_size = data_size; if (cache->n_items > cache->size * 1.5) rehash(cache); diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index bb21dd5ed9..4b5fe7be9f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -109,7 +109,7 @@ do_copy_texsubimage(struct intel_context *intel, return GL_FALSE; } - intelFlush(ctx); + // intelFlush(ctx); LOCK_HARDWARE(intel); { drm_intel_bo *dst_bo = intel_region_buffer(intel, -- cgit v1.2.3 From 99077e77927ec26edf85bfef81a6d433171c3a1e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 12 Nov 2009 20:08:44 -0800 Subject: i965: Flag BRW_NEW_CONTEXT on some context state. Fixing this is a prereq for avoiding flagging all state at new batch time. Eliminating that still causes problems, though (notably glean logicOp fails on my GM965). --- src/mesa/drivers/dri/i965/brw_curbe.c | 2 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index 4be6c77aa1..aadcfbe2da 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -130,7 +130,7 @@ static void calculate_curbe_offsets( struct brw_context *brw ) const struct brw_tracked_state brw_curbe_offsets = { .dirty = { .mesa = _NEW_TRANSFORM, - .brw = BRW_NEW_VERTEX_PROGRAM, + .brw = BRW_NEW_VERTEX_PROGRAM | BRW_NEW_CONTEXT, .cache = CACHE_NEW_WM_PROG }, .prepare = calculate_curbe_offsets diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index ea71857548..4b0d598336 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -66,7 +66,7 @@ static void upload_blend_constant_color(struct brw_context *brw) const struct brw_tracked_state brw_blend_constant_color = { .dirty = { .mesa = _NEW_COLOR, - .brw = 0, + .brw = BRW_NEW_CONTEXT, .cache = 0 }, .emit = upload_blend_constant_color @@ -93,7 +93,7 @@ static void upload_drawing_rect(struct brw_context *brw) const struct brw_tracked_state brw_drawing_rect = { .dirty = { .mesa = _NEW_BUFFERS, - .brw = 0, + .brw = BRW_NEW_CONTEXT, .cache = 0 }, .emit = upload_drawing_rect @@ -317,7 +317,7 @@ static void upload_polygon_stipple(struct brw_context *brw) const struct brw_tracked_state brw_polygon_stipple = { .dirty = { .mesa = _NEW_POLYGONSTIPPLE, - .brw = 0, + .brw = BRW_NEW_CONTEXT, .cache = 0 }, .emit = upload_polygon_stipple @@ -362,7 +362,7 @@ static void upload_polygon_stipple_offset(struct brw_context *brw) const struct brw_tracked_state brw_polygon_stipple_offset = { .dirty = { .mesa = _NEW_WINDOW_POS, - .brw = 0, + .brw = BRW_NEW_CONTEXT, .cache = 0 }, .emit = upload_polygon_stipple_offset @@ -425,7 +425,7 @@ static void upload_line_stipple(struct brw_context *brw) const struct brw_tracked_state brw_line_stipple = { .dirty = { .mesa = _NEW_LINE, - .brw = 0, + .brw = BRW_NEW_CONTEXT, .cache = 0 }, .emit = upload_line_stipple -- cgit v1.2.3 From a0fd49b33455317466a75ec77eb292f41d6021d7 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 13 Nov 2009 15:16:17 -0800 Subject: i965: Clean up emit_tex a bit. --- src/mesa/drivers/dri/i965/brw_wm_emit.c | 51 ++++++++++++++++----------------- 1 file changed, 24 insertions(+), 27 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index d91fad0f45..a47bf3f667 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -828,8 +828,8 @@ static void emit_tex( struct brw_wm_compile *c, struct brw_reg *arg ) { struct brw_compile *p = &c->func; - GLuint msgLength, responseLength; - GLuint i, nr; + GLuint cur_mrf = 2, response_length; + GLuint i, nr_texcoords; GLuint emit; GLuint msg_type; @@ -838,17 +838,17 @@ static void emit_tex( struct brw_wm_compile *c, switch (inst->tex_idx) { case TEXTURE_1D_INDEX: emit = WRITEMASK_X; - nr = 1; + nr_texcoords = 1; break; case TEXTURE_2D_INDEX: case TEXTURE_RECT_INDEX: emit = WRITEMASK_XY; - nr = 2; + nr_texcoords = 2; break; case TEXTURE_3D_INDEX: case TEXTURE_CUBE_INDEX: emit = WRITEMASK_XYZ; - nr = 3; + nr_texcoords = 3; break; default: /* unexpected target */ @@ -857,31 +857,28 @@ static void emit_tex( struct brw_wm_compile *c, /* For shadow comparisons, we have to supply u,v,r. */ if (inst->tex_shadow) - nr = 3; + nr_texcoords = 3; - msgLength = 1; - - for (i = 0; i < nr; i++) { + for (i = 0; i < nr_texcoords; i++) { if (emit & (1<brw) && inst->tex_shadow) { - brw_MOV(p, brw_message_reg(msgLength+1), brw_imm_f(0)); - msgLength += 2; + brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0)); + cur_mrf += 2; } /* Fill in the shadow comparison reference value. */ if (inst->tex_shadow) { - brw_MOV(p, brw_message_reg(msgLength+1), arg[2]); - msgLength += 2; + if (BRW_IS_IGDNG(p->brw)) { + /* Fill in the cube map array index value. */ + brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0)); + cur_mrf += 2; + } + brw_MOV(p, brw_message_reg(cur_mrf), arg[2]); + cur_mrf += 2; } - responseLength = 8; /* always */ + response_length = 8; /* always */ if (BRW_IS_IGDNG(p->brw)) { if (inst->tex_shadow) @@ -895,19 +892,19 @@ static void emit_tex( struct brw_wm_compile *c, msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE; } - brw_SAMPLE(p, + brw_SAMPLE(p, retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW), 1, retype(c->payload.depth[0].hw_reg, BRW_REGISTER_TYPE_UW), SURF_INDEX_TEXTURE(inst->tex_unit), inst->tex_unit, /* sampler */ inst->writemask, - msg_type, - responseLength, - msgLength, - 0, + msg_type, + response_length, + cur_mrf - 1, + 0, 1, - BRW_SAMPLER_SIMD_MODE_SIMD16); + BRW_SAMPLER_SIMD_MODE_SIMD16); } -- cgit v1.2.3 From 1be0efcbdc74f9a84136c9d1f953755c1560e52e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 19 Aug 2009 14:48:11 -0700 Subject: i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c. New comments should explain some of the confusion about how this message works. --- src/mesa/drivers/dri/i965/brw_wm.h | 8 +++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 87 ++++++++++++++++++++---------- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 95 +++------------------------------ 3 files changed, 72 insertions(+), 118 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 7db212e392..c497e8a46b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -420,6 +420,14 @@ void emit_sop(struct brw_compile *p, GLuint cond, const struct brw_reg *arg0, const struct brw_reg *arg1); +void emit_tex(struct brw_wm_compile *c, + struct brw_reg *dst, + GLuint dst_flags, + struct brw_reg *arg, + struct brw_reg depth_payload, + GLuint tex_idx, + GLuint sampler, + GLboolean shadow); void emit_wpos_xy(struct brw_wm_compile *c, const struct brw_reg *dst, GLuint mask, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index a47bf3f667..52bb73971b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -818,24 +818,41 @@ void emit_math2(struct brw_wm_compile *c, } brw_pop_insn_state(p); } - -static void emit_tex( struct brw_wm_compile *c, - const struct brw_wm_instruction *inst, - struct brw_reg *dst, - GLuint dst_flags, - struct brw_reg *arg ) +void emit_tex(struct brw_wm_compile *c, + struct brw_reg *dst, + GLuint dst_flags, + struct brw_reg *arg, + struct brw_reg depth_payload, + GLuint tex_idx, + GLuint sampler, + GLboolean shadow) { struct brw_compile *p = &c->func; + struct brw_reg dst_retyped; GLuint cur_mrf = 2, response_length; GLuint i, nr_texcoords; GLuint emit; GLuint msg_type; + GLuint mrf_per_channel; + GLuint simd_mode; + + if (c->dispatch_width == 16) { + mrf_per_channel = 2; + response_length = 8; + dst_retyped = retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW); + simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16; + } else { + mrf_per_channel = 1; + response_length = 4; + dst_retyped = retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW); + simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8; + } /* How many input regs are there? */ - switch (inst->tex_idx) { + switch (tex_idx) { case TEXTURE_1D_INDEX: emit = WRITEMASK_X; nr_texcoords = 1; @@ -855,56 +872,66 @@ static void emit_tex( struct brw_wm_compile *c, abort(); } + /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */ + if (!BRW_IS_IGDNG(p->brw) && c->dispatch_width == 8) + nr_texcoords = 3; + /* For shadow comparisons, we have to supply u,v,r. */ - if (inst->tex_shadow) + if (shadow) nr_texcoords = 3; + /* Emit the texcoords. */ for (i = 0; i < nr_texcoords; i++) { if (emit & (1<tex_shadow) { + if (shadow) { if (BRW_IS_IGDNG(p->brw)) { /* Fill in the cube map array index value. */ brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0)); - cur_mrf += 2; + cur_mrf += mrf_per_channel; + } else if (c->dispatch_width == 8) { + /* Fill in the LOD bias value. */ + brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0)); + cur_mrf += mrf_per_channel; } brw_MOV(p, brw_message_reg(cur_mrf), arg[2]); - cur_mrf += 2; + cur_mrf += mrf_per_channel; } - response_length = 8; /* always */ - if (BRW_IS_IGDNG(p->brw)) { - if (inst->tex_shadow) - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG; - else - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG; + if (shadow) + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG; + else + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG; } else { - if (inst->tex_shadow) - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; - else - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE; + /* Note that G45 and older determines shadow compare and dispatch width + * from message length for most messages. + */ + if (c->dispatch_width == 16 && shadow) + msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE; + else + msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE; } brw_SAMPLE(p, - retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW), + dst_retyped, 1, - retype(c->payload.depth[0].hw_reg, BRW_REGISTER_TYPE_UW), - SURF_INDEX_TEXTURE(inst->tex_unit), - inst->tex_unit, /* sampler */ - inst->writemask, + retype(depth_payload, BRW_REGISTER_TYPE_UW), + SURF_INDEX_TEXTURE(sampler), + sampler, + dst_flags & WRITEMASK_XYZW, msg_type, response_length, cur_mrf - 1, 0, 1, - BRW_SAMPLER_SIMD_MODE_SIMD16); + simd_mode); } @@ -1530,7 +1557,9 @@ void brw_wm_emit( struct brw_wm_compile *c ) /* Texturing operations: */ case OPCODE_TEX: - emit_tex(c, inst, dst, dst_flags, args[0]); + emit_tex(c, dst, dst_flags, args[0], c->payload.depth[0].hw_reg, + inst->tex_idx, inst->tex_unit, + inst->tex_shadow); break; case OPCODE_TXB: diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 42a13fc80f..4af01a5f2a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1871,94 +1871,6 @@ static void emit_txb(struct brw_wm_compile *c, BRW_SAMPLER_SIMD_MODE_SIMD8); } - -static void emit_tex(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - struct brw_reg dst[4], src[4], payload_reg; - /* Note: TexSrcUnit was already looked up through SamplerTextures[] */ - const GLuint unit = inst->TexSrcUnit; - GLuint msg_len; - GLuint i, nr; - GLuint emit; - GLboolean shadow = (c->key.shadowtex_mask & (1<TexSrcTarget) { - case TEXTURE_1D_INDEX: - emit = WRITEMASK_X; - nr = 1; - break; - case TEXTURE_2D_INDEX: - case TEXTURE_RECT_INDEX: - emit = WRITEMASK_XY; - nr = 2; - break; - case TEXTURE_3D_INDEX: - case TEXTURE_CUBE_INDEX: - emit = WRITEMASK_XYZ; - nr = 3; - break; - default: - /* invalid target */ - abort(); - } - msg_len = 1; - - /* move/load S, T, R coords */ - for (i = 0; i < nr; i++) { - static const GLuint swz[4] = {0,1,2,2}; - if (emit & (1<brw)) { - if (shadow) - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG; - else - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_IGDNG; - } else { - /* Does it work for shadow on SIMD8 ? */ - msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE; - } - - brw_SAMPLE(p, - retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), /* dest */ - 1, /* msg_reg_nr */ - retype(payload_reg, BRW_REGISTER_TYPE_UW), /* src0 */ - SURF_INDEX_TEXTURE(unit), - unit, /* sampler */ - inst->DstReg.WriteMask, /* writemask */ - msg_type, /* msg_type */ - 4, /* response_length */ - shadow ? 6 : 4, /* msg_length */ - 0, /* eot */ - 1, - BRW_SAMPLER_SIMD_MODE_SIMD8); - - if (shadow) - brw_MOV(p, dst[3], brw_imm_f(1.0)); -} - - /** * Resolve subroutine calls after code emit is done. */ @@ -2179,7 +2091,12 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) emit_noise4(c, inst); break; case OPCODE_TEX: - emit_tex(c, inst); + emit_tex(c, dst, dst_flags, args[0], + get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, + 0, 1, 0, 0), + inst->TexSrcTarget, + inst->TexSrcUnit, + (c->key.shadowtex_mask & (1 << inst->TexSrcUnit)) != 0); break; case OPCODE_TXB: emit_txb(c, inst); -- cgit v1.2.3 From 57f40b18377f87c434f17d5670a13838d58065c9 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 19 Aug 2009 13:44:13 -0700 Subject: i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.c This should fix TXB on G45 and older in the GLSL case. --- src/mesa/drivers/dri/i965/brw_wm.h | 7 +++ src/mesa/drivers/dri/i965/brw_wm_emit.c | 81 +++++++++++++++++++++------------ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 76 ++----------------------------- 3 files changed, 63 insertions(+), 101 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index c497e8a46b..b3c05eb0ad 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -428,6 +428,13 @@ void emit_tex(struct brw_wm_compile *c, GLuint tex_idx, GLuint sampler, GLboolean shadow); +void emit_txb(struct brw_wm_compile *c, + struct brw_reg *dst, + GLuint dst_flags, + struct brw_reg *arg, + struct brw_reg depth_payload, + GLuint tex_idx, + GLuint sampler); void emit_wpos_xy(struct brw_wm_compile *c, const struct brw_reg *dst, GLuint mask, diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 52bb73971b..5390fd2584 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -935,57 +935,77 @@ void emit_tex(struct brw_wm_compile *c, } -static void emit_txb( struct brw_wm_compile *c, - const struct brw_wm_instruction *inst, - struct brw_reg *dst, - GLuint dst_flags, - struct brw_reg *arg ) +void emit_txb(struct brw_wm_compile *c, + struct brw_reg *dst, + GLuint dst_flags, + struct brw_reg *arg, + struct brw_reg depth_payload, + GLuint tex_idx, + GLuint sampler) { struct brw_compile *p = &c->func; GLuint msgLength; GLuint msg_type; - /* Shadow ignored for txb. + GLuint mrf_per_channel; + GLuint response_length; + struct brw_reg dst_retyped; + + /* The G45 and older chipsets don't support 8-wide dispatch for LOD biased + * samples, so we'll use the 16-wide instruction, leave the second halves + * undefined, and trust the execution mask to keep the undefined pixels + * from mattering. */ - switch (inst->tex_idx) { + if (c->dispatch_width == 16 || !BRW_IS_IGDNG(p->brw)) { + if (BRW_IS_IGDNG(p->brw)) + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG; + else + msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; + mrf_per_channel = 2; + dst_retyped = retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW); + response_length = 8; + } else { + msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG; + mrf_per_channel = 1; + dst_retyped = retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW); + response_length = 4; + } + + /* Shadow ignored for txb. */ + switch (tex_idx) { case TEXTURE_1D_INDEX: - brw_MOV(p, brw_message_reg(2), arg[0]); - brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); - brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); + brw_MOV(p, brw_message_reg(2 + 0 * mrf_per_channel), arg[0]); + brw_MOV(p, brw_message_reg(2 + 1 * mrf_per_channel), brw_imm_f(0)); + brw_MOV(p, brw_message_reg(2 + 2 * mrf_per_channel), brw_imm_f(0)); break; case TEXTURE_2D_INDEX: case TEXTURE_RECT_INDEX: - brw_MOV(p, brw_message_reg(2), arg[0]); - brw_MOV(p, brw_message_reg(4), arg[1]); - brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); + brw_MOV(p, brw_message_reg(2 + 0 * mrf_per_channel), arg[0]); + brw_MOV(p, brw_message_reg(2 + 1 * mrf_per_channel), arg[1]); + brw_MOV(p, brw_message_reg(2 + 2 * mrf_per_channel), brw_imm_f(0)); break; case TEXTURE_3D_INDEX: case TEXTURE_CUBE_INDEX: - brw_MOV(p, brw_message_reg(2), arg[0]); - brw_MOV(p, brw_message_reg(4), arg[1]); - brw_MOV(p, brw_message_reg(6), arg[2]); + brw_MOV(p, brw_message_reg(2 + 0 * mrf_per_channel), arg[0]); + brw_MOV(p, brw_message_reg(2 + 1 * mrf_per_channel), arg[1]); + brw_MOV(p, brw_message_reg(2 + 2 * mrf_per_channel), arg[2]); break; default: /* unexpected target */ abort(); } - brw_MOV(p, brw_message_reg(8), arg[3]); - msgLength = 9; - - if (BRW_IS_IGDNG(p->brw)) - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG; - else - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; + brw_MOV(p, brw_message_reg(2 + 3 * mrf_per_channel), arg[3]); + msgLength = 2 + 4 * mrf_per_channel - 1; brw_SAMPLE(p, - retype(vec16(dst[0]), BRW_REGISTER_TYPE_UW), + dst_retyped, 1, - retype(c->payload.depth[0].hw_reg, BRW_REGISTER_TYPE_UW), - SURF_INDEX_TEXTURE(inst->tex_unit), - inst->tex_unit, /* sampler */ - inst->writemask, + retype(depth_payload, BRW_REGISTER_TYPE_UW), + SURF_INDEX_TEXTURE(sampler), + sampler, + dst_flags & WRITEMASK_XYZW, msg_type, - 8, /* responseLength */ + response_length, msgLength, 0, 1, @@ -1563,7 +1583,8 @@ void brw_wm_emit( struct brw_wm_compile *c ) break; case OPCODE_TXB: - emit_txb(c, inst, dst, dst_flags, args[0]); + emit_txb(c, dst, dst_flags, args[0], c->payload.depth[0].hw_reg, + inst->tex_idx, inst->tex_unit); break; case OPCODE_KIL: diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 4af01a5f2a..3ab446164c 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1801,76 +1801,6 @@ static void emit_noise4( struct brw_wm_compile *c, release_tmps( c, mark ); } - -/* TODO - BIAS on SIMD8 not working yet... - */ -static void emit_txb(struct brw_wm_compile *c, - const struct prog_instruction *inst) -{ - struct brw_compile *p = &c->func; - struct brw_reg dst[4], src[4], payload_reg; - /* Note: TexSrcUnit was already looked up through SamplerTextures[] */ - const GLuint unit = inst->TexSrcUnit; - GLuint i; - GLuint msg_type; - - assert(unit < BRW_MAX_TEX_UNIT); - - payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0); - - for (i = 0; i < 4; i++) - dst[i] = get_dst_reg(c, inst, i); - for (i = 0; i < 4; i++) - src[i] = get_src_reg(c, inst, 0, i); - - switch (inst->TexSrcTarget) { - case TEXTURE_1D_INDEX: - brw_MOV(p, brw_message_reg(2), src[0]); /* s coord */ - brw_MOV(p, brw_message_reg(3), brw_imm_f(0)); /* t coord */ - brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); /* r coord */ - break; - case TEXTURE_2D_INDEX: - case TEXTURE_RECT_INDEX: - brw_MOV(p, brw_message_reg(2), src[0]); - brw_MOV(p, brw_message_reg(3), src[1]); - brw_MOV(p, brw_message_reg(4), brw_imm_f(0)); - break; - case TEXTURE_3D_INDEX: - case TEXTURE_CUBE_INDEX: - brw_MOV(p, brw_message_reg(2), src[0]); - brw_MOV(p, brw_message_reg(3), src[1]); - brw_MOV(p, brw_message_reg(4), src[2]); - break; - default: - /* invalid target */ - abort(); - } - brw_MOV(p, brw_message_reg(5), src[3]); /* bias */ - brw_MOV(p, brw_message_reg(6), brw_imm_f(0)); /* ref (unused?) */ - - if (BRW_IS_IGDNG(p->brw)) { - msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG; - } else { - /* Does it work well on SIMD8? */ - msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; - } - - brw_SAMPLE(p, - retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW), /* dest */ - 1, /* msg_reg_nr */ - retype(payload_reg, BRW_REGISTER_TYPE_UW), /* src0 */ - SURF_INDEX_TEXTURE(unit), - unit, /* sampler */ - inst->DstReg.WriteMask, /* writemask */ - msg_type, /* msg_type */ - 4, /* response_length */ - 4, /* msg_length */ - 0, /* eot */ - 1, - BRW_SAMPLER_SIMD_MODE_SIMD8); -} - /** * Resolve subroutine calls after code emit is done. */ @@ -2099,7 +2029,11 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) (c->key.shadowtex_mask & (1 << inst->TexSrcUnit)) != 0); break; case OPCODE_TXB: - emit_txb(c, inst); + emit_txb(c, dst, dst_flags, args[0], + get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, + 0, 1, 0, 0), + inst->TexSrcTarget, + c->fp->program.Base.SamplerUnits[inst->TexSrcUnit]); break; case OPCODE_KIL_NV: emit_kil(c); -- cgit v1.2.3 From fdfbae3381553fc93202560abe3b41b4d543f0bf Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Mon, 16 Nov 2009 15:09:24 -0800 Subject: i965: Use MESA_FORMAT_AL1616 when appropriate --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +++ src/mesa/drivers/dri/intel/intel_tex_format.c | 12 +++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index e2f0a383e7..47035cc6fc 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -86,6 +86,9 @@ static GLuint translate_tex_format( gl_format mesa_format, case MESA_FORMAT_AL88: return BRW_SURFACEFORMAT_L8A8_UNORM; + case MESA_FORMAT_AL1616: + return BRW_SURFACEFORMAT_L16A16_UNORM; + case MESA_FORMAT_RGB888: assert(0); /* not supported for sampling */ return BRW_SURFACEFORMAT_R8G8B8_UNORM; diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index f37a545c7f..bfa3dba1f5 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -95,14 +95,20 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, case GL_COMPRESSED_LUMINANCE: return MESA_FORMAT_L8; + case GL_LUMINANCE12_ALPHA4: + case GL_LUMINANCE12_ALPHA12: + case GL_LUMINANCE16_ALPHA16: +#ifndef I915 + return MESA_FORMAT_AL1616; +#else + /* FALLTHROUGH */ +#endif + case 2: case GL_LUMINANCE_ALPHA: case GL_LUMINANCE4_ALPHA4: case GL_LUMINANCE6_ALPHA2: case GL_LUMINANCE8_ALPHA8: - case GL_LUMINANCE12_ALPHA4: - case GL_LUMINANCE12_ALPHA12: - case GL_LUMINANCE16_ALPHA16: case GL_COMPRESSED_LUMINANCE_ALPHA: return MESA_FORMAT_AL88; -- cgit v1.2.3 From 5606dfb572bf4b89b4882265924705bacc8c182b Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 17 Nov 2009 16:10:24 -0800 Subject: Merge branch 'outputswritten64' Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h --- src/mesa/drivers/dri/i965/brw_clip.c | 2 +- src/mesa/drivers/dri/i965/brw_clip.h | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 6 +----- src/mesa/drivers/dri/i965/brw_gs.h | 2 +- src/mesa/drivers/dri/i965/brw_sf.c | 6 +++--- src/mesa/drivers/dri/i965/brw_sf.h | 2 +- src/mesa/drivers/dri/i965/brw_sf_emit.c | 18 +++++++++--------- src/mesa/drivers/dri/i965/brw_util.c | 2 +- src/mesa/drivers/dri/i965/brw_util.h | 2 +- src/mesa/drivers/dri/i965/brw_vs.c | 2 +- src/mesa/drivers/dri/i965/brw_vs_emit.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_wm.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_fp.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_pass2.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_state.c | 2 +- src/mesa/drivers/dri/r200/r200_tcl.c | 15 ++++++++------- src/mesa/main/config.h | 2 +- src/mesa/main/context.c | 8 +++++--- src/mesa/main/ffvertex_prog.c | 2 +- src/mesa/main/mtypes.h | 27 ++++++++++++++++++++++++++- src/mesa/main/texenvprogram.c | 2 +- src/mesa/shader/prog_print.c | 6 +++--- src/mesa/shader/program_parse.tab.c | 2 +- src/mesa/shader/program_parse.y | 2 +- src/mesa/shader/programopt.c | 8 ++++---- src/mesa/shader/slang/slang_link.c | 25 +++++++++++++++---------- src/mesa/state_tracker/st_atom_shader.c | 2 +- src/mesa/state_tracker/st_program.c | 2 +- src/mesa/swrast/s_fragprog.c | 12 ++++++------ src/mesa/tnl/t_context.c | 2 +- src/mesa/tnl/t_vb_program.c | 8 ++++---- 33 files changed, 111 insertions(+), 82 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index f45dcf8282..dbd10a5297 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -78,7 +78,7 @@ static void compile_clip_prog( struct brw_context *brw, delta = REG_SIZE; for (i = 0; i < VERT_RESULT_MAX; i++) - if (c.key.attrs & (1<= VERT_RESULT_TEX0 && i <= VERT_RESULT_TEX7) { @@ -147,7 +147,7 @@ static void upload_sf_prog(struct brw_context *brw) * edgeflag testing here, it is already done in the clip * program. */ - if (key.attrs & (1<key.attrs & (1<key.attrs & BITFIELD64_BIT(attr)) ? 1 : 0; } /*********************************************************************** @@ -122,8 +122,8 @@ static void do_twoside_color( struct brw_sf_compile *c ) * Flat shading */ -#define VERT_RESULT_COLOR_BITS ((1<nr_setup_regs - 1); - GLuint persp_mask; - GLuint linear_mask; + GLbitfield64 persp_mask; + GLbitfield64 linear_mask; if (c->key.do_flat_shading || c->key.linear_color) persp_mask = c->key.attrs & ~(FRAG_BIT_WPOS | @@ -331,10 +331,10 @@ static GLboolean calculate_masks( struct brw_sf_compile *c, *pc_linear = 0; *pc = 0xf; - if (persp_mask & (1 << c->idx_to_attr[reg*2])) + if (persp_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2])) *pc_persp = 0xf; - if (linear_mask & (1 << c->idx_to_attr[reg*2])) + if (linear_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2])) *pc_linear = 0xf; /* Maybe only processs one attribute on the final round: @@ -342,10 +342,10 @@ static GLboolean calculate_masks( struct brw_sf_compile *c, if (reg*2+1 < c->nr_setup_attrs) { *pc |= 0xf0; - if (persp_mask & (1 << c->idx_to_attr[reg*2+1])) + if (persp_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2+1])) *pc_persp |= 0xf0; - if (linear_mask & (1 << c->idx_to_attr[reg*2+1])) + if (linear_mask & BITFIELD64_BIT(c->idx_to_attr[reg*2+1])) *pc_linear |= 0xf0; } diff --git a/src/mesa/drivers/dri/i965/brw_util.c b/src/mesa/drivers/dri/i965/brw_util.c index ce21aa4869..bba9249d1b 100644 --- a/src/mesa/drivers/dri/i965/brw_util.c +++ b/src/mesa/drivers/dri/i965/brw_util.c @@ -35,7 +35,7 @@ #include "brw_util.h" #include "brw_defines.h" -GLuint brw_count_bits( GLuint val ) +GLuint brw_count_bits(uint64_t val) { GLuint i; for (i = 0; val ; val >>= 1) diff --git a/src/mesa/drivers/dri/i965/brw_util.h b/src/mesa/drivers/dri/i965/brw_util.h index 33e7cd87e4..04f3175d3e 100644 --- a/src/mesa/drivers/dri/i965/brw_util.h +++ b/src/mesa/drivers/dri/i965/brw_util.h @@ -35,7 +35,7 @@ #include "main/mtypes.h" -extern GLuint brw_count_bits( GLuint val ); +extern GLuint brw_count_bits(uint64_t val); extern GLuint brw_parameter_list_state_flags(struct gl_program_parameter_list *paramList); extern GLuint brw_translate_blend_factor( GLenum factor ); extern GLuint brw_translate_blend_equation( GLenum mode ); diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index f0c79efbd9..fd055e225e 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -56,7 +56,7 @@ static void do_vs_prog( struct brw_context *brw, c.prog_data.inputs_read = vp->program.Base.InputsRead; if (c.key.copy_edgeflag) { - c.prog_data.outputs_written |= 1<prog_data.outputs_written & (1 << i)) { + if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) { c->nr_outputs++; assert(i < Elements(c->regs[PROGRAM_OUTPUT])); if (i == VERT_RESULT_HPOS) { @@ -1124,7 +1124,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) /* Update the header for point size, user clipping flags, and -ve rhw * workaround. */ - if ((c->prog_data.outputs_written & (1<prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || c->key.nr_userclip || BRW_IS_965(p->brw)) { struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); @@ -1134,7 +1134,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) brw_set_access_mode(p, BRW_ALIGN_16); - if (c->prog_data.outputs_written & (1<prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { struct brw_reg psiz = c->regs[PROGRAM_OUTPUT][VERT_RESULT_PSIZ]; brw_MUL(p, brw_writemask(header1, WRITEMASK_W), brw_swizzle1(psiz, 0), brw_imm_f(1<<11)); brw_AND(p, brw_writemask(header1, WRITEMASK_W), header1, brw_imm_ud(0x7ff<<8)); @@ -1224,7 +1224,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) */ GLuint i, mrf = 0; for (i = c->first_overflow_output; i < VERT_RESULT_MAX; i++) { - if (c->prog_data.outputs_written & (1 << i)) { + if (c->prog_data.outputs_written & BITFIELD64_BIT(i)) { /* move from GRF to MRF */ brw_MOV(p, brw_message_reg(4+mrf), c->regs[PROGRAM_OUTPUT][i]); mrf++; diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index d8971321f3..77e3b2c32a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -231,7 +231,7 @@ static void brw_wm_populate_key( struct brw_context *brw, ctx->Color.AlphaEnabled) lookup |= IZ_PS_KILL_ALPHATEST_BIT; - if (fp->program.Base.OutputsWritten & (1<program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) lookup |= IZ_PS_COMPUTES_DEPTH_BIT; /* _NEW_DEPTH */ @@ -347,7 +347,7 @@ static void brw_wm_populate_key( struct brw_context *brw, key->nr_color_regions = brw->state.nr_color_regions; /* CACHE_NEW_VS_PROG */ - key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS; + key->vp_outputs_written = brw->vs.prog_data->outputs_written; /* The unique fragment program ID */ key->program_string_id = fp->id; diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index b3c05eb0ad..9dcb6e14bb 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -79,7 +79,7 @@ struct brw_wm_prog_key { GLuint program_string_id:32; GLushort origin_x, origin_y; GLushort drawable_height; - GLuint vp_outputs_written; + GLbitfield64 vp_outputs_written; }; diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 1c4f62ba48..7d03179588 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -986,7 +986,7 @@ static void emit_render_target_writes( struct brw_wm_compile *c ) } else { /* if gl_FragData[0] is written, use it, else use gl_FragColor */ - if (c->fp->program.Base.OutputsWritten & (1 << FRAG_RESULT_DATA0)) + if (c->fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0)) outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_DATA0); else outcolor = src_reg(PROGRAM_OUTPUT, FRAG_RESULT_COLOR); diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 3ab446164c..e8c2cb66ec 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -371,7 +371,7 @@ static void prealloc_reg(struct brw_wm_compile *c) for (j = 0; j < 4; j++) set_reg(c, PROGRAM_PAYLOAD, fp_input, j, reg); } - if (c->key.vp_outputs_written & (1 << i)) { + if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) { reg_index += 2; } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c index 6faea018fb..31303febf0 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c +++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c @@ -82,8 +82,8 @@ static void init_registers( struct brw_wm_compile *c ) for (j = 0; j < c->nr_creg; j++) prealloc_reg(c, &c->creg[j], i++); - for (j = 0; j < FRAG_ATTRIB_MAX; j++) { - if (c->key.vp_outputs_written & (1<key.vp_outputs_written & BITFIELD64_BIT(j)) { int fp_index; if (j >= VERT_RESULT_VAR0) diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index 361f91292b..f89ed9bce7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -106,7 +106,7 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) /* as far as we can tell */ key->computes_depth = - (fp->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) != 0; + (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0; /* BRW_NEW_DEPTH_BUFFER * Override for NULL depthbuffer case, required by the Pixel Shader Computed * Depth field. diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c index c702910ef2..e7d48a7f29 100644 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ b/src/mesa/drivers/dri/r200/r200_tcl.c @@ -509,25 +509,26 @@ static GLboolean r200_run_tcl_render( GLcontext *ctx, prog to a not enabled output however, so just don't mess with it. We only need to change compsel. */ GLuint out_compsel = 0; - GLuint vp_out = rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten; + const GLbitfield64 vp_out = + rmesa->curr_vp_hw->mesa_program.Base.OutputsWritten; vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0]; - assert(vp_out & (1 << VERT_RESULT_HPOS)); + assert(vp_out & BITFIELD64_BIT(VERT_RESULT_HPOS)); out_compsel = R200_OUTPUT_XYZW; - if (vp_out & (1 << VERT_RESULT_COL0)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL0)) { out_compsel |= R200_OUTPUT_COLOR_0; } - if (vp_out & (1 << VERT_RESULT_COL1)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_COL1)) { out_compsel |= R200_OUTPUT_COLOR_1; } - if (vp_out & (1 << VERT_RESULT_FOGC)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_FOGC)) { out_compsel |= R200_OUTPUT_DISCRETE_FOG; } - if (vp_out & (1 << VERT_RESULT_PSIZ)) { + if (vp_out & BITFIELD64_BIT(VERT_RESULT_PSIZ)) { out_compsel |= R200_OUTPUT_PT_SIZE; } for (i = VERT_RESULT_TEX0; i < VERT_RESULT_TEX6; i++) { - if (vp_out & (1 << i)) { + if (vp_out & BITFIELD64_BIT(i)) { out_compsel |= R200_OUTPUT_TEX_0 << (i - VERT_RESULT_TEX0); } } diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h index 8a09efdb53..c5048970cc 100644 --- a/src/mesa/main/config.h +++ b/src/mesa/main/config.h @@ -205,7 +205,7 @@ #define MAX_VARYING 16 /**< number of float[4] vectors */ #define MAX_SAMPLERS MAX_TEXTURE_IMAGE_UNITS #define MAX_PROGRAM_INPUTS 32 -#define MAX_PROGRAM_OUTPUTS 32 +#define MAX_PROGRAM_OUTPUTS 64 /*@}*/ /** For GL_ARB_vertex_program */ diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index 101d3c6b67..b5bf46718f 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -601,9 +601,11 @@ _mesa_init_constants(GLcontext *ctx) ASSERT(MAX_NV_VERTEX_PROGRAM_INPUTS <= VERT_ATTRIB_MAX); ASSERT(MAX_NV_VERTEX_PROGRAM_OUTPUTS <= VERT_RESULT_MAX); - /* check that we don't exceed various 32-bit bitfields */ - ASSERT(VERT_RESULT_MAX <= 32); - ASSERT(FRAG_ATTRIB_MAX <= 32); + /* check that we don't exceed the size of various bitfields */ + ASSERT(VERT_RESULT_MAX <= + (8 * sizeof(ctx->VertexProgram._Current->Base.OutputsWritten))); + ASSERT(FRAG_ATTRIB_MAX <= + (8 * sizeof(ctx->FragmentProgram._Current->Base.InputsRead))); } diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c index 356476e35a..fe2416d894 100644 --- a/src/mesa/main/ffvertex_prog.c +++ b/src/mesa/main/ffvertex_prog.c @@ -438,7 +438,7 @@ static struct ureg register_input( struct tnl_program *p, GLuint input ) */ static struct ureg register_output( struct tnl_program *p, GLuint output ) { - p->program->Base.OutputsWritten |= (1<program->Base.OutputsWritten |= BITFIELD64_BIT(output); return make_ureg(PROGRAM_OUTPUT, output); } diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 34c51b5442..881d233ca3 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -78,6 +78,31 @@ #endif +/** + * \name 64-bit extension of GLbitfield. + */ +/*@{*/ +typedef GLuint64 GLbitfield64; + +#define BITFIELD64_ONE 1ULL +#define BITFIELD64_ALLONES ~0ULL + +/** Set a single bit */ +#define BITFIELD64_BIT(b) (BITFIELD64_ONE << (b)) + +/** Set a mask of the least significant \c b bits */ +#define BITFIELD64_MASK(b) (((b) >= 64) ? BITFIELD64_ALLONES : \ + (BITFIELD64_BIT(b) - 1)) + +/** + * Set all bits from l (low bit) to h (high bit), inclusive. + * + * \note \C BITFIELD_64_RANGE(0, 63) return 64 set bits. + */ +#define BITFIELD64_RANGE(l, h) (BITFIELD64_MASK((h) + 1) & ~BITFIELD64_MASK(l)) +/*@}*/ + + /** * \name Some forward type declarations */ @@ -1670,7 +1695,7 @@ struct gl_program struct prog_instruction *Instructions; GLbitfield InputsRead; /**< Bitmask of which input regs are read */ - GLbitfield OutputsWritten; /**< Bitmask of which output regs are written to */ + GLbitfield64 OutputsWritten; /**< Bitmask of which output regs are written */ GLbitfield InputFlags[MAX_PROGRAM_INPUTS]; /**< PROG_PARAM_BIT_x flags */ GLbitfield OutputFlags[MAX_PROGRAM_OUTPUTS]; /**< PROG_PARAM_BIT_x flags */ GLbitfield TexturesUsed[MAX_TEXTURE_UNITS]; /**< TEXTURE_x_BIT bitmask */ diff --git a/src/mesa/main/texenvprogram.c b/src/mesa/main/texenvprogram.c index d7e77e759e..f439d4addb 100644 --- a/src/mesa/main/texenvprogram.c +++ b/src/mesa/main/texenvprogram.c @@ -367,7 +367,7 @@ static GLbitfield get_fp_input_mask( GLcontext *ctx ) else { /* calculate from vp->outputs */ struct gl_vertex_program *vprog; - GLbitfield vp_outputs; + GLbitfield64 vp_outputs; /* Choose GLSL vertex shader over ARB vertex program. Need this * since vertex shader state validation comes after fragment state diff --git a/src/mesa/shader/prog_print.c b/src/mesa/shader/prog_print.c index ba4d39452f..52c102cbaa 100644 --- a/src/mesa/shader/prog_print.c +++ b/src/mesa/shader/prog_print.c @@ -826,11 +826,11 @@ _mesa_print_program(const struct gl_program *prog) * XXX move to imports.[ch] if useful elsewhere. */ static const char * -binary(GLbitfield val) +binary(GLbitfield64 val) { - static char buf[50]; + static char buf[80]; GLint i, len = 0; - for (i = 31; i >= 0; --i) { + for (i = 63; i >= 0; --i) { if (val & (1 << i)) buf[len++] = '1'; else if (len > 0 || i == 0) diff --git a/src/mesa/shader/program_parse.tab.c b/src/mesa/shader/program_parse.tab.c index b9ef88b64b..d4f8429488 100644 --- a/src/mesa/shader/program_parse.tab.c +++ b/src/mesa/shader/program_parse.tab.c @@ -2622,7 +2622,7 @@ yyreduce: YYERROR; } - state->prog->OutputsWritten |= (1U << (yyval.dst_reg).Index); + state->prog->OutputsWritten |= BITFIELD64_BIT((yyval.dst_reg).Index); } ;} break; diff --git a/src/mesa/shader/program_parse.y b/src/mesa/shader/program_parse.y index d07bf85b36..8ca6f9805b 100644 --- a/src/mesa/shader/program_parse.y +++ b/src/mesa/shader/program_parse.y @@ -643,7 +643,7 @@ maskedDstReg: dstReg optionalMask optionalCcMask YYERROR; } - state->prog->OutputsWritten |= (1U << $$.Index); + state->prog->OutputsWritten |= BITFIELD64_BIT($$.Index); } } ; diff --git a/src/mesa/shader/programopt.c b/src/mesa/shader/programopt.c index 3b8529592d..a0daac1b80 100644 --- a/src/mesa/shader/programopt.c +++ b/src/mesa/shader/programopt.c @@ -109,7 +109,7 @@ _mesa_insert_mvp_dp4_code(GLcontext *ctx, struct gl_vertex_program *vprog) vprog->Base.Instructions = newInst; vprog->Base.NumInstructions = newLen; vprog->Base.InputsRead |= VERT_BIT_POS; - vprog->Base.OutputsWritten |= (1 << VERT_RESULT_HPOS); + vprog->Base.OutputsWritten |= BITFIELD64_BIT(VERT_RESULT_HPOS); } @@ -211,7 +211,7 @@ _mesa_insert_mvp_mad_code(GLcontext *ctx, struct gl_vertex_program *vprog) vprog->Base.Instructions = newInst; vprog->Base.NumInstructions = newLen; vprog->Base.InputsRead |= VERT_BIT_POS; - vprog->Base.OutputsWritten |= (1 << VERT_RESULT_HPOS); + vprog->Base.OutputsWritten |= BITFIELD64_BIT(VERT_RESULT_HPOS); } @@ -613,7 +613,7 @@ _mesa_nop_fragment_program(GLcontext *ctx, struct gl_fragment_program *prog) prog->Base.Instructions = inst; prog->Base.NumInstructions = 2; prog->Base.InputsRead = 1 << inputAttr; - prog->Base.OutputsWritten = 1 << FRAG_RESULT_COLOR; + prog->Base.OutputsWritten = BITFIELD64_BIT(FRAG_RESULT_COLOR); } @@ -657,7 +657,7 @@ _mesa_nop_vertex_program(GLcontext *ctx, struct gl_vertex_program *prog) prog->Base.Instructions = inst; prog->Base.NumInstructions = 2; prog->Base.InputsRead = 1 << inputAttr; - prog->Base.OutputsWritten = 1 << VERT_RESULT_COL0; + prog->Base.OutputsWritten = BITFIELD64_BIT(VERT_RESULT_COL0); /* * Now insert code to do standard modelview/projection transformation. diff --git a/src/mesa/shader/slang/slang_link.c b/src/mesa/shader/slang/slang_link.c index 144c126525..0a2bc49780 100644 --- a/src/mesa/shader/slang/slang_link.c +++ b/src/mesa/shader/slang/slang_link.c @@ -515,7 +515,7 @@ _slang_update_inputs_outputs(struct gl_program *prog) } if (inst->DstReg.File == PROGRAM_OUTPUT) { - prog->OutputsWritten |= 1 << inst->DstReg.Index; + prog->OutputsWritten |= BITFIELD64_BIT(inst->DstReg.Index); if (inst->DstReg.RelAddr) { /* If the output attribute is indexed with relative addressing * we know that it must be a varying or texcoord such as @@ -528,14 +528,17 @@ _slang_update_inputs_outputs(struct gl_program *prog) if (prog->Target == GL_VERTEX_PROGRAM_ARB) { if (inst->DstReg.Index == VERT_RESULT_TEX0) { /* mark all texcoord outputs as written */ - const GLbitfield mask = - ((1 << MAX_TEXTURE_COORD_UNITS) - 1) << VERT_RESULT_TEX0; + const GLbitfield64 mask = + BITFIELD64_RANGE(VERT_RESULT_TEX0, + (VERT_RESULT_TEX0 + + MAX_TEXTURE_COORD_UNITS - 1)); prog->OutputsWritten |= mask; } else if (inst->DstReg.Index == VERT_RESULT_VAR0) { /* mark all generic varying outputs as written */ - const GLbitfield mask = - ((1 << MAX_VARYING) - 1) << VERT_RESULT_VAR0; + const GLbitfield64 mask = + BITFIELD64_RANGE(VERT_RESULT_VAR0, + (VERT_RESULT_VAR0 + MAX_VARYING - 1)); prog->OutputsWritten |= mask; } } @@ -807,7 +810,8 @@ _slang_link(GLcontext *ctx, if (shProg->VertexProgram) { _slang_update_inputs_outputs(&shProg->VertexProgram->Base); _slang_count_temporaries(&shProg->VertexProgram->Base); - if (!(shProg->VertexProgram->Base.OutputsWritten & (1 << VERT_RESULT_HPOS))) { + if (!(shProg->VertexProgram->Base.OutputsWritten + & BITFIELD64_BIT(VERT_RESULT_HPOS))) { /* the vertex program did not compute a vertex position */ link_error(shProg, "gl_Position was not written by vertex shader\n"); @@ -825,7 +829,7 @@ _slang_link(GLcontext *ctx, if (shProg->FragmentProgram) { const GLbitfield varyingRead = shProg->FragmentProgram->Base.InputsRead >> FRAG_ATTRIB_VAR0; - const GLbitfield varyingWritten = shProg->VertexProgram ? + const GLbitfield64 varyingWritten = shProg->VertexProgram ? shProg->VertexProgram->Base.OutputsWritten >> VERT_RESULT_VAR0 : 0x0; if ((varyingRead & varyingWritten) != varyingRead) { link_error(shProg, @@ -836,9 +840,10 @@ _slang_link(GLcontext *ctx, /* check that gl_FragColor and gl_FragData are not both written to */ if (shProg->FragmentProgram) { - GLbitfield outputsWritten = shProg->FragmentProgram->Base.OutputsWritten; - if ((outputsWritten & ((1 << FRAG_RESULT_COLOR))) && - (outputsWritten >= (1 << FRAG_RESULT_DATA0))) { + const GLbitfield64 outputsWritten = + shProg->FragmentProgram->Base.OutputsWritten; + if ((outputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR)) && + (outputsWritten >= BITFIELD64_BIT(FRAG_RESULT_DATA0))) { link_error(shProg, "Fragment program cannot write both gl_FragColor" " and gl_FragData[].\n"); return; diff --git a/src/mesa/state_tracker/st_atom_shader.c b/src/mesa/state_tracker/st_atom_shader.c index ee649be885..6e311e537e 100644 --- a/src/mesa/state_tracker/st_atom_shader.c +++ b/src/mesa/state_tracker/st_atom_shader.c @@ -176,7 +176,7 @@ find_translated_vp(struct st_context *st, /* See if we need to translate vertex program to TGSI form */ if (xvp->serialNo != stvp->serialNo) { GLuint outAttr; - const GLbitfield outputsWritten = stvp->Base.Base.OutputsWritten; + const GLbitfield64 outputsWritten = stvp->Base.Base.OutputsWritten; GLuint numVpOuts = 0; GLboolean emitPntSize = GL_FALSE, emitBFC0 = GL_FALSE, emitBFC1 = GL_FALSE; GLbitfield usedGenerics = 0x0; diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c index 6d02722c13..190b6a5526 100644 --- a/src/mesa/state_tracker/st_program.c +++ b/src/mesa/state_tracker/st_program.c @@ -469,7 +469,7 @@ st_translate_fragment_program(struct st_context *st, */ { uint numColors = 0; - GLbitfield outputsWritten = stfp->Base.Base.OutputsWritten; + GLbitfield64 outputsWritten = stfp->Base.Base.OutputsWritten; /* if z is written, emit that first */ if (outputsWritten & (1 << FRAG_RESULT_DEPTH)) { diff --git a/src/mesa/swrast/s_fragprog.c b/src/mesa/swrast/s_fragprog.c index 77a77f0bcb..a22d34415d 100644 --- a/src/mesa/swrast/s_fragprog.c +++ b/src/mesa/swrast/s_fragprog.c @@ -190,7 +190,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) { SWcontext *swrast = SWRAST_CONTEXT(ctx); const struct gl_fragment_program *program = ctx->FragmentProgram._Current; - const GLbitfield outputsWritten = program->Base.OutputsWritten; + const GLbitfield64 outputsWritten = program->Base.OutputsWritten; struct gl_program_machine *machine = &swrast->FragProgMachine; GLuint i; @@ -201,7 +201,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) if (_mesa_execute_program(ctx, &program->Base, machine)) { /* Store result color */ - if (outputsWritten & (1 << FRAG_RESULT_COLOR)) { + if (outputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR)) { COPY_4V(span->array->attribs[FRAG_ATTRIB_COL0][i], machine->Outputs[FRAG_RESULT_COLOR]); } @@ -212,7 +212,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) */ GLuint buf; for (buf = 0; buf < ctx->DrawBuffer->_NumColorDrawBuffers; buf++) { - if (outputsWritten & (1 << (FRAG_RESULT_DATA0 + buf))) { + if (outputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + buf)) { COPY_4V(span->array->attribs[FRAG_ATTRIB_COL0 + buf][i], machine->Outputs[FRAG_RESULT_DATA0 + buf]); } @@ -220,7 +220,7 @@ run_program(GLcontext *ctx, SWspan *span, GLuint start, GLuint end) } /* Store result depth/z */ - if (outputsWritten & (1 << FRAG_RESULT_DEPTH)) { + if (outputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { const GLfloat depth = machine->Outputs[FRAG_RESULT_DEPTH][2]; if (depth <= 0.0) span->array->z[i] = 0; @@ -256,12 +256,12 @@ _swrast_exec_fragment_program( GLcontext *ctx, SWspan *span ) run_program(ctx, span, 0, span->end); - if (program->Base.OutputsWritten & (1 << FRAG_RESULT_COLOR)) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR)) { span->interpMask &= ~SPAN_RGBA; span->arrayMask |= SPAN_RGBA; } - if (program->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) { span->interpMask &= ~SPAN_Z; span->arrayMask |= SPAN_Z; } diff --git a/src/mesa/tnl/t_context.c b/src/mesa/tnl/t_context.c index f2771cde09..db21b4589d 100644 --- a/src/mesa/tnl/t_context.c +++ b/src/mesa/tnl/t_context.c @@ -171,7 +171,7 @@ _tnl_InvalidateState( GLcontext *ctx, GLuint new_state ) if (vp) { GLuint i; for (i = 0; i < MAX_VARYING; i++) { - if (vp->Base.OutputsWritten & (1 << (VERT_RESULT_VAR0 + i))) { + if (vp->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_VAR0 + i)) { RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_GENERIC(i)); } diff --git a/src/mesa/tnl/t_vb_program.c b/src/mesa/tnl/t_vb_program.c index c10a27614f..e69f7d5766 100644 --- a/src/mesa/tnl/t_vb_program.c +++ b/src/mesa/tnl/t_vb_program.c @@ -329,7 +329,7 @@ run_vp( GLcontext *ctx, struct tnl_pipeline_stage *stage ) /* make list of outputs to save some time below */ numOutputs = 0; for (i = 0; i < VERT_RESULT_MAX; i++) { - if (program->Base.OutputsWritten & (1 << i)) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(i)) { outputs[numOutputs++] = i; } } @@ -407,14 +407,14 @@ run_vp( GLcontext *ctx, struct tnl_pipeline_stage *stage ) /* Fixup fog and point size results if needed */ if (program->IsNVProgram) { if (ctx->Fog.Enabled && - (program->Base.OutputsWritten & (1 << VERT_RESULT_FOGC)) == 0) { + (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_FOGC)) == 0) { for (i = 0; i < VB->Count; i++) { store->results[VERT_RESULT_FOGC].data[i][0] = 1.0; } } if (ctx->VertexProgram.PointSizeEnabled && - (program->Base.OutputsWritten & (1 << VERT_RESULT_PSIZ)) == 0) { + (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_PSIZ)) == 0) { for (i = 0; i < VB->Count; i++) { store->results[VERT_RESULT_PSIZ].data[i][0] = ctx->Point.Size; } @@ -472,7 +472,7 @@ run_vp( GLcontext *ctx, struct tnl_pipeline_stage *stage ) } for (i = 0; i < ctx->Const.MaxVarying; i++) { - if (program->Base.OutputsWritten & (1 << (VERT_RESULT_VAR0 + i))) { + if (program->Base.OutputsWritten & BITFIELD64_BIT(VERT_RESULT_VAR0 + i)) { /* Note: varying results get put into the generic attributes */ VB->AttribPtr[VERT_ATTRIB_GENERIC0+i] = &store->results[VERT_RESULT_VAR0 + i]; -- cgit v1.2.3 From 92d35b91f132deda1fb27d2071a50e8187301fe5 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 03:01:42 -0800 Subject: i965: Pack the brw_wm_prog_key better. --- src/mesa/drivers/dri/i965/brw_wm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 9dcb6e14bb..b9b987ea70 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -76,10 +76,10 @@ struct brw_wm_prog_key { GLushort tex_swizzles[BRW_MAX_TEX_UNIT]; - GLuint program_string_id:32; GLushort origin_x, origin_y; GLushort drawable_height; GLbitfield64 vp_outputs_written; + GLuint program_string_id:32; }; -- cgit v1.2.3 From 15fa484f514726a29bbf24df33c0551844f878d0 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 03:05:14 -0800 Subject: mesa: Remove gratuitous padding in prog_dst_register. The padding was there to indicate the amount of space left from the number of expected bytes in the struct minus allocated bits. But uint bitfields get packed so that they don't cross uint boundaries, and we ended up allocating an extra dword to hold the pad field! --- src/mesa/drivers/dri/i965/brw_wm_fp.c | 1 - src/mesa/main/ffvertex_prog.c | 1 - src/mesa/shader/prog_instruction.h | 1 - 3 files changed, 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index 7d03179588..3737faf26f 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -138,7 +138,6 @@ static struct prog_dst_register dst_reg(GLuint file, GLuint idx) reg.CondMask = COND_TR; reg.CondSwizzle = 0; reg.CondSrc = 0; - reg.pad = 0; return reg; } diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c index fe2416d894..5cfa898031 100644 --- a/src/mesa/main/ffvertex_prog.c +++ b/src/mesa/main/ffvertex_prog.c @@ -523,7 +523,6 @@ static void emit_dst( struct prog_dst_register *dst, dst->CondMask = COND_TR; /* always pass cond test */ dst->CondSwizzle = SWIZZLE_NOOP; dst->CondSrc = 0; - dst->pad = 0; /* Check that bitfield sizes aren't exceeded */ ASSERT(dst->Index == reg.idx); } diff --git a/src/mesa/shader/prog_instruction.h b/src/mesa/shader/prog_instruction.h index 1c687bc16c..224350caac 100644 --- a/src/mesa/shader/prog_instruction.h +++ b/src/mesa/shader/prog_instruction.h @@ -312,7 +312,6 @@ struct prog_dst_register */ GLuint CondSrc:1; /*@}*/ - GLuint pad:28; }; -- cgit v1.2.3 From edd449fb9714ec1aa2d6c0cf95623f460594e685 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 03:13:14 -0800 Subject: i965: Pack brw_wm_fragment_program better. --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index fded47aa2f..6d2ce15682 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -172,8 +172,8 @@ struct brw_fragment_program { GLuint id; /**< serial no. to identify frag progs, never re-used */ GLboolean isGLSL; /**< really, any IF/LOOP/CONT/BREAK instructions */ - dri_bo *const_buffer; /** Program constant buffer/surface */ GLboolean use_const_buffer; + dri_bo *const_buffer; /** Program constant buffer/surface */ /** for debugging, which texture units are referenced */ GLbitfield tex_units_used; -- cgit v1.2.3 From a376e5c48237be0300bce6702ed947086d3ee23f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 03:21:17 -0800 Subject: intel: Consistently use no_batch_wrap in intel_context struct. --- src/mesa/drivers/dri/i915/i830_vtbl.c | 3 --- src/mesa/drivers/dri/i915/i915_vtbl.c | 3 --- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_draw.c | 4 ++-- src/mesa/drivers/dri/i965/brw_vtbl.c | 3 --- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 3 +++ 6 files changed, 5 insertions(+), 12 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 7d76b39caa..c05c7759ac 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -714,9 +714,6 @@ i830_new_batch(struct intel_context *intel) { struct i830_context *i830 = i830_context(&intel->ctx); i830->state.emitted = 0; - - /* Check that we didn't just wrap our batchbuffer at a bad time. */ - assert(!intel->no_batch_wrap); } static void diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 77ba8d5581..3e7b5101cc 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -667,9 +667,6 @@ i915_new_batch(struct intel_context *intel) * difficulties associated with them (physical address requirements). */ i915->state.emitted = 0; - - /* Check that we didn't just wrap our batchbuffer at a bad time. */ - assert(!intel->no_batch_wrap); } static void diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 6d2ce15682..e73e21433c 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -438,7 +438,6 @@ struct brw_context GLuint primitive; GLboolean emit_state_always; - GLboolean no_batch_wrap; struct { struct brw_state_flags dirty; diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 8bcb6083f7..7ad860898f 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -145,7 +145,7 @@ static void brw_emit_prim(struct brw_context *brw, prim_packet.base_vert_location = prim->basevertex; /* Can't wrap here, since we rely on the validated state. */ - brw->no_batch_wrap = GL_TRUE; + intel->no_batch_wrap = GL_TRUE; /* If we're set to always flush, do it before and after the primitive emit. * We want to catch both missed flushes that hurt instruction/state cache @@ -163,7 +163,7 @@ static void brw_emit_prim(struct brw_context *brw, intel_batchbuffer_emit_mi_flush(intel->batch); } - brw->no_batch_wrap = GL_FALSE; + intel->no_batch_wrap = GL_FALSE; } static void brw_merge_inputs( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 114e6bd018..dc47f08dd4 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -144,9 +144,6 @@ static void brw_new_batch( struct intel_context *intel ) { struct brw_context *brw = brw_context(&intel->ctx); - /* Check that we didn't just wrap our batchbuffer at a bad time. */ - assert(!brw->no_batch_wrap); - brw->curbe.need_new_bo = GL_TRUE; /* Mark all context state as needing to be re-emitted. diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index ca6e2fa5b1..12c5a30d6b 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -244,6 +244,9 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, if (intel->vtbl.finish_batch) intel->vtbl.finish_batch(intel); + /* Check that we didn't just wrap our batchbuffer at a bad time. */ + assert(!intel->no_batch_wrap); + batch->reserved_space = BATCH_RESERVED; /* TODO: Just pass the relocation list and dma buffer up to the -- cgit v1.2.3 From 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 18 Nov 2009 18:15:25 +0100 Subject: intel: Remove non-GEM support. This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked. --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ---- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 4 +- src/mesa/drivers/dri/intel/intel_context.c | 38 ++++------------- src/mesa/drivers/dri/intel/intel_context.h | 6 --- src/mesa/drivers/dri/intel/intel_extensions.c | 14 ++----- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 16 +++----- src/mesa/drivers/dri/intel/intel_regions.c | 57 +++++--------------------- src/mesa/drivers/dri/intel/intel_screen.c | 38 ++++------------- src/mesa/drivers/dri/intel/intel_screen.h | 1 - src/mesa/drivers/dri/intel/intel_span.c | 13 ++---- 10 files changed, 43 insertions(+), 152 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 271a88dae0..7c796dae93 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -243,14 +243,6 @@ static void wrap_buffers( struct brw_context *brw, dri_bo_unreference(brw->vb.upload.bo); brw->vb.upload.bo = dri_bo_alloc(brw->intel.bufmgr, "temporary VBO", size, 1); - - /* Set the internal VBO\ to no-backing-store. We only use them as a - * temporary within a brw_try_draw_prims while the lock is held. - */ - /* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH - FAKE TO PUSH THIS STUFF */ -// if (!brw->intel.ttm) -// dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL); } static void get_space( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 12c5a30d6b..2eae9b66d8 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -80,7 +80,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch) batch->buf = NULL; } - if (!batch->buffer && intel->ttm == GL_TRUE) + if (!batch->buffer) batch->buffer = malloc (intel->maxBatchSize); batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer", @@ -212,7 +212,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, batch->reserved_space = 0; /* Emit a flush if the bufmgr doesn't do it for us. */ - if (intel->always_flush_cache || !intel->ttm) { + if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(batch); used = batch->ptr - batch->map; } diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 7b7c0a0b5a..1434ae530b 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -176,9 +176,7 @@ intelGetString(GLcontext * ctx, GLenum name) break; } - (void) driGetRendererString(buffer, chipset, - (intel->ttm) ? DRIVER_DATE_GEM : DRIVER_DATE, - 0); + (void) driGetRendererString(buffer, chipset, DRIVER_DATE_GEM, 0); return (GLubyte *) buffer; default: @@ -601,6 +599,7 @@ intelInitContext(struct intel_context *intel, __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; int fthrottle_mode; + int bo_reuse_mode; if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx, functions, (void *) intel)) { @@ -635,18 +634,14 @@ intelInitContext(struct intel_context *intel, intel->maxBatchSize = BATCH_SZ; intel->bufmgr = intelScreen->bufmgr; - intel->ttm = intelScreen->ttm; - if (intel->ttm) { - int bo_reuse_mode; - bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); - switch (bo_reuse_mode) { - case DRI_CONF_BO_REUSE_DISABLED: - break; - case DRI_CONF_BO_REUSE_ALL: - intel_bufmgr_gem_enable_reuse(intel->bufmgr); - break; - } + bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); + switch (bo_reuse_mode) { + case DRI_CONF_BO_REUSE_DISABLED: + break; + case DRI_CONF_BO_REUSE_ALL: + intel_bufmgr_gem_enable_reuse(intel->bufmgr); + break; } /* This doesn't yet catch all non-conformant rendering, but it's a @@ -1052,21 +1047,6 @@ intelContendedLock(struct intel_context *intel, GLuint flags) sarea->ctxOwner = me; } - /* If the last consumer of the texture memory wasn't us, notify the fake - * bufmgr and record the new owner. We should have the memory shared - * between contexts of a single fake bufmgr, but this will at least make - * things correct for now. - */ - if (!intel->ttm && sarea->texAge != intel->hHWContext) { - sarea->texAge = intel->hHWContext; - intel_bufmgr_fake_contended_lock_take(intel->bufmgr); - if (INTEL_DEBUG & DEBUG_BATCH) - intel_decode_context_reset(); - if (INTEL_DEBUG & DEBUG_BUFMGR) - fprintf(stderr, "Lost Textures: sarea->texAge %x hw context %x\n", - sarea->ctxOwner, intel->hHWContext); - } - /* Drawable changed? */ if (dPriv && intel->lastStamp != dPriv->lastStamp) { diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index f16f502c1d..481202c971 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -181,12 +181,6 @@ struct intel_context struct intel_region *back_region; struct intel_region *depth_region; - /** - * This value indicates that the kernel memory manager is being used - * instead of the fake client-side memory manager. - */ - GLboolean ttm; - struct intel_batchbuffer *batch; drm_intel_bo *first_post_swapbuffers_batch; GLboolean no_batch_wrap; diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 1682e115cc..f5fe543b5d 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -79,6 +79,7 @@ static const struct dri_extension card_extensions[] = { { "GL_ARB_half_float_pixel", NULL }, { "GL_ARB_map_buffer_range", GL_ARB_map_buffer_range_functions }, { "GL_ARB_multitexture", NULL }, + { "GL_ARB_pixel_buffer_object", NULL }, { "GL_ARB_point_parameters", GL_ARB_point_parameters_functions }, { "GL_ARB_point_sprite", NULL }, { "GL_ARB_shader_objects", GL_ARB_shader_objects_functions }, @@ -104,6 +105,8 @@ static const struct dri_extension card_extensions[] = { { "GL_EXT_blend_logic_op", NULL }, { "GL_EXT_blend_subtract", NULL }, { "GL_EXT_cull_vertex", GL_EXT_cull_vertex_functions }, + { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, + { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, { "GL_EXT_fog_coord", GL_EXT_fog_coord_functions }, { "GL_EXT_gpu_program_parameters", GL_EXT_gpu_program_parameters_functions }, { "GL_EXT_packed_depth_stencil", NULL }, @@ -176,14 +179,6 @@ static const struct dri_extension arb_oq_extensions[] = { { NULL, NULL } }; - -static const struct dri_extension ttm_extensions[] = { - { "GL_ARB_pixel_buffer_object", NULL }, - { "GL_EXT_framebuffer_blit", GL_EXT_framebuffer_blit_functions }, - { "GL_EXT_framebuffer_object", GL_EXT_framebuffer_object_functions }, - { NULL, NULL } -}; - static const struct dri_extension fragment_shader_extensions[] = { { "GL_ARB_fragment_shader", NULL }, { NULL, NULL } @@ -202,9 +197,6 @@ intelInitExtensions(GLcontext *ctx) */ driInitExtensions(ctx, card_extensions, GL_FALSE); - if (intel->ttm) - driInitExtensions(ctx, ttm_extensions, GL_FALSE); - if (IS_965(intel->intelScreen->deviceID)) driInitExtensions(ctx, brw_extensions, GL_FALSE); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index abb3024bfb..6a565f80cf 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -224,16 +224,12 @@ int intel_miptree_pitch_align (struct intel_context *intel, if (!mt->compressed) { int pitch_align; - if (intel->ttm) { - /* XXX: Align pitch to multiple of 64 bytes for now to allow - * render-to-texture to work in all cases. This should probably be - * replaced at some point by some scheme to only do this when really - * necessary. - */ - pitch_align = 64; - } else { - pitch_align = 4; - } + /* XXX: Align pitch to multiple of 64 bytes for now to allow + * render-to-texture to work in all cases. This should probably be + * replaced at some point by some scheme to only do this when really + * necessary. + */ + pitch_align = 64; if (tiling == I915_TILING_X) pitch_align = 512; diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 80975163d4..d6b9dc4446 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -542,55 +542,18 @@ intel_recreate_static(struct intel_context *intel, region->buffer = NULL; } - if (intel->ttm) { - assert(region_desc->bo_handle != -1); - region->buffer = intel_bo_gem_create_from_name(intel->bufmgr, - name, - region_desc->bo_handle); - - ret = dri_bo_get_tiling(region->buffer, ®ion->tiling, - ®ion->bit_6_swizzle); - if (ret != 0) { - fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", - region_desc->bo_handle, name, strerror(-ret)); - intel_region_release(®ion); - return NULL; - } - } else { - if (region->classic_map != NULL) { - drmUnmap(region->classic_map, - region->pitch * region->cpp * region->height); - region->classic_map = NULL; - } - ret = drmMap(intel->driFd, region_desc->handle, - region->pitch * region->cpp * region->height, - ®ion->classic_map); - if (ret != 0) { - fprintf(stderr, "Failed to drmMap %s buffer\n", name); - free(region); - return NULL; - } - - region->buffer = intel_bo_fake_alloc_static(intel->bufmgr, + assert(region_desc->bo_handle != -1); + region->buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, - region_desc->offset, - region->pitch * region->cpp * - region->height, - region->classic_map); - - /* The sarea just gives us a boolean for whether it's tiled or not, - * instead of which tiling mode it is. Guess. - */ - if (region_desc->tiled) { - if (intel->gen >= 4 && region_desc == &intelScreen->depth) - region->tiling = I915_TILING_Y; - else - region->tiling = I915_TILING_X; - } else { - region->tiling = I915_TILING_NONE; - } + region_desc->bo_handle); - region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE; + ret = dri_bo_get_tiling(region->buffer, ®ion->tiling, + ®ion->bit_6_swizzle); + if (ret != 0) { + fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n", + region_desc->bo_handle, name, strerror(-ret)); + intel_region_release(®ion); + return NULL; } assert(region->buffer != NULL); diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 789135b49f..2c5a884a9b 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -605,7 +605,6 @@ intelFillInModes(__DRIscreenPrivate *psp, static GLboolean intel_init_bufmgr(intelScreenPrivate *intelScreen) { - GLboolean gem_disable = getenv("INTEL_NO_GEM") != NULL; int gem_kernel = 0; GLboolean gem_supported; struct drm_i915_getparam gp; @@ -622,43 +621,24 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) /* If we've got a new enough DDX that's initializing GEM and giving us * object handles for the shared buffers, use that. */ - intelScreen->ttm = GL_FALSE; if (intelScreen->driScrnPriv->dri2.enabled) gem_supported = GL_TRUE; else if (intelScreen->driScrnPriv->ddx_version.minor >= 9 && gem_kernel && intelScreen->front.bo_handle != -1) gem_supported = GL_TRUE; - else - gem_supported = GL_FALSE; - - if (!gem_disable && gem_supported) { - intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ); - if (intelScreen->bufmgr != NULL) - intelScreen->ttm = GL_TRUE; + else { + fprintf(stderr, "[%s:%u] Error initializing GEM.\n", + __func__, __LINE__); + return GL_FALSE; } + + intelScreen->bufmgr = intel_bufmgr_gem_init(spriv->fd, BATCH_SZ); /* Otherwise, use the classic buffer manager. */ if (intelScreen->bufmgr == NULL) { - if (gem_disable) { - _mesa_warning(NULL, "GEM disabled. Using classic."); - } else { - _mesa_warning(NULL, - "Failed to initialize GEM. Falling back to classic."); - } - - if (intelScreen->tex.size == 0) { - fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", - __func__, __LINE__); - return GL_FALSE; - } - - intelScreen->bufmgr = - intel_bufmgr_fake_init(spriv->fd, - intelScreen->tex.offset, - intelScreen->tex.map, - intelScreen->tex.size, - (unsigned int * volatile) - &intelScreen->sarea->last_dispatch); + fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n", + __func__, __LINE__); + return GL_FALSE; } if (intel_get_param(spriv, I915_PARAM_NUM_FENCES_AVAIL, &num_fences)) diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index a9b9e109a6..14ca0903b6 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -77,7 +77,6 @@ typedef struct GLboolean no_hw; GLboolean no_vbo; - int ttm; dri_bufmgr *bufmgr; GLboolean kernel_exec_fencing; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 3607c7dded..2c89a66a95 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -613,15 +613,7 @@ intel_set_span_functions(struct intel_context *intel, struct gl_renderbuffer *rb) { struct intel_renderbuffer *irb = (struct intel_renderbuffer *) rb; - uint32_t tiling; - - /* If in GEM mode, we need to do the tile address swizzling ourselves, - * instead of the fence registers handling it. - */ - if (intel->ttm) - tiling = irb->region->tiling; - else - tiling = I915_TILING_NONE; + uint32_t tiling = irb->region->tiling; if (intel->intelScreen->kernel_exec_fencing) { switch (irb->texformat) { @@ -673,6 +665,9 @@ intel_set_span_functions(struct intel_context *intel, return; } + /* If in GEM mode, we need to do the tile address swizzling ourselves, + * instead of the fence registers handling it. + */ switch (irb->texformat) { case MESA_FORMAT_RGB565: switch (tiling) { -- cgit v1.2.3 From 8451b29d9628f09b65962385bfbd95cd7f26427f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Sat, 21 Nov 2009 13:33:21 +0100 Subject: i965: Fix several memory leaks on exit. Bug #25194. --- src/mesa/drivers/dri/i965/brw_state.h | 1 + src/mesa/drivers/dri/i965/brw_state_upload.c | 2 +- src/mesa/drivers/dri/i965/brw_vtbl.c | 12 +++++++++--- src/mesa/drivers/dri/i965/brw_wm.c | 1 - 4 files changed, 11 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index ab6f158080..b129b1f1c3 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -112,6 +112,7 @@ void brw_validate_state(struct brw_context *brw); void brw_upload_state(struct brw_context *brw); void brw_init_state(struct brw_context *brw); void brw_destroy_state(struct brw_context *brw); +void brw_clear_validated_bos(struct brw_context *brw); /*********************************************************************** * brw_state_cache.c diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index f4283bda1b..af8dfb4c15 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -143,7 +143,7 @@ static void xor_states( struct brw_state_flags *result, result->cache = a->cache ^ b->cache; } -static void +void brw_clear_validated_bos(struct brw_context *brw) { int i; diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 114e6bd018..34aaea3736 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -46,7 +46,7 @@ #include "brw_state.h" #include "brw_fallback.h" #include "brw_vs.h" - +#include "brw_wm.h" static void dri_bo_release(dri_bo **bo) @@ -66,8 +66,14 @@ static void brw_destroy_context( struct intel_context *intel ) brw_destroy_state(brw); brw_draw_destroy( brw ); - - _mesa_free(brw->wm.compile_data); + brw_clear_validated_bos(brw); + if (brw->wm.compile_data) { + _mesa_free(brw->wm.compile_data->instruction); + _mesa_free(brw->wm.compile_data->vreg); + _mesa_free(brw->wm.compile_data->refs); + _mesa_free(brw->wm.compile_data->prog_instructions); + _mesa_free(brw->wm.compile_data); + } for (i = 0; i < brw->state.nr_color_regions; i++) intel_region_release(&brw->state.color_regions[i]); diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 77e3b2c32a..6895f64410 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -157,7 +157,6 @@ static void do_wm_prog( struct brw_context *brw, sizeof(*c->prog_instructions)); c->vreg = _mesa_calloc(BRW_WM_MAX_VREG * sizeof(*c->vreg)); c->refs = _mesa_calloc(BRW_WM_MAX_REF * sizeof(*c->refs)); - c->vreg = _mesa_calloc(BRW_WM_MAX_VREG * sizeof(*c->vreg)); } else { void *instruction = c->instruction; void *prog_instructions = c->prog_instructions; -- cgit v1.2.3 From 853d4807fe220b17cf5af5a76b24f2466238013b Mon Sep 17 00:00:00 2001 From: Michal Krol Date: Tue, 1 Dec 2009 11:19:33 +0100 Subject: mesa: Update vertex texture code after gallium changes. --- src/mesa/drivers/dri/i965/brw_context.c | 1 + src/mesa/main/context.c | 1 + src/mesa/main/get.c | 8 ++++---- src/mesa/main/get_gen.py | 2 +- src/mesa/main/mtypes.h | 1 + src/mesa/state_tracker/st_atom_sampler.c | 9 +++++++++ src/mesa/state_tracker/st_atom_texture.c | 8 ++++++++ src/mesa/state_tracker/st_extensions.c | 4 ++++ 8 files changed, 29 insertions(+), 5 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 48685c087b..8bdda60697 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -111,6 +111,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits, ctx->Const.MaxTextureImageUnits); ctx->Const.MaxVertexTextureImageUnits = 0; /* no vertex shader textures */ + ctx->Const.MaxCombinedTextureImageUnits = 0; /* Mesa limits textures to 4kx4k; it would be nice to fix that someday */ diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index b5bf46718f..03fc57e665 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -575,6 +575,7 @@ _mesa_init_constants(GLcontext *ctx) #if FEATURE_ARB_vertex_shader ctx->Const.MaxVertexTextureImageUnits = MAX_VERTEX_TEXTURE_IMAGE_UNITS; + ctx->Const.MaxCombinedTextureImageUnits = MAX_COMBINED_TEXTURE_IMAGE_UNITS; ctx->Const.MaxVarying = MAX_VARYING; #endif diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c index 6c5ce02913..e8932f83b6 100644 --- a/src/mesa/main/get.c +++ b/src/mesa/main/get.c @@ -1876,7 +1876,7 @@ _mesa_GetBooleanv( GLenum pname, GLboolean *params ) break; case GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS_ARB: CHECK_EXT1(ARB_vertex_shader, "GetBooleanv"); - params[0] = INT_TO_BOOLEAN(MAX_COMBINED_TEXTURE_IMAGE_UNITS); + params[0] = INT_TO_BOOLEAN(ctx->Const.MaxCombinedTextureImageUnits); break; case GL_CURRENT_PROGRAM: CHECK_EXT1(ARB_shader_objects, "GetBooleanv"); @@ -3711,7 +3711,7 @@ _mesa_GetFloatv( GLenum pname, GLfloat *params ) break; case GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS_ARB: CHECK_EXT1(ARB_vertex_shader, "GetFloatv"); - params[0] = (GLfloat)(MAX_COMBINED_TEXTURE_IMAGE_UNITS); + params[0] = (GLfloat)(ctx->Const.MaxCombinedTextureImageUnits); break; case GL_CURRENT_PROGRAM: CHECK_EXT1(ARB_shader_objects, "GetFloatv"); @@ -5546,7 +5546,7 @@ _mesa_GetIntegerv( GLenum pname, GLint *params ) break; case GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS_ARB: CHECK_EXT1(ARB_vertex_shader, "GetIntegerv"); - params[0] = MAX_COMBINED_TEXTURE_IMAGE_UNITS; + params[0] = ctx->Const.MaxCombinedTextureImageUnits; break; case GL_CURRENT_PROGRAM: CHECK_EXT1(ARB_shader_objects, "GetIntegerv"); @@ -7382,7 +7382,7 @@ _mesa_GetInteger64v( GLenum pname, GLint64 *params ) break; case GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS_ARB: CHECK_EXT1(ARB_vertex_shader, "GetInteger64v"); - params[0] = (GLint64)(MAX_COMBINED_TEXTURE_IMAGE_UNITS); + params[0] = (GLint64)(ctx->Const.MaxCombinedTextureImageUnits); break; case GL_CURRENT_PROGRAM: CHECK_EXT1(ARB_shader_objects, "GetInteger64v"); diff --git a/src/mesa/main/get_gen.py b/src/mesa/main/get_gen.py index 930c3362fa..a29962d334 100644 --- a/src/mesa/main/get_gen.py +++ b/src/mesa/main/get_gen.py @@ -1006,7 +1006,7 @@ StateVars = [ ( "GL_MAX_VERTEX_TEXTURE_IMAGE_UNITS_ARB", GLint, ["ctx->Const.MaxVertexTextureImageUnits"], "", ["ARB_vertex_shader"] ), ( "GL_MAX_COMBINED_TEXTURE_IMAGE_UNITS_ARB", GLint, - ["MAX_COMBINED_TEXTURE_IMAGE_UNITS"], "", ["ARB_vertex_shader"] ), + ["ctx->Const.MaxCombinedTextureImageUnits"], "", ["ARB_vertex_shader"] ), # GL_ARB_shader_objects # Actually, this token isn't part of GL_ARB_shader_objects, but is diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 881d233ca3..5f01244827 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -2319,6 +2319,7 @@ struct gl_constants GLuint MaxTextureCoordUnits; GLuint MaxTextureImageUnits; GLuint MaxVertexTextureImageUnits; + GLuint MaxCombinedTextureImageUnits; GLuint MaxTextureUnits; /**< = MIN(CoordUnits, ImageUnits) */ GLfloat MaxTextureMaxAnisotropy; /**< GL_EXT_texture_filter_anisotropic */ GLfloat MaxTextureLodBias; /**< GL_EXT_texture_lod_bias */ diff --git a/src/mesa/state_tracker/st_atom_sampler.c b/src/mesa/state_tracker/st_atom_sampler.c index 6611956ae8..d6e3a3e561 100644 --- a/src/mesa/state_tracker/st_atom_sampler.c +++ b/src/mesa/state_tracker/st_atom_sampler.c @@ -229,14 +229,23 @@ update_samplers(struct st_context *st) /*printf("%s su=%u non-null\n", __FUNCTION__, su);*/ cso_single_sampler(st->cso_context, su, sampler); + if (su < st->ctx->Const.MaxVertexTextureImageUnits) { + cso_single_vertex_sampler(st->cso_context, su, sampler); + } } else { /*printf("%s su=%u null\n", __FUNCTION__, su);*/ cso_single_sampler(st->cso_context, su, NULL); + if (su < st->ctx->Const.MaxVertexTextureImageUnits) { + cso_single_vertex_sampler(st->cso_context, su, NULL); + } } } cso_single_sampler_done(st->cso_context); + if (st->ctx->Const.MaxVertexTextureImageUnits > 0) { + cso_single_vertex_sampler_done(st->cso_context); + } } diff --git a/src/mesa/state_tracker/st_atom_texture.c b/src/mesa/state_tracker/st_atom_texture.c index 4d4f97da7e..0b68447d21 100644 --- a/src/mesa/state_tracker/st_atom_texture.c +++ b/src/mesa/state_tracker/st_atom_texture.c @@ -32,6 +32,8 @@ */ +#include "main/macros.h" + #include "st_context.h" #include "st_atom.h" #include "st_texture.h" @@ -99,6 +101,12 @@ update_textures(struct st_context *st) cso_set_sampler_textures(st->cso_context, st->state.num_textures, st->state.sampler_texture); + if (st->ctx->Const.MaxVertexTextureImageUnits > 0) { + cso_set_vertex_sampler_textures(st->cso_context, + MIN2(st->state.num_textures, + st->ctx->Const.MaxVertexTextureImageUnits), + st->state.sampler_texture); + } } diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index 57fe72d76a..ef3cbc53ee 100644 --- a/src/mesa/state_tracker/st_extensions.c +++ b/src/mesa/state_tracker/st_extensions.c @@ -92,6 +92,10 @@ void st_init_limits(struct st_context *st) = _min(screen->get_param(screen, PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS), MAX_VERTEX_TEXTURE_IMAGE_UNITS); + c->MaxCombinedTextureImageUnits + = _min(screen->get_param(screen, PIPE_CAP_MAX_COMBINED_SAMPLERS), + MAX_COMBINED_TEXTURE_IMAGE_UNITS); + c->MaxTextureCoordUnits = _min(c->MaxTextureImageUnits, MAX_TEXTURE_COORD_UNITS); -- cgit v1.2.3 From f06c8bd8dd961c9b722759b5d1f8fca78023aba8 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 15 Dec 2009 14:32:47 -0800 Subject: i965: Add support for OPCODE_CMP in the VS to fix GLSL sqrt() Bug #25628. Fixes piglit case glsl-vs-sqrt-zero. --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 00efd3443d..27aac8b54a 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -392,6 +392,17 @@ static void emit_sge( struct brw_vs_compile *c, emit_sop(c, dst, arg0, arg1, BRW_CONDITIONAL_GE); } +static void emit_cmp( struct brw_compile *p, + struct brw_reg dst, + struct brw_reg arg0, + struct brw_reg arg1, + struct brw_reg arg2 ) +{ + brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, arg0, brw_imm_f(0)); + brw_SEL(p, dst, arg1, arg2); + brw_set_predicate_control(p, BRW_PREDICATE_NONE); +} + static void emit_max( struct brw_compile *p, struct brw_reg dst, struct brw_reg arg0, @@ -1485,6 +1496,9 @@ void brw_vs_emit(struct brw_vs_compile *c ) brw_MOV(p, brw_acc_reg(), args[2]); brw_MAC(p, dst, args[0], args[1]); break; + case OPCODE_CMP: + emit_cmp(p, dst, args[0], args[1], args[2]); + break; case OPCODE_MAX: emit_max(p, dst, args[0], args[1]); break; -- cgit v1.2.3 From 51e945ec9c0b803f5e998f87449fb02a7c39ae65 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 10 Dec 2009 09:16:37 -0800 Subject: intel: Attempt to fix up after "Update vertex texture code." The MaxCombinedTextureImageUnits is the total number of samplers that can be bound between vertex, geometry, and fragment, not 0. This should report the correct value on 965 now. Other DRI drivers may also need updating if their MaxVertexTextureImageUnits != 0 (for example, if using the sw vertex pipeline). It's not clear to me if there's going to be a valid value for this limit other than MaxTextureImageUnits + MaxVertexTextureImageUnits (+ MaxGeometryTextureImageUnits eventually). If not, then we should probably just move this into the core at Get time. Bug #25518 (wine regression). Fixes piglit vp-combined-image-units. --- src/mesa/drivers/dri/i915/i915_context.c | 3 +++ src/mesa/drivers/dri/i965/brw_context.c | 4 +++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c index 7d4c7cfbab..0485be2cc1 100644 --- a/src/mesa/drivers/dri/i915/i915_context.c +++ b/src/mesa/drivers/dri/i915/i915_context.c @@ -143,6 +143,9 @@ i915CreateContext(const __GLcontextModes * mesaVis, ctx->Const.MaxTextureImageUnits = I915_TEX_UNITS; ctx->Const.MaxTextureCoordUnits = I915_TEX_UNITS; ctx->Const.MaxVarying = I915_TEX_UNITS; + ctx->Const.MaxCombinedTextureImageUnits = + ctx->Const.MaxVertexTextureImageUnits + + ctx->Const.MaxTextureImageUnits; /* Advertise the full hardware capabilities. The new memory * manager should cope much better with overload situations: diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 8bdda60697..78bea82949 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -111,7 +111,9 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureCoordUnits, ctx->Const.MaxTextureImageUnits); ctx->Const.MaxVertexTextureImageUnits = 0; /* no vertex shader textures */ - ctx->Const.MaxCombinedTextureImageUnits = 0; + ctx->Const.MaxCombinedTextureImageUnits = + ctx->Const.MaxVertexTextureImageUnits + + ctx->Const.MaxTextureImageUnits; /* Mesa limits textures to 4kx4k; it would be nice to fix that someday */ -- cgit v1.2.3 From 3078bd136d6ee1d9ad16b4c834cad23b005304a4 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 09:57:27 -0800 Subject: intel: Axe intel_renderbuffer::texformat Since the texformat branch merge, the value of intel_renderbuffer::texformat is just a copy of gl_renderbuffer::Format. --- src/mesa/drivers/dri/i915/i830_vtbl.c | 4 ++-- src/mesa/drivers/dri/i915/i915_vtbl.c | 4 ++-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 ++-- src/mesa/drivers/dri/intel/intel_blit.c | 4 ++-- src/mesa/drivers/dri/intel/intel_fbo.c | 13 ++----------- src/mesa/drivers/dri/intel/intel_fbo.h | 2 -- src/mesa/drivers/dri/intel/intel_span.c | 6 +++--- 7 files changed, 13 insertions(+), 24 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index a6f554701e..e8c8d5a048 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -645,7 +645,7 @@ i830_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */ if (irb != NULL) { - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; @@ -661,7 +661,7 @@ i830_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat); + irb->Base.Format); } } diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 77ba8d5581..ff97e5a944 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -587,7 +587,7 @@ i915_state_draw_region(struct intel_context *intel, DSTORG_VERT_BIAS(0x8) | /* .5 */ LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL); if (irb != NULL) { - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: value |= DV_PF_8888; @@ -603,7 +603,7 @@ i915_state_draw_region(struct intel_context *intel, break; default: _mesa_problem(ctx, "Bad renderbuffer format: %d\n", - irb->texformat); + irb->Base.Format); } } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 47035cc6fc..b7b6eaec2b 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -537,7 +537,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, region_bo = region->buffer; key.surface_type = BRW_SURFACE_2D; - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; @@ -554,7 +554,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM; break; default: - _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->texformat); + _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format); } key.tiling = region->tiling; if (brw->intel.intelScreen->driScrnPriv->dri2.enabled) { diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 817223da41..9f638b0ef9 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -496,7 +496,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: clearVal = intel->ClearColor8888; @@ -514,7 +514,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) break; default: _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n", - irb->texformat); + irb->Base.Format); clearVal = 0; } } diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 679fa2f82a..649fd1a78f 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -117,7 +117,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB5: rb->Format = MESA_FORMAT_RGB565; rb->DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_RGB565; cpp = 2; break; case GL_RGB: @@ -125,9 +124,8 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGB10: case GL_RGB12: case GL_RGB16: - rb->Format = MESA_FORMAT_ARGB8888; + rb->Format = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ rb->DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; /* XXX: Need xrgb8888 */ cpp = 4; break; case GL_RGBA: @@ -140,7 +138,6 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, case GL_RGBA16: rb->Format = MESA_FORMAT_ARGB8888; rb->DataType = GL_UNSIGNED_BYTE; - irb->texformat = MESA_FORMAT_ARGB8888; cpp = 4; break; case GL_STENCIL_INDEX: @@ -152,13 +149,11 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; cpp = 4; - irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_COMPONENT16: rb->Format = MESA_FORMAT_Z16; rb->DataType = GL_UNSIGNED_SHORT; cpp = 2; - irb->texformat = MESA_FORMAT_Z16; break; case GL_DEPTH_COMPONENT: case GL_DEPTH_COMPONENT24: @@ -166,14 +161,12 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; cpp = 4; - irb->texformat = MESA_FORMAT_S8_Z24; break; case GL_DEPTH_STENCIL_EXT: case GL_DEPTH24_STENCIL8_EXT: rb->Format = MESA_FORMAT_S8_Z24; rb->DataType = GL_UNSIGNED_INT_24_8_EXT; cpp = 4; - irb->texformat = MESA_FORMAT_S8_Z24; break; default: _mesa_problem(ctx, @@ -347,7 +340,6 @@ intel_create_renderbuffer(gl_format format) irb->Base.Format = format; irb->Base.InternalFormat = irb->Base._BaseFormat; - irb->texformat = format; /* intel-specific methods */ irb->Base.Delete = intel_delete_renderbuffer; @@ -424,7 +416,6 @@ static GLboolean intel_update_wrapper(GLcontext *ctx, struct intel_renderbuffer *irb, struct gl_texture_image *texImage) { - irb->texformat = texImage->TexFormat; gl_format texFormat; if (texImage->TexFormat == MESA_FORMAT_ARGB8888) { @@ -640,7 +631,7 @@ intel_validate_framebuffer(GLcontext *ctx, struct gl_framebuffer *fb) continue; } - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_ARGB8888: case MESA_FORMAT_XRGB8888: case MESA_FORMAT_RGB565: diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index 50a8a95985..fa43077d6a 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -62,8 +62,6 @@ struct intel_renderbuffer struct gl_renderbuffer Base; struct intel_region *region; - gl_format texformat; - GLuint vbl_pending; /**< vblank sequence number of pending flip */ uint8_t *span_cache; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 3607c7dded..f02fbe9875 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -624,7 +624,7 @@ intel_set_span_functions(struct intel_context *intel, tiling = I915_TILING_NONE; if (intel->intelScreen->kernel_exec_fencing) { - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_RGB565: intel_gttmap_InitPointers_RGB565(rb); break; @@ -667,13 +667,13 @@ intel_set_span_functions(struct intel_context *intel, default: _mesa_problem(NULL, "Unexpected MesaFormat %d in intelSetSpanFunctions", - irb->texformat); + irb->Base.Format); break; } return; } - switch (irb->texformat) { + switch (irb->Base.Format) { case MESA_FORMAT_RGB565: switch (tiling) { case I915_TILING_NONE: -- cgit v1.2.3 From eadd9b8e16e3b1ad35fec54f780a0f94ac43988f Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 21:13:05 -0800 Subject: i965: Fix handling of drawing to MESA_FORMAT_XRGB8888 It turns out that 965 and friends cannot actually render to an xRGB surfaces. Instead, the surface has to be RGBA with writes to alpha disabled and the blend function modified to always use 1.0 for destination alpha. --- src/mesa/drivers/dri/i965/brw_cc.c | 34 ++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 17 +++++++++--- 2 files changed, 48 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index d4ccd28c9e..ab301b9a3a 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -34,6 +34,7 @@ #include "brw_state.h" #include "brw_defines.h" #include "brw_util.h" +#include "intel_fbo.h" #include "main/macros.h" #include "main/enums.h" @@ -89,6 +90,28 @@ struct brw_cc_unit_key { GLenum depth_func; }; +/** + * Modify blend function to force destination alpha to 1.0 + * + * If \c function specifies a blend function that uses destination alpha, + * replace it with a function that hard-wires destination alpha to 1.0. This + * is used when rendering to xRGB targets. + */ +static GLenum +fix_xRGB_alpha(GLenum function) +{ + switch (function) { + case GL_DST_ALPHA: + return GL_ONE; + + case GL_ONE_MINUS_DST_ALPHA: + case GL_SRC_ALPHA_SATURATE: + return GL_ZERO; + } + + return function; +} + static void cc_unit_populate_key(struct brw_context *brw, struct brw_cc_unit_key *key) { @@ -132,6 +155,17 @@ cc_unit_populate_key(struct brw_context *brw, struct brw_cc_unit_key *key) key->blend_dst_rgb = ctx->Color.BlendDstRGB; key->blend_src_a = ctx->Color.BlendSrcA; key->blend_dst_a = ctx->Color.BlendDstA; + + /* If the renderbuffer is XRGB, we have to frob the blend function to + * force the destination alpha to 1.0. This means replacing GL_DST_ALPHA + * with GL_ONE and GL_ONE_MINUS_DST_ALPAH with GL_ZERO. + */ + if (ctx->Visual.alphaBits == 0) { + key->blend_src_rgb = fix_xRGB_alpha(key->blend_src_rgb); + key->blend_src_a = fix_xRGB_alpha(key->blend_src_a); + key->blend_dst_rgb = fix_xRGB_alpha(key->blend_dst_rgb); + key->blend_dst_a = fix_xRGB_alpha(key->blend_dst_a); + } } key->alpha_enabled = ctx->Color.AlphaEnabled; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index b7b6eaec2b..74cf66f9f8 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -538,11 +538,15 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.surface_type = BRW_SURFACE_2D; switch (irb->Base.Format) { + /* XRGB and ARGB are treated the same here because the chips in this + * family cannot render to XRGB targets. This means that we have to + * mask writes to alpha (ala glColorMask) and reconfigure the alpha + * blending hardware to use GL_ONE (or GL_ZERO) for cases where + * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used. + */ case MESA_FORMAT_ARGB8888: - key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; - break; case MESA_FORMAT_XRGB8888: - key.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; + key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; case MESA_FORMAT_RGB565: key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; @@ -579,6 +583,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw, /* _NEW_COLOR */ memcpy(key.color_mask, ctx->Color.ColorMask, sizeof(key.color_mask)); + + /* As mentioned above, disable writes to the alpha component when the + * renderbuffer is XRGB. + */ + if (ctx->Visual.alphaBits == 0) + key.color_mask[3] = GL_FALSE; + key.color_blend = (!ctx->Color._LogicOpEnabled && ctx->Color.BlendEnabled); -- cgit v1.2.3 From e624b77eb2d594cde053c73a530836e05227126a Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 8 Dec 2009 23:25:26 -0800 Subject: intel: Remove ARGB internal_format == GL_RGB hacks Now that XRGB is supported, we don't need to hack around cases of an RGBA format buffer with an internal format of GL_RGB. --- src/mesa/drivers/dri/i915/i830_texstate.c | 5 +-- src/mesa/drivers/dri/i915/i915_texstate.c | 5 +-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 10 +---- src/mesa/drivers/dri/intel/intel_span.c | 49 +++++++----------------- 4 files changed, 17 insertions(+), 52 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index f4bbb53b86..ce409b3a60 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -55,10 +55,7 @@ translate_texture_format(GLuint mesa_format, GLuint internal_format) case MESA_FORMAT_ARGB4444: return MAPSURF_16BIT | MT_16BIT_ARGB4444; case MESA_FORMAT_ARGB8888: - if (internal_format == GL_RGB) - return MAPSURF_32BIT | MT_32BIT_XRGB8888; - else - return MAPSURF_32BIT | MT_32BIT_ARGB8888; + return MAPSURF_32BIT | MT_32BIT_ARGB8888; case MESA_FORMAT_XRGB8888: return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index d6689af53f..f52ff2bcc4 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -56,10 +56,7 @@ translate_texture_format(gl_format mesa_format, GLuint internal_format, case MESA_FORMAT_ARGB4444: return MAPSURF_16BIT | MT_16BIT_ARGB4444; case MESA_FORMAT_ARGB8888: - if (internal_format == GL_RGB) - return MAPSURF_32BIT | MT_32BIT_XRGB8888; - else - return MAPSURF_32BIT | MT_32BIT_ARGB8888; + return MAPSURF_32BIT | MT_32BIT_ARGB8888; case MESA_FORMAT_XRGB8888: return MAPSURF_32BIT | MT_32BIT_XRGB8888; case MESA_FORMAT_YCBCR_REV: diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 74cf66f9f8..3f9b1fbfdc 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -94,20 +94,14 @@ static GLuint translate_tex_format( gl_format mesa_format, return BRW_SURFACEFORMAT_R8G8B8_UNORM; case MESA_FORMAT_ARGB8888: - if (internal_format == GL_RGB) - return BRW_SURFACEFORMAT_B8G8R8X8_UNORM; - else - return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; + return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; case MESA_FORMAT_XRGB8888: return BRW_SURFACEFORMAT_B8G8R8X8_UNORM; case MESA_FORMAT_RGBA8888_REV: _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()"); - if (internal_format == GL_RGB) - return BRW_SURFACEFORMAT_R8G8B8X8_UNORM; - else - return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; + return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; case MESA_FORMAT_RGB565: return BRW_SURFACEFORMAT_B5G6R5_UNORM; diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 725ba5c97d..34c3d9df74 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -638,13 +638,7 @@ intel_set_span_functions(struct intel_context *intel, intel_gttmap_InitPointers_xRGB8888(rb); break; case MESA_FORMAT_ARGB8888: - if (rb->_BaseFormat == GL_RGB) { - /* XXX remove this code someday when we enable XRGB surfaces */ - /* 8888 RGBx */ - intel_gttmap_InitPointers_xRGB8888(rb); - } else { - intel_gttmap_InitPointers_ARGB8888(rb); - } + intel_gttmap_InitPointers_ARGB8888(rb); break; case MESA_FORMAT_Z16: intel_gttmap_InitDepthPointers_z16(rb); @@ -731,35 +725,18 @@ intel_set_span_functions(struct intel_context *intel, } break; case MESA_FORMAT_ARGB8888: - if (rb->_BaseFormat == GL_RGB) { - /* XXX remove this code someday when we enable XRGB surfaces */ - /* 8888 RGBx */ - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_xRGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_xRGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_xRGB8888(rb); - break; - } - } else { - /* 8888 RGBA */ - switch (tiling) { - case I915_TILING_NONE: - default: - intelInitPointers_ARGB8888(rb); - break; - case I915_TILING_X: - intel_XTile_InitPointers_ARGB8888(rb); - break; - case I915_TILING_Y: - intel_YTile_InitPointers_ARGB8888(rb); - break; - } + /* 8888 RGBA */ + switch (tiling) { + case I915_TILING_NONE: + default: + intelInitPointers_ARGB8888(rb); + break; + case I915_TILING_X: + intel_XTile_InitPointers_ARGB8888(rb); + break; + case I915_TILING_Y: + intel_YTile_InitPointers_ARGB8888(rb); + break; } break; case MESA_FORMAT_Z16: -- cgit v1.2.3 From 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 16 Dec 2009 14:45:50 -0800 Subject: intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync. Saves ~480 bytes of code. --- src/mesa/drivers/dri/i965/brw_clip.c | 11 ++++++----- src/mesa/drivers/dri/i965/brw_clip.h | 1 - src/mesa/drivers/dri/i965/brw_clip_line.c | 3 ++- src/mesa/drivers/dri/i965/brw_clip_state.c | 3 ++- src/mesa/drivers/dri/i965/brw_clip_tri.c | 5 +++-- src/mesa/drivers/dri/i965/brw_clip_util.c | 8 ++++++-- src/mesa/drivers/dri/i965/brw_draw_upload.c | 4 ++-- src/mesa/drivers/dri/i965/brw_eu_emit.c | 27 ++++++++++++++++++--------- src/mesa/drivers/dri/i965/brw_gs.c | 4 ++-- src/mesa/drivers/dri/i965/brw_gs.h | 1 - src/mesa/drivers/dri/i965/brw_gs_emit.c | 20 +++++++++++++++----- src/mesa/drivers/dri/i965/brw_gs_state.c | 3 ++- src/mesa/drivers/dri/i965/brw_misc_state.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_sf_emit.c | 6 ++++-- src/mesa/drivers/dri/i965/brw_sf_state.c | 9 +++++---- src/mesa/drivers/dri/i965/brw_tex_layout.c | 2 +- src/mesa/drivers/dri/i965/brw_urb.c | 3 ++- src/mesa/drivers/dri/i965/brw_vs_emit.c | 13 ++++++++----- src/mesa/drivers/dri/i965/brw_vs_state.c | 7 ++++--- src/mesa/drivers/dri/i965/brw_wm_emit.c | 15 +++++++++------ src/mesa/drivers/dri/i965/brw_wm_glsl.c | 3 ++- src/mesa/drivers/dri/i965/brw_wm_state.c | 7 ++++--- src/mesa/drivers/dri/intel/intel_context.c | 5 +++++ src/mesa/drivers/dri/intel/intel_context.h | 2 ++ 24 files changed, 108 insertions(+), 62 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c index dbd10a5297..af1d975de9 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.c +++ b/src/mesa/drivers/dri/i965/brw_clip.c @@ -50,6 +50,7 @@ static void compile_clip_prog( struct brw_context *brw, struct brw_clip_prog_key *key ) { + struct intel_context *intel = &brw->intel; struct brw_clip_compile c; const GLuint *program; GLuint program_size; @@ -65,14 +66,13 @@ static void compile_clip_prog( struct brw_context *brw, c.func.single_program_flow = 1; c.key = *key; - c.need_ff_sync = BRW_IS_IGDNG(brw); /* Need to locate the two positions present in vertex + header. * These are currently hardcoded: */ c.header_position_offset = ATTR_SIZE; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) delta = 3 * REG_SIZE; else delta = REG_SIZE; @@ -85,7 +85,7 @@ static void compile_clip_prog( struct brw_context *brw, c.nr_attrs = brw_count_bits(c.key.attrs); - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ else c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ @@ -143,7 +143,8 @@ static void compile_clip_prog( struct brw_context *brw, */ static void upload_clip_prog(struct brw_context *brw) { - GLcontext *ctx = &brw->intel.ctx; + struct intel_context *intel = &brw->intel; + GLcontext *ctx = &intel->ctx; struct brw_clip_prog_key key; memset(&key, 0, sizeof(key)); @@ -160,7 +161,7 @@ static void upload_clip_prog(struct brw_context *brw) /* _NEW_TRANSFORM */ key.nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled); - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) key.clip_mode = BRW_CLIPMODE_KERNEL_CLIP; else key.clip_mode = BRW_CLIPMODE_NORMAL; diff --git a/src/mesa/drivers/dri/i965/brw_clip.h b/src/mesa/drivers/dri/i965/brw_clip.h index 1c6825510a..d71bac7f61 100644 --- a/src/mesa/drivers/dri/i965/brw_clip.h +++ b/src/mesa/drivers/dri/i965/brw_clip.h @@ -118,7 +118,6 @@ struct brw_clip_compile { GLuint header_position_offset; GLuint offset[VERT_ATTRIB_MAX]; - GLboolean need_ff_sync; }; #define ATTR_SIZE (4*4) diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index fa9648f50f..59727af88d 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -46,6 +46,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) { + struct intel_context *intel = &c->func.brw->intel; GLuint i = 0,j; /* Register usage is static, precompute here: @@ -85,7 +86,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) i++; } - if (c->need_ff_sync) { + if (intel->needs_ff_sync) { c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; } diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index 234b3744bf..28ed634631 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -74,6 +74,7 @@ static dri_bo * clip_unit_create_from_key(struct brw_context *brw, struct brw_clip_unit_key *key) { + struct intel_context *intel = &brw->intel; struct brw_clip_unit_state clip; dri_bo *bo; @@ -105,7 +106,7 @@ clip_unit_create_from_key(struct brw_context *brw, /* Although up to 16 concurrent Clip threads are allowed on IGDNG, * only 2 threads can output VUEs at a time. */ - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) clip.thread4.max_threads = 16 - 1; else clip.thread4.max_threads = 2 - 1; diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index cf79224be4..ec15e9a697 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -51,6 +51,7 @@ static void release_tmps( struct brw_clip_compile *c ) void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, GLuint nr_verts ) { + struct intel_context *intel = &c->func.brw->intel; GLuint i = 0,j; /* Register usage is static, precompute here: @@ -78,7 +79,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, for (j = 0; j < 3; j++) { GLuint delta = c->nr_attrs*16 + 32; - if (BRW_IS_IGDNG(c->func.brw)) + if (intel->is_ironlake) delta = c->nr_attrs * 16 + 32 * 3; brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0)); @@ -119,7 +120,7 @@ void brw_clip_tri_alloc_regs( struct brw_clip_compile *c, i++; } - if (c->need_ff_sync) { + if (intel->needs_ff_sync) { c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); i++; } diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c index 5a73abdfee..091ebfc34c 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_util.c +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c @@ -359,7 +359,9 @@ void brw_clip_init_clipmask( struct brw_clip_compile *c ) void brw_clip_ff_sync(struct brw_clip_compile *c) { - if (c->need_ff_sync) { + struct intel_context *intel = &c->func.brw->intel; + + if (intel->needs_ff_sync) { struct brw_compile *p = &c->func; struct brw_instruction *need_ff_sync; @@ -388,7 +390,9 @@ void brw_clip_ff_sync(struct brw_clip_compile *c) void brw_clip_init_ff_sync(struct brw_clip_compile *c) { - if (c->need_ff_sync) { + struct intel_context *intel = &c->func.brw->intel; + + if (intel->needs_ff_sync) { struct brw_compile *p = &c->func; brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0)); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 7c796dae93..2c9902c90f 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -527,7 +527,7 @@ static void brw_emit_vertices(struct brw_context *brw) OUT_RELOC(input->bo, I915_GEM_DOMAIN_VERTEX, 0, input->offset); - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { OUT_RELOC(input->bo, I915_GEM_DOMAIN_VERTEX, 0, input->bo->size - 1); @@ -563,7 +563,7 @@ static void brw_emit_vertices(struct brw_context *brw) (format << BRW_VE0_FORMAT_SHIFT) | (0 << BRW_VE0_SRC_OFFSET_SHIFT)); - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) | (comp1 << BRW_VE1_COMPONENT_1_SHIFT) | (comp2 << BRW_VE1_COMPONENT_2_SHIFT) | diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 7ceabba288..67673e9911 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -252,9 +252,10 @@ static void brw_set_math_message( struct brw_context *brw, GLboolean saturate, GLuint dataType ) { + struct intel_context *intel = &brw->intel; brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { insn->bits3.math_igdng.function = function; insn->bits3.math_igdng.int_type = integer_type; insn->bits3.math_igdng.precision = low_precision; @@ -319,9 +320,10 @@ static void brw_set_urb_message( struct brw_context *brw, GLuint offset, GLuint swizzle_control ) { + struct intel_context *intel = &brw->intel; brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { insn->bits3.urb_igdng.opcode = 0; /* ? */ insn->bits3.urb_igdng.offset = offset; insn->bits3.urb_igdng.swizzle_control = swizzle_control; @@ -358,9 +360,10 @@ static void brw_set_dp_write_message( struct brw_context *brw, GLuint response_length, GLuint end_of_thread ) { + struct intel_context *intel = &brw->intel; brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { insn->bits3.dp_write_igdng.binding_table_index = binding_table_index; insn->bits3.dp_write_igdng.msg_control = msg_control; insn->bits3.dp_write_igdng.pixel_scoreboard_clear = pixel_scoreboard_clear; @@ -395,9 +398,10 @@ static void brw_set_dp_read_message( struct brw_context *brw, GLuint response_length, GLuint end_of_thread ) { + struct intel_context *intel = &brw->intel; brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { insn->bits3.dp_read_igdng.binding_table_index = binding_table_index; insn->bits3.dp_read_igdng.msg_control = msg_control; insn->bits3.dp_read_igdng.msg_type = msg_type; @@ -433,10 +437,11 @@ static void brw_set_sampler_message(struct brw_context *brw, GLuint header_present, GLuint simd_mode) { + struct intel_context *intel = &brw->intel; assert(eot == 0); brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { insn->bits3.sampler_igdng.binding_table_index = binding_table_index; insn->bits3.sampler_igdng.sampler = sampler; insn->bits3.sampler_igdng.msg_type = msg_type; @@ -648,10 +653,11 @@ struct brw_instruction *brw_IF(struct brw_compile *p, GLuint execute_size) struct brw_instruction *brw_ELSE(struct brw_compile *p, struct brw_instruction *if_insn) { + struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; GLuint br = 1; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) br = 2; if (p->single_program_flow) { @@ -690,9 +696,10 @@ struct brw_instruction *brw_ELSE(struct brw_compile *p, void brw_ENDIF(struct brw_compile *p, struct brw_instruction *patch_insn) { + struct intel_context *intel = &p->brw->intel; GLuint br = 1; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) br = 2; if (p->single_program_flow) { @@ -803,10 +810,11 @@ struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size) struct brw_instruction *brw_WHILE(struct brw_compile *p, struct brw_instruction *do_insn) { + struct intel_context *intel = &p->brw->intel; struct brw_instruction *insn; GLuint br = 1; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) br = 2; if (p->single_program_flow) @@ -846,10 +854,11 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p, void brw_land_fwd_jump(struct brw_compile *p, struct brw_instruction *jmp_insn) { + struct intel_context *intel = &p->brw->intel; struct brw_instruction *landing = &p->store[p->nr_insn]; GLuint jmpi = 1; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) jmpi = 2; assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI); diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c index 610b6c35e2..1bc3eccf49 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.c +++ b/src/mesa/drivers/dri/i965/brw_gs.c @@ -47,6 +47,7 @@ static void compile_gs_prog( struct brw_context *brw, struct brw_gs_prog_key *key ) { + struct intel_context *intel = &brw->intel; struct brw_gs_compile c; const GLuint *program; GLuint program_size; @@ -54,13 +55,12 @@ static void compile_gs_prog( struct brw_context *brw, memset(&c, 0, sizeof(c)); c.key = *key; - c.need_ff_sync = BRW_IS_IGDNG(brw); /* Need to locate the two positions present in vertex + header. * These are currently hardcoded: */ c.nr_attrs = brw_count_bits(c.key.attrs); - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) c.nr_regs = (c.nr_attrs + 1) / 2 + 3; /* are vertices packed, or reg-aligned? */ else c.nr_regs = (c.nr_attrs + 1) / 2 + 1; /* are vertices packed, or reg-aligned? */ diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h index 010c1c2352..813b8d447a 100644 --- a/src/mesa/drivers/dri/i965/brw_gs.h +++ b/src/mesa/drivers/dri/i965/brw_gs.h @@ -63,7 +63,6 @@ struct brw_gs_compile { GLuint nr_attrs; GLuint nr_regs; GLuint nr_bytes; - GLboolean need_ff_sync; }; #define ATTR_SIZE (4*4) diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c b/src/mesa/drivers/dri/i965/brw_gs_emit.c index 0fc5b02c61..a81b972ef4 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c @@ -122,12 +122,14 @@ static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim) void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) { + struct intel_context *intel = &c->func.brw->intel; + brw_gs_alloc_regs(c, 4); /* Use polygons for correct edgeflag behaviour. Note that vertex 3 * is the PV for quads, but vertex 0 for polygons: */ - if (c->need_ff_sync) + if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); if (key->pv_first) { brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); @@ -145,9 +147,11 @@ void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) { + struct intel_context *intel = &c->func.brw->intel; + brw_gs_alloc_regs(c, 4); - if (c->need_ff_sync) + if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); if (key->pv_first) { brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START)); @@ -165,9 +169,11 @@ void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key ) void brw_gs_tris( struct brw_gs_compile *c ) { + struct intel_context *intel = &c->func.brw->intel; + brw_gs_alloc_regs(c, 3); - if (c->need_ff_sync) + if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_TRILIST << 2) | R02_PRIM_START)); brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_TRILIST << 2)); @@ -176,9 +182,11 @@ void brw_gs_tris( struct brw_gs_compile *c ) void brw_gs_lines( struct brw_gs_compile *c ) { + struct intel_context *intel = &c->func.brw->intel; + brw_gs_alloc_regs(c, 2); - if (c->need_ff_sync) + if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_START)); brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_END)); @@ -186,9 +194,11 @@ void brw_gs_lines( struct brw_gs_compile *c ) void brw_gs_points( struct brw_gs_compile *c ) { + struct intel_context *intel = &c->func.brw->intel; + brw_gs_alloc_regs(c, 1); - if (c->need_ff_sync) + if (intel->needs_ff_sync) brw_gs_ff_sync(c, 1); brw_gs_emit_vue(c, c->reg.vertex[0], 1, ((_3DPRIM_POINTLIST << 2) | R02_PRIM_START | R02_PRIM_END)); } diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c b/src/mesa/drivers/dri/i965/brw_gs_state.c index ed9d2ffe60..1af5790a67 100644 --- a/src/mesa/drivers/dri/i965/brw_gs_state.c +++ b/src/mesa/drivers/dri/i965/brw_gs_state.c @@ -72,6 +72,7 @@ gs_unit_populate_key(struct brw_context *brw, struct brw_gs_unit_key *key) static dri_bo * gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key) { + struct intel_context *intel = &brw->intel; struct brw_gs_unit_state gs; dri_bo *bo; @@ -98,7 +99,7 @@ gs_unit_create_from_key(struct brw_context *brw, struct brw_gs_unit_key *key) else gs.thread4.max_threads = 0; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) gs.thread4.rendering_enable = 1; if (INTEL_DEBUG & DEBUG_STATS) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 4b0d598336..6cb2da28e6 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -212,7 +212,7 @@ static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; - unsigned int len = (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? 6 : 5; + unsigned int len = (BRW_IS_G4X(brw) || intel->is_ironlake) ? 6 : 5; if (region == NULL) { BEGIN_BATCH(len, IGNORE_CLIPRECTS); @@ -223,7 +223,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); - if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) + if (BRW_IS_G4X(brw) || intel->is_ironlake) OUT_BATCH(0); ADVANCE_BATCH(); @@ -262,7 +262,7 @@ static void emit_depthbuffer(struct brw_context *brw) ((region->height - 1) << 19)); OUT_BATCH(0); - if (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) + if (BRW_IS_G4X(brw) || intel->is_ironlake) OUT_BATCH(0); ADVANCE_BATCH(); @@ -512,7 +512,7 @@ static void upload_state_base_address( struct brw_context *brw ) /* Output the structure (brw_state_base_address) directly to the * batchbuffer, so we can emit relocations inline. */ - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { BEGIN_BATCH(8, IGNORE_CLIPRECTS); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); OUT_BATCH(1); /* General state base address */ diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c b/src/mesa/drivers/dri/i965/brw_sf_emit.c index 3eae41ee74..bb08055e3b 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_emit.c +++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c @@ -149,6 +149,7 @@ static void copy_colors( struct brw_sf_compile *c, static void do_flatshade_triangle( struct brw_sf_compile *c ) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; struct brw_reg ip = brw_ip_reg(); GLuint nr = brw_count_bits(c->key.attrs & VERT_RESULT_COLOR_BITS); GLuint jmpi = 1; @@ -161,7 +162,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c ) if (c->key.primitive == SF_UNFILLED_TRIS) return; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) jmpi = 2; brw_push_insn_state(p); @@ -187,6 +188,7 @@ static void do_flatshade_triangle( struct brw_sf_compile *c ) static void do_flatshade_line( struct brw_sf_compile *c ) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; struct brw_reg ip = brw_ip_reg(); GLuint nr = brw_count_bits(c->key.attrs & VERT_RESULT_COLOR_BITS); GLuint jmpi = 1; @@ -199,7 +201,7 @@ static void do_flatshade_line( struct brw_sf_compile *c ) if (c->key.primitive == SF_UNFILLED_TRIS) return; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) jmpi = 2; brw_push_insn_state(p); diff --git a/src/mesa/drivers/dri/i965/brw_sf_state.c b/src/mesa/drivers/dri/i965/brw_sf_state.c index bb69435ec0..09223b7cfb 100644 --- a/src/mesa/drivers/dri/i965/brw_sf_state.c +++ b/src/mesa/drivers/dri/i965/brw_sf_state.c @@ -165,6 +165,7 @@ static dri_bo * sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, dri_bo **reloc_bufs) { + struct intel_context *intel = &brw->intel; struct brw_sf_unit_state sf; dri_bo *bo; int chipset_max_threads; @@ -177,7 +178,7 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, sf.thread3.dispatch_grf_start_reg = 3; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) sf.thread3.urb_entry_read_offset = 3; else sf.thread3.urb_entry_read_offset = 1; @@ -187,10 +188,10 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key, sf.thread4.nr_urb_entries = key->nr_urb_entries; sf.thread4.urb_entry_allocation_size = key->sfsize - 1; - /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or - * 48(IGDNG) threads + /* Each SF thread produces 1 PUE, and there can be up to 24 (Pre-Ironlake) or + * 48 (Ironlake) threads. */ - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) chipset_max_threads = 48; else chipset_max_threads = 24; diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index e59e52ed86..64a9535282 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -49,7 +49,7 @@ GLboolean brw_miptree_layout(struct intel_context *intel, switch (mt->target) { case GL_TEXTURE_CUBE_MAP: - if (IS_IGDNG(intel->intelScreen->deviceID)) { + if (intel->is_ironlake) { GLuint align_h = 2, align_w = 4; GLuint level; GLuint x = 0; diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index 8c6f4355a6..e1e8a90ca7 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -113,6 +113,7 @@ static GLboolean check_urb_layout( struct brw_context *brw ) */ static void recalculate_urb_fence( struct brw_context *brw ) { + struct intel_context *intel = &brw->intel; GLuint csize = brw->curbe.total_size; GLuint vsize = brw->vs.prog_data->urb_entry_size; GLuint sfsize = brw->sf.prog_data->urb_entry_size; @@ -146,7 +147,7 @@ static void recalculate_urb_fence( struct brw_context *brw ) brw->urb.constrained = 0; - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { brw->urb.nr_vs_entries = 128; brw->urb.nr_sf_entries = 48; if (check_urb_layout(brw)) { diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 27aac8b54a..21d2fec707 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -67,6 +67,7 @@ static void release_tmps( struct brw_vs_compile *c ) */ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) { + struct intel_context *intel = &c->func.brw->intel; GLuint i, reg = 0, mrf; int attributes_in_vue; @@ -141,7 +142,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) c->first_output = reg; c->first_overflow_output = 0; - if (BRW_IS_IGDNG(c->func.brw)) + if (intel->is_ironlake) mrf = 8; else mrf = 4; @@ -238,7 +239,7 @@ static void brw_vs_alloc_regs( struct brw_vs_compile *c ) */ attributes_in_vue = MAX2(c->nr_outputs, c->nr_inputs); - if (BRW_IS_IGDNG(c->func.brw)) + if (intel->is_ironlake) c->prog_data.urb_entry_size = (attributes_in_vue + 6 + 3) / 4; else c->prog_data.urb_entry_size = (attributes_in_vue + 2 + 3) / 4; @@ -1113,6 +1114,7 @@ static void emit_swz( struct brw_vs_compile *c, static void emit_vertex_write( struct brw_vs_compile *c) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; struct brw_reg m0 = brw_message_reg(0); struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS]; struct brw_reg ndc; @@ -1195,8 +1197,8 @@ static void emit_vertex_write( struct brw_vs_compile *c) brw_set_access_mode(p, BRW_ALIGN_1); brw_MOV(p, offset(m0, 2), ndc); - if (BRW_IS_IGDNG(p->brw)) { - /* There are 20 DWs (D0-D19) in VUE vertex header on IGDNG */ + if (intel->is_ironlake) { + /* There are 20 DWs (D0-D19) in VUE vertex header on Ironlake */ brw_MOV(p, offset(m0, 3), pos); /* a portion of vertex header */ /* m4, m5 contain the distances from vertex to the user clip planeXXX. * Seems it is useless for us. @@ -1359,6 +1361,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) #define MAX_LOOP_DEPTH 32 struct brw_compile *p = &c->func; struct brw_context *brw = p->brw; + struct intel_context *intel = &brw->intel; const GLuint nr_insns = c->vp->program.Base.NumInstructions; GLuint insn, if_depth = 0, loop_depth = 0; GLuint end_offset = 0; @@ -1592,7 +1595,7 @@ void brw_vs_emit(struct brw_vs_compile *c ) loop_depth--; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) br = 2; inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]); diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index 7285466645..fdc55aa1b2 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -82,6 +82,7 @@ vs_unit_populate_key(struct brw_context *brw, struct brw_vs_unit_key *key) static dri_bo * vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) { + struct intel_context *intel = &brw->intel; struct brw_vs_unit_state vs; dri_bo *bo; int chipset_max_threads; @@ -98,7 +99,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) */ vs.thread1.single_program_flow = 0; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) vs.thread1.binding_table_entry_count = 0; /* hardware requirement */ else vs.thread1.binding_table_entry_count = key->nr_surfaces; @@ -109,7 +110,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) vs.thread3.urb_entry_read_offset = 0; vs.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; - if (BRW_IS_IGDNG(brw)) { + if (intel->is_ironlake) { switch (key->nr_urb_entries) { case 8: case 12: @@ -145,7 +146,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) vs.thread4.urb_entry_allocation_size = key->urb_size - 1; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) chipset_max_threads = 72; else if (BRW_IS_G4X(brw)) chipset_max_threads = 32; diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 5390fd2584..bcaa793de1 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -830,6 +830,7 @@ void emit_tex(struct brw_wm_compile *c, GLboolean shadow) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; struct brw_reg dst_retyped; GLuint cur_mrf = 2, response_length; GLuint i, nr_texcoords; @@ -873,7 +874,7 @@ void emit_tex(struct brw_wm_compile *c, } /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */ - if (!BRW_IS_IGDNG(p->brw) && c->dispatch_width == 8) + if (!intel->is_ironlake && c->dispatch_width == 8) nr_texcoords = 3; /* For shadow comparisons, we have to supply u,v,r. */ @@ -891,7 +892,7 @@ void emit_tex(struct brw_wm_compile *c, /* Fill in the shadow comparison reference value. */ if (shadow) { - if (BRW_IS_IGDNG(p->brw)) { + if (intel->is_ironlake) { /* Fill in the cube map array index value. */ brw_MOV(p, brw_message_reg(cur_mrf), brw_imm_f(0)); cur_mrf += mrf_per_channel; @@ -904,7 +905,7 @@ void emit_tex(struct brw_wm_compile *c, cur_mrf += mrf_per_channel; } - if (BRW_IS_IGDNG(p->brw)) { + if (intel->is_ironlake) { if (shadow) msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_IGDNG; else @@ -944,6 +945,7 @@ void emit_txb(struct brw_wm_compile *c, GLuint sampler) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; GLuint msgLength; GLuint msg_type; GLuint mrf_per_channel; @@ -955,8 +957,8 @@ void emit_txb(struct brw_wm_compile *c, * undefined, and trust the execution mask to keep the undefined pixels * from mattering. */ - if (c->dispatch_width == 16 || !BRW_IS_IGDNG(p->brw)) { - if (BRW_IS_IGDNG(p->brw)) + if (c->dispatch_width == 16 || !intel->is_ironlake) { + if (intel->is_ironlake) msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_IGDNG; else msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS; @@ -1160,6 +1162,7 @@ void emit_fb_write(struct brw_wm_compile *c, { struct brw_compile *p = &c->func; struct brw_context *brw = p->brw; + struct intel_context *intel = &brw->intel; GLuint nr = 2; GLuint channel; @@ -1174,7 +1177,7 @@ void emit_fb_write(struct brw_wm_compile *c, brw_push_insn_state(p); for (channel = 0; channel < 4; channel++) { - if (c->dispatch_width == 16 && (BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))) { + if (c->dispatch_width == 16 && (BRW_IS_G4X(brw) || intel->is_ironlake)) { /* By setting the high bit of the MRF register number, we indicate * that we want COMPR4 mode - instead of doing the usual destination * + 1 for the second half we get destination + 4. diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index e8c2cb66ec..f294387c80 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1826,6 +1826,7 @@ get_argument_regs(struct brw_wm_compile *c, static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) { + struct intel_context *intel = &brw->intel; #define MAX_IF_DEPTH 32 #define MAX_LOOP_DEPTH 32 struct brw_instruction *if_inst[MAX_IF_DEPTH], *loop_inst[MAX_LOOP_DEPTH]; @@ -2096,7 +2097,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) struct brw_instruction *inst0, *inst1; GLuint br = 1; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) br = 2; loop_depth--; diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index f89ed9bce7..fe795fadf8 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -71,7 +71,7 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) key->max_threads = 1; else { /* WM maximum threads is number of EUs times number of threads per EU. */ - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) key->max_threads = 12 * 6; else if (BRW_IS_G4X(brw)) key->max_threads = 10 * 5; @@ -140,6 +140,7 @@ static dri_bo * wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, dri_bo **reloc_bufs) { + struct intel_context *intel = &brw->intel; struct brw_wm_unit_state wm; dri_bo *bo; @@ -150,7 +151,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, wm.thread1.depth_coef_urb_read_offset = 1; wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) wm.thread1.binding_table_entry_count = 0; /* hardware requirement */ else wm.thread1.binding_table_entry_count = key->nr_surfaces; @@ -170,7 +171,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length; wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2; - if (BRW_IS_IGDNG(brw)) + if (intel->is_ironlake) wm.wm4.sampler_count = 0; /* hardware requirement */ else wm.wm4.sampler_count = (key->sampler_count + 1) / 4; diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index c616d32ebb..234f99a00e 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -620,6 +620,11 @@ intelInitContext(struct intel_context *intel, else intel->gen = 2; + if (IS_IGDNG(intel->intelScreen->deviceID)) { + intel->is_ironlake = GL_TRUE; + intel->needs_ff_sync = GL_TRUE; + } + /* Dri stuff */ intel->hHWContext = driContextPriv->hHWContext; intel->driFd = sPriv->fd; diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 481202c971..f7d9016d71 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -176,6 +176,8 @@ struct intel_context * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965. */ int gen; + GLboolean needs_ff_sync; + GLboolean is_ironlake; struct intel_region *front_region; struct intel_region *back_region; -- cgit v1.2.3 From 0b87f143c466f7e5bd730895ee29f1cd20a68f9b Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 16 Dec 2009 15:22:26 -0800 Subject: intel: Replace IS_G4X() across the driver with context structure usage. Saves ~2KB of code. --- src/mesa/drivers/dri/i965/brw_clip_state.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_util.c | 7 +++--- src/mesa/drivers/dri/i965/brw_context.c | 32 ++++++++++++++++++++++++ src/mesa/drivers/dri/i965/brw_context.h | 11 +++++++- src/mesa/drivers/dri/i965/brw_defines.h | 9 ++----- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- src/mesa/drivers/dri/i965/brw_fallback.c | 4 +-- src/mesa/drivers/dri/i965/brw_misc_state.c | 10 ++++---- src/mesa/drivers/dri/i965/brw_urb.c | 9 ++++--- src/mesa/drivers/dri/i965/brw_vs_state.c | 14 ++--------- src/mesa/drivers/dri/i965/brw_wm_emit.c | 3 +-- src/mesa/drivers/dri/i965/brw_wm_state.c | 18 ++----------- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 ++-- src/mesa/drivers/dri/intel/intel_context.c | 4 +++ src/mesa/drivers/dri/intel/intel_context.h | 4 +++ src/mesa/drivers/dri/intel/intel_tex_format.c | 4 +-- 16 files changed, 79 insertions(+), 59 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index 28ed634631..c8f24a94e4 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -131,7 +131,7 @@ clip_unit_create_from_key(struct brw_context *brw, clip.clip5.api_mode = BRW_CLIP_API_OGL; clip.clip5.clip_mode = key->clip_mode; - if (BRW_IS_G4X(brw)) + if (intel->is_g4x) clip.clip5.negative_w_clip_test = 1; clip.clip6.clipper_viewport_state_ptr = 0; diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c b/src/mesa/drivers/dri/i965/brw_clip_util.c index 091ebfc34c..86fed59fa4 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_util.c +++ b/src/mesa/drivers/dri/i965/brw_clip_util.c @@ -135,6 +135,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, GLboolean force_edgeflag) { struct brw_compile *p = &c->func; + struct intel_context *intel = &p->brw->intel; struct brw_reg tmp = get_tmp(c); GLuint i; @@ -142,7 +143,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, */ /* * After CLIP stage, only first 256 bits of the VUE are read - * back on IGDNG, so needn't change it + * back on Ironlake, so needn't change it */ brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1); @@ -151,7 +152,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, for (i = 0; i < c->nr_attrs; i++) { GLuint delta = i*16 + 32; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) delta = i * 16 + 32 * 3; if (delta == c->offset[VERT_RESULT_EDGE]) { @@ -185,7 +186,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c, if (i & 1) { GLuint delta = i*16 + 32; - if (BRW_IS_IGDNG(p->brw)) + if (intel->is_ironlake) delta = i * 16 + 32 * 3; brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0)); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 78bea82949..282566f8d5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -158,6 +158,38 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, MIN2(ctx->Const.FragmentProgram.MaxNativeParameters, ctx->Const.FragmentProgram.MaxEnvParams); + if (intel->is_ironlake || intel->is_g4x) { + brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_GM45; + brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45; + brw->has_surface_tile_offset = GL_TRUE; + brw->has_compr4 = GL_TRUE; + } else { + brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965; + brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965; + brw->has_surface_tile_offset = GL_FALSE; + brw->has_compr4 = GL_FALSE; + } + + /* WM maximum threads is number of EUs times number of threads per EU. */ + if (intel->is_ironlake) { + brw->urb.size = 1024; + brw->vs_max_threads = 72; + brw->wm_max_threads = 12 * 6; + } else if (intel->is_g4x) { + brw->urb.size = 384; + brw->vs_max_threads = 32; + brw->wm_max_threads = 10 * 5; + } else { + brw->urb.size = 256; + brw->vs_max_threads = 16; + brw->wm_max_threads = 8 * 4; + } + + if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) { + brw->vs_max_threads = 1; + brw->wm_max_threads = 1; + } + brw_init_state( brw ); brw->state.dirty.mesa = ~0; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index e73e21433c..4ae48bba05 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -438,7 +438,9 @@ struct brw_context GLuint primitive; GLboolean emit_state_always; - + GLboolean has_surface_tile_offset; + GLboolean has_compr4; +; struct { struct brw_state_flags dirty; @@ -514,6 +516,12 @@ struct brw_context */ GLuint next_free_page; + /* hw-dependent 3DSTATE_VF_STATISTICS opcode */ + uint32_t CMD_VF_STATISTICS; + /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */ + uint32_t CMD_PIPELINE_SELECT; + int vs_max_threads; + int wm_max_threads; /* BRW_NEW_URB_ALLOCATIONS: */ @@ -541,6 +549,7 @@ struct brw_context GLuint clip_start; GLuint sf_start; GLuint cs_start; + GLuint size; /* Hardware URB size, in KB. */ } urb; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index c19510bbd4..2ee331a200 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -832,12 +832,7 @@ #include "intel_chipset.h" -#define BRW_IS_G4X(brw) (IS_G4X((brw)->intel.intelScreen->deviceID)) -#define BRW_IS_IGDNG(brw) (IS_IGDNG((brw)->intel.intelScreen->deviceID)) -#define BRW_IS_965(brw) (!(BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw))) -#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965) -#define CMD_VF_STATISTICS(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965) -#define URB_SIZES(brw) (BRW_IS_IGDNG(brw) ? 1024 : \ - (BRW_IS_G4X(brw) ? 384 : 256)) /* 512 bit units */ +#define BRW_IS_965(brw) (!(brw)->intel.is_g4x && \ + !(brw)->intel.is_ironlake) #endif diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 67673e9911..3413c96928 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -452,7 +452,7 @@ static void brw_set_sampler_message(struct brw_context *brw, insn->bits3.sampler_igdng.end_of_thread = eot; insn->bits2.send_igdng.sfid = BRW_MESSAGE_TARGET_SAMPLER; insn->bits2.send_igdng.end_of_thread = eot; - } else if (BRW_IS_G4X(brw)) { + } else if (intel->is_g4x) { insn->bits3.sampler_g4x.binding_table_index = binding_table_index; insn->bits3.sampler_g4x.sampler = sampler; insn->bits3.sampler_g4x.msg_type = msg_type; diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index 562a17844b..fe5c1ae279 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -47,7 +47,6 @@ static GLboolean do_check_fallback(struct brw_context *brw) { - struct intel_context *intel = &brw->intel; GLcontext *ctx = &brw->intel.ctx; GLuint i; @@ -86,8 +85,7 @@ static GLboolean do_check_fallback(struct brw_context *brw) } /* _NEW_BUFFERS */ - if (IS_965(intel->intelScreen->deviceID) && - !IS_G4X(intel->intelScreen->deviceID)) { + if (!brw->has_surface_tile_offset) { for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; struct intel_renderbuffer *irb = intel_renderbuffer(rb); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 6cb2da28e6..fd14eaa612 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -212,7 +212,7 @@ static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; - unsigned int len = (BRW_IS_G4X(brw) || intel->is_ironlake) ? 6 : 5; + unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5; if (region == NULL) { BEGIN_BATCH(len, IGNORE_CLIPRECTS); @@ -223,7 +223,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); - if (BRW_IS_G4X(brw) || intel->is_ironlake) + if (intel->is_g4x || intel->is_ironlake) OUT_BATCH(0); ADVANCE_BATCH(); @@ -262,7 +262,7 @@ static void emit_depthbuffer(struct brw_context *brw) ((region->height - 1) << 19)); OUT_BATCH(0); - if (BRW_IS_G4X(brw) || intel->is_ironlake) + if (intel->is_g4x || intel->is_ironlake) OUT_BATCH(0); ADVANCE_BATCH(); @@ -444,7 +444,7 @@ static void upload_invarient_state( struct brw_context *brw ) struct brw_pipeline_select ps; memset(&ps, 0, sizeof(ps)); - ps.header.opcode = CMD_PIPELINE_SELECT(brw); + ps.header.opcode = brw->CMD_PIPELINE_SELECT; ps.header.pipeline_select = 0; BRW_BATCH_STRUCT(brw, &ps); } @@ -480,7 +480,7 @@ static void upload_invarient_state( struct brw_context *brw ) struct brw_vf_statistics vfs; memset(&vfs, 0, sizeof(vfs)); - vfs.opcode = CMD_VF_STATISTICS(brw); + vfs.opcode = brw->CMD_VF_STATISTICS; if (INTEL_DEBUG & DEBUG_STATS) vfs.statistics_enable = 1; diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index e1e8a90ca7..f2cdb203b8 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -105,7 +105,8 @@ static GLboolean check_urb_layout( struct brw_context *brw ) brw->urb.sf_start = brw->urb.clip_start + brw->urb.nr_clip_entries * brw->urb.vsize; brw->urb.cs_start = brw->urb.sf_start + brw->urb.nr_sf_entries * brw->urb.sfsize; - return brw->urb.cs_start + brw->urb.nr_cs_entries * brw->urb.csize <= URB_SIZES(brw); + return brw->urb.cs_start + brw->urb.nr_cs_entries * + brw->urb.csize <= brw->urb.size; } /* Most minimal update, forces re-emit of URB fence packet after GS @@ -157,7 +158,7 @@ static void recalculate_urb_fence( struct brw_context *brw ) brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries; brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries; } - } else if (BRW_IS_G4X(brw)) { + } else if (intel->is_g4x) { brw->urb.nr_vs_entries = 64; if (check_urb_layout(brw)) { goto done; @@ -201,7 +202,7 @@ done: brw->urb.clip_start, brw->urb.sf_start, brw->urb.cs_start, - URB_SIZES(brw)); + brw->urb.size); brw->state.dirty.brw |= BRW_NEW_URB_FENCE; } @@ -245,7 +246,7 @@ void brw_upload_urb_fence(struct brw_context *brw) uf.bits0.gs_fence = brw->urb.clip_start; uf.bits0.clp_fence = brw->urb.sf_start; uf.bits1.sf_fence = brw->urb.cs_start; - uf.bits1.cs_fence = URB_SIZES(brw); + uf.bits1.cs_fence = brw->urb.size; BRW_BATCH_STRUCT(brw, &uf); } diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index fdc55aa1b2..345ffa7ee1 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -85,7 +85,6 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) struct intel_context *intel = &brw->intel; struct brw_vs_unit_state vs; dri_bo *bo; - int chipset_max_threads; memset(&vs, 0, sizeof(vs)); @@ -136,7 +135,7 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) case 32: break; case 64: - assert(BRW_IS_G4X(brw)); + assert(intel->is_g4x); break; default: assert(0); @@ -146,17 +145,8 @@ vs_unit_create_from_key(struct brw_context *brw, struct brw_vs_unit_key *key) vs.thread4.urb_entry_allocation_size = key->urb_size - 1; - if (intel->is_ironlake) - chipset_max_threads = 72; - else if (BRW_IS_G4X(brw)) - chipset_max_threads = 32; - else - chipset_max_threads = 16; vs.thread4.max_threads = CLAMP(key->nr_urb_entries / 2, - 1, chipset_max_threads) - 1; - - if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) - vs.thread4.max_threads = 0; + 1, brw->vs_max_threads) - 1; /* No samplers for ARB_vp programs: */ diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index bcaa793de1..7811689d6a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1162,7 +1162,6 @@ void emit_fb_write(struct brw_wm_compile *c, { struct brw_compile *p = &c->func; struct brw_context *brw = p->brw; - struct intel_context *intel = &brw->intel; GLuint nr = 2; GLuint channel; @@ -1177,7 +1176,7 @@ void emit_fb_write(struct brw_wm_compile *c, brw_push_insn_state(p); for (channel = 0; channel < 4; channel++) { - if (c->dispatch_width == 16 && (BRW_IS_G4X(brw) || intel->is_ironlake)) { + if (c->dispatch_width == 16 && brw->has_compr4) { /* By setting the high bit of the MRF register number, we indicate * that we want COMPR4 mode - instead of doing the usual destination * + 1 for the second half we get destination + 4. diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index fe795fadf8..d3373ea79e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -49,8 +49,6 @@ struct brw_wm_unit_key { unsigned int curbe_offset; unsigned int urb_size; - unsigned int max_threads; - unsigned int nr_surfaces, sampler_count; GLboolean uses_depth, computes_depth, uses_kill, is_glsl; GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable; @@ -67,18 +65,6 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) memset(key, 0, sizeof(*key)); - if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) - key->max_threads = 1; - else { - /* WM maximum threads is number of EUs times number of threads per EU. */ - if (intel->is_ironlake) - key->max_threads = 12 * 6; - else if (BRW_IS_G4X(brw)) - key->max_threads = 10 * 5; - else - key->max_threads = 8 * 4; - } - /* CACHE_NEW_WM_PROG */ key->total_grf = brw->wm.prog_data->total_grf; key->urb_entry_read_length = brw->wm.prog_data->urb_read_length; @@ -192,7 +178,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key, else wm.wm5.enable_16_pix = 1; - wm.wm5.max_threads = key->max_threads - 1; + wm.wm5.max_threads = brw->wm_max_threads - 1; wm.wm5.thread_dispatch_enable = 1; /* AKA: color_write */ wm.wm5.legacy_line_rast = 0; wm.wm5.legacy_global_depth_bias = 0; @@ -269,7 +255,7 @@ static void upload_wm_unit( struct brw_context *brw ) */ assert(key.total_scratch <= 12 * 1024); if (key.total_scratch) { - GLuint total = key.total_scratch * key.max_threads; + GLuint total = key.total_scratch * brw->wm_max_threads; if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) { dri_bo_unreference(brw->wm.scratch_bo); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 8335e5a650..8810f2a380 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -608,8 +608,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, surf.ss1.base_addr = key.draw_offset - tile_offset; - assert(BRW_IS_G4X(brw) || tile_offset == 0); - if (BRW_IS_G4X(brw)) { + if (brw->has_surface_tile_offset) { if (key.tiling == I915_TILING_X) { /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. @@ -620,6 +619,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, surf.ss5.x_offset = (tile_offset % 128) / key.cpp / 4; surf.ss5.y_offset = tile_offset / 128 / 2; } + } else { + assert(tile_offset == 0); } } if (region_bo != NULL) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 234f99a00e..6f567dc4d0 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -623,6 +623,10 @@ intelInitContext(struct intel_context *intel, if (IS_IGDNG(intel->intelScreen->deviceID)) { intel->is_ironlake = GL_TRUE; intel->needs_ff_sync = GL_TRUE; + intel->has_luminance_srgb = GL_TRUE; + } else if (IS_G4X(intel->intelScreen->deviceID)) { + intel->has_luminance_srgb = GL_TRUE; + intel->is_g4x = GL_TRUE; } /* Dri stuff */ diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index f7d9016d71..e46764e99c 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -178,6 +178,10 @@ struct intel_context int gen; GLboolean needs_ff_sync; GLboolean is_ironlake; + GLboolean is_g4x; + GLboolean has_luminance_srgb; + + int urb_size; struct intel_region *front_region; struct intel_region *back_region; diff --git a/src/mesa/drivers/dri/intel/intel_tex_format.c b/src/mesa/drivers/dri/intel/intel_tex_format.c index 87efb72cc5..a7c6c45ffe 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_format.c +++ b/src/mesa/drivers/dri/intel/intel_tex_format.c @@ -173,13 +173,13 @@ intelChooseTextureFormat(GLcontext * ctx, GLint internalFormat, return MESA_FORMAT_SARGB8; case GL_SLUMINANCE_EXT: case GL_SLUMINANCE8_EXT: - if (IS_G4X(intel->intelScreen->deviceID)) + if (intel->has_luminance_srgb) return MESA_FORMAT_SL8; else return MESA_FORMAT_SARGB8; case GL_SLUMINANCE_ALPHA_EXT: case GL_SLUMINANCE8_ALPHA8_EXT: - if (IS_G4X(intel->intelScreen->deviceID)) + if (intel->has_luminance_srgb) return MESA_FORMAT_SLA8; else return MESA_FORMAT_SARGB8; -- cgit v1.2.3 From cb3810dd19760797e699c47929f655b829c4d339 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 16 Dec 2009 15:42:55 -0800 Subject: intel: Replace IS_965 checks with context structure usage. Saves another 600 bytes or so of code. --- src/mesa/drivers/dri/i965/brw_clip_line.c | 9 +++++---- src/mesa/drivers/dri/i965/brw_clip_tri.c | 3 ++- src/mesa/drivers/dri/i965/brw_context.c | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_defines.h | 3 --- src/mesa/drivers/dri/i965/brw_misc_state.c | 4 ++-- src/mesa/drivers/dri/i965/brw_vs_emit.c | 7 ++++--- src/mesa/drivers/dri/intel/intel_extensions.c | 2 +- 8 files changed, 18 insertions(+), 16 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 59727af88d..afc0b11049 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -127,6 +127,7 @@ static void brw_clip_line_alloc_regs( struct brw_clip_compile *c ) static void clip_and_emit_line( struct brw_clip_compile *c ) { struct brw_compile *p = &c->func; + struct brw_context *brw = p->brw; struct brw_indirect vtx0 = brw_indirect(0, 0); struct brw_indirect vtx1 = brw_indirect(1, 0); struct brw_indirect newvtx0 = brw_indirect(2, 0); @@ -153,7 +154,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_init_clipmask(c); /* -ve rhw workaround */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); @@ -190,7 +191,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) * Both can be negative on GM965/G965 due to RHW workaround * if so, this object should be rejected. */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0)); is_neg2 = brw_IF(p, BRW_EXECUTE_1); { @@ -215,7 +216,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) /* If both are positive, do nothing */ /* Only on GM965/G965 */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0)); is_neg2 = brw_IF(p, BRW_EXECUTE_1); } @@ -230,7 +231,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_set_predicate_control(p, BRW_PREDICATE_NONE); } - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_ENDIF(p, is_neg2); } } diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index ec15e9a697..cfbb8f2686 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -572,6 +572,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) { struct brw_instruction *neg_rhw; struct brw_compile *p = &c->func; + struct brw_context *brw = p->brw; brw_clip_tri_alloc_regs(c, 3 + c->key.nr_userclip + 6); brw_clip_tri_init_vertices(c); brw_clip_init_clipmask(c); @@ -579,7 +580,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) /* if -ve rhw workaround bit is set, do cliptest */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 282566f8d5..d8af2c512b 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -163,11 +163,10 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45; brw->has_surface_tile_offset = GL_TRUE; brw->has_compr4 = GL_TRUE; + brw->has_aa_line_parameters = GL_TRUE; } else { brw->CMD_VF_STATISTICS = CMD_VF_STATISTICS_965; brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965; - brw->has_surface_tile_offset = GL_FALSE; - brw->has_compr4 = GL_FALSE; } /* WM maximum threads is number of EUs times number of threads per EU. */ @@ -183,6 +182,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, brw->urb.size = 256; brw->vs_max_threads = 16; brw->wm_max_threads = 8 * 4; + brw->has_negative_rhw_bug = GL_TRUE; } if (INTEL_DEBUG & DEBUG_SINGLE_THREAD) { diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 4ae48bba05..ea5503e2fe 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -440,6 +440,8 @@ struct brw_context GLboolean emit_state_always; GLboolean has_surface_tile_offset; GLboolean has_compr4; + GLboolean has_negative_rhw_bug; + GLboolean has_aa_line_parameters; ; struct { struct brw_state_flags dirty; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2ee331a200..ea0d7e05d4 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -832,7 +832,4 @@ #include "intel_chipset.h" -#define BRW_IS_965(brw) (!(brw)->intel.is_g4x && \ - !(brw)->intel.is_ironlake) - #endif diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index fd14eaa612..d437b1e030 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -374,8 +374,8 @@ const struct brw_tracked_state brw_polygon_stipple_offset = { static void upload_aa_line_parameters(struct brw_context *brw) { struct brw_aa_line_parameters balp; - - if (BRW_IS_965(brw)) + + if (!brw->has_aa_line_parameters) return; /* use legacy aa line coverage computation */ diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 21d2fec707..1b84dd505f 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1114,7 +1114,8 @@ static void emit_swz( struct brw_vs_compile *c, static void emit_vertex_write( struct brw_vs_compile *c) { struct brw_compile *p = &c->func; - struct intel_context *intel = &p->brw->intel; + struct brw_context *brw = p->brw; + struct intel_context *intel = &brw->intel; struct brw_reg m0 = brw_message_reg(0); struct brw_reg pos = c->regs[PROGRAM_OUTPUT][VERT_RESULT_HPOS]; struct brw_reg ndc; @@ -1138,7 +1139,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * workaround. */ if ((c->prog_data.outputs_written & BITFIELD64_BIT(VERT_RESULT_PSIZ)) || - c->key.nr_userclip || BRW_IS_965(p->brw)) + c->key.nr_userclip || brw->has_negative_rhw_bug) { struct brw_reg header1 = retype(get_tmp(c), BRW_REGISTER_TYPE_UD); GLuint i; @@ -1169,7 +1170,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * Later, clipping will detect ucp[6] and ensure the primitive is * clipped against all fixed planes. */ - if (BRW_IS_965(p->brw)) { + if (brw->has_negative_rhw_bug) { brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_L, diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c b/src/mesa/drivers/dri/intel/intel_extensions.c index 86dc42cc51..bb50531d98 100644 --- a/src/mesa/drivers/dri/intel/intel_extensions.c +++ b/src/mesa/drivers/dri/intel/intel_extensions.c @@ -196,7 +196,7 @@ intelInitExtensions(GLcontext *ctx) */ driInitExtensions(ctx, card_extensions, GL_FALSE); - if (IS_965(intel->intelScreen->deviceID)) + if (intel->gen >= 4) driInitExtensions(ctx, brw_extensions, GL_FALSE); if (IS_915(intel->intelScreen->deviceID) -- cgit v1.2.3 From f5ad1d0d02cae06bff3ee120c75ad4ab458d2c7d Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Thu, 24 Dec 2009 16:26:09 -0800 Subject: i965: Add missing va_end. --- src/mesa/drivers/dri/i965/brw_disasm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 9fef230507..130bd0f3e5 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -365,6 +365,7 @@ static int format (FILE *f, char *format, ...) va_start (args, format); vsnprintf (buf, sizeof (buf) - 1, format, args); + va_end (args); string (f, buf); return 0; } -- cgit v1.2.3 From 2447786ed00a19466c9cc9b9efbfa084e88114eb Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Thu, 24 Dec 2009 22:58:05 -0800 Subject: i965: Fix assert. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 241cdc33f8..b346277f17 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -852,7 +852,7 @@ void brw_land_fwd_jump(struct brw_compile *p, jmpi = 2; assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI); - assert(jmp_insn->bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE); + assert(jmp_insn->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE); jmp_insn->bits3.ud = jmpi * ((landing - jmp_insn) - 1); } -- cgit v1.2.3 From 070bbd4fcd5d2b669b880b91730a7ad9d130e416 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 22 Dec 2009 17:05:10 -0800 Subject: i965: Fix setup of immediate types for gen4 disasm. Caught by clang. --- src/mesa/drivers/dri/i965/brw_disasm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 9fef230507..47629dfa3d 100644 --- a/src/mesa/drivers/dri/i965/brw_disasm.c +++ b/src/mesa/drivers/dri/i965/brw_disasm.c @@ -239,7 +239,7 @@ char *imm_encoding[8] = { [2] = "UW", [3] = "W", [5] = "VF", - [5] = "V", + [6] = "V", [7] = "F" }; -- cgit v1.2.3 From c196a3592a73bfe11db5100a9ba1aff07fb8a60e Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 22 Dec 2009 17:18:03 -0800 Subject: i965: Clean up double initialization of dst_flags from a rebase resolve. Caught by clang. --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index f294387c80..43646528f5 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -1877,10 +1877,6 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) else brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE); - dst_flags = inst->DstReg.WriteMask; - if (inst->SaturateMode == SATURATE_ZERO_ONE) - dst_flags |= SATURATE; - switch (inst->Opcode) { case WM_PIXELXY: emit_pixel_xy(c, dst, dst_flags); -- cgit v1.2.3 From c4ac1f8299ddc3b60f7f32c58c0310deacac22c6 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 22 Dec 2009 17:30:13 -0800 Subject: i965: Extra asserts on flow control instructions to clarify for clang. --- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index 43646528f5..eccbfd5fa3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -2040,6 +2040,7 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) if_inst[if_depth++] = brw_IF(p, BRW_EXECUTE_8); break; case OPCODE_ELSE: + assert(if_depth > 0); if_inst[if_depth-1] = brw_ELSE(p, if_inst[if_depth-1]); break; case OPCODE_ENDIF: @@ -2095,7 +2096,8 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c) if (intel->is_ironlake) br = 2; - + + assert(loop_depth > 0); loop_depth--; inst0 = inst1 = brw_WHILE(p, loop_inst[loop_depth]); /* patch all the BREAK/CONT instructions from last BGNLOOP */ -- cgit v1.2.3 From c67bb15d4e3da430d511444bd7d159ccb0c84b73 Mon Sep 17 00:00:00 2001 From: Vinson Lee Date: Mon, 28 Dec 2009 18:46:15 -0800 Subject: intel: Silence compiler warnings. --- src/mesa/drivers/dri/i915/intel_render.c | 4 ++-- src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 ++++-- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/brw_wm_emit.c | 2 +- src/mesa/drivers/dri/i965/brw_wm_glsl.c | 2 +- src/mesa/drivers/dri/intel/intel_context.h | 8 ++++---- src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 2 +- src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +- 9 files changed, 16 insertions(+), 14 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c index 410052b3c2..ec209391ab 100644 --- a/src/mesa/drivers/dri/i915/intel_render.c +++ b/src/mesa/drivers/dri/i915/intel_render.c @@ -117,7 +117,7 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim) intel_set_prim(intel, hw_prim[prim]); } -static inline GLuint intel_get_vb_max(struct intel_context *intel) +static INLINE GLuint intel_get_vb_max(struct intel_context *intel) { GLuint ret; @@ -129,7 +129,7 @@ static inline GLuint intel_get_vb_max(struct intel_context *intel) return ret; } -static inline GLuint intel_get_current_max(struct intel_context *intel) +static INLINE GLuint intel_get_current_max(struct intel_context *intel) { if (intel->intelScreen->no_vbo) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 271a88dae0..c66f43abae 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -249,8 +249,10 @@ static void wrap_buffers( struct brw_context *brw, */ /* DON'T DO THIS AS IF WE HAVE TO RE-ORG MEMORY WE NEED SOMEWHERE WITH FAKE TO PUSH THIS STUFF */ -// if (!brw->intel.ttm) -// dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL); + /* + if (!brw->intel.ttm) + dri_bo_fake_disable_backing_store(brw->vb.upload.bo, NULL, NULL); + */ } static void get_space( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 7a4c046a49..c8fb0a288f 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -199,7 +199,7 @@ void brw_set_src1( struct brw_instruction *insn, * in the future: */ assert (reg.address_mode == BRW_ADDRESS_DIRECT); - //assert (reg.file == BRW_GENERAL_REGISTER_FILE); + /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */ if (insn->header.access_mode == BRW_ALIGN_1) { insn->bits3.da1.src1_subreg_nr = reg.subnr; diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index b129b1f1c3..14d5319796 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -35,7 +35,7 @@ #include "brw_context.h" -static inline void +static INLINE void brw_add_validated_bo(struct brw_context *brw, dri_bo *bo) { assert(brw->state.validated_bo_count < ARRAY_SIZE(brw->state.validated_bos)); diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 5390fd2584..66fb611d50 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1084,7 +1084,7 @@ static void emit_kil_nv( struct brw_wm_compile *c ) brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK + brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */ brw_AND(p, r0uw, c->emit_mask_reg, r0uw); brw_pop_insn_state(p); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_glsl.c b/src/mesa/drivers/dri/i965/brw_wm_glsl.c index e8c2cb66ec..7e5533e258 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_glsl.c +++ b/src/mesa/drivers/dri/i965/brw_wm_glsl.c @@ -743,7 +743,7 @@ static void emit_kil(struct brw_wm_compile *c) struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); brw_push_insn_state(p); brw_set_mask_control(p, BRW_MASK_DISABLE); - brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK + brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); /* IMASK */ brw_AND(p, depth, c->emit_mask_reg, depth); brw_pop_insn_state(p); } diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index eb7be7ddd0..1afec09a34 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -354,14 +354,14 @@ extern char *__progname; #define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) #define IS_POWER_OF_TWO(val) (((val) & (val - 1)) == 0) -static inline uint32_t +static INLINE uint32_t U_FIXED(float value, uint32_t frac_bits) { value *= (1 << frac_bits); return value < 0 ? 0 : value; } -static inline uint32_t +static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) { return value * (1 << frac_bits); @@ -588,7 +588,7 @@ is_power_of_two(uint32_t value) return (value & (value - 1)) == 0; } -static inline void +static INLINE void intel_bo_map_gtt_preferred(struct intel_context *intel, drm_intel_bo *bo, GLboolean write) @@ -599,7 +599,7 @@ intel_bo_map_gtt_preferred(struct intel_context *intel, drm_intel_bo_map(bo, write); } -static inline void +static INLINE void intel_bo_unmap_gtt_preferred(struct intel_context *intel, drm_intel_bo *bo) { diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index 9545ef4b49..19ca515242 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -166,7 +166,7 @@ static GLuint get_bitmap_rect(GLsizei width, GLsizei height, * Returns the low Y value of the vertical range given, flipped according to * whether the framebuffer is or not. */ -static inline int +static INLINE int y_flip(struct gl_framebuffer *fb, int y, int height) { if (fb->Name != 0) diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index 767d04d2f4..ee953cfbe7 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -109,7 +109,7 @@ do_copy_texsubimage(struct intel_context *intel, return GL_FALSE; } - // intelFlush(ctx); + /* intelFlush(ctx); */ LOCK_HARDWARE(intel); { drm_intel_bo *dst_bo = intel_region_buffer(intel, -- cgit v1.2.3 From fd5511d27fc44096117c47ab503fb5b47f993061 Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Tue, 29 Dec 2009 16:17:14 -0700 Subject: mesa: implement per-buffer color masking This is part of the GL_EXT_draw_buffers2 extension and part of GL 3.0. The ctx->Color.ColorMask field is now a 2-D array. Until drivers are modified to support per-buffer color masking, they can just look at the 0th color mask. The new _mesa_ColorMaskIndexed() function will be called by glColorMaskIndexedEXT() or glColorMaski(). --- src/mesa/drivers/common/driverfuncs.c | 22 ++++++-- src/mesa/drivers/common/meta.c | 32 ++++++++--- src/mesa/drivers/directfb/idirectfbgl_mesa.c | 8 +-- src/mesa/drivers/dri/gamma/gamma_state.c | 8 +-- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/drivers/dri/intel/intel_clear.c | 2 +- src/mesa/drivers/dri/intel/intel_pixel.c | 8 +-- src/mesa/drivers/dri/intel/intel_pixel_copy.c | 8 +-- src/mesa/drivers/dri/mach64/mach64_state.c | 8 +-- src/mesa/drivers/dri/mga/mgapixel.c | 24 ++++---- src/mesa/drivers/dri/mga/mgastate.c | 10 ++-- src/mesa/drivers/dri/r128/r128_state.c | 8 +-- src/mesa/drivers/dri/r200/r200_pixel.c | 16 +++--- src/mesa/drivers/dri/r200/r200_state.c | 8 +-- src/mesa/drivers/dri/r300/r300_state.c | 7 ++- src/mesa/drivers/dri/r600/r700_clear.c | 2 +- src/mesa/drivers/dri/r600/r700_state.c | 8 +-- src/mesa/drivers/dri/radeon/radeon_state.c | 8 +-- src/mesa/drivers/dri/savage/savageioctl.c | 14 ++--- src/mesa/drivers/dri/tdfx/tdfx_pixels.c | 8 +-- src/mesa/drivers/dri/tdfx/tdfx_render.c | 6 +- src/mesa/drivers/dri/unichrome/via_state.c | 10 ++-- src/mesa/drivers/windows/gdi/wmesa.c | 8 +-- .../drivers/windows/gldirect/dx7/gld_driver_dx7.c | 10 ++-- .../drivers/windows/gldirect/dx8/gld_driver_dx8.c | 10 ++-- .../drivers/windows/gldirect/dx9/gld_driver_dx9.c | 10 ++-- src/mesa/drivers/x11/xm_dd.c | 2 +- src/mesa/main/attrib.c | 20 +++++-- src/mesa/main/blend.c | 59 +++++++++++++++++--- src/mesa/main/blend.h | 4 ++ src/mesa/main/dd.h | 2 + src/mesa/main/get.c | 65 +++++++++++++++------- src/mesa/main/get_gen.py | 17 ++++-- src/mesa/main/mtypes.h | 2 +- src/mesa/state_tracker/st_atom_blend.c | 8 +-- src/mesa/state_tracker/st_cb_accum.c | 2 +- src/mesa/state_tracker/st_cb_clear.c | 16 +++--- src/mesa/swrast/s_accum.c | 2 +- src/mesa/swrast/s_clear.c | 50 ++++++----------- src/mesa/swrast/s_context.c | 28 ++++++++-- src/mesa/swrast/s_masking.c | 20 +++---- src/mesa/swrast/s_masking.h | 2 +- src/mesa/swrast/s_span.c | 8 +-- src/mesa/swrast/s_triangle.c | 8 +-- 44 files changed, 350 insertions(+), 230 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/common/driverfuncs.c b/src/mesa/drivers/common/driverfuncs.c index 9b271f85e9..5c5e17820d 100644 --- a/src/mesa/drivers/common/driverfuncs.c +++ b/src/mesa/drivers/common/driverfuncs.c @@ -264,11 +264,23 @@ _mesa_init_driver_state(GLcontext *ctx) ctx->Color.BlendDstRGB, ctx->Color.BlendSrcA, ctx->Color.BlendDstA); - ctx->Driver.ColorMask(ctx, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); + if (ctx->Driver.ColorMaskIndexed) { + GLuint i; + for (i = 0; i < ctx->Const.MaxDrawBuffers; i++) { + ctx->Driver.ColorMaskIndexed(ctx, i, + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP]); + } + } + else { + ctx->Driver.ColorMask(ctx, + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP]); + } ctx->Driver.CullFace(ctx, ctx->Polygon.CullFaceMode); ctx->Driver.DepthFunc(ctx, ctx->Depth.Func); diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index da2c06677a..0676173745 100644 --- a/src/mesa/drivers/common/meta.c +++ b/src/mesa/drivers/common/meta.c @@ -111,7 +111,7 @@ struct save_state GLboolean ColorLogicOpEnabled; /** META_COLOR_MASK */ - GLubyte ColorMask[4]; + GLubyte ColorMask[MAX_DRAW_BUFFERS][4]; /** META_DEPTH_TEST */ struct gl_depthbuffer_attrib Depth; @@ -347,11 +347,12 @@ _mesa_meta_begin(GLcontext *ctx, GLbitfield state) } if (state & META_COLOR_MASK) { - COPY_4V(save->ColorMask, ctx->Color.ColorMask); - if (!ctx->Color.ColorMask[0] || - !ctx->Color.ColorMask[1] || - !ctx->Color.ColorMask[2] || - !ctx->Color.ColorMask[3]) + memcpy(save->ColorMask, ctx->Color.ColorMask, + sizeof(ctx->Color.ColorMask)); + if (!ctx->Color.ColorMask[0][0] || + !ctx->Color.ColorMask[0][1] || + !ctx->Color.ColorMask[0][2] || + !ctx->Color.ColorMask[0][3]) _mesa_ColorMask(GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE); } @@ -581,9 +582,22 @@ _mesa_meta_end(GLcontext *ctx) } if (state & META_COLOR_MASK) { - if (!TEST_EQ_4V(ctx->Color.ColorMask, save->ColorMask)) - _mesa_ColorMask(save->ColorMask[0], save->ColorMask[1], - save->ColorMask[2], save->ColorMask[3]); + GLuint i; + for (i = 0; i < ctx->Const.MaxDrawBuffers; i++) { + if (!TEST_EQ_4V(ctx->Color.ColorMask[i], save->ColorMask[i])) { + if (i == 0) { + _mesa_ColorMask(save->ColorMask[i][0], save->ColorMask[i][1], + save->ColorMask[i][2], save->ColorMask[i][3]); + } + else { + _mesa_ColorMaskIndexed(i, + save->ColorMask[i][0], + save->ColorMask[i][1], + save->ColorMask[i][2], + save->ColorMask[i][3]); + } + } + } } if (state & META_DEPTH_TEST) { diff --git a/src/mesa/drivers/directfb/idirectfbgl_mesa.c b/src/mesa/drivers/directfb/idirectfbgl_mesa.c index 93593403c1..62a3269d17 100644 --- a/src/mesa/drivers/directfb/idirectfbgl_mesa.c +++ b/src/mesa/drivers/directfb/idirectfbgl_mesa.c @@ -407,10 +407,10 @@ dfbClear( GLcontext *ctx, GLbitfield mask ) #define BUFFER_BIT_MASK (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT | \ BUFFER_BIT_BACK_LEFT | BUFFER_BIT_BACK_RIGHT ) if (mask & BUFFER_BIT_MASK && - ctx->Color.ColorMask[0] && - ctx->Color.ColorMask[1] && - ctx->Color.ColorMask[2] && - ctx->Color.ColorMask[3]) + ctx->Color.ColorMask[0][0] && + ctx->Color.ColorMask[0][1] && + ctx->Color.ColorMask[0][2] && + ctx->Color.ColorMask[0][3]) { DFBRegion clip; GLubyte a, r, g, b; diff --git a/src/mesa/drivers/dri/gamma/gamma_state.c b/src/mesa/drivers/dri/gamma/gamma_state.c index 59272f9bc9..bdd1c86ab7 100644 --- a/src/mesa/drivers/dri/gamma/gamma_state.c +++ b/src/mesa/drivers/dri/gamma/gamma_state.c @@ -813,10 +813,10 @@ static void gammaUpdateMasks( GLcontext *ctx ) GLuint mask = gammaPackColor( gmesa->gammaScreen->cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP] ); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP] ); if (gmesa->gammaScreen->cpp == 2) mask |= mask << 16; diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 8810f2a380..7aca3aac8e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -575,7 +575,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.draw_offset = 0; } /* _NEW_COLOR */ - memcpy(key.color_mask, ctx->Color.ColorMask, + memcpy(key.color_mask, ctx->Color.ColorMask[0], sizeof(key.color_mask)); /* As mentioned above, disable writes to the alpha component when the diff --git a/src/mesa/drivers/dri/intel/intel_clear.c b/src/mesa/drivers/dri/intel/intel_clear.c index f682ee3de5..956f2339ff 100644 --- a/src/mesa/drivers/dri/intel/intel_clear.c +++ b/src/mesa/drivers/dri/intel/intel_clear.c @@ -68,7 +68,7 @@ static void intelClear(GLcontext *ctx, GLbitfield mask) { struct intel_context *intel = intel_context(ctx); - const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask); + const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask[0]); GLbitfield tri_mask = 0; GLbitfield blit_mask = 0; GLbitfield swrast_mask = 0; diff --git a/src/mesa/drivers/dri/intel/intel_pixel.c b/src/mesa/drivers/dri/intel/intel_pixel.c index 993e427a99..5142f3dcd9 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel.c +++ b/src/mesa/drivers/dri/intel/intel_pixel.c @@ -88,10 +88,10 @@ intel_check_blit_fragment_ops(GLcontext * ctx, GLboolean src_alpha_is_one) return GL_FALSE; } - if (!(ctx->Color.ColorMask[0] && - ctx->Color.ColorMask[1] && - ctx->Color.ColorMask[2] && - ctx->Color.ColorMask[3])) { + if (!(ctx->Color.ColorMask[0][0] && + ctx->Color.ColorMask[0][1] && + ctx->Color.ColorMask[0][2] && + ctx->Color.ColorMask[0][3])) { DBG("fallback due to color masking\n"); return GL_FALSE; } diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c index 622aaa22d6..689a00cb00 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c @@ -83,10 +83,10 @@ intel_check_copypixel_blit_fragment_ops(GLcontext * ctx) ctx->Depth.Test || ctx->Fog.Enabled || ctx->Stencil._Enabled || - !ctx->Color.ColorMask[0] || - !ctx->Color.ColorMask[1] || - !ctx->Color.ColorMask[2] || - !ctx->Color.ColorMask[3] || + !ctx->Color.ColorMask[0][0] || + !ctx->Color.ColorMask[0][1] || + !ctx->Color.ColorMask[0][2] || + !ctx->Color.ColorMask[0][3] || ctx->Texture._EnabledUnits || ctx->FragmentProgram._Enabled || ctx->Color.BlendEnabled); diff --git a/src/mesa/drivers/dri/mach64/mach64_state.c b/src/mesa/drivers/dri/mach64/mach64_state.c index 3a023187ce..902905de71 100644 --- a/src/mesa/drivers/dri/mach64/mach64_state.c +++ b/src/mesa/drivers/dri/mach64/mach64_state.c @@ -527,10 +527,10 @@ static void mach64UpdateMasks( GLcontext *ctx ) /* mach64 can't color mask with alpha blending enabled */ if ( !ctx->Color.BlendEnabled ) { mask = mach64PackColor( mmesa->mach64Screen->cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP] ); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP] ); } if ( mmesa->setup.dp_write_mask != mask ) { diff --git a/src/mesa/drivers/dri/mga/mgapixel.c b/src/mesa/drivers/dri/mga/mgapixel.c index 977dfa0b76..05b30ba61e 100644 --- a/src/mesa/drivers/dri/mga/mgapixel.c +++ b/src/mesa/drivers/dri/mga/mgapixel.c @@ -134,10 +134,10 @@ check_color_per_fragment_ops( const GLcontext *ctx ) ctx->Fog.Enabled || ctx->Scissor.Enabled || ctx->Stencil._Enabled || - !ctx->Color.ColorMask[0] || - !ctx->Color.ColorMask[1] || - !ctx->Color.ColorMask[2] || - !ctx->Color.ColorMask[3] || + !ctx->Color.ColorMask[0][0] || + !ctx->Color.ColorMask[0][1] || + !ctx->Color.ColorMask[0][2] || + !ctx->Color.ColorMask[0][3] || ctx->Color.ColorLogicOpEnabled || ctx->Texture._EnabledUnits ) && @@ -150,10 +150,10 @@ static GLboolean check_depth_per_fragment_ops( const GLcontext *ctx ) { return ( ctx->Current.RasterPosValid && - ctx->Color.ColorMask[RCOMP] == 0 && - ctx->Color.ColorMask[BCOMP] == 0 && - ctx->Color.ColorMask[GCOMP] == 0 && - ctx->Color.ColorMask[ACOMP] == 0 && + ctx->Color.ColorMask[0][RCOMP] == 0 && + ctx->Color.ColorMask[0][BCOMP] == 0 && + ctx->Color.ColorMask[0][GCOMP] == 0 && + ctx->Color.ColorMask[0][ACOMP] == 0 && ctx->Pixel.ZoomX == 1.0F && ( ctx->Pixel.ZoomY == 1.0F || ctx->Pixel.ZoomY == -1.0F ) ); } @@ -525,10 +525,10 @@ mgaTryDrawPixels( GLcontext *ctx, mmesa->mgaScreen->backOffset); planemask = mgaPackColor(cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP]); if (cpp == 2) planemask |= planemask << 16; diff --git a/src/mesa/drivers/dri/mga/mgastate.c b/src/mesa/drivers/dri/mga/mgastate.c index 7c830ec097..1e51057534 100644 --- a/src/mesa/drivers/dri/mga/mgastate.c +++ b/src/mesa/drivers/dri/mga/mgastate.c @@ -374,13 +374,11 @@ static void mgaDDColorMask(GLcontext *ctx, { mgaContextPtr mmesa = MGA_CONTEXT( ctx ); mgaScreenPrivate *mgaScreen = mmesa->mgaScreen; - - GLuint mask = mgaPackColor(mgaScreen->cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP]); if (mgaScreen->cpp == 2) mask = mask | (mask << 16); diff --git a/src/mesa/drivers/dri/r128/r128_state.c b/src/mesa/drivers/dri/r128/r128_state.c index 4ae7bf5b97..ac175d59ec 100644 --- a/src/mesa/drivers/dri/r128/r128_state.c +++ b/src/mesa/drivers/dri/r128/r128_state.c @@ -702,10 +702,10 @@ static void r128UpdateMasks( GLcontext *ctx ) r128ContextPtr rmesa = R128_CONTEXT(ctx); GLuint mask = r128PackColor( rmesa->r128Screen->cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP] ); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP] ); if ( rmesa->setup.plane_3d_mask_c != mask ) { rmesa->setup.plane_3d_mask_c = mask; diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 95773871e0..94e43c7d66 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -88,10 +88,10 @@ check_color_per_fragment_ops( const GLcontext *ctx ) ctx->Fog.Enabled || ctx->Scissor.Enabled || ctx->Stencil._Enabled || - !ctx->Color.ColorMask[0] || - !ctx->Color.ColorMask[1] || - !ctx->Color.ColorMask[2] || - !ctx->Color.ColorMask[3] || + !ctx->Color.ColorMask[0][0] || + !ctx->Color.ColorMask[0][1] || + !ctx->Color.ColorMask[0][2] || + !ctx->Color.ColorMask[0][3] || ctx->Color.ColorLogicOpEnabled || ctx->Texture._EnabledUnits ) && @@ -400,10 +400,10 @@ r200TryDrawPixels( GLcontext *ctx, case GL_RGBA: case GL_BGRA: planemask = radeonPackColor(cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP]); if (cpp == 2) planemask |= planemask << 16; diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 6d99c039de..529cb62264 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -721,10 +721,10 @@ static void r200ColorMask( GLcontext *ctx, if (!rrb) return; mask = radeonPackColor( rrb->cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP] ); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP] ); if (!(r && g && b && a)) diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index 23f81fe790..f90bfd4f4f 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -1768,9 +1768,10 @@ static void r300ResetHwState(r300ContextPtr r300) radeon_firevertices(&r300->radeon); r300ColorMask(ctx, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], ctx->Color.ColorMask[ACOMP]); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP]); r300Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); r300DepthMask(ctx, ctx->Depth.Mask); diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index 526d3843d1..c0ac54a844 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -50,7 +50,7 @@ void r700Clear(GLcontext * ctx, GLbitfield mask) { context_t *context = R700_CONTEXT(ctx); __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon); - const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask); + const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask[0]); GLbitfield swrast_mask = 0, tri_mask = 0; int i; struct gl_framebuffer *fb = ctx->DrawBuffer; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index 16b05d5cd9..fc6fb29fd6 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -1724,10 +1724,10 @@ void r700InitState(GLcontext * ctx) //------------------- r700InitSQConfig(ctx); r700ColorMask(ctx, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP]); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP]); r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); r700DepthMask(ctx, ctx->Depth.Mask); diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index f6c733ab20..1fcb545204 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -521,10 +521,10 @@ static void radeonColorMask( GLcontext *ctx, return; mask = radeonPackColor( rrb->cpp, - ctx->Color.ColorMask[RCOMP], - ctx->Color.ColorMask[GCOMP], - ctx->Color.ColorMask[BCOMP], - ctx->Color.ColorMask[ACOMP] ); + ctx->Color.ColorMask[0][RCOMP], + ctx->Color.ColorMask[0][GCOMP], + ctx->Color.ColorMask[0][BCOMP], + ctx->Color.ColorMask[0][ACOMP] ); if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) { RADEON_STATECHANGE( rmesa, msk ); diff --git a/src/mesa/drivers/dri/savage/savageioctl.c b/src/mesa/drivers/dri/savage/savageioctl.c index 77ab8d16e0..706fc97935 100644 --- a/src/mesa/drivers/dri/savage/savageioctl.c +++ b/src/mesa/drivers/dri/savage/savageioctl.c @@ -360,15 +360,15 @@ static void savageDDClear( GLcontext *ctx, GLbitfield mask ) depthMask = 0; switch (imesa->savageScreen->cpp) { case 2: - colorMask = PACK_COLOR_565(ctx->Color.ColorMask[0], - ctx->Color.ColorMask[1], - ctx->Color.ColorMask[2]); + colorMask = PACK_COLOR_565(ctx->Color.ColorMask[0][0], + ctx->Color.ColorMask[0][1], + ctx->Color.ColorMask[0][2]); break; case 4: - colorMask = PACK_COLOR_8888(ctx->Color.ColorMask[3], - ctx->Color.ColorMask[2], - ctx->Color.ColorMask[1], - ctx->Color.ColorMask[0]); + colorMask = PACK_COLOR_8888(ctx->Color.ColorMask[0][3], + ctx->Color.ColorMask[0][2], + ctx->Color.ColorMask[0][1], + ctx->Color.ColorMask[0][0]); break; } diff --git a/src/mesa/drivers/dri/tdfx/tdfx_pixels.c b/src/mesa/drivers/dri/tdfx/tdfx_pixels.c index 18729d5ae0..a3b1775e90 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_pixels.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_pixels.c @@ -611,10 +611,10 @@ tdfx_drawpixels_R8G8B8A8(GLcontext * ctx, GLint x, GLint y, ctx->Fog.Enabled || ctx->Scissor.Enabled || ctx->Stencil._Enabled || - !ctx->Color.ColorMask[0] || - !ctx->Color.ColorMask[1] || - !ctx->Color.ColorMask[2] || - !ctx->Color.ColorMask[3] || + !ctx->Color.ColorMask[0][0] || + !ctx->Color.ColorMask[0][1] || + !ctx->Color.ColorMask[0][2] || + !ctx->Color.ColorMask[0][3] || ctx->Color.ColorLogicOpEnabled || ctx->Texture._EnabledUnits || fxMesa->Fallback) diff --git a/src/mesa/drivers/dri/tdfx/tdfx_render.c b/src/mesa/drivers/dri/tdfx/tdfx_render.c index 2cd8e12d95..79d63f72ac 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_render.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_render.c @@ -76,8 +76,8 @@ static void tdfxClear( GLcontext *ctx, GLbitfield mask ) if (fxMesa->glCtx->Visual.redBits != 8) { /* can only do color masking if running in 24/32bpp on Napalm */ - if (ctx->Color.ColorMask[RCOMP] != ctx->Color.ColorMask[GCOMP] || - ctx->Color.ColorMask[GCOMP] != ctx->Color.ColorMask[BCOMP]) { + if (ctx->Color.ColorMask[0][RCOMP] != ctx->Color.ColorMask[0][GCOMP] || + ctx->Color.ColorMask[0][GCOMP] != ctx->Color.ColorMask[0][BCOMP]) { softwareMask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT)); mask &= ~(BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT); } @@ -721,7 +721,7 @@ void tdfxEmitHwStateLocked( tdfxContextPtr fxMesa ) fxMesa->Glide.grColorMask( fxMesa->Color.ColorMask[RCOMP] || fxMesa->Color.ColorMask[GCOMP] || fxMesa->Color.ColorMask[BCOMP], - /*fxMesa->Color.ColorMask[ACOMP]*/GL_FALSE/*[dBorca] no-no*/ ); + /*fxMesa->Color.ColorMask[0][ACOMP]*/GL_FALSE/*[dBorca] no-no*/ ); } fxMesa->dirty &= ~TDFX_UPLOAD_COLOR_MASK; } diff --git a/src/mesa/drivers/dri/unichrome/via_state.c b/src/mesa/drivers/dri/unichrome/via_state.c index 840e4e42da..a9db6c45f7 100644 --- a/src/mesa/drivers/dri/unichrome/via_state.c +++ b/src/mesa/drivers/dri/unichrome/via_state.c @@ -1238,12 +1238,12 @@ static void viaChooseColorState(GLcontext *ctx) else vmesa->regHROP = HC_HROP_P; - vmesa->regHFBBMSKL = PACK_COLOR_888(ctx->Color.ColorMask[0], - ctx->Color.ColorMask[1], - ctx->Color.ColorMask[2]); - vmesa->regHROP |= ctx->Color.ColorMask[3]; + vmesa->regHFBBMSKL = PACK_COLOR_888(ctx->Color.ColorMask[0][0], + ctx->Color.ColorMask[0][1], + ctx->Color.ColorMask[0][2]); + vmesa->regHROP |= ctx->Color.ColorMask[0][3]; - if (ctx->Color.ColorMask[3]) + if (ctx->Color.ColorMask[0][3]) vmesa->regEnable |= HC_HenAW_MASK; else vmesa->regEnable &= ~HC_HenAW_MASK; diff --git a/src/mesa/drivers/windows/gdi/wmesa.c b/src/mesa/drivers/windows/gdi/wmesa.c index 8929b22af1..76c825a090 100644 --- a/src/mesa/drivers/windows/gdi/wmesa.c +++ b/src/mesa/drivers/windows/gdi/wmesa.c @@ -301,10 +301,10 @@ static void clear(GLcontext *ctx, GLbitfield mask) /* Let swrast do all the work if the masks are not set to * clear all channels. */ - if (ctx->Color.ColorMask[0] != 0xff || - ctx->Color.ColorMask[1] != 0xff || - ctx->Color.ColorMask[2] != 0xff || - ctx->Color.ColorMask[3] != 0xff) { + if (!ctx->Color.ColorMask[0][0] || + !ctx->Color.ColorMask[0][1] || + !ctx->Color.ColorMask[0][2] || + !ctx->Color.ColorMask[0][3]) { _swrast_Clear(ctx, mask); return; } diff --git a/src/mesa/drivers/windows/gldirect/dx7/gld_driver_dx7.c b/src/mesa/drivers/windows/gldirect/dx7/gld_driver_dx7.c index d5fa642800..7b202dfda7 100644 --- a/src/mesa/drivers/windows/gldirect/dx7/gld_driver_dx7.c +++ b/src/mesa/drivers/windows/gldirect/dx7/gld_driver_dx7.c @@ -269,7 +269,7 @@ void gld_Clear_DX7( D3DRECT d3dClearRect; // TODO: Colourmask - const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask; + const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask[0]; if (!gld->pDev) return; @@ -427,10 +427,10 @@ void gld_NEW_COLOR( /* // Color mask - unsupported by DX7 - if (ctx->Color.ColorMask[0]) dwFlags |= D3DCOLORWRITEENABLE_RED; - if (ctx->Color.ColorMask[1]) dwFlags |= D3DCOLORWRITEENABLE_GREEN; - if (ctx->Color.ColorMask[2]) dwFlags |= D3DCOLORWRITEENABLE_BLUE; - if (ctx->Color.ColorMask[3]) dwFlags |= D3DCOLORWRITEENABLE_ALPHA; + if (ctx->Color.ColorMask[0][0]) dwFlags |= D3DCOLORWRITEENABLE_RED; + if (ctx->Color.ColorMask[0][1]) dwFlags |= D3DCOLORWRITEENABLE_GREEN; + if (ctx->Color.ColorMask[0][2]) dwFlags |= D3DCOLORWRITEENABLE_BLUE; + if (ctx->Color.ColorMask[0][3]) dwFlags |= D3DCOLORWRITEENABLE_ALPHA; _GLD_DX7_DEV(SetRenderState(gld->pDev, D3DRENDERSTATE_COLORWRITEENABLE, dwFlags)); */ } diff --git a/src/mesa/drivers/windows/gldirect/dx8/gld_driver_dx8.c b/src/mesa/drivers/windows/gldirect/dx8/gld_driver_dx8.c index 7afa9190cd..7eeb9db2d1 100644 --- a/src/mesa/drivers/windows/gldirect/dx8/gld_driver_dx8.c +++ b/src/mesa/drivers/windows/gldirect/dx8/gld_driver_dx8.c @@ -269,7 +269,7 @@ void gld_Clear_DX8( D3DRECT d3dClearRect; // TODO: Colourmask - const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask; + const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask[0]; if (!gld->pDev) return; @@ -426,10 +426,10 @@ void gld_NEW_COLOR( _GLD_DX8_DEV(SetRenderState(gld->pDev, D3DRS_DESTBLEND, dest)); // Color mask - if (ctx->Color.ColorMask[0]) dwFlags |= D3DCOLORWRITEENABLE_RED; - if (ctx->Color.ColorMask[1]) dwFlags |= D3DCOLORWRITEENABLE_GREEN; - if (ctx->Color.ColorMask[2]) dwFlags |= D3DCOLORWRITEENABLE_BLUE; - if (ctx->Color.ColorMask[3]) dwFlags |= D3DCOLORWRITEENABLE_ALPHA; + if (ctx->Color.ColorMask[0][0]) dwFlags |= D3DCOLORWRITEENABLE_RED; + if (ctx->Color.ColorMask[0][1]) dwFlags |= D3DCOLORWRITEENABLE_GREEN; + if (ctx->Color.ColorMask[0][2]) dwFlags |= D3DCOLORWRITEENABLE_BLUE; + if (ctx->Color.ColorMask[0][3]) dwFlags |= D3DCOLORWRITEENABLE_ALPHA; _GLD_DX8_DEV(SetRenderState(gld->pDev, D3DRS_COLORWRITEENABLE, dwFlags)); } diff --git a/src/mesa/drivers/windows/gldirect/dx9/gld_driver_dx9.c b/src/mesa/drivers/windows/gldirect/dx9/gld_driver_dx9.c index c191564d6e..0558462dea 100644 --- a/src/mesa/drivers/windows/gldirect/dx9/gld_driver_dx9.c +++ b/src/mesa/drivers/windows/gldirect/dx9/gld_driver_dx9.c @@ -269,7 +269,7 @@ void gld_Clear_DX9( D3DRECT d3dClearRect; // TODO: Colourmask - const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask; + const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask[0]; if (!gld->pDev) return; @@ -424,10 +424,10 @@ void gld_NEW_COLOR( _GLD_DX9_DEV(SetRenderState(gld->pDev, D3DRS_DESTBLEND, dest)); // Color mask - if (ctx->Color.ColorMask[0]) dwFlags |= D3DCOLORWRITEENABLE_RED; - if (ctx->Color.ColorMask[1]) dwFlags |= D3DCOLORWRITEENABLE_GREEN; - if (ctx->Color.ColorMask[2]) dwFlags |= D3DCOLORWRITEENABLE_BLUE; - if (ctx->Color.ColorMask[3]) dwFlags |= D3DCOLORWRITEENABLE_ALPHA; + if (ctx->Color.ColorMask[0][0]) dwFlags |= D3DCOLORWRITEENABLE_RED; + if (ctx->Color.ColorMask[0][1]) dwFlags |= D3DCOLORWRITEENABLE_GREEN; + if (ctx->Color.ColorMask[0][2]) dwFlags |= D3DCOLORWRITEENABLE_BLUE; + if (ctx->Color.ColorMask[0][3]) dwFlags |= D3DCOLORWRITEENABLE_ALPHA; _GLD_DX9_DEV(SetRenderState(gld->pDev, D3DRS_COLORWRITEENABLE, dwFlags)); } diff --git a/src/mesa/drivers/x11/xm_dd.c b/src/mesa/drivers/x11/xm_dd.c index a27d7045ab..df04e3a101 100644 --- a/src/mesa/drivers/x11/xm_dd.c +++ b/src/mesa/drivers/x11/xm_dd.c @@ -381,7 +381,7 @@ clear_buffers(GLcontext *ctx, GLbitfield buffers) { if (ctx->DrawBuffer->Name == 0) { /* this is a window system framebuffer */ - const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask; + const GLuint *colorMask = (GLuint *) &ctx->Color.ColorMask[0]; XMesaBuffer b = XMESA_BUFFER(ctx->DrawBuffer); const GLint x = ctx->DrawBuffer->_Xmin; const GLint y = ctx->DrawBuffer->_Ymin; diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c index 88ce0a4281..30e97a6e38 100644 --- a/src/mesa/main/attrib.c +++ b/src/mesa/main/attrib.c @@ -919,10 +919,22 @@ _mesa_PopAttrib(void) color->ClearColor[2], color->ClearColor[3]); _mesa_IndexMask(color->IndexMask); - _mesa_ColorMask((GLboolean) (color->ColorMask[0] != 0), - (GLboolean) (color->ColorMask[1] != 0), - (GLboolean) (color->ColorMask[2] != 0), - (GLboolean) (color->ColorMask[3] != 0)); + if (1/*ctx->Extensions.EXT_draw_buffers2*/) { + _mesa_ColorMask((GLboolean) (color->ColorMask[0][0] != 0), + (GLboolean) (color->ColorMask[0][1] != 0), + (GLboolean) (color->ColorMask[0][2] != 0), + (GLboolean) (color->ColorMask[0][3] != 0)); + } + else { + GLuint i; + for (i = 0; i < ctx->Const.MaxDrawBuffers; i++) { + _mesa_ColorMaskIndexed(i, + (GLboolean) (color->ColorMask[i][0] != 0), + (GLboolean) (color->ColorMask[i][1] != 0), + (GLboolean) (color->ColorMask[i][2] != 0), + (GLboolean) (color->ColorMask[i][3] != 0)); + } + } { /* Need to determine if more than one color output is * specified. If so, call glDrawBuffersARB, else call diff --git a/src/mesa/main/blend.c b/src/mesa/main/blend.c index 5a9d94e12d..b8170dd468 100644 --- a/src/mesa/main/blend.c +++ b/src/mesa/main/blend.c @@ -484,6 +484,8 @@ _mesa_ColorMask( GLboolean red, GLboolean green, { GET_CURRENT_CONTEXT(ctx); GLubyte tmp[4]; + GLuint i; + GLboolean flushed; ASSERT_OUTSIDE_BEGIN_END(ctx); if (MESA_VERBOSE & VERBOSE_API) @@ -497,14 +499,58 @@ _mesa_ColorMask( GLboolean red, GLboolean green, tmp[BCOMP] = blue ? 0xff : 0x0; tmp[ACOMP] = alpha ? 0xff : 0x0; - if (TEST_EQ_4UBV(tmp, ctx->Color.ColorMask)) + flushed = GL_FALSE; + for (i = 0; i < ctx->Const.MaxDrawBuffers; i++) { + if (!TEST_EQ_4V(tmp, ctx->Color.ColorMask[i])) { + if (!flushed) { + FLUSH_VERTICES(ctx, _NEW_COLOR); + } + flushed = GL_TRUE; + COPY_4UBV(ctx->Color.ColorMask[i], tmp); + } + } + + if (ctx->Driver.ColorMask) + ctx->Driver.ColorMask( ctx, red, green, blue, alpha ); +} + + +/** + * For GL_EXT_draw_buffers2 and GL3 + */ +void GLAPIENTRY +_mesa_ColorMaskIndexed( GLuint buf, GLboolean red, GLboolean green, + GLboolean blue, GLboolean alpha ) +{ + GLubyte tmp[4]; + GET_CURRENT_CONTEXT(ctx); + ASSERT_OUTSIDE_BEGIN_END(ctx); + + if (MESA_VERBOSE & VERBOSE_API) + _mesa_debug(ctx, "glColorMaskIndexed %u %d %d %d %d\n", + buf, red, green, blue, alpha); + + if (buf >= ctx->Const.MaxDrawBuffers) { + _mesa_error(ctx, GL_INVALID_VALUE, "glColorMaskIndexed(buf=%u)", buf); + return; + } + + /* Shouldn't have any information about channel depth in core mesa + * -- should probably store these as the native booleans: + */ + tmp[RCOMP] = red ? 0xff : 0x0; + tmp[GCOMP] = green ? 0xff : 0x0; + tmp[BCOMP] = blue ? 0xff : 0x0; + tmp[ACOMP] = alpha ? 0xff : 0x0; + + if (TEST_EQ_4V(tmp, ctx->Color.ColorMask[buf])) return; FLUSH_VERTICES(ctx, _NEW_COLOR); - COPY_4UBV(ctx->Color.ColorMask, tmp); + COPY_4UBV(ctx->Color.ColorMask[buf], tmp); - if (ctx->Driver.ColorMask) - ctx->Driver.ColorMask( ctx, red, green, blue, alpha ); + if (ctx->Driver.ColorMaskIndexed) + ctx->Driver.ColorMaskIndexed(ctx, buf, red, green, blue, alpha); } @@ -555,10 +601,7 @@ void _mesa_init_color( GLcontext * ctx ) { /* Color buffer group */ ctx->Color.IndexMask = ~0u; - ctx->Color.ColorMask[0] = 0xff; - ctx->Color.ColorMask[1] = 0xff; - ctx->Color.ColorMask[2] = 0xff; - ctx->Color.ColorMask[3] = 0xff; + memset(ctx->Color.ColorMask, 0xff, sizeof(ctx->Color.ColorMask)); ctx->Color.ClearIndex = 0; ASSIGN_4V( ctx->Color.ClearColor, 0, 0, 0, 0 ); ctx->Color.AlphaEnabled = GL_FALSE; diff --git a/src/mesa/main/blend.h b/src/mesa/main/blend.h index 5c0f2783a7..b4fd7470eb 100644 --- a/src/mesa/main/blend.h +++ b/src/mesa/main/blend.h @@ -72,6 +72,10 @@ extern void GLAPIENTRY _mesa_ColorMask( GLboolean red, GLboolean green, GLboolean blue, GLboolean alpha ); +extern void GLAPIENTRY +_mesa_ColorMaskIndexed( GLuint buf, GLboolean red, GLboolean green, + GLboolean blue, GLboolean alpha ); + extern void GLAPIENTRY _mesa_ClampColorARB(GLenum target, GLenum clamp); diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h index 6dadf5c079..496b0d2ba8 100644 --- a/src/mesa/main/dd.h +++ b/src/mesa/main/dd.h @@ -625,6 +625,8 @@ struct dd_function_table { /** Enable and disable writing of frame buffer color components */ void (*ColorMask)(GLcontext *ctx, GLboolean rmask, GLboolean gmask, GLboolean bmask, GLboolean amask ); + void (*ColorMaskIndexed)(GLcontext *ctx, GLuint buf, GLboolean rmask, + GLboolean gmask, GLboolean bmask, GLboolean amask); /** Cause a material color to track the current color */ void (*ColorMaterial)(GLcontext *ctx, GLenum face, GLenum mode); /** Specify whether front- or back-facing facets can be culled */ diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c index aff67466bc..44396a0491 100644 --- a/src/mesa/main/get.c +++ b/src/mesa/main/get.c @@ -210,10 +210,10 @@ _mesa_GetBooleanv( GLenum pname, GLboolean *params ) params[0] = ENUM_TO_BOOLEAN(ctx->Light.ColorMaterialMode); break; case GL_COLOR_WRITEMASK: - params[0] = INT_TO_BOOLEAN(ctx->Color.ColorMask[RCOMP] ? 1 : 0); - params[1] = INT_TO_BOOLEAN(ctx->Color.ColorMask[GCOMP] ? 1 : 0); - params[2] = INT_TO_BOOLEAN(ctx->Color.ColorMask[BCOMP] ? 1 : 0); - params[3] = INT_TO_BOOLEAN(ctx->Color.ColorMask[ACOMP] ? 1 : 0); + params[0] = INT_TO_BOOLEAN(ctx->Color.ColorMask[0][RCOMP] ? 1 : 0); + params[1] = INT_TO_BOOLEAN(ctx->Color.ColorMask[0][GCOMP] ? 1 : 0); + params[2] = INT_TO_BOOLEAN(ctx->Color.ColorMask[0][BCOMP] ? 1 : 0); + params[3] = INT_TO_BOOLEAN(ctx->Color.ColorMask[0][ACOMP] ? 1 : 0); break; case GL_CULL_FACE: params[0] = ctx->Polygon.CullFlag; @@ -2045,10 +2045,10 @@ _mesa_GetFloatv( GLenum pname, GLfloat *params ) params[0] = ENUM_TO_FLOAT(ctx->Light.ColorMaterialMode); break; case GL_COLOR_WRITEMASK: - params[0] = (GLfloat)(ctx->Color.ColorMask[RCOMP] ? 1 : 0); - params[1] = (GLfloat)(ctx->Color.ColorMask[GCOMP] ? 1 : 0); - params[2] = (GLfloat)(ctx->Color.ColorMask[BCOMP] ? 1 : 0); - params[3] = (GLfloat)(ctx->Color.ColorMask[ACOMP] ? 1 : 0); + params[0] = (GLfloat)(ctx->Color.ColorMask[0][RCOMP] ? 1 : 0); + params[1] = (GLfloat)(ctx->Color.ColorMask[0][GCOMP] ? 1 : 0); + params[2] = (GLfloat)(ctx->Color.ColorMask[0][BCOMP] ? 1 : 0); + params[3] = (GLfloat)(ctx->Color.ColorMask[0][ACOMP] ? 1 : 0); break; case GL_CULL_FACE: params[0] = BOOLEAN_TO_FLOAT(ctx->Polygon.CullFlag); @@ -3880,10 +3880,10 @@ _mesa_GetIntegerv( GLenum pname, GLint *params ) params[0] = ENUM_TO_INT(ctx->Light.ColorMaterialMode); break; case GL_COLOR_WRITEMASK: - params[0] = ctx->Color.ColorMask[RCOMP] ? 1 : 0; - params[1] = ctx->Color.ColorMask[GCOMP] ? 1 : 0; - params[2] = ctx->Color.ColorMask[BCOMP] ? 1 : 0; - params[3] = ctx->Color.ColorMask[ACOMP] ? 1 : 0; + params[0] = ctx->Color.ColorMask[0][RCOMP] ? 1 : 0; + params[1] = ctx->Color.ColorMask[0][GCOMP] ? 1 : 0; + params[2] = ctx->Color.ColorMask[0][BCOMP] ? 1 : 0; + params[3] = ctx->Color.ColorMask[0][ACOMP] ? 1 : 0; break; case GL_CULL_FACE: params[0] = BOOLEAN_TO_INT(ctx->Polygon.CullFlag); @@ -5716,10 +5716,10 @@ _mesa_GetInteger64v( GLenum pname, GLint64 *params ) params[0] = ENUM_TO_INT64(ctx->Light.ColorMaterialMode); break; case GL_COLOR_WRITEMASK: - params[0] = (GLint64)(ctx->Color.ColorMask[RCOMP] ? 1 : 0); - params[1] = (GLint64)(ctx->Color.ColorMask[GCOMP] ? 1 : 0); - params[2] = (GLint64)(ctx->Color.ColorMask[BCOMP] ? 1 : 0); - params[3] = (GLint64)(ctx->Color.ColorMask[ACOMP] ? 1 : 0); + params[0] = (GLint64)(ctx->Color.ColorMask[0][RCOMP] ? 1 : 0); + params[1] = (GLint64)(ctx->Color.ColorMask[0][GCOMP] ? 1 : 0); + params[2] = (GLint64)(ctx->Color.ColorMask[0][BCOMP] ? 1 : 0); + params[3] = (GLint64)(ctx->Color.ColorMask[0][ACOMP] ? 1 : 0); break; case GL_CULL_FACE: params[0] = BOOLEAN_TO_INT64(ctx->Polygon.CullFlag); @@ -7448,11 +7448,20 @@ _mesa_GetBooleanIndexedv( GLenum pname, GLuint index, GLboolean *params ) switch (pname) { case GL_BLEND: - if (index >= MAX_DRAW_BUFFERS) { + if (index >= ctx->Const.MaxDrawBuffers) { _mesa_error(ctx, GL_INVALID_VALUE, "glGetBooleanIndexedv(index=%u), index", pname); } params[0] = INT_TO_BOOLEAN(((ctx->Color.BlendEnabled >> index) & 1)); break; + case GL_COLOR_WRITEMASK: + if (index >= ctx->Const.MaxDrawBuffers) { + _mesa_error(ctx, GL_INVALID_VALUE, "glGetBooleanIndexedv(index=%u), index", pname); + } + params[0] = INT_TO_BOOLEAN(ctx->Color.ColorMask[index][RCOMP] ? 1 : 0); + params[1] = INT_TO_BOOLEAN(ctx->Color.ColorMask[index][GCOMP] ? 1 : 0); + params[2] = INT_TO_BOOLEAN(ctx->Color.ColorMask[index][BCOMP] ? 1 : 0); + params[3] = INT_TO_BOOLEAN(ctx->Color.ColorMask[index][ACOMP] ? 1 : 0); + break; default: _mesa_error(ctx, GL_INVALID_ENUM, "glGetBooleanIndexedv(pname=0x%x)", pname); } @@ -7472,11 +7481,20 @@ _mesa_GetIntegerIndexedv( GLenum pname, GLuint index, GLint *params ) switch (pname) { case GL_BLEND: - if (index >= MAX_DRAW_BUFFERS) { + if (index >= ctx->Const.MaxDrawBuffers) { _mesa_error(ctx, GL_INVALID_VALUE, "glGetIntegerIndexedv(index=%u), index", pname); } params[0] = ((ctx->Color.BlendEnabled >> index) & 1); break; + case GL_COLOR_WRITEMASK: + if (index >= ctx->Const.MaxDrawBuffers) { + _mesa_error(ctx, GL_INVALID_VALUE, "glGetIntegerIndexedv(index=%u), index", pname); + } + params[0] = ctx->Color.ColorMask[index][RCOMP] ? 1 : 0; + params[1] = ctx->Color.ColorMask[index][GCOMP] ? 1 : 0; + params[2] = ctx->Color.ColorMask[index][BCOMP] ? 1 : 0; + params[3] = ctx->Color.ColorMask[index][ACOMP] ? 1 : 0; + break; default: _mesa_error(ctx, GL_INVALID_ENUM, "glGetIntegerIndexedv(pname=0x%x)", pname); } @@ -7497,11 +7515,20 @@ _mesa_GetInteger64Indexedv( GLenum pname, GLuint index, GLint64 *params ) switch (pname) { case GL_BLEND: - if (index >= MAX_DRAW_BUFFERS) { + if (index >= ctx->Const.MaxDrawBuffers) { _mesa_error(ctx, GL_INVALID_VALUE, "glGetInteger64Indexedv(index=%u), index", pname); } params[0] = (GLint64)(((ctx->Color.BlendEnabled >> index) & 1)); break; + case GL_COLOR_WRITEMASK: + if (index >= ctx->Const.MaxDrawBuffers) { + _mesa_error(ctx, GL_INVALID_VALUE, "glGetInteger64Indexedv(index=%u), index", pname); + } + params[0] = (GLint64)(ctx->Color.ColorMask[index][RCOMP] ? 1 : 0); + params[1] = (GLint64)(ctx->Color.ColorMask[index][GCOMP] ? 1 : 0); + params[2] = (GLint64)(ctx->Color.ColorMask[index][BCOMP] ? 1 : 0); + params[3] = (GLint64)(ctx->Color.ColorMask[index][ACOMP] ? 1 : 0); + break; default: _mesa_error(ctx, GL_INVALID_ENUM, "glGetInteger64Indexedv(pname=0x%x)", pname); } diff --git a/src/mesa/main/get_gen.py b/src/mesa/main/get_gen.py index 8b6500fae1..18708be260 100644 --- a/src/mesa/main/get_gen.py +++ b/src/mesa/main/get_gen.py @@ -126,10 +126,10 @@ StateVars = [ ( "GL_COLOR_MATERIAL_PARAMETER", GLenum, ["ctx->Light.ColorMaterialMode"], "", None ), ( "GL_COLOR_WRITEMASK", GLint, - [ "ctx->Color.ColorMask[RCOMP] ? 1 : 0", - "ctx->Color.ColorMask[GCOMP] ? 1 : 0", - "ctx->Color.ColorMask[BCOMP] ? 1 : 0", - "ctx->Color.ColorMask[ACOMP] ? 1 : 0" ], "", None ), + [ "ctx->Color.ColorMask[0][RCOMP] ? 1 : 0", + "ctx->Color.ColorMask[0][GCOMP] ? 1 : 0", + "ctx->Color.ColorMask[0][BCOMP] ? 1 : 0", + "ctx->Color.ColorMask[0][ACOMP] ? 1 : 0" ], "", None ), ( "GL_CULL_FACE", GLboolean, ["ctx->Polygon.CullFlag"], "", None ), ( "GL_CULL_FACE_MODE", GLenum, ["ctx->Polygon.CullFaceMode"], "", None ), ( "GL_CURRENT_COLOR", GLfloatN, @@ -1035,7 +1035,14 @@ StateVars = [ # These are queried via glGetIntegetIndexdvEXT() or glGetIntegeri_v() IndexedStateVars = [ - ( "GL_BLEND", GLint, ["((ctx->Color.BlendEnabled >> index) & 1)"], "MAX_DRAW_BUFFERS", None ), + ( "GL_BLEND", GLint, ["((ctx->Color.BlendEnabled >> index) & 1)"], + "ctx->Const.MaxDrawBuffers", None ), + ( "GL_COLOR_WRITEMASK", GLint, + [ "ctx->Color.ColorMask[index][RCOMP] ? 1 : 0", + "ctx->Color.ColorMask[index][GCOMP] ? 1 : 0", + "ctx->Color.ColorMask[index][BCOMP] ? 1 : 0", + "ctx->Color.ColorMask[index][ACOMP] ? 1 : 0" ], + "ctx->Const.MaxDrawBuffers", None ), # XXX more to come... ] diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 170c35b11c..7ef2852242 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -564,7 +564,7 @@ struct gl_colorbuffer_attrib GLclampf ClearColor[4]; /**< Color to use for glClear */ GLuint IndexMask; /**< Color index write mask */ - GLubyte ColorMask[4]; /**< Each flag is 0xff or 0x0 */ + GLubyte ColorMask[MAX_DRAW_BUFFERS][4];/**< Each flag is 0xff or 0x0 */ GLenum DrawBuffer[MAX_DRAW_BUFFERS]; /**< Which buffer to draw into */ diff --git a/src/mesa/state_tracker/st_atom_blend.c b/src/mesa/state_tracker/st_atom_blend.c index 35c09c3e08..43e62c29f3 100644 --- a/src/mesa/state_tracker/st_atom_blend.c +++ b/src/mesa/state_tracker/st_atom_blend.c @@ -200,13 +200,13 @@ update_blend( struct st_context *st ) } /* Colormask - maybe reverse these bits? */ - if (st->ctx->Color.ColorMask[0]) + if (st->ctx->Color.ColorMask[0][0]) blend->colormask |= PIPE_MASK_R; - if (st->ctx->Color.ColorMask[1]) + if (st->ctx->Color.ColorMask[0][1]) blend->colormask |= PIPE_MASK_G; - if (st->ctx->Color.ColorMask[2]) + if (st->ctx->Color.ColorMask[0][2]) blend->colormask |= PIPE_MASK_B; - if (st->ctx->Color.ColorMask[3]) + if (st->ctx->Color.ColorMask[0][3]) blend->colormask |= PIPE_MASK_A; if (st->ctx->Color.DitherFlag) diff --git a/src/mesa/state_tracker/st_cb_accum.c b/src/mesa/state_tracker/st_cb_accum.c index a6b9765452..da7b97d325 100644 --- a/src/mesa/state_tracker/st_cb_accum.c +++ b/src/mesa/state_tracker/st_cb_accum.c @@ -229,7 +229,7 @@ accum_return(GLcontext *ctx, GLfloat value, { struct pipe_context *pipe = ctx->st->pipe; struct pipe_screen *screen = pipe->screen; - const GLubyte *colormask = ctx->Color.ColorMask; + const GLubyte *colormask = ctx->Color.ColorMask[0]; enum pipe_transfer_usage usage; struct pipe_transfer *color_trans; size_t stride = acc_strb->stride; diff --git a/src/mesa/state_tracker/st_cb_clear.c b/src/mesa/state_tracker/st_cb_clear.c index 72b30e7c04..192d765f45 100644 --- a/src/mesa/state_tracker/st_cb_clear.c +++ b/src/mesa/state_tracker/st_cb_clear.c @@ -232,13 +232,13 @@ clear_with_quad(GLcontext *ctx, blend.rgb_dst_factor = PIPE_BLENDFACTOR_ZERO; blend.alpha_dst_factor = PIPE_BLENDFACTOR_ZERO; if (color) { - if (ctx->Color.ColorMask[0]) + if (ctx->Color.ColorMask[0][0]) blend.colormask |= PIPE_MASK_R; - if (ctx->Color.ColorMask[1]) + if (ctx->Color.ColorMask[0][1]) blend.colormask |= PIPE_MASK_G; - if (ctx->Color.ColorMask[2]) + if (ctx->Color.ColorMask[0][2]) blend.colormask |= PIPE_MASK_B; - if (ctx->Color.ColorMask[3]) + if (ctx->Color.ColorMask[0][3]) blend.colormask |= PIPE_MASK_A; if (st->ctx->Color.DitherFlag) blend.dither = 1; @@ -300,10 +300,10 @@ check_clear_color_with_quad(GLcontext *ctx, struct gl_renderbuffer *rb) ctx->Scissor.Height < rb->Height)) return TRUE; - if (!ctx->Color.ColorMask[0] || - !ctx->Color.ColorMask[1] || - !ctx->Color.ColorMask[2] || - !ctx->Color.ColorMask[3]) + if (!ctx->Color.ColorMask[0][0] || + !ctx->Color.ColorMask[0][1] || + !ctx->Color.ColorMask[0][2] || + !ctx->Color.ColorMask[0][3]) return TRUE; return FALSE; diff --git a/src/mesa/swrast/s_accum.c b/src/mesa/swrast/s_accum.c index c6c7dbf5cf..2d8c361e5d 100644 --- a/src/mesa/swrast/s_accum.c +++ b/src/mesa/swrast/s_accum.c @@ -528,7 +528,7 @@ accum_return(GLcontext *ctx, GLfloat value, for (buffer = 0; buffer < fb->_NumColorDrawBuffers; buffer++) { struct gl_renderbuffer *rb = fb->_ColorDrawBuffers[buffer]; if (masking) { - _swrast_mask_rgba_span(ctx, rb, &span); + _swrast_mask_rgba_span(ctx, rb, &span, buffer); } rb->PutRow(ctx, rb, width, xpos, ypos + i, span.array->rgba, NULL); } diff --git a/src/mesa/swrast/s_clear.c b/src/mesa/swrast/s_clear.c index 002718ded8..2d27797d43 100644 --- a/src/mesa/swrast/s_clear.c +++ b/src/mesa/swrast/s_clear.c @@ -40,7 +40,8 @@ * Clear the color buffer when glColorMask is in effect. */ static void -clear_rgba_buffer_with_masking(GLcontext *ctx, struct gl_renderbuffer *rb) +clear_rgba_buffer_with_masking(GLcontext *ctx, struct gl_renderbuffer *rb, + GLuint buf) { const GLint x = ctx->DrawBuffer->_Xmin; const GLint y = ctx->DrawBuffer->_Ymin; @@ -95,7 +96,7 @@ clear_rgba_buffer_with_masking(GLcontext *ctx, struct gl_renderbuffer *rb) for (i = 0; i < height; i++) { span.x = x; span.y = y + i; - _swrast_mask_rgba_span(ctx, rb, &span); + _swrast_mask_rgba_span(ctx, rb, &span, buf); /* write masked row */ rb->PutRow(ctx, rb, width, x, y + i, span.array->rgba, NULL); } @@ -145,7 +146,7 @@ clear_ci_buffer_with_masking(GLcontext *ctx, struct gl_renderbuffer *rb) * Clear an rgba color buffer without channel masking. */ static void -clear_rgba_buffer(GLcontext *ctx, struct gl_renderbuffer *rb) +clear_rgba_buffer(GLcontext *ctx, struct gl_renderbuffer *rb, GLuint buf) { const GLint x = ctx->DrawBuffer->_Xmin; const GLint y = ctx->DrawBuffer->_Ymin; @@ -158,10 +159,10 @@ clear_rgba_buffer(GLcontext *ctx, struct gl_renderbuffer *rb) ASSERT(ctx->Visual.rgbMode); - ASSERT(ctx->Color.ColorMask[0] && - ctx->Color.ColorMask[1] && - ctx->Color.ColorMask[2] && - ctx->Color.ColorMask[3]); + ASSERT(ctx->Color.ColorMask[buf][0] && + ctx->Color.ColorMask[buf][1] && + ctx->Color.ColorMask[buf][2] && + ctx->Color.ColorMask[buf][3]); ASSERT(rb->PutMonoRow); @@ -246,43 +247,24 @@ clear_ci_buffer(GLcontext *ctx, struct gl_renderbuffer *rb) static void clear_color_buffers(GLcontext *ctx) { - GLboolean masking; GLuint buf; - if (ctx->Visual.rgbMode) { - if (ctx->Color.ColorMask[0] && - ctx->Color.ColorMask[1] && - ctx->Color.ColorMask[2] && - ctx->Color.ColorMask[3]) { - masking = GL_FALSE; - } - else { - masking = GL_TRUE; - } - } - else { - struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0]; - const GLuint indexMask = (1 << _mesa_get_format_bits(rb->Format, GL_INDEX_BITS)) - 1; - if ((ctx->Color.IndexMask & indexMask) == indexMask) { - masking = GL_FALSE; - } - else { - masking = GL_TRUE; - } - } - for (buf = 0; buf < ctx->DrawBuffer->_NumColorDrawBuffers; buf++) { struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[buf]; if (ctx->Visual.rgbMode) { - if (masking) { - clear_rgba_buffer_with_masking(ctx, rb); + if (ctx->Color.ColorMask[buf][0] == 0 || + ctx->Color.ColorMask[buf][1] == 0 || + ctx->Color.ColorMask[buf][2] == 0 || + ctx->Color.ColorMask[buf][3] == 0) { + clear_rgba_buffer_with_masking(ctx, rb, buf); } else { - clear_rgba_buffer(ctx, rb); + clear_rgba_buffer(ctx, rb, buf); } } else { - if (masking) { + const GLuint indexMask = (1 << _mesa_get_format_bits(rb->Format, GL_INDEX_BITS)) - 1; + if ((ctx->Color.IndexMask & indexMask) != indexMask) { clear_ci_buffer_with_masking(ctx, rb); } else { diff --git a/src/mesa/swrast/s_context.c b/src/mesa/swrast/s_context.c index abf0008565..f9092c215a 100644 --- a/src/mesa/swrast/s_context.c +++ b/src/mesa/swrast/s_context.c @@ -55,6 +55,7 @@ _swrast_update_rasterflags( GLcontext *ctx ) { SWcontext *swrast = SWRAST_CONTEXT(ctx); GLbitfield rasterMask = 0; + GLuint i; if (ctx->Color.AlphaEnabled) rasterMask |= ALPHATEST_BIT; if (ctx->Color.BlendEnabled) rasterMask |= BLEND_BIT; @@ -63,8 +64,15 @@ _swrast_update_rasterflags( GLcontext *ctx ) if (ctx->Scissor.Enabled) rasterMask |= CLIP_BIT; if (ctx->Stencil._Enabled) rasterMask |= STENCIL_BIT; if (ctx->Visual.rgbMode) { - const GLuint colorMask = *((GLuint *) &ctx->Color.ColorMask); - if (colorMask != 0xffffffff) rasterMask |= MASKING_BIT; + for (i = 0; i < ctx->Const.MaxDrawBuffers; i++) { + if (!ctx->Color.ColorMask[i][0] || + !ctx->Color.ColorMask[i][1] || + !ctx->Color.ColorMask[i][2] || + !ctx->Color.ColorMask[i][3]) { + rasterMask |= MASKING_BIT; + break; + } + } if (ctx->Color._LogicOpEnabled) rasterMask |= LOGIC_OP_BIT; if (ctx->Texture._EnabledUnits) rasterMask |= TEXTURE_BIT; } @@ -92,13 +100,23 @@ _swrast_update_rasterflags( GLcontext *ctx ) /* more than one color buffer designated for writing (or zero buffers) */ rasterMask |= MULTI_DRAW_BIT; } - else if (ctx->Visual.rgbMode && *((GLuint *) ctx->Color.ColorMask) == 0) { - rasterMask |= MULTI_DRAW_BIT; /* all RGBA channels disabled */ - } else if (!ctx->Visual.rgbMode && ctx->Color.IndexMask==0) { rasterMask |= MULTI_DRAW_BIT; /* all color index bits disabled */ } + if (ctx->Visual.rgbMode) { + for (i = 0; i < ctx->Const.MaxDrawBuffers; i++) { + if (ctx->Color.ColorMask[i][0] + + ctx->Color.ColorMask[i][1] + + ctx->Color.ColorMask[i][2] + + ctx->Color.ColorMask[i][3] == 0) { + rasterMask |= MULTI_DRAW_BIT; /* all RGBA channels disabled */ + break; + } + } + } + + if (ctx->FragmentProgram._Current) { rasterMask |= FRAGPROG_BIT; } diff --git a/src/mesa/swrast/s_masking.c b/src/mesa/swrast/s_masking.c index df779b0739..69c2feb6da 100644 --- a/src/mesa/swrast/s_masking.c +++ b/src/mesa/swrast/s_masking.c @@ -41,7 +41,7 @@ */ void _swrast_mask_rgba_span(GLcontext *ctx, struct gl_renderbuffer *rb, - SWspan *span) + SWspan *span, GLuint buf) { const GLuint n = span->end; void *rbPixels; @@ -58,7 +58,7 @@ _swrast_mask_rgba_span(GLcontext *ctx, struct gl_renderbuffer *rb, */ if (span->array->ChanType == GL_UNSIGNED_BYTE) { /* treat 4xGLubyte as 1xGLuint */ - const GLuint srcMask = *((GLuint *) ctx->Color.ColorMask); + const GLuint srcMask = *((GLuint *) ctx->Color.ColorMask[buf]); const GLuint dstMask = ~srcMask; const GLuint *dst = (const GLuint *) rbPixels; GLuint *src = (GLuint *) span->array->rgba8; @@ -70,10 +70,10 @@ _swrast_mask_rgba_span(GLcontext *ctx, struct gl_renderbuffer *rb, else if (span->array->ChanType == GL_UNSIGNED_SHORT) { /* 2-byte components */ /* XXX try to use 64-bit arithmetic someday */ - const GLushort rMask = ctx->Color.ColorMask[RCOMP] ? 0xffff : 0x0; - const GLushort gMask = ctx->Color.ColorMask[GCOMP] ? 0xffff : 0x0; - const GLushort bMask = ctx->Color.ColorMask[BCOMP] ? 0xffff : 0x0; - const GLushort aMask = ctx->Color.ColorMask[ACOMP] ? 0xffff : 0x0; + const GLushort rMask = ctx->Color.ColorMask[buf][RCOMP] ? 0xffff : 0x0; + const GLushort gMask = ctx->Color.ColorMask[buf][GCOMP] ? 0xffff : 0x0; + const GLushort bMask = ctx->Color.ColorMask[buf][BCOMP] ? 0xffff : 0x0; + const GLushort aMask = ctx->Color.ColorMask[buf][ACOMP] ? 0xffff : 0x0; const GLushort (*dst)[4] = (const GLushort (*)[4]) rbPixels; GLushort (*src)[4] = span->array->rgba16; GLuint i; @@ -86,10 +86,10 @@ _swrast_mask_rgba_span(GLcontext *ctx, struct gl_renderbuffer *rb, } else { /* 4-byte components */ - const GLuint rMask = ctx->Color.ColorMask[RCOMP] ? ~0x0 : 0x0; - const GLuint gMask = ctx->Color.ColorMask[GCOMP] ? ~0x0 : 0x0; - const GLuint bMask = ctx->Color.ColorMask[BCOMP] ? ~0x0 : 0x0; - const GLuint aMask = ctx->Color.ColorMask[ACOMP] ? ~0x0 : 0x0; + const GLuint rMask = ctx->Color.ColorMask[buf][RCOMP] ? ~0x0 : 0x0; + const GLuint gMask = ctx->Color.ColorMask[buf][GCOMP] ? ~0x0 : 0x0; + const GLuint bMask = ctx->Color.ColorMask[buf][BCOMP] ? ~0x0 : 0x0; + const GLuint aMask = ctx->Color.ColorMask[buf][ACOMP] ? ~0x0 : 0x0; const GLuint (*dst)[4] = (const GLuint (*)[4]) rbPixels; GLuint (*src)[4] = (GLuint (*)[4]) span->array->attribs[FRAG_ATTRIB_COL0]; GLuint i; diff --git a/src/mesa/swrast/s_masking.h b/src/mesa/swrast/s_masking.h index 3260ca34e3..fed47f8cfb 100644 --- a/src/mesa/swrast/s_masking.h +++ b/src/mesa/swrast/s_masking.h @@ -32,7 +32,7 @@ extern void _swrast_mask_rgba_span(GLcontext *ctx, struct gl_renderbuffer *rb, - SWspan *span); + SWspan *span, GLuint buf); extern void diff --git a/src/mesa/swrast/s_span.c b/src/mesa/swrast/s_span.c index 00de13d495..a311d4b4bd 100644 --- a/src/mesa/swrast/s_span.c +++ b/src/mesa/swrast/s_span.c @@ -1278,7 +1278,7 @@ void _swrast_write_rgba_span( GLcontext *ctx, SWspan *span) { const SWcontext *swrast = SWRAST_CONTEXT(ctx); - const GLuint colorMask = *((GLuint *) ctx->Color.ColorMask); + const GLuint *colorMask = (GLuint *) ctx->Color.ColorMask; const GLbitfield origInterpMask = span->interpMask; const GLbitfield origArrayMask = span->arrayMask; const GLbitfield origArrayAttribs = span->arrayAttribs; @@ -1389,7 +1389,7 @@ _swrast_write_rgba_span( GLcontext *ctx, SWspan *span) /* We had to wait until now to check for glColorMask(0,0,0,0) because of * the occlusion test. */ - if (colorMask == 0x0) { + if (fb->_NumColorDrawBuffers == 1 && colorMask[0] == 0x0) { /* no colors to write */ goto end; } @@ -1483,8 +1483,8 @@ _swrast_write_rgba_span( GLcontext *ctx, SWspan *span) _swrast_blend_span(ctx, rb, span); } - if (colorMask != 0xffffffff) { - _swrast_mask_rgba_span(ctx, rb, span); + if (colorMask[buf] != 0xffffffff) { + _swrast_mask_rgba_span(ctx, rb, span, buf); } if (span->arrayMask & SPAN_XY) { diff --git a/src/mesa/swrast/s_triangle.c b/src/mesa/swrast/s_triangle.c index 5bec606696..11184b72ce 100644 --- a/src/mesa/swrast/s_triangle.c +++ b/src/mesa/swrast/s_triangle.c @@ -1030,10 +1030,10 @@ _swrast_choose_triangle( GLcontext *ctx ) ctx->Depth.Func == GL_LESS && !ctx->Stencil._Enabled) { if ((rgbmode && - ctx->Color.ColorMask[0] == 0 && - ctx->Color.ColorMask[1] == 0 && - ctx->Color.ColorMask[2] == 0 && - ctx->Color.ColorMask[3] == 0) + ctx->Color.ColorMask[0][0] == 0 && + ctx->Color.ColorMask[0][1] == 0 && + ctx->Color.ColorMask[0][2] == 0 && + ctx->Color.ColorMask[0][3] == 0) || (!rgbmode && ctx->Color.IndexMask == 0)) { USE(occlusion_zless_triangle); -- cgit v1.2.3 From 8616cec5c9889e6166839b33baa8db52f04d409c Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 17:03:33 -0500 Subject: Check for libdrm_$chipset.pc when needed This adds missing pkg-config lookup for intel and moves the radeon lookup into a case...esac so it's only looked up when one or more of the radeon drivers are enabled. --- configs/autoconf.in | 2 ++ configure.ac | 30 +++++++++++++++++++++--------- src/mesa/drivers/dri/i915/Makefile | 3 ++- src/mesa/drivers/dri/i965/Makefile | 3 ++- 4 files changed, 27 insertions(+), 11 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/configs/autoconf.in b/configs/autoconf.in index b94d9bce46..f63618ebea 100644 --- a/configs/autoconf.in +++ b/configs/autoconf.in @@ -22,6 +22,8 @@ LDFLAGS = @LDFLAGS@ EXTRA_LIB_PATH = @EXTRA_LIB_PATH@ RADEON_CFLAGS = @RADEON_CFLAGS@ RADEON_LDFLAGS = @RADEON_LDFLAGS@ +INTEL_LIBS = @INTEL_LIBS@ +INTEL_CFLAGS = @INTEL_CFLAGS@ # Assembler MESA_ASM_SOURCES = @MESA_ASM_SOURCES@ diff --git a/configure.ac b/configure.ac index b2a969bc8c..d3fbd02713 100644 --- a/configure.ac +++ b/configure.ac @@ -447,8 +447,6 @@ AC_SUBST([GALLIUM_WINSYS_DIRS]) AC_SUBST([GALLIUM_WINSYS_DRM_DIRS]) AC_SUBST([GALLIUM_DRIVERS_DIRS]) AC_SUBST([GALLIUM_STATE_TRACKERS_DIRS]) -AC_SUBST([RADEON_CFLAGS]) -AC_SUBST([RADEON_LDFLAGS]) dnl dnl User supplied program configuration @@ -576,13 +574,6 @@ dri) GL_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED dri2proto >= $DRI2PROTO_REQUIRED" DRI_PC_REQ_PRIV="libdrm >= $LIBDRM_REQUIRED" - PKG_CHECK_MODULES([LIBDRM_RADEON], [libdrm_radeon libdrm >= $LIBDRM_RADEON_REQUIRED], HAVE_LIBDRM_RADEON=yes, HAVE_LIBDRM_RADEON=no) - - if test "$HAVE_LIBDRM_RADEON" = yes; then - RADEON_CFLAGS="-DHAVE_LIBDRM_RADEON=1 $LIBDRM_RADEON_CFLAGS" - RADEON_LDFLAGS=$LIBDRM_RADEON_LIBS - fi - # find the DRI deps for libGL if test "$x11_pkgconfig" = yes; then # add xcb modules if necessary @@ -802,6 +793,27 @@ AC_SUBST([DRI_DIRS]) AC_SUBST([EXPAT_INCLUDES]) AC_SUBST([DRI_LIB_DEPS]) +case $DRI_DIRS in +*i915*|*i965*) + PKG_CHECK_MODULES([INTEL], [libdrm_intel]) + ;; + +*radeon*|*r200*|*r300*|*r600*) + PKG_CHECK_MODULES([LIBDRM_RADEON], + [libdrm_radeon libdrm >= $LIBDRM_RADEON_REQUIRED], + HAVE_LIBDRM_RADEON=yes, + HAVE_LIBDRM_RADEON=no) + + if test "$HAVE_LIBDRM_RADEON" = yes; then + RADEON_CFLAGS="-DHAVE_LIBDRM_RADEON=1 $LIBDRM_RADEON_CFLAGS" + RADEON_LDFLAGS=$LIBDRM_RADEON_LIBS + fi + ;; +esac +AC_SUBST([RADEON_CFLAGS]) +AC_SUBST([RADEON_LDFLAGS]) + + dnl dnl OSMesa configuration dnl diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile index 37f15aa767..788e78654e 100644 --- a/src/mesa/drivers/dri/i915/Makefile +++ b/src/mesa/drivers/dri/i915/Makefile @@ -64,7 +64,8 @@ DRIVER_DEFINES = -I../intel -I../intel/server -DI915 \ $(shell pkg-config libdrm --atleast-version=2.3.1 \ && echo "-DDRM_VBLANK_FLIP=DRM_VBLANK_FLIP") -DRI_LIB_DEPS += -ldrm_intel +INCLUDES += $(INTEL_CFLAGS) +DRI_LIB_DEPS += $(INTEL_LIBS) include ../Makefile.template diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index 7a55333e89..7cdbdc7071 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -96,7 +96,8 @@ ASM_SOURCES = DRIVER_DEFINES = -I../intel -I../intel/server -DRI_LIB_DEPS += -ldrm_intel +INCLUDES += $(INTEL_CFLAGS) +DRI_LIB_DEPS += $(INTEL_LIBS) include ../Makefile.template -- cgit v1.2.3 From d61f07318c8678901b948fdaa8ccdf37aa3203e9 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 17:09:12 -0500 Subject: Remove leftover __DRI{screen,drawable,context}Private references As part of the DRI driver interface rewrite I merged __DRIscreenPrivate and __DRIscreen, and likewise for __DRIdrawablePrivate and __DRIcontextPrivate. I left typedefs in place though, to avoid renaming all the *Private use internal to the driver. That was probably a mistake, and it turns out a one-line find+sed combo can do the mass rename. Better late than never. --- src/egl/drivers/dri/egldri.c | 26 ++++++------ src/gallium/state_trackers/dri/dri_context.c | 14 +++---- src/gallium/state_trackers/dri/dri_context.h | 22 +++++------ src/gallium/state_trackers/dri/dri_drawable.c | 24 +++++------ src/gallium/state_trackers/dri/dri_drawable.h | 18 ++++----- src/gallium/state_trackers/dri/dri_screen.c | 8 ++-- src/gallium/state_trackers/dri/dri_screen.h | 4 +- src/glx/mini/miniglx.c | 12 +++--- src/glx/x11/dri_glx.c | 2 +- src/mesa/drivers/dri/common/dri_util.c | 24 +++++------ src/mesa/drivers/dri/common/dri_util.h | 5 --- src/mesa/drivers/dri/common/drirenderbuffer.c | 4 +- src/mesa/drivers/dri/common/drirenderbuffer.h | 8 ++-- src/mesa/drivers/dri/common/vblank.c | 20 +++++----- src/mesa/drivers/dri/common/vblank.h | 16 ++++---- src/mesa/drivers/dri/fb/fb_dri.c | 36 ++++++++--------- src/mesa/drivers/dri/fb/fb_egl.c | 6 +-- src/mesa/drivers/dri/ffb/ffb_bitmap.c | 2 +- src/mesa/drivers/dri/ffb/ffb_clear.c | 4 +- src/mesa/drivers/dri/ffb/ffb_context.h | 4 +- src/mesa/drivers/dri/ffb/ffb_depth.c | 8 ++-- src/mesa/drivers/dri/ffb/ffb_span.c | 2 +- src/mesa/drivers/dri/ffb/ffb_state.c | 6 +-- src/mesa/drivers/dri/ffb/ffb_stencil.c | 8 ++-- src/mesa/drivers/dri/ffb/ffb_tris.c | 2 +- src/mesa/drivers/dri/ffb/ffb_xmesa.c | 32 +++++++-------- src/mesa/drivers/dri/ffb/ffb_xmesa.h | 2 +- src/mesa/drivers/dri/gamma/gamma_context.c | 4 +- src/mesa/drivers/dri/gamma/gamma_context.h | 12 +++--- src/mesa/drivers/dri/gamma/gamma_lock.c | 4 +- src/mesa/drivers/dri/gamma/gamma_macros.h | 6 +-- src/mesa/drivers/dri/gamma/gamma_screen.c | 4 +- src/mesa/drivers/dri/gamma/gamma_screen.h | 2 +- src/mesa/drivers/dri/gamma/gamma_span.c | 8 ++-- src/mesa/drivers/dri/gamma/gamma_state.c | 4 +- src/mesa/drivers/dri/gamma/gamma_xmesa.c | 28 ++++++------- src/mesa/drivers/dri/i810/i810context.c | 24 +++++------ src/mesa/drivers/dri/i810/i810context.h | 4 +- src/mesa/drivers/dri/i810/i810ioctl.c | 6 +-- src/mesa/drivers/dri/i810/i810ioctl.h | 4 +- src/mesa/drivers/dri/i810/i810screen.c | 10 ++--- src/mesa/drivers/dri/i810/i810screen.h | 16 ++++---- src/mesa/drivers/dri/i810/i810span.c | 4 +- src/mesa/drivers/dri/i810/i810state.c | 2 +- src/mesa/drivers/dri/i915/i830_context.c | 2 +- src/mesa/drivers/dri/i915/i830_context.h | 2 +- src/mesa/drivers/dri/i915/i915_context.c | 2 +- src/mesa/drivers/dri/i915/i915_context.h | 2 +- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 2 +- src/mesa/drivers/dri/intel/intel_blit.c | 2 +- src/mesa/drivers/dri/intel/intel_blit.h | 2 +- src/mesa/drivers/dri/intel/intel_buffers.c | 2 +- src/mesa/drivers/dri/intel/intel_context.c | 22 +++++------ src/mesa/drivers/dri/intel/intel_context.h | 10 ++--- src/mesa/drivers/dri/intel/intel_pixel_read.c | 4 +- src/mesa/drivers/dri/intel/intel_screen.c | 36 ++++++++--------- src/mesa/drivers/dri/intel/intel_screen.h | 14 +++---- src/mesa/drivers/dri/intel/intel_swapbuffers.c | 10 ++--- src/mesa/drivers/dri/intel/intel_swapbuffers.h | 6 +-- src/mesa/drivers/dri/intel/intel_tex_copy.c | 2 +- src/mesa/drivers/dri/mach64/mach64_context.c | 14 +++---- src/mesa/drivers/dri/mach64/mach64_context.h | 18 ++++----- src/mesa/drivers/dri/mach64/mach64_ioctl.c | 4 +- src/mesa/drivers/dri/mach64/mach64_ioctl.h | 2 +- src/mesa/drivers/dri/mach64/mach64_lock.c | 4 +- src/mesa/drivers/dri/mach64/mach64_screen.c | 18 ++++----- src/mesa/drivers/dri/mach64/mach64_screen.h | 2 +- src/mesa/drivers/dri/mach64/mach64_span.c | 8 ++-- src/mesa/drivers/dri/mach64/mach64_state.c | 4 +- src/mesa/drivers/dri/mga/mga_xmesa.c | 32 +++++++-------- src/mesa/drivers/dri/mga/mga_xmesa.h | 2 +- src/mesa/drivers/dri/mga/mgacontext.h | 6 +-- src/mesa/drivers/dri/mga/mgaioctl.c | 6 +-- src/mesa/drivers/dri/mga/mgaioctl.h | 2 +- src/mesa/drivers/dri/mga/mgapixel.c | 4 +- src/mesa/drivers/dri/mga/mgaspan.c | 8 ++-- src/mesa/drivers/dri/mga/mgastate.c | 6 +-- src/mesa/drivers/dri/r128/r128_context.c | 14 +++---- src/mesa/drivers/dri/r128/r128_context.h | 18 ++++----- src/mesa/drivers/dri/r128/r128_ioctl.c | 6 +-- src/mesa/drivers/dri/r128/r128_ioctl.h | 4 +- src/mesa/drivers/dri/r128/r128_lock.c | 4 +- src/mesa/drivers/dri/r128/r128_screen.c | 18 ++++----- src/mesa/drivers/dri/r128/r128_screen.h | 2 +- src/mesa/drivers/dri/r128/r128_span.c | 8 ++-- src/mesa/drivers/dri/r128/r128_state.c | 2 +- src/mesa/drivers/dri/r200/r200_context.c | 6 +-- src/mesa/drivers/dri/r200/r200_context.h | 12 +++--- src/mesa/drivers/dri/r200/r200_ioctl.c | 4 +- src/mesa/drivers/dri/r200/r200_pixel.c | 4 +- src/mesa/drivers/dri/r200/r200_state.c | 4 +- src/mesa/drivers/dri/r300/r300_context.c | 4 +- src/mesa/drivers/dri/r300/r300_context.h | 4 +- src/mesa/drivers/dri/r300/r300_state.c | 6 +-- src/mesa/drivers/dri/r600/r600_context.c | 4 +- src/mesa/drivers/dri/r600/r600_context.h | 2 +- src/mesa/drivers/dri/r600/r700_clear.c | 2 +- src/mesa/drivers/dri/r600/r700_state.c | 4 +- src/mesa/drivers/dri/radeon/radeon_common.c | 24 +++++------ src/mesa/drivers/dri/radeon/radeon_common.h | 8 ++-- .../drivers/dri/radeon/radeon_common_context.c | 14 +++---- .../drivers/dri/radeon/radeon_common_context.h | 22 +++++------ src/mesa/drivers/dri/radeon/radeon_context.c | 4 +- src/mesa/drivers/dri/radeon/radeon_context.h | 2 +- src/mesa/drivers/dri/radeon/radeon_fbo.c | 2 +- src/mesa/drivers/dri/radeon/radeon_ioctl.c | 4 +- src/mesa/drivers/dri/radeon/radeon_lock.c | 6 +-- src/mesa/drivers/dri/radeon/radeon_screen.c | 26 ++++++------ src/mesa/drivers/dri/radeon/radeon_screen.h | 4 +- src/mesa/drivers/dri/radeon/radeon_state.c | 4 +- src/mesa/drivers/dri/savage/savage_init.h | 2 +- src/mesa/drivers/dri/savage/savage_xmesa.c | 46 +++++++++++----------- src/mesa/drivers/dri/savage/savagecontext.h | 6 +-- src/mesa/drivers/dri/savage/savageioctl.c | 4 +- src/mesa/drivers/dri/savage/savageioctl.h | 2 +- src/mesa/drivers/dri/savage/savagespan.c | 4 +- src/mesa/drivers/dri/sis/sis_context.c | 14 +++---- src/mesa/drivers/dri/sis/sis_context.h | 18 ++++----- src/mesa/drivers/dri/sis/sis_lock.c | 4 +- src/mesa/drivers/dri/sis/sis_screen.c | 18 ++++----- src/mesa/drivers/dri/sis/sis_screen.h | 2 +- src/mesa/drivers/dri/sis/sis_span.c | 4 +- src/mesa/drivers/dri/tdfx/tdfx_context.c | 16 ++++---- src/mesa/drivers/dri/tdfx/tdfx_context.h | 20 +++++----- src/mesa/drivers/dri/tdfx/tdfx_lock.c | 8 ++-- src/mesa/drivers/dri/tdfx/tdfx_pixels.c | 4 +- src/mesa/drivers/dri/tdfx/tdfx_render.c | 2 +- src/mesa/drivers/dri/tdfx/tdfx_screen.c | 18 ++++----- src/mesa/drivers/dri/tdfx/tdfx_screen.h | 2 +- src/mesa/drivers/dri/tdfx/tdfx_span.c | 4 +- src/mesa/drivers/dri/tdfx/tdfx_state.c | 2 +- src/mesa/drivers/dri/unichrome/via_context.c | 30 +++++++------- src/mesa/drivers/dri/unichrome/via_context.h | 8 ++-- src/mesa/drivers/dri/unichrome/via_ioctl.c | 14 +++---- src/mesa/drivers/dri/unichrome/via_ioctl.h | 4 +- src/mesa/drivers/dri/unichrome/via_screen.c | 16 ++++---- src/mesa/drivers/dri/unichrome/via_screen.h | 16 ++++---- src/mesa/drivers/dri/unichrome/via_span.c | 4 +- src/mesa/drivers/dri/unichrome/via_state.c | 4 +- 141 files changed, 634 insertions(+), 639 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/egl/drivers/dri/egldri.c b/src/egl/drivers/dri/egldri.c index 9e400be624..ca6821dad0 100644 --- a/src/egl/drivers/dri/egldri.c +++ b/src/egl/drivers/dri/egldri.c @@ -675,13 +675,13 @@ __eglCreateContextWithConfig(__DRInativeDisplay* ndpy, int screen, drm_context_t * hHWContext) { __DRIscreen *pDRIScreen; - __DRIscreenPrivate *psp; + __DRIscreen *psp; pDRIScreen = __eglFindDRIScreen(ndpy, screen); if ( (pDRIScreen == NULL) || (pDRIScreen->private == NULL) ) { return GL_FALSE; } - psp = (__DRIscreenPrivate *) pDRIScreen->private; + psp = (__DRIscreen *) pDRIScreen->private; if (psp->fd) { if (drmCreateContext(psp->fd, hHWContext)) { _eglLog(_EGL_WARNING, "drmCreateContext failed."); @@ -691,14 +691,14 @@ __eglCreateContextWithConfig(__DRInativeDisplay* ndpy, int screen, } #if 0 __DRIscreen *pDRIScreen; - __DRIscreenPrivate *psp; + __DRIscreen *psp; pDRIScreen = __glXFindDRIScreen(dpy, screen); if ( (pDRIScreen == NULL) || (pDRIScreen->private == NULL) ) { return GL_FALSE; } - psp = (__DRIscreenPrivate *) pDRIScreen->private; + psp = (__DRIscreen *) pDRIScreen->private; if (psp->fd) { if (drmCreateContext(psp->fd, hHWContext)) { @@ -716,13 +716,13 @@ static GLboolean __eglDestroyContext( __DRInativeDisplay * ndpy, int screen, __DRIid context ) { __DRIscreen *pDRIScreen; - __DRIscreenPrivate *psp; + __DRIscreen *psp; pDRIScreen = __eglFindDRIScreen(ndpy, screen); if ( (pDRIScreen == NULL) || (pDRIScreen->private == NULL) ) { return GL_FALSE; } - psp = (__DRIscreenPrivate *) pDRIScreen->private; + psp = (__DRIscreen *) pDRIScreen->private; if (psp->fd) drmDestroyContext(psp->fd, context); @@ -735,13 +735,13 @@ __eglCreateDrawable(__DRInativeDisplay * ndpy, int screen, __DRIid drawable, drm_drawable_t * hHWDrawable) { __DRIscreen *pDRIScreen; - __DRIscreenPrivate *psp; + __DRIscreen *psp; pDRIScreen = __eglFindDRIScreen(ndpy, screen); if ( (pDRIScreen == NULL) || (pDRIScreen->private == NULL) ) { return GL_FALSE; } - psp = (__DRIscreenPrivate *) pDRIScreen->private; + psp = (__DRIscreen *) pDRIScreen->private; if (psp->fd) { if (drmCreateDrawable(psp->fd, hHWDrawable)) { _eglLog(_EGL_WARNING, "drmCreateDrawable failed."); @@ -756,13 +756,13 @@ static GLboolean __eglDestroyDrawable( __DRInativeDisplay * ndpy, int screen, __DRIid drawable ) { __DRIscreen *pDRIScreen; - __DRIscreenPrivate *psp; + __DRIscreen *psp; pDRIScreen = __eglFindDRIScreen(ndpy, screen); if ( (pDRIScreen == NULL) || (pDRIScreen->private == NULL) ) { return GL_FALSE; } - psp = (__DRIscreenPrivate *) pDRIScreen->private; + psp = (__DRIscreen *) pDRIScreen->private; if (psp->fd) drmDestroyDrawable(psp->fd, drawable); @@ -778,7 +778,7 @@ __eglGetDrawableInfo(__DRInativeDisplay * ndpy, int screen, __DRIid drawable, int* numBackClipRects, drm_clip_rect_t ** pBackClipRects ) { __DRIscreen *pDRIScreen; - __DRIscreenPrivate *psp; + __DRIscreen *psp; driSurface *surf = Lookup_driSurface((EGLSurface) drawable); pDRIScreen = __eglFindDRIScreen(ndpy, screen); @@ -786,7 +786,7 @@ __eglGetDrawableInfo(__DRInativeDisplay * ndpy, int screen, __DRIid drawable, if ( (pDRIScreen == NULL) || (pDRIScreen->private == NULL) ) { return GL_FALSE; } - psp = (__DRIscreenPrivate *) pDRIScreen->private; + psp = (__DRIscreen *) pDRIScreen->private; *X = 0; *Y = 0; *W = surf->Base.Width; @@ -807,7 +807,7 @@ __eglGetDrawableInfo(__DRInativeDisplay * ndpy, int screen, __DRIid drawable, GLXDrawable drawable = (GLXDrawable) draw; drm_clip_rect_t * cliprect; Display* display = (Display*)dpy; - __DRIcontextPrivate *pcp = (__DRIcontextPrivate *)CurrentContext->driContext.private; + __DRIcontext *pcp = (__DRIcontext *)CurrentContext->driContext.private; if (drawable == 0) { return GL_FALSE; } diff --git a/src/gallium/state_trackers/dri/dri_context.c b/src/gallium/state_trackers/dri/dri_context.c index 8819936fca..f2e5f3fb23 100644 --- a/src/gallium/state_trackers/dri/dri_context.c +++ b/src/gallium/state_trackers/dri/dri_context.c @@ -44,9 +44,9 @@ GLboolean dri_create_context(const __GLcontextModes * visual, - __DRIcontextPrivate * cPriv, void *sharedContextPrivate) + __DRIcontext * cPriv, void *sharedContextPrivate) { - __DRIscreenPrivate *sPriv = cPriv->driScreenPriv; + __DRIscreen *sPriv = cPriv->driScreenPriv; struct dri_screen *screen = dri_screen(sPriv); struct dri_context *ctx = NULL; struct st_context *st_share = NULL; @@ -97,7 +97,7 @@ dri_create_context(const __GLcontextModes * visual, } void -dri_destroy_context(__DRIcontextPrivate * cPriv) +dri_destroy_context(__DRIcontext * cPriv) { struct dri_context *ctx = dri_context(cPriv); @@ -116,7 +116,7 @@ dri_destroy_context(__DRIcontextPrivate * cPriv) } GLboolean -dri_unbind_context(__DRIcontextPrivate * cPriv) +dri_unbind_context(__DRIcontext * cPriv) { if (cPriv) { struct dri_context *ctx = dri_context(cPriv); @@ -133,9 +133,9 @@ dri_unbind_context(__DRIcontextPrivate * cPriv) } GLboolean -dri_make_current(__DRIcontextPrivate * cPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv) +dri_make_current(__DRIcontext * cPriv, + __DRIdrawable * driDrawPriv, + __DRIdrawable * driReadPriv) { if (cPriv) { struct dri_context *ctx = dri_context(cPriv); diff --git a/src/gallium/state_trackers/dri/dri_context.h b/src/gallium/state_trackers/dri/dri_context.h index 4650178734..13f497462f 100644 --- a/src/gallium/state_trackers/dri/dri_context.h +++ b/src/gallium/state_trackers/dri/dri_context.h @@ -44,10 +44,10 @@ struct dri_drawable; struct dri_context { /* dri */ - __DRIscreenPrivate *sPriv; - __DRIcontextPrivate *cPriv; - __DRIdrawablePrivate *dPriv; - __DRIdrawablePrivate *rPriv; + __DRIscreen *sPriv; + __DRIcontext *cPriv; + __DRIdrawable *dPriv; + __DRIdrawable *rPriv; driOptionCache optionCache; @@ -67,7 +67,7 @@ struct dri_context }; static INLINE struct dri_context * -dri_context(__DRIcontextPrivate * driContextPriv) +dri_context(__DRIcontext * driContextPriv) { return (struct dri_context *)driContextPriv->driverPrivate; } @@ -99,18 +99,18 @@ dri_unlock(struct dri_context *ctx) */ extern struct dri1_api_lock_funcs dri1_lf; -void dri_destroy_context(__DRIcontextPrivate * driContextPriv); +void dri_destroy_context(__DRIcontext * driContextPriv); -boolean dri_unbind_context(__DRIcontextPrivate * driContextPriv); +boolean dri_unbind_context(__DRIcontext * driContextPriv); boolean -dri_make_current(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); +dri_make_current(__DRIcontext * driContextPriv, + __DRIdrawable * driDrawPriv, + __DRIdrawable * driReadPriv); boolean dri_create_context(const __GLcontextModes * visual, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); /*********************************************************************** diff --git a/src/gallium/state_trackers/dri/dri_drawable.c b/src/gallium/state_trackers/dri/dri_drawable.c index 4b12243ddf..1058dd38c2 100644 --- a/src/gallium/state_trackers/dri/dri_drawable.c +++ b/src/gallium/state_trackers/dri/dri_drawable.c @@ -118,7 +118,7 @@ dri2_check_if_pixmap(__DRIbuffer *buffers, int count) * This will be called a drawable is known to have been resized. */ void -dri_get_buffers(__DRIdrawablePrivate * dPriv) +dri_get_buffers(__DRIdrawable * dPriv) { struct dri_drawable *drawable = dri_drawable(dPriv); @@ -299,8 +299,8 @@ dri_flush_frontbuffer(struct pipe_screen *screen, * This is called when we need to set up GL rendering to a new X window. */ boolean -dri_create_buffer(__DRIscreenPrivate * sPriv, - __DRIdrawablePrivate * dPriv, +dri_create_buffer(__DRIscreen * sPriv, + __DRIdrawable * dPriv, const __GLcontextModes * visual, boolean isPixmap) { struct dri_screen *screen = sPriv->private; @@ -416,7 +416,7 @@ dri_swap_fences_push_back(struct dri_drawable *draw, } void -dri_destroy_buffer(__DRIdrawablePrivate * dPriv) +dri_destroy_buffer(__DRIdrawable * dPriv) { struct dri_drawable *drawable = dri_drawable(dPriv); struct pipe_fence_handle *fence; @@ -434,8 +434,8 @@ dri_destroy_buffer(__DRIdrawablePrivate * dPriv) static void dri1_update_drawables_locked(struct dri_context *ctx, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv) + __DRIdrawable * driDrawPriv, + __DRIdrawable * driReadPriv) { if (ctx->stLostLock) { ctx->stLostLock = FALSE; @@ -458,8 +458,8 @@ dri1_update_drawables_locked(struct dri_context *ctx, static void dri1_propagate_drawable_change(struct dri_context *ctx) { - __DRIdrawablePrivate *dPriv = ctx->dPriv; - __DRIdrawablePrivate *rPriv = ctx->rPriv; + __DRIdrawable *dPriv = ctx->dPriv; + __DRIdrawable *rPriv = ctx->rPriv; boolean flushed = FALSE; if (dPriv && ctx->d_stamp != dPriv->lastStamp) { @@ -532,7 +532,7 @@ static void dri1_swap_copy(struct dri_context *ctx, struct pipe_surface *dst, struct pipe_surface *src, - __DRIdrawablePrivate * dPriv, const struct drm_clip_rect *bbox) + __DRIdrawable * dPriv, const struct drm_clip_rect *bbox) { struct pipe_context *pipe = ctx->pipe; struct drm_clip_rect clip; @@ -563,7 +563,7 @@ dri1_swap_copy(struct dri_context *ctx, static void dri1_copy_to_front(struct dri_context *ctx, struct pipe_surface *surf, - __DRIdrawablePrivate * dPriv, + __DRIdrawable * dPriv, const struct drm_clip_rect *sub_box, struct pipe_fence_handle **fence) { @@ -636,7 +636,7 @@ dri1_flush_frontbuffer(struct pipe_screen *screen, } void -dri_swap_buffers(__DRIdrawablePrivate * dPriv) +dri_swap_buffers(__DRIdrawable * dPriv) { struct dri_context *ctx; struct pipe_surface *back_surf; @@ -668,7 +668,7 @@ dri_swap_buffers(__DRIdrawablePrivate * dPriv) } void -dri_copy_sub_buffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h) +dri_copy_sub_buffer(__DRIdrawable * dPriv, int x, int y, int w, int h) { struct pipe_screen *screen = dri_screen(dPriv->driScreenPriv)->pipe_screen; struct drm_clip_rect sub_bbox; diff --git a/src/gallium/state_trackers/dri/dri_drawable.h b/src/gallium/state_trackers/dri/dri_drawable.h index b910930db4..80bb5d7f61 100644 --- a/src/gallium/state_trackers/dri/dri_drawable.h +++ b/src/gallium/state_trackers/dri/dri_drawable.h @@ -41,8 +41,8 @@ struct dri_context; struct dri_drawable { /* dri */ - __DRIdrawablePrivate *dPriv; - __DRIscreenPrivate *sPriv; + __DRIdrawable *dPriv; + __DRIscreen *sPriv; unsigned attachments[8]; unsigned num_attachments; @@ -67,7 +67,7 @@ struct dri_drawable }; static INLINE struct dri_drawable * -dri_drawable(__DRIdrawablePrivate * driDrawPriv) +dri_drawable(__DRIdrawable * driDrawPriv) { return (struct dri_drawable *)driDrawPriv->driverPrivate; } @@ -76,22 +76,22 @@ dri_drawable(__DRIdrawablePrivate * driDrawPriv) * dri_drawable.c */ boolean -dri_create_buffer(__DRIscreenPrivate * sPriv, - __DRIdrawablePrivate * dPriv, +dri_create_buffer(__DRIscreen * sPriv, + __DRIdrawable * dPriv, const __GLcontextModes * visual, boolean isPixmap); void dri_flush_frontbuffer(struct pipe_screen *screen, struct pipe_surface *surf, void *context_private); -void dri_swap_buffers(__DRIdrawablePrivate * dPriv); +void dri_swap_buffers(__DRIdrawable * dPriv); void -dri_copy_sub_buffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h); +dri_copy_sub_buffer(__DRIdrawable * dPriv, int x, int y, int w, int h); -void dri_get_buffers(__DRIdrawablePrivate * dPriv); +void dri_get_buffers(__DRIdrawable * dPriv); -void dri_destroy_buffer(__DRIdrawablePrivate * dPriv); +void dri_destroy_buffer(__DRIdrawable * dPriv); void dri2_set_tex_buffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv); diff --git a/src/gallium/state_trackers/dri/dri_screen.c b/src/gallium/state_trackers/dri/dri_screen.c index cb864d45d5..ce79d09901 100644 --- a/src/gallium/state_trackers/dri/dri_screen.c +++ b/src/gallium/state_trackers/dri/dri_screen.c @@ -202,7 +202,7 @@ dri_fill_in_modes(struct dri_screen *screen, * Get information about previous buffer swaps. */ static int -dri_get_swap_info(__DRIdrawablePrivate * dPriv, __DRIswapInfo * sInfo) +dri_get_swap_info(__DRIdrawable * dPriv, __DRIswapInfo * sInfo) { if (dPriv == NULL || dPriv->driverPrivate == NULL || sInfo == NULL) return -1; @@ -220,7 +220,7 @@ dri_copy_version(struct dri1_api_version *dst, } static const __DRIconfig ** -dri_init_screen(__DRIscreenPrivate * sPriv) +dri_init_screen(__DRIscreen * sPriv) { struct dri_screen *screen; const __DRIconfig **configs; @@ -285,7 +285,7 @@ dri_init_screen(__DRIscreenPrivate * sPriv) * Returns the __GLcontextModes supported by this driver. */ static const __DRIconfig ** -dri_init_screen2(__DRIscreenPrivate * sPriv) +dri_init_screen2(__DRIscreen * sPriv) { struct dri_screen *screen; struct drm_create_screen_arg arg; @@ -319,7 +319,7 @@ dri_init_screen2(__DRIscreenPrivate * sPriv) } static void -dri_destroy_screen(__DRIscreenPrivate * sPriv) +dri_destroy_screen(__DRIscreen * sPriv) { struct dri_screen *screen = dri_screen(sPriv); diff --git a/src/gallium/state_trackers/dri/dri_screen.h b/src/gallium/state_trackers/dri/dri_screen.h index f6c56d0f0c..03387a0e81 100644 --- a/src/gallium/state_trackers/dri/dri_screen.h +++ b/src/gallium/state_trackers/dri/dri_screen.h @@ -42,7 +42,7 @@ struct dri_screen { /* dri */ - __DRIscreenPrivate *sPriv; + __DRIscreen *sPriv; /** * Configuration cache with default values for all contexts @@ -63,7 +63,7 @@ struct dri_screen /** cast wrapper */ static INLINE struct dri_screen * -dri_screen(__DRIscreenPrivate * sPriv) +dri_screen(__DRIscreen * sPriv) { return (struct dri_screen *)sPriv->private; } diff --git a/src/glx/mini/miniglx.c b/src/glx/mini/miniglx.c index 874b88bc49..e9a10b4ac7 100644 --- a/src/glx/mini/miniglx.c +++ b/src/glx/mini/miniglx.c @@ -2278,14 +2278,14 @@ __glXCreateContextWithConfig(__DRInativeDisplay *dpy, int screen, int fbconfigID, void *contextID, drm_context_t *hHWContext) { __DRIscreen *pDRIScreen; - __DRIscreenPrivate *psp; + __DRIscreen *psp; pDRIScreen = __glXFindDRIScreen(dpy, screen); if ( (pDRIScreen == NULL) || (pDRIScreen->private == NULL) ) { return GL_FALSE; } - psp = (__DRIscreenPrivate *) pDRIScreen->private; + psp = (__DRIscreen *) pDRIScreen->private; if (psp->fd) { if (drmCreateContext(psp->fd, hHWContext)) { @@ -2310,9 +2310,9 @@ __glXGetDrawableInfo(__DRInativeDisplay *dpy, int scrn, GLXDrawable drawable = (GLXDrawable) draw; drm_clip_rect_t * cliprect; Display* display = (Display*)dpy; - __DRIscreenPrivate *psp = display->driScreen.private; - __DRIcontextPrivate *pcp = (__DRIcontextPrivate *)CurrentContext->driContext.private; - __DRIdrawablePrivate *pdp = pcp->driDrawablePriv; + __DRIscreen *psp = display->driScreen.private; + __DRIcontext *pcp = (__DRIcontext *)CurrentContext->driContext.private; + __DRIdrawable *pdp = pcp->driDrawablePriv; if (drawable == 0) { return GL_FALSE; } @@ -2357,7 +2357,7 @@ xf86DRI_CreateDrawable(__DRInativeDisplay *dpy, int screen, __DRIid drawable, { Display *display = (Display *)dpy; - __DRIscreenPrivate *psp = display->driScreen.private; + __DRIscreen *psp = display->driScreen.private; int ret; ret = drmCreateDrawable(psp->fd, hHWDrawable); diff --git a/src/glx/x11/dri_glx.c b/src/glx/x11/dri_glx.c index 4f7acb6cc3..4ff99b8eda 100644 --- a/src/glx/x11/dri_glx.c +++ b/src/glx/x11/dri_glx.c @@ -292,7 +292,7 @@ static const __DRIextension *loader_extensions[] = { * \param driDpy DRI display information. * \param createNewScreen Pointer to the client-side driver's * \c __driCreateNewScreen function. - * \returns A pointer to the \c __DRIscreenPrivate structure returned by + * \returns A pointer to the \c __DRIscreen structure returned by * the client-side driver on success, or \c NULL on failure. */ static void * diff --git a/src/mesa/drivers/dri/common/dri_util.c b/src/mesa/drivers/dri/common/dri_util.c index 547f18a009..fd0359fac9 100644 --- a/src/mesa/drivers/dri/common/dri_util.c +++ b/src/mesa/drivers/dri/common/dri_util.c @@ -97,7 +97,7 @@ driIntersectArea( drm_clip_rect_t rect1, drm_clip_rect_t rect2 ) * * \internal * This function calls __DriverAPIRec::UnbindContext, and then decrements - * __DRIdrawablePrivateRec::refcount which must be non-zero for a successful + * __DRIdrawableRec::refcount which must be non-zero for a successful * return. * * While casting the opaque private pointers associated with the parameters @@ -167,7 +167,7 @@ static int driBindContext(__DRIcontext *pcp, __DRIdrawable *pdp, __DRIdrawable *prp) { - __DRIscreenPrivate *psp = NULL; + __DRIscreen *psp = NULL; /* Bind the drawable to the context */ @@ -220,7 +220,7 @@ static int driBindContext(__DRIcontext *pcp, * * \param pdp pointer to the private drawable information to update. * - * This function basically updates the __DRIdrawablePrivate struct's + * This function basically updates the __DRIdrawable struct's * cliprect information by calling \c __DRIinterfaceMethods::getDrawableInfo. * This is usually called by the DRI_VALIDATE_DRAWABLE_INFO macro which * compares the __DRIdrwablePrivate pStamp and lastStamp values. If @@ -228,10 +228,10 @@ static int driBindContext(__DRIcontext *pcp, * info. */ void -__driUtilUpdateDrawableInfo(__DRIdrawablePrivate *pdp) +__driUtilUpdateDrawableInfo(__DRIdrawable *pdp) { - __DRIscreenPrivate *psp = pdp->driScreenPriv; - __DRIcontextPrivate *pcp = pdp->driContextPriv; + __DRIscreen *psp = pdp->driScreenPriv; + __DRIcontext *pcp = pdp->driContextPriv; if (!pcp || ((pdp != pcp->driDrawablePriv) && (pdp != pcp->driReadablePriv))) { @@ -309,7 +309,7 @@ static void driReportDamage(__DRIdrawable *pdp, * \param drawablePrivate opaque pointer to the per-drawable private info. * * \internal - * This function calls __DRIdrawablePrivate::swapBuffers. + * This function calls __DRIdrawable::swapBuffers. * * Is called directly from glXSwapBuffers(). */ @@ -497,7 +497,7 @@ static void dri_get_drawable(__DRIdrawable *pdp) static void dri_put_drawable(__DRIdrawable *pdp) { - __DRIscreenPrivate *psp; + __DRIscreen *psp; if (pdp) { pdp->refcount--; @@ -560,7 +560,7 @@ driDestroyContext(__DRIcontext *pcp) * success, or \c NULL on failure. * * \internal - * This function allocates and fills a __DRIcontextPrivateRec structure. It + * This function allocates and fills a __DRIcontextRec structure. It * performs some device independent initialization and passes all the * relevent information to __DriverAPIRec::CreateContext to create the * context. @@ -871,7 +871,7 @@ driQueryFrameTracking(__DRIdrawable *dpriv, __DRIswapInfo sInfo; int status; int64_t ust; - __DRIscreenPrivate *psp = dpriv->driScreenPriv; + __DRIscreen *psp = dpriv->driScreenPriv; status = dpriv->driScreenPriv->DriverAPI.GetSwapInfo( dpriv, & sInfo ); if ( status == 0 ) { @@ -921,14 +921,14 @@ const __DRIframeTrackingExtension driFrameTrackingExtension = { * be possible to cache the sync rate? */ float -driCalculateSwapUsage( __DRIdrawablePrivate *dPriv, int64_t last_swap_ust, +driCalculateSwapUsage( __DRIdrawable *dPriv, int64_t last_swap_ust, int64_t current_ust ) { int32_t n; int32_t d; int interval; float usage = 1.0; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; + __DRIscreen *psp = dPriv->driScreenPriv; if ( (*psp->systemTime->getMSCRate)(dPriv, &n, &d, dPriv->loaderPrivate) ) { interval = (dPriv->swap_interval != 0) ? dPriv->swap_interval : 1; diff --git a/src/mesa/drivers/dri/common/dri_util.h b/src/mesa/drivers/dri/common/dri_util.h index c95a5c8299..984e5e6909 100644 --- a/src/mesa/drivers/dri/common/dri_util.h +++ b/src/mesa/drivers/dri/common/dri_util.h @@ -59,11 +59,6 @@ typedef struct __DRIswapInfoRec __DRIswapInfo; -/* Typedefs to avoid rewriting the world. */ -typedef struct __DRIscreenRec __DRIscreenPrivate; -typedef struct __DRIdrawableRec __DRIdrawablePrivate; -typedef struct __DRIcontextRec __DRIcontextPrivate; - /** * Extensions. */ diff --git a/src/mesa/drivers/dri/common/drirenderbuffer.c b/src/mesa/drivers/dri/common/drirenderbuffer.c index 4e7e92c82b..3126ea8476 100644 --- a/src/mesa/drivers/dri/common/drirenderbuffer.c +++ b/src/mesa/drivers/dri/common/drirenderbuffer.c @@ -56,7 +56,7 @@ driDeleteRenderbuffer(struct gl_renderbuffer *rb) driRenderbuffer * driNewRenderbuffer(gl_format format, GLvoid *addr, GLint cpp, GLint offset, GLint pitch, - __DRIdrawablePrivate *dPriv) + __DRIdrawable *dPriv) { driRenderbuffer *drb; @@ -196,7 +196,7 @@ driFlipRenderbuffers(struct gl_framebuffer *fb, GLboolean flipped) * gl_framebuffer object. */ void -driUpdateFramebufferSize(GLcontext *ctx, const __DRIdrawablePrivate *dPriv) +driUpdateFramebufferSize(GLcontext *ctx, const __DRIdrawable *dPriv) { struct gl_framebuffer *fb = (struct gl_framebuffer *) dPriv->driverPrivate; if (fb && (dPriv->w != fb->Width || dPriv->h != fb->Height)) { diff --git a/src/mesa/drivers/dri/common/drirenderbuffer.h b/src/mesa/drivers/dri/common/drirenderbuffer.h index 3a5cbcdaac..677511334d 100644 --- a/src/mesa/drivers/dri/common/drirenderbuffer.h +++ b/src/mesa/drivers/dri/common/drirenderbuffer.h @@ -43,10 +43,10 @@ typedef struct { GLint flippedPitch; GLvoid *flippedData; /* mmap'd address of buffer memory, if used */ - /* Pointer to corresponding __DRIdrawablePrivate. This is used to compute + /* Pointer to corresponding __DRIdrawable. This is used to compute * the window's position within the framebuffer. */ - __DRIdrawablePrivate *dPriv; + __DRIdrawable *dPriv; /* XXX this is for radeon/r200 only. We should really create a new * r200Renderbuffer class, derived from this class... not a huge deal. @@ -66,14 +66,14 @@ typedef struct { extern driRenderbuffer * driNewRenderbuffer(gl_format format, GLvoid *addr, GLint cpp, GLint offset, GLint pitch, - __DRIdrawablePrivate *dPriv); + __DRIdrawable *dPriv); extern void driFlipRenderbuffers(struct gl_framebuffer *fb, GLboolean flipped); extern void -driUpdateFramebufferSize(GLcontext *ctx, const __DRIdrawablePrivate *dPriv); +driUpdateFramebufferSize(GLcontext *ctx, const __DRIdrawable *dPriv); #endif /* DRIRENDERBUFFER_H */ diff --git a/src/mesa/drivers/dri/common/vblank.c b/src/mesa/drivers/dri/common/vblank.c index 12aeaa108f..49b22a2dc7 100644 --- a/src/mesa/drivers/dri/common/vblank.c +++ b/src/mesa/drivers/dri/common/vblank.c @@ -34,12 +34,12 @@ #include "vblank.h" #include "xmlpool.h" -static unsigned int msc_to_vblank(__DRIdrawablePrivate * dPriv, int64_t msc) +static unsigned int msc_to_vblank(__DRIdrawable * dPriv, int64_t msc) { return (unsigned int)(msc - dPriv->msc_base + dPriv->vblank_base); } -static int64_t vblank_to_msc(__DRIdrawablePrivate * dPriv, unsigned int vblank) +static int64_t vblank_to_msc(__DRIdrawable * dPriv, unsigned int vblank) { return (int64_t)(vblank - dPriv->vblank_base + dPriv->msc_base); } @@ -64,8 +64,8 @@ static int64_t vblank_to_msc(__DRIdrawablePrivate * dPriv, unsigned int vblank) * \return Zero is returned on success. A negative errno value * is returned on failure. */ -int driDrawableGetMSC32( __DRIscreenPrivate * priv, - __DRIdrawablePrivate * dPriv, +int driDrawableGetMSC32( __DRIscreen * priv, + __DRIdrawable * dPriv, int64_t * count) { drmVBlank vbl; @@ -122,7 +122,7 @@ int driDrawableGetMSC32( __DRIscreenPrivate * priv, * \return Zero on success or \c GLX_BAD_CONTEXT on failure. */ -int driWaitForMSC32( __DRIdrawablePrivate *priv, +int driWaitForMSC32( __DRIdrawable *priv, int64_t target_msc, int64_t divisor, int64_t remainder, int64_t * msc ) { @@ -278,7 +278,7 @@ static int do_wait( drmVBlank * vbl, GLuint * vbl_seq, int fd ) */ static unsigned -driGetDefaultVBlankInterval( const __DRIdrawablePrivate *priv ) +driGetDefaultVBlankInterval( const __DRIdrawable *priv ) { if ( (priv->vblFlags & (VBLANK_FLAG_THROTTLE | VBLANK_FLAG_SYNC)) != 0 ) { return 1; @@ -295,7 +295,7 @@ driGetDefaultVBlankInterval( const __DRIdrawablePrivate *priv ) * direct rendering context. */ -void driDrawableInitVBlank( __DRIdrawablePrivate *priv ) +void driDrawableInitVBlank( __DRIdrawable *priv ) { if ( priv->swap_interval == (unsigned)-1 && !( priv->vblFlags & VBLANK_FLAG_NO_IRQ ) ) { @@ -320,7 +320,7 @@ void driDrawableInitVBlank( __DRIdrawablePrivate *priv ) */ unsigned -driGetVBlankInterval( const __DRIdrawablePrivate *priv ) +driGetVBlankInterval( const __DRIdrawable *priv ) { if ( (priv->vblFlags & VBLANK_FLAG_INTERVAL) != 0 ) { /* this must have been initialized when the drawable was first bound @@ -340,7 +340,7 @@ driGetVBlankInterval( const __DRIdrawablePrivate *priv ) */ void -driGetCurrentVBlank( __DRIdrawablePrivate *priv ) +driGetCurrentVBlank( __DRIdrawable *priv ) { drmVBlank vbl; @@ -366,7 +366,7 @@ driGetCurrentVBlank( __DRIdrawablePrivate *priv ) */ int -driWaitForVBlank( __DRIdrawablePrivate *priv, GLboolean * missed_deadline ) +driWaitForVBlank( __DRIdrawable *priv, GLboolean * missed_deadline ) { drmVBlank vbl; unsigned original_seq; diff --git a/src/mesa/drivers/dri/common/vblank.h b/src/mesa/drivers/dri/common/vblank.h index 8b2c761a11..29d1ad8003 100644 --- a/src/mesa/drivers/dri/common/vblank.h +++ b/src/mesa/drivers/dri/common/vblank.h @@ -44,17 +44,17 @@ #define VBLANK_FLAG_SECONDARY (1U << 8) /* Wait for secondary vblank. */ -extern int driGetMSC32( __DRIscreenPrivate * priv, int64_t * count ); -extern int driDrawableGetMSC32( __DRIscreenPrivate * priv, - __DRIdrawablePrivate * drawablePrivate, +extern int driGetMSC32( __DRIscreen * priv, int64_t * count ); +extern int driDrawableGetMSC32( __DRIscreen * priv, + __DRIdrawable * drawablePrivate, int64_t * count); -extern int driWaitForMSC32( __DRIdrawablePrivate *priv, +extern int driWaitForMSC32( __DRIdrawable *priv, int64_t target_msc, int64_t divisor, int64_t remainder, int64_t * msc ); extern GLuint driGetDefaultVBlankFlags( const driOptionCache *optionCache ); -extern void driDrawableInitVBlank ( __DRIdrawablePrivate *priv ); -extern unsigned driGetVBlankInterval( const __DRIdrawablePrivate *priv ); -extern void driGetCurrentVBlank( __DRIdrawablePrivate *priv ); -extern int driWaitForVBlank( __DRIdrawablePrivate *priv, +extern void driDrawableInitVBlank ( __DRIdrawable *priv ); +extern unsigned driGetVBlankInterval( const __DRIdrawable *priv ); +extern void driGetCurrentVBlank( __DRIdrawable *priv ); +extern int driWaitForVBlank( __DRIdrawable *priv, GLboolean * missed_deadline ); #undef usleep diff --git a/src/mesa/drivers/dri/fb/fb_dri.c b/src/mesa/drivers/dri/fb/fb_dri.c index fd869b2fe7..11058b3853 100644 --- a/src/mesa/drivers/dri/fb/fb_dri.c +++ b/src/mesa/drivers/dri/fb/fb_dri.c @@ -64,9 +64,9 @@ typedef struct { GLcontext *glCtx; /* Mesa context */ struct { - __DRIcontextPrivate *context; - __DRIscreenPrivate *screen; - __DRIdrawablePrivate *drawable; /* drawable bound to this ctx */ + __DRIcontext *context; + __DRIscreen *screen; + __DRIdrawable *drawable; /* drawable bound to this ctx */ } dri; } fbContext, *fbContextPtr; @@ -313,14 +313,14 @@ fbSetSpanFunctions(driRenderbuffer *drb, const GLvisual *vis) /* Initialize the driver specific screen private data. */ static GLboolean -fbInitDriver( __DRIscreenPrivate *sPriv ) +fbInitDriver( __DRIscreen *sPriv ) { sPriv->private = NULL; return GL_TRUE; } static void -fbDestroyScreen( __DRIscreenPrivate *sPriv ) +fbDestroyScreen( __DRIscreen *sPriv ) { } @@ -329,7 +329,7 @@ fbDestroyScreen( __DRIscreenPrivate *sPriv ) */ static GLboolean fbCreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate) { fbContextPtr fbmesa; @@ -384,7 +384,7 @@ fbCreateContext( const __GLcontextModes *glVisual, static void -fbDestroyContext( __DRIcontextPrivate *driContextPriv ) +fbDestroyContext( __DRIcontext *driContextPriv ) { GET_CURRENT_CONTEXT(ctx); fbContextPtr fbmesa = (fbContextPtr) driContextPriv->driverPrivate; @@ -415,8 +415,8 @@ fbDestroyContext( __DRIcontextPrivate *driContextPriv ) * data. */ static GLboolean -fbCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +fbCreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -478,7 +478,7 @@ fbCreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -fbDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +fbDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } @@ -488,7 +488,7 @@ fbDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) /* If the backbuffer is on a videocard, this is extraordinarily slow! */ static void -fbSwapBuffers( __DRIdrawablePrivate *dPriv ) +fbSwapBuffers( __DRIdrawable *dPriv ) { struct gl_framebuffer *mesa_framebuffer = (struct gl_framebuffer *)dPriv->driverPrivate; struct gl_renderbuffer * front_renderbuffer = mesa_framebuffer->Attachment[BUFFER_FRONT_LEFT].Renderbuffer; @@ -532,9 +532,9 @@ fbSwapBuffers( __DRIdrawablePrivate *dPriv ) * buffer `b'. */ static GLboolean -fbMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) +fbMakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ) { if ( driContextPriv ) { fbContextPtr newFbCtx = @@ -556,7 +556,7 @@ fbMakeCurrent( __DRIcontextPrivate *driContextPriv, /* Force the context `c' to be unbound from its buffer. */ static GLboolean -fbUnbindContext( __DRIcontextPrivate *driContextPriv ) +fbUnbindContext( __DRIcontext *driContextPriv ) { return GL_TRUE; } @@ -657,7 +657,7 @@ struct DRIDriverRec __driDriver = { }; static __GLcontextModes * -fbFillInModes( __DRIscreenPrivate *psp, +fbFillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { @@ -745,7 +745,7 @@ fbFillInModes( __DRIscreenPrivate *psp, * with the \c __GLcontextModes that the driver can support for windows or * pbuffers. * - * \return A pointer to a \c __DRIscreenPrivate on success, or \c NULL on + * \return A pointer to a \c __DRIscreen on success, or \c NULL on * failure. */ PUBLIC @@ -759,7 +759,7 @@ void * __driCreateNewScreen( __DRInativeDisplay *dpy, int scrn, __DRIscreen *psc int internal_api_version, __GLcontextModes ** driver_modes ) { - __DRIscreenPrivate *psp; + __DRIscreen *psp; static const __DRIversion ddx_expected = { 4, 0, 0 }; static const __DRIversion dri_expected = { 4, 0, 0 }; static const __DRIversion drm_expected = { 1, 5, 0 }; diff --git a/src/mesa/drivers/dri/fb/fb_egl.c b/src/mesa/drivers/dri/fb/fb_egl.c index eb7adf8224..02e44bb8ee 100644 --- a/src/mesa/drivers/dri/fb/fb_egl.c +++ b/src/mesa/drivers/dri/fb/fb_egl.c @@ -84,9 +84,9 @@ typedef struct fb_context _EGLContext Base; /* base class/object */ GLcontext *glCtx; struct { - __DRIcontextPrivate *context; - __DRIscreenPrivate *screen; - __DRIdrawablePrivate *drawable; /* drawable bound to this ctx */ + __DRIcontext *context; + __DRIscreen *screen; + __DRIdrawable *drawable; /* drawable bound to this ctx */ } dri; } fbContext, *fbContextPtr; diff --git a/src/mesa/drivers/dri/ffb/ffb_bitmap.c b/src/mesa/drivers/dri/ffb/ffb_bitmap.c index f89c0412df..611afddfaf 100644 --- a/src/mesa/drivers/dri/ffb/ffb_bitmap.c +++ b/src/mesa/drivers/dri/ffb/ffb_bitmap.c @@ -46,7 +46,7 @@ ffb_bitmap(GLcontext *ctx, GLint px, GLint py, { ffbContextPtr fmesa = FFB_CONTEXT(ctx); ffb_fbcPtr ffb = fmesa->regs; - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; unsigned int ppc, pixel; GLint row, col, row_stride; const GLubyte *src; diff --git a/src/mesa/drivers/dri/ffb/ffb_clear.c b/src/mesa/drivers/dri/ffb/ffb_clear.c index 776fb487f8..dfe60f36f2 100644 --- a/src/mesa/drivers/dri/ffb/ffb_clear.c +++ b/src/mesa/drivers/dri/ffb/ffb_clear.c @@ -123,7 +123,7 @@ CreatorComputePageFillFixups(struct ff_fixups *fixups, } static void -ffb_do_clear(GLcontext *ctx, __DRIdrawablePrivate *dPriv) +ffb_do_clear(GLcontext *ctx, __DRIdrawable *dPriv) { ffbContextPtr fmesa = FFB_CONTEXT(ctx); FFBDRIPtr gDRIPriv = (FFBDRIPtr) fmesa->driScreen->pDevPriv; @@ -252,7 +252,7 @@ ffb_do_clear(GLcontext *ctx, __DRIdrawablePrivate *dPriv) void ffbDDClear(GLcontext *ctx, GLbitfield mask) { ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; unsigned int stcmask = BUFFER_BIT_STENCIL; #ifdef CLEAR_TRACE diff --git a/src/mesa/drivers/dri/ffb/ffb_context.h b/src/mesa/drivers/dri/ffb/ffb_context.h index 77f87d41c3..4d1d53ff59 100644 --- a/src/mesa/drivers/dri/ffb/ffb_context.h +++ b/src/mesa/drivers/dri/ffb/ffb_context.h @@ -273,8 +273,8 @@ do { if ((STATE_MASK) & ~((FMESA)->state_dirty)) { \ unsigned int setupnewinputs; unsigned int new_gl_state; - __DRIdrawablePrivate *driDrawable; - __DRIscreenPrivate *driScreen; + __DRIdrawable *driDrawable; + __DRIscreen *driScreen; ffbScreenPrivate *ffbScreen; ffb_dri_state_t *ffb_sarea; } ffbContextRec, *ffbContextPtr; diff --git a/src/mesa/drivers/dri/ffb/ffb_depth.c b/src/mesa/drivers/dri/ffb/ffb_depth.c index 71f204d21e..5d509ff696 100644 --- a/src/mesa/drivers/dri/ffb/ffb_depth.c +++ b/src/mesa/drivers/dri/ffb/ffb_depth.c @@ -49,7 +49,7 @@ static void FFBWriteDepthSpan( GLcontext *ctx, #endif if (ctx->Depth.Mask) { ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; GLuint *zptr; GLuint i; @@ -110,7 +110,7 @@ static void FFBWriteDepthPixels( GLcontext *ctx, #endif if (ctx->Depth.Mask) { ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; char *zbase; GLuint i; @@ -153,7 +153,7 @@ static void FFBReadDepthSpan( GLcontext *ctx, { GLuint *depth = (GLuint *) values; ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; GLuint *zptr; GLuint i; @@ -194,7 +194,7 @@ static void FFBReadDepthPixels( GLcontext *ctx, { GLuint *depth = (GLuint *) values; ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; char *zbase; GLuint i; diff --git a/src/mesa/drivers/dri/ffb/ffb_span.c b/src/mesa/drivers/dri/ffb/ffb_span.c index 0d3d604095..8ec33a11bc 100644 --- a/src/mesa/drivers/dri/ffb/ffb_span.c +++ b/src/mesa/drivers/dri/ffb/ffb_span.c @@ -45,7 +45,7 @@ UNLOCK_HARDWARE(fmesa); \ #define LOCAL_VARS \ - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; \ + __DRIdrawable *dPriv = fmesa->driDrawable; \ GLuint height = dPriv->h; \ GLuint p; \ char *buf; \ diff --git a/src/mesa/drivers/dri/ffb/ffb_state.c b/src/mesa/drivers/dri/ffb/ffb_state.c index 5eb8f417ff..6f8a46d1fc 100644 --- a/src/mesa/drivers/dri/ffb/ffb_state.c +++ b/src/mesa/drivers/dri/ffb/ffb_state.c @@ -384,7 +384,7 @@ ffbDDStencilOpSeparate(GLcontext *ctx, GLenum face, GLenum fail, static void ffbCalcViewportRegs(GLcontext *ctx) { ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; GLuint xmin, xmax, ymin, ymax, zmin, zmax; unsigned int vcmin, vcmax; @@ -430,7 +430,7 @@ void ffbCalcViewport(GLcontext *ctx) ffbContextPtr fmesa = FFB_CONTEXT(ctx); const GLfloat *v = ctx->Viewport._WindowMap.m; GLfloat *m = fmesa->hw_viewport; - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; m[MAT_SX] = v[MAT_SX]; m[MAT_TX] = v[MAT_TX] + dPriv->x + SUBPIXEL_X; @@ -762,7 +762,7 @@ static void ffbDDLineStipple(GLcontext *ctx, GLint factor, GLushort pattern) void ffbXformAreaPattern(ffbContextPtr fmesa, const GLubyte *mask) { - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; int i, lines, xoff; lines = 0; diff --git a/src/mesa/drivers/dri/ffb/ffb_stencil.c b/src/mesa/drivers/dri/ffb/ffb_stencil.c index 921a83d274..ce8ef43c91 100644 --- a/src/mesa/drivers/dri/ffb/ffb_stencil.c +++ b/src/mesa/drivers/dri/ffb/ffb_stencil.c @@ -48,7 +48,7 @@ static void FFBWriteStencilSpan( GLcontext *ctx, #endif if (ctx->Depth.Mask) { ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; GLuint *zptr; GLuint i; @@ -93,7 +93,7 @@ static void FFBWriteStencilPixels( GLcontext *ctx, #endif if (ctx->Depth.Mask) { ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; char *zbase; GLuint i; @@ -136,7 +136,7 @@ static void FFBReadStencilSpan( GLcontext *ctx, { GLubyte *stencil = (GLubyte *) values; ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; GLuint *zptr; GLuint i; @@ -176,7 +176,7 @@ static void FFBReadStencilPixels( GLcontext *ctx, { GLubyte *stencil = (GLubyte *) values; ffbContextPtr fmesa = FFB_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; + __DRIdrawable *dPriv = fmesa->driDrawable; char *zbase; GLuint i; diff --git a/src/mesa/drivers/dri/ffb/ffb_tris.c b/src/mesa/drivers/dri/ffb/ffb_tris.c index e7dd960ba1..8bf5ae498f 100644 --- a/src/mesa/drivers/dri/ffb/ffb_tris.c +++ b/src/mesa/drivers/dri/ffb/ffb_tris.c @@ -351,7 +351,7 @@ static struct { #define LOCAL_VARS(n) \ ffbContextPtr fmesa = FFB_CONTEXT(ctx); \ - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; \ + __DRIdrawable *dPriv = fmesa->driDrawable; \ ffb_color color[n] = { { 0 } }; \ (void) color; (void) dPriv; diff --git a/src/mesa/drivers/dri/ffb/ffb_xmesa.c b/src/mesa/drivers/dri/ffb/ffb_xmesa.c index 09cc26d09e..ea212e9dbd 100644 --- a/src/mesa/drivers/dri/ffb/ffb_xmesa.c +++ b/src/mesa/drivers/dri/ffb/ffb_xmesa.c @@ -62,7 +62,7 @@ #include "drirenderbuffer.h" static GLboolean -ffbInitDriver(__DRIscreenPrivate *sPriv) +ffbInitDriver(__DRIscreen *sPriv) { ffbScreenPrivate *ffbScreen; FFBDRIPtr gDRIPriv = (FFBDRIPtr) sPriv->pDevPriv; @@ -154,7 +154,7 @@ ffbInitDriver(__DRIscreenPrivate *sPriv) static void -ffbDestroyScreen(__DRIscreenPrivate *sPriv) +ffbDestroyScreen(__DRIscreen *sPriv) { ffbScreenPrivate *ffbScreen = sPriv->private; FFBDRIPtr gDRIPriv = (FFBDRIPtr) sPriv->pDevPriv; @@ -183,12 +183,12 @@ static const struct tnl_pipeline_stage *ffb_pipeline[] = { /* Create and initialize the Mesa and driver specific context data */ static GLboolean ffbCreateContext(const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate) { ffbContextPtr fmesa; GLcontext *ctx, *shareCtx; - __DRIscreenPrivate *sPriv; + __DRIscreen *sPriv; ffbScreenPrivate *ffbScreen; char *debug; struct dd_function_table functions; @@ -306,7 +306,7 @@ ffbCreateContext(const __GLcontextModes *mesaVis, } static void -ffbDestroyContext(__DRIcontextPrivate *driContextPriv) +ffbDestroyContext(__DRIcontext *driContextPriv) { ffbContextPtr fmesa = (ffbContextPtr) driContextPriv->driverPrivate; @@ -328,8 +328,8 @@ ffbDestroyContext(__DRIcontextPrivate *driContextPriv) /* Create and initialize the Mesa and driver specific pixmap buffer data */ static GLboolean -ffbCreateBuffer(__DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +ffbCreateBuffer(__DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -392,7 +392,7 @@ ffbCreateBuffer(__DRIscreenPrivate *driScrnPriv, static void -ffbDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +ffbDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } @@ -401,7 +401,7 @@ ffbDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) #define USE_FAST_SWAP static void -ffbSwapBuffers( __DRIdrawablePrivate *dPriv ) +ffbSwapBuffers( __DRIdrawable *dPriv ) { ffbContextPtr fmesa = (ffbContextPtr) dPriv->driContextPriv->driverPrivate; unsigned int fbc, wid, wid_reg_val, dac_db_bit; @@ -532,9 +532,9 @@ static void ffb_init_wid(ffbContextPtr fmesa, unsigned int wid) /* Force the context `c' to be the current context and associate with it buffer `b' */ static GLboolean -ffbMakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv) +ffbMakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv) { if (driContextPriv) { ffbContextPtr fmesa = (ffbContextPtr) driContextPriv->driverPrivate; @@ -581,15 +581,15 @@ ffbMakeCurrent(__DRIcontextPrivate *driContextPriv, /* Force the context `c' to be unbound from its buffer */ static GLboolean -ffbUnbindContext(__DRIcontextPrivate *driContextPriv) +ffbUnbindContext(__DRIcontext *driContextPriv) { return GL_TRUE; } void ffbXMesaUpdateState(ffbContextPtr fmesa) { - __DRIdrawablePrivate *dPriv = fmesa->driDrawable; - __DRIscreenPrivate *sPriv = fmesa->driScreen; + __DRIdrawable *dPriv = fmesa->driDrawable; + __DRIscreen *sPriv = fmesa->driScreen; int stamp = dPriv->lastStamp; DRI_VALIDATE_DRAWABLE_INFO(sPriv, dPriv); @@ -607,7 +607,7 @@ void ffbXMesaUpdateState(ffbContextPtr fmesa) } static const __DRIconfig ** -ffbFillInModes( __DRIscreenPrivate *psp, +ffbFillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { diff --git a/src/mesa/drivers/dri/ffb/ffb_xmesa.h b/src/mesa/drivers/dri/ffb/ffb_xmesa.h index 255da4c5f8..2b1740d221 100644 --- a/src/mesa/drivers/dri/ffb/ffb_xmesa.h +++ b/src/mesa/drivers/dri/ffb/ffb_xmesa.h @@ -11,7 +11,7 @@ #include "ffb_fifo.h" typedef struct { - __DRIscreenPrivate *sPriv; + __DRIscreen *sPriv; ffb_fbcPtr regs; ffb_dacPtr dac; volatile char *sfb8r; diff --git a/src/mesa/drivers/dri/gamma/gamma_context.c b/src/mesa/drivers/dri/gamma/gamma_context.c index b0ac299daa..bab5b69a8e 100644 --- a/src/mesa/drivers/dri/gamma/gamma_context.c +++ b/src/mesa/drivers/dri/gamma/gamma_context.c @@ -68,11 +68,11 @@ static const struct tnl_pipeline_stage *gamma_pipeline[] = { }; GLboolean gammaCreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate) { GLcontext *ctx, *shareCtx; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; gammaContextPtr gmesa; gammaScreenPtr gammascrn; GLINTSAREADRIPtr saPriv=(GLINTSAREADRIPtr)(((char*)sPriv->pSAREA)+ diff --git a/src/mesa/drivers/dri/gamma/gamma_context.h b/src/mesa/drivers/dri/gamma/gamma_context.h index a32ccb6007..c386aa3007 100644 --- a/src/mesa/drivers/dri/gamma/gamma_context.h +++ b/src/mesa/drivers/dri/gamma/gamma_context.h @@ -58,10 +58,10 @@ typedef union { #define MAX_TEXTURE_STACK 2 extern void gammaDDUpdateHWState(GLcontext *ctx); -extern gammaScreenPtr gammaCreateScreen(__DRIscreenPrivate *sPriv); -extern void gammaDestroyScreen(__DRIscreenPrivate *sPriv); +extern gammaScreenPtr gammaCreateScreen(__DRIscreen *sPriv); +extern void gammaDestroyScreen(__DRIscreen *sPriv); extern GLboolean gammaCreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate); #define GAMMA_UPLOAD_ALL 0xffffffff @@ -230,9 +230,9 @@ typedef void (*gamma_point_func)( gammaContextPtr, struct gamma_context { GLcontext *glCtx; /* Mesa context */ - __DRIcontextPrivate *driContext; - __DRIscreenPrivate *driScreen; - __DRIdrawablePrivate *driDrawable; + __DRIcontext *driContext; + __DRIscreen *driScreen; + __DRIdrawable *driDrawable; GLuint new_gl_state; GLuint new_state; diff --git a/src/mesa/drivers/dri/gamma/gamma_lock.c b/src/mesa/drivers/dri/gamma/gamma_lock.c index 8f2d01688c..cd4acef24d 100644 --- a/src/mesa/drivers/dri/gamma/gamma_lock.c +++ b/src/mesa/drivers/dri/gamma/gamma_lock.c @@ -19,8 +19,8 @@ int prevLockLine = 0; */ void gammaGetLock( gammaContextPtr gmesa, GLuint flags ) { - __DRIdrawablePrivate *dPriv = gmesa->driDrawable; - __DRIscreenPrivate *sPriv = gmesa->driScreen; + __DRIdrawable *dPriv = gmesa->driDrawable; + __DRIscreen *sPriv = gmesa->driScreen; drmGetLock( gmesa->driFd, gmesa->hHWContext, flags ); diff --git a/src/mesa/drivers/dri/gamma/gamma_macros.h b/src/mesa/drivers/dri/gamma/gamma_macros.h index c15483b770..d962dcdb56 100644 --- a/src/mesa/drivers/dri/gamma/gamma_macros.h +++ b/src/mesa/drivers/dri/gamma/gamma_macros.h @@ -245,8 +245,8 @@ do { \ #ifdef DO_VALIDATE #define VALIDATE_DRAWABLE_INFO_NO_LOCK(gcp) \ do { \ - /*__DRIscreenPrivate *psp = gcp->driScreen;*/ \ - __DRIdrawablePrivate *pdp = gcp->driDrawable; \ + /*__DRIscreen *psp = gcp->driScreen;*/ \ + __DRIdrawable *pdp = gcp->driDrawable; \ \ if (*(pdp->pStamp) != pdp->lastStamp) { \ int old_index = pdp->index; \ @@ -301,7 +301,7 @@ do { \ #define VALIDATE_DRAWABLE_INFO(gcp) \ do { \ - __DRIscreenPrivate *psp = gcp->driScreen; \ + __DRIscreen *psp = gcp->driScreen; \ if (gcp->driDrawable) { \ DRM_SPINLOCK(&psp->pSAREA->drawable_lock, psp->drawLockID); \ VALIDATE_DRAWABLE_INFO_NO_LOCK(gcp); \ diff --git a/src/mesa/drivers/dri/gamma/gamma_screen.c b/src/mesa/drivers/dri/gamma/gamma_screen.c index f899ebec96..f72a4a5696 100644 --- a/src/mesa/drivers/dri/gamma/gamma_screen.c +++ b/src/mesa/drivers/dri/gamma/gamma_screen.c @@ -29,7 +29,7 @@ #include "main/imports.h" -gammaScreenPtr gammaCreateScreen( __DRIscreenPrivate *sPriv ) +gammaScreenPtr gammaCreateScreen( __DRIscreen *sPriv ) { gammaScreenPtr gammaScreen; GLINTDRIPtr gDRIPriv = (GLINTDRIPtr)sPriv->pDevPriv; @@ -129,7 +129,7 @@ gammaScreenPtr gammaCreateScreen( __DRIscreenPrivate *sPriv ) /* Destroy the device specific screen private data struct. */ -void gammaDestroyScreen( __DRIscreenPrivate *sPriv ) +void gammaDestroyScreen( __DRIscreen *sPriv ) { gammaScreenPtr gammaScreen = (gammaScreenPtr)sPriv->private; diff --git a/src/mesa/drivers/dri/gamma/gamma_screen.h b/src/mesa/drivers/dri/gamma/gamma_screen.h index 7f0ed6f80e..c716ea89c2 100644 --- a/src/mesa/drivers/dri/gamma/gamma_screen.h +++ b/src/mesa/drivers/dri/gamma/gamma_screen.h @@ -11,7 +11,7 @@ typedef struct { drmBufMapPtr bufs; /* Map of DMA buffers */ - __DRIscreenPrivate *driScreen; /* Back pointer to DRI screen */ + __DRIscreen *driScreen; /* Back pointer to DRI screen */ int cpp; int frontPitch; diff --git a/src/mesa/drivers/dri/gamma/gamma_span.c b/src/mesa/drivers/dri/gamma/gamma_span.c index cdaaac3f3a..3f0b81800c 100644 --- a/src/mesa/drivers/dri/gamma/gamma_span.c +++ b/src/mesa/drivers/dri/gamma/gamma_span.c @@ -10,8 +10,8 @@ #define LOCAL_VARS \ gammaContextPtr gmesa = GAMMA_CONTEXT(ctx); \ gammaScreenPtr gammascrn = gmesa->gammaScreen; \ - __DRIscreenPrivate *sPriv = gmesa->driScreen; \ - __DRIdrawablePrivate *dPriv = gmesa->driDrawable; \ + __DRIscreen *sPriv = gmesa->driScreen; \ + __DRIdrawable *dPriv = gmesa->driDrawable; \ GLuint pitch = sPriv->fbWidth * gammascrn->cpp; \ GLuint height = dPriv->h; \ char *buf = (char *)(sPriv->pFB + \ @@ -24,8 +24,8 @@ /* FIXME! Depth/Stencil read/writes don't work ! */ #define LOCAL_DEPTH_VARS \ gammaScreenPtr gammascrn = gmesa->gammaScreen; \ - __DRIdrawablePrivate *dPriv = gmesa->driDrawable; \ - __DRIscreenPrivate *sPriv = gmesa->driScreen; \ + __DRIdrawable *dPriv = gmesa->driDrawable; \ + __DRIscreen *sPriv = gmesa->driScreen; \ GLuint pitch = gammascrn->depthPitch; \ GLuint height = dPriv->h; \ char *buf = (char *)(sPriv->pFB + \ diff --git a/src/mesa/drivers/dri/gamma/gamma_state.c b/src/mesa/drivers/dri/gamma/gamma_state.c index bdd1c86ab7..47df37466d 100644 --- a/src/mesa/drivers/dri/gamma/gamma_state.c +++ b/src/mesa/drivers/dri/gamma/gamma_state.c @@ -1070,7 +1070,7 @@ static void gammaDDReadBuffer( GLcontext *ctx, GLenum mode ) void gammaUpdateWindow( GLcontext *ctx ) { gammaContextPtr gmesa = GAMMA_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = gmesa->driDrawable; + __DRIdrawable *dPriv = gmesa->driDrawable; GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = gmesa->driScreen->fbHeight - (GLfloat)dPriv->y - dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1109,7 +1109,7 @@ static void gammaDDDepthRange( GLcontext *ctx, GLclampd nearval, void gammaUpdateViewportOffset( GLcontext *ctx ) { gammaContextPtr gmesa = GAMMA_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = gmesa->driDrawable; + __DRIdrawable *dPriv = gmesa->driDrawable; GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = gmesa->driScreen->fbHeight - (GLfloat)dPriv->y - dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; diff --git a/src/mesa/drivers/dri/gamma/gamma_xmesa.c b/src/mesa/drivers/dri/gamma/gamma_xmesa.c index 7b5b53589c..3492f5cb0f 100644 --- a/src/mesa/drivers/dri/gamma/gamma_xmesa.c +++ b/src/mesa/drivers/dri/gamma/gamma_xmesa.c @@ -36,7 +36,7 @@ #include "vbo/vbo.h" static GLboolean -gammaInitDriver(__DRIscreenPrivate *sPriv) +gammaInitDriver(__DRIscreen *sPriv) { sPriv->private = (void *) gammaCreateScreen( sPriv ); @@ -49,7 +49,7 @@ gammaInitDriver(__DRIscreenPrivate *sPriv) } static void -gammaDestroyContext(__DRIcontextPrivate *driContextPriv) +gammaDestroyContext(__DRIcontext *driContextPriv) { gammaContextPtr gmesa = (gammaContextPtr)driContextPriv->driverPrivate; @@ -72,8 +72,8 @@ gammaDestroyContext(__DRIcontextPrivate *driContextPriv) static GLboolean -gammaCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +gammaCreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -94,17 +94,17 @@ gammaCreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -gammaDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +gammaDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } static void -gammaSwapBuffers( __DRIdrawablePrivate *dPriv ) +gammaSwapBuffers( __DRIdrawable *dPriv ) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { gammaContextPtr gmesa; - __DRIscreenPrivate *driScrnPriv; + __DRIscreen *driScrnPriv; GLcontext *ctx; gmesa = (gammaContextPtr) dPriv->driContextPriv->driverPrivate; @@ -127,7 +127,7 @@ gammaSwapBuffers( __DRIdrawablePrivate *dPriv ) int i; int nRect = dPriv->numClipRects; drm_clip_rect_t *pRect = dPriv->pClipRects; - __DRIscreenPrivate *driScrnPriv = gmesa->driScreen; + __DRIscreen *driScrnPriv = gmesa->driScreen; GLINTDRIPtr gDRIPriv = (GLINTDRIPtr)driScrnPriv->pDevPriv; CHECK_DMA_BUFFER(gmesa, 2); @@ -193,9 +193,9 @@ gammaSwapBuffers( __DRIdrawablePrivate *dPriv ) } static GLboolean -gammaMakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv) +gammaMakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv) { if (driContextPriv) { GET_CURRENT_CONTEXT(ctx); @@ -232,7 +232,7 @@ newGammaCtx->new_state |= GAMMA_NEW_WINDOW; /* FIXME */ static GLboolean -gammaUnbindContext( __DRIcontextPrivate *driContextPriv ) +gammaUnbindContext( __DRIcontext *driContextPriv ) { return GL_TRUE; } @@ -254,12 +254,12 @@ const struct __DriverAPIRec driDriverAPI = { /* * This is the bootstrap function for the driver. * The __driCreateScreen name is the symbol that libGL.so fetches. - * Return: pointer to a __DRIscreenPrivate. + * Return: pointer to a __DRIscreen. */ void *__driCreateScreen(Display *dpy, int scrn, __DRIscreen *psc, int numConfigs, __GLXvisualConfig *config) { - __DRIscreenPrivate *psp; + __DRIscreen *psp; psp = __driUtilCreateScreen(dpy, scrn, psc, numConfigs, config, &gammaAPI); return (void *) psp; } diff --git a/src/mesa/drivers/dri/i810/i810context.c b/src/mesa/drivers/dri/i810/i810context.c index 7311b2e765..bd9cfe5c0f 100644 --- a/src/mesa/drivers/dri/i810/i810context.c +++ b/src/mesa/drivers/dri/i810/i810context.c @@ -170,12 +170,12 @@ static const struct dri_debug_control debug_control[] = GLboolean i810CreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ) { GLcontext *ctx, *shareCtx; i810ContextPtr imesa; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; i810ScreenPrivate *i810Screen = (i810ScreenPrivate *)sPriv->private; I810SAREAPtr saPriv = (I810SAREAPtr) (((GLubyte *)sPriv->pSAREA) + i810Screen->sarea_priv_offset); @@ -337,7 +337,7 @@ i810CreateContext( const __GLcontextModes *mesaVis, } void -i810DestroyContext(__DRIcontextPrivate *driContextPriv) +i810DestroyContext(__DRIcontext *driContextPriv) { i810ContextPtr imesa = (i810ContextPtr) driContextPriv->driverPrivate; @@ -378,7 +378,7 @@ i810DestroyContext(__DRIcontextPrivate *driContextPriv) void i810XMesaSetFrontClipRects( i810ContextPtr imesa ) { - __DRIdrawablePrivate *dPriv = imesa->driDrawable; + __DRIdrawable *dPriv = imesa->driDrawable; imesa->numClipRects = dPriv->numClipRects; imesa->pClipRects = dPriv->pClipRects; @@ -392,7 +392,7 @@ void i810XMesaSetFrontClipRects( i810ContextPtr imesa ) void i810XMesaSetBackClipRects( i810ContextPtr imesa ) { - __DRIdrawablePrivate *dPriv = imesa->driDrawable; + __DRIdrawable *dPriv = imesa->driDrawable; if (imesa->sarea->pf_enabled == 0 && dPriv->numBackClipRects == 0) { @@ -430,7 +430,7 @@ static void i810XMesaWindowMoved( i810ContextPtr imesa ) GLboolean -i810UnbindContext(__DRIcontextPrivate *driContextPriv) +i810UnbindContext(__DRIcontext *driContextPriv) { i810ContextPtr imesa = (i810ContextPtr) driContextPriv->driverPrivate; if (imesa) { @@ -444,9 +444,9 @@ i810UnbindContext(__DRIcontextPrivate *driContextPriv) GLboolean -i810MakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv) +i810MakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv) { if (driContextPriv) { i810ContextPtr imesa = (i810ContextPtr) driContextPriv->driverPrivate; @@ -504,8 +504,8 @@ i810UpdatePageFlipping( i810ContextPtr imesa ) void i810GetLock( i810ContextPtr imesa, GLuint flags ) { - __DRIdrawablePrivate *dPriv = imesa->driDrawable; - __DRIscreenPrivate *sPriv = imesa->driScreen; + __DRIdrawable *dPriv = imesa->driDrawable; + __DRIscreen *sPriv = imesa->driScreen; I810SAREAPtr sarea = imesa->sarea; int me = imesa->hHWContext; unsigned i; @@ -551,7 +551,7 @@ void i810GetLock( i810ContextPtr imesa, GLuint flags ) void -i810SwapBuffers( __DRIdrawablePrivate *dPriv ) +i810SwapBuffers( __DRIdrawable *dPriv ) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { i810ContextPtr imesa; diff --git a/src/mesa/drivers/dri/i810/i810context.h b/src/mesa/drivers/dri/i810/i810context.h index 4b8c71d7c6..19529db020 100644 --- a/src/mesa/drivers/dri/i810/i810context.h +++ b/src/mesa/drivers/dri/i810/i810context.h @@ -170,8 +170,8 @@ struct i810_context_t { drm_hw_lock_t *driHwLock; int driFd; - __DRIdrawablePrivate *driDrawable; - __DRIscreenPrivate *driScreen; + __DRIdrawable *driDrawable; + __DRIscreen *driScreen; i810ScreenPrivate *i810Screen; I810SAREAPtr sarea; }; diff --git a/src/mesa/drivers/dri/i810/i810ioctl.c b/src/mesa/drivers/dri/i810/i810ioctl.c index 3df9c2ac47..623d50c5cb 100644 --- a/src/mesa/drivers/dri/i810/i810ioctl.c +++ b/src/mesa/drivers/dri/i810/i810ioctl.c @@ -50,7 +50,7 @@ static drmBufPtr i810_get_buffer_ioctl( i810ContextPtr imesa ) static void i810Clear( GLcontext *ctx, GLbitfield mask ) { i810ContextPtr imesa = I810_CONTEXT( ctx ); - __DRIdrawablePrivate *dPriv = imesa->driDrawable; + __DRIdrawable *dPriv = imesa->driDrawable; const GLuint colorMask = *((GLuint *) &ctx->Color.ColorMask); drmI810Clear clear; unsigned int i; @@ -149,7 +149,7 @@ static void i810Clear( GLcontext *ctx, GLbitfield mask ) /* * Copy the back buffer to the front buffer. */ -void i810CopyBuffer( const __DRIdrawablePrivate *dPriv ) +void i810CopyBuffer( const __DRIdrawable *dPriv ) { i810ContextPtr imesa; drm_clip_rect_t *pbox; @@ -197,7 +197,7 @@ void i810CopyBuffer( const __DRIdrawablePrivate *dPriv ) /* * XXX implement when full-screen extension is done. */ -void i810PageFlip( const __DRIdrawablePrivate *dPriv ) +void i810PageFlip( const __DRIdrawable *dPriv ) { i810ContextPtr imesa; int tmp, ret; diff --git a/src/mesa/drivers/dri/i810/i810ioctl.h b/src/mesa/drivers/dri/i810/i810ioctl.h index dfd6e21088..926e38ce51 100644 --- a/src/mesa/drivers/dri/i810/i810ioctl.h +++ b/src/mesa/drivers/dri/i810/i810ioctl.h @@ -14,8 +14,8 @@ void i810WaitAge( i810ContextPtr imesa, int age ); void i810DmaFinish( i810ContextPtr imesa ); void i810RegetLockQuiescent( i810ContextPtr imesa ); void i810InitIoctlFuncs( struct dd_function_table *functions ); -void i810CopyBuffer( const __DRIdrawablePrivate *dpriv ); -void i810PageFlip( const __DRIdrawablePrivate *dpriv ); +void i810CopyBuffer( const __DRIdrawable *dpriv ); +void i810PageFlip( const __DRIdrawable *dpriv ); int i810_check_copy(int fd); #define I810_STATECHANGE(imesa, flag) \ diff --git a/src/mesa/drivers/dri/i810/i810screen.c b/src/mesa/drivers/dri/i810/i810screen.c index 2f6b8631ff..09da4700c7 100644 --- a/src/mesa/drivers/dri/i810/i810screen.c +++ b/src/mesa/drivers/dri/i810/i810screen.c @@ -54,7 +54,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include "GL/internal/dri_interface.h" static const __DRIconfig ** -i810FillInModes( __DRIscreenPrivate *psp, +i810FillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { @@ -255,7 +255,7 @@ i810InitScreen(__DRIscreen *sPriv) } static void -i810DestroyScreen(__DRIscreenPrivate *sPriv) +i810DestroyScreen(__DRIscreen *sPriv) { i810ScreenPrivate *i810Screen = (i810ScreenPrivate *)sPriv->private; @@ -274,8 +274,8 @@ i810DestroyScreen(__DRIscreenPrivate *sPriv) * Create a buffer which corresponds to the window. */ static GLboolean -i810CreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +i810CreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -335,7 +335,7 @@ i810CreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -i810DestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +i810DestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } diff --git a/src/mesa/drivers/dri/i810/i810screen.h b/src/mesa/drivers/dri/i810/i810screen.h index b29937665a..734e2fb002 100644 --- a/src/mesa/drivers/dri/i810/i810screen.h +++ b/src/mesa/drivers/dri/i810/i810screen.h @@ -71,7 +71,7 @@ typedef struct { int textureSize; int logTextureGranularity; - __DRIscreenPrivate *driScrnPriv; + __DRIscreen *driScrnPriv; drmBufMapPtr bufs; unsigned int sarea_priv_offset; } i810ScreenPrivate; @@ -79,21 +79,21 @@ typedef struct { extern GLboolean i810CreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ); extern void -i810DestroyContext(__DRIcontextPrivate *driContextPriv); +i810DestroyContext(__DRIcontext *driContextPriv); extern GLboolean -i810UnbindContext(__DRIcontextPrivate *driContextPriv); +i810UnbindContext(__DRIcontext *driContextPriv); extern GLboolean -i810MakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv); +i810MakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv); extern void -i810SwapBuffers(__DRIdrawablePrivate *driDrawPriv); +i810SwapBuffers(__DRIdrawable *driDrawPriv); #endif diff --git a/src/mesa/drivers/dri/i810/i810span.c b/src/mesa/drivers/dri/i810/i810span.c index 510723f445..6576f6745e 100644 --- a/src/mesa/drivers/dri/i810/i810span.c +++ b/src/mesa/drivers/dri/i810/i810span.c @@ -15,7 +15,7 @@ #define LOCAL_VARS \ i810ContextPtr imesa = I810_CONTEXT(ctx); \ - __DRIdrawablePrivate *dPriv = imesa->driDrawable; \ + __DRIdrawable *dPriv = imesa->driDrawable; \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ GLuint pitch = drb->pitch; \ GLuint height = dPriv->h; \ @@ -27,7 +27,7 @@ #define LOCAL_DEPTH_VARS \ i810ContextPtr imesa = I810_CONTEXT(ctx); \ - __DRIdrawablePrivate *dPriv = imesa->driDrawable; \ + __DRIdrawable *dPriv = imesa->driDrawable; \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ GLuint pitch = drb->pitch; \ GLuint height = dPriv->h; \ diff --git a/src/mesa/drivers/dri/i810/i810state.c b/src/mesa/drivers/dri/i810/i810state.c index 1e7a6cfe47..642245c61c 100644 --- a/src/mesa/drivers/dri/i810/i810state.c +++ b/src/mesa/drivers/dri/i810/i810state.c @@ -641,7 +641,7 @@ static void i810Enable(GLcontext *ctx, GLenum cap, GLboolean state) void i810EmitDrawingRectangle( i810ContextPtr imesa ) { - __DRIdrawablePrivate *dPriv = imesa->driDrawable; + __DRIdrawable *dPriv = imesa->driDrawable; i810ScreenPrivate *i810Screen = imesa->i810Screen; int x0 = imesa->drawX; int y0 = imesa->drawY; diff --git a/src/mesa/drivers/dri/i915/i830_context.c b/src/mesa/drivers/dri/i915/i830_context.c index 840946f908..4cb6305988 100644 --- a/src/mesa/drivers/dri/i915/i830_context.c +++ b/src/mesa/drivers/dri/i915/i830_context.c @@ -53,7 +53,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[]; GLboolean i830CreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate) { struct dd_function_table functions; diff --git a/src/mesa/drivers/dri/i915/i830_context.h b/src/mesa/drivers/dri/i915/i830_context.h index f73cbbf88b..592ae53976 100644 --- a/src/mesa/drivers/dri/i915/i830_context.h +++ b/src/mesa/drivers/dri/i915/i830_context.h @@ -178,7 +178,7 @@ i830_state_draw_region(struct intel_context *intel, */ extern GLboolean i830CreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); /* i830_tex.c, i830_texstate.c diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c index 0485be2cc1..7c7711da09 100644 --- a/src/mesa/drivers/dri/i915/i915_context.c +++ b/src/mesa/drivers/dri/i915/i915_context.c @@ -100,7 +100,7 @@ extern const struct tnl_pipeline_stage *intel_pipeline[]; GLboolean i915CreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate) { struct dd_function_table functions; diff --git a/src/mesa/drivers/dri/i915/i915_context.h b/src/mesa/drivers/dri/i915/i915_context.h index 25418d5f7a..f55b551139 100644 --- a/src/mesa/drivers/dri/i915/i915_context.h +++ b/src/mesa/drivers/dri/i915/i915_context.h @@ -318,7 +318,7 @@ do { \ * i915_context.c */ extern GLboolean i915CreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index d8af2c512b..7bb15956b5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -77,7 +77,7 @@ static void brwInitDriverFunctions( struct dd_function_table *functions ) } GLboolean brwCreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate) { struct dd_function_table functions; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index ea5503e2fe..0dd3087143 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -679,7 +679,7 @@ void brwInitVtbl( struct brw_context *brw ); * brw_context.c */ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate); /*====================================================================== diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index d437b1e030..2155feec84 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -330,7 +330,7 @@ const struct brw_tracked_state brw_polygon_stipple = { static void upload_polygon_stipple_offset(struct brw_context *brw) { - __DRIdrawablePrivate *dPriv = brw->intel.driDrawable; + __DRIdrawable *dPriv = brw->intel.driDrawable; struct brw_polygon_stipple_offset bpso; memset(&bpso, 0, sizeof(bpso)); diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index da9beba030..4b83e1d22d 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -47,7 +47,7 @@ * Used for SwapBuffers(). */ void -intelCopyBuffer(const __DRIdrawablePrivate * dPriv, +intelCopyBuffer(const __DRIdrawable * dPriv, const drm_clip_rect_t * rect) { diff --git a/src/mesa/drivers/dri/intel/intel_blit.h b/src/mesa/drivers/dri/intel/intel_blit.h index 240cb7cd1b..eb66fe0481 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.h +++ b/src/mesa/drivers/dri/intel/intel_blit.h @@ -30,7 +30,7 @@ #include "intel_context.h" -extern void intelCopyBuffer(const __DRIdrawablePrivate * dpriv, +extern void intelCopyBuffer(const __DRIdrawable * dpriv, const drm_clip_rect_t * rect); extern void intelClearWithBlit(GLcontext * ctx, GLbitfield mask); diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index 97d56e4e67..219b3603f7 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -102,7 +102,7 @@ intel_get_cliprects(struct intel_context *intel, unsigned int *num_cliprects, int *x_off, int *y_off) { - __DRIdrawablePrivate *dPriv = intel->driDrawable; + __DRIdrawable *dPriv = intel->driDrawable; if (intel->constant_cliprect) { /* FBO or DRI2 rendering, which can just use the fb's size. */ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index eccba5bd23..5ed09f14ca 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -590,13 +590,13 @@ intelInitDriverFunctions(struct dd_function_table *functions) GLboolean intelInitContext(struct intel_context *intel, const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate, struct dd_function_table *functions) { GLcontext *ctx = &intel->ctx; GLcontext *shareCtx = (GLcontext *) sharedContextPrivate; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; int bo_reuse_mode; @@ -801,7 +801,7 @@ intelInitContext(struct intel_context *intel, } void -intelDestroyContext(__DRIcontextPrivate * driContextPriv) +intelDestroyContext(__DRIcontext * driContextPriv) { struct intel_context *intel = (struct intel_context *) driContextPriv->driverPrivate; @@ -857,7 +857,7 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv) * to avoid many layers of "if" constructs. */ do { - __DRIdrawablePrivate * driDrawPriv = intel->driDrawable; + __DRIdrawable * driDrawPriv = intel->driDrawable; struct intel_framebuffer *intel_fb; struct intel_renderbuffer *irbDepth, *irbStencil; if (!driDrawPriv) { @@ -910,7 +910,7 @@ intelDestroyContext(__DRIcontextPrivate * driContextPriv) } GLboolean -intelUnbindContext(__DRIcontextPrivate * driContextPriv) +intelUnbindContext(__DRIcontext * driContextPriv) { struct intel_context *intel = (struct intel_context *) driContextPriv->driverPrivate; @@ -924,11 +924,11 @@ intelUnbindContext(__DRIcontextPrivate * driContextPriv) } GLboolean -intelMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv) +intelMakeCurrent(__DRIcontext * driContextPriv, + __DRIdrawable * driDrawPriv, + __DRIdrawable * driReadPriv) { - __DRIscreenPrivate *psp = driDrawPriv->driScreenPriv; + __DRIscreen *psp = driDrawPriv->driScreenPriv; struct intel_context *intel; GET_CURRENT_CONTEXT(curCtx); @@ -1031,8 +1031,8 @@ intelMakeCurrent(__DRIcontextPrivate * driContextPriv, static void intelContendedLock(struct intel_context *intel, GLuint flags) { - __DRIdrawablePrivate *dPriv = intel->driDrawable; - __DRIscreenPrivate *sPriv = intel->driScreen; + __DRIdrawable *dPriv = intel->driDrawable; + __DRIscreen *sPriv = intel->driScreen; volatile drm_i915_sarea_t *sarea = intel->sarea; int me = intel->hHWContext; diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 09e8223bc7..6e0b47160a 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -299,10 +299,10 @@ struct intel_context drmLock *driHwLock; int driFd; - __DRIcontextPrivate *driContext; - __DRIdrawablePrivate *driDrawable; - __DRIdrawablePrivate *driReadDrawable; - __DRIscreenPrivate *driScreen; + __DRIcontext *driContext; + __DRIdrawable *driDrawable; + __DRIdrawable *driReadDrawable; + __DRIscreen *driScreen; intelScreenPrivate *intelScreen; volatile drm_i915_sarea_t *sarea; @@ -439,7 +439,7 @@ extern int INTEL_DEBUG; extern GLboolean intelInitContext(struct intel_context *intel, const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate, struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c index 20424e2e58..3b75b718ff 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_read.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c @@ -77,7 +77,7 @@ do_texture_readpixels(GLcontext * ctx, struct intel_context *intel = intel_context(ctx); intelScreenPrivate *screen = intel->intelScreen; GLint pitch = pack->RowLength ? pack->RowLength : width; - __DRIdrawablePrivate *dPriv = intel->driDrawable; + __DRIdrawable *dPriv = intel->driDrawable; int textureFormat; GLenum glTextureFormat; int destFormat, depthFormat, destPitch; @@ -233,7 +233,7 @@ do_blit_readpixels(GLcontext * ctx, dri_bo *dst_buffer = intel_bufferobj_buffer(intel, dst, all ? INTEL_WRITE_FULL : INTEL_WRITE_PART); - __DRIdrawablePrivate *dPriv = intel->driReadDrawable; + __DRIdrawable *dPriv = intel->driReadDrawable; int nbox = dPriv->numClipRects; drm_clip_rect_t *box = dPriv->pClipRects; drm_clip_rect_t rect; diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index a3d676741a..d8d89b1ec1 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -109,7 +109,7 @@ static PFNGLXCREATECONTEXTMODES create_context_modes = NULL; * \return GL_TRUE if success, GL_FALSE if error. */ GLboolean -intelMapScreenRegions(__DRIscreenPrivate * sPriv) +intelMapScreenRegions(__DRIscreen * sPriv) { intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; @@ -140,7 +140,7 @@ intelUnmapScreenRegions(intelScreenPrivate * intelScreen) static void intelPrintDRIInfo(intelScreenPrivate * intelScreen, - __DRIscreenPrivate * sPriv, I830DRIPtr gDRIPriv) + __DRIscreen * sPriv, I830DRIPtr gDRIPriv) { fprintf(stderr, "*** Front size: 0x%x offset: 0x%x pitch: %d\n", intelScreen->front.size, intelScreen->front.offset, @@ -248,7 +248,7 @@ static const __DRIextension *intelScreenExtensions[] = { }; static GLboolean -intel_get_param(__DRIscreenPrivate *psp, int param, int *value) +intel_get_param(__DRIscreen *psp, int param, int *value) { int ret; struct drm_i915_getparam gp; @@ -265,7 +265,7 @@ intel_get_param(__DRIscreenPrivate *psp, int param, int *value) return GL_TRUE; } -static GLboolean intelInitDriver(__DRIscreenPrivate *sPriv) +static GLboolean intelInitDriver(__DRIscreen *sPriv) { intelScreenPrivate *intelScreen; I830DRIPtr gDRIPriv = (I830DRIPtr) sPriv->pDevPriv; @@ -321,7 +321,7 @@ static GLboolean intelInitDriver(__DRIscreenPrivate *sPriv) static void -intelDestroyScreen(__DRIscreenPrivate * sPriv) +intelDestroyScreen(__DRIscreen * sPriv) { intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; @@ -338,8 +338,8 @@ intelDestroyScreen(__DRIscreenPrivate * sPriv) * This is called when we need to set up GL rendering to a new X window. */ static GLboolean -intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, - __DRIdrawablePrivate * driDrawPriv, +intelCreateBuffer(__DRIscreen * driScrnPriv, + __DRIdrawable * driDrawPriv, const __GLcontextModes * mesaVis, GLboolean isPixmap) { if (isPixmap) { @@ -415,7 +415,7 @@ intelCreateBuffer(__DRIscreenPrivate * driScrnPriv, } static void -intelDestroyBuffer(__DRIdrawablePrivate * driDrawPriv) +intelDestroyBuffer(__DRIdrawable * driDrawPriv) { struct intel_framebuffer *intel_fb = driDrawPriv->driverPrivate; struct intel_renderbuffer *depth_rb; @@ -449,7 +449,7 @@ intelDestroyBuffer(__DRIdrawablePrivate * driDrawPriv) * Get information about previous buffer swaps. */ static int -intelGetSwapInfo(__DRIdrawablePrivate * dPriv, __DRIswapInfo * sInfo) +intelGetSwapInfo(__DRIdrawable * dPriv, __DRIswapInfo * sInfo) { struct intel_framebuffer *intel_fb; @@ -476,22 +476,22 @@ intelGetSwapInfo(__DRIdrawablePrivate * dPriv, __DRIswapInfo * sInfo) * functions. */ extern GLboolean i830CreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); extern GLboolean i915CreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); extern GLboolean brwCreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); static GLboolean intelCreateContext(const __GLcontextModes * mesaVis, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate) { - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; intelScreenPrivate *intelScreen = (intelScreenPrivate *) sPriv->private; #ifdef I915 @@ -514,7 +514,7 @@ intelCreateContext(const __GLcontextModes * mesaVis, static __DRIconfig ** -intelFillInModes(__DRIscreenPrivate *psp, +intelFillInModes(__DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer) { @@ -606,7 +606,7 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) { int gem_kernel = 0; struct drm_i915_getparam gp; - __DRIscreenPrivate *spriv = intelScreen->driScrnPriv; + __DRIscreen *spriv = intelScreen->driScrnPriv; int num_fences = 0; intelScreen->no_hw = getenv("INTEL_NO_HW") != NULL; @@ -650,7 +650,7 @@ intel_init_bufmgr(intelScreenPrivate *intelScreen) * * \return the __GLcontextModes supported by this driver */ -static const __DRIconfig **intelInitScreen(__DRIscreenPrivate *psp) +static const __DRIconfig **intelInitScreen(__DRIscreen *psp) { intelScreenPrivate *intelScreen; #ifdef I915 @@ -706,7 +706,7 @@ struct intel_context *intelScreenContext(intelScreenPrivate *intelScreen) * \return the __GLcontextModes supported by this driver */ static const -__DRIconfig **intelInitScreen2(__DRIscreenPrivate *psp) +__DRIconfig **intelInitScreen2(__DRIscreen *psp) { intelScreenPrivate *intelScreen; GLenum fb_format[3]; diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index 14ca0903b6..e87e306d86 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -66,7 +66,7 @@ typedef struct int logTextureGranularity; - __DRIscreenPrivate *driScrnPriv; + __DRIscreen *driScrnPriv; volatile drm_i915_sarea_t *sarea; @@ -88,18 +88,18 @@ typedef struct -extern GLboolean intelMapScreenRegions(__DRIscreenPrivate * sPriv); +extern GLboolean intelMapScreenRegions(__DRIscreen * sPriv); extern void intelUnmapScreenRegions(intelScreenPrivate * intelScreen); -extern void intelDestroyContext(__DRIcontextPrivate * driContextPriv); +extern void intelDestroyContext(__DRIcontext * driContextPriv); -extern GLboolean intelUnbindContext(__DRIcontextPrivate * driContextPriv); +extern GLboolean intelUnbindContext(__DRIcontext * driContextPriv); extern GLboolean -intelMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); +intelMakeCurrent(__DRIcontext * driContextPriv, + __DRIdrawable * driDrawPriv, + __DRIdrawable * driReadPriv); extern struct intel_context *intelScreenContext(intelScreenPrivate *intelScreen); diff --git a/src/mesa/drivers/dri/intel/intel_swapbuffers.c b/src/mesa/drivers/dri/intel/intel_swapbuffers.c index 5ae1240718..c975b40d3c 100644 --- a/src/mesa/drivers/dri/intel/intel_swapbuffers.c +++ b/src/mesa/drivers/dri/intel/intel_swapbuffers.c @@ -41,7 +41,7 @@ * When considering multiple crtcs. */ GLuint -intelFixupVblank(struct intel_context *intel, __DRIdrawablePrivate *dPriv) +intelFixupVblank(struct intel_context *intel, __DRIdrawable *dPriv) { if (!intel->intelScreen->driScrnPriv->dri2.enabled && intel->intelScreen->driScrnPriv->ddx_version.minor >= 7) { @@ -85,9 +85,9 @@ intelFixupVblank(struct intel_context *intel, __DRIdrawablePrivate *dPriv) * Called from driSwapBuffers() */ void -intelSwapBuffers(__DRIdrawablePrivate * dPriv) +intelSwapBuffers(__DRIdrawable * dPriv) { - __DRIscreenPrivate *psp = dPriv->driScreenPriv; + __DRIscreen *psp = dPriv->driScreenPriv; if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { GET_CURRENT_CONTEXT(ctx); @@ -144,7 +144,7 @@ intelSwapBuffers(__DRIdrawablePrivate * dPriv) * Called from driCopySubBuffer() */ void -intelCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h) +intelCopySubBuffer(__DRIdrawable * dPriv, int x, int y, int w, int h) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { struct intel_context *intel = @@ -176,7 +176,7 @@ void intelWindowMoved(struct intel_context *intel) { GLcontext *ctx = &intel->ctx; - __DRIdrawablePrivate *dPriv = intel->driDrawable; + __DRIdrawable *dPriv = intel->driDrawable; struct intel_framebuffer *intel_fb = dPriv->driverPrivate; if (!intel->intelScreen->driScrnPriv->dri2.enabled && diff --git a/src/mesa/drivers/dri/intel/intel_swapbuffers.h b/src/mesa/drivers/dri/intel/intel_swapbuffers.h index 75bb6242ff..82b77c6362 100644 --- a/src/mesa/drivers/dri/intel/intel_swapbuffers.h +++ b/src/mesa/drivers/dri/intel/intel_swapbuffers.h @@ -37,13 +37,13 @@ struct intel_framebuffer; extern void -intelSwapBuffers(__DRIdrawablePrivate * dPriv); +intelSwapBuffers(__DRIdrawable * dPriv); extern void -intelCopySubBuffer(__DRIdrawablePrivate * dPriv, int x, int y, int w, int h); +intelCopySubBuffer(__DRIdrawable * dPriv, int x, int y, int w, int h); extern GLuint -intelFixupVblank(struct intel_context *intel, __DRIdrawablePrivate *dPriv); +intelFixupVblank(struct intel_context *intel, __DRIdrawable *dPriv); extern void intelWindowMoved(struct intel_context *intel); diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index ee953cfbe7..a70738c958 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -138,7 +138,7 @@ do_copy_texsubimage(struct intel_context *intel, if (ctx->ReadBuffer->Name == 0) { /* reading from a window, adjust x, y */ - const __DRIdrawablePrivate *dPriv = intel->driReadDrawable; + const __DRIdrawable *dPriv = intel->driReadDrawable; y = dPriv->y + (dPriv->h - (y + height)); x += dPriv->x; diff --git a/src/mesa/drivers/dri/mach64/mach64_context.c b/src/mesa/drivers/dri/mach64/mach64_context.c index 2bca293b3c..3b4ef7ffd8 100644 --- a/src/mesa/drivers/dri/mach64/mach64_context.c +++ b/src/mesa/drivers/dri/mach64/mach64_context.c @@ -89,11 +89,11 @@ static const struct dri_extension card_extensions[] = /* Create the device specific context. */ GLboolean mach64CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ) { GLcontext *ctx, *shareCtx; - __DRIscreenPrivate *driScreen = driContextPriv->driScreenPriv; + __DRIscreen *driScreen = driContextPriv->driScreenPriv; struct dd_function_table functions; mach64ContextPtr mmesa; mach64ScreenPtr mach64Screen; @@ -260,7 +260,7 @@ GLboolean mach64CreateContext( const __GLcontextModes *glVisual, /* Destroy the device specific context. */ -void mach64DestroyContext( __DRIcontextPrivate *driContextPriv ) +void mach64DestroyContext( __DRIcontext *driContextPriv ) { mach64ContextPtr mmesa = (mach64ContextPtr) driContextPriv->driverPrivate; @@ -307,9 +307,9 @@ void mach64DestroyContext( __DRIcontextPrivate *driContextPriv ) * buffer `b'. */ GLboolean -mach64MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) +mach64MakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ) { if ( driContextPriv ) { GET_CURRENT_CONTEXT(ctx); @@ -352,7 +352,7 @@ mach64MakeCurrent( __DRIcontextPrivate *driContextPriv, /* Force the context `c' to be unbound from its buffer. */ GLboolean -mach64UnbindContext( __DRIcontextPrivate *driContextPriv ) +mach64UnbindContext( __DRIcontext *driContextPriv ) { return GL_TRUE; } diff --git a/src/mesa/drivers/dri/mach64/mach64_context.h b/src/mesa/drivers/dri/mach64/mach64_context.h index 854751626d..18fc859d01 100644 --- a/src/mesa/drivers/dri/mach64/mach64_context.h +++ b/src/mesa/drivers/dri/mach64/mach64_context.h @@ -232,9 +232,9 @@ struct mach64_context { /* Mirrors of some DRI state */ - __DRIcontextPrivate *driContext; /* DRI context */ - __DRIscreenPrivate *driScreen; /* DRI screen */ - __DRIdrawablePrivate *driDrawable; /* DRI drawable bound to this ctx */ + __DRIcontext *driContext; /* DRI context */ + __DRIscreen *driScreen; /* DRI screen */ + __DRIdrawable *driDrawable; /* DRI drawable bound to this ctx */ unsigned int lastStamp; /* mirror driDrawable->lastStamp */ @@ -274,16 +274,16 @@ struct mach64_context { extern GLboolean mach64CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ); -extern void mach64DestroyContext( __DRIcontextPrivate * ); +extern void mach64DestroyContext( __DRIcontext * ); -extern GLboolean mach64MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ); +extern GLboolean mach64MakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ); -extern GLboolean mach64UnbindContext( __DRIcontextPrivate *driContextPriv ); +extern GLboolean mach64UnbindContext( __DRIcontext *driContextPriv ); /* ================================================================ * Byte ordering diff --git a/src/mesa/drivers/dri/mach64/mach64_ioctl.c b/src/mesa/drivers/dri/mach64/mach64_ioctl.c index ef5c0625c3..03587c44fd 100644 --- a/src/mesa/drivers/dri/mach64/mach64_ioctl.c +++ b/src/mesa/drivers/dri/mach64/mach64_ioctl.c @@ -279,7 +279,7 @@ static int mach64WaitForFrameCompletion( mach64ContextPtr mmesa ) /* Copy the back color buffer to the front color buffer. */ -void mach64CopyBuffer( __DRIdrawablePrivate *dPriv ) +void mach64CopyBuffer( __DRIdrawable *dPriv ) { mach64ContextPtr mmesa; GLint nbox, i, ret; @@ -668,7 +668,7 @@ void mach64PerformanceBoxesLocked( mach64ContextPtr mmesa ) static void mach64DDClear( GLcontext *ctx, GLbitfield mask ) { mach64ContextPtr mmesa = MACH64_CONTEXT( ctx ); - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; + __DRIdrawable *dPriv = mmesa->driDrawable; drm_mach64_clear_t clear; GLuint flags = 0; GLint i; diff --git a/src/mesa/drivers/dri/mach64/mach64_ioctl.h b/src/mesa/drivers/dri/mach64/mach64_ioctl.h index 6ef9bc0bca..1ffda1932f 100644 --- a/src/mesa/drivers/dri/mach64/mach64_ioctl.h +++ b/src/mesa/drivers/dri/mach64/mach64_ioctl.h @@ -78,7 +78,7 @@ extern void mach64FireBlitLocked( mach64ContextPtr mmesa, void *buffer, GLint offset, GLint pitch, GLint format, GLint x, GLint y, GLint width, GLint height ); -extern void mach64CopyBuffer( __DRIdrawablePrivate *dPriv ); +extern void mach64CopyBuffer( __DRIdrawable *dPriv ); #if ENABLE_PERF_BOXES extern void mach64PerformanceCounters( mach64ContextPtr mmesa ); extern void mach64PerformanceBoxesLocked( mach64ContextPtr mmesa ); diff --git a/src/mesa/drivers/dri/mach64/mach64_lock.c b/src/mesa/drivers/dri/mach64/mach64_lock.c index d018ba4174..8653c77da5 100644 --- a/src/mesa/drivers/dri/mach64/mach64_lock.c +++ b/src/mesa/drivers/dri/mach64/mach64_lock.c @@ -51,8 +51,8 @@ int prevLockLine = 0; */ void mach64GetLock( mach64ContextPtr mmesa, GLuint flags ) { - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; - __DRIscreenPrivate *sPriv = mmesa->driScreen; + __DRIdrawable *dPriv = mmesa->driDrawable; + __DRIscreen *sPriv = mmesa->driScreen; drm_mach64_sarea_t *sarea = mmesa->sarea; int i; diff --git a/src/mesa/drivers/dri/mach64/mach64_screen.c b/src/mesa/drivers/dri/mach64/mach64_screen.c index 3b19cf5333..63515d278c 100644 --- a/src/mesa/drivers/dri/mach64/mach64_screen.c +++ b/src/mesa/drivers/dri/mach64/mach64_screen.c @@ -68,7 +68,7 @@ static const GLuint __driNConfigOptions = 2; #endif static const __DRIconfig ** -mach64FillInModes( __DRIscreenPrivate *psp, +mach64FillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { @@ -144,7 +144,7 @@ mach64FillInModes( __DRIscreenPrivate *psp, /* Create the device specific screen private data struct. */ static mach64ScreenRec * -mach64CreateScreen( __DRIscreenPrivate *sPriv ) +mach64CreateScreen( __DRIscreen *sPriv ) { mach64ScreenPtr mach64Screen; ATIDRIPtr serverInfo = (ATIDRIPtr)sPriv->pDevPriv; @@ -272,7 +272,7 @@ mach64CreateScreen( __DRIscreenPrivate *sPriv ) /* Destroy the device specific screen private data struct. */ static void -mach64DestroyScreen( __DRIscreenPrivate *driScreen ) +mach64DestroyScreen( __DRIscreen *driScreen ) { mach64ScreenRec *mach64Screen = (mach64ScreenRec *) driScreen->private; @@ -299,8 +299,8 @@ mach64DestroyScreen( __DRIscreenPrivate *driScreen ) * data. */ static GLboolean -mach64CreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +mach64CreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -370,7 +370,7 @@ mach64CreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -mach64DestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +mach64DestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } @@ -378,7 +378,7 @@ mach64DestroyBuffer(__DRIdrawablePrivate *driDrawPriv) /* Copy the back color buffer to the front color buffer */ static void -mach64SwapBuffers(__DRIdrawablePrivate *dPriv) +mach64SwapBuffers(__DRIdrawable *dPriv) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { mach64ContextPtr mmesa; @@ -400,7 +400,7 @@ mach64SwapBuffers(__DRIdrawablePrivate *dPriv) /* Initialize the driver specific screen private data. */ static GLboolean -mach64InitDriver( __DRIscreenPrivate *driScreen ) +mach64InitDriver( __DRIscreen *driScreen ) { driScreen->private = (void *) mach64CreateScreen( driScreen ); @@ -420,7 +420,7 @@ mach64InitDriver( __DRIscreenPrivate *driScreen ) * \return the __GLcontextModes supported by this driver */ static const __DRIconfig ** -mach64InitScreen(__DRIscreenPrivate *psp) +mach64InitScreen(__DRIscreen *psp) { static const __DRIversion ddx_expected = { 6, 4, 0 }; static const __DRIversion dri_expected = { 4, 0, 0 }; diff --git a/src/mesa/drivers/dri/mach64/mach64_screen.h b/src/mesa/drivers/dri/mach64/mach64_screen.h index be5e29a3e5..1966809c03 100644 --- a/src/mesa/drivers/dri/mach64/mach64_screen.h +++ b/src/mesa/drivers/dri/mach64/mach64_screen.h @@ -70,7 +70,7 @@ typedef struct { drmBufMapPtr buffers; - __DRIscreenPrivate *driScreen; + __DRIscreen *driScreen; driOptionCache optionCache; diff --git a/src/mesa/drivers/dri/mach64/mach64_span.c b/src/mesa/drivers/dri/mach64/mach64_span.c index 500319e0e3..b4ba2a41c9 100644 --- a/src/mesa/drivers/dri/mach64/mach64_span.c +++ b/src/mesa/drivers/dri/mach64/mach64_span.c @@ -40,8 +40,8 @@ #define LOCAL_VARS \ mach64ContextPtr mmesa = MACH64_CONTEXT(ctx); \ - __DRIscreenPrivate *sPriv = mmesa->driScreen; \ - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; \ + __DRIscreen *sPriv = mmesa->driScreen; \ + __DRIdrawable *dPriv = mmesa->driDrawable; \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ GLuint height = dPriv->h; \ GLushort p; \ @@ -49,8 +49,8 @@ #define LOCAL_DEPTH_VARS \ mach64ContextPtr mmesa = MACH64_CONTEXT(ctx); \ - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; \ - __DRIscreenPrivate *driScreen = mmesa->driScreen; \ + __DRIdrawable *dPriv = mmesa->driDrawable; \ + __DRIscreen *driScreen = mmesa->driScreen; \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ GLuint height = dPriv->h; \ char *buf = (char *)(driScreen->pFB + drb->offset + \ diff --git a/src/mesa/drivers/dri/mach64/mach64_state.c b/src/mesa/drivers/dri/mach64/mach64_state.c index 902905de71..df7cbc8670 100644 --- a/src/mesa/drivers/dri/mach64/mach64_state.c +++ b/src/mesa/drivers/dri/mach64/mach64_state.c @@ -388,7 +388,7 @@ static void mach64UpdateClipping( GLcontext *ctx ) mach64ScreenPtr mach64Screen = mmesa->mach64Screen; if ( mmesa->driDrawable ) { - __DRIdrawablePrivate *drawable = mmesa->driDrawable; + __DRIdrawable *drawable = mmesa->driDrawable; int x1 = 0; int y1 = 0; int x2 = drawable->w - 1; @@ -689,7 +689,7 @@ static void mach64DDLogicOpCode( GLcontext *ctx, GLenum opcode ) void mach64SetCliprects( GLcontext *ctx, GLenum mode ) { mach64ContextPtr mmesa = MACH64_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; + __DRIdrawable *dPriv = mmesa->driDrawable; switch ( mode ) { case GL_FRONT_LEFT: diff --git a/src/mesa/drivers/dri/mga/mga_xmesa.c b/src/mesa/drivers/dri/mga/mga_xmesa.c index 2c7f50c498..428afa5895 100644 --- a/src/mesa/drivers/dri/mga/mga_xmesa.c +++ b/src/mesa/drivers/dri/mga/mga_xmesa.c @@ -108,7 +108,7 @@ int MGA_DEBUG = 0; #endif static const __DRIconfig ** -mgaFillInModes( __DRIscreenPrivate *psp, +mgaFillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { @@ -190,7 +190,7 @@ const __DRIextension *mgaScreenExtensions[] = { }; static GLboolean -mgaInitDriver(__DRIscreenPrivate *sPriv) +mgaInitDriver(__DRIscreen *sPriv) { mgaScreenPrivate *mgaScreen; MGADRIPtr serverInfo = (MGADRIPtr)sPriv->pDevPriv; @@ -332,7 +332,7 @@ mgaInitDriver(__DRIscreenPrivate *sPriv) static void -mgaDestroyScreen(__DRIscreenPrivate *sPriv) +mgaDestroyScreen(__DRIscreen *sPriv) { mgaScreenPrivate *mgaScreen = (mgaScreenPrivate *) sPriv->private; @@ -426,14 +426,14 @@ static const struct dri_debug_control debug_control[] = static GLboolean mgaCreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ) { int i; unsigned maxlevels; GLcontext *ctx, *shareCtx; mgaContextPtr mmesa; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; mgaScreenPrivate *mgaScreen = (mgaScreenPrivate *)sPriv->private; drm_mga_sarea_t *saPriv = (drm_mga_sarea_t *)(((char*)sPriv->pSAREA)+ mgaScreen->sarea_priv_offset); @@ -645,7 +645,7 @@ mgaCreateContext( const __GLcontextModes *mesaVis, } static void -mgaDestroyContext(__DRIcontextPrivate *driContextPriv) +mgaDestroyContext(__DRIcontext *driContextPriv) { mgaContextPtr mmesa = (mgaContextPtr) driContextPriv->driverPrivate; @@ -697,8 +697,8 @@ mgaDestroyContext(__DRIcontextPrivate *driContextPriv) static GLboolean -mgaCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +mgaCreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -814,13 +814,13 @@ mgaCreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -mgaDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +mgaDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } static void -mgaSwapBuffers(__DRIdrawablePrivate *dPriv) +mgaSwapBuffers(__DRIdrawable *dPriv) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { mgaContextPtr mmesa; @@ -839,7 +839,7 @@ mgaSwapBuffers(__DRIdrawablePrivate *dPriv) } static GLboolean -mgaUnbindContext(__DRIcontextPrivate *driContextPriv) +mgaUnbindContext(__DRIcontext *driContextPriv) { mgaContextPtr mmesa = (mgaContextPtr) driContextPriv->driverPrivate; if (mmesa) @@ -855,9 +855,9 @@ mgaUnbindContext(__DRIcontextPrivate *driContextPriv) * But why are we doing context initialization here??? */ static GLboolean -mgaMakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv) +mgaMakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv) { if (driContextPriv) { mgaContextPtr mmesa = (mgaContextPtr) driContextPriv->driverPrivate; @@ -892,7 +892,7 @@ mgaMakeCurrent(__DRIcontextPrivate *driContextPriv, void mgaGetLock( mgaContextPtr mmesa, GLuint flags ) { - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; + __DRIdrawable *dPriv = mmesa->driDrawable; drm_mga_sarea_t *sarea = mmesa->sarea; int me = mmesa->hHWContext; int i; @@ -960,7 +960,7 @@ static const __DRIconfig **mgaInitScreen(__DRIscreen *psp) * Get information about previous buffer swaps. */ static int -getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) +getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ) { mgaContextPtr mmesa; diff --git a/src/mesa/drivers/dri/mga/mga_xmesa.h b/src/mesa/drivers/dri/mga/mga_xmesa.h index 07c22bd596..aee146090c 100644 --- a/src/mesa/drivers/dri/mga/mga_xmesa.h +++ b/src/mesa/drivers/dri/mga/mga_xmesa.h @@ -67,7 +67,7 @@ typedef struct mga_screen_private_s { char *texVirtual[MGA_NR_TEX_HEAPS]; - __DRIscreenPrivate *sPriv; + __DRIscreen *sPriv; drmBufMapPtr bufs; drmRegion mmio; diff --git a/src/mesa/drivers/dri/mga/mgacontext.h b/src/mesa/drivers/dri/mga/mgacontext.h index 30640a29b3..4141565931 100644 --- a/src/mesa/drivers/dri/mga/mgacontext.h +++ b/src/mesa/drivers/dri/mga/mgacontext.h @@ -294,10 +294,10 @@ struct mga_context_t { drm_context_t hHWContext; drm_hw_lock_t *driHwLock; int driFd; - __DRIdrawablePrivate *driDrawable; - __DRIdrawablePrivate *driReadable; + __DRIdrawable *driDrawable; + __DRIdrawable *driReadable; - __DRIscreenPrivate *driScreen; + __DRIscreen *driScreen; struct mga_screen_private_s *mgaScreen; drm_mga_sarea_t *sarea; diff --git a/src/mesa/drivers/dri/mga/mgaioctl.c b/src/mesa/drivers/dri/mga/mgaioctl.c index 4438bad920..8ce5d802ab 100644 --- a/src/mesa/drivers/dri/mga/mgaioctl.c +++ b/src/mesa/drivers/dri/mga/mgaioctl.c @@ -207,7 +207,7 @@ static void mgaClear( GLcontext *ctx, GLbitfield mask ) { mgaContextPtr mmesa = MGA_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; + __DRIdrawable *dPriv = mmesa->driDrawable; GLuint flags = 0; GLuint clear_color = mmesa->ClearColor; GLuint clear_depth = 0; @@ -409,7 +409,7 @@ static void mgaWaitForFrameCompletion( mgaContextPtr mmesa ) /* * Copy the back buffer to the front buffer. */ -void mgaCopyBuffer( __DRIdrawablePrivate *dPriv ) +void mgaCopyBuffer( __DRIdrawable *dPriv ) { mgaContextPtr mmesa; drm_clip_rect_t *pbox; @@ -417,7 +417,7 @@ void mgaCopyBuffer( __DRIdrawablePrivate *dPriv ) GLint ret; GLint i; GLboolean missed_target; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; + __DRIscreen *psp = dPriv->driScreenPriv; assert(dPriv); assert(dPriv->driContextPriv); diff --git a/src/mesa/drivers/dri/mga/mgaioctl.h b/src/mesa/drivers/dri/mga/mgaioctl.h index dbc823de80..7a8660d203 100644 --- a/src/mesa/drivers/dri/mga/mgaioctl.h +++ b/src/mesa/drivers/dri/mga/mgaioctl.h @@ -32,7 +32,7 @@ #include "mgacontext.h" #include "mga_xmesa.h" -void mgaCopyBuffer( __DRIdrawablePrivate *dPriv ); +void mgaCopyBuffer( __DRIdrawable *dPriv ); void mgaWaitForVBlank( mgaContextPtr mmesa ); void mgaGetILoadBufferLocked( mgaContextPtr mmesa ); diff --git a/src/mesa/drivers/dri/mga/mgapixel.c b/src/mesa/drivers/dri/mga/mgapixel.c index 05b30ba61e..69415f8a83 100644 --- a/src/mesa/drivers/dri/mga/mgapixel.c +++ b/src/mesa/drivers/dri/mga/mgapixel.c @@ -299,7 +299,7 @@ mgaTryReadPixels( GLcontext *ctx, #if 0 { - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; + __DRIdrawable *dPriv = mmesa->driDrawable; int nbox, retcode, i; UPDATE_LOCK( mmesa, DRM_LOCK_FLUSH | DRM_LOCK_QUIESCENT ); @@ -399,7 +399,7 @@ static void do_draw_pix( GLcontext *ctx, #if 0 mgaContextPtr mmesa = MGA_CONTEXT(ctx); drmMGABlit blit; - __DRIdrawablePrivate *dPriv = mmesa->driDrawable; + __DRIdrawable *dPriv = mmesa->driDrawable; drm_clip_rect_t pbox = dPriv->pClipRects; int nbox = dPriv->numClipRects; int retcode, i; diff --git a/src/mesa/drivers/dri/mga/mgaspan.c b/src/mesa/drivers/dri/mga/mgaspan.c index 2ff1cac8e2..10606c152c 100644 --- a/src/mesa/drivers/dri/mga/mgaspan.c +++ b/src/mesa/drivers/dri/mga/mgaspan.c @@ -36,9 +36,9 @@ #define LOCAL_VARS \ mgaContextPtr mmesa = MGA_CONTEXT(ctx); \ - __DRIscreenPrivate *sPriv = mmesa->driScreen; \ + __DRIscreen *sPriv = mmesa->driScreen; \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + const __DRIdrawable *dPriv = drb->dPriv; \ GLuint pitch = drb->pitch; \ GLuint height = dPriv->h; \ char *buf = (char *)(sPriv->pFB + \ @@ -52,9 +52,9 @@ #define LOCAL_DEPTH_VARS \ mgaContextPtr mmesa = MGA_CONTEXT(ctx); \ - __DRIscreenPrivate *sPriv = mmesa->driScreen; \ + __DRIscreen *sPriv = mmesa->driScreen; \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ - const __DRIdrawablePrivate *dPriv = drb->dPriv; \ + const __DRIdrawable *dPriv = drb->dPriv; \ GLuint pitch = drb->pitch; \ GLuint height = dPriv->h; \ char *buf = (char *)(sPriv->pFB + \ diff --git a/src/mesa/drivers/dri/mga/mgastate.c b/src/mesa/drivers/dri/mga/mgastate.c index 1e51057534..0253044761 100644 --- a/src/mesa/drivers/dri/mga/mgastate.c +++ b/src/mesa/drivers/dri/mga/mgastate.c @@ -746,7 +746,7 @@ static void mgaDDLogicOp( GLcontext *ctx, GLenum opcode ) static void mga_set_cliprects(mgaContextPtr mmesa) { - __DRIdrawablePrivate *driDrawable = mmesa->driDrawable; + __DRIdrawable *driDrawable = mmesa->driDrawable; if ((mmesa->draw_buffer != MGA_FRONT) || (driDrawable->numBackClipRects == 0)) { @@ -774,8 +774,8 @@ static void mga_set_cliprects(mgaContextPtr mmesa) void mgaUpdateRects( mgaContextPtr mmesa, GLuint buffers ) { - __DRIdrawablePrivate *const driDrawable = mmesa->driDrawable; - __DRIdrawablePrivate *const driReadable = mmesa->driReadable; + __DRIdrawable *const driDrawable = mmesa->driDrawable; + __DRIdrawable *const driReadable = mmesa->driReadable; mmesa->dirty_cliprects = 0; diff --git a/src/mesa/drivers/dri/r128/r128_context.c b/src/mesa/drivers/dri/r128/r128_context.c index 0b250876c5..e389e1c87b 100644 --- a/src/mesa/drivers/dri/r128/r128_context.c +++ b/src/mesa/drivers/dri/r128/r128_context.c @@ -101,11 +101,11 @@ static const struct dri_debug_control debug_control[] = /* Create the device specific context. */ GLboolean r128CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ) { GLcontext *ctx, *shareCtx; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; struct dd_function_table functions; r128ContextPtr rmesa; r128ScreenPtr r128scrn; @@ -274,7 +274,7 @@ GLboolean r128CreateContext( const __GLcontextModes *glVisual, /* Destroy the device specific context. */ -void r128DestroyContext( __DRIcontextPrivate *driContextPriv ) +void r128DestroyContext( __DRIcontext *driContextPriv ) { r128ContextPtr rmesa = (r128ContextPtr) driContextPriv->driverPrivate; @@ -325,9 +325,9 @@ void r128DestroyContext( __DRIcontextPrivate *driContextPriv ) * buffer `b'. */ GLboolean -r128MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) +r128MakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ) { if ( driContextPriv ) { GET_CURRENT_CONTEXT(ctx); @@ -364,7 +364,7 @@ r128MakeCurrent( __DRIcontextPrivate *driContextPriv, /* Force the context `c' to be unbound from its buffer. */ GLboolean -r128UnbindContext( __DRIcontextPrivate *driContextPriv ) +r128UnbindContext( __DRIcontext *driContextPriv ) { return GL_TRUE; } diff --git a/src/mesa/drivers/dri/r128/r128_context.h b/src/mesa/drivers/dri/r128/r128_context.h index 0e10209a6a..65f845c115 100644 --- a/src/mesa/drivers/dri/r128/r128_context.h +++ b/src/mesa/drivers/dri/r128/r128_context.h @@ -186,9 +186,9 @@ struct r128_context { /* Mirrors of some DRI state */ - __DRIcontextPrivate *driContext; /* DRI context */ - __DRIscreenPrivate *driScreen; /* DRI screen */ - __DRIdrawablePrivate *driDrawable; /* DRI drawable bound to this ctx */ + __DRIcontext *driContext; /* DRI context */ + __DRIscreen *driScreen; /* DRI screen */ + __DRIdrawable *driDrawable; /* DRI drawable bound to this ctx */ unsigned int lastStamp; /* mirror driDrawable->lastStamp */ @@ -225,16 +225,16 @@ struct r128_context { extern GLboolean r128CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ); -extern void r128DestroyContext( __DRIcontextPrivate * ); +extern void r128DestroyContext( __DRIcontext * ); -extern GLboolean r128MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ); +extern GLboolean r128MakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ); -extern GLboolean r128UnbindContext( __DRIcontextPrivate *driContextPriv ); +extern GLboolean r128UnbindContext( __DRIcontext *driContextPriv ); /* ================================================================ * Debugging: diff --git a/src/mesa/drivers/dri/r128/r128_ioctl.c b/src/mesa/drivers/dri/r128/r128_ioctl.c index 84ac3d9f79..56758d971c 100644 --- a/src/mesa/drivers/dri/r128/r128_ioctl.c +++ b/src/mesa/drivers/dri/r128/r128_ioctl.c @@ -248,7 +248,7 @@ static int r128WaitForFrameCompletion( r128ContextPtr rmesa ) /* Copy the back color buffer to the front color buffer. */ -void r128CopyBuffer( __DRIdrawablePrivate *dPriv ) +void r128CopyBuffer( __DRIdrawable *dPriv ) { r128ContextPtr rmesa; GLint nbox, i, ret; @@ -327,7 +327,7 @@ void r128CopyBuffer( __DRIdrawablePrivate *dPriv ) #endif } -void r128PageFlip( __DRIdrawablePrivate *dPriv ) +void r128PageFlip( __DRIdrawable *dPriv ) { r128ContextPtr rmesa; GLint ret; @@ -401,7 +401,7 @@ void r128PageFlip( __DRIdrawablePrivate *dPriv ) static void r128Clear( GLcontext *ctx, GLbitfield mask ) { r128ContextPtr rmesa = R128_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = rmesa->driDrawable; + __DRIdrawable *dPriv = rmesa->driDrawable; drm_r128_clear_t clear; GLuint flags = 0; GLint i; diff --git a/src/mesa/drivers/dri/r128/r128_ioctl.h b/src/mesa/drivers/dri/r128/r128_ioctl.h index 4b0c9cdc7f..84ace900ee 100644 --- a/src/mesa/drivers/dri/r128/r128_ioctl.h +++ b/src/mesa/drivers/dri/r128/r128_ioctl.h @@ -85,8 +85,8 @@ extern void r128ReadDepthSpanLocked( r128ContextPtr rmesa, extern void r128ReadDepthPixelsLocked( r128ContextPtr rmesa, GLuint n, const GLint x[], const GLint y[] ); -extern void r128CopyBuffer( __DRIdrawablePrivate *dPriv ); -extern void r128PageFlip( __DRIdrawablePrivate *dPriv ); +extern void r128CopyBuffer( __DRIdrawable *dPriv ); +extern void r128PageFlip( __DRIdrawable *dPriv ); void r128WaitForVBlank( r128ContextPtr rmesa ); extern void r128WaitForIdleLocked( r128ContextPtr rmesa ); diff --git a/src/mesa/drivers/dri/r128/r128_lock.c b/src/mesa/drivers/dri/r128/r128_lock.c index 81488a2742..9bc3515b5a 100644 --- a/src/mesa/drivers/dri/r128/r128_lock.c +++ b/src/mesa/drivers/dri/r128/r128_lock.c @@ -68,8 +68,8 @@ r128UpdatePageFlipping( r128ContextPtr rmesa ) */ void r128GetLock( r128ContextPtr rmesa, GLuint flags ) { - __DRIdrawablePrivate *dPriv = rmesa->driDrawable; - __DRIscreenPrivate *sPriv = rmesa->driScreen; + __DRIdrawable *dPriv = rmesa->driDrawable; + __DRIscreen *sPriv = rmesa->driScreen; drm_r128_sarea_t *sarea = rmesa->sarea; int i; diff --git a/src/mesa/drivers/dri/r128/r128_screen.c b/src/mesa/drivers/dri/r128/r128_screen.c index 9da3b5fb73..fe3fb8747e 100644 --- a/src/mesa/drivers/dri/r128/r128_screen.c +++ b/src/mesa/drivers/dri/r128/r128_screen.c @@ -91,7 +91,7 @@ static const GLuint __driNConfigOptions = 3; /* Create the device specific screen private data struct. */ static r128ScreenPtr -r128CreateScreen( __DRIscreenPrivate *sPriv ) +r128CreateScreen( __DRIscreen *sPriv ) { r128ScreenPtr r128Screen; R128DRIPtr r128DRIPriv = (R128DRIPtr)sPriv->pDevPriv; @@ -236,7 +236,7 @@ r128CreateScreen( __DRIscreenPrivate *sPriv ) /* Destroy the device specific screen private data struct. */ static void -r128DestroyScreen( __DRIscreenPrivate *sPriv ) +r128DestroyScreen( __DRIscreen *sPriv ) { r128ScreenPtr r128Screen = (r128ScreenPtr)sPriv->private; @@ -262,8 +262,8 @@ r128DestroyScreen( __DRIscreenPrivate *sPriv ) * data. */ static GLboolean -r128CreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +r128CreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -349,7 +349,7 @@ r128CreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -r128DestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +r128DestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } @@ -357,7 +357,7 @@ r128DestroyBuffer(__DRIdrawablePrivate *driDrawPriv) /* Copy the back color buffer to the front color buffer */ static void -r128SwapBuffers(__DRIdrawablePrivate *dPriv) +r128SwapBuffers(__DRIdrawable *dPriv) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { r128ContextPtr rmesa; @@ -384,7 +384,7 @@ r128SwapBuffers(__DRIdrawablePrivate *dPriv) /* Initialize the driver specific screen private data. */ static GLboolean -r128InitDriver( __DRIscreenPrivate *sPriv ) +r128InitDriver( __DRIscreen *sPriv ) { sPriv->private = (void *) r128CreateScreen( sPriv ); @@ -397,7 +397,7 @@ r128InitDriver( __DRIscreenPrivate *sPriv ) } static const __DRIconfig ** -r128FillInModes( __DRIscreenPrivate *psp, +r128FillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { @@ -478,7 +478,7 @@ r128FillInModes( __DRIscreenPrivate *psp, * \return the __GLcontextModes supported by this driver */ static const __DRIconfig ** -r128InitScreen(__DRIscreenPrivate *psp) +r128InitScreen(__DRIscreen *psp) { static const __DRIversion ddx_expected = { 4, 0, 0 }; static const __DRIversion dri_expected = { 4, 0, 0 }; diff --git a/src/mesa/drivers/dri/r128/r128_screen.h b/src/mesa/drivers/dri/r128/r128_screen.h index e2fa1677c9..8d450adff3 100644 --- a/src/mesa/drivers/dri/r128/r128_screen.h +++ b/src/mesa/drivers/dri/r128/r128_screen.h @@ -71,7 +71,7 @@ typedef struct { drmBufMapPtr buffers; - __DRIscreenPrivate *driScreen; + __DRIscreen *driScreen; unsigned int sarea_priv_offset; /* Configuration cache with default values for all contexts */ diff --git a/src/mesa/drivers/dri/r128/r128_span.c b/src/mesa/drivers/dri/r128/r128_span.c index d238cc3c94..0413e5b4f1 100644 --- a/src/mesa/drivers/dri/r128/r128_span.c +++ b/src/mesa/drivers/dri/r128/r128_span.c @@ -50,8 +50,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define LOCAL_VARS \ r128ContextPtr rmesa = R128_CONTEXT(ctx); \ - __DRIscreenPrivate *sPriv = rmesa->driScreen; \ - __DRIdrawablePrivate *dPriv = rmesa->driDrawable; \ + __DRIscreen *sPriv = rmesa->driScreen; \ + __DRIdrawable *dPriv = rmesa->driDrawable; \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ GLuint height = dPriv->h; \ GLuint p; \ @@ -60,8 +60,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define LOCAL_DEPTH_VARS \ r128ContextPtr rmesa = R128_CONTEXT(ctx); \ r128ScreenPtr r128scrn = rmesa->r128Screen; \ - __DRIscreenPrivate *sPriv = rmesa->driScreen; \ - __DRIdrawablePrivate *dPriv = rmesa->driDrawable; \ + __DRIscreen *sPriv = rmesa->driScreen; \ + __DRIdrawable *dPriv = rmesa->driDrawable; \ GLuint height = dPriv->h; \ (void) r128scrn; (void) sPriv; (void) height diff --git a/src/mesa/drivers/dri/r128/r128_state.c b/src/mesa/drivers/dri/r128/r128_state.c index ac175d59ec..2254a7a4ff 100644 --- a/src/mesa/drivers/dri/r128/r128_state.c +++ b/src/mesa/drivers/dri/r128/r128_state.c @@ -572,7 +572,7 @@ static void r128UpdateClipping( GLcontext *ctx ) r128ContextPtr rmesa = R128_CONTEXT(ctx); if ( rmesa->driDrawable ) { - __DRIdrawablePrivate *drawable = rmesa->driDrawable; + __DRIdrawable *drawable = rmesa->driDrawable; int x1 = 0; int y1 = 0; int x2 = drawable->w - 1; diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c index 5f985d624d..f34e319222 100644 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ b/src/mesa/drivers/dri/r200/r200_context.c @@ -274,10 +274,10 @@ static void r200_init_vtbl(radeonContextPtr radeon) /* Create the device specific rendering context. */ GLboolean r200CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate) { - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; r200ContextPtr rmesa; @@ -496,7 +496,7 @@ GLboolean r200CreateContext( const __GLcontextModes *glVisual, } -void r200DestroyContext( __DRIcontextPrivate *driContextPriv ) +void r200DestroyContext( __DRIcontext *driContextPriv ) { int i; r200ContextPtr rmesa = (r200ContextPtr)driContextPriv->driverPrivate; diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h index 246f98c6dc..17e4d8962e 100644 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ b/src/mesa/drivers/dri/r200/r200_context.h @@ -636,14 +636,14 @@ struct r200_context { #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) -extern void r200DestroyContext( __DRIcontextPrivate *driContextPriv ); +extern void r200DestroyContext( __DRIcontext *driContextPriv ); extern GLboolean r200CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate); -extern GLboolean r200MakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ); -extern GLboolean r200UnbindContext( __DRIcontextPrivate *driContextPriv ); +extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ); +extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv ); /* ================================================================ * Debugging: diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c index b238adb972..66c5d3655a 100644 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ b/src/mesa/drivers/dri/r200/r200_ioctl.c @@ -61,7 +61,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. static void r200KernelClear(GLcontext *ctx, GLuint flags) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLint cx, cy, cw, ch, ret; GLuint i; @@ -185,7 +185,7 @@ static void r200KernelClear(GLcontext *ctx, GLuint flags) static void r200Clear( GLcontext *ctx, GLbitfield mask ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLuint flags = 0; GLuint color_mask = 0; GLuint orig_mask = mask; diff --git a/src/mesa/drivers/dri/r200/r200_pixel.c b/src/mesa/drivers/dri/r200/r200_pixel.c index 94e43c7d66..bfb7e2a2ed 100644 --- a/src/mesa/drivers/dri/r200/r200_pixel.c +++ b/src/mesa/drivers/dri/r200/r200_pixel.c @@ -214,7 +214,7 @@ r200TryReadPixels( GLcontext *ctx, } { - __DRIdrawablePrivate *dPriv = rmesa->radeon.dri.drawable; + __DRIdrawable *dPriv = rmesa->radeon.dri.drawable; driRenderbuffer *drb = (driRenderbuffer *) ctx->ReadBuffer->_ColorReadBuffer; int nbox = dPriv->numClipRects; int src_offset = drb->offset @@ -298,7 +298,7 @@ static void do_draw_pix( GLcontext *ctx, #if 0 r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); drm_clip_rect_t *box = dPriv->pClipRects; struct gl_renderbuffer *rb = ctx->ReadBuffer->_ColorDrawBuffers[0]; driRenderbuffer *drb = (driRenderbuffer *) rb; diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c index 529cb62264..7fe482fe15 100644 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ b/src/mesa/drivers/dri/r200/r200_state.c @@ -1585,7 +1585,7 @@ static void r200ClearStencil( GLcontext *ctx, GLint s ) void r200UpdateWindow( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1665,7 +1665,7 @@ static void r200DepthRange( GLcontext *ctx, GLclampd nearval, void r200UpdateViewportOffset( GLcontext *ctx ) { r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c index 3c6ec2a34a..1f6ccf6ddc 100644 --- a/src/mesa/drivers/dri/r300/r300_context.c +++ b/src/mesa/drivers/dri/r300/r300_context.c @@ -463,10 +463,10 @@ static void r300InitIoctlFuncs(struct dd_function_table *functions) /* Create the device specific rendering context. */ GLboolean r300CreateContext(const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate) { - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); struct dd_function_table functions; r300ContextPtr r300; diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h index 54a92a2e44..546cd8ddde 100644 --- a/src/mesa/drivers/dri/r300/r300_context.h +++ b/src/mesa/drivers/dri/r300/r300_context.h @@ -543,9 +543,9 @@ struct r300_context { #define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx)) -extern void r300DestroyContext(__DRIcontextPrivate * driContextPriv); +extern void r300DestroyContext(__DRIcontext * driContextPriv); extern GLboolean r300CreateContext(const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); extern void r300InitShaderFuncs(struct dd_function_table *functions); diff --git a/src/mesa/drivers/dri/r300/r300_state.c b/src/mesa/drivers/dri/r300/r300_state.c index f90bfd4f4f..c51285aad9 100644 --- a/src/mesa/drivers/dri/r300/r300_state.c +++ b/src/mesa/drivers/dri/r300/r300_state.c @@ -997,7 +997,7 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face, static void r300UpdateWindow(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1050,7 +1050,7 @@ static void r300DepthRange(GLcontext * ctx, GLclampd nearval, GLclampd farval) void r300UpdateViewportOffset(GLcontext * ctx) { r300ContextPtr rmesa = R300_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = (GLfloat) dPriv->x; GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -2040,7 +2040,7 @@ static const GLfloat *get_fragmentprogram_constant(GLcontext *ctx, GLuint index, } case RC_STATE_R300_WINDOW_DIMENSION: { - __DRIdrawablePrivate * drawable = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable * drawable = radeon_get_drawable(&rmesa->radeon); buffer[0] = drawable->w * 0.5f; /* width*0.5 */ buffer[1] = drawable->h * 0.5f; /* height*0.5 */ buffer[2] = 0.5F; /* for moving range [-1 1] -> [0 1] */ diff --git a/src/mesa/drivers/dri/r600/r600_context.c b/src/mesa/drivers/dri/r600/r600_context.c index 45bbc3c071..0d8b5b45ac 100644 --- a/src/mesa/drivers/dri/r600/r600_context.c +++ b/src/mesa/drivers/dri/r600/r600_context.c @@ -345,10 +345,10 @@ static void r600InitGLExtensions(GLcontext *ctx) /* Create the device specific rendering context. */ GLboolean r600CreateContext(const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate) { - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); struct dd_function_table functions; context_t *r600; diff --git a/src/mesa/drivers/dri/r600/r600_context.h b/src/mesa/drivers/dri/r600/r600_context.h index 94662ab547..a1b4af715e 100644 --- a/src/mesa/drivers/dri/r600/r600_context.h +++ b/src/mesa/drivers/dri/r600/r600_context.h @@ -154,7 +154,7 @@ struct r600_context { #define GL_CONTEXT(context) ((GLcontext *)(context->radeon.glCtx)) extern GLboolean r600CreateContext(const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); #define R700_CONTEXT_STATES(context) ((R700_CHIP_CONTEXT *)(&context->hw)) diff --git a/src/mesa/drivers/dri/r600/r700_clear.c b/src/mesa/drivers/dri/r600/r700_clear.c index c0ac54a844..98bfdd0937 100644 --- a/src/mesa/drivers/dri/r600/r700_clear.c +++ b/src/mesa/drivers/dri/r600/r700_clear.c @@ -49,7 +49,7 @@ static GLboolean r700ClearFast(context_t *context, GLbitfield mask) void r700Clear(GLcontext * ctx, GLbitfield mask) { context_t *context = R700_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon); const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask[0]); GLbitfield swrast_mask = 0, tri_mask = 0; int i; diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c index fc6fb29fd6..3c8cb579f9 100644 --- a/src/mesa/drivers/dri/r600/r700_state.c +++ b/src/mesa/drivers/dri/r600/r700_state.c @@ -85,7 +85,7 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------ { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon); GLfloat xoffset = (GLfloat) dPriv->x; GLfloat yoffset = (GLfloat) dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1071,7 +1071,7 @@ static void r700UpdateWindow(GLcontext * ctx, int id) //-------------------- { context_t *context = R700_CONTEXT(ctx); R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&context->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&context->radeon); GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c index c0b3165dda..e0b853bc97 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.c +++ b/src/mesa/drivers/dri/radeon/radeon_common.c @@ -137,7 +137,7 @@ void radeon_get_cliprects(radeonContextPtr radeon, unsigned int *num_cliprects, int *x_off, int *y_off) { - __DRIdrawablePrivate *dPriv = radeon_get_drawable(radeon); + __DRIdrawable *dPriv = radeon_get_drawable(radeon); struct radeon_framebuffer *rfb = dPriv->driverPrivate; if (radeon->constant_cliprect) { @@ -169,8 +169,8 @@ void radeon_get_cliprects(radeonContextPtr radeon, */ void radeonSetCliprects(radeonContextPtr radeon) { - __DRIdrawablePrivate *const drawable = radeon_get_drawable(radeon); - __DRIdrawablePrivate *const readable = radeon_get_readable(radeon); + __DRIdrawable *const drawable = radeon_get_drawable(radeon); + __DRIdrawable *const readable = radeon_get_readable(radeon); struct radeon_framebuffer *const draw_rfb = drawable->driverPrivate; struct radeon_framebuffer *const read_rfb = readable->driverPrivate; int x_off, y_off; @@ -229,7 +229,7 @@ void radeonUpdateScissor( GLcontext *ctx ) } if (!rmesa->radeonScreen->kernel_mm) { /* Fix scissors for dri 1 */ - __DRIdrawablePrivate *dPriv = radeon_get_drawable(rmesa); + __DRIdrawable *dPriv = radeon_get_drawable(rmesa); x1 += dPriv->x; x2 += dPriv->x + 1; min_x += dPriv->x; @@ -428,7 +428,7 @@ static void radeon_flip_renderbuffers(struct radeon_framebuffer *rfb) /* Copy the back color buffer to the front color buffer. */ -void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, +void radeonCopyBuffer( __DRIdrawable *dPriv, const drm_clip_rect_t *rect) { radeonContextPtr rmesa; @@ -496,7 +496,7 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, UNLOCK_HARDWARE( rmesa ); } -static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_target) +static int radeonScheduleSwap(__DRIdrawable *dPriv, GLboolean *missed_target) { radeonContextPtr rmesa; @@ -519,11 +519,11 @@ static int radeonScheduleSwap(__DRIdrawablePrivate *dPriv, GLboolean *missed_tar return 0; } -static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) +static GLboolean radeonPageFlip( __DRIdrawable *dPriv ) { radeonContextPtr radeon; GLint ret; - __DRIscreenPrivate *psp; + __DRIscreen *psp; struct radeon_renderbuffer *rrb; struct radeon_framebuffer *rfb; @@ -571,10 +571,10 @@ static GLboolean radeonPageFlip( __DRIdrawablePrivate *dPriv ) /** * Swap front and back buffer. */ -void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) +void radeonSwapBuffers(__DRIdrawable * dPriv) { int64_t ust; - __DRIscreenPrivate *psp; + __DRIscreen *psp; if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { radeonContextPtr radeon; @@ -615,7 +615,7 @@ void radeonSwapBuffers(__DRIdrawablePrivate * dPriv) } } -void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, +void radeonCopySubBuffer(__DRIdrawable * dPriv, int x, int y, int w, int h ) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { @@ -1130,7 +1130,7 @@ flush_front: if (screen->dri2.loader && (screen->dri2.loader->base.version >= 2) && (screen->dri2.loader->flushFrontBuffer != NULL)) { - __DRIdrawablePrivate * drawable = radeon_get_drawable(radeon); + __DRIdrawable * drawable = radeon_get_drawable(radeon); (*screen->dri2.loader->flushFrontBuffer)(drawable, drawable->loaderPrivate); /* Only clear the dirty bit if front-buffer rendering is no longer diff --git a/src/mesa/drivers/dri/radeon/radeon_common.h b/src/mesa/drivers/dri/radeon/radeon_common.h index faad145cc4..f31f08edf3 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common.h +++ b/src/mesa/drivers/dri/radeon/radeon_common.h @@ -13,10 +13,10 @@ void radeonScissor(GLcontext* ctx, GLint x, GLint y, GLsizei w, GLsizei h); void radeonWaitForIdleLocked(radeonContextPtr radeon); extern uint32_t radeonGetAge(radeonContextPtr radeon); -void radeonCopyBuffer( __DRIdrawablePrivate *dPriv, +void radeonCopyBuffer( __DRIdrawable *dPriv, const drm_clip_rect_t *rect); -void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); -void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, +void radeonSwapBuffers(__DRIdrawable * dPriv); +void radeonCopySubBuffer(__DRIdrawable * dPriv, int x, int y, int w, int h ); void radeonUpdatePageFlipping(radeonContextPtr rmesa); @@ -42,7 +42,7 @@ void radeon_renderbuffer_set_bo(struct radeon_renderbuffer *rb, struct radeon_bo *bo); struct radeon_renderbuffer * -radeon_create_renderbuffer(gl_format format, __DRIdrawablePrivate *driDrawPriv); +radeon_create_renderbuffer(gl_format format, __DRIdrawable *driDrawPriv); void radeon_check_front_buffer_rendering(GLcontext *ctx); static inline struct radeon_renderbuffer *radeon_renderbuffer(struct gl_renderbuffer *rb) diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.c b/src/mesa/drivers/dri/radeon/radeon_common_context.c index 5c68bf5df6..b9c29b937e 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.c @@ -181,10 +181,10 @@ static void radeonInitDriverFuncs(struct dd_function_table *functions) GLboolean radeonInitContext(radeonContextPtr radeon, struct dd_function_table* functions, const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate) { - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); GLcontext* ctx; GLcontext* shareCtx; @@ -291,7 +291,7 @@ static void radeon_destroy_atom_list(radeonContextPtr radeon) * Cleanup common context fields. * Called by r200DestroyContext/r300DestroyContext */ -void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) +void radeonDestroyContext(__DRIcontext *driContextPriv ) { #ifdef RADEON_BO_TRACK FILE *track; @@ -355,7 +355,7 @@ void radeonDestroyContext(__DRIcontextPrivate *driContextPriv ) /* Force the context `c' to be unbound from its buffer. */ -GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv) +GLboolean radeonUnbindContext(__DRIcontext * driContextPriv) { radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; @@ -720,9 +720,9 @@ radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable, /* Force the context `c' to be the current context and associate with it * buffer `b'. */ -GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv) +GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv, + __DRIdrawable * driDrawPriv, + __DRIdrawable * driReadPriv) { radeonContextPtr radeon; struct radeon_framebuffer *drfb; diff --git a/src/mesa/drivers/dri/radeon/radeon_common_context.h b/src/mesa/drivers/dri/radeon/radeon_common_context.h index 0739496e03..ab79d2dc0f 100644 --- a/src/mesa/drivers/dri/radeon/radeon_common_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_common_context.h @@ -92,7 +92,7 @@ struct radeon_renderbuffer GLuint pf_pending; /**< sequence number of pending flip */ GLuint vbl_pending; /**< vblank sequence number of pending flip */ - __DRIdrawablePrivate *dPriv; + __DRIdrawable *dPriv; }; struct radeon_framebuffer @@ -381,8 +381,8 @@ struct radeon_store { }; struct radeon_dri_mirror { - __DRIcontextPrivate *context; /* DRI context */ - __DRIscreenPrivate *screen; /* DRI screen */ + __DRIcontext *context; /* DRI context */ + __DRIscreen *screen; /* DRI screen */ drm_context_t hwContext; drm_hw_lock_t *hwLock; @@ -523,12 +523,12 @@ struct radeon_context { #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx)) -static inline __DRIdrawablePrivate* radeon_get_drawable(radeonContextPtr radeon) +static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon) { return radeon->dri.context->driDrawablePriv; } -static inline __DRIdrawablePrivate* radeon_get_readable(radeonContextPtr radeon) +static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon) { return radeon->dri.context->driReadablePriv; } @@ -581,16 +581,16 @@ static INLINE uint32_t radeonPackFloat24(float f) GLboolean radeonInitContext(radeonContextPtr radeon, struct dd_function_table* functions, const __GLcontextModes * glVisual, - __DRIcontextPrivate * driContextPriv, + __DRIcontext * driContextPriv, void *sharedContextPrivate); void radeonCleanupContext(radeonContextPtr radeon); -GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); +GLboolean radeonUnbindContext(__DRIcontext * driContextPriv); void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable, GLboolean front_only); -GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, - __DRIdrawablePrivate * driDrawPriv, - __DRIdrawablePrivate * driReadPriv); -extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); +GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv, + __DRIdrawable * driDrawPriv, + __DRIdrawable * driReadPriv); +extern void radeonDestroyContext(__DRIcontext * driContextPriv); #endif diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 5e700be4a5..3cd305b0a2 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -208,10 +208,10 @@ static void r100_init_vtbl(radeonContextPtr radeon) */ GLboolean r100CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate) { - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; radeonScreenPtr screen = (radeonScreenPtr)(sPriv->private); struct dd_function_table functions; r100ContextPtr rmesa; diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index 12ab33a009..dfedc38bfd 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -451,7 +451,7 @@ struct r100_context { #define RADEON_OLD_PACKETS 1 extern GLboolean r100CreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate); diff --git a/src/mesa/drivers/dri/radeon/radeon_fbo.c b/src/mesa/drivers/dri/radeon/radeon_fbo.c index a536436d55..7b1f84a715 100644 --- a/src/mesa/drivers/dri/radeon/radeon_fbo.c +++ b/src/mesa/drivers/dri/radeon/radeon_fbo.c @@ -247,7 +247,7 @@ radeon_nop_alloc_storage(GLcontext * ctx, struct gl_renderbuffer *rb, * Not used for user-created renderbuffers. */ struct radeon_renderbuffer * -radeon_create_renderbuffer(gl_format format, __DRIdrawablePrivate *driDrawPriv) +radeon_create_renderbuffer(gl_format format, __DRIdrawable *driDrawPriv) { struct radeon_renderbuffer *rrb; diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 13fd6f9971..a9d50c5d07 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -449,7 +449,7 @@ void radeonEmitAOS( r100ContextPtr rmesa, static void radeonKernelClear(GLcontext *ctx, GLuint flags) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); drm_radeon_sarea_t *sarea = rmesa->radeon.sarea; uint32_t clear; GLint ret, i; @@ -570,7 +570,7 @@ static void radeonKernelClear(GLcontext *ctx, GLuint flags) static void radeonClear( GLcontext *ctx, GLbitfield mask ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLuint flags = 0; GLuint color_mask = 0; GLuint orig_mask = mask; diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index 7ad781ba61..9dee691938 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -58,9 +58,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ void radeonGetLock(radeonContextPtr rmesa, GLuint flags) { - __DRIdrawablePrivate *const drawable = radeon_get_drawable(rmesa); - __DRIdrawablePrivate *const readable = radeon_get_readable(rmesa); - __DRIscreenPrivate *sPriv = rmesa->dri.screen; + __DRIdrawable *const drawable = radeon_get_drawable(rmesa); + __DRIdrawable *const readable = radeon_get_readable(rmesa); + __DRIscreen *sPriv = rmesa->dri.screen; drmGetLock(rmesa->dri.fd, rmesa->dri.hwContext, flags); diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index be2d8365ef..801d7e147c 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -214,10 +214,10 @@ static const GLuint __driNConfigOptions = 17; #endif -static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); +static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ); static int -radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) +radeonGetParam(__DRIscreen *sPriv, int param, void *value) { int ret; drm_radeon_getparam_t gp = { 0 }; @@ -249,7 +249,7 @@ radeonGetParam(__DRIscreenPrivate *sPriv, int param, void *value) } static const __DRIconfig ** -radeonFillInModes( __DRIscreenPrivate *psp, +radeonFillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { @@ -911,7 +911,7 @@ static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id) /* Create the device specific screen private data struct. */ static radeonScreenPtr -radeonCreateScreen( __DRIscreenPrivate *sPriv ) +radeonCreateScreen( __DRIscreen *sPriv ) { radeonScreenPtr screen; RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; @@ -1250,7 +1250,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) } static radeonScreenPtr -radeonCreateScreen2(__DRIscreenPrivate *sPriv) +radeonCreateScreen2(__DRIscreen *sPriv) { radeonScreenPtr screen; int i; @@ -1401,7 +1401,7 @@ radeonCreateScreen2(__DRIscreenPrivate *sPriv) /* Destroy the device specific screen private data struct. */ static void -radeonDestroyScreen( __DRIscreenPrivate *sPriv ) +radeonDestroyScreen( __DRIscreen *sPriv ) { radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; @@ -1435,7 +1435,7 @@ radeonDestroyScreen( __DRIscreenPrivate *sPriv ) /* Initialize the driver specific screen private data. */ static GLboolean -radeonInitDriver( __DRIscreenPrivate *sPriv ) +radeonInitDriver( __DRIscreen *sPriv ) { if (sPriv->dri2.enabled) { sPriv->private = (void *) radeonCreateScreen2( sPriv ); @@ -1459,8 +1459,8 @@ radeonInitDriver( __DRIscreenPrivate *sPriv ) * pbuffers. */ static GLboolean -radeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +radeonCreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -1559,7 +1559,7 @@ static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb) } void -radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +radeonDestroyBuffer(__DRIdrawable *driDrawPriv) { struct radeon_framebuffer *rfb; if (!driDrawPriv) @@ -1581,7 +1581,7 @@ radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) * \return the __GLcontextModes supported by this driver */ static const __DRIconfig ** -radeonInitScreen(__DRIscreenPrivate *psp) +radeonInitScreen(__DRIscreen *psp) { #if defined(RADEON_R100) static const char *driver_name = "Radeon"; @@ -1631,7 +1631,7 @@ radeonInitScreen(__DRIscreenPrivate *psp) * \return the __GLcontextModes supported by this driver */ static const -__DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) +__DRIconfig **radeonInitScreen2(__DRIscreen *psp) { GLenum fb_format[3]; GLenum fb_type[3]; @@ -1698,7 +1698,7 @@ __DRIconfig **radeonInitScreen2(__DRIscreenPrivate *psp) * Get information about previous buffer swaps. */ static int -getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) +getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ) { struct radeon_framebuffer *rfb; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 15744e8828..5e6d432e11 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -86,7 +86,7 @@ typedef struct radeon_screen { __volatile__ uint32_t *scratch; - __DRIscreenPrivate *driScreen; + __DRIscreen *driScreen; unsigned int sarea_priv_offset; unsigned int gart_buffer_offset; /* offset in card memory space */ unsigned int gart_texture_offset; /* offset in card memory space */ @@ -123,5 +123,5 @@ typedef struct radeon_screen { #define IS_R600_CLASS(screen) \ ((screen->chip_flags & RADEON_CLASS_MASK) == RADEON_CLASS_R600) -extern void radeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv); +extern void radeonDestroyBuffer(__DRIdrawable *driDrawPriv); #endif /* __RADEON_SCREEN_H__ */ diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index 1fcb545204..1c9ec36dae 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1400,7 +1400,7 @@ static void radeonClearStencil( GLcontext *ctx, GLint s ) void radeonUpdateWindow( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = dPriv ? (GLfloat) dPriv->x : 0; GLfloat yoffset = dPriv ? (GLfloat) dPriv->y + dPriv->h : 0; const GLfloat *v = ctx->Viewport._WindowMap.m; @@ -1455,7 +1455,7 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval, void radeonUpdateViewportOffset( GLcontext *ctx ) { r100ContextPtr rmesa = R100_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = radeon_get_drawable(&rmesa->radeon); + __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); GLfloat xoffset = (GLfloat)dPriv->x; GLfloat yoffset = (GLfloat)dPriv->y + dPriv->h; const GLfloat *v = ctx->Viewport._WindowMap.m; diff --git a/src/mesa/drivers/dri/savage/savage_init.h b/src/mesa/drivers/dri/savage/savage_init.h index abb8440fc4..bfd3077d70 100644 --- a/src/mesa/drivers/dri/savage/savage_init.h +++ b/src/mesa/drivers/dri/savage/savage_init.h @@ -66,7 +66,7 @@ typedef struct { unsigned int logTextureGranularity[SAVAGE_NR_TEX_HEAPS]; drmAddress texVirtual[SAVAGE_NR_TEX_HEAPS]; - __DRIscreenPrivate *driScrnPriv; + __DRIscreen *driScrnPriv; savageRegion aperture; savageRegion agpTextures; diff --git a/src/mesa/drivers/dri/savage/savage_xmesa.c b/src/mesa/drivers/dri/savage/savage_xmesa.c index d307b81e8e..564e68eb89 100644 --- a/src/mesa/drivers/dri/savage/savage_xmesa.c +++ b/src/mesa/drivers/dri/savage/savage_xmesa.c @@ -168,7 +168,7 @@ PUBLIC const __DRIextension *savageScreenExtensions[] = { }; static GLboolean -savageInitDriver(__DRIscreenPrivate *sPriv) +savageInitDriver(__DRIscreen *sPriv) { savageScreenPrivate *savageScreen; SAVAGEDRIPtr gDRIPriv = (SAVAGEDRIPtr)sPriv->pDevPriv; @@ -272,7 +272,7 @@ savageInitDriver(__DRIscreenPrivate *sPriv) /* Accessed by dlsym from dri_mesa_init.c */ static void -savageDestroyScreen(__DRIscreenPrivate *sPriv) +savageDestroyScreen(__DRIscreen *sPriv) { savageScreenPrivate *savageScreen = (savageScreenPrivate *)sPriv->private; @@ -288,12 +288,12 @@ savageDestroyScreen(__DRIscreenPrivate *sPriv) static GLboolean savageCreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ) { GLcontext *ctx, *shareCtx; savageContextPtr imesa; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; struct dd_function_table functions; savageScreenPrivate *savageScreen = (savageScreenPrivate *)sPriv->private; drm_savage_sarea_t *saPriv=(drm_savage_sarea_t *)(((char*)sPriv->pSAREA)+ @@ -546,7 +546,7 @@ savageCreateContext( const __GLcontextModes *mesaVis, } static void -savageDestroyContext(__DRIcontextPrivate *driContextPriv) +savageDestroyContext(__DRIcontext *driContextPriv) { savageContextPtr imesa = (savageContextPtr) driContextPriv->driverPrivate; GLuint i; @@ -580,8 +580,8 @@ savageDestroyContext(__DRIcontextPrivate *driContextPriv) static GLboolean -savageCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +savageCreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap) { @@ -675,13 +675,13 @@ savageCreateBuffer( __DRIscreenPrivate *driScrnPriv, } static void -savageDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +savageDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } #if 0 -void XMesaSwapBuffers(__DRIdrawablePrivate *driDrawPriv) +void XMesaSwapBuffers(__DRIdrawable *driDrawPriv) { /* XXX should do swap according to the buffer, not the context! */ savageContextPtr imesa = savageCtx; @@ -694,7 +694,7 @@ void XMesaSwapBuffers(__DRIdrawablePrivate *driDrawPriv) void savageXMesaSetClipRects(savageContextPtr imesa) { - __DRIdrawablePrivate *dPriv = imesa->driDrawable; + __DRIdrawable *dPriv = imesa->driDrawable; if ((dPriv->numBackClipRects == 0) || (imesa->glCtx->DrawBuffer->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT)) { @@ -715,8 +715,8 @@ void savageXMesaSetClipRects(savageContextPtr imesa) static void savageXMesaWindowMoved( savageContextPtr imesa ) { - __DRIdrawablePrivate *const drawable = imesa->driDrawable; - __DRIdrawablePrivate *const readable = imesa->driReadable; + __DRIdrawable *const drawable = imesa->driDrawable; + __DRIdrawable *const readable = imesa->driReadable; if (0) fprintf(stderr, "savageXMesaWindowMoved\n\n"); @@ -731,7 +731,7 @@ static void savageXMesaWindowMoved( savageContextPtr imesa ) static GLboolean -savageUnbindContext(__DRIcontextPrivate *driContextPriv) +savageUnbindContext(__DRIcontext *driContextPriv) { savageContextPtr savage = (savageContextPtr) driContextPriv->driverPrivate; if (savage) @@ -742,7 +742,7 @@ savageUnbindContext(__DRIcontextPrivate *driContextPriv) #if 0 static GLboolean -savageOpenFullScreen(__DRIcontextPrivate *driContextPriv) +savageOpenFullScreen(__DRIcontext *driContextPriv) { @@ -761,7 +761,7 @@ savageOpenFullScreen(__DRIcontextPrivate *driContextPriv) } static GLboolean -savageCloseFullScreen(__DRIcontextPrivate *driContextPriv) +savageCloseFullScreen(__DRIcontext *driContextPriv) { if (driContextPriv) { @@ -777,9 +777,9 @@ savageCloseFullScreen(__DRIcontextPrivate *driContextPriv) #endif static GLboolean -savageMakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv) +savageMakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv) { if (driContextPriv) { savageContextPtr imesa @@ -816,9 +816,9 @@ savageMakeCurrent(__DRIcontextPrivate *driContextPriv, void savageGetLock( savageContextPtr imesa, GLuint flags ) { - __DRIdrawablePrivate *const drawable = imesa->driDrawable; - __DRIdrawablePrivate *const readable = imesa->driReadable; - __DRIscreenPrivate *sPriv = imesa->driScreen; + __DRIdrawable *const drawable = imesa->driDrawable; + __DRIdrawable *const readable = imesa->driReadable; + __DRIscreen *sPriv = imesa->driScreen; drm_savage_sarea_t *sarea = imesa->sarea; int me = imesa->hHWContext; int stamp = drawable->lastStamp; @@ -883,7 +883,7 @@ void savageGetLock( savageContextPtr imesa, GLuint flags ) } static const __DRIconfig ** -savageFillInModes( __DRIscreenPrivate *psp, +savageFillInModes( __DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, GLboolean have_back_buffer ) { @@ -967,7 +967,7 @@ savageFillInModes( __DRIscreenPrivate *psp, * \return the __GLcontextModes supported by this driver */ static const __DRIconfig ** -savageInitScreen(__DRIscreenPrivate *psp) +savageInitScreen(__DRIscreen *psp) { static const __DRIversion ddx_expected = { 2, 0, 0 }; static const __DRIversion dri_expected = { 4, 0, 0 }; diff --git a/src/mesa/drivers/dri/savage/savagecontext.h b/src/mesa/drivers/dri/savage/savagecontext.h index 53a37db1cb..ba1e6e1e1a 100644 --- a/src/mesa/drivers/dri/savage/savagecontext.h +++ b/src/mesa/drivers/dri/savage/savagecontext.h @@ -271,10 +271,10 @@ struct savage_context_t { drm_hw_lock_t *driHwLock; GLuint driFd; - __DRIdrawablePrivate *driDrawable; - __DRIdrawablePrivate *driReadable; + __DRIdrawable *driDrawable; + __DRIdrawable *driReadable; - __DRIscreenPrivate *driScreen; + __DRIscreen *driScreen; savageScreenPrivate *savageScreen; drm_savage_sarea_t *sarea; diff --git a/src/mesa/drivers/dri/savage/savageioctl.c b/src/mesa/drivers/dri/savage/savageioctl.c index 706fc97935..d0b64e801a 100644 --- a/src/mesa/drivers/dri/savage/savageioctl.c +++ b/src/mesa/drivers/dri/savage/savageioctl.c @@ -433,7 +433,7 @@ static void savageDDClear( GLcontext *ctx, GLbitfield mask ) /* * Copy the back buffer to the front buffer. */ -void savageSwapBuffers( __DRIdrawablePrivate *dPriv ) +void savageSwapBuffers( __DRIdrawable *dPriv ) { savageContextPtr imesa; @@ -537,7 +537,7 @@ void savageFlushVertices( savageContextPtr imesa ) void savageFlushCmdBufLocked( savageContextPtr imesa, GLboolean discard ) { - __DRIdrawablePrivate *dPriv = imesa->driDrawable; + __DRIdrawable *dPriv = imesa->driDrawable; if (!imesa->dmaVtxBuf.total) discard = GL_FALSE; diff --git a/src/mesa/drivers/dri/savage/savageioctl.h b/src/mesa/drivers/dri/savage/savageioctl.h index 639605cc51..e7e80816c1 100644 --- a/src/mesa/drivers/dri/savage/savageioctl.h +++ b/src/mesa/drivers/dri/savage/savageioctl.h @@ -39,7 +39,7 @@ void savageFlushCmdBuf( savageContextPtr imesa, GLboolean discard ); void savageDDInitIoctlFuncs( GLcontext *ctx ); -void savageSwapBuffers( __DRIdrawablePrivate *dPriv ); +void savageSwapBuffers( __DRIdrawable *dPriv ); #define WAIT_IDLE_EMPTY(imesa) do { \ if (SAVAGE_DEBUG & DEBUG_VERBOSE_MSG) \ diff --git a/src/mesa/drivers/dri/savage/savagespan.c b/src/mesa/drivers/dri/savage/savagespan.c index 3bb6fbcc63..792e166d9c 100644 --- a/src/mesa/drivers/dri/savage/savagespan.c +++ b/src/mesa/drivers/dri/savage/savagespan.c @@ -34,7 +34,7 @@ #define LOCAL_VARS \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ - __DRIdrawablePrivate *const dPriv = drb->dPriv; \ + __DRIdrawable *const dPriv = drb->dPriv; \ GLuint cpp = drb->cpp; \ GLuint pitch = drb->pitch; \ GLuint height = dPriv->h; \ @@ -44,7 +44,7 @@ #define LOCAL_DEPTH_VARS \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ - __DRIdrawablePrivate *const dPriv = drb->dPriv; \ + __DRIdrawable *const dPriv = drb->dPriv; \ GLuint zpp = drb->cpp; \ GLuint pitch = drb->pitch; \ GLuint height = dPriv->h; \ diff --git a/src/mesa/drivers/dri/sis/sis_context.c b/src/mesa/drivers/dri/sis/sis_context.c index f501e7ad2e..1f88e9ccdd 100644 --- a/src/mesa/drivers/dri/sis/sis_context.c +++ b/src/mesa/drivers/dri/sis/sis_context.c @@ -160,11 +160,11 @@ void sisReAllocateBuffers(GLcontext *ctx, GLframebuffer *drawbuffer, GLboolean sisCreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ) { GLcontext *ctx, *shareCtx; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; sisContextPtr smesa; sisScreenPtr sisScreen; int i; @@ -337,7 +337,7 @@ sisCreateContext( const __GLcontextModes *glVisual, } void -sisDestroyContext ( __DRIcontextPrivate *driContextPriv ) +sisDestroyContext ( __DRIcontext *driContextPriv ) { sisContextPtr smesa = (sisContextPtr)driContextPriv->driverPrivate; @@ -365,9 +365,9 @@ sisDestroyContext ( __DRIcontextPrivate *driContextPriv ) } GLboolean -sisMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) +sisMakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ) { if ( driContextPriv ) { GET_CURRENT_CONTEXT(ctx); @@ -396,7 +396,7 @@ sisMakeCurrent( __DRIcontextPrivate *driContextPriv, } GLboolean -sisUnbindContext( __DRIcontextPrivate *driContextPriv ) +sisUnbindContext( __DRIcontext *driContextPriv ) { return GL_TRUE; } diff --git a/src/mesa/drivers/dri/sis/sis_context.h b/src/mesa/drivers/dri/sis/sis_context.h index bc53cb5efa..4179ee081a 100644 --- a/src/mesa/drivers/dri/sis/sis_context.h +++ b/src/mesa/drivers/dri/sis/sis_context.h @@ -359,9 +359,9 @@ struct sis_context /* Mirrors of some DRI state */ - __DRIcontextPrivate *driContext; /* DRI context */ - __DRIscreenPrivate *driScreen; /* DRI screen */ - __DRIdrawablePrivate *driDrawable; /* DRI drawable bound to this ctx */ + __DRIcontext *driContext; /* DRI context */ + __DRIscreen *driScreen; /* DRI screen */ + __DRIdrawable *driDrawable; /* DRI drawable bound to this ctx */ unsigned int lastStamp; /* mirror driDrawable->lastStamp */ @@ -439,18 +439,18 @@ enum _sis_verbose { }; extern GLboolean sisCreateContext( const __GLcontextModes *glVisual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ); -extern void sisDestroyContext( __DRIcontextPrivate * ); +extern void sisDestroyContext( __DRIcontext * ); void sisReAllocateBuffers(GLcontext *ctx, GLframebuffer *drawbuffer, GLuint width, GLuint height); -extern GLboolean sisMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ); +extern GLboolean sisMakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ); -extern GLboolean sisUnbindContext( __DRIcontextPrivate *driContextPriv ); +extern GLboolean sisUnbindContext( __DRIcontext *driContextPriv ); void WaitEngIdle (sisContextPtr smesa); void Wait2DEngIdle (sisContextPtr smesa); diff --git a/src/mesa/drivers/dri/sis/sis_lock.c b/src/mesa/drivers/dri/sis/sis_lock.c index 806110cad4..b8ff4e31e2 100644 --- a/src/mesa/drivers/dri/sis/sis_lock.c +++ b/src/mesa/drivers/dri/sis/sis_lock.c @@ -46,8 +46,8 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. void sisGetLock( sisContextPtr smesa, GLuint flags ) { - __DRIdrawablePrivate *dPriv = smesa->driDrawable; - __DRIscreenPrivate *sPriv = smesa->driScreen; + __DRIdrawable *dPriv = smesa->driDrawable; + __DRIscreen *sPriv = smesa->driScreen; SISSAREAPrivPtr sarea = smesa->sarea; drmGetLock( smesa->driFd, smesa->hHWContext, flags ); diff --git a/src/mesa/drivers/dri/sis/sis_screen.c b/src/mesa/drivers/dri/sis/sis_screen.c index fec9158236..f39a51ab69 100644 --- a/src/mesa/drivers/dri/sis/sis_screen.c +++ b/src/mesa/drivers/dri/sis/sis_screen.c @@ -65,7 +65,7 @@ static const GLuint __driNConfigOptions = 3; extern const struct dri_extension card_extensions[]; static const __DRIconfig ** -sisFillInModes(__DRIscreenPrivate *psp, int bpp) +sisFillInModes(__DRIscreen *psp, int bpp) { __DRIconfig **configs; unsigned depth_buffer_factor; @@ -117,7 +117,7 @@ sisFillInModes(__DRIscreenPrivate *psp, int bpp) /* Create the device specific screen private data struct. */ static sisScreenPtr -sisCreateScreen( __DRIscreenPrivate *sPriv ) +sisCreateScreen( __DRIscreen *sPriv ) { sisScreenPtr sisScreen; SISDRIPtr sisDRIPriv = (SISDRIPtr)sPriv->pDevPriv; @@ -172,7 +172,7 @@ sisCreateScreen( __DRIscreenPrivate *sPriv ) /* Destroy the device specific screen private data struct. */ static void -sisDestroyScreen( __DRIscreenPrivate *sPriv ) +sisDestroyScreen( __DRIscreen *sPriv ) { sisScreenPtr sisScreen = (sisScreenPtr)sPriv->private; @@ -192,8 +192,8 @@ sisDestroyScreen( __DRIscreenPrivate *sPriv ) * data. */ static GLboolean -sisCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +sisCreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -219,12 +219,12 @@ sisCreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -sisDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +sisDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } -static void sisCopyBuffer( __DRIdrawablePrivate *dPriv ) +static void sisCopyBuffer( __DRIdrawable *dPriv ) { sisContextPtr smesa = (sisContextPtr)dPriv->driContextPriv->driverPrivate; int i; @@ -259,7 +259,7 @@ static void sisCopyBuffer( __DRIdrawablePrivate *dPriv ) /* Copy the back color buffer to the front color buffer */ static void -sisSwapBuffers(__DRIdrawablePrivate *dPriv) +sisSwapBuffers(__DRIdrawable *dPriv) { if (dPriv->driContextPriv && dPriv->driContextPriv->driverPrivate) { sisContextPtr smesa = (sisContextPtr) dPriv->driContextPriv->driverPrivate; @@ -284,7 +284,7 @@ sisSwapBuffers(__DRIdrawablePrivate *dPriv) * \return the __GLcontextModes supported by this driver */ static const __DRIconfig ** -sisInitScreen(__DRIscreenPrivate *psp) +sisInitScreen(__DRIscreen *psp) { static const __DRIversion ddx_expected = {0, 8, 0}; static const __DRIversion dri_expected = {4, 0, 0}; diff --git a/src/mesa/drivers/dri/sis/sis_screen.h b/src/mesa/drivers/dri/sis/sis_screen.h index 07c29cfa09..8009fecc31 100644 --- a/src/mesa/drivers/dri/sis/sis_screen.h +++ b/src/mesa/drivers/dri/sis/sis_screen.h @@ -50,7 +50,7 @@ typedef struct { int cpp; unsigned int screenX, screenY; - __DRIscreenPrivate *driScreen; + __DRIscreen *driScreen; unsigned int sarea_priv_offset; /* Configuration cache with default values for all contexts */ diff --git a/src/mesa/drivers/dri/sis/sis_span.c b/src/mesa/drivers/dri/sis/sis_span.c index cfbb51007d..008b00160e 100644 --- a/src/mesa/drivers/dri/sis/sis_span.c +++ b/src/mesa/drivers/dri/sis/sis_span.c @@ -42,7 +42,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define LOCAL_VARS \ sisContextPtr smesa = SIS_CONTEXT(ctx); \ - __DRIdrawablePrivate *dPriv = smesa->driDrawable; \ + __DRIdrawable *dPriv = smesa->driDrawable; \ struct sis_renderbuffer *srb = (struct sis_renderbuffer *) rb; \ GLuint pitch = srb->pitch; \ char *buf = srb->map; \ @@ -52,7 +52,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define LOCAL_DEPTH_VARS \ sisContextPtr smesa = SIS_CONTEXT(ctx); \ - __DRIdrawablePrivate *dPriv = smesa->driDrawable; \ + __DRIdrawable *dPriv = smesa->driDrawable; \ struct sis_renderbuffer *srb = (struct sis_renderbuffer *) rb; \ char *buf = srb->map; diff --git a/src/mesa/drivers/dri/tdfx/tdfx_context.c b/src/mesa/drivers/dri/tdfx/tdfx_context.c index e742d414a5..edb1875f76 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_context.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_context.c @@ -165,12 +165,12 @@ static const struct dri_debug_control debug_control[] = }; GLboolean tdfxCreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ) { tdfxContextPtr fxMesa; GLcontext *ctx, *shareCtx; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; tdfxScreenPrivate *fxScreen = (tdfxScreenPrivate *) sPriv->private; TDFXSAREAPriv *saPriv = (TDFXSAREAPriv *) ((char *) sPriv->pSAREA + sizeof(drm_sarea_t)); @@ -441,7 +441,7 @@ static GLboolean tdfxInitVertexFormats( tdfxContextPtr fxMesa ) * Initialize the state in an tdfxContextPtr struct. */ static GLboolean -tdfxInitContext( __DRIdrawablePrivate *driDrawPriv, tdfxContextPtr fxMesa ) +tdfxInitContext( __DRIdrawable *driDrawPriv, tdfxContextPtr fxMesa ) { /* KW: Would be nice to make one of these a member of the other. */ @@ -563,7 +563,7 @@ tdfxInitContext( __DRIdrawablePrivate *driDrawPriv, tdfxContextPtr fxMesa ) void -tdfxDestroyContext( __DRIcontextPrivate *driContextPriv ) +tdfxDestroyContext( __DRIcontext *driContextPriv ) { tdfxContextPtr fxMesa = (tdfxContextPtr) driContextPriv->driverPrivate; @@ -607,7 +607,7 @@ tdfxDestroyContext( __DRIcontextPrivate *driContextPriv ) GLboolean -tdfxUnbindContext( __DRIcontextPrivate *driContextPriv ) +tdfxUnbindContext( __DRIcontext *driContextPriv ) { GET_CURRENT_CONTEXT(ctx); tdfxContextPtr fxMesa = TDFX_CONTEXT(ctx); @@ -626,9 +626,9 @@ tdfxUnbindContext( __DRIcontextPrivate *driContextPriv ) GLboolean -tdfxMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ) +tdfxMakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ) { if ( TDFX_DEBUG & DEBUG_VERBOSE_DRI ) { fprintf( stderr, "%s( %p )\n", __FUNCTION__, (void *)driContextPriv ); diff --git a/src/mesa/drivers/dri/tdfx/tdfx_context.h b/src/mesa/drivers/dri/tdfx/tdfx_context.h index 3bcb545119..6e25cac301 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_context.h +++ b/src/mesa/drivers/dri/tdfx/tdfx_context.h @@ -892,18 +892,18 @@ struct tdfx_context { char rendererString[100]; /* stuff added for DRI */ - __DRIscreenPrivate *driScreen; - __DRIcontextPrivate *driContext; + __DRIscreen *driScreen; + __DRIcontext *driContext; /** * DRI drawable bound to this context for drawing. */ - __DRIdrawablePrivate *driDrawable; + __DRIdrawable *driDrawable; /** * DRI drawable bound to this context for reading. */ - __DRIdrawablePrivate *driReadable; + __DRIdrawable *driReadable; drm_context_t hHWContext; drm_hw_lock_t *driHwLock; @@ -938,19 +938,19 @@ struct tdfx_context { extern GLboolean tdfxCreateContext( const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate ); extern void -tdfxDestroyContext( __DRIcontextPrivate *driContextPriv ); +tdfxDestroyContext( __DRIcontext *driContextPriv ); extern GLboolean -tdfxUnbindContext( __DRIcontextPrivate *driContextPriv ); +tdfxUnbindContext( __DRIcontext *driContextPriv ); extern GLboolean -tdfxMakeCurrent( __DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv ); +tdfxMakeCurrent( __DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv ); extern GLboolean tdfxInitGlide( tdfxContextPtr tmesa ); diff --git a/src/mesa/drivers/dri/tdfx/tdfx_lock.c b/src/mesa/drivers/dri/tdfx/tdfx_lock.c index 17cdc51ee1..4f84240104 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_lock.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_lock.c @@ -45,10 +45,10 @@ void tdfxGetLock( tdfxContextPtr fxMesa ) { - __DRIcontextPrivate *cPriv = fxMesa->driContext; - __DRIdrawablePrivate *const drawable = cPriv->driDrawablePriv; - __DRIdrawablePrivate *const readable = cPriv->driReadablePriv; - __DRIscreenPrivate *sPriv = drawable->driScreenPriv; + __DRIcontext *cPriv = fxMesa->driContext; + __DRIdrawable *const drawable = cPriv->driDrawablePriv; + __DRIdrawable *const readable = cPriv->driReadablePriv; + __DRIscreen *sPriv = drawable->driScreenPriv; TDFXSAREAPriv *saPriv = (TDFXSAREAPriv *) (((char *) sPriv->pSAREA) + fxMesa->fxScreen->sarea_priv_offset); unsigned int stamp = drawable->lastStamp; diff --git a/src/mesa/drivers/dri/tdfx/tdfx_pixels.c b/src/mesa/drivers/dri/tdfx/tdfx_pixels.c index a3b1775e90..65f0464f8a 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_pixels.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_pixels.c @@ -495,7 +495,7 @@ tdfx_readpixels_R5G6B5(GLcontext * ctx, GLint x, GLint y, { tdfxContextPtr fxMesa = TDFX_CONTEXT(ctx); GrLfbInfo_t info; - __DRIdrawablePrivate *const readable = fxMesa->driReadable; + __DRIdrawable *const readable = fxMesa->driReadable; const GLint winX = readable->x; const GLint winY = readable->y + readable->h - 1; const GLint scrX = winX + x; @@ -553,7 +553,7 @@ tdfx_readpixels_R8G8B8A8(GLcontext * ctx, GLint x, GLint y, { tdfxContextPtr fxMesa = TDFX_CONTEXT(ctx); GrLfbInfo_t info; - __DRIdrawablePrivate *const readable = fxMesa->driReadable; + __DRIdrawable *const readable = fxMesa->driReadable; const GLint winX = readable->x; const GLint winY = readable->y + readable->h - 1; const GLint scrX = winX + x; diff --git a/src/mesa/drivers/dri/tdfx/tdfx_render.c b/src/mesa/drivers/dri/tdfx/tdfx_render.c index 79d63f72ac..979bcd4514 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_render.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_render.c @@ -556,7 +556,7 @@ static void uploadTextureImages( tdfxContextPtr fxMesa ) */ void tdfxUploadClipping( tdfxContextPtr fxMesa ) { - __DRIdrawablePrivate *dPriv = fxMesa->driDrawable; + __DRIdrawable *dPriv = fxMesa->driDrawable; assert(dPriv); diff --git a/src/mesa/drivers/dri/tdfx/tdfx_screen.c b/src/mesa/drivers/dri/tdfx/tdfx_screen.c index 2eb0024d40..d72d8e0d47 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_screen.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_screen.c @@ -70,7 +70,7 @@ static const __DRIextension *tdfxExtensions[] = { static const GLuint __driNConfigOptions = 1; static GLboolean -tdfxCreateScreen( __DRIscreenPrivate *sPriv ) +tdfxCreateScreen( __DRIscreen *sPriv ) { tdfxScreenPrivate *fxScreen; TDFXDRIPtr fxDRIPriv = (TDFXDRIPtr) sPriv->pDevPriv; @@ -121,7 +121,7 @@ tdfxCreateScreen( __DRIscreenPrivate *sPriv ) static void -tdfxDestroyScreen( __DRIscreenPrivate *sPriv ) +tdfxDestroyScreen( __DRIscreen *sPriv ) { tdfxScreenPrivate *fxScreen = (tdfxScreenPrivate *) sPriv->private; @@ -139,7 +139,7 @@ tdfxDestroyScreen( __DRIscreenPrivate *sPriv ) static GLboolean -tdfxInitDriver( __DRIscreenPrivate *sPriv ) +tdfxInitDriver( __DRIscreen *sPriv ) { if ( TDFX_DEBUG & DEBUG_VERBOSE_DRI ) { fprintf( stderr, "%s( %p )\n", __FUNCTION__, (void *)sPriv ); @@ -155,8 +155,8 @@ tdfxInitDriver( __DRIscreenPrivate *sPriv ) static GLboolean -tdfxCreateBuffer( __DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +tdfxCreateBuffer( __DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap ) { @@ -227,14 +227,14 @@ tdfxCreateBuffer( __DRIscreenPrivate *driScrnPriv, static void -tdfxDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +tdfxDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } static void -tdfxSwapBuffers( __DRIdrawablePrivate *driDrawPriv ) +tdfxSwapBuffers( __DRIdrawable *driDrawPriv ) { GET_CURRENT_CONTEXT(ctx); @@ -253,7 +253,7 @@ tdfxSwapBuffers( __DRIdrawablePrivate *driDrawPriv ) * we have to do a glFinish (per the GLX spec). */ if ( ctx ) { - __DRIdrawablePrivate *curDrawPriv; + __DRIdrawable *curDrawPriv; fxMesa = TDFX_CONTEXT(ctx); curDrawPriv = fxMesa->driContext->driDrawablePriv; @@ -341,7 +341,7 @@ tdfxSwapBuffers( __DRIdrawablePrivate *driDrawPriv ) } static const __DRIconfig ** -tdfxFillInModes(__DRIscreenPrivate *psp, +tdfxFillInModes(__DRIscreen *psp, unsigned pixel_bits, unsigned depth_bits, unsigned stencil_bits, diff --git a/src/mesa/drivers/dri/tdfx/tdfx_screen.h b/src/mesa/drivers/dri/tdfx/tdfx_screen.h index 5a68898b36..6aa42e8667 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_screen.h +++ b/src/mesa/drivers/dri/tdfx/tdfx_screen.h @@ -61,7 +61,7 @@ typedef struct { int textureOffset; int textureSize; - __DRIscreenPrivate *driScrnPriv; + __DRIscreen *driScrnPriv; unsigned int sarea_priv_offset; /* Configuration cache with default values for all contexts */ diff --git a/src/mesa/drivers/dri/tdfx/tdfx_span.c b/src/mesa/drivers/dri/tdfx/tdfx_span.c index 6b38fa5a01..a17bcd952a 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_span.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_span.c @@ -47,7 +47,7 @@ #define LOCAL_VARS \ driRenderbuffer *drb = (driRenderbuffer *) rb; \ - __DRIdrawablePrivate *const dPriv = drb->dPriv; \ + __DRIdrawable *const dPriv = drb->dPriv; \ GLuint pitch = drb->backBuffer ? info.strideInBytes \ : (drb->pitch * drb->cpp); \ const GLuint bottom = dPriv->h - 1; \ @@ -104,7 +104,7 @@ #define HW_READ_CLIPLOOP() \ do { \ - const __DRIdrawablePrivate *dPriv = fxMesa->driDrawable; \ + const __DRIdrawable *dPriv = fxMesa->driDrawable; \ drm_clip_rect_t *rect = dPriv->pClipRects; \ int _nc = dPriv->numClipRects; \ while (_nc--) { \ diff --git a/src/mesa/drivers/dri/tdfx/tdfx_state.c b/src/mesa/drivers/dri/tdfx/tdfx_state.c index cf2712720f..cdb61a0ce0 100644 --- a/src/mesa/drivers/dri/tdfx/tdfx_state.c +++ b/src/mesa/drivers/dri/tdfx/tdfx_state.c @@ -621,7 +621,7 @@ static int intersect_rect( drm_clip_rect_t *out, void tdfxUpdateClipping( GLcontext *ctx ) { tdfxContextPtr fxMesa = TDFX_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = fxMesa->driDrawable; + __DRIdrawable *dPriv = fxMesa->driDrawable; if ( TDFX_DEBUG & DEBUG_VERBOSE_API ) { fprintf( stderr, "%s()\n", __FUNCTION__ ); diff --git a/src/mesa/drivers/dri/unichrome/via_context.c b/src/mesa/drivers/dri/unichrome/via_context.c index 0524becf3e..d17a160271 100644 --- a/src/mesa/drivers/dri/unichrome/via_context.c +++ b/src/mesa/drivers/dri/unichrome/via_context.c @@ -148,7 +148,7 @@ viaRenderbufferStorage(GLcontext *ctx, struct gl_renderbuffer *rb, static void viaInitRenderbuffer(struct via_renderbuffer *vrb, GLenum format, - __DRIdrawablePrivate *dPriv) + __DRIdrawable *dPriv) { const GLuint name = 0; struct gl_renderbuffer *rb = & vrb->Base; @@ -207,7 +207,7 @@ viaInitRenderbuffer(struct via_renderbuffer *vrb, GLenum format, static GLboolean calculate_buffer_parameters(struct via_context *vmesa, struct gl_framebuffer *fb, - __DRIdrawablePrivate *dPriv) + __DRIdrawable *dPriv) { const unsigned shift = vmesa->viaScreen->bitsPerPixel / 16; const unsigned extra = 32; @@ -460,12 +460,12 @@ FreeBuffer(struct via_context *vmesa) GLboolean viaCreateContext(const __GLcontextModes *visual, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate) { GLcontext *ctx, *shareCtx; struct via_context *vmesa; - __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; + __DRIscreen *sPriv = driContextPriv->driScreenPriv; viaScreenPrivate *viaScreen = (viaScreenPrivate *)sPriv->private; drm_via_sarea_t *saPriv = (drm_via_sarea_t *) (((GLubyte *)sPriv->pSAREA) + viaScreen->sareaPrivOffset); @@ -679,7 +679,7 @@ viaCreateContext(const __GLcontextModes *visual, } void -viaDestroyContext(__DRIcontextPrivate *driContextPriv) +viaDestroyContext(__DRIcontext *driContextPriv) { GET_CURRENT_CONTEXT(ctx); struct via_context *vmesa = @@ -729,8 +729,8 @@ viaDestroyContext(__DRIcontextPrivate *driContextPriv) void viaXMesaWindowMoved(struct via_context *vmesa) { - __DRIdrawablePrivate *const drawable = vmesa->driDrawable; - __DRIdrawablePrivate *const readable = vmesa->driReadable; + __DRIdrawable *const drawable = vmesa->driDrawable; + __DRIdrawable *const readable = vmesa->driReadable; struct via_renderbuffer * draw_buffer; struct via_renderbuffer * read_buffer; GLuint bytePerPixel = vmesa->viaScreen->bitsPerPixel >> 3; @@ -813,15 +813,15 @@ void viaXMesaWindowMoved(struct via_context *vmesa) } GLboolean -viaUnbindContext(__DRIcontextPrivate *driContextPriv) +viaUnbindContext(__DRIcontext *driContextPriv) { return GL_TRUE; } GLboolean -viaMakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv) +viaMakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv) { if (VIA_DEBUG & DEBUG_DRI) { fprintf(stderr, "driContextPriv = %016lx\n", (unsigned long)driContextPriv); @@ -897,8 +897,8 @@ viaMakeCurrent(__DRIcontextPrivate *driContextPriv, void viaGetLock(struct via_context *vmesa, GLuint flags) { - __DRIdrawablePrivate *dPriv = vmesa->driDrawable; - __DRIscreenPrivate *sPriv = vmesa->driScreen; + __DRIdrawable *dPriv = vmesa->driDrawable; + __DRIscreen *sPriv = vmesa->driScreen; drmGetLock(vmesa->driFd, vmesa->hHWContext, flags); @@ -928,9 +928,9 @@ void viaGetLock(struct via_context *vmesa, GLuint flags) void -viaSwapBuffers(__DRIdrawablePrivate *drawablePrivate) +viaSwapBuffers(__DRIdrawable *drawablePrivate) { - __DRIdrawablePrivate *dPriv = (__DRIdrawablePrivate *)drawablePrivate; + __DRIdrawable *dPriv = (__DRIdrawable *)drawablePrivate; if (dPriv && dPriv->driContextPriv && diff --git a/src/mesa/drivers/dri/unichrome/via_context.h b/src/mesa/drivers/dri/unichrome/via_context.h index 4cc9e475c2..4e1ab3a6ca 100644 --- a/src/mesa/drivers/dri/unichrome/via_context.h +++ b/src/mesa/drivers/dri/unichrome/via_context.h @@ -105,7 +105,7 @@ struct via_renderbuffer { int drawW; int drawH; - __DRIdrawablePrivate *dPriv; + __DRIdrawable *dPriv; }; @@ -294,14 +294,14 @@ struct via_context { /** * DRI drawable bound to this context for drawing. */ - __DRIdrawablePrivate *driDrawable; + __DRIdrawable *driDrawable; /** * DRI drawable bound to this context for reading. */ - __DRIdrawablePrivate *driReadable; + __DRIdrawable *driReadable; - __DRIscreenPrivate *driScreen; + __DRIscreen *driScreen; viaScreenPrivate *viaScreen; drm_via_sarea_t *sarea; volatile GLuint* regMMIOBase; diff --git a/src/mesa/drivers/dri/unichrome/via_ioctl.c b/src/mesa/drivers/dri/unichrome/via_ioctl.c index 91c94fa377..8d4edfa305 100644 --- a/src/mesa/drivers/dri/unichrome/via_ioctl.c +++ b/src/mesa/drivers/dri/unichrome/via_ioctl.c @@ -205,7 +205,7 @@ static void viaFillBuffer(struct via_context *vmesa, static void viaClear(GLcontext *ctx, GLbitfield mask) { struct via_context *vmesa = VIA_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = vmesa->driDrawable; + __DRIdrawable *dPriv = vmesa->driDrawable; struct via_renderbuffer *const vrb = (struct via_renderbuffer *) dPriv->driverPrivate; int flag = 0; @@ -507,12 +507,12 @@ void viaWaitIdleLocked( struct via_context *vmesa, GLboolean light ) * except that WAIT_IDLE() will spin the CPU polling, while this is * IRQ driven. */ -static void viaWaitIdleVBlank( __DRIdrawablePrivate *dPriv, +static void viaWaitIdleVBlank( __DRIdrawable *dPriv, struct via_context *vmesa, GLuint value ) { GLboolean missed_target; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; + __DRIscreen *psp = dPriv->driScreenPriv; VIA_FLUSH_DMA(vmesa); @@ -591,11 +591,11 @@ void viaResetPageFlippingLocked(struct via_context *vmesa) /* * Copy the back buffer to the front buffer. */ -void viaCopyBuffer(__DRIdrawablePrivate *dPriv) +void viaCopyBuffer(__DRIdrawable *dPriv) { struct via_context *vmesa = (struct via_context *)dPriv->driContextPriv->driverPrivate; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; + __DRIscreen *psp = dPriv->driScreenPriv; if (VIA_DEBUG & DEBUG_IOCTL) fprintf(stderr, @@ -635,12 +635,12 @@ void viaCopyBuffer(__DRIdrawablePrivate *dPriv) } -void viaPageFlip(__DRIdrawablePrivate *dPriv) +void viaPageFlip(__DRIdrawable *dPriv) { struct via_context *vmesa = (struct via_context *)dPriv->driContextPriv->driverPrivate; struct via_renderbuffer buffer_tmp; - __DRIscreenPrivate *psp = dPriv->driScreenPriv; + __DRIscreen *psp = dPriv->driScreenPriv; VIA_FLUSH_DMA(vmesa); if (dPriv->vblFlags == VBLANK_FLAG_SYNC && diff --git a/src/mesa/drivers/dri/unichrome/via_ioctl.h b/src/mesa/drivers/dri/unichrome/via_ioctl.h index 14a833a97d..c6b32cf085 100644 --- a/src/mesa/drivers/dri/unichrome/via_ioctl.h +++ b/src/mesa/drivers/dri/unichrome/via_ioctl.h @@ -33,8 +33,8 @@ void viaFlushDma(struct via_context *vmesa); void viaFlushDmaLocked(struct via_context *vmesa, GLuint flags); void viaInitIoctlFuncs(GLcontext *ctx); -void viaCopyBuffer(__DRIdrawablePrivate *dpriv); -void viaPageFlip(__DRIdrawablePrivate *dpriv); +void viaCopyBuffer(__DRIdrawable *dpriv); +void viaPageFlip(__DRIdrawable *dpriv); void viaCheckDma(struct via_context *vmesa, GLuint bytes); void viaResetPageFlippingLocked(struct via_context *vmesa); void viaWaitIdle(struct via_context *vmesa, GLboolean light); diff --git a/src/mesa/drivers/dri/unichrome/via_screen.c b/src/mesa/drivers/dri/unichrome/via_screen.c index e0bf58ca9a..82668f2def 100644 --- a/src/mesa/drivers/dri/unichrome/via_screen.c +++ b/src/mesa/drivers/dri/unichrome/via_screen.c @@ -90,7 +90,7 @@ static void via_free_empty_buffers( drmBufMapPtr bufs ) static GLboolean -viaInitDriver(__DRIscreenPrivate *sPriv) +viaInitDriver(__DRIscreen *sPriv) { viaScreenPrivate *viaScreen; VIADRIPtr gDRIPriv = (VIADRIPtr)sPriv->pDevPriv; @@ -184,7 +184,7 @@ viaInitDriver(__DRIscreenPrivate *sPriv) } static void -viaDestroyScreen(__DRIscreenPrivate *sPriv) +viaDestroyScreen(__DRIscreen *sPriv) { viaScreenPrivate *viaScreen = (viaScreenPrivate *)sPriv->private; VIADRIPtr gDRIPriv = (VIADRIPtr)sPriv->pDevPriv; @@ -203,8 +203,8 @@ viaDestroyScreen(__DRIscreenPrivate *sPriv) static GLboolean -viaCreateBuffer(__DRIscreenPrivate *driScrnPriv, - __DRIdrawablePrivate *driDrawPriv, +viaCreateBuffer(__DRIscreen *driScrnPriv, + __DRIdrawable *driDrawPriv, const __GLcontextModes *mesaVis, GLboolean isPixmap) { @@ -314,13 +314,13 @@ viaCreateBuffer(__DRIscreenPrivate *driScrnPriv, static void -viaDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) +viaDestroyBuffer(__DRIdrawable *driDrawPriv) { _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } static const __DRIconfig ** -viaFillInModes( __DRIscreenPrivate *psp, +viaFillInModes( __DRIscreen *psp, unsigned pixel_bits, GLboolean have_back_buffer ) { __DRIconfig **configs; @@ -377,7 +377,7 @@ viaFillInModes( __DRIscreenPrivate *psp, * \return the __GLcontextModes supported by this driver */ static const __DRIconfig ** -viaInitScreen(__DRIscreenPrivate *psp) +viaInitScreen(__DRIscreen *psp) { static const __DRIversion ddx_expected = { VIA_DRIDDX_VERSION_MAJOR, VIA_DRIDDX_VERSION_MINOR, @@ -405,7 +405,7 @@ viaInitScreen(__DRIscreenPrivate *psp) * Get information about previous buffer swaps. */ static int -getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) +getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo ) { struct via_context *vmesa; diff --git a/src/mesa/drivers/dri/unichrome/via_screen.h b/src/mesa/drivers/dri/unichrome/via_screen.h index c3ef722ff0..aa662e01c0 100644 --- a/src/mesa/drivers/dri/unichrome/via_screen.h +++ b/src/mesa/drivers/dri/unichrome/via_screen.h @@ -61,7 +61,7 @@ typedef struct { drmAddress agpLinearStart; GLuint agpBase; - __DRIscreenPrivate *driScrnPriv; + __DRIscreen *driScrnPriv; drmBufMapPtr bufs; unsigned int sareaPrivOffset; /*=* John Sheng [2003.12.9] Tuxracer & VQ *=*/ @@ -77,21 +77,21 @@ typedef struct { extern GLboolean viaCreateContext(const __GLcontextModes *mesaVis, - __DRIcontextPrivate *driContextPriv, + __DRIcontext *driContextPriv, void *sharedContextPrivate); extern void -viaDestroyContext(__DRIcontextPrivate *driContextPriv); +viaDestroyContext(__DRIcontext *driContextPriv); extern GLboolean -viaUnbindContext(__DRIcontextPrivate *driContextPriv); +viaUnbindContext(__DRIcontext *driContextPriv); extern GLboolean -viaMakeCurrent(__DRIcontextPrivate *driContextPriv, - __DRIdrawablePrivate *driDrawPriv, - __DRIdrawablePrivate *driReadPriv); +viaMakeCurrent(__DRIcontext *driContextPriv, + __DRIdrawable *driDrawPriv, + __DRIdrawable *driReadPriv); extern void -viaSwapBuffers(__DRIdrawablePrivate *drawablePrivate); +viaSwapBuffers(__DRIdrawable *drawablePrivate); #endif diff --git a/src/mesa/drivers/dri/unichrome/via_span.c b/src/mesa/drivers/dri/unichrome/via_span.c index e847164cd0..fa3cbf7a79 100644 --- a/src/mesa/drivers/dri/unichrome/via_span.c +++ b/src/mesa/drivers/dri/unichrome/via_span.c @@ -43,7 +43,7 @@ #undef LOCAL_VARS #define LOCAL_VARS \ struct via_renderbuffer *vrb = (struct via_renderbuffer *) rb; \ - __DRIdrawablePrivate *dPriv = vrb->dPriv; \ + __DRIdrawable *dPriv = vrb->dPriv; \ GLuint pitch = vrb->pitch; \ GLuint height = dPriv->h; \ GLint p = 0; \ @@ -80,7 +80,7 @@ */ #define LOCAL_DEPTH_VARS \ struct via_renderbuffer *vrb = (struct via_renderbuffer *) rb; \ - __DRIdrawablePrivate *dPriv = vrb->dPriv; \ + __DRIdrawable *dPriv = vrb->dPriv; \ GLuint depth_pitch = vrb->pitch; \ GLuint height = dPriv->h; \ char *buf = (char *)(vrb->map) diff --git a/src/mesa/drivers/dri/unichrome/via_state.c b/src/mesa/drivers/dri/unichrome/via_state.c index a9db6c45f7..5a8d927de1 100644 --- a/src/mesa/drivers/dri/unichrome/via_state.c +++ b/src/mesa/drivers/dri/unichrome/via_state.c @@ -476,7 +476,7 @@ void viaEmitState(struct via_context *vmesa) */ if (ctx->Polygon.StippleFlag) { GLuint *stipple = &ctx->PolygonStipple[0]; - __DRIdrawablePrivate *dPriv = vmesa->driDrawable; + __DRIdrawable *dPriv = vmesa->driDrawable; struct via_renderbuffer *const vrb = (struct via_renderbuffer *) dPriv->driverPrivate; GLint i; @@ -722,7 +722,7 @@ static void viaColorMask(GLcontext *ctx, void viaCalcViewport(GLcontext *ctx) { struct via_context *vmesa = VIA_CONTEXT(ctx); - __DRIdrawablePrivate *dPriv = vmesa->driDrawable; + __DRIdrawable *dPriv = vmesa->driDrawable; struct via_renderbuffer *const vrb = (struct via_renderbuffer *) dPriv->driverPrivate; const GLfloat *v = ctx->Viewport._WindowMap.m; -- cgit v1.2.3 From 01dc463e5d5513e059eea601710cd4babe02610d Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 18:42:23 -0500 Subject: intel: Drop LOCK/UNLOCK_HARDWARE() --- src/mesa/drivers/dri/i965/brw_draw.c | 4 - src/mesa/drivers/dri/intel/intel_batchbuffer.c | 20 +--- src/mesa/drivers/dri/intel/intel_blit.c | 6 -- src/mesa/drivers/dri/intel/intel_context.c | 131 +----------------------- src/mesa/drivers/dri/intel/intel_context.h | 9 -- src/mesa/drivers/dri/intel/intel_pixel_bitmap.c | 3 - src/mesa/drivers/dri/intel/intel_pixel_copy.c | 4 - src/mesa/drivers/dri/intel/intel_pixel_read.c | 7 -- src/mesa/drivers/dri/intel/intel_regions.c | 4 - src/mesa/drivers/dri/intel/intel_span.c | 3 - src/mesa/drivers/dri/intel/intel_tex_copy.c | 5 - src/mesa/drivers/dri/intel/intel_tex_image.c | 7 -- src/mesa/drivers/dri/intel/intel_tex_subimage.c | 4 - 13 files changed, 3 insertions(+), 204 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 7ad860898f..f99d607d86 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -339,10 +339,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, * so can't access it earlier. */ - LOCK_HARDWARE(intel); - if (!intel->constant_cliprect && intel->driDrawable->numClipRects == 0) { - UNLOCK_HARDWARE(intel); return GL_TRUE; } @@ -404,7 +401,6 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, if (intel->always_flush_batch) intel_batchbuffer_flush(intel->batch); out: - UNLOCK_HARDWARE(intel); brw_state_cache_check_size(brw); diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 2eae9b66d8..77a0159f18 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -129,8 +129,7 @@ intel_batchbuffer_free(struct intel_batchbuffer *batch) /* TODO: Push this whole function into bufmgr. */ static void -do_flush_locked(struct intel_batchbuffer *batch, - GLuint used, GLboolean allow_unlock) +do_flush_locked(struct intel_batchbuffer *batch, GLuint used) { struct intel_context *intel = batch->intel; int ret = 0; @@ -160,18 +159,6 @@ do_flush_locked(struct intel_batchbuffer *batch, (x_off & 0xffff) | (y_off << 16)); } - if (batch->cliprect_mode == LOOP_CLIPRECTS && num_cliprects == 0) { - if (allow_unlock) { - /* If we are not doing any actual user-visible rendering, - * do a sched_yield to keep the app from pegging the cpu while - * achieving nothing. - */ - UNLOCK_HARDWARE(intel); - sched_yield(); - LOCK_HARDWARE(intel); - } - } - if (INTEL_DEBUG & DEBUG_BATCH) { dri_bo_map(batch->buf, GL_FALSE); intel_decode(batch->buf->virtual, used / 4, batch->buf->offset, @@ -183,7 +170,6 @@ do_flush_locked(struct intel_batchbuffer *batch, } if (ret != 0) { - UNLOCK_HARDWARE(intel); exit(1); } intel->vtbl.new_batch(intel); @@ -252,9 +238,7 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, /* TODO: Just pass the relocation list and dma buffer up to the * kernel. */ - LOCK_HARDWARE(intel); - do_flush_locked(batch, used, GL_FALSE); - UNLOCK_HARDWARE(intel); + do_flush_locked(batch, used); if (INTEL_DEBUG & DEBUG_SYNC) { fprintf(stderr, "waiting for idle\n"); diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 3f2f8eb7cd..c6e4341d71 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -117,7 +117,6 @@ intelEmitCopyBlit(struct intel_context *intel, } while (pass < 2); if (pass >= 2) { - LOCK_HARDWARE(intel); dri_bo_map(dst_buffer, GL_TRUE); dri_bo_map(src_buffer, GL_FALSE); _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset, @@ -131,7 +130,6 @@ intelEmitCopyBlit(struct intel_context *intel, dri_bo_unmap(src_buffer); dri_bo_unmap(dst_buffer); - UNLOCK_HARDWARE(intel); return GL_TRUE; } @@ -239,8 +237,6 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) skipBuffers = BUFFER_BIT_STENCIL; } - LOCK_HARDWARE(intel); - intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); if (num_cliprects) { GLint cx, cy, cw, ch; @@ -412,8 +408,6 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) } } } - - UNLOCK_HARDWARE(intel); } GLboolean diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 5ed09f14ca..b5e742f8fe 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -611,6 +611,7 @@ intelInitContext(struct intel_context *intel, intel->driScreen = sPriv; intel->sarea = intelScreen->sarea; intel->driContext = driContextPriv; + intel->driFd = sPriv->fd; if (IS_965(intel->intelScreen->deviceID)) { intel->gen = 4; @@ -632,11 +633,6 @@ intelInitContext(struct intel_context *intel, intel->is_g4x = GL_TRUE; } - /* Dri stuff */ - intel->hHWContext = driContextPriv->hHWContext; - intel->driFd = sPriv->fd; - intel->driHwLock = sPriv->lock; - driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache, intel->driScreen->myNum, (intel->gen >= 4) ? "i965" : "i915"); @@ -1027,128 +1023,3 @@ intelMakeCurrent(__DRIcontext * driContextPriv, return GL_TRUE; } - -static void -intelContendedLock(struct intel_context *intel, GLuint flags) -{ - __DRIdrawable *dPriv = intel->driDrawable; - __DRIscreen *sPriv = intel->driScreen; - volatile drm_i915_sarea_t *sarea = intel->sarea; - int me = intel->hHWContext; - - drmGetLock(intel->driFd, intel->hHWContext, flags); - - if (INTEL_DEBUG & DEBUG_LOCK) - _mesa_printf("%s - got contended lock\n", __progname); - - /* If the window moved, may need to set a new cliprect now. - * - * NOTE: This releases and regains the hw lock, so all state - * checking must be done *after* this call: - */ - if (dPriv) - DRI_VALIDATE_DRAWABLE_INFO(sPriv, dPriv); - - if (sarea && sarea->ctxOwner != me) { - if (INTEL_DEBUG & DEBUG_BUFMGR) { - fprintf(stderr, "Lost Context: sarea->ctxOwner %x me %x\n", - sarea->ctxOwner, me); - } - sarea->ctxOwner = me; - } - - /* Drawable changed? - */ - if (dPriv && intel->lastStamp != dPriv->lastStamp) { - intelWindowMoved(intel); - intel->lastStamp = dPriv->lastStamp; - } -} - - -_glthread_DECLARE_STATIC_MUTEX(lockMutex); - -/* Lock the hardware and validate our state. - */ -void LOCK_HARDWARE( struct intel_context *intel ) -{ - __DRIdrawable *dPriv = intel->driDrawable; - __DRIscreen *sPriv = intel->driScreen; - char __ret = 0; - struct intel_framebuffer *intel_fb = NULL; - struct intel_renderbuffer *intel_rb = NULL; - - intel->locked++; - if (intel->locked >= 2) - return; - - if (!sPriv->dri2.enabled) - _glthread_LOCK_MUTEX(lockMutex); - - if (intel->driDrawable) { - intel_fb = intel->driDrawable->driverPrivate; - - if (intel_fb) - intel_rb = - intel_get_renderbuffer(&intel_fb->Base, - intel_fb->Base._ColorDrawBufferIndexes[0]); - } - - if (intel_rb && dPriv->vblFlags && - !(dPriv->vblFlags & VBLANK_FLAG_NO_IRQ) && - (intel_fb->vbl_waited - intel_rb->vbl_pending) > (1<<23)) { - drmVBlank vbl; - - vbl.request.type = DRM_VBLANK_ABSOLUTE; - - if ( dPriv->vblFlags & VBLANK_FLAG_SECONDARY ) { - vbl.request.type |= DRM_VBLANK_SECONDARY; - } - - vbl.request.sequence = intel_rb->vbl_pending; - drmWaitVBlank(intel->driFd, &vbl); - intel_fb->vbl_waited = vbl.reply.sequence; - } - - if (!sPriv->dri2.enabled) { - DRM_CAS(intel->driHwLock, intel->hHWContext, - (DRM_LOCK_HELD|intel->hHWContext), __ret); - - if (__ret) - intelContendedLock( intel, 0 ); - } - - - if (INTEL_DEBUG & DEBUG_LOCK) - _mesa_printf("%s - locked\n", __progname); -} - - -/* Unlock the hardware using the global current context - */ -void UNLOCK_HARDWARE( struct intel_context *intel ) -{ - __DRIscreen *sPriv = intel->driScreen; - - intel->locked--; - if (intel->locked > 0) - return; - - assert(intel->locked == 0); - - if (!sPriv->dri2.enabled) { - DRM_UNLOCK(intel->driFd, intel->driHwLock, intel->hHWContext); - _glthread_UNLOCK_MUTEX(lockMutex); - } - - if (INTEL_DEBUG & DEBUG_LOCK) - _mesa_printf("%s - unlocked\n", __progname); - - /** - * Nothing should be left in batch outside of LOCK/UNLOCK which references - * cliprects. - */ - if (intel->batch->cliprect_mode == REFERENCES_CLIPRECTS) - intel_batchbuffer_flush(intel->batch); -} - diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 6e0b47160a..ec026f8024 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -295,8 +295,6 @@ struct intel_context drm_clip_rect_t draw_rect; drm_clip_rect_t scissor_rect; - drm_context_t hHWContext; - drmLock *driHwLock; int driFd; __DRIcontext *driContext; @@ -320,11 +318,6 @@ struct intel_context GLuint swap_missed_count; }; -/* These are functions now: - */ -void LOCK_HARDWARE( struct intel_context *intel ); -void UNLOCK_HARDWARE( struct intel_context *intel ); - extern char *__progname; @@ -443,8 +436,6 @@ extern GLboolean intelInitContext(struct intel_context *intel, void *sharedContextPrivate, struct dd_function_table *functions); -extern void intelGetLock(struct intel_context *intel, GLuint flags); - extern void intelFinish(GLcontext * ctx); extern void intelFlush(GLcontext * ctx); diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index f23f94f35e..85e5ad2cdd 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -236,8 +236,6 @@ do_blit_bitmap( GLcontext *ctx, if (!intel_check_blit_fragment_ops(ctx, tmpColor[3] == 1.0F)) return GL_FALSE; - LOCK_HARDWARE(intel); - intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); if (num_cliprects != 0) { GLuint i; @@ -325,7 +323,6 @@ do_blit_bitmap( GLcontext *ctx, } } out: - UNLOCK_HARDWARE(intel); if (INTEL_DEBUG & DEBUG_SYNC) intel_batchbuffer_flush(intel->batch); diff --git a/src/mesa/drivers/dri/intel/intel_pixel_copy.c b/src/mesa/drivers/dri/intel/intel_pixel_copy.c index 689a00cb00..01c440907b 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_copy.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_copy.c @@ -134,8 +134,6 @@ do_blit_copypixels(GLcontext * ctx, intelFlush(&intel->ctx); - LOCK_HARDWARE(intel); - intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); if (num_cliprects != 0) { GLint delta_x; @@ -214,13 +212,11 @@ do_blit_copypixels(GLcontext * ctx, ctx->Color.ColorLogicOpEnabled ? ctx->Color.LogicOp : GL_COPY)) { DBG("%s: blit failure\n", __FUNCTION__); - UNLOCK_HARDWARE(intel); return GL_FALSE; } } } out: - UNLOCK_HARDWARE(intel); intel_check_front_buffer_rendering(intel); diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c index 3b75b718ff..9c0fdc6067 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_read.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c @@ -105,15 +105,12 @@ do_texture_readpixels(GLcontext * ctx, return GL_FALSE; } - LOCK_HARDWARE(intel); - if (intel->driDrawable->numClipRects) { intel->vtbl.install_meta_state(intel); intel->vtbl.meta_no_depth_write(intel); intel->vtbl.meta_no_stencil_write(intel); if (!driClipRectToFramebuffer(ctx->ReadBuffer, &x, &y, &width, &height)) { - UNLOCK_HARDWARE(intel); SET_STATE(i830, state); if (INTEL_DEBUG & DEBUG_PIXEL) fprintf(stderr, "%s: cliprect failed\n", __FUNCTION__); @@ -150,7 +147,6 @@ do_texture_readpixels(GLcontext * ctx, intel->vtbl.leave_meta_state(intel); } - UNLOCK_HARDWARE(intel); intel_region_wait_fence(ctx, dest_region); /* required by GL */ return GL_TRUE; @@ -224,7 +220,6 @@ do_blit_readpixels(GLcontext * ctx, * fire with lock held to guarentee cliprects are correct. */ intelFlush(&intel->ctx); - LOCK_HARDWARE(intel); if (intel->driReadDrawable->numClipRects) { GLboolean all = (width * height * src->cpp == dst->Base.Size && @@ -261,12 +256,10 @@ do_blit_readpixels(GLcontext * ctx, rect.y2 - src_rect.y2, rect.x2 - rect.x1, rect.y2 - rect.y1, GL_COPY)) { - UNLOCK_HARDWARE(intel); return GL_FALSE; } } } - UNLOCK_HARDWARE(intel); if (INTEL_DEBUG & DEBUG_PIXEL) _mesa_printf("%s - DONE\n", __FUNCTION__); diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index d6b9dc4446..cff34ff9ac 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -362,14 +362,12 @@ intel_region_data(struct intel_context *intel, intel_region_cow(intel, dst); } - LOCK_HARDWARE(intel); _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset, dst->cpp, dst->pitch, dstx, dsty, width, height, src, src_pitch, srcx, srcy); intel_region_unmap(intel, dst); - UNLOCK_HARDWARE(intel); } /* Copy rectangular sub-regions. Need better logic about when to @@ -485,7 +483,6 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region) /* Now blit from the texture buffer to the new buffer: */ - LOCK_HARDWARE(intel); ok = intelEmitCopyBlit(intel, region->cpp, region->pitch, pbo->buffer, 0, region->tiling, @@ -494,7 +491,6 @@ intel_region_cow(struct intel_context *intel, struct intel_region *region) region->pitch, region->height, GL_COPY); assert(ok); - UNLOCK_HARDWARE(intel); } dri_bo * diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index d1681e9088..605734d8e5 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -517,7 +517,6 @@ intelSpanRenderStart(GLcontext * ctx) GLuint i; intelFlush(&intel->ctx); - LOCK_HARDWARE(intel); for (i = 0; i < ctx->Const.MaxTextureImageUnits; i++) { if (ctx->Texture.Unit[i]._ReallyEnabled) { @@ -553,8 +552,6 @@ intelSpanRenderFinish(GLcontext * ctx) intel_map_unmap_framebuffer(intel, ctx->DrawBuffer, GL_FALSE); if (ctx->ReadBuffer != ctx->DrawBuffer) intel_map_unmap_framebuffer(intel, ctx->ReadBuffer, GL_FALSE); - - UNLOCK_HARDWARE(intel); } diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index a70738c958..e1d0b12752 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -110,7 +110,6 @@ do_copy_texsubimage(struct intel_context *intel, } /* intelFlush(ctx); */ - LOCK_HARDWARE(intel); { drm_intel_bo *dst_bo = intel_region_buffer(intel, intelImage->mt->region, @@ -132,7 +131,6 @@ do_copy_texsubimage(struct intel_context *intel, /* Can't blit to tiled buffers with non-tile-aligned offset. */ if (intelImage->mt->region->tiling == I915_TILING_Y) { - UNLOCK_HARDWARE(intel); return GL_FALSE; } @@ -169,13 +167,10 @@ do_copy_texsubimage(struct intel_context *intel, x, y, image_x + dstx, image_y + dsty, width, height, GL_COPY)) { - UNLOCK_HARDWARE(intel); return GL_FALSE; } } - UNLOCK_HARDWARE(intel); - return GL_TRUE; } diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 66d61f93ea..498d944c52 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -235,7 +235,6 @@ try_pbo_upload(struct intel_context *intel, if (drm_intel_bo_references(intel->batch->buf, dst_buffer)) intelFlush(&intel->ctx); - LOCK_HARDWARE(intel); { dri_bo *src_buffer = intel_bufferobj_buffer(intel, pbo, INTEL_READ); @@ -245,11 +244,9 @@ try_pbo_upload(struct intel_context *intel, dst_stride, dst_buffer, 0, GL_FALSE, 0, 0, dst_x, dst_y, width, height, GL_COPY)) { - UNLOCK_HARDWARE(intel); return GL_FALSE; } } - UNLOCK_HARDWARE(intel); return GL_TRUE; } @@ -469,8 +466,6 @@ intelTexImage(GLcontext * ctx, pixels, unpack, "glTexImage"); } - LOCK_HARDWARE(intel); - if (intelImage->mt) { if (pixels != NULL) { /* Flush any queued rendering with the texture before mapping. */ @@ -551,8 +546,6 @@ intelTexImage(GLcontext * ctx, intel_miptree_image_unmap(intel, intelImage->mt); texImage->Data = NULL; } - - UNLOCK_HARDWARE(intel); } diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index 1f68208266..7f1dc89022 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -72,8 +72,6 @@ intelTexSubimage(GLcontext * ctx, if (!pixels) return; - LOCK_HARDWARE(intel); - /* Map buffer if necessary. Need to lock to prevent other contexts * from uploading the buffer under us. */ @@ -129,8 +127,6 @@ intelTexSubimage(GLcontext * ctx, intel_miptree_image_unmap(intel, intelImage->mt); texImage->Data = NULL; } - - UNLOCK_HARDWARE(intel); } -- cgit v1.2.3 From 5203b7227ccb6b618fa42f08434d4a3cf123dca2 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 20:01:08 -0500 Subject: intel: Drop batchbuffer cliprect_mode tracking --- src/mesa/drivers/dri/i915/i830_vtbl.c | 14 +++---- src/mesa/drivers/dri/i915/i915_vtbl.c | 16 +++----- src/mesa/drivers/dri/i915/intel_tris.c | 7 ++-- src/mesa/drivers/dri/i965/brw_curbe.c | 2 +- src/mesa/drivers/dri/i965/brw_draw.c | 5 +-- src/mesa/drivers/dri/i965/brw_draw_upload.c | 8 ++-- src/mesa/drivers/dri/i965/brw_misc_state.c | 14 +++---- src/mesa/drivers/dri/i965/brw_queryobj.c | 4 +- src/mesa/drivers/dri/i965/brw_state.h | 2 +- src/mesa/drivers/dri/i965/brw_state_batch.c | 4 +- src/mesa/drivers/dri/intel/intel_batchbuffer.c | 30 +++----------- src/mesa/drivers/dri/intel/intel_batchbuffer.h | 57 ++------------------------ src/mesa/drivers/dri/intel/intel_blit.c | 14 +++---- 13 files changed, 49 insertions(+), 128 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index 1e3c8301d8..f2a67bbb53 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -298,7 +298,7 @@ i830_emit_invarient_state(struct intel_context *intel) { BATCH_LOCALS; - BEGIN_BATCH(29, IGNORE_CLIPRECTS); + BEGIN_BATCH(29); OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); OUT_BATCH(0); @@ -366,7 +366,7 @@ i830_emit_invarient_state(struct intel_context *intel) #define emit( intel, state, size ) \ - intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS ) + intel_batchbuffer_data(intel->batch, state, size ) static GLuint get_dirty(struct i830_hw_state *state) @@ -429,13 +429,9 @@ i830_emit_state(struct intel_context *intel) * It might be better to talk about explicit places where * scheduling is allowed, rather than assume that it is whenever a * batchbuffer fills up. - * - * Set the space as LOOP_CLIPRECTS now, since that's what our primitives - * will be emitted under. */ intel_batchbuffer_require_space(intel->batch, - get_state_size(state) + INTEL_PRIM_EMIT_SIZE, - LOOP_CLIPRECTS); + get_state_size(state) + INTEL_PRIM_EMIT_SIZE); count = 0; again: aper_count = 0; @@ -501,7 +497,7 @@ i830_emit_state(struct intel_context *intel) if (intel->constant_cliprect) count += 6; - BEGIN_BATCH(count, IGNORE_CLIPRECTS); + BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); OUT_RELOC(state->draw_region->buffer, @@ -544,7 +540,7 @@ i830_emit_state(struct intel_context *intel) if ((dirty & I830_UPLOAD_TEX(i))) { DBG("I830_UPLOAD_TEX(%d):\n", i); - BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1, IGNORE_CLIPRECTS); + BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1); OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]); if (state->tex_buffer[i]) { diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 9f7635a953..251c54697b 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -174,7 +174,7 @@ i915_emit_invarient_state(struct intel_context *intel) { BATCH_LOCALS; - BEGIN_BATCH(17, IGNORE_CLIPRECTS); + BEGIN_BATCH(17); OUT_BATCH(_3DSTATE_AA_CMD | AA_LINE_ECAAR_WIDTH_ENABLE | @@ -220,7 +220,7 @@ i915_emit_invarient_state(struct intel_context *intel) #define emit(intel, state, size ) \ - intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS ) + intel_batchbuffer_data(intel->batch, state, size) static GLuint get_dirty(struct i915_hw_state *state) @@ -301,13 +301,9 @@ i915_emit_state(struct intel_context *intel) * It might be better to talk about explicit places where * scheduling is allowed, rather than assume that it is whenever a * batchbuffer fills up. - * - * Set the space as LOOP_CLIPRECTS now, since that's what our primitives - * will be emitted under. */ intel_batchbuffer_require_space(intel->batch, - get_state_size(state) + INTEL_PRIM_EMIT_SIZE, - LOOP_CLIPRECTS); + get_state_size(state) + INTEL_PRIM_EMIT_SIZE); count = 0; again: aper_count = 0; @@ -384,7 +380,7 @@ i915_emit_state(struct intel_context *intel) if (intel->constant_cliprect) count += 6; - BEGIN_BATCH(count, IGNORE_CLIPRECTS); + BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); OUT_RELOC(state->draw_region->buffer, @@ -441,7 +437,7 @@ i915_emit_state(struct intel_context *intel) if (dirty & I915_UPLOAD_TEX(i)) nr++; - BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS); + BEGIN_BATCH(2 + nr * 3); OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr)); OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); for (i = 0; i < I915_TEX_UNITS; i++) @@ -465,7 +461,7 @@ i915_emit_state(struct intel_context *intel) } ADVANCE_BATCH(); - BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS); + BEGIN_BATCH(2 + nr * 3); OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr)); OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); for (i = 0; i < I915_TEX_UNITS; i++) diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index 63c5ae96dc..e99baf8e0e 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -89,7 +89,6 @@ intel_flush_inline_primitive(struct intel_context *intel) static void intel_start_inline(struct intel_context *intel, uint32_t prim) { - uint32_t batch_flags = LOOP_CLIPRECTS; BATCH_LOCALS; intel->vtbl.emit_state(intel); @@ -101,7 +100,7 @@ static void intel_start_inline(struct intel_context *intel, uint32_t prim) /* Emit a slot which will be filled with the inline primitive * command later. */ - BEGIN_BATCH(2, batch_flags); + BEGIN_BATCH(2); OUT_BATCH(0); assert((intel->batch->dirty_state & (1<<1)) == 0); @@ -252,7 +251,7 @@ void intel_flush_prim(struct intel_context *intel) #endif if (intel->gen >= 3) { - BEGIN_BATCH(5, LOOP_CLIPRECTS); + BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(0) | I1_LOAD_S(1) | 1); assert((offset & !S0_VB_OFFSET_MASK) == 0); @@ -270,7 +269,7 @@ void intel_flush_prim(struct intel_context *intel) } else { struct i830_context *i830 = i830_context(&intel->ctx); - BEGIN_BATCH(5, LOOP_CLIPRECTS); + BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(0) | I1_LOAD_S(2) | 1); /* S0 */ diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index aadcfbe2da..190310afbb 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -340,7 +340,7 @@ static void emit_constant_buffer(struct brw_context *brw) struct intel_context *intel = &brw->intel; GLuint sz = brw->curbe.total_size; - BEGIN_BATCH(2, IGNORE_CLIPRECTS); + BEGIN_BATCH(2); if (sz == 0) { OUT_BATCH((CMD_CONST_BUFFER << 16) | (2 - 2)); OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index f99d607d86..8d80c8bcfc 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -157,7 +157,7 @@ static void brw_emit_prim(struct brw_context *brw, } if (prim_packet.verts_per_instance) { intel_batchbuffer_data( brw->intel.batch, &prim_packet, - sizeof(prim_packet), LOOP_CLIPRECTS); + sizeof(prim_packet)); } if (intel->always_flush_cache) { intel_batchbuffer_emit_mi_flush(intel->batch); @@ -353,8 +353,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, * an upper bound of how much we might emit in a single * brw_try_draw_prims(). */ - intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4, - LOOP_CLIPRECTS); + intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4); hw_prim = brw_set_prim(brw, prim[i].mode); diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 2c9902c90f..c773b71507 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -494,7 +494,7 @@ static void brw_emit_vertices(struct brw_context *brw) * a VE loads from them. */ if (brw->vb.nr_enabled == 0) { - BEGIN_BATCH(3, IGNORE_CLIPRECTS); + BEGIN_BATCH(3); OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | 1); OUT_BATCH((0 << BRW_VE0_INDEX_SHIFT) | BRW_VE0_VALID | @@ -514,7 +514,7 @@ static void brw_emit_vertices(struct brw_context *brw) * are interleaved or from the same VBO. TBD if this makes a * performance difference. */ - BEGIN_BATCH(1 + brw->vb.nr_enabled * 4, IGNORE_CLIPRECTS); + BEGIN_BATCH(1 + brw->vb.nr_enabled * 4); OUT_BATCH((CMD_VERTEX_BUFFER << 16) | ((1 + brw->vb.nr_enabled * 4) - 2)); @@ -537,7 +537,7 @@ static void brw_emit_vertices(struct brw_context *brw) } ADVANCE_BATCH(); - BEGIN_BATCH(1 + brw->vb.nr_enabled * 2, IGNORE_CLIPRECTS); + BEGIN_BATCH(1 + brw->vb.nr_enabled * 2); OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | ((1 + brw->vb.nr_enabled * 2) - 2)); for (i = 0; i < brw->vb.nr_enabled; i++) { struct brw_vertex_element *input = brw->vb.enabled[i]; @@ -704,7 +704,7 @@ static void brw_emit_index_buffer(struct brw_context *brw) ib.header.bits.index_format = get_index_type(index_buffer->type); ib.header.bits.cut_index_enable = 0; - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH( ib.header.dword ); OUT_RELOC(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 2155feec84..1bd3979f9b 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -81,7 +81,7 @@ static void upload_drawing_rect(struct brw_context *brw) if (!intel->constant_cliprect) return; - BEGIN_BATCH(4, NO_LOOP_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965); OUT_BATCH(0); /* xmin, ymin */ OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) | @@ -116,7 +116,7 @@ static void upload_binding_table_pointers(struct brw_context *brw) { struct intel_context *intel = &brw->intel; - BEGIN_BATCH(6, IGNORE_CLIPRECTS); + BEGIN_BATCH(6); OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2)); if (brw->vs.bind_bo != NULL) OUT_RELOC(brw->vs.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* vs */ @@ -150,7 +150,7 @@ static void upload_pipelined_state_pointers(struct brw_context *brw ) { struct intel_context *intel = &brw->intel; - BEGIN_BATCH(7, IGNORE_CLIPRECTS); + BEGIN_BATCH(7); OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2)); OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); if (brw->gs.prog_active) @@ -215,7 +215,7 @@ static void emit_depthbuffer(struct brw_context *brw) unsigned int len = (intel->is_g4x || intel->is_ironlake) ? 6 : 5; if (region == NULL) { - BEGIN_BATCH(len, IGNORE_CLIPRECTS); + BEGIN_BATCH(len); OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29)); @@ -247,7 +247,7 @@ static void emit_depthbuffer(struct brw_context *brw) assert(region->tiling != I915_TILING_X); - BEGIN_BATCH(len, IGNORE_CLIPRECTS); + BEGIN_BATCH(len); OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | (format << 18) | @@ -513,7 +513,7 @@ static void upload_state_base_address( struct brw_context *brw ) * batchbuffer, so we can emit relocations inline. */ if (intel->is_ironlake) { - BEGIN_BATCH(8, IGNORE_CLIPRECTS); + BEGIN_BATCH(8); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); OUT_BATCH(1); /* General state base address */ OUT_BATCH(1); /* Surface state base address */ @@ -524,7 +524,7 @@ static void upload_state_base_address( struct brw_context *brw ) OUT_BATCH(1); /* Instruction access upper bound */ ADVANCE_BATCH(); } else { - BEGIN_BATCH(6, IGNORE_CLIPRECTS); + BEGIN_BATCH(6); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2)); OUT_BATCH(1); /* General state base address */ OUT_BATCH(1); /* Surface state base address */ diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index a195bc32b0..5399a74244 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -188,7 +188,7 @@ brw_emit_query_begin(struct brw_context *brw) if (brw->query.active || is_empty_list(&brw->query.active_head)) return; - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); @@ -227,7 +227,7 @@ brw_emit_query_end(struct brw_context *brw) if (!brw->query.active) return; - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_DEPTH_COUNT); diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 14d5319796..9c9d145c4b 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -151,7 +151,7 @@ void brw_state_cache_bo_delete(struct brw_cache *cache, dri_bo *bo); /*********************************************************************** * brw_state_batch.c */ -#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s)), IGNORE_CLIPRECTS) +#define BRW_BATCH_STRUCT(brw, s) intel_batchbuffer_data( brw->intel.batch, (s), sizeof(*(s))) #define BRW_CACHED_BATCH_STRUCT(brw, s) brw_cached_batch_struct( brw, (s), sizeof(*(s)) ) GLboolean brw_cached_batch_struct( struct brw_context *brw, diff --git a/src/mesa/drivers/dri/i965/brw_state_batch.c b/src/mesa/drivers/dri/i965/brw_state_batch.c index 7821898cf9..ed8120d617 100644 --- a/src/mesa/drivers/dri/i965/brw_state_batch.c +++ b/src/mesa/drivers/dri/i965/brw_state_batch.c @@ -48,7 +48,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw, struct header *newheader = (struct header *)data; if (brw->emit_state_always) { - intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS); + intel_batchbuffer_data(brw->intel.batch, data, sz); return GL_TRUE; } @@ -75,7 +75,7 @@ GLboolean brw_cached_batch_struct( struct brw_context *brw, emit: memcpy(item->header, newheader, sz); - intel_batchbuffer_data(brw->intel.batch, data, sz, IGNORE_CLIPRECTS); + intel_batchbuffer_data(brw->intel.batch, data, sz); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 77a0159f18..3a4b21a844 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -94,7 +94,6 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch) batch->size = intel->maxBatchSize; batch->ptr = batch->map; batch->dirty_state = ~0; - batch->cliprect_mode = IGNORE_CLIPRECTS; } struct intel_batchbuffer * @@ -133,8 +132,6 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used) { struct intel_context *intel = batch->intel; int ret = 0; - unsigned int num_cliprects = 0; - struct drm_clip_rect *cliprects = NULL; int x_off = 0, y_off = 0; if (batch->buffer) @@ -145,19 +142,7 @@ do_flush_locked(struct intel_batchbuffer *batch, GLuint used) batch->map = NULL; batch->ptr = NULL; - - if (batch->cliprect_mode == LOOP_CLIPRECTS) { - intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); - } - /* Dispatch the batchbuffer, if it has some effect (nonzero cliprects). - * Can't short-circuit like this once we have hardware contexts, but we - * should always be in DRI2 mode by then anyway. - */ - if ((batch->cliprect_mode != LOOP_CLIPRECTS || - num_cliprects != 0) && !intel->no_hw) { - dri_bo_exec(batch->buf, used, cliprects, num_cliprects, - (x_off & 0xffff) | (y_off << 16)); - } + dri_bo_exec(batch->buf, used, NULL, 0, (x_off & 0xffff) | (y_off << 16)); if (INTEL_DEBUG & DEBUG_BATCH) { dri_bo_map(batch->buf, GL_FALSE); @@ -187,10 +172,8 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, drm_intel_bo_reference(intel->first_post_swapbuffers_batch); } - if (used == 0) { - batch->cliprect_mode = IGNORE_CLIPRECTS; + if (used == 0) return; - } if (INTEL_DEBUG & DEBUG_BATCH) fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line, @@ -280,11 +263,10 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, void intel_batchbuffer_data(struct intel_batchbuffer *batch, - const void *data, GLuint bytes, - enum cliprect_mode cliprect_mode) + const void *data, GLuint bytes) { assert((bytes & 3) == 0); - intel_batchbuffer_require_space(batch, bytes, cliprect_mode); + intel_batchbuffer_require_space(batch, bytes); __memcpy(batch->ptr, data, bytes); batch->ptr += bytes; } @@ -301,7 +283,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) struct intel_context *intel = batch->intel; if (intel->gen >= 4) { - BEGIN_BATCH(4, IGNORE_CLIPRECTS); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PIPE_CONTROL | PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_WRITE_FLUSH | @@ -311,7 +293,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); } else { - BEGIN_BATCH(1, IGNORE_CLIPRECTS); + BEGIN_BATCH(1); OUT_BATCH(MI_FLUSH); ADVANCE_BATCH(); } diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index d4a94454dd..b052b724d8 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -10,35 +10,6 @@ #define BATCH_SZ 16384 #define BATCH_RESERVED 16 -enum cliprect_mode { - /** - * Batchbuffer contents may be looped over per cliprect, but do not - * require it. - */ - IGNORE_CLIPRECTS, - /** - * Batchbuffer contents require looping over per cliprect at batch submit - * time. - * - * This will be upgraded to NO_LOOP_CLIPRECTS when there's a single - * constant cliprect, as in DRI2 or FBO rendering. - */ - LOOP_CLIPRECTS, - /** - * Batchbuffer contents contain drawing that should not be executed multiple - * times. - */ - NO_LOOP_CLIPRECTS, - /** - * Batchbuffer contents contain drawing that already handles cliprects, such - * as 2D drawing to front/back/depth that doesn't respect DRAWING_RECTANGLE. - * - * Equivalent behavior to NO_LOOP_CLIPRECTS, but may not persist in batch - * outside of LOCK/UNLOCK. This is upgraded to just NO_LOOP_CLIPRECTS when - * there's a constant cliprect, as in DRI2 or FBO rendering. - */ - REFERENCES_CLIPRECTS -}; struct intel_batchbuffer { @@ -51,8 +22,6 @@ struct intel_batchbuffer GLubyte *map; GLubyte *ptr; - enum cliprect_mode cliprect_mode; - GLuint size; /** Tracking of BEGIN_BATCH()/OUT_BATCH()/ADVANCE_BATCH() debugging */ @@ -85,8 +54,7 @@ void intel_batchbuffer_reset(struct intel_batchbuffer *batch); * intel_buffer_dword() calls. */ void intel_batchbuffer_data(struct intel_batchbuffer *batch, - const void *data, GLuint bytes, - enum cliprect_mode cliprect_mode); + const void *data, GLuint bytes); void intel_batchbuffer_release_space(struct intel_batchbuffer *batch, GLuint bytes); @@ -121,36 +89,19 @@ intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, GLuint dword) static INLINE void intel_batchbuffer_require_space(struct intel_batchbuffer *batch, - GLuint sz, - enum cliprect_mode cliprect_mode) + GLuint sz) { assert(sz < batch->size - 8); if (intel_batchbuffer_space(batch) < sz) intel_batchbuffer_flush(batch); - - if ((cliprect_mode == LOOP_CLIPRECTS || - cliprect_mode == REFERENCES_CLIPRECTS) && - batch->intel->constant_cliprect) - cliprect_mode = NO_LOOP_CLIPRECTS; - - if (cliprect_mode != IGNORE_CLIPRECTS) { - if (batch->cliprect_mode == IGNORE_CLIPRECTS) { - batch->cliprect_mode = cliprect_mode; - } else { - if (batch->cliprect_mode != cliprect_mode) { - intel_batchbuffer_flush(batch); - batch->cliprect_mode = cliprect_mode; - } - } - } } /* Here are the crusty old macros, to be removed: */ #define BATCH_LOCALS -#define BEGIN_BATCH(n, cliprect_mode) do { \ - intel_batchbuffer_require_space(intel->batch, (n)*4, cliprect_mode); \ +#define BEGIN_BATCH(n) do { \ + intel_batchbuffer_require_space(intel->batch, (n)*4); \ assert(intel->batch->emit.start_ptr == NULL); \ intel->batch->emit.total = (n) * 4; \ intel->batch->emit.start_ptr = intel->batch->ptr; \ diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index c6e4341d71..55bee0084c 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -134,7 +134,7 @@ intelEmitCopyBlit(struct intel_context *intel, return GL_TRUE; } - intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); + intel_batchbuffer_require_space(intel->batch, 8 * 4); DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", __FUNCTION__, src_buffer, src_pitch, src_offset, src_x, src_y, @@ -179,7 +179,7 @@ intelEmitCopyBlit(struct intel_context *intel, assert(dst_x < dst_x2); assert(dst_y < dst_y2); - BEGIN_BATCH(8, NO_LOOP_CLIPRECTS); + BEGIN_BATCH(8); OUT_BATCH(CMD); OUT_BATCH(BR13 | (uint16_t)dst_pitch); OUT_BATCH((dst_y << 16) | dst_x); @@ -393,7 +393,7 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask) assert(x1 < x2); assert(y1 < y2); - BEGIN_BATCH(6, REFERENCES_CLIPRECTS); + BEGIN_BATCH(6); OUT_BATCH(CMD); OUT_BATCH(BR13); OUT_BATCH((y1 << 16) | x1); @@ -449,8 +449,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, intel_batchbuffer_require_space( intel->batch, (8 * 4) + (3 * 4) + - dwords * 4, - REFERENCES_CLIPRECTS ); + dwords * 4 ); opcode = XY_SETUP_BLT_CMD; if (cpp == 4) @@ -472,7 +471,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, if (dst_tiling != I915_TILING_NONE) blit_cmd |= XY_DST_TILED; - BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS); + BEGIN_BATCH(8 + 3); OUT_BATCH(opcode); OUT_BATCH(br13); OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ @@ -491,8 +490,7 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, intel_batchbuffer_data( intel->batch, src_bits, - dwords * 4, - REFERENCES_CLIPRECTS ); + dwords * 4 ); intel_batchbuffer_emit_mi_flush(intel->batch); -- cgit v1.2.3 From a6e1d3edac90016ca9662ca0a9707a2d4fba1726 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 21:41:57 -0500 Subject: intel: Remove client-side vblank code --- src/mesa/drivers/dri/i915/Makefile | 1 - src/mesa/drivers/dri/i965/Makefile | 1 - src/mesa/drivers/dri/intel/intel_context.c | 29 --------- src/mesa/drivers/dri/intel/intel_context.h | 9 --- src/mesa/drivers/dri/intel/intel_fbo.h | 12 ---- src/mesa/drivers/dri/intel/intel_screen.c | 36 ------------ src/mesa/drivers/dri/intel/intel_swapbuffers.c | 81 -------------------------- src/mesa/drivers/dri/intel/intel_swapbuffers.h | 52 ----------------- 8 files changed, 221 deletions(-) delete mode 100644 src/mesa/drivers/dri/intel/intel_swapbuffers.c delete mode 100644 src/mesa/drivers/dri/intel/intel_swapbuffers.h (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/Makefile b/src/mesa/drivers/dri/i915/Makefile index 788e78654e..cf32476f40 100644 --- a/src/mesa/drivers/dri/i915/Makefile +++ b/src/mesa/drivers/dri/i915/Makefile @@ -34,7 +34,6 @@ DRIVER_SOURCES = \ intel_pixel_read.c \ intel_buffers.c \ intel_blit.c \ - intel_swapbuffers.c \ i915_tex_layout.c \ i915_texstate.c \ i915_context.c \ diff --git a/src/mesa/drivers/dri/i965/Makefile b/src/mesa/drivers/dri/i965/Makefile index 7cdbdc7071..7758a792fd 100644 --- a/src/mesa/drivers/dri/i965/Makefile +++ b/src/mesa/drivers/dri/i965/Makefile @@ -24,7 +24,6 @@ DRIVER_SOURCES = \ intel_pixel_draw.c \ intel_pixel_read.c \ intel_state.c \ - intel_swapbuffers.c \ intel_syncobj.c \ intel_tex.c \ intel_tex_copy.c \ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 4a17711cfe..2ecf67152f 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -55,10 +55,8 @@ #include "intel_decode.h" #include "intel_bufmgr.h" #include "intel_screen.h" -#include "intel_swapbuffers.h" #include "drirenderbuffer.h" -#include "vblank.h" #include "utils.h" #include "xmlpool.h" /* for symbolic values of enum-type options */ @@ -868,7 +866,6 @@ intelMakeCurrent(__DRIcontext * driContextPriv, __DRIdrawable * driDrawPriv, __DRIdrawable * driReadPriv) { - __DRIscreen *psp = driDrawPriv->driScreenPriv; struct intel_context *intel; GET_CURRENT_CONTEXT(curCtx); @@ -904,32 +901,6 @@ intelMakeCurrent(__DRIcontext * driContextPriv, _mesa_make_current(&intel->ctx, &intel_fb->Base, readFb); intel->driReadDrawable = driReadPriv; - - if (intel->driDrawable != driDrawPriv) { - if (driDrawPriv->swap_interval == (unsigned)-1) { - int i; - - driDrawPriv->vblFlags = (intel->intelScreen->irq_active != 0) - ? driGetDefaultVBlankFlags(&intel->optionCache) - : VBLANK_FLAG_NO_IRQ; - - /* Prevent error printf if one crtc is disabled, this will - * be properly calculated in intelWindowMoved() next. - */ - driDrawPriv->vblFlags = intelFixupVblank(intel, driDrawPriv); - - (*psp->systemTime->getUST) (&intel_fb->swap_ust); - driDrawableInitVBlank(driDrawPriv); - intel_fb->vbl_waited = driDrawPriv->vblSeq; - - for (i = 0; i < 2; i++) { - if (intel_fb->color_rb[i]) - intel_fb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq; - } - } - intel->driDrawable = driDrawPriv; - } - intel_draw_buffer(&intel->ctx, &intel_fb->Base); } else { diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 808a0a2ac2..bd3166d64a 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -298,20 +298,11 @@ struct intel_context __DRIdrawable *driReadDrawable; __DRIscreen *driScreen; intelScreenPrivate *intelScreen; - volatile drm_i915_sarea_t *sarea; - - GLuint lastStamp; /** * Configuration cache */ driOptionCache optionCache; - - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; }; extern char *__progname; diff --git a/src/mesa/drivers/dri/intel/intel_fbo.h b/src/mesa/drivers/dri/intel/intel_fbo.h index fa43077d6a..72c31f9ba5 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.h +++ b/src/mesa/drivers/dri/intel/intel_fbo.h @@ -41,16 +41,6 @@ struct intel_framebuffer struct gl_framebuffer Base; struct intel_renderbuffer *color_rb[2]; - - /* VBI - */ - GLuint vbl_waited; - - int64_t swap_ust; - int64_t swap_missed_ust; - - GLuint swap_count; - GLuint swap_missed_count; }; @@ -62,8 +52,6 @@ struct intel_renderbuffer struct gl_renderbuffer Base; struct intel_region *region; - GLuint vbl_pending; /**< vblank sequence number of pending flip */ - uint8_t *span_cache; unsigned long span_cache_offset; }; diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 59d5f01d47..2d18997204 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -31,7 +31,6 @@ #include "main/renderbuffer.h" #include "utils.h" -#include "vblank.h" #include "xmlpool.h" #include "intel_batchbuffer.h" @@ -41,7 +40,6 @@ #include "intel_extensions.h" #include "intel_fbo.h" #include "intel_regions.h" -#include "intel_swapbuffers.h" #include "intel_screen.h" #include "intel_span.h" #include "intel_tex.h" @@ -117,9 +115,6 @@ static const __DRItexBufferExtension intelTexBufferExtension = { static const __DRIextension *intelScreenExtensions[] = { &driReadDrawableExtension, - &driSwapControlExtension.base, - &driFrameTrackingExtension.base, - &driMediaStreamCounterExtension.base, &intelTexOffsetExtension.base, &intelTexBufferExtension.base, NULL @@ -266,33 +261,6 @@ intelDestroyBuffer(__DRIdrawable * driDrawPriv) _mesa_reference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate)), NULL); } - -/** - * Get information about previous buffer swaps. - */ -static int -intelGetSwapInfo(__DRIdrawable * dPriv, __DRIswapInfo * sInfo) -{ - struct intel_framebuffer *intel_fb; - - if ((dPriv == NULL) || (dPriv->driverPrivate == NULL) - || (sInfo == NULL)) { - return -1; - } - - intel_fb = dPriv->driverPrivate; - sInfo->swap_count = intel_fb->swap_count; - sInfo->swap_ust = intel_fb->swap_ust; - sInfo->swap_missed_count = intel_fb->swap_missed_count; - - sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) - ? driCalculateSwapUsage(dPriv, 0, intel_fb->swap_missed_ust) - : 0.0; - - return 0; -} - - /* There are probably better ways to do this, such as an * init-designated function to register chipids and createcontext * functions. @@ -513,10 +481,6 @@ const struct __DriverAPIRec driDriverAPI = { .DestroyBuffer = intelDestroyBuffer, .MakeCurrent = intelMakeCurrent, .UnbindContext = intelUnbindContext, - .GetSwapInfo = intelGetSwapInfo, - .GetDrawableMSC = driDrawableGetMSC32, - .WaitForMSC = driWaitForMSC32, - .InitScreen2 = intelInitScreen2, }; diff --git a/src/mesa/drivers/dri/intel/intel_swapbuffers.c b/src/mesa/drivers/dri/intel/intel_swapbuffers.c deleted file mode 100644 index 65441495a7..0000000000 --- a/src/mesa/drivers/dri/intel/intel_swapbuffers.c +++ /dev/null @@ -1,81 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "intel_blit.h" -#include "intel_buffers.h" -#include "intel_swapbuffers.h" -#include "intel_fbo.h" -#include "intel_batchbuffer.h" -#include "drirenderbuffer.h" -#include "vblank.h" -#include "i915_drm.h" - - - -/* - * Correct a drawablePrivate's set of vblank flags WRT the current context. - * When considering multiple crtcs. - */ -GLuint -intelFixupVblank(struct intel_context *intel, __DRIdrawable *dPriv) -{ - if (!intel->intelScreen->driScrnPriv->dri2.enabled && - intel->intelScreen->driScrnPriv->ddx_version.minor >= 7) { - volatile drm_i915_sarea_t *sarea = intel->sarea; - drm_clip_rect_t drw_rect = { .x1 = dPriv->x, .x2 = dPriv->x + dPriv->w, - .y1 = dPriv->y, .y2 = dPriv->y + dPriv->h }; - drm_clip_rect_t planeA_rect = { .x1 = sarea->planeA_x, .y1 = sarea->planeA_y, - .x2 = sarea->planeA_x + sarea->planeA_w, - .y2 = sarea->planeA_y + sarea->planeA_h }; - drm_clip_rect_t planeB_rect = { .x1 = sarea->planeB_x, .y1 = sarea->planeB_y, - .x2 = sarea->planeB_x + sarea->planeB_w, - .y2 = sarea->planeB_y + sarea->planeB_h }; - GLint areaA = driIntersectArea( drw_rect, planeA_rect ); - GLint areaB = driIntersectArea( drw_rect, planeB_rect ); - GLuint flags; - - /* Update vblank info - */ - if (areaB > areaA || (areaA == areaB && areaB > 0)) { - flags = dPriv->vblFlags | VBLANK_FLAG_SECONDARY; - } else { - flags = dPriv->vblFlags & ~VBLANK_FLAG_SECONDARY; - } - - /* Do the stupid test: Is one of them actually disabled? - */ - if (sarea->planeA_w == 0 || sarea->planeA_h == 0) { - flags = dPriv->vblFlags | VBLANK_FLAG_SECONDARY; - } else if (sarea->planeB_w == 0 || sarea->planeB_h == 0) { - flags = dPriv->vblFlags & ~VBLANK_FLAG_SECONDARY; - } - - return flags; - } else { - return dPriv->vblFlags & ~VBLANK_FLAG_SECONDARY; - } -} diff --git a/src/mesa/drivers/dri/intel/intel_swapbuffers.h b/src/mesa/drivers/dri/intel/intel_swapbuffers.h deleted file mode 100644 index 82b77c6362..0000000000 --- a/src/mesa/drivers/dri/intel/intel_swapbuffers.h +++ /dev/null @@ -1,52 +0,0 @@ - -/************************************************************************** - * - * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#ifndef INTEL_SWAPBUFFERS_H -#define INTEL_SWAPBUFFERS_H - -#include "dri_util.h" -#include "drm.h" - -struct intel_context; -struct intel_framebuffer; - - -extern void -intelSwapBuffers(__DRIdrawable * dPriv); - -extern void -intelCopySubBuffer(__DRIdrawable * dPriv, int x, int y, int w, int h); - -extern GLuint -intelFixupVblank(struct intel_context *intel, __DRIdrawable *dPriv); - -extern void -intelWindowMoved(struct intel_context *intel); - - -#endif /* INTEL_SWAPBUFFERS_H */ -- cgit v1.2.3 From 2861d9200be15cc44e8825387d3bd79086523c67 Mon Sep 17 00:00:00 2001 From: Kristian Høgsberg Date: Fri, 1 Jan 2010 22:56:36 -0500 Subject: intel: Drop more cliprect bookkeeping --- src/mesa/drivers/dri/i915/i830_vtbl.c | 46 +++++++++---------------- src/mesa/drivers/dri/i915/i915_vtbl.c | 46 +++++++++---------------- src/mesa/drivers/dri/i965/brw_draw.c | 4 --- src/mesa/drivers/dri/i965/brw_misc_state.c | 3 -- src/mesa/drivers/dri/intel/intel_buffers.c | 54 +++++++----------------------- src/mesa/drivers/dri/intel/intel_context.h | 13 ------- 6 files changed, 44 insertions(+), 122 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index f2a67bbb53..4471ca2bbb 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -487,16 +487,13 @@ i830_emit_state(struct intel_context *intel) } if (dirty & I830_UPLOAD_BUFFERS) { - GLuint count = 9; + GLuint count = 15; DBG("I830_UPLOAD_BUFFERS:\n"); if (state->depth_region) count += 3; - if (intel->constant_cliprect) - count += 6; - BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); @@ -519,15 +516,13 @@ i830_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I830_DESTREG_SR1]); OUT_BATCH(state->Buffer[I830_DESTREG_SR2]); - if (intel->constant_cliprect) { - assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]); - OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]); - } + assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]); + OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]); ADVANCE_BATCH(); } @@ -669,23 +664,14 @@ i830_state_draw_region(struct intel_context *intel, } state->Buffer[I830_DESTREG_DV1] = value; - if (intel->constant_cliprect) { - state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; - state->Buffer[I830_DESTREG_DRAWRECT1] = 0; - state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ - state->Buffer[I830_DESTREG_DRAWRECT3] = - (ctx->DrawBuffer->Width & 0xffff) | - (ctx->DrawBuffer->Height << 16); - state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ - state->Buffer[I830_DESTREG_DRAWRECT5] = 0; - } else { - state->Buffer[I830_DESTREG_DRAWRECT0] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT1] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT2] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT3] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT4] = MI_NOOP; - state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP; - } + state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; + state->Buffer[I830_DESTREG_DRAWRECT1] = 0; + state->Buffer[I830_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ + state->Buffer[I830_DESTREG_DRAWRECT3] = + (ctx->DrawBuffer->Width & 0xffff) | + (ctx->DrawBuffer->Height << 16); + state->Buffer[I830_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ + state->Buffer[I830_DESTREG_DRAWRECT5] = 0; I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS); diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 251c54697b..266e6848c3 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -369,7 +369,7 @@ i915_emit_state(struct intel_context *intel) } if (dirty & I915_UPLOAD_BUFFERS) { - GLuint count = 9; + GLuint count = 15; if (INTEL_DEBUG & DEBUG_STATE) fprintf(stderr, "I915_UPLOAD_BUFFERS:\n"); @@ -377,9 +377,6 @@ i915_emit_state(struct intel_context *intel) if (state->depth_region) count += 3; - if (intel->constant_cliprect) - count += 6; - BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); @@ -402,15 +399,13 @@ i915_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I915_DESTREG_SR1]); OUT_BATCH(state->Buffer[I915_DESTREG_SR2]); - if (intel->constant_cliprect) { - assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]); - } + assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]); + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]); ADVANCE_BATCH(); } @@ -619,23 +614,14 @@ i915_state_draw_region(struct intel_context *intel, } state->Buffer[I915_DESTREG_DV1] = value; - if (intel->constant_cliprect) { - state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; - state->Buffer[I915_DESTREG_DRAWRECT1] = 0; - state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ - state->Buffer[I915_DESTREG_DRAWRECT3] = - (ctx->DrawBuffer->Width & 0xffff) | - (ctx->DrawBuffer->Height << 16); - state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ - state->Buffer[I915_DESTREG_DRAWRECT5] = 0; - } else { - state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP; - state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP; - } + state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; + state->Buffer[I915_DESTREG_DRAWRECT1] = 0; + state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */ + state->Buffer[I915_DESTREG_DRAWRECT3] = + (ctx->DrawBuffer->Width & 0xffff) | + (ctx->DrawBuffer->Height << 16); + state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */ + state->Buffer[I915_DESTREG_DRAWRECT5] = 0; I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); } diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 8d80c8bcfc..df281b27d5 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -339,10 +339,6 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, * so can't access it earlier. */ - if (!intel->constant_cliprect && intel->driDrawable->numClipRects == 0) { - return GL_TRUE; - } - for (i = 0; i < nr_prims; i++) { uint32_t hw_prim; diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 1bd3979f9b..7b70f787b7 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -78,9 +78,6 @@ static void upload_drawing_rect(struct brw_context *brw) struct intel_context *intel = &brw->intel; GLcontext *ctx = &intel->ctx; - if (!intel->constant_cliprect) - return; - BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965); OUT_BATCH(0); /* xmin, ymin */ diff --git a/src/mesa/drivers/dri/intel/intel_buffers.c b/src/mesa/drivers/dri/intel/intel_buffers.c index 219b3603f7..7c4b79f743 100644 --- a/src/mesa/drivers/dri/intel/intel_buffers.c +++ b/src/mesa/drivers/dri/intel/intel_buffers.c @@ -102,33 +102,15 @@ intel_get_cliprects(struct intel_context *intel, unsigned int *num_cliprects, int *x_off, int *y_off) { - __DRIdrawable *dPriv = intel->driDrawable; - - if (intel->constant_cliprect) { - /* FBO or DRI2 rendering, which can just use the fb's size. */ - intel->fboRect.x1 = 0; - intel->fboRect.y1 = 0; - intel->fboRect.x2 = intel->ctx.DrawBuffer->Width; - intel->fboRect.y2 = intel->ctx.DrawBuffer->Height; - - *cliprects = &intel->fboRect; - *num_cliprects = 1; - *x_off = 0; - *y_off = 0; - } else if (intel->front_cliprects || dPriv->numBackClipRects == 0) { - /* use the front clip rects */ - *cliprects = dPriv->pClipRects; - *num_cliprects = dPriv->numClipRects; - *x_off = dPriv->x; - *y_off = dPriv->y; - } - else { - /* use the back clip rects */ - *num_cliprects = dPriv->numBackClipRects; - *cliprects = dPriv->pBackClipRects; - *x_off = dPriv->backX; - *y_off = dPriv->backY; - } + intel->fboRect.x1 = 0; + intel->fboRect.y1 = 0; + intel->fboRect.x2 = intel->ctx.DrawBuffer->Width; + intel->fboRect.y2 = intel->ctx.DrawBuffer->Height; + + *cliprects = &intel->fboRect; + *num_cliprects = 1; + *x_off = 0; + *y_off = 0; } @@ -202,7 +184,6 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) || (fb->_NumColorDrawBuffers == 0)) { /* writing to 0 */ colorRegions[0] = NULL; - intel->constant_cliprect = GL_TRUE; } else if (fb->_NumColorDrawBuffers > 1) { int i; @@ -212,34 +193,23 @@ intel_draw_buffer(GLcontext * ctx, struct gl_framebuffer *fb) irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); colorRegions[i] = irb ? irb->region : NULL; } - intel->constant_cliprect = GL_TRUE; } else { /* Get the intel_renderbuffer for the single colorbuffer we're drawing - * into, and set up cliprects if it's a DRI1 window front buffer. + * into. */ if (fb->Name == 0) { - intel->constant_cliprect = intel->driScreen->dri2.enabled; /* drawing to window system buffer */ - if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) { - if (!intel->constant_cliprect && !intel->front_cliprects) - intel_batchbuffer_flush(intel->batch); - intel->front_cliprects = GL_TRUE; + if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT); - } - else { - if (!intel->constant_cliprect && intel->front_cliprects) - intel_batchbuffer_flush(intel->batch); - intel->front_cliprects = GL_FALSE; + else colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT); - } } else { /* drawing to user-created FBO */ struct intel_renderbuffer *irb; irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]); colorRegions[0] = (irb && irb->region) ? irb->region : NULL; - intel->constant_cliprect = GL_TRUE; } } diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index bd3166d64a..c7b7235836 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -247,19 +247,6 @@ struct intel_context intel_line_func draw_line; intel_tri_func draw_tri; - /** - * Set to true if a single constant cliprect should be used in the - * batchbuffer. Otherwise, cliprects must be calculated at batchbuffer - * flush time while the lock is held. - */ - GLboolean constant_cliprect; - - /** - * In !constant_cliprect mode, set to true if the front cliprects should be - * used instead of back. - */ - GLboolean front_cliprects; - /** * Set if rendering has occured to the drawable's front buffer. * -- cgit v1.2.3 From 63610fae4f46361f2500577a83bf5ac6f9e8b0ac Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Mon, 4 Jan 2010 08:47:01 -0800 Subject: i965: Fix the surface offset calculation for tiled buffers. If we ever had a non-tile-aligned tiled renderbuffer, the math was all off. Use the existing x,y coordinates instead of trying to reconstruct them from an incorrectly-calculated offset value. --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 50 ++++++++++++++---------- 1 file changed, 30 insertions(+), 20 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 8335e5a650..afb36b7bd7 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -522,7 +522,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, GLubyte color_mask[4]; GLboolean color_blend; uint32_t tiling; - uint32_t draw_offset; + uint32_t draw_x; + uint32_t draw_y; } key; memset(&key, 0, sizeof(key)); @@ -564,7 +565,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, } key.pitch = region->pitch; key.cpp = region->cpp; - key.draw_offset = region->draw_offset; /* cur 3d or cube face offset */ + key.draw_x = region->draw_x; + key.draw_y = region->draw_y; } else { key.surface_type = BRW_SURFACE_NULL; key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; @@ -572,7 +574,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, key.width = 1; key.height = 1; key.cpp = 4; - key.draw_offset = 0; + key.draw_x = 0; + key.draw_y = 0; } /* _NEW_COLOR */ memcpy(key.color_mask, ctx->Color.ColorMask, @@ -602,25 +605,32 @@ brw_update_renderbuffer_surface(struct brw_context *brw, surf.ss0.surface_format = key.surface_format; surf.ss0.surface_type = key.surface_type; if (key.tiling == I915_TILING_NONE) { - surf.ss1.base_addr = key.draw_offset; + surf.ss1.base_addr = (key.draw_x + key.draw_y * key.pitch) * key.cpp; } else { - uint32_t tile_offset = key.draw_offset % 4096; - - surf.ss1.base_addr = key.draw_offset - tile_offset; - - assert(BRW_IS_G4X(brw) || tile_offset == 0); - if (BRW_IS_G4X(brw)) { - if (key.tiling == I915_TILING_X) { - /* Note that the low bits of these fields are missing, so - * there's the possibility of getting in trouble. - */ - surf.ss5.x_offset = (tile_offset % 512) / key.cpp / 4; - surf.ss5.y_offset = tile_offset / 512 / 2; - } else { - surf.ss5.x_offset = (tile_offset % 128) / key.cpp / 4; - surf.ss5.y_offset = tile_offset / 128 / 2; - } + uint32_t tile_base, tile_x, tile_y; + uint32_t pitch = key.pitch * key.cpp; + + if (key.tiling == I915_TILING_X) { + tile_x = key.draw_x % (512 / key.cpp); + tile_y = key.draw_y % 8; + tile_base = ((key.draw_y / 8) * (8 * pitch)); + tile_base += (key.draw_x - tile_x) / (512 / key.cpp) * 4096; + } else { + /* Y */ + tile_x = key.draw_x % (128 / key.cpp); + tile_y = key.draw_y % 32; + tile_base = ((key.draw_y / 32) * (32 * pitch)); + tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096; } + assert(BRW_IS_G4X(brw) || (tile_x == 0 && tile_y == 0)); + assert(tile_x % 4 == 0); + assert(tile_y % 2 == 0); + /* Note that the low bits of these fields are missing, so + * there's the possibility of getting in trouble. + */ + surf.ss1.base_addr = tile_base; + surf.ss5.x_offset = tile_x / 4; + surf.ss5.y_offset = tile_y / 2; } if (region_bo != NULL) surf.ss1.base_addr += region_bo->offset; /* reloc */ -- cgit v1.2.3 From f6c2d1f94ffa8f87b22ed1ff5c465d0e9aa1489e Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Mon, 4 Jan 2010 19:53:28 -0700 Subject: mesa: make texture BorderColor a union of float/int/uint When we have integer-valued texture formats, the texture border color must also store integer and uint values. With GL 3.0, the new glTexParameterIiv() and glTexParameterIuiv() functions can set the border color to int or uint values. --- src/mesa/drivers/dri/gamma/gamma_tex.c | 4 +-- src/mesa/drivers/dri/i810/i810tex.c | 4 +-- src/mesa/drivers/dri/i915/i830_texstate.c | 8 ++--- src/mesa/drivers/dri/i915/i915_texstate.c | 8 ++--- src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 10 +++---- src/mesa/drivers/dri/mach64/mach64_tex.c | 4 +-- src/mesa/drivers/dri/mga/mgatex.c | 4 +-- src/mesa/drivers/dri/r128/r128_tex.c | 4 +-- src/mesa/drivers/dri/r200/r200_tex.c | 4 +-- src/mesa/drivers/dri/r300/r300_tex.c | 4 +-- src/mesa/drivers/dri/r600/r600_tex.c | 4 +-- src/mesa/drivers/dri/radeon/radeon_tex.c | 4 +-- src/mesa/drivers/dri/savage/savagetex.c | 4 +-- src/mesa/drivers/dri/sis/sis_texstate.c | 8 ++--- src/mesa/drivers/dri/unichrome/via_state.c | 16 +++++----- src/mesa/main/attrib.c | 2 +- src/mesa/main/mtypes.h | 6 +++- src/mesa/main/texobj.c | 8 ++--- src/mesa/main/texparam.c | 21 ++++++------- src/mesa/state_tracker/st_atom_sampler.c | 2 +- src/mesa/swrast/s_texfilter.c | 38 ++++++++++++------------ 21 files changed, 84 insertions(+), 83 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/gamma/gamma_tex.c b/src/mesa/drivers/dri/gamma/gamma_tex.c index 0dad250e4d..694e5eba5b 100644 --- a/src/mesa/drivers/dri/gamma/gamma_tex.c +++ b/src/mesa/drivers/dri/gamma/gamma_tex.c @@ -145,7 +145,7 @@ static void gammaTexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - gammaSetTexBorderColor( gmesa, t, tObj->BorderColor ); + gammaSetTexBorderColor( gmesa, t, tObj->BorderColor.f ); break; case GL_TEXTURE_BASE_LEVEL: @@ -349,7 +349,7 @@ static void gammaBindTexture( GLcontext *ctx, GLenum target, gammaSetTexWrapping( t, tObj->WrapS, tObj->WrapT ); gammaSetTexFilter( gmesa, t, tObj->MinFilter, tObj->MagFilter, bias ); - gammaSetTexBorderColor( gmesa, t, tObj->BorderColor ); + gammaSetTexBorderColor( gmesa, t, tObj->BorderColor.f ); } } diff --git a/src/mesa/drivers/dri/i810/i810tex.c b/src/mesa/drivers/dri/i810/i810tex.c index 2f6978f5aa..e764644a6c 100644 --- a/src/mesa/drivers/dri/i810/i810tex.c +++ b/src/mesa/drivers/dri/i810/i810tex.c @@ -210,7 +210,7 @@ i810AllocTexObj( GLcontext *ctx, struct gl_texture_object *texObj ) i810SetTexWrapping( t, texObj->WrapS, texObj->WrapT ); /*i830SetTexMaxAnisotropy( t, texObj->MaxAnisotropy );*/ i810SetTexFilter( imesa, t, texObj->MinFilter, texObj->MagFilter, bias ); - i810SetTexBorderColor( t, texObj->BorderColor ); + i810SetTexBorderColor( t, texObj->BorderColor.f ); } return t; @@ -251,7 +251,7 @@ static void i810TexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - i810SetTexBorderColor( t, tObj->BorderColor ); + i810SetTexBorderColor( t, tObj->BorderColor.f ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 27c5aa1e08..7525f9f2e0 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -304,10 +304,10 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) } /* convert border color from float to ubyte */ - CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]); - CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]); - CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]); - CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]); + CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]); + CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]); + CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]); + CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]); state[I830_TEXREG_TM0S4] = PACK_COLOR_8888(border[3], border[0], diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index db71c00941..3ee4c8653a 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -348,10 +348,10 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) } /* convert border color from float to ubyte */ - CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor[0]); - CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor[1]); - CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor[2]); - CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor[3]); + CLAMPED_FLOAT_TO_UBYTE(border[0], tObj->BorderColor.f[0]); + CLAMPED_FLOAT_TO_UBYTE(border[1], tObj->BorderColor.f[1]); + CLAMPED_FLOAT_TO_UBYTE(border[2], tObj->BorderColor.f[2]); + CLAMPED_FLOAT_TO_UBYTE(border[3], tObj->BorderColor.f[3]); if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) { /* GL specs that border color for depth textures is taken from the diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index aa2e519588..ad267a4e6a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -262,10 +262,10 @@ brw_wm_sampler_populate_key(struct brw_context *brw, dri_bo_unreference(brw->wm.sdc_bo[unit]); if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) { float bordercolor[4] = { - texObj->BorderColor[0], - texObj->BorderColor[0], - texObj->BorderColor[0], - texObj->BorderColor[0] + texObj->BorderColor.f[0], + texObj->BorderColor.f[0], + texObj->BorderColor.f[0], + texObj->BorderColor.f[0] }; /* GL specs that border color for depth textures is taken from the * R channel, while the hardware uses A. Spam R into all the @@ -274,7 +274,7 @@ brw_wm_sampler_populate_key(struct brw_context *brw, brw->wm.sdc_bo[unit] = upload_default_color(brw, bordercolor); } else { brw->wm.sdc_bo[unit] = upload_default_color(brw, - texObj->BorderColor); + texObj->BorderColor.f); } key->sampler_count = unit + 1; } diff --git a/src/mesa/drivers/dri/mach64/mach64_tex.c b/src/mesa/drivers/dri/mach64/mach64_tex.c index 72917ee13b..6627d3c38a 100644 --- a/src/mesa/drivers/dri/mach64/mach64_tex.c +++ b/src/mesa/drivers/dri/mach64/mach64_tex.c @@ -130,7 +130,7 @@ mach64AllocTexObj( struct gl_texture_object *texObj ) mach64SetTexWrap( t, texObj->WrapS, texObj->WrapT ); mach64SetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - mach64SetTexBorderColor( t, texObj->BorderColor ); + mach64SetTexBorderColor( t, texObj->BorderColor.f ); return t; } @@ -470,7 +470,7 @@ static void mach64DDTexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_BORDER_COLOR: if ( t->base.bound ) FLUSH_BATCH( mmesa ); - mach64SetTexBorderColor( t, tObj->BorderColor ); + mach64SetTexBorderColor( t, tObj->BorderColor.f ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/mga/mgatex.c b/src/mesa/drivers/dri/mga/mgatex.c index 9163371b33..62a9317cd4 100644 --- a/src/mesa/drivers/dri/mga/mgatex.c +++ b/src/mesa/drivers/dri/mga/mgatex.c @@ -332,7 +332,7 @@ mgaAllocTexObj( struct gl_texture_object *tObj ) mgaSetTexWrapping( t, tObj->WrapS, tObj->WrapT ); mgaSetTexFilter( t, tObj->MinFilter, tObj->MagFilter ); - mgaSetTexBorderColor( t, tObj->BorderColor ); + mgaSetTexBorderColor( t, tObj->BorderColor.f ); } return( t ); @@ -461,7 +461,7 @@ mgaTexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_BORDER_COLOR: FLUSH_BATCH(mmesa); - mgaSetTexBorderColor(t, tObj->BorderColor); + mgaSetTexBorderColor(t, tObj->BorderColor.f); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/r128/r128_tex.c b/src/mesa/drivers/dri/r128/r128_tex.c index 0a1207fb89..f1be7cc1c4 100644 --- a/src/mesa/drivers/dri/r128/r128_tex.c +++ b/src/mesa/drivers/dri/r128/r128_tex.c @@ -169,7 +169,7 @@ static r128TexObjPtr r128AllocTexObj( struct gl_texture_object *texObj ) r128SetTexWrap( t, texObj->WrapS, texObj->WrapT ); r128SetTexFilter( t, texObj->MinFilter, texObj->MagFilter ); - r128SetTexBorderColor( t, texObj->BorderColor ); + r128SetTexBorderColor( t, texObj->BorderColor.f ); } return t; @@ -535,7 +535,7 @@ static void r128TexParameter( GLcontext *ctx, GLenum target, case GL_TEXTURE_BORDER_COLOR: if ( t->base.bound ) FLUSH_BATCH( rmesa ); - r128SetTexBorderColor( t, tObj->BorderColor ); + r128SetTexBorderColor( t, tObj->BorderColor.f ); break; case GL_TEXTURE_BASE_LEVEL: diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c index a417721553..5b87ba6ccd 100644 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ b/src/mesa/drivers/dri/r200/r200_tex.c @@ -378,7 +378,7 @@ static void r200TexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - r200SetTexBorderColor( t, texObj->BorderColor ); + r200SetTexBorderColor( t, texObj->BorderColor.f ); break; case GL_TEXTURE_BASE_LEVEL: @@ -470,7 +470,7 @@ static struct gl_texture_object *r200NewTextureObject(GLcontext * ctx, r200SetTexWrap( t, t->base.WrapS, t->base.WrapT, t->base.WrapR ); r200SetTexMaxAnisotropy( t, t->base.MaxAnisotropy ); r200SetTexFilter(t, t->base.MinFilter, t->base.MagFilter); - r200SetTexBorderColor(t, t->base.BorderColor); + r200SetTexBorderColor(t, t->base.BorderColor.f); return &t->base; } diff --git a/src/mesa/drivers/dri/r300/r300_tex.c b/src/mesa/drivers/dri/r300/r300_tex.c index ac3d5b1bec..963f648cb1 100644 --- a/src/mesa/drivers/dri/r300/r300_tex.c +++ b/src/mesa/drivers/dri/r300/r300_tex.c @@ -215,7 +215,7 @@ static void r300TexParameter(GLcontext * ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - r300SetTexBorderColor(t, texObj->BorderColor); + r300SetTexBorderColor(t, texObj->BorderColor.f); break; case GL_TEXTURE_BASE_LEVEL: @@ -307,7 +307,7 @@ static struct gl_texture_object *r300NewTextureObject(GLcontext * ctx, /* Initialize hardware state */ r300UpdateTexWrap(t); r300SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy); - r300SetTexBorderColor(t, t->base.BorderColor); + r300SetTexBorderColor(t, t->base.BorderColor.f); return &t->base; } diff --git a/src/mesa/drivers/dri/r600/r600_tex.c b/src/mesa/drivers/dri/r600/r600_tex.c index 9d83a64e22..f745fe3e8a 100644 --- a/src/mesa/drivers/dri/r600/r600_tex.c +++ b/src/mesa/drivers/dri/r600/r600_tex.c @@ -305,7 +305,7 @@ static void r600TexParameter(GLcontext * ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - r600SetTexBorderColor(t, texObj->BorderColor); + r600SetTexBorderColor(t, texObj->BorderColor.f); break; case GL_TEXTURE_BASE_LEVEL: @@ -391,7 +391,7 @@ static struct gl_texture_object *r600NewTextureObject(GLcontext * ctx, r600SetTexDefaultState(t); r600UpdateTexWrap(t); r600SetTexFilter(t, t->base.MinFilter, t->base.MagFilter, t->base.MaxAnisotropy); - r600SetTexBorderColor(t, t->base.BorderColor); + r600SetTexBorderColor(t, t->base.BorderColor.f); return &t->base; } diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c index 749ab75f20..14163f13af 100644 --- a/src/mesa/drivers/dri/radeon/radeon_tex.c +++ b/src/mesa/drivers/dri/radeon/radeon_tex.c @@ -341,7 +341,7 @@ static void radeonTexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - radeonSetTexBorderColor( t, texObj->BorderColor ); + radeonSetTexBorderColor( t, texObj->BorderColor.f ); break; case GL_TEXTURE_BASE_LEVEL: @@ -428,7 +428,7 @@ radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target ) radeonSetTexWrap( t, t->base.WrapS, t->base.WrapT ); radeonSetTexMaxAnisotropy( t, t->base.MaxAnisotropy ); radeonSetTexFilter( t, t->base.MinFilter, t->base.MagFilter ); - radeonSetTexBorderColor( t, t->base.BorderColor ); + radeonSetTexBorderColor( t, t->base.BorderColor.f ); return &t->base; } diff --git a/src/mesa/drivers/dri/savage/savagetex.c b/src/mesa/drivers/dri/savage/savagetex.c index 6c97bb6c70..97598f599e 100644 --- a/src/mesa/drivers/dri/savage/savagetex.c +++ b/src/mesa/drivers/dri/savage/savagetex.c @@ -507,7 +507,7 @@ savageAllocTexObj( struct gl_texture_object *texObj ) savageSetTexWrapping(t,texObj->WrapS,texObj->WrapT); savageSetTexFilter(t,texObj->MinFilter,texObj->MagFilter); - savageSetTexBorderColor(t,texObj->BorderColor); + savageSetTexBorderColor(t,texObj->BorderColor.f); } return t; @@ -2044,7 +2044,7 @@ static void savageTexParameter( GLcontext *ctx, GLenum target, break; case GL_TEXTURE_BORDER_COLOR: - savageSetTexBorderColor(t,tObj->BorderColor); + savageSetTexBorderColor(t,tObj->BorderColor.f); break; default: diff --git a/src/mesa/drivers/dri/sis/sis_texstate.c b/src/mesa/drivers/dri/sis/sis_texstate.c index a507173b21..4c22a10cf7 100644 --- a/src/mesa/drivers/dri/sis/sis_texstate.c +++ b/src/mesa/drivers/dri/sis/sis_texstate.c @@ -457,10 +457,10 @@ sis_set_texobj_parm( GLcontext *ctx, struct gl_texture_object *texObj, { GLubyte c[4]; - CLAMPED_FLOAT_TO_UBYTE(c[0], texObj->BorderColor[0]); - CLAMPED_FLOAT_TO_UBYTE(c[1], texObj->BorderColor[1]); - CLAMPED_FLOAT_TO_UBYTE(c[2], texObj->BorderColor[2]); - CLAMPED_FLOAT_TO_UBYTE(c[3], texObj->BorderColor[3]); + CLAMPED_FLOAT_TO_UBYTE(c[0], texObj->BorderColor.f[0]); + CLAMPED_FLOAT_TO_UBYTE(c[1], texObj->BorderColor.f[1]); + CLAMPED_FLOAT_TO_UBYTE(c[2], texObj->BorderColor.f[2]); + CLAMPED_FLOAT_TO_UBYTE(c[3], texObj->BorderColor.f[3]); current->texture[hw_unit].hwTextureBorderColor = PACK_COLOR_8888(c[3], c[0], c[1], c[2]); diff --git a/src/mesa/drivers/dri/unichrome/via_state.c b/src/mesa/drivers/dri/unichrome/via_state.c index a9db6c45f7..1698230952 100644 --- a/src/mesa/drivers/dri/unichrome/via_state.c +++ b/src/mesa/drivers/dri/unichrome/via_state.c @@ -891,10 +891,10 @@ static GLboolean viaChooseTextureState(GLcontext *ctx) if (texObj->Image[0][texObj->BaseLevel]->Border > 0) { vmesa->regHTXnTB[0] |= (HC_HTXnTB_TBC_S | HC_HTXnTB_TBC_T); vmesa->regHTXnTBC[0] = - PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->BorderColor[0]), - FLOAT_TO_UBYTE(texObj->BorderColor[1]), - FLOAT_TO_UBYTE(texObj->BorderColor[2])); - vmesa->regHTXnTRAH[0] = FLOAT_TO_UBYTE(texObj->BorderColor[3]); + PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->BorderColor.f[0]), + FLOAT_TO_UBYTE(texObj->BorderColor.f[1]), + FLOAT_TO_UBYTE(texObj->BorderColor.f[2])); + vmesa->regHTXnTRAH[0] = FLOAT_TO_UBYTE(texObj->BorderColor.f[3]); } if (texUnit0->LodBias != 0.0f) { @@ -924,10 +924,10 @@ static GLboolean viaChooseTextureState(GLcontext *ctx) if (texObj->Image[0][texObj->BaseLevel]->Border > 0) { vmesa->regHTXnTB[1] |= (HC_HTXnTB_TBC_S | HC_HTXnTB_TBC_T); vmesa->regHTXnTBC[1] = - PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->BorderColor[0]), - FLOAT_TO_UBYTE(texObj->BorderColor[1]), - FLOAT_TO_UBYTE(texObj->BorderColor[2])); - vmesa->regHTXnTRAH[1] = FLOAT_TO_UBYTE(texObj->BorderColor[3]); + PACK_COLOR_888(FLOAT_TO_UBYTE(texObj->BorderColor.f[0]), + FLOAT_TO_UBYTE(texObj->BorderColor.f[1]), + FLOAT_TO_UBYTE(texObj->BorderColor.f[2])); + vmesa->regHTXnTRAH[1] = FLOAT_TO_UBYTE(texObj->BorderColor.f[3]); } diff --git a/src/mesa/main/attrib.c b/src/mesa/main/attrib.c index fb15a5ba47..0641b98b3b 100644 --- a/src/mesa/main/attrib.c +++ b/src/mesa/main/attrib.c @@ -835,7 +835,7 @@ pop_texture_group(GLcontext *ctx, struct texture_state *texstate) _mesa_BindTexture(target, obj->Name); - _mesa_TexParameterfv(target, GL_TEXTURE_BORDER_COLOR, obj->BorderColor); + _mesa_TexParameterfv(target, GL_TEXTURE_BORDER_COLOR, obj->BorderColor.f); _mesa_TexParameterf(target, GL_TEXTURE_PRIORITY, obj->Priority); _mesa_TexParameteri(target, GL_TEXTURE_WRAP_S, obj->WrapS); _mesa_TexParameteri(target, GL_TEXTURE_WRAP_T, obj->WrapT); diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index a7f70a1875..01ad246504 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -1217,7 +1217,11 @@ struct gl_texture_object GLuint Name; /**< the user-visible texture object ID */ GLenum Target; /**< GL_TEXTURE_1D, GL_TEXTURE_2D, etc. */ GLfloat Priority; /**< in [0,1] */ - GLfloat BorderColor[4]; /**< unclamped */ + union { + GLfloat f[4]; + GLuint ui[4]; + GLint i[4]; + } BorderColor; /**< Interpreted according to texture format */ GLenum WrapS; /**< S-axis texture image wrap mode */ GLenum WrapT; /**< T-axis texture image wrap mode */ GLenum WrapR; /**< R-axis texture image wrap mode */ diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c index 09fe7b85ba..7f0a246025 100644 --- a/src/mesa/main/texobj.c +++ b/src/mesa/main/texobj.c @@ -228,10 +228,10 @@ _mesa_copy_texture_object( struct gl_texture_object *dest, dest->Target = src->Target; dest->Name = src->Name; dest->Priority = src->Priority; - dest->BorderColor[0] = src->BorderColor[0]; - dest->BorderColor[1] = src->BorderColor[1]; - dest->BorderColor[2] = src->BorderColor[2]; - dest->BorderColor[3] = src->BorderColor[3]; + dest->BorderColor.f[0] = src->BorderColor.f[0]; + dest->BorderColor.f[1] = src->BorderColor.f[1]; + dest->BorderColor.f[2] = src->BorderColor.f[2]; + dest->BorderColor.f[3] = src->BorderColor.f[3]; dest->WrapS = src->WrapS; dest->WrapT = src->WrapT; dest->WrapR = src->WrapR; diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c index 73db7d713c..474b950def 100644 --- a/src/mesa/main/texparam.c +++ b/src/mesa/main/texparam.c @@ -511,10 +511,7 @@ set_tex_parameterf(GLcontext *ctx, case GL_TEXTURE_BORDER_COLOR: flush(ctx, texObj); - texObj->BorderColor[RCOMP] = params[0]; - texObj->BorderColor[GCOMP] = params[1]; - texObj->BorderColor[BCOMP] = params[2]; - texObj->BorderColor[ACOMP] = params[3]; + COPY_4V(texObj->BorderColor.f, params); return GL_TRUE; default: @@ -1008,10 +1005,10 @@ _mesa_GetTexParameterfv( GLenum target, GLenum pname, GLfloat *params ) *params = ENUM_TO_FLOAT(obj->WrapR); break; case GL_TEXTURE_BORDER_COLOR: - params[0] = CLAMP(obj->BorderColor[0], 0.0F, 1.0F); - params[1] = CLAMP(obj->BorderColor[1], 0.0F, 1.0F); - params[2] = CLAMP(obj->BorderColor[2], 0.0F, 1.0F); - params[3] = CLAMP(obj->BorderColor[3], 0.0F, 1.0F); + params[0] = CLAMP(obj->BorderColor.f[0], 0.0F, 1.0F); + params[1] = CLAMP(obj->BorderColor.f[1], 0.0F, 1.0F); + params[2] = CLAMP(obj->BorderColor.f[2], 0.0F, 1.0F); + params[3] = CLAMP(obj->BorderColor.f[3], 0.0F, 1.0F); break; case GL_TEXTURE_RESIDENT: { @@ -1166,10 +1163,10 @@ _mesa_GetTexParameteriv( GLenum target, GLenum pname, GLint *params ) case GL_TEXTURE_BORDER_COLOR: { GLfloat b[4]; - b[0] = CLAMP(obj->BorderColor[0], 0.0F, 1.0F); - b[1] = CLAMP(obj->BorderColor[1], 0.0F, 1.0F); - b[2] = CLAMP(obj->BorderColor[2], 0.0F, 1.0F); - b[3] = CLAMP(obj->BorderColor[3], 0.0F, 1.0F); + b[0] = CLAMP(obj->BorderColor.f[0], 0.0F, 1.0F); + b[1] = CLAMP(obj->BorderColor.f[1], 0.0F, 1.0F); + b[2] = CLAMP(obj->BorderColor.f[2], 0.0F, 1.0F); + b[3] = CLAMP(obj->BorderColor.f[3], 0.0F, 1.0F); params[0] = FLOAT_TO_INT(b[0]); params[1] = FLOAT_TO_INT(b[1]); params[2] = FLOAT_TO_INT(b[2]); diff --git a/src/mesa/state_tracker/st_atom_sampler.c b/src/mesa/state_tracker/st_atom_sampler.c index d6e3a3e561..e1d6fa9eca 100644 --- a/src/mesa/state_tracker/st_atom_sampler.c +++ b/src/mesa/state_tracker/st_atom_sampler.c @@ -208,7 +208,7 @@ update_samplers(struct st_context *st) assert(sampler->min_lod <= sampler->max_lod); } - xlate_border_color(texobj->BorderColor, + xlate_border_color(texobj->BorderColor.f, teximg ? teximg->_BaseFormat : GL_RGBA, sampler->border_color); diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c index 0bb988e3ef..76b65cc755 100644 --- a/src/mesa/swrast/s_texfilter.c +++ b/src/mesa/swrast/s_texfilter.c @@ -747,28 +747,28 @@ get_border_color(const struct gl_texture_object *tObj, { switch (img->_BaseFormat) { case GL_RGB: - rgba[0] = tObj->BorderColor[0]; - rgba[1] = tObj->BorderColor[1]; - rgba[2] = tObj->BorderColor[2]; + rgba[0] = tObj->BorderColor.f[0]; + rgba[1] = tObj->BorderColor.f[1]; + rgba[2] = tObj->BorderColor.f[2]; rgba[3] = 1.0F; break; case GL_ALPHA: rgba[0] = rgba[1] = rgba[2] = 0.0; - rgba[3] = tObj->BorderColor[3]; + rgba[3] = tObj->BorderColor.f[3]; break; case GL_LUMINANCE: - rgba[0] = rgba[1] = rgba[2] = tObj->BorderColor[0]; + rgba[0] = rgba[1] = rgba[2] = tObj->BorderColor.f[0]; rgba[3] = 1.0; break; case GL_LUMINANCE_ALPHA: - rgba[0] = rgba[1] = rgba[2] = tObj->BorderColor[0]; - rgba[3] = tObj->BorderColor[3]; + rgba[0] = rgba[1] = rgba[2] = tObj->BorderColor.f[0]; + rgba[3] = tObj->BorderColor.f[3]; break; case GL_INTENSITY: - rgba[0] = rgba[1] = rgba[2] = rgba[3] = tObj->BorderColor[0]; + rgba[0] = rgba[1] = rgba[2] = rgba[3] = tObj->BorderColor.f[0]; break; default: - COPY_4V(rgba, tObj->BorderColor); + COPY_4V(rgba, tObj->BorderColor.f); } } @@ -2331,7 +2331,7 @@ sample_2d_array_linear(GLcontext *ctx, array = clamp_rect_coord_nearest(tObj->WrapR, texcoord[2], depth); if (array < 0 || array >= depth) { - COPY_4V(rgba, tObj->BorderColor); + COPY_4V(rgba, tObj->BorderColor.f); } else { if (img->Border) { @@ -3002,7 +3002,7 @@ sample_depth_texture( GLcontext *ctx, img->FetchTexelf(img, col, row, slice, &depthSample); } else { - depthSample = tObj->BorderColor[0]; + depthSample = tObj->BorderColor.f[0]; } result = shadow_compare(function, texcoords[i][compare_coord], @@ -3053,21 +3053,21 @@ sample_depth_texture( GLcontext *ctx, } if (slice < 0 || slice >= (GLint) depth) { - depth00 = tObj->BorderColor[0]; - depth01 = tObj->BorderColor[0]; - depth10 = tObj->BorderColor[0]; - depth11 = tObj->BorderColor[0]; + depth00 = tObj->BorderColor.f[0]; + depth01 = tObj->BorderColor.f[0]; + depth10 = tObj->BorderColor.f[0]; + depth11 = tObj->BorderColor.f[0]; } else { /* get four depth samples from the texture */ if (useBorderTexel & (I0BIT | J0BIT)) { - depth00 = tObj->BorderColor[0]; + depth00 = tObj->BorderColor.f[0]; } else { img->FetchTexelf(img, i0, j0, slice, &depth00); } if (useBorderTexel & (I1BIT | J0BIT)) { - depth10 = tObj->BorderColor[0]; + depth10 = tObj->BorderColor.f[0]; } else { img->FetchTexelf(img, i1, j0, slice, &depth10); @@ -3075,13 +3075,13 @@ sample_depth_texture( GLcontext *ctx, if (tObj->Target != GL_TEXTURE_1D_ARRAY_EXT) { if (useBorderTexel & (I0BIT | J1BIT)) { - depth01 = tObj->BorderColor[0]; + depth01 = tObj->BorderColor.f[0]; } else { img->FetchTexelf(img, i0, j1, slice, &depth01); } if (useBorderTexel & (I1BIT | J1BIT)) { - depth11 = tObj->BorderColor[0]; + depth11 = tObj->BorderColor.f[0]; } else { img->FetchTexelf(img, i1, j1, slice, &depth11); -- cgit v1.2.3 From 5a7c2a99a65399a59f54c6a0756c106c1ae048ff Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 5 Jan 2010 11:07:54 -0800 Subject: i965: Fix build after blind merge of mesa 7.7 by Brian. --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 9db434c596..f26cfabb7d 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -511,7 +511,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, unsigned int unit) { - GLcontext *ctx = &brw->intel.ctx; + struct intel_context *intel = &brw->intel;; + GLcontext *ctx = &intel->ctx; dri_bo *region_bo = NULL; struct intel_renderbuffer *irb = intel_renderbuffer(rb); struct intel_region *region = irb ? irb->region : NULL; @@ -622,7 +623,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, tile_base = ((key.draw_y / 32) * (32 * pitch)); tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096; } - assert(BRW_IS_G4X(brw) || (tile_x == 0 && tile_y == 0)); + assert(intel->is_g4x || (tile_x == 0 && tile_y == 0)); assert(tile_x % 4 == 0); assert(tile_y % 2 == 0); /* Note that the low bits of these fields are missing, so -- cgit v1.2.3 From 46f55798269013063d57ae83a8444a64aeb64a51 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 5 Jan 2010 12:01:13 -0800 Subject: intel: Remove leftover symlinks from DRI1 removal. --- src/mesa/drivers/dri/i915/intel_swapbuffers.c | 1 - src/mesa/drivers/dri/i965/intel_swapbuffers.c | 1 - 2 files changed, 2 deletions(-) delete mode 120000 src/mesa/drivers/dri/i915/intel_swapbuffers.c delete mode 120000 src/mesa/drivers/dri/i965/intel_swapbuffers.c (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i915/intel_swapbuffers.c b/src/mesa/drivers/dri/i915/intel_swapbuffers.c deleted file mode 120000 index 148d5215aa..0000000000 --- a/src/mesa/drivers/dri/i915/intel_swapbuffers.c +++ /dev/null @@ -1 +0,0 @@ -../intel/intel_swapbuffers.c \ No newline at end of file diff --git a/src/mesa/drivers/dri/i965/intel_swapbuffers.c b/src/mesa/drivers/dri/i965/intel_swapbuffers.c deleted file mode 120000 index 148d5215aa..0000000000 --- a/src/mesa/drivers/dri/i965/intel_swapbuffers.c +++ /dev/null @@ -1 +0,0 @@ -../intel/intel_swapbuffers.c \ No newline at end of file -- cgit v1.2.3