From 43346fb1fb43f91cb3e90d84b442dc08d6c9550d Mon Sep 17 00:00:00 2001 From: Brian Paul Date: Wed, 2 Jul 2008 09:14:53 -0600 Subject: set ctx->Const.MaxVertexTextureImageUnits = 0 This disallows vertex shader texture sampling. See bugs 16157, 13838. --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 33f1bba085..1c7ad5c9c8 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -125,7 +125,7 @@ GLboolean brwCreateContext( const __GLcontextModes *mesaVis, ctx->Const.MaxTextureUnits = BRW_MAX_TEX_UNIT; ctx->Const.MaxTextureImageUnits = BRW_MAX_TEX_UNIT; ctx->Const.MaxTextureCoordUnits = BRW_MAX_TEX_UNIT; - + ctx->Const.MaxVertexTextureImageUnits = 0; /* no vertex shader textures */ /* Advertise the full hardware capabilities. The new memory * manager should cope much better with overload situations: -- cgit v1.2.3 From 92c075eeb7c330ea420400d1c2bae57356b19f03 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Tue, 8 Jul 2008 14:14:04 +0800 Subject: i965: official name for GM45 chipset --- src/mesa/drivers/dri/i965/brw_clip_line.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_state.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_tri.c | 2 +- src/mesa/drivers/dri/i965/brw_defines.h | 13 +++++++------ src/mesa/drivers/dri/i965/brw_eu_emit.c | 16 ++++++++-------- src/mesa/drivers/dri/i965/brw_misc_state.c | 8 ++++---- src/mesa/drivers/dri/i965/brw_structs.h | 4 ++-- src/mesa/drivers/dri/i965/brw_vs_emit.c | 2 +- src/mesa/drivers/dri/intel/intel_chipset.h | 10 +++++----- src/mesa/drivers/dri/intel/intel_context.c | 4 +++- 10 files changed, 33 insertions(+), 30 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_clip_line.c b/src/mesa/drivers/dri/i965/brw_clip_line.c index 7d51cddfc3..0930e6a573 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_line.c +++ b/src/mesa/drivers/dri/i965/brw_clip_line.c @@ -148,7 +148,7 @@ static void clip_and_emit_line( struct brw_clip_compile *c ) brw_clip_init_clipmask(c); /* -ve rhw workaround */ - if (!BRW_IS_IGD(p->brw)) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index 7cb21f894e..2d0b24c5ca 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -102,7 +102,7 @@ clip_unit_create_from_key(struct brw_context *brw, clip.clip5.api_mode = BRW_CLIP_API_OGL; clip.clip5.clip_mode = key->clip_mode; - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) clip.clip5.negative_w_clip_test = 1; clip.clip6.clipper_viewport_state_ptr = 0; diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c b/src/mesa/drivers/dri/i965/brw_clip_tri.c index f1fc6e1e9d..7c703179fe 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_tri.c +++ b/src/mesa/drivers/dri/i965/brw_clip_tri.c @@ -536,7 +536,7 @@ void brw_emit_tri_clip( struct brw_clip_compile *c ) /* if -ve rhw workaround bit is set, do cliptest */ - if (!BRW_IS_IGD(p->brw)) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw))) { brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ); brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<20)); diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 3aada8cab1..92c058ade8 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -804,7 +804,7 @@ #define CMD_STATE_BASE_ADDRESS 0x6101 #define CMD_STATE_INSN_POINTER 0x6102 #define CMD_PIPELINE_SELECT_965 0x6104 -#define CMD_PIPELINE_SELECT_IGD 0x6904 +#define CMD_PIPELINE_SELECT_GM45 0x6904 #define CMD_PIPELINED_STATE_POINTERS 0x7800 #define CMD_BINDING_TABLE_PTRS 0x7801 @@ -836,7 +836,7 @@ #define CMD_INDEX_BUFFER 0x780a #define CMD_VF_STATISTICS_965 0x780b -#define CMD_VF_STATISTICS_IGD 0x680b +#define CMD_VF_STATISTICS_GM45 0x680b #define CMD_DRAW_RECT 0x7900 #define CMD_BLEND_CONSTANT_COLOR 0x7901 @@ -862,9 +862,10 @@ #include "intel_chipset.h" -#define BRW_IS_IGD(brw) (IS_IGD((brw)->intel.intelScreen->deviceID)) -#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_IGD(brw)) ? CMD_PIPELINE_SELECT_IGD : CMD_PIPELINE_SELECT_965) -#define CMD_VF_STATISTICS(brw) ((BRW_IS_IGD(brw)) ? CMD_VF_STATISTICS_IGD : CMD_VF_STATISTICS_965) -#define URB_SIZES(brw) ((BRW_IS_IGD(brw)) ? 384 : 256) /* 512 bit unit */ +#define BRW_IS_GM45(brw) (IS_GM45_GM((brw)->intel.intelScreen->deviceID)) +#define BRW_IS_G4X(brw) (IS_G4X((brw)->intel.intelScreen->deviceID)) +#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965) +#define CMD_VF_STATISTICS(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965) +#define URB_SIZES(brw) ((BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? 384 : 256) /* 512 bit unit */ #endif diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index fefd30bc7f..6b97f8b170 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -329,14 +329,14 @@ static void brw_set_sampler_message(struct brw_context *brw, { brw_set_src1(insn, brw_imm_d(0)); - if (BRW_IS_IGD(brw)) { - insn->bits3.sampler_igd.binding_table_index = binding_table_index; - insn->bits3.sampler_igd.sampler = sampler; - insn->bits3.sampler_igd.msg_type = msg_type; - insn->bits3.sampler_igd.response_length = response_length; - insn->bits3.sampler_igd.msg_length = msg_length; - insn->bits3.sampler_igd.end_of_thread = eot; - insn->bits3.sampler_igd.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) { + insn->bits3.sampler_gm45_g4x.binding_table_index = binding_table_index; + insn->bits3.sampler_gm45_g4x.sampler = sampler; + insn->bits3.sampler_gm45_g4x.msg_type = msg_type; + insn->bits3.sampler_gm45_g4x.response_length = response_length; + insn->bits3.sampler_gm45_g4x.msg_length = msg_length; + insn->bits3.sampler_gm45_g4x.end_of_thread = eot; + insn->bits3.sampler_gm45_g4x.msg_target = BRW_MESSAGE_TARGET_SAMPLER; } else { insn->bits3.sampler.binding_table_index = binding_table_index; insn->bits3.sampler.sampler = sampler; diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 26ec797b5f..62df2590f3 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -192,7 +192,7 @@ static void emit_depthbuffer(struct brw_context *brw) { struct intel_context *intel = &brw->intel; struct intel_region *region = brw->state.depth_region; - unsigned int len = BRW_IS_IGD(brw) ? sizeof(struct brw_depthbuffer_igd) / 4 : sizeof(struct brw_depthbuffer) / 4; + unsigned int len = (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? sizeof(struct brw_depthbuffer_gm45_g4x) / 4 : sizeof(struct brw_depthbuffer) / 4; if (region == NULL) { BEGIN_BATCH(len, IGNORE_CLIPRECTS); @@ -203,7 +203,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(0); OUT_BATCH(0); - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) OUT_BATCH(0); ADVANCE_BATCH(); @@ -239,7 +239,7 @@ static void emit_depthbuffer(struct brw_context *brw) ((region->height - 1) << 19)); OUT_BATCH(0); - if (BRW_IS_IGD(brw)) + if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) OUT_BATCH(0); ADVANCE_BATCH(); @@ -324,7 +324,7 @@ static void upload_aa_line_parameters(struct brw_context *brw) { struct brw_aa_line_parameters balp; - if (!BRW_IS_IGD(brw)) + if (!(BRW_IS_GM45(brw) || BRW_IS_G4X(brw))) return; /* use legacy aa line coverage computation */ diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h index 1326280e00..ec865c925a 100644 --- a/src/mesa/drivers/dri/i965/brw_structs.h +++ b/src/mesa/drivers/dri/i965/brw_structs.h @@ -175,7 +175,7 @@ struct brw_depthbuffer } dword4; }; -struct brw_depthbuffer_igd +struct brw_depthbuffer_gm45_g4x { union header_union header; @@ -1405,7 +1405,7 @@ struct brw_instruction GLuint msg_target:4; GLuint pad1:3; GLuint end_of_thread:1; - } sampler_igd; + } sampler_gm45_g4x; struct brw_urb_immediate urb; diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 3cac97c71f..7767d1369c 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -867,7 +867,7 @@ static void emit_vertex_write( struct brw_vs_compile *c) * Later, clipping will detect ucp[6] and ensure the primitive is * clipped against all fixed planes. */ - if (!BRW_IS_IGD(p->brw) && !c->key.know_w_is_one) { + if (!(BRW_IS_GM45(p->brw) || BRW_IS_G4X(p->brw)) && !c->key.know_w_is_one) { brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_L, diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 4a5166263a..15b9ef4312 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -53,7 +53,7 @@ #define PCI_CHIP_I965_GM 0x2A02 #define PCI_CHIP_I965_GME 0x2A12 -#define PCI_CHIP_IGD_GM 0x2A42 +#define PCI_CHIP_GM45_GM 0x2A42 #define PCI_CHIP_IGD_E_G 0x2E02 #define PCI_CHIP_Q45_G 0x2E12 @@ -65,13 +65,12 @@ devid == PCI_CHIP_I945_GME || \ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ - devid == PCI_CHIP_IGD_GM) + devid == PCI_CHIP_GM45_GM) -#define IS_IGD_GM(devid) (devid == PCI_CHIP_IGD_GM) +#define IS_GM45_GM(devid) (devid == PCI_CHIP_GM45_GM) #define IS_G4X(devid) (devid == PCI_CHIP_IGD_E_G || \ devid == PCI_CHIP_Q45_G || \ devid == PCI_CHIP_G45_G) -#define IS_IGD(devid) (IS_IGD_GM(devid) || IS_G4X(devid)) #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ devid == PCI_CHIP_E7221_G || \ @@ -90,7 +89,8 @@ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_I946_GZ || \ - IS_IGD(devid)) + IS_GM45_GM(devid) || \ + IS_G4X(devid)) #define IS_9XX(devid) (IS_915(devid) || \ IS_945(devid) || \ diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 671b3f68a3..f8ea6461c9 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -166,7 +166,9 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_I965_GME: chipset = "Intel(R) 965GME/GLE"; break; - case PCI_CHIP_IGD_GM: + case PCI_CHIP_GM45_GM: + chipset = "Mobile Intel® GM45 Express Chipset"; + break; case PCI_CHIP_IGD_E_G: chipset = "Intel(R) Integrated Graphics Device"; break; -- cgit v1.2.3 From b4b7326717d3253656f9702fc04f06f8d210a6aa Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Fri, 18 Jul 2008 17:40:11 +0800 Subject: intel: fix texture border issue. (bug #16697) --- src/mesa/drivers/dri/i965/brw_fallback.c | 5 ++++- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 5 ++++- src/mesa/drivers/dri/intel/intel_tex_image.c | 5 ++++- src/mesa/drivers/dri/intel/intel_tex_validate.c | 5 ++++- 4 files changed, 16 insertions(+), 4 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c index b5cf821a93..8a8fb50cb9 100644 --- a/src/mesa/drivers/dri/i965/brw_fallback.c +++ b/src/mesa/drivers/dri/i965/brw_fallback.c @@ -73,7 +73,10 @@ static GLboolean do_check_fallback(struct brw_context *brw) if (texUnit->_ReallyEnabled) { struct intel_texture_object *intelObj = intel_texture_object(texUnit->_Current); struct gl_texture_image *texImage = intelObj->base.Image[0][intelObj->firstLevel]; - if (texImage->Border) { + if (texImage->Border || + ((texImage->_BaseFormat == GL_DEPTH_COMPONENT) && + ((texImage->TexObject->WrapS == GL_CLAMP_TO_BORDER) || + (texImage->TexObject->WrapT == GL_CLAMP_TO_BORDER)))) { DBG("FALLBACK: texture border\n"); return GL_TRUE; } diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 9205627813..1b645c7262 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -265,7 +265,10 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt, { /* Images with borders are never pulled into mipmap trees. */ - if (image->Border) + if (image->Border || + ((image->_BaseFormat == GL_DEPTH_COMPONENT) && + ((image->TexObject->WrapS == GL_CLAMP_TO_BORDER) || + (image->TexObject->WrapT == GL_CLAMP_TO_BORDER)))) return GL_FALSE; if (image->InternalFormat != mt->internal_format || diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 95ddbd5920..f261034c18 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -75,7 +75,10 @@ guess_and_alloc_mipmap_tree(struct intel_context *intel, DBG("%s\n", __FUNCTION__); - if (intelImage->base.Border) + if (intelImage->base.Border || + ((intelImage->base._BaseFormat == GL_DEPTH_COMPONENT) && + ((intelObj->base.WrapS == GL_CLAMP_TO_BORDER) || + (intelObj->base.WrapT == GL_CLAMP_TO_BORDER)))) return; if (intelImage->level > intelObj->base.BaseLevel && diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index 992c75c519..f56c236e61 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -144,7 +144,10 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) /* Fallback case: */ - if (firstImage->base.Border) { + if (firstImage->base.Border || + ((firstImage->base._BaseFormat == GL_DEPTH_COMPONENT) && + ((tObj->WrapS == GL_CLAMP_TO_BORDER) || + (tObj->WrapT == GL_CLAMP_TO_BORDER)))) { if (intelObj->mt) { intel_miptree_release(intel, &intelObj->mt); } -- cgit v1.2.3 From b993d539a76e7f1446890a85e4b61deec4d4162d Mon Sep 17 00:00:00 2001 From: Pawel Pieczul Date: Mon, 21 Jul 2008 10:57:20 -0700 Subject: 965: Fix color clamping issues --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 7767d1369c..8c7bc98c61 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1160,9 +1160,29 @@ void brw_vs_emit(struct brw_vs_compile *c ) } if (inst->DstReg.File == PROGRAM_OUTPUT - &&inst->DstReg.Index != VERT_RESULT_HPOS - &&c->output_regs[inst->DstReg.Index].used_in_src) - brw_MOV(p, get_dst(c, inst->DstReg), dst); + && inst->DstReg.Index != VERT_RESULT_HPOS + && c->output_regs[inst->DstReg.Index].used_in_src) { + /* Result color clamping. + * + * When destination register is an output register and it's + * primary/secondary front/back color, we have to clamp the result + * to [0,1]. This is done by enabling the saturation bit for the + * last instruction. + * + * We don't use brw_set_saturate() as it modifies + * p->current->header.saturate, which affects all the subsequent + * instructions. Instead, we directly modify the header of the last + * (already stored) instruction. + */ + if (inst->DstReg.File == PROGRAM_OUTPUT) { + if ((inst->DstReg.Index == VERT_RESULT_COL0) || + (inst->DstReg.Index == VERT_RESULT_COL1) || + (inst->DstReg.Index == VERT_RESULT_BFC0) || + (inst->DstReg.Index == VERT_RESULT_BFC1)) { + p->store[p->nr_insn-1].header.saturate = 1; + } + } + } release_tmps(c); } -- cgit v1.2.3 From 117533759fc6ee57f65a48e7115d4f564ed167f4 Mon Sep 17 00:00:00 2001 From: Pawel Pieczul Date: Wed, 23 Jul 2008 15:43:23 -0700 Subject: 965: Fix partially transparent textures in Doom 3 engine games Numbers of destination depth registers corrected (destination stencil register was sent as depth register). --- src/mesa/drivers/dri/i965/brw_wm_emit.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index ba9168b6ef..9b919b9cfe 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -948,15 +948,16 @@ static void emit_fb_write( struct brw_wm_compile *c, GLuint off = c->key.dest_depth_reg % 2; if (off != 0) { - brw_push_insn_state(p); - brw_set_compression_control(p, BRW_COMPRESSION_NONE); - brw_MOV(p, brw_message_reg(nr), arg1[comp]); - /* 2nd half? */ - brw_MOV(p, brw_message_reg(nr+1), offset(arg1[comp],1)); - brw_pop_insn_state(p); + brw_push_insn_state(p); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); + + brw_MOV(p, brw_message_reg(nr), offset(arg1[comp],1)); + /* 2nd half? */ + brw_MOV(p, brw_message_reg(nr+1), arg1[comp+1]); + brw_pop_insn_state(p); } else { - brw_MOV(p, brw_message_reg(nr), arg1[comp]); + brw_MOV(p, brw_message_reg(nr), arg1[comp]); } nr += 2; } -- cgit v1.2.3 From 6118d830a63d1637587671bdfa9810f3e31c24e7 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Thu, 24 Jul 2008 08:39:51 -0700 Subject: Revert "965: Fix color clamping issues" This reverts commit b993d539a76e7f1446890a85e4b61deec4d4162d. The patch was applied incorrectly. Actual fix coming soon. Sorry for the noise. --- src/mesa/drivers/dri/i965/brw_vs_emit.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_vs_emit.c b/src/mesa/drivers/dri/i965/brw_vs_emit.c index 8c7bc98c61..7767d1369c 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_emit.c +++ b/src/mesa/drivers/dri/i965/brw_vs_emit.c @@ -1160,29 +1160,9 @@ void brw_vs_emit(struct brw_vs_compile *c ) } if (inst->DstReg.File == PROGRAM_OUTPUT - && inst->DstReg.Index != VERT_RESULT_HPOS - && c->output_regs[inst->DstReg.Index].used_in_src) { - /* Result color clamping. - * - * When destination register is an output register and it's - * primary/secondary front/back color, we have to clamp the result - * to [0,1]. This is done by enabling the saturation bit for the - * last instruction. - * - * We don't use brw_set_saturate() as it modifies - * p->current->header.saturate, which affects all the subsequent - * instructions. Instead, we directly modify the header of the last - * (already stored) instruction. - */ - if (inst->DstReg.File == PROGRAM_OUTPUT) { - if ((inst->DstReg.Index == VERT_RESULT_COL0) || - (inst->DstReg.Index == VERT_RESULT_COL1) || - (inst->DstReg.Index == VERT_RESULT_BFC0) || - (inst->DstReg.Index == VERT_RESULT_BFC1)) { - p->store[p->nr_insn-1].header.saturate = 1; - } - } - } + &&inst->DstReg.Index != VERT_RESULT_HPOS + &&c->output_regs[inst->DstReg.Index].used_in_src) + brw_MOV(p, get_dst(c, inst->DstReg), dst); release_tmps(c); } -- cgit v1.2.3 From d4244683a61f66cfb78408a37cf2587587847f96 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 25 Jul 2008 19:56:56 +1000 Subject: i965: make tex offset override work.. should fix fd.o 14441 --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 50 +++++++++++++++--------- 1 file changed, 31 insertions(+), 19 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 0d91391964..d7758075d1 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -155,6 +155,7 @@ struct brw_wm_surface_key { GLint width, height, depth; GLint pitch, cpp; GLboolean tiled; + GLuint offset; }; static dri_bo * @@ -173,8 +174,10 @@ brw_create_texture_surface( struct brw_context *brw, /* This is ok for all textures with channel width 8bit or less: */ /* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */ - - surf.ss1.base_addr = key->bo->offset; /* reloc */ + if (key->bo) + surf.ss1.base_addr = key->bo->offset; /* reloc */ + else + surf.ss1.base_addr = key->offset; surf.ss2.mip_count = key->last_level - key->first_level; surf.ss2.width = key->width - 1; @@ -198,17 +201,17 @@ brw_create_texture_surface( struct brw_context *brw, bo = brw_upload_cache(&brw->cache, BRW_SS_SURFACE, key, sizeof(*key), - &key->bo, 1, + &key->bo, key->bo ? 1 : 0, &surf, sizeof(surf), NULL, NULL); - - /* Emit relocation to surface contents */ - dri_emit_reloc(bo, - DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, - 0, - offsetof(struct brw_surface_state, ss1), - key->bo); - + if (key->bo) { + /* Emit relocation to surface contents */ + dri_emit_reloc(bo, + DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ, + 0, + offsetof(struct brw_surface_state, ss1), + key->bo); + } return bo; } @@ -223,26 +226,35 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) int ret = 0; memset(&key, 0, sizeof(key)); + + if (intelObj->imageOverride) { + key.pitch = intelObj->pitchOverride / intelObj->mt->cpp; + key.depth = intelObj->depthOverride; + key.bo = NULL; + key.offset = intelObj->textureOffset; + } else { + key.pitch = intelObj->mt->pitch; + key.depth = firstImage->Depth; + key.bo = intelObj->mt->region->buffer; + key.offset = 0; + ret |= dri_bufmgr_check_aperture_space(key.bo); + } + key.target = tObj->Target; key.depthmode = tObj->DepthMode; key.format = firstImage->TexFormat->MesaFormat; - key.bo = intelObj->mt->region->buffer; key.first_level = intelObj->firstLevel; key.last_level = intelObj->lastLevel; key.width = firstImage->Width; key.height = firstImage->Height; - key.pitch = intelObj->mt->pitch; key.cpp = intelObj->mt->cpp; - key.depth = firstImage->Depth; key.tiled = intelObj->mt->region->tiled; - ret |= dri_bufmgr_check_aperture_space(key.bo); - dri_bo_unreference(brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS]); brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_search_cache(&brw->cache, BRW_SS_SURFACE, - &key, sizeof(key), - &key.bo, 1, - NULL); + &key, sizeof(key), + &key.bo, key.bo ? 1 : 0, + NULL); if (brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] == NULL) { brw->wm.surf_bo[unit + MAX_DRAW_BUFFERS] = brw_create_texture_surface(brw, &key); } -- cgit v1.2.3 From 9bc9e0ecb0fb2069b2c123e665eb2118e358098f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 25 Jul 2008 20:32:22 +1000 Subject: i965: fixup format for TFP zero copy --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'src/mesa/drivers/dri/i965') diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index d7758075d1..2ba3eb4de8 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -169,7 +169,17 @@ brw_create_texture_surface( struct brw_context *brw, surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; surf.ss0.surface_type = translate_tex_target(key->target); - surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode); + + if (key->bo) + surf.ss0.surface_format = translate_tex_format(key->format, key->depthmode); + else { + switch(key->depth) { + case 32: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM; break; + default: + case 24: surf.ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8X8_UNORM; break; + case 16: surf.ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM; break; + } + } /* This is ok for all textures with channel width 8bit or less: */ @@ -233,6 +243,7 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) key.bo = NULL; key.offset = intelObj->textureOffset; } else { + key.format = firstImage->TexFormat->MesaFormat; key.pitch = intelObj->mt->pitch; key.depth = firstImage->Depth; key.bo = intelObj->mt->region->buffer; @@ -242,7 +253,6 @@ brw_update_texture_surface( GLcontext *ctx, GLuint unit ) key.target = tObj->Target; key.depthmode = tObj->DepthMode; - key.format = firstImage->TexFormat->MesaFormat; key.first_level = intelObj->firstLevel; key.last_level = intelObj->lastLevel; key.width = firstImage->Width; -- cgit v1.2.3